AlderLake Board Code: AlderLake Board Package

AlderLake Board Code
AlderLake Board Package

1 - Overview

2 - Board Module

3 - Bios Image

4 - Board Package Structure

5 - Build Introduction

6 - API

7 - Board Package Dependencies

Generated on Wed Jan 5 2022 01:27:52 for AlderLake Board Code by doxygen 1.8.20


AlderLake Board Code: 1 - Overview

  • AlderLake Board Package
1 - Overview

Purpose

The purpose of this document is to describe the external architecture and interfaces provided in the Board Package.

Note
Board Package Code specifications are auto generated via doxygen

Supported Boards

Todo, supported board types

Summary

Todo, project how the BoardPkg is an integration point of silicon and platform IPs..etc


AlderLake Board Code: 2 - Board Module

  • AlderLake Board Package
2 - Board Module

2.1 - ACPI

2.1.1 - Architectural Overview

ACPI ASL code is generally categorized into one of the modules listed below:

  • System Agent ASL Code

    This module contains the ASL files for the System Agent Host Bridge and the bridges/devices inside it. All ASL files for System Agent are included in the System Agent Reference Code package. HOST_BUS.ASL: Defines various Alderlake System Agent PCI Configuration Space registers which will be used to dynamically produce all resources in the Host Bus. SA.ASL: Currently defines the device objects for the PCI Express* Graphics bridge and port, and IGD. INTELGFX.ASL: Defines the methods to enable/disable output switching, store display switching and LCD brightness BIOS control and return valid addresses for all display device encoders present in the system, etc. IgdOpRn.ASL: Defines OperationRegions to cover the IGD PCI configuration space as described in the IGD OpRegion specification. IgdOGBDA.ASL: This file contains Get BIOS Data Area function support for the IGD OpRegion/Software SCI mechanism. IgdOMOBF.ASL: This file contains ASL code for handling the events, i.e. hotkeys and other system interrupts. IgdOSBCB.ASL: This file contains the system BIOS call back functionality for the OpRegion/Software SCI mechanism

  • PCH ASL Code

    This module contains the definitions for the OperationRegions for accesses to the PCH and the methods to use it. All ASL files for the PCH are included in the PCH Reference Code package. PCH.ASL: Defines the OperationRegions for the accesses to the registers inside PCH, and PCH!|s internal devices. PchAudio.ASL: Defines the OperationRegion for the accesses to HDA controller. PchPcie.ASL: Defines the OperationRegion for the accesses to PCI Express Root Bridge registers. PchSmb.ASL: Defines the OperationRegion for the accesses to SMBus PCI Configuration Space and I/O mapped registers, and the methods to execute various SMBus transactions.

  • CPU ASL Code

    This module contains the tables, methods, P-state, C-state and T-state support. These will be dynamically loaded according to OS CPU driver capabilities. All CPU ASL files are included in the CPU Reference Code package. Cpu0Cst.ASL/ApCst.ASL: Defines _CST method for all processors to publish C-State capability. Cpu0Ist.ASL/ApIst.ASL: Defines _PPC, _PCT, _PSS method for all processors to publish P-State capabilities. Cpu0Tst.ASL/ApTst.ASL: Defines _TPC, _PTC, _TSS, _TSD method for all processors to publish T-State capabilities. CpuPm.ASL: Defines the methods to get the information for properly initializing tables and dynamically loading them.

  • Platform ASL Code

    This module contains all platform-related ACPI name spaces and methods. All Platform ASL files are in this Platform Sample package, of which most of the Differentiated System Description Table (DSDT) consists. The following sections will introduce all of ASL files in this package top-to-down in hierarchy. !V DSDT.ASL:This file makes up all components into most of the DSDT, which contains information and descriptions for various system features. Additionally, this file also contains power management packages that defines system _S0, _S1, _S3, _S4 and _S5 state mode. The ASL files listed below are included into this file to compose the whole DSDT.

    • Amlupd.asl
    • PlatformNvs.asl
    • PCItree.asl
    • Platform.asl
    • CPU.asl
    • Thermal.asl
    • PCI_DRC.asl
    • Video.asl
    • Gpe.asl
    • PCIEDOCK.asl
    • Pch.asl: Not in this package. Refer to the PCH Reference Code
    • Sa.asl: Not in this package. Refer to the SA Reference Code
      • Note: _S0 and _S5 are mandatory system states.

Globally-Used Data

  • AmlUpd.ASL: Defines the namespaces for the support of system states.
  • PlatformNvs.ASL: Define a Global region of ACPI NVS Region that may be used for any type of implementation. The starting offset and size will be fixed up by the System BIOS during POST.

PciTree.ASL: This conducts the whole system bus (_SB), starting with PCI Host Bridge Bus hierarchy (_PCI0), incorporating all devices resident in bus 0. This may make references to others ASL files located over other reference code packages, e.g. HOST_BUS.ASL in System Agent Reference Code package. Additionally, this also defines the namespaces for the possible resources (_PRS) for LINKA/B/C/D/E/F/G/H and for routing information (_PRT)

  • Cpu.ASL: The definitions of processor methods for all logical processors under _PR
  • Gpe.ASL: This ASL file contains most of General-Purpose Events methods (_Lxx).
  • LpcB.asl: Defines the OperationRegions for PIRQx Routing Control Registers, I/O Decode Ranges Register, RCBA and Keyboard Controller I/O ports; declares PS/2 keyboard and mouse device. In addition, this drags in the ASL files of the devices resident in LPC bus.
  • EC.ASL: Defines an EC device containing an EC Space and Query Event methods (_Qxx) for handling battery, thermal, docking system, LID, ALS and specific hotkeys; also defines an AC device, a lid switch and power button.
  • Thermal.ASL: Defines two thermal zones: TZ00 and TZ01. The former is for active cooling and the later is for passive cooling. It also defines twoPowerResources: FN00 and FN01, for fan control in active cooling.
  • Super I/O Controllers
    • NAT_COM.ASL/NAT_FDC.ASL/NAT_LPT.ASL/NAT_SIO.ASL: Defines the devices and methods for the National Super I/O controller support.
    • SMSC1000_COM.ASL/SMSC1000_LPT.ASL/SMSC1000_SIO.ASL: Defines the devices and methods for the SMSC1000 Super I/O controller support.
    • SMSC1007_COM.ASL/SMSC1007_SIO.ASL: Defines the devices and methods for the SMSC1007 Super I/O controller support.
    • WPCN381U_COM.asl/WPCN381U_LPT.ASL/WPCN381U_FDC.asl /WPCN381U_SIO.asl: Defines the devices and methods for the Winbond* WPCN381 SuperIO support.
  • PCIEDOCK.ASL: Defines a docking station device with the related control methods, e.g. _EJ0 (a control method that ejects a device; _EJ0 means hot-ejection), _DCK (indicates that this device is a docking station and also controls the isolation logic on the docking connector for docking or undocking), _EDL (returns a packaged list of devices that are dependent on a device.
  • Platform.ASL: Defines some standard methods, e.g. _PIC (for OS to inform the ASL code which interrupt controller is being used, 8259 or APIC), _PTS (Prepare to Sleep, is called when the OS is about to enter a sleep state.), _WAK (is called when the OS is about to wake from sleep state), _INI (is used to determine the OS) and some useful methods for other ASL code!|s use, e.g. P8XH (for port-80 display), GETB (creates then returns a smaller buffer), PNOT (performs all OS-needed notifications during a Power Switch.), TRAP (generates a Mutex protected SMI I/O Trap), NHPG (clears the PCI Express hot-plug SCI enable bits), NPME (clear PCI Express PME SCI enable bits), etc.
  • PCI_DRC.ASL: Defines memory regions for RCRB, MCH BAR, DMI BAR, EP BAR, PCIE BAR Thermal BAR, TTT base address (for TxT), VTD Engine Memory Range, Flash Range, Local APIC Range as Motherboard Resources (PNP0C02). The _BAS, _LEN will be dynamically updated (in _CRS method) to match the real configurations.

ACPI FVI Support

  • This module creates the version information of the ACPI Reference Code, referring to the SMBIOS type 0xDD described in Firmware Version Information (FVI) Interface Specification v0.8

SSDT PTID ASL Code

  • PTID (Power and Temperature Instrumentation) is in an SSDT by design, which is able to dynamically loaded by EFI ACPI Table Protocol.
  • Ptid.ASL: This file contains the code for Thermal Monitoring support for the PTIMon (Power and Temperature Instrumentation Monitor Utility) application to report temperature, power and Fan speed.

Dynamic Platform & Thermal Framework (DPTF)

  • The DPTF reference code is a Framework compliant DXE driver that consists of two main components: 1.DPTF device initialization 2.ACPI SSDT tables It does all the DPTF specific initializations and loads the ACPI tables which provide the AML code to control the various thermal components. DPTF is Intel!|s implementation of the ACPI 5.0 Thermal model. Following are the main features supported by the SSDT tables:
    • Support multiple thermal device components within a single Thermal Zone
    • Device components contain embedded temperature sensors and cooling controls (passive and/or active)
    • Device components expose thermal trip points
    • Device thermal interfaces exposed via device!|s driver The Intel DPTF Thermal Zone has various ACPI objects:
    • Participant device objects like CPU, Memory, Fan and on board sensors (called Generic participant devices)
    • Thermal Objects like PATC, PATx, GTSH, _SCP All these objects are described in detail in the IntelU+00AE Dynamic Platform & Thermal Framework 7.0 BIOS Writer!|s Guide Version.

  • DPTF SSDT The DPTF reference code for Alderlake is loaded in one SSDT by the DXE driver in Dptf.c. All ASL files will be included in Dptf.asl, which is the SSDT file.

    Participants (devices) can be exposed or hidden via the ACPI status method (_STA). Each participant is contained in its own ASL file. The file name format is DeviceParticipant.asl.

    Policies (methods and data structures) can be exposed or hidden by conditionally returning the GUID!|s in the IDSP method. Each policy is contained in its own ASL file. The file name format is DeviceNamePolicy.asl

    Additionally, platforms can be customized by simply removing the unwanted include files from Dptf.asl.

    • Dptf.ASL: The main ASL file with IDSP, _OSC and utility methods. All other files are included here. Customer can remove features here.
    • Art.ASL: Active cooling table for customer modification.
    • Ertm.ASL: Participant list for customer modification.
    • Trt.ASL: Thermal relationship table for customer modification.
    • Dppm.ASL: Guids for Active, Passive, Critical and Cooling mode policies.
    • B0D4Participant.ASL: System agent device.
    • B0D4CtdpPolicy.ASL: CTDP policy.
    • B0D4LpmPolicy.ASL: LPM policy.
    • B0D4DppmPolicy.ASL: DPPM policy.
    • TcpuParticipant.ASL: CPU device for ATOM. This will not be used if B0D4 device is used.
    • TcpuDppmPolicy.ASL: DPPM policy.
    • TpchParticipant.ASL: PCH device.
    • TpchDppmPolicy.ASL: DPPM policy.
    • TAmbParticipant.ASL: Ambient sensor device.
    • TAmbDppmPolicy.ASL: DPPM policy.
    • TEfnParticipant.ASL: Exhaust fan device.
    • TEfnDppmPolicy.ASL: DPPM policy.
    • TFN1Participant.ASL: Fan 1 device.
    • TFN2Participant.ASL: Fan 2 device.
    • TMemParticipant.ASL: Memory device.
    • TMemDppmPolicy.ASL: DPPM policy.
    • TSknParticipant.ASL: Skin temperature sensor.
    • TSknDppmPolicy.ASL: DPPM policy.
    • T_VRParticipant.ASL: Voltage regulator temperature sensor.
    • T_VRDppmPolicy.ASL: DPPM policy.

Miscellaneous ASL Code

2.1.2 - Rationale

The Platform Sample code was designed with the ease of customization and integration as a primary goal. Organizing code in individual functional directories and consolidating all the chipset code in a chipset module were the approaches adopted to achieve this.

2.1.3 - Requirements

  • Framework compliant
    • ASL code build with iASL.exe vesion 20180209
    • Build with EDKII code base with specific module revision
    • Compliant to the UEFI 2.1 specification (where appropriate)
    • Compliant to the Framework 0.9x specifications
    • Compliant to VS2015 compiler
  • Easily portable to different Framework-compliant code bases utilizing the EDK
  • Easily portable to different platforms
  • Able to support Client platforms (Mobile and Desktop) with the same code

2.1.4 - API

  • 4.1 ACPI Info Protocol

    _ACPI_INFO_PROTOCOL

    Note
    This is an Output from reference Code

  • 4.2 ACPI Platform Policy Protocol

    _ACPI_PLATFORM_POLICY_PROTOCOL

2.1.5 - Build Flags

The following build flags are used for enabling or disabling features/Configurations.

  • MDEPKG_NDEBUG TRUE
  • EFI_S3_RESUME TRUE

2.1.6 - MiscInfo

2.2 - SerialIo I2C Devices

Steps for changing SerialIoDevice location (I2C or SPI Bus) & adding new location (I2C or SPI Bus) for SerialIoDevice & adding new type of I2C or SPI device.

Introduction of Main Files

FILE | DESCRIPTION
AlderLakeXBoardConfigPatchTable.h | "X" is depend on Board SKU. Switch all Variables of PchSetup.hfr from each Platform Table.
SerialIoDevices.asl | Init All SerialIo Bus it owned Bus number and Bitmap from "PchSetup.hfr".

This is Current 8 Bits Map of I2C Devices for combinedly use in "AlderLakeXBoardConfigPatchTable.h"

I2C DEVICES | BIT0 ~ BIT7
SERIAL_IO_I2C_TOUCHPAD | 0x01
SERIAL_IO_I2C_TOUCHPANEL | 0x02
SERIAL_IO_I2C_UCMC | 0x04
4th_SERIAL_IO_I2C_DEVICE_NONE | 0x08
5th_SERIAL_IO_I2C_DEVICE_NONE | 0x10
6th_SERIAL_IO_I2C_DEVICE_NONE | 0x20
7th_SERIAL_IO_I2C_DEVICE_NONE | 0x40
8th_SERIAL_IO_I2C_DEVICE_NONE | 0x80

This is Current 8 Bits Map of SPI Devices for combinedly use in "AlderLakeXBoardConfigPatchTable.h"

SPI DEVICES | BIT0 ~ BIT7
SERIAL_IO_SPI_FINGERPRINT | 0x01
2nd_SERIAL_IO_SPI_DEVICE_NONE | 0x02
3rd_SERIAL_IO_SPI_DEVICE_NONE | 0x04
4th_SERIAL_IO_SPI_DEVICE_NONE | 0x08
5th_SERIAL_IO_SPI_DEVICE_NONE | 0x10
6th_SERIAL_IO_SPI_DEVICE_NONE | 0x20
7th_SERIAL_IO_SPI_DEVICE_NONE | 0x40
8th_SERIAL_IO_SPI_DEVICE_NONE | 0x80

Examples for Reference

01. Steps for changing SerialIoDevice location (I2C or SPI Bus)

Ex : Platform BoardIdTglX's Bus I2C4 supported Touch Pad and Touch Panel at same time, and PchI2cTouchPadIrqMode set to GPIO mode.

AlderLakeBoardPkg\AlderLakeXBoards\Include\AlderLakeXBoardConfigPatchTable.h

_// BoardIdTglX 0x99 \
{ SIZE_OF_FIELD (SETUP_DATA, PchI2cSensorDevicePort[ SERIAL_IO_I2C4 ]), OFFSET_OF (SETUP_DATA, PchI2cSensorDevicePort[SERIAL_IO_I2C4]),(SERIAL_IO_I2C_TOUCHPAD | SERIAL_IO_I2C_TOUCHPANEL) },
{ SIZE_OF_FIELD (SETUP_DATA, PchI2cTouchPadIrqMode), OFFSET_OF (SETUP_DATA, PchI2cTouchPadIrqMode), 0}

02. Steps for adding new location (I2C or SPI Bus) for SerialIoDevice**

Ex : Create new Bus as I2C6, it must be store related info under the Scope of Bus.

AlderLakeBoardPkg\Acpi\AcpiTables\Dsdt\SerialIoDevices.asl

#define SERIAL_IO_I2C6 0x6 // New Define in"SetupVariable.h" & "SerialIoDevices.asl"
Scope(\_SB.PC00.I2C6) {
Store (SDS6, I2CN)
Store (SERIAL_IO_I2C6, I2CX)
...}

03. Steps for adding new type of I2C or SPI device**

Ex : Add new SPI Device as EyesPrint which is Bit2 in SPI_2 BUS Bitmap, Link to related page and variable and page.

Please check DoxygenPlat.chm for the detail of Step 03.


AlderLake Board Code: 3 - Bios Image

  • AlderLake Board Package
3 - Bios Image

Todo, the contents of each FVs need to fill up.

0. Flash Layout

NVRAM | IBB | Protect
FV Advanced (Signed2048Sha256) | Post IBB FV witch will be authenticated by core | Region protect by PCH Flash protection Range Registers FPRR and BIOS Guard SFAM
FV Security | Boot Guard IBB
FV OsBoot (Signed2048Sha256) | Post IBB FV witch will be authenticated by core
FV UefiBoot (Signed2048Sha256)
FV PostMemory (Signed2048Sha256)
FV Microcode |  |
FV FspS (Only for FSP wrapper build) | Boot Guard IBB | Region protect by PCH Flash protection Range Registers FPRR and BIOS Guard SFAM
FV PreMemory
Note
# BootGuard IBB = FvPreMemory + FvFSP + FvSecurity. To maintain the chain of trust, FvPostMemory + FvAdvanced + FvUefiBoot + FvOsBoot firmware volumes need to be signed and authenticated during UEFI Bios boot.

1. FvAdvanced - Todo

Driver Name(.inf) | Build Condition
Sample.inf | gSiPkgTokenSpaceGuid.Sample == TRUE

2. FvSecurity - Todo

Driver Name(.inf) | Build Condition
Sample.inf | gSiPkgTokenSpaceGuid.Sample == TRUE

3. FvOsBoot - Todo

Driver Name(.inf) | Build Condition
Sample.inf | gPlatformModuleTokenSpaceGuid.Sample == TRUE

4. FvUefiBoot - Todo

Driver Name(.inf) | Build Condition
Sample.inf | gSiPkgTokenSpaceGuid.Sample == TRUE && gPlatformModuleTokenSpaceGuid.Sample2 == FALSE

5. FvPostMemory - Todo

Driver Name(.inf) | Build Condition
Sample.inf | gPlatformModuleTokenSpaceGuid.Sample == TRUE && gPlatformModuleTokenSpaceGuid.Sample2 == TRUE

6. FvFSPs - FSP-S binary

7. FvPreMemory - Todo

Driver Name(.inf) | Build Condition
Sample.inf | gPlatformModuleTokenSpaceGuid.Sample == TRUE && gPlatformModuleTokenSpaceGuid.Sample2 == TRUE


AlderLake Board Code: 4 - Board Package Structure

  • AlderLake Board Package
4 - Board Package Structure

Todo, provide the tree structure of board


AlderLake Board Code: 5 - Build Introduction

  • AlderLake Board Package
5 - Build Introduction

Todo, details of different builds supported. Below information is copied from DoxygenPlat with the adjustment for BoardPkg.

When building SiPkg with RoyalPark and BoardPkg please follow below steps:

  1. Restrieve RoyalPark, AlderLakeBoardPkg and all required binary/tool files (Microcode and GOP...). Or you may exclude those binary files in FDF file if not required.

    PCDs consumed by DSC and FDF for optional feature

    PCDs consumed by DSC and FDF for Optional Feature (with default setting) DESCRIPTION

    PCDs consumed by DSC or FDF for bin files

    PCDs consumed by DSC or FDF for BIN files (with default setting) | DESCRIPTION
    gBoardModuleTokenSpaceGuid.PcdStartupAcmBinEnable|TRUE | #StartupAcm.bin
    gBoardModuleTokenSpaceGuid.PcdReservedFitBinEnable|TRUE | #ReservedFIT.bin

    PCDs consumed by DSC or FDF for efi files

    PCDs consumed by DSC or FDF for EFI files (with default setting) | DESCRIPTION
    gBoardModuleTokenSpaceGuid.PcdMebxEfiEnable|TRUE | #Mebx.efi
    gBoardModuleTokenSpaceGuid.PcdMebxSetupBrowserEnable|TRUE | #MebxSetupBrowser.efi
    gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE | #IntelGopDriver.efi
    gBoardModuleTokenSpaceGuid.PcdRaidDriverEfiEnable|TRUE | #RaidDriver.efi
    gBoardModuleTokenSpaceGuid.PcdRsteDriverEfiEnable|TRUE | #SataDriverRste.efi

    Summary the paths of all Binary as below, depends on platform design some of them may not be required:

    • AlderLakeBoardPkg\Binaries\BiosGuard\BiosGuardModule.bin
    • AlderLakeBoardPkg\Binaries\BiosGuard\BiosGuardModuleSim.bin
    • AlderLakeBoardPkg\Binaries\BootGuard\ACM\StartupAcm.bin
    • AlderLakeBoardPkg\Binaries\Microcode\*.*
    • AlderLakeBoardPkg\Binaries\UefiDriver\Gop\*.*
    • AlderLakeBoardPkg\Binaries\UefiDriver\Mebx\*.*
    • AlderLakeBoardPkg\Binaries\UefiDriver\MebxSetupBrowser\*.*
    • AlderLakeBoardPkg\Binaries\UefiDriver\Raid\*.*
      Note
      If FitGen is not required, please remove the lines in AlderLakeBoardPkg\postbuild.bat where FitGen called.
  2. Generate Rsa2048Sha256 Private, public PEM key pair and name the file as privkey.pem and pubkey.pem accordingly. Also generate SHA256 hash of public key and include this as RAW file in Firmware volume.
  3. Retrieve ClientOneSiliconPkg (for Source code building).
  4. All AlderLakeBoardPkg, AlderLakePlatSamplePkg, ClientOneSiliconPkg should be in root of RoyalPark source.
  5. For building with SiPkg source code, go to AlderLakeBoardPkg and type "prep && bld" to compile the whole source code.

  6. The Full BIOS binary (Descriptor/ME FW + BIOS ROM) generated may not boot on the system as the build steps do not cover all of the strap settings. Please get working Descriptor/ME FW and combine with BIOS.ROM generated by this build to be a full Binary to boot the system.

    Note
    BootGuard: BootGuard ACM authenticates IBB which includes FvPreMemory + FvFSP + FvSecurity (only in FSP wrapper build). With this consideration, it is mandated to Sign FvPostMemory + FvAdvanced + FvUefiBoot + FvOsBoot. SignedSection driver authenticates all signed FVs before launching it and the chain of trust will be maintained. Based on the IBB size, BootGuard ACM with release BIOS works on 2MB LLC silicon and BootGuard ACM with both Release/Debug Bioses work on 4MB LLC silicon. This is not a recommendation and 2MB LLC silicon can boot with Debug BIOS too, if the IBB size meets the requirement. Refer to BootGuard BIOS writers guide for more details.


AlderLake Board Code: 6 - API

  • AlderLake Board Package
6 - API

Todo, list of APIs produced, consumed, implemented etc.


AlderLake Board Code: 7 - Board Package Dependencies

  • AlderLake Board Package
7 - Board Package Dependencies

Todo


AlderLake Board Code: File List

File List
Here is a list of all documented files with brief descriptions:
AcpiByteStream.h | Byte stream structures for ACPI
AcpiCommon.h | Header file for ACPI common Initialization Driver
AcpiGnvsInit.c | Acpi Gnvs Init Library
AcpiPlatform.c | Advanced ACPI Driver
AcpiPlatform.h | This is an implementation of the Advanced ACPI driver
AdvancedPmaxDxe.c | Advanced PMAX table install and update driver
BoardAcpiDxe.c | Board ACPI Driver
Ecdt.h | This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT)
Facs.h | This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS)
Fadt6.3.h | This file describes the contents of the ACPI Fixed ACPI Description Table (FADT)
GenSsdtLib.c | ACPI SSDT table generation library
GenSsdtLib.h | This is an implementation of the ACPI platform driver
Hpet.h | This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET)
Madt.h | This file describes the contents of the ACPI Multiple APIC Description Table (MADT)
Mcfg.h | This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG)
MofSampleDev.h |
MofTestDev.h |
UpdateDsdt.c | ACPI Update DSDT Library


AlderLake Board Code: AcpiByteStream.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
AcpiByteStream.h File Reference

Byte stream structures for ACPI. More...

#include <IndustryStandard/Acpi.h>
Include dependency graph for AcpiByteStream.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Byte stream structures for ACPI.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiByteStream.h.


AlderLake Board Code: AcpiCommon.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Include
AcpiCommon.h File Reference

Header file for ACPI common Initialization Driver. More...

Go to the source code of this file.

Detailed Description

Header file for ACPI common Initialization Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiCommon.h.


AlderLake Board Code: AcpiGnvsInit.c File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • BoardAcpiDxe
Functions
AcpiGnvsInit.c File Reference

Acpi Gnvs Init Library. More...

#include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/PlatformNvsArea.h>
#include <Protocol/MpService.h>
Include dependency graph for AcpiGnvsInit.c:

Go to the source code of this file.

Functions

EFI_STATUS AcpiGnvsInit (IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize. More...

Detailed Description

Acpi Gnvs Init Library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiGnvsInit.c.

Function Documentation

◆ AcpiGnvsInit()

EFI_STATUS AcpiGnvsInit ( IN OUT VOID ** PlatformNvsAreaPtr )

Global NVS initialize.

Parameters
[in] PlatformNvsAreaPtr - Pointer of global NVS area
Return values
EFI_SUCCESS | - Allocate Global NVS completed.
EFI_OUT_OF_RESOURCES | - Failed to allocate required page for GNVS.

Definition at line 56 of file AcpiGnvsInit.c.


AlderLake Board Code: AcpiPlatform.c File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
Functions
AcpiPlatform.c File Reference

Advanced ACPI Driver. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/HobLib.h>
#include <Guid/HobList.h>
#include <Protocol/FirmwareVolume2.h>
#include <PlatformBoardId.h>
#include <IndustryStandard/AcpiAml.h>
#include <IndustryStandard/Pci30.h>
#include "AcpiPlatform.h"
#include <Library/PciSegmentLib.h>
#include <Library/PchInfoLib.h>
#include <Library/PchPcieRpLib.h>
#include <Library/SerialIoAccessLib.h>
#include <Library/GpioLib.h>
#include <Library/EspiLib.h>
#include <Library/GbeLib.h>
#include <Library/PchPciBdfLib.h>
#include <MeBiosPayloadHob.h>
#include <PlatformBoardConfig.h>
#include <Library/CpuPlatformLib.h>
#include <PlatformBoardType.h>
#include <PlatformInfo.h>
#include <Guid/S3MemoryVariable.h>
#include <Protocol/VariableLock.h>
#include <Mcfg.h>
#include <Usb4PlatformHob.h>
#include <Library/IpuLib.h>
#include <Library/GnaInfoLib.h>
#include <Library/VmdInfoLib.h>
#include <Library/SataLib.h>
#include <Library/SataSocLib.h>
#include <Library/GraphicsInfoLib.h>
#include "GenSsdtLib.h"
Include dependency graph for AcpiPlatform.c:

Go to the source code of this file.

Functions

VOID STATIC | InstallSocAcpiTable (IN EFI_GUID *SsdtTableGuid, IN UINT64 Signature)
Install Soc ACPI Table. More...
VOID | InstallXhciAcpiTable (VOID)
Install Xhci ACPI Table.
EFI_STATUS | LocateSupportProtocol (IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol. More...
UINT32 | GetEcGpeNumber (VOID)
This function will provide the EC GPE number for ECDT update according to platform design. More...
EFI_STATUS | PlatformUpdateTables (IN OUT EFI_ACPI_COMMON_HEADER *Table, IN OUT EFI_ACPI_TABLE_VERSION *Version)
This function will update any runtime platform specific information. More...
VOID | IsHardwareChange (VOID)
This function calculates RCR based on PCI Device ID and Vendor ID from the devices available on the platform. More...
EFI_STATUS | AllocateMemoryBelow4G (IN EFI_MEMORY_TYPE MemoryType, IN UINTN Size, OUT VOID **Buffer)
Allocate MemoryType below 4G memory address. More...
EFI_STATUS | GuidStringToAcpiBuffer (IN CHAR16 *GuidString, OUT UINT64 *AcpiGuidPart1, OUT UINT64 *AcpiGuidPart2)
Convert string containing GUID in the canonical form: "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp" where aa - pp are unicode hexadecimal digits to the buffer format to be used in ACPI, byte ordering: [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7] [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16]. More...
EFI_STATUS | SetAcpiSetupVariables (VOID)
Save Acpi Setup relatived variables. More...
EFI_STATUS | InstallAcpiPlatform (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
ACPI Platform driver installation function. More...
EFI_STATUS | SortCpuLocalApicInTable (IN EFI_MP_SERVICES_PROTOCOL *MpService)
Sort ordering of CPUs according to the priorities of cores and threads. More...
EFI_STATUS | WaitInputEmpty (IN UINTN Timeout)
I/O work flow to wait input buffer empty in given time. More...
EFI_STATUS | WaitOutputFull (IN UINTN Timeout)
I/O work flow to wait output buffer full in given time. More...
EFI_STATUS | In8042AuxData (IN OUT UINT8 *Data)
I/O work flow of in 8042 Aux data. More...
EFI_STATUS | Out8042AuxCommand (IN UINT8 Command)
I/O work flow of outing 8042 Aux command. More...
EFI_STATUS | PS2MouseEnable (VOID)
Issue command to enable Ps2 mouse. More...
BOOLEAN | IsPs2MouseConnected (VOID)
Check whether there is Ps/2 mouse device in system. More...

Detailed Description

Advanced ACPI Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiPlatform.c.

Function Documentation

◆ AllocateMemoryBelow4G()

EFI_STATUS AllocateMemoryBelow4G | ( | IN EFI_MEMORY_TYPE | MemoryType,
 |  | IN UINTN | Size,
 |  | OUT VOID ** | Buffer
 | ) |  |

Allocate MemoryType below 4G memory address.

Parameters
[in] | Size | - Size of memory to allocate.
[in] | Buffer | - Allocated address for output.
Return values
EFI_SUCCESS | - Memory successfully allocated.
Other | - Other errors occur.

Definition at line 2334 of file AcpiPlatform.c.

◆ GetEcGpeNumber()

UINT32 GetEcGpeNumber ( VOID )

This function will provide the EC GPE number for ECDT update according to platform design.

Return values
EcGpeNumber EC GPE number to be reported in ECDT

Definition at line 580 of file AcpiPlatform.c.

◆ GuidStringToAcpiBuffer()

EFI_STATUS GuidStringToAcpiBuffer | ( | IN CHAR16 * | GuidString,
 |  | OUT UINT64 * | AcpiGuidPart1,
 |  | OUT UINT64 * | AcpiGuidPart2
 | ) |  |

Convert string containing GUID in the canonical form: "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp" where aa - pp are unicode hexadecimal digits to the buffer format to be used in ACPI, byte ordering: [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7] [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16].

Parameters
[in] | GuidString | - GUID String null terminated (aligned on a 16-bit boundary)
[out] | AcpiGuidPart1 | - First half of buffer (bytes 0 - 7)
[out] | AcpiGuidPart2 | - Second half of buffer (bytes 8 - 16)
Return values
EFI_SUCCESS | - String converted successfully.
EFI_UNSUPPORTED | - Wrong input string format.

Definition at line 2504 of file AcpiPlatform.c.

◆ In8042AuxData()

EFI_STATUS In8042AuxData ( IN OUT UINT8 * Data )

I/O work flow of in 8042 Aux data.

Parameters
Data Buffer holding return value.
Return values
EFI_SUCCESS | Success to excute I/O work flow
EFI_TIMEOUT | Keyboard controller time out.

Definition at line 5259 of file AcpiPlatform.c.

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◆ InstallAcpiPlatform()

EFI_STATUS InstallAcpiPlatform | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

ACPI Platform driver installation function.

Entry point of the ACPI platform driver.

Parameters
[in] | ImageHandle | Handle for this drivers loaded image protocol.
[in] | SystemTable | EFI system table.
Return values
EFI_SUCCESS | The driver installed without error.
EFI_ABORTED | The driver encountered an error and could not complete installation of the ACPI tables.

PMAX Configuration

Get TcssHob HOB

Definition at line 2625 of file AcpiPlatform.c.

◆ InstallSocAcpiTable()

VOID STATIC InstallSocAcpiTable | ( | IN EFI_GUID * | SsdtTableGuid,
 |  | IN UINT64 | Signature
 | ) |  |

Install Soc ACPI Table.

Parameters
[in] | *SsdtTableGuid | Pointer to GUID that identifies new SSDT table
[in] | Signature | Signature of the table

Definition at line 102 of file AcpiPlatform.c.

◆ IsHardwareChange()

VOID IsHardwareChange ( VOID )

This function calculates RCR based on PCI Device ID and Vendor ID from the devices available on the platform.

It also includes other instances of BIOS change to calculate CRC and provides as HWSignature filed in FADT table.

Definition at line 2127 of file AcpiPlatform.c.

◆ IsPs2MouseConnected()

BOOLEAN IsPs2MouseConnected ( VOID )

Check whether there is Ps/2 mouse device in system.

Return values
TRUE | - Keyboard in System.
FALSE | - Keyboard not in System.

Definition at line 5374 of file AcpiPlatform.c.

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◆ LocateSupportProtocol()

EFI_STATUS LocateSupportProtocol | ( | IN EFI_GUID * | Protocol,
 |  | IN EFI_GUID | gEfiAcpiMultiTableStorageGuid,
 |  | OUT VOID ** | Instance,
 |  | IN BOOLEAN | Type
 | ) |  |

Locate the first instance of a protocol.

If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table storage file.

Parameters
[in] | Protocol | The protocol to find.
[in] | Instance | Return pointer to the first instance of the protocol.
[in] | Type | TRUE if the desired protocol is a FV protocol.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The protocol could not be located.
EFI_OUT_OF_RESOURCES | There are not enough resources to find the protocol.

Definition at line 451 of file AcpiPlatform.c.

◆ Out8042AuxCommand()

EFI_STATUS Out8042AuxCommand ( IN UINT8 Command )

I/O work flow of outing 8042 Aux command.

Parameters
Command Aux I/O command
Return values
EFI_SUCCESS | Success to excute I/O work flow
EFI_TIMEOUT | Keyboard controller time out.

Definition at line 5287 of file AcpiPlatform.c.

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◆ PlatformUpdateTables()

EFI_STATUS PlatformUpdateTables | ( | IN OUT EFI_ACPI_COMMON_HEADER * | Table,
 |  | IN OUT EFI_ACPI_TABLE_VERSION * | Version
 | ) |  |

This function will update any runtime platform specific information.

This currently includes: Setting OEM table values, ID, table ID, creator ID and creator revision. Enabling the proper processor entries in the APIC tables It also indicates with which ACPI table version the table belongs.

Parameters
[in] | Table | The table to update
[in] | Version | Where to install this table
Return values
EFI_SUCCESS Updated tables commplete.

Definition at line 616 of file AcpiPlatform.c.

◆ PS2MouseEnable()

EFI_STATUS PS2MouseEnable ( VOID )

Issue command to enable Ps2 mouse.

Returns
Status of command issuing.

Definition at line 5356 of file AcpiPlatform.c.

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◆ SetAcpiSetupVariables()

EFI_STATUS SetAcpiSetupVariables ( VOID )

Save Acpi Setup relatived variables.

Locate table with matching ID

Definition at line 2561 of file AcpiPlatform.c.

◆ SortCpuLocalApicInTable()

EFI_STATUS SortCpuLocalApicInTable ( IN EFI_MP_SERVICES_PROTOCOL * MpService )

Sort ordering of CPUs according to the priorities of cores and threads.

ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core

Parameters
[in] MpService The MP servicde protocol (used to retrievel MP info)
Return values
EFI_SUCCESS The driver installed without error.

Definition at line 4986 of file AcpiPlatform.c.

◆ WaitInputEmpty()

EFI_STATUS WaitInputEmpty ( IN UINTN Timeout )

I/O work flow to wait input buffer empty in given time.

Parameters
[in] Timeout Wating time.
Return values
EFI_TIMEOUT | if input is still not empty in given time.
EFI_SUCCESS | input is empty.

Definition at line 5178 of file AcpiPlatform.c.

◆ WaitOutputFull()

EFI_STATUS WaitOutputFull ( IN UINTN Timeout )

I/O work flow to wait output buffer full in given time.

Parameters
[in] Timeout given time
Return values
EFI_TIMEOUT | output is not full in given time
EFI_SUCCESS | output is full in given time.

Definition at line 5219 of file AcpiPlatform.c.


AlderLake Board Code: AcpiPlatform.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
Functions
AcpiPlatform.h File Reference

This is an implementation of the Advanced ACPI driver. More...

#include <IndustryStandard/Acpi.h>
#include <Guid/EventGroup.h>
#include <Guid/GlobalVariable.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/LocalApicLib.h>
#include <Protocol/CpuIo2.h>
#include <Protocol/AcpiTable.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/MpService.h>
#include <Register/Cpuid.h>
#include <Protocol/PciIo.h>
#include <Library/PchCycleDecodingLib.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
#include <Library/DxeAcpiGnvsInitLib.h>
#include <Register/PchRegs.h>
#include <Register/SaRegsHostBridge.h>
#include <Protocol/PlatformNvsArea.h>
#include <Platform.h>
#include <Library/AslUpdateLib.h>
#include <SetupVariable.h>
#include <Library/EcMiscLib.h>
#include <Acpi/AcpiTables/Fadt/Fadt6.3.h>
Include dependency graph for AcpiPlatform.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | LocateSupportProtocol (IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol. More...
EFI_STATUS | InstallAcpiPlatform (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point of the ACPI platform driver. More...
EFI_STATUS | SortCpuLocalApicInTable (IN EFI_MP_SERVICES_PROTOCOL *MpService)
Sort ordering of CPUs according to the priorities of cores and threads. More...
BOOLEAN | IsPs2MouseConnected (VOID)
Check whether there is Ps/2 mouse device in system. More...

Detailed Description

This is an implementation of the Advanced ACPI driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiPlatform.h.

Function Documentation

◆ InstallAcpiPlatform()

EFI_STATUS InstallAcpiPlatform | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Entry point of the ACPI platform driver.

Parameters
[in] | ImageHandle | A handle for the image that is initializing this driver
[in] | SystemTable | A pointer to the EFI system table
Return values
EFI_SUCCESS | The driver installed without error.
EFI_ABORTED | The driver encountered an error and could not complete installation of the ACPI tables.

Entry point of the ACPI platform driver.

Parameters
[in] | ImageHandle | Handle for this drivers loaded image protocol.
[in] | SystemTable | EFI system table.
Return values
EFI_SUCCESS | The driver installed without error.
EFI_ABORTED | The driver encountered an error and could not complete installation of the ACPI tables.

PMAX Configuration

Get TcssHob HOB

Definition at line 2625 of file AcpiPlatform.c.

◆ IsPs2MouseConnected()

BOOLEAN IsPs2MouseConnected ( VOID )

Check whether there is Ps/2 mouse device in system.

Return values
TRUE | - Keyboard in System.
FALSE | - Keyboard not in System.

Definition at line 5374 of file AcpiPlatform.c.

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◆ LocateSupportProtocol()

EFI_STATUS LocateSupportProtocol | ( | IN EFI_GUID * | Protocol,
 |  | IN EFI_GUID | gEfiAcpiMultiTableStorageGuid,
 |  | OUT VOID ** | Instance,
 |  | IN BOOLEAN | Type
 | ) |  |

Locate the first instance of a protocol.

If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table storage file.

Parameters
[in] | Protocol | The protocol to find.
[in] | Instance | Return pointer to the first instance of the protocol.
[in] | Type | TRUE if the desired protocol is a FV protocol.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The protocol could not be located.
EFI_OUT_OF_RESOURCES | There are not enough resources to find the protocol.

Definition at line 451 of file AcpiPlatform.c.

◆ SortCpuLocalApicInTable()

EFI_STATUS SortCpuLocalApicInTable ( IN EFI_MP_SERVICES_PROTOCOL * MpService )

Sort ordering of CPUs according to the priorities of cores and threads.

ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core

Parameters
[in] MpService The MP servicde protocol (used to retrievel MP info)
Return values
EFI_SUCCESS The driver installed without error.

Definition at line 4986 of file AcpiPlatform.c.


AlderLake Board Code: AdvancedPmaxDxe.c File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
Functions
AdvancedPmaxDxe.c File Reference

Advanced PMAX table install and update driver. More...

#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/FirmwareVolume2.h>
#include <IndustryStandard/AcpiAml.h>
#include <Library/AslUpdateLib.h>
#include <Library/PcdLib.h>
#include <PlatformBoardConfig.h>
#include <PmaxDevDef.h>
Include dependency graph for AdvancedPmaxDxe.c:

Go to the source code of this file.

Functions

UINTN | GetStrLength (IN CHAR8 *StrPtr)
Calculate the string length, will include NULL-terminated. More...
EFI_STATUS | InstallTable (IN EFI_ACPI_DESCRIPTION_HEADER *Table)
Install the PMAX table. More...
EFI_STATUS | UpdatePmaxTable (IN OUT EFI_ACPI_DESCRIPTION_HEADER *PmaxTable)
Get PCD and update the values. More...
EFI_STATUS | FindPmaxTable (OUT EFI_ACPI_DESCRIPTION_HEADER **PmaxTable)
Find PMAX SSDT Table. More...
EFI_STATUS | InstallPmaxTable (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
PMAX table installation driver. More...

Detailed Description

Advanced PMAX table install and update driver.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Definition in file AdvancedPmaxDxe.c.

Function Documentation

◆ FindPmaxTable()

EFI_STATUS FindPmaxTable ( OUT EFI_ACPI_DESCRIPTION_HEADER ** PmaxTable )

Find PMAX SSDT Table.

Parameters
[out] PmaxTable Point to PMAX table.
Return values
EFI_SUCCESS | Find PMAX table successfully.
Other | The function encountered an error and could not complete process.

Definition at line 240 of file AdvancedPmaxDxe.c.

◆ GetStrLength()

UINTN GetStrLength ( IN CHAR8 * StrPtr )

Calculate the string length, will include NULL-terminated.

Parameters
[in] StrPtr Point to the string.
Return values
String length.

Definition at line 54 of file AdvancedPmaxDxe.c.

◆ InstallPmaxTable()

EFI_STATUS InstallPmaxTable | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

PMAX table installation driver.

Parameters
[in] | ImageHandle | Handle for this drivers loaded image protocol.
[in] | SystemTable | EFI system table.
Return values
EFI_SUCCESS | The driver installed without error.
Other | The driver encountered an error and could not complete installation of the ACPI tables.

Definition at line 363 of file AdvancedPmaxDxe.c.

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◆ InstallTable()

EFI_STATUS InstallTable ( IN EFI_ACPI_DESCRIPTION_HEADER * Table )

Install the PMAX table.

Parameters
[in] Table Point to PMAX table..
Return values
EFI_SUCCESS | Install table success.
Other | The function encountered an error and could not complete process.

Definition at line 75 of file AdvancedPmaxDxe.c.

◆ UpdatePmaxTable()

EFI_STATUS UpdatePmaxTable ( IN OUT EFI_ACPI_DESCRIPTION_HEADER * PmaxTable )

Get PCD and update the values.

Parameters
[in,out] PmaxTable Point to PMAX table.
Return values
EFI_SUCCESS | The function completed successfully.
Other | The function encountered an error and could not complete process.

Definition at line 111 of file AdvancedPmaxDxe.c.

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AlderLake Board Code: BoardAcpiDxe.c File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • BoardAcpiDxe
Functions
BoardAcpiDxe.c File Reference

Board ACPI Driver. More...

#include <Base.h>
#include <Uefi.h>
#include <IndustryStandard/Acpi.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/PciLib.h>
#include <Library/BoardAcpiTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/AslUpdateLib.h>
#include <Protocol/PlatformNvsArea.h>
#include <Protocol/FirmwareVolume2.h>
#include <Protocol/AcpiTable.h>
Include dependency graph for BoardAcpiDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS | AcpiGnvsInit (IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize. More...
EFI_STATUS | LocateSupportProtocol (IN EFI_GUID *Protocol, IN EFI_GUID *gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol. More...
EFI_STATUS | InstallAcpiBoard (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
ACPI Platform driver installation function. More...

Detailed Description

Board ACPI Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BoardAcpiDxe.c.

Function Documentation

◆ AcpiGnvsInit()

EFI_STATUS AcpiGnvsInit ( IN OUT VOID ** PlatformNvsAreaPtr )

Global NVS initialize.

Parameters
[in] PlatformNvsAreaPtr - Pointer of global NVS area
Return values
EFI_SUCCESS | - Allocate Global NVS completed.
EFI_OUT_OF_RESOURCES | - Failed to allocate required page for GNVS.

Definition at line 56 of file AcpiGnvsInit.c.

◆ InstallAcpiBoard()

EFI_STATUS InstallAcpiBoard | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

ACPI Platform driver installation function.

Parameters
[in] | ImageHandle | Handle for this drivers loaded image protocol.
[in] | SystemTable | EFI system table.
Return values
EFI_SUCCESS | The driver installed without error.
EFI_ABORTED | The driver encountered an error and could not complete installation of the ACPI tables.

Definition at line 298 of file BoardAcpiDxe.c.

Here is the call graph for this function:

◆ LocateSupportProtocol()

EFI_STATUS LocateSupportProtocol | ( | IN EFI_GUID * | Protocol,
 |  | IN EFI_GUID * | gEfiAcpiMultiTableStorageGuid,
 |  | OUT VOID ** | Instance,
 |  | IN BOOLEAN | Type
 | ) |  |

Locate the first instance of a protocol.

If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table storage file.

Parameters
[in] | Protocol | The protocol to find.
[in] | Instance | Return pointer to the first instance of the protocol.
[in] | Type | TRUE if the desired protocol is a FV protocol.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The protocol could not be located.
EFI_OUT_OF_RESOURCES | There are not enough resources to find the protocol.

Definition at line 94 of file BoardAcpiDxe.c.


AlderLake Board Code: Ecdt.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Ecdt
Ecdt.h File Reference

This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT). More...

#include <IndustryStandard/Acpi.h>
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Detailed Description

This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT).

All changes to the ECDT contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Ecdt.h.


AlderLake Board Code: Facs.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Facs
Facs.h File Reference

This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS). More...

#include <IndustryStandard/Acpi.h>
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Detailed Description

This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS).

All changes to the FACS contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Facs.h.


AlderLake Board Code: Fadt6.3.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Fadt
Fadt6.3.h File Reference

This file describes the contents of the ACPI Fixed ACPI Description Table (FADT). More...

#include <IndustryStandard/Acpi.h>
#include "Register/PmcRegs.h"
#include "Register/TcoRegs.h"
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Detailed Description

This file describes the contents of the ACPI Fixed ACPI Description Table (FADT).

All changes to the FADT contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 2020-2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Fadt6.3.h.


AlderLake Board Code: GenSsdtLib.c File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
Functions
GenSsdtLib.c File Reference

ACPI SSDT table generation library. More...

#include "AcpiByteStream.h"
#include <Base.h>
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/HobLib.h>
#include <Guid/HobList.h>
#include <Library/UefiBootServicesTableLib.h>
#include <IndustryStandard/Acpi.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Protocol/AcpiTable.h>
#include <Protocol/AcpiSystemDescriptionTable.h>
#include <Library/MemoryAllocationLib.h>
Include dependency graph for GenSsdtLib.c:

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Functions

EFI_STATUS GenerateSsdtFromConfigFile (VOID)
Generate SSDTs from ACPI data available in BIOS board files or ACPI data generated from PCT tool FVs.

Detailed Description

ACPI SSDT table generation library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GenSsdtLib.c.


AlderLake Board Code: GenSsdtLib.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
Functions
GenSsdtLib.h File Reference

This is an implementation of the ACPI platform driver. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS GenerateSsdtFromConfigFile (VOID)
Generate SSDTs from ACPI data available in BIOS board files or ACPI data generated from PCT tool FVs.

Detailed Description

This is an implementation of the ACPI platform driver.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GenSsdtLib.h.


AlderLake Board Code: Hpet.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Hpet
Hpet.h File Reference

This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET). More...

#include <IndustryStandard/Acpi30.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
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Detailed Description

This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET).

All changes to the HPET contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Hpet.h.


AlderLake Board Code: Madt.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Madt
Madt.h File Reference

This file describes the contents of the ACPI Multiple APIC Description Table (MADT). More...

#include <IndustryStandard/Acpi.h>
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Detailed Description

This file describes the contents of the ACPI Multiple APIC Description Table (MADT).

To make changes to the MADT, it is necessary to update the count for the APIC structure being updated, and to modify table found in Madt.c.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Madt.h.


AlderLake Board Code: Mcfg.h File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Mcfg
Mcfg.h File Reference

This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG). More...

#include <IndustryStandard/Acpi30.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
Include dependency graph for Mcfg.h:
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Detailed Description

This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG).

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Mcfg.h.


AlderLake Board Code: MofSampleDev.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Dsdt
MofSampleDev.h
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51 0x08, 0xc0, 0xd0, 0xff, 0xff, 0x0c, 0x01, 0x0e, 0x58, 0x7e, 0x86, 0x00, 0xa6, 0xd7, 0x26, 0x58,
52 0xe7, 0x03, 0x5c, 0xd0, 0xe7, 0x81, 0x09, 0x24, 0xf7, 0xb8, 0xa0, 0x68, 0x30, 0x28, 0x0b, 0x27,
53 0x4b, 0x20, 0x8a, 0xec, 0x93, 0x25, 0xe6, 0xf0, 0xe0, 0xd1, 0x82, 0xe3, 0x4e, 0xf0, 0x42, 0xe4,
54 0xc1, 0x7b, 0x90, 0x8f, 0x89, 0x21, 0xa2, 0xbc, 0xb4, 0x19, 0xef, 0x9d, 0xed, 0x90, 0xe2, 0x1c,
55 0xc8, 0x4b, 0x24, 0x0e, 0x2d, 0xd6, 0x11, 0xfb, 0x8e, 0xe0, 0xdb, 0xa4, 0x6f, 0x7e, 0x1c, 0x22,
56 0xc8, 0x83, 0xa1, 0x4f, 0x92, 0xb0, 0xb1, 0x6b, 0xbb, 0x07, 0x68, 0x30, 0x41, 0x1e, 0x20, 0x22,
57 0x04, 0x39, 0x97, 0xa3, 0x0a, 0xf3, 0xf4, 0xf8, 0x2e, 0xe9, 0x89, 0x86, 0xf3, 0x49, 0xd2, 0xff,
58 0x7f, 0x20, 0x1f, 0x20, 0x5e, 0x25, 0x43, 0xb1, 0x4b, 0x45, 0xc8, 0x17, 0xc9, 0x20, 0xaf, 0x94,
59 0xc1, 0x22, 0x07, 0x0b, 0x13, 0xef, 0x49, 0x92, 0x89, 0x7d, 0x31, 0xe8, 0xc0, 0xea, 0x93, 0x24,
60 0xc0, 0x0f, 0x91, 0x27, 0x0a, 0x1d, 0x68, 0x70, 0xa3, 0xf0, 0x81, 0xe1, 0xf5, 0x02, 0x23, 0xea,
61 0x64, 0x41, 0x45, 0x9d, 0x47, 0x50, 0x27, 0x09, 0x1f, 0x22, 0x18, 0x28, 0x3f, 0xbd, 0x61, 0x06,
62 0x06, 0x1f, 0x10, 0xef, 0x7d, 0xca, 0xe4, 0x4e, 0x62, 0x40, 0x16, 0xe2, 0x58, 0x01, 0xfd, 0xff,
63 0x7f, 0xac, 0xe0, 0xd7, 0x87, 0x38, 0x67, 0x71, 0x3e, 0x06, 0x3c, 0x8a, 0xd7, 0x12, 0xcc, 0x20,
64 0xce, 0xc1, 0x77, 0x96, 0x28, 0xc6, 0x78, 0xf2, 0x30, 0x8c, 0x91, 0x0c, 0xea, 0x93, 0x1c, 0x76,
65 0x00, 0xec, 0xfe, 0x6b, 0x88, 0x40, 0xaf, 0x18, 0x7c, 0x6c, 0xec, 0xac, 0x03, 0xbe, 0x93, 0xe7,
66 0xb3, 0x29, 0x98, 0x6e, 0x2e, 0xb8, 0xf3, 0xc4, 0x43, 0x08, 0x1f, 0x9b, 0x07, 0xe5, 0x89, 0xb2,
67 0xe3, 0x08, 0xe6, 0x74, 0x0a, 0x4c, 0xae, 0x48, 0x1e, 0x02, 0x3f, 0x68, 0x78, 0x08, 0x7c, 0x00,
68 0xad, 0xce, 0x92, 0xdc, 0x4e, 0xce, 0x0d, 0x77, 0x52, 0xe0, 0x53, 0xc2, 0x0d, 0x00, 0xa3, 0xd0,
69 0xa6, 0x4f, 0x8d, 0x46, 0xad, 0x1a, 0x94, 0xa9, 0x51, 0xa6, 0x41, 0xad, 0x3e, 0x95, 0x1a, 0x33,
70 0x76, 0x4a, 0xb0, 0xc0, 0x87, 0x85, 0x4e, 0x0e, 0x8e, 0x07, 0x42, 0x23, 0x1d, 0x75, 0x64, 0xe4,
71 0x44, 0x6a, 0x10, 0x01, 0x59, 0xca, 0xe9, 0x55, 0x40, 0x3e, 0xbf, 0x72, 0xc1, 0x26, 0x80, 0x98,
72 0x7c, 0x10, 0x01, 0x93, 0x47, 0x83, 0x40, 0x2c, 0xc8, 0x06, 0x08, 0x13, 0xad, 0x03, 0x84, 0xfd,
73 0xff, 0x01


AlderLake Board Code: MofTestDev.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Dsdt
MofTestDev.h
1 0x46,0x4F,0x4D,0x42,0x01,0x00,0x00,0x00,0xE1,0x02,0x00,0x00,0xC2,0x06,0x00,0x00,
2 0x44,0x53,0x00,0x01,0x1A,0x7D,0xDA,0x54,0xA8,0x5D,0x83,0x00,0x01,0x06,0x18,0x42,
3 0x20,0x14,0x03,0x89,0xC0,0xA2,0x69,0x24,0xC7,0x01,0x0C,0x86,0xCB,0x72,0x20,0xE4,
4 0x82,0x89,0x09,0x10,0x01,0x21,0xAF,0x02,0x6C,0x0A,0x30,0x09,0xA2,0xFE,0xFD,0x21,
5 0x4A,0x82,0x43,0x09,0x81,0x90,0x64,0x01,0xE6,0x05,0xE8,0x16,0x60,0x58,0x80,0x6D,
6 0x01,0xA6,0x05,0x38,0x86,0xA4,0xD2,0xC0,0x29,0x81,0xA5,0x40,0x48,0xB8,0x00,0xE5,
7 0x02,0x7C,0x0B,0xD0,0x8E,0x28,0xDC,0x96,0x61,0x44,0xE0,0x51,0x44,0xB6,0x50,0x34,
8 0x0A,0x8D,0x1D,0x86,0x65,0x82,0x69,0x10,0x87,0x51,0x36,0xB2,0x08,0x3C,0xA1,0x4E,
9 0x05,0xC8,0x15,0x20,0x4C,0x80,0x78,0x54,0x61,0x34,0x07,0x45,0x20,0x43,0x63,0xC4,
10 0x40,0x48,0x22,0xAC,0x9C,0x63,0x6B,0x14,0xA7,0x71,0x34,0xA5,0x63,0x68,0x04,0xC7,
11 0x75,0x40,0x06,0xE9,0x7D,0x3A,0x44,0xD0,0x84,0x34,0x8A,0x68,0x21,0xA2,0x04,0x3D,
12 0x8E,0x20,0x81,0x23,0x24,0x30,0xCC,0x31,0x60,0x64,0x40,0xC8,0xB3,0x00,0xEB,0x83,
13 0x23,0x04,0x76,0x2F,0xC0,0x98,0x00,0x8D,0x10,0x72,0x26,0xC0,0xA0,0x00,0x85,0x02,
14 0xBC,0xC1,0xC8,0x96,0x00,0x6D,0x02,0x94,0x21,0x68,0x4A,0x51,0x0E,0x2A,0x48,0xB8,
15 0x28,0x16,0x87,0x26,0x88,0x16,0x51,0x08,0x68,0x84,0xD6,0x60,0x84,0x1B,0x2E,0x46,
16 0x84,0x93,0x8B,0x1C,0xA2,0xFD,0x41,0x90,0x68,0x47,0x01,0x49,0x00,0x51,0xA4,0xD1,
17 0xA0,0x86,0x9F,0xE0,0x71,0xC0,0x47,0x81,0x93,0x3B,0xA9,0x13,0x33,0xC8,0x89,0x1D,
18 0x5D,0x9D,0xE7,0x00,0x32,0x62,0x86,0x95,0xE0,0xD7,0xC0,0x07,0x03,0xBC,0x6B,0x40,
19 0xDD,0x08,0x9E,0x07,0xD8,0x30,0xC3,0x61,0x86,0xE8,0xD1,0x86,0xFB,0xFF,0x9F,0xC0,
20 0x21,0x32,0x40,0x0F,0xED,0x51,0x00,0xEB,0x70,0x32,0x3A,0x07,0x94,0x2A,0xC0,0xEC,
21 0x99,0x40,0x33,0x4B,0x70,0x3C,0x3E,0x00,0x78,0x3E,0x27,0x9C,0xC0,0xF2,0x07,0x81,
22 0x1A,0x99,0xA1,0x3D,0xE3,0xD3,0x7A,0x0F,0xF0,0xF1,0xE0,0xB0,0x98,0x58,0x08,0x29,
23 0x80,0xD0,0x78,0xC0,0xAF,0xF8,0x68,0x20,0x84,0x97,0x05,0xCF,0xD7,0x87,0x04,0x03,
24 0x63,0x07,0x64,0xBF,0x02,0x10,0x82,0xBF,0x2E,0x1C,0xD1,0x43,0x43,0x84,0x04,0x2F,
25 0x03,0x47,0x50,0x29,0xBE,0xB0,0x0E,0x21,0x46,0xA4,0x18,0x51,0x82,0xD4,0x0A,0xA1,
26 0xE9,0x87,0x49,0x50,0xE4,0xC9,0x01,0x3D,0x02,0x8E,0x77,0x02,0xC7,0x13,0xD9,0xE3,
27 0x89,0x72,0x12,0x07,0xE4,0x33,0x85,0x11,0x4E,0xF3,0x51,0xE2,0xD1,0xC2,0x9A,0x67,
28 0xA4,0x13,0xC3,0x39,0xBD,0x0D,0x98,0xA0,0xB2,0xE7,0x80,0x8E,0x1F,0x56,0x05,0x22,
29 0x1B,0x4B,0xF5,0x39,0x83,0x6A,0x5E,0xAE,0x46,0x74,0xCC,0xC7,0xEA,0x11,0x9C,0xB4,
30 0xA7,0x17,0xD9,0x4A,0xC1,0x04,0xEC,0x61,0x5B,0x23,0x85,0xD4,0xD0,0x68,0x3C,0x06,
31 0x77,0xFE,0x13,0x09,0x05,0x31,0xA0,0xC3,0x41,0xC8,0xC9,0x49,0x00,0xA5,0x62,0xBC,
32 0xE4,0x68,0xC1,0x08,0xA6,0x81,0xD0,0xDD,0xC1,0xF3,0xF3,0x3D,0x80,0xDF,0x4C,0x7C,
33 0x32,0x30,0xB0,0xEF,0x13,0x6F,0x1C,0xF0,0xFF,0xFF,0x37,0x0E,0x36,0x09,0x8C,0x9A,
34 0x23,0x04,0x9D,0x02,0xBF,0x00,0xBC,0x0A,0x98,0xC0,0xBA,0x2E,0x06,0xD0,0x4F,0x1D,
35 0x1E,0xA8,0xAF,0x1C,0x67,0x63,0x7D,0x07,0x03,0x50,0x00,0xF9,0x22,0xE0,0x93,0xC1,
36 0xC3,0x00,0xBB,0x19,0x18,0x26,0x9A,0xD1,0xB9,0xA8,0x69,0xA3,0x64,0xC0,0x68,0xDA,
37 0x06,0xF1,0xB4,0x1D,0x71,0xDA,0x68,0x68,0x5F,0x05,0x7C,0x11,0x70,0xA8,0x61,0xD3,
38 0x3B,0x07,0x7E,0xAE,0x67,0x16,0xD0,0x93,0xF0,0x91,0xE4,0xB8,0xC1,0x32,0x0A,0x06,
39 0x1E,0x24,0x8E,0x47,0xC1,0x26,0xCE,0x07,0xE0,0x89,0xF3,0x71,0xF9,0x86,0x01,0x7F,
40 0xE4,0x58,0x82,0x02,0x67,0x0E,0x72,0x78,0x4C,0xB0,0x51,0x51,0x59,0xE3,0x42,0x8D,
41 0xD2,0x57,0x20,0x86,0x7D,0x82,0x16,0x3D,0x48,0x9D,0x2F,0x0E,0xEA,0x69,0xC4,0x63,
42 0x33,0xAC,0xC7,0xFD,0xFF,0x0F,0x8B,0x41,0x0B,0x7B,0xB8,0x2F,0x22,0x3E,0xC5,0x78,
43 0x66,0xC6,0x08,0xEB,0xB1,0x7B,0x40,0x8F,0x10,0xE0,0x01,0x7B,0x35,0x39,0xD3,0x07,
44 0x97,0x3F,0x8E,0xEA,0x20,0x74,0xDF,0xE0,0x28,0x21,0x1E,0x38,0x30,0x04,0x15,0xDA,
45 0xF4,0xA9,0xD1,0xA8,0x55,0x83,0x32,0x35,0xCA,0x34,0xA8,0xD5,0xA7,0x52,0x63,0xC6,
46 0x3C,0x5C,0x8E,0xE8,0x41,0x81,0xBC,0x13,0x34,0x42,0x87,0x00,0xA1,0x42,0x9E,0x08,
47 0x32,0x72,0x0F,0x31,0x88,0x80,0xAC,0xCC,0x02,0x10,0xD3,0x09,0x22,0x20,0xFF,0xFF,
48 0x01


AlderLake Board Code: UpdateDsdt.c File Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • BoardAcpiDxe
UpdateDsdt.c File Reference

ACPI Update DSDT Library. More...

#include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/PciLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/PlatformNvsArea.h>
Include dependency graph for UpdateDsdt.c:

Go to the source code of this file.

Detailed Description

ACPI Update DSDT Library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file UpdateDsdt.c.


AlderLake Board Code: File Members

Here is a list of all documented file members with links to the documentation:

- a -

  • AcpiGnvsInit() : AcpiGnvsInit.c , BoardAcpiDxe.c
  • AllocateMemoryBelow4G() : AcpiPlatform.c

- f -

  • FindPmaxTable() : AdvancedPmaxDxe.c

- g -

  • GenerateSsdtFromConfigFile() : GenSsdtLib.c , GenSsdtLib.h
  • GetEcGpeNumber() : AcpiPlatform.c
  • GetStrLength() : AdvancedPmaxDxe.c
  • GuidStringToAcpiBuffer() : AcpiPlatform.c

- i -

  • In8042AuxData() : AcpiPlatform.c
  • InstallAcpiBoard() : BoardAcpiDxe.c
  • InstallAcpiPlatform() : AcpiPlatform.c , AcpiPlatform.h
  • InstallPmaxTable() : AdvancedPmaxDxe.c
  • InstallSocAcpiTable() : AcpiPlatform.c
  • InstallTable() : AdvancedPmaxDxe.c
  • InstallXhciAcpiTable() : AcpiPlatform.c
  • IsHardwareChange() : AcpiPlatform.c
  • IsPs2MouseConnected() : AcpiPlatform.c , AcpiPlatform.h

- l -

  • LocateSupportProtocol() : AcpiPlatform.c , AcpiPlatform.h , BoardAcpiDxe.c

- o -

  • Out8042AuxCommand() : AcpiPlatform.c

- p -

  • PlatformUpdateTables() : AcpiPlatform.c
  • PS2MouseEnable() : AcpiPlatform.c

- s -

  • SetAcpiSetupVariables() : AcpiPlatform.c
  • SortCpuLocalApicInTable() : AcpiPlatform.c , AcpiPlatform.h

- u -

  • UpdatePmaxTable() : AdvancedPmaxDxe.c

- w -

  • WaitInputEmpty() : AcpiPlatform.c
  • WaitOutputFull() : AcpiPlatform.c


AlderLake Board Code: File Members

- a -

  • AcpiGnvsInit() : AcpiGnvsInit.c , BoardAcpiDxe.c
  • AllocateMemoryBelow4G() : AcpiPlatform.c

- f -

  • FindPmaxTable() : AdvancedPmaxDxe.c

- g -

  • GenerateSsdtFromConfigFile() : GenSsdtLib.c , GenSsdtLib.h
  • GetEcGpeNumber() : AcpiPlatform.c
  • GetStrLength() : AdvancedPmaxDxe.c
  • GuidStringToAcpiBuffer() : AcpiPlatform.c

- i -

  • In8042AuxData() : AcpiPlatform.c
  • InstallAcpiBoard() : BoardAcpiDxe.c
  • InstallAcpiPlatform() : AcpiPlatform.c , AcpiPlatform.h
  • InstallPmaxTable() : AdvancedPmaxDxe.c
  • InstallSocAcpiTable() : AcpiPlatform.c
  • InstallTable() : AdvancedPmaxDxe.c
  • InstallXhciAcpiTable() : AcpiPlatform.c
  • IsHardwareChange() : AcpiPlatform.c
  • IsPs2MouseConnected() : AcpiPlatform.c , AcpiPlatform.h

- l -

  • LocateSupportProtocol() : AcpiPlatform.c , AcpiPlatform.h , BoardAcpiDxe.c

- o -

  • Out8042AuxCommand() : AcpiPlatform.c

- p -

  • PlatformUpdateTables() : AcpiPlatform.c
  • PS2MouseEnable() : AcpiPlatform.c

- s -

  • SetAcpiSetupVariables() : AcpiPlatform.c
  • SortCpuLocalApicInTable() : AcpiPlatform.c , AcpiPlatform.h

- u -

  • UpdatePmaxTable() : AdvancedPmaxDxe.c

- w -

  • WaitInputEmpty() : AcpiPlatform.c
  • WaitOutputFull() : AcpiPlatform.c


AlderLake Board Code: AcpiByteStream.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
AcpiByteStream.h
Go to the documentation of this file.
1 /**@file
2 Byte stream structures for ACPI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ACPI_BYTE_STREAM_H_
36 #define _ACPI_BYTE_STREAM_H_
37
38 #include <IndustryStandard/Acpi.h>
39
40 // @todo: Push these macros to Acpi.h file in Edk2 core.
41
42 //
43 // Definition block ecoding
44 //
45 #define ACPI_DEFINITION_BLOCK_LEADBYTE_OFFSET 0x24
46 #define ACPI_DEFINITION_BLOCK_PACKAGE_LENGTH_OFFSET 0x25
47
48 //
49 // External byte stream values and offsets
50 //
51 #define ACPI_EXTERNAL_OPCODE 0x15
52 #define ACPI_HEADER_EXTERNAL_OFFSET 0x24
53 #define ACPI_EXTERNAL_PCI_BUS_NUMBER_OFFSET 0xA
54 #define ACPI_EXTERNAL_NAME_TYPE_PREFIX_OFFSET 0x2
55 #define ACPI_EXTERNAL_NAME_OBJECT_COUNT_OFFSET 0x3
56
57 #define ACPI_DUAL_NAME_PREFIX 0x2E
58 #define ACPI_MULTI_NAME_PREFIX 0x2F
59
60 #define ACPI_SCOPE_OPCODE 0x10
61 #define ACPI_SCOPE_PACKAGE_LENGTH_OFFSET 0x1
62 #define ACPI_SCOPE_PCI_BUS_NUMBER_OFFSET 0x9
63
64 #define ACPI_PACKAGE_LENGTH_BYTEDATA_COUNT_MASK 0x3F
65
66 #define ACPI_DEVICE_PACKAGE_LENGTH_OFFSET 0X2
67
68 #define ACPI_NAME_OBJECT_STRING_OFFSET 0x6
69
70 #define ACPI_METHOD_NAME_OFFSET 0x1
71
72 #define ACPI_UNIQUE_ID_NUMBER_OFFSET 0x5
73
74 #define ACPI_CRS_BUFFER_LENGTH_PREFIX 0x8
75 #define ACPI_CRS_BUFFER_LENGTH_OFFSET 0x9
76
77 #define ACPI_BYTE_PREFIX_OPCODE 0x0A
78 #define ACPI_WORD_PREFIX_OPCODE 0x0B
79 #define ACPI_DWORD_PREFIX_OPCODE 0x0C
80 #define ACPI_STRING_PREFIX_OPCODE 0x0D
81 #define ACPI_QWORD_PREFIX_OPCODE 0x0E
82
83 #define ACPI_I2C_RESOURCE_CONTROLLER_NUMBER_OFFSET 0x1F
84
85 #define ACPI_STA_RETURN_VALUE_OFFSET 0x9
86 #define ACPI_STA_RETURN_VALUE_DEVICE_ENABLED 0xF
87 #define ACPI_STA_RETURN_VALUE_DEVICE_DISABLED 0x0
88
89 #define ACPI_GPIO_RESOURCE_TYPE 0x1
90 #define ACPI_GPIO_RESOURCE_TYPE_INTERRUPT 0x1
91 #define ACPI_GPIO_RESOURCE_TYPE_IO 0x2
92
93 #define ACPI_I2C_RESOURCE_TYPE 0x2
94
95 #define ASCII_0_ORDINAL ((UINT32) '0')
96
97 typedef struct {
98 UINT8 GpioConnectionDescriptor; // 0x8C
99 UINT8 Length1;
100 UINT8 Length2;
101 UINT8 RevisionId;
102 UINT8 GpioConnectionType; // 0x0 - Interrupt, 0x01 - IO Connection, 0x02-0xFF reserved
103 UINT8 GeneralFlags1;
104 UINT8 GeneralFlags2;
105 UINT8 InterruptAndIoFlags1;
106 UINT8 InterruptAndIoFlags2;
107 UINT8 PinConfiguration;
108 UINT8 OutputDriveStrength1;
109 UINT8 OutputDriveStrength2;
110 UINT8 DebounceTimeOut1;
111 UINT8 DebounceTimeOut2;
112 UINT8 PinTableOffset1;
113 UINT8 PinTableOffset2;
114 UINT8 ResourceSourceIndex;
115 UINT8 ResourceSourceNameOffset1;
116 UINT8 ResourceSourceNameOffset2;
117 UINT8 VendorDataOffset1;
118 UINT8 VendorDataOffset2;
119 UINT8 VendorDataLength1;
120 UINT8 VendorDataLength2;
121 UINT8 PinNumber1;
122 UINT8 PinNumber2;
123 CHAR8 ResourceSource[15];
124 } GPIO_RESOURCE;
125
126 typedef enum {
127 GpioInterrupt,
128 GpioIo
129 } GPIO_CONNECTION_TYPE;
130
131 typedef struct {
132 UINT8 I2cBusConnectionDescriptor; // 0x8E
133 UINT8 Length1;
134 UINT8 Length2;
135 UINT8 RevisionId;
136 UINT8 ResourceSourceIndex;
137 UINT8 SerialBusType; // 0x1 for I2C
138 UINT8 GeneralFlags;
139 UINT8 TypeSpecificFlags1;
140 UINT8 TypeSpecificFlags2;
141 UINT8 TypeSpecificRevisionId; // 0x1 for I2C
142 UINT8 TypeDataLength1; // minimum value 0x6
143 UINT8 TypeDataLength2; // minimum value 0x0
144 UINT32 ConnectionSpeed;
145 UINT16 SlaveAddress;
146 CHAR8 ResourceSource[15];
147 } I2C_SERIAL_BUS_RESOURCE;
148
149 typedef struct {
150 UINT8 ResourceType;
151 UINT16 GpioNumber;
152 UINT8 GpioResourceType;
153 BOOLEAN Shared;
154 } GPIO_RESOURCE_DATA;
155
156 typedef struct {
157 UINT8 ResourceType;
158 UINT32 I2cSlaveAddress;
159 UINT32 ConnectionSpeed;
160 UINT8 I2cSliceNumber;
161 } I2C_RESOURCE_DATA;
162
163 typedef struct {
164 CHAR8 DeviceName[4];
165 CHAR8 HardwareId[8];
166 CHAR8 CompatibilityId[8];
167 UINT32 UniqueId;
168 UINT8 Address;
169 CHAR8 DosDeviceName[32];
170 UINT8 EnableStatus;
171 UINT8 NumberOfResources;
172 } SSDT_DEVICE_DATA;
173
174 typedef struct {
175 EFI_GUID Guid;
176 UINT8 Revision;
177 UINT16 Count;
178 UINT8 Rsvd[5];
179 } PCT_ACPI_BLOCK_HDR;
180
181 #endif


AlderLake Board Code: AcpiCommon.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Include
AcpiCommon.h
Go to the documentation of this file.
1 /** @file
2 Header file for ACPI common Initialization Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ACPI_COMMON_H_
36 #define _ACPI_COMMON_H_
37
38 #define EFI_ACPI_S3_RESUME_SCRIPT_TABLE 0x00
39
40
41
42
43 #endif


AlderLake Board Code: AcpiGnvsInit.c Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • BoardAcpiDxe
AcpiGnvsInit.c
Go to the documentation of this file.
1 /** @file
2 Acpi Gnvs Init Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Uefi.h>
36 #include <Library/IoLib.h>
37 #include <Library/PciLib.h>
38 #include <Library/DebugLib.h>
39 #include <Library/BaseMemoryLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41
42 #include <Protocol/PlatformNvsArea.h>
43 #include <Protocol/MpService.h>
44
45 /**
46 @brief
47 Global NVS initialize.
48
49 @param[in] PlatformNvsAreaPtr - Pointer of global NVS area
50
51 @retval EFI_SUCCESS - Allocate Global NVS completed.
52 @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
53 **/
54 EFI_STATUS
55 EFIAPI
56 AcpiGnvsInit (
57 IN OUT VOID **PlatformNvsAreaPtr
58 )
59 {
60 UINTN Pages;
61 EFI_PHYSICAL_ADDRESS Address;
62 EFI_STATUS Status;
63 PLATFORM_NVS_AREA_PROTOCOL *GNVS;
64 EFI_MP_SERVICES_PROTOCOL *MpService;
65 UINTN NumberOfCPUs;
66 UINTN NumberOfEnabledCPUs;
67
68 Pages = EFI_SIZE_TO_PAGES (sizeof (PLATFORM_NVS_AREA));
69 Address = 0xffffffff; // allocate address below 4G.
70
71 Status = gBS->AllocatePages (
72 AllocateMaxAddress,
73 EfiACPIMemoryNVS,
74 Pages,
75 &Address
76 );
77 ASSERT_EFI_ERROR (Status);
78 if (EFI_ERROR(Status)) {
79 return Status;
80 }
81
82 //
83 // Locate the MP services protocol
84 // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
85 //
86 Status = gBS->LocateProtocol (
87 &gEfiMpServiceProtocolGuid,
88 NULL,
89 (VOID **) &MpService
90 );
91 ASSERT_EFI_ERROR (Status);
92
93 //
94 // Determine the number of processors
95 //
96 MpService->GetNumberOfProcessors (
97 MpService,
98 &NumberOfCPUs,
99 &NumberOfEnabledCPUs
100 );
101
102 *PlatformNvsAreaPtr = (VOID *) (UINTN) Address;
103 SetMem (*PlatformNvsAreaPtr, sizeof (PLATFORM_NVS_AREA), 0);
104
105 //
106 // GNVS default value init here...
107 //
108 GNVS = (PLATFORM_NVS_AREA_PROTOCOL *) &Address;
109
110 GNVS->Area->ThreadCount = (UINT8)NumberOfEnabledCPUs;
111
112 //
113 // Miscellaneous
114 //
115 GNVS->Area->PL1LimitCS = 0;
116 GNVS->Area->PL1LimitCSValue = 4500;
117
118 return EFI_SUCCESS;
119 }
120
AcpiGnvsInit
EFI_STATUS AcpiGnvsInit(IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize.
Definition: AcpiGnvsInit.c:56


AlderLake Board Code: AcpiPlatform.c Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
AcpiPlatform.c
Go to the documentation of this file.
1 /** @file
2 Advanced ACPI Driver
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include <Base.h>
35 #include <Uefi.h>
36 #include <Library/HobLib.h>
37 #include <Guid/HobList.h>
38 #include <Protocol/FirmwareVolume2.h>
39 #include <PlatformBoardId.h>
40 #include <IndustryStandard/AcpiAml.h>
41 #include <IndustryStandard/Pci30.h>
42 #include "AcpiPlatform.h"
43 #include <Library/PciSegmentLib.h>
44 #include <Library/PchInfoLib.h>
45 #include <Library/PchPcieRpLib.h>
46 #include <Library/SerialIoAccessLib.h>
47 #include <Library/GpioLib.h>
48 #include <Library/EspiLib.h>
49 #include <Library/GbeLib.h>
50 #include <Library/PchPciBdfLib.h>
51 #include <MeBiosPayloadHob.h>
52 #include <PlatformBoardConfig.h>
53 #include <Library/CpuPlatformLib.h>
54 #include <PlatformBoardType.h>
55 #include <PlatformInfo.h>
56 #include <Guid/S3MemoryVariable.h>
57 #include <Protocol/VariableLock.h>
58 #include <Mcfg.h>
59 #if FixedPcdGetBool(PcdITbtEnable) == 1
60 #include <TcssDataHob.h>
61 #endif
62 #include <Usb4PlatformHob.h>
63 #include <Library/IpuLib.h>
64 #include <Library/GnaInfoLib.h>
65 #include <Library/VmdInfoLib.h>
66 #include <Library/SataLib.h>
67 #include <Library/SataSocLib.h>
68 #include <Library/GraphicsInfoLib.h>
69 #include "GenSsdtLib.h"
70 // Global variables
71 //
72 GLOBAL_REMOVE_IF_UNREFERENCED VOID *mGfxNvsAddress;
73 GLOBAL_REMOVE_IF_UNREFERENCED ME_SETUP mMeSetup;
74 GLOBAL_REMOVE_IF_UNREFERENCED PCH_SETUP mPchSetup;
75 GLOBAL_REMOVE_IF_UNREFERENCED SETUP_DATA mSystemConfiguration;
76 GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL mPlatformNvsAreaProtocol;
77
78 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_IO2_PROTOCOL *mCpuIo;
79 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable;
80 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_APIC_ID_REORDER_MAP *mCpuApicIdReorderTable;
81 GLOBAL_REMOVE_IF_UNREFERENCED UINTN mNumberOfCpus;
82 GLOBAL_REMOVE_IF_UNREFERENCED UINTN mNumberOfEnabledCpus;
83 GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN IsX2ApicMode;
84
85 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_PACKAGE_INFO mSbspPackageInfo;
86 #if FixedPcdGetBool(PcdITbtEnable) == 1
87 GLOBAL_REMOVE_IF_UNREFERENCED TCSS_DATA_HOB *mTcssHob;
88 #endif
89 //
90 // Function implementations
91 //
92
93 /**
94 Install Soc ACPI Table
95
96 @param[in] *SsdtTableGuid Pointer to GUID that identifies new SSDT table
97 @param[in] Signature Signature of the table
98
99 **/
100 VOID
101 STATIC
102 InstallSocAcpiTable (
103 IN EFI_GUID *SsdtTableGuid,
104 IN UINT64 Signature
105 )
106 {
107 EFI_STATUS Status;
108 EFI_HANDLE *HandleBuffer;
109 UINTN NumberOfHandles;
110 UINTN Index;
111 INTN Instance;
112 UINTN Size;
113 UINT32 FvStatus;
114 UINTN TableHandle;
115 EFI_FV_FILETYPE FileType;
116 EFI_FV_FILE_ATTRIBUTES Attributes;
117 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
118 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
119 EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
120 EFI_ACPI_COMMON_HEADER *Table;
121
122 FwVol = NULL;
123 Table = NULL;
124
125 //
126 // Locate FV protocol.
127 //
128 Status = gBS->LocateHandleBuffer (
129 ByProtocol,
130 &gEfiFirmwareVolume2ProtocolGuid,
131 NULL,
132 &NumberOfHandles,
133 &HandleBuffer
134 );
135 ASSERT_EFI_ERROR (Status);
136
137 //
138 // Look for FV with ACPI storage file
139 //
140 for (Index = 0; Index < NumberOfHandles; Index++) {
141 //
142 // Get the protocol on this handle
143 // This should not fail because of LocateHandleBuffer
144 //
145 Status = gBS->HandleProtocol (
146 HandleBuffer[Index],
147 &gEfiFirmwareVolume2ProtocolGuid,
148 (VOID **) &FwVol
149 );
150 ASSERT_EFI_ERROR (Status);
151 if (FwVol == NULL) {
152 return;
153 }
154 //
155 // See if it has the ACPI storage file
156 //
157 Size = 0;
158 FvStatus = 0;
159 Status = FwVol->ReadFile (
160 FwVol,
161 SsdtTableGuid,
162 NULL,
163 &Size,
164 &FileType,
165 &Attributes,
166 &FvStatus
167 );
168 if (!EFI_ERROR (Status)) {
169 break;
170 }
171 }
172 //
173 // Free any allocated buffers
174 //
175 FreePool (HandleBuffer);
176
177 //
178 // Sanity check that we found our data file
179 //
180 ASSERT (FwVol);
181
182 //
183 // Locate ACPI tables
184 //
185 Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
186
187 //
188 // Read tables from the storage file.
189 //
190 if (FwVol == NULL) {
191 ASSERT_EFI_ERROR (EFI_NOT_FOUND);
192 return;
193 }
194 Instance = 0;
195
196 while (Status == EFI_SUCCESS) {
197 //
198 // Read the ACPI tables
199 //
200 Status = FwVol->ReadSection (
201 FwVol,
202 SsdtTableGuid,
203 EFI_SECTION_RAW,
204 Instance,
205 (VOID **) &Table,
206 &Size,
207 &FvStatus
208 );
209 if (!EFI_ERROR (Status)) {
210 TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
211
212 if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId == Signature) {
213 TableHandle = 0;
214 //
215 // Add the table
216 //
217 Status = AcpiTable->InstallAcpiTable (
218 AcpiTable,
219 TableHeader,
220 TableHeader->Length,
221 &TableHandle
222 );
223 }
224
225 //
226 // Increment the instance
227 //
228 Instance++;
229 Table = NULL;
230 }
231 }
232 }
233
234 /**
235 Install Xhci ACPI Table
236 **/
237 VOID
238 InstallXhciAcpiTable (
239 VOID
240 )
241 {
242 EFI_STATUS Status;
243 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
244 EFI_ACPI_COMMON_HEADER *CurrentTable;
245 UINT32 FvStatus;
246 UINTN Size;
247 UINTN TableHandle;
248 INTN Instance;
249 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
250 EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
251 EFI_GUID EfiAcpiMultiTableStorageGuid;
252
253 EfiAcpiMultiTableStorageGuid = gAcpiTableStorageGuid;
254 Instance = 0;
255 TableHandle = 0;
256 CurrentTable = NULL;
257 FwVol = NULL;
258
259 DEBUG ((DEBUG_INFO, "InstallXhciAcpiTable\n"));
260 //
261 // Update OEM table ID
262 //
263 if (PcdGet64 (PcdXhciAcpiTableSignature) == 0) {
264 DEBUG ((DEBUG_INFO, "InstallXhciAcpiTable: Cannot find PcdXhciAcpiTableSignature\n"));
265 return;
266 }
267
268 //
269 // Find the AcpiSupport protocol
270 //
271 Status = LocateSupportProtocol (
272 &gEfiAcpiTableProtocolGuid,
273 EfiAcpiMultiTableStorageGuid,
274 (VOID **) &AcpiTable,
275 FALSE
276 );
277 ASSERT_EFI_ERROR (Status);
278
279 //
280 // Locate the firmware volume protocol
281 //
282 Status = LocateSupportProtocol (
283 &gEfiFirmwareVolume2ProtocolGuid,
284 EfiAcpiMultiTableStorageGuid,
285 (VOID **) &FwVol,
286 TRUE
287 );
288
289 //
290 // Read tables from the storage file.
291 //
292 while (Status == EFI_SUCCESS) {
293 Status = FwVol->ReadSection (
294 FwVol,
295 &EfiAcpiMultiTableStorageGuid,
296 EFI_SECTION_RAW,
297 Instance,
298 (VOID **) &CurrentTable,
299 &Size,
300 &FvStatus
301 );
302
303 if (!EFI_ERROR (Status)) {
304
305 TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
306
307 if (TableHeader->OemTableId == PcdGet64 (PcdXhciAcpiTableSignature)) {
308 DEBUG ((DEBUG_INFO, "Install xhci table: %x\n", TableHeader->OemTableId));
309 //
310 // Add the table
311 //
312 TableHandle = 0;
313
314 Status = AcpiTable->InstallAcpiTable (
315 AcpiTable,
316 CurrentTable,
317 CurrentTable->Length,
318 &TableHandle
319 );
320
321 break;
322 }
323
324 //
325 // Increment the instance
326 //
327 Instance++;
328 gBS->FreePool (CurrentTable);
329 CurrentTable = NULL;
330 }
331 }
332
333 if (CurrentTable != NULL) {
334 gBS->FreePool (CurrentTable);
335 CurrentTable = NULL;
336 }
337 }
338
339 VOID
340 PublishOverClockingAcpiTable (
341 VOID
342 )
343 {
344 EFI_STATUS Status;
345 EFI_HANDLE *HandleBuffer;
346 UINTN NumberOfHandles;
347 UINTN Index;
348 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
349 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
350 EFI_ACPI_COMMON_HEADER *Table;
351 UINTN Size;
352 UINT32 FvStatus;
353 EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
354 UINTN TableHandle;
355
356 FwVol = NULL;
357 Table = NULL;
358
359 DEBUG ((DEBUG_INFO, "PublishOverClockingAcpiTable\n"));
360
361 //
362 // Locate FV protocol.
363 //
364 Status = gBS->LocateHandleBuffer (
365 ByProtocol,
366 &gEfiFirmwareVolume2ProtocolGuid,
367 NULL,
368 &NumberOfHandles,
369 &HandleBuffer
370 );
371 ASSERT_EFI_ERROR (Status);
372
373 //
374 // Look for FV with ACPI storage file
375 //
376 for (Index = 0; Index < NumberOfHandles; Index++) {
377
378 //
379 // Get the protocol on this handle
380 // This should not fail because of LocateHandleBuffer
381 //
382 Status = gBS->HandleProtocol (
383 HandleBuffer[Index],
384 &gEfiFirmwareVolume2ProtocolGuid,
385 (VOID **) &FwVol
386 );
387 ASSERT_EFI_ERROR (Status);
388
389 //
390 // See if it has the OverClocking Acpi Table file
391 //
392 Status = FwVol->ReadSection (
393 FwVol,
394 &gOcAcpiTableStorageGuid,
395 EFI_SECTION_RAW,
396 0,
397 (VOID **) &Table,
398 &Size,
399 &FvStatus
400 );
401 if (!EFI_ERROR (Status)) {
402 break;
403 }
404 }
405 //
406 // Free any allocated buffers
407 //
408 FreePool (HandleBuffer);
409
410 //
411 // Not find the table, it's fine the over clocking support is not enabled
412 //
413 if (Table == NULL) {
414 return;
415 }
416
417 Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
418
419 TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
420 if (CompareMem (&TableHeader->OemTableId, "PerfTune", 8) == 0) {
421 TableHandle = 0;
422 Status = AcpiTable->InstallAcpiTable (
423 AcpiTable,
424 Table,
425 Table->Length,
426 &TableHandle
427 );
428 }
429
430 if (Table != NULL) {
431 gBS->FreePool (Table);
432 Table = NULL;
433 }
434
435 }
436
437 /**
438 Locate the first instance of a protocol. If the protocol requested is an
439 FV protocol, then it will return the first FV that contains the ACPI table
440 storage file.
441
442 @param[in] Protocol The protocol to find.
443 @param[in] Instance Return pointer to the first instance of the protocol.
444 @param[in] Type TRUE if the desired protocol is a FV protocol.
445
446 @retval EFI_SUCCESS The function completed successfully.
447 @retval EFI_NOT_FOUND The protocol could not be located.
448 @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
449 **/
450 EFI_STATUS
451 LocateSupportProtocol (
452 IN EFI_GUID *Protocol,
453 IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
454 OUT VOID **Instance,
455 IN BOOLEAN Type
456 )
457 {
458 EFI_STATUS Status;
459 EFI_HANDLE *HandleBuffer;
460 UINTN NumberOfHandles;
461 EFI_FV_FILETYPE FileType;
462 UINT32 FvStatus;
463 EFI_FV_FILE_ATTRIBUTES Attributes;
464 UINTN Size;
465 UINTN Index;
466
467 //
468 // Locate protocol.
469 //
470 Status = gBS->LocateHandleBuffer (
471 ByProtocol,
472 Protocol,
473 NULL,
474 &NumberOfHandles,
475 &HandleBuffer
476 );
477 if (EFI_ERROR (Status)) {
478 //
479 // Defined errors at this time are not found and out of resources.
480 //
481 return Status;
482 }
483
484 //
485 // Looking for FV with ACPI storage file
486 //
487 for (Index = 0; Index < NumberOfHandles; Index++) {
488
489 //
490 // Get the protocol on this handle
491 // This should not fail because of LocateHandleBuffer
492 //
493 Status = gBS->HandleProtocol (
494 HandleBuffer[Index],
495 Protocol,
496 Instance
497 );
498 ASSERT_EFI_ERROR (Status);
499
500 if (!Type) {
501
502 //
503 // Not looking for the FV protocol, so find the first instance of the
504 // protocol. There should not be any errors because our handle buffer
505 // should always contain at least one or LocateHandleBuffer would have
506 // returned not found.
507 //
508 break;
509 }
510
511 //
512 // See if it has the ACPI storage file
513 //
514 Size = 0;
515 FvStatus = 0;
516 Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
517 *Instance,
518 &gEfiAcpiMultiTableStorageGuid,
519 NULL,
520 &Size,
521 &FileType,
522 &Attributes,
523 &FvStatus
524 );
525
526 //
527 // If we found it, then we are done
528 //
529 if (Status == EFI_SUCCESS) {
530 break;
531 }
532 }
533
534 //
535 // Our exit status is determined by the success of the previous operations
536 // If the protocol was found, Instance already points to it.
537 //
538 //
539 // Free any allocated buffers
540 //
541 FreePool (HandleBuffer);
542
543 return Status;
544 }
545
546 /*
547 This function will determine whether Native ASPM is supported on the platform.
548
549 @param[in] SystemConfiguration System configuration data
550
551 @return TRUE if Native ASPM is supported, FALSE otherwise
552 */
553 BOOLEAN
554 IsNativeAspmSupported (
555 CONST SETUP_DATA* SystemConfiguration
556 )
557 {
558 if (SystemConfiguration->PciExpNative == 0) {
559 return FALSE;
560 }
561 switch (SystemConfiguration->NativeAspmEnable) {
562 case 0:
563 return FALSE;
564 case 1:
565 return TRUE;
566 case 2: /* AUTO */
567 return PchIsPcieNativeAspmSupported ();
568 default:
569 ASSERT (0);
570 }
571 return TRUE;
572 }
573
574 /**
575 This function will provide the EC GPE number for ECDT update according to platform design
576
577 @retval EcGpeNumber EC GPE number to be reported in ECDT
578 **/
579 UINT32
580 GetEcGpeNumber (
581 VOID
582 )
583 {
584 UINT32 EcGpeNumber;
585
586 //
587 // EC GPE number assignment should be same as Method _GPE under ACPI EC Device which is used for OS without ECDT support
588 //
589 if (IsEspiEnabled ()) {
590 EcGpeNumber = 0x6E;
591 } else {
592 EcGpeNumber = 23;
593 if (mPlatformNvsAreaProtocol.Area->PcdSmcRuntimeSciPin != 0) {
594 GpioGetGpeNumber ((GPIO_PAD) mPlatformNvsAreaProtocol.Area->PcdSmcRuntimeSciPin, &EcGpeNumber);
595 }
596 }
597
598 DEBUG((DEBUG_INFO, "ACPI EcGpeNumber = 0x%x\n ", EcGpeNumber));
599
600 return EcGpeNumber;
601 }
602
603 /**
604 This function will update any runtime platform specific information.
605 This currently includes:
606 Setting OEM table values, ID, table ID, creator ID and creator revision.
607 Enabling the proper processor entries in the APIC tables
608 It also indicates with which ACPI table version the table belongs.
609
610 @param[in] Table The table to update
611 @param[in] Version Where to install this table
612
613 @retval EFI_SUCCESS Updated tables commplete.
614 **/
615 EFI_STATUS
616 PlatformUpdateTables (
617 IN OUT EFI_ACPI_COMMON_HEADER *Table,
618 IN OUT EFI_ACPI_TABLE_VERSION *Version
619 )
620 {
621 EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
622 UINT8 *CurrPtr;
623 UINT8 *TmpDsdtPointer;
624 UINT8 *EndPtr;
625 EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ApicPtr;
626 EFI_STATUS Status;
627 EFI_MP_SERVICES_PROTOCOL *MpService;
628
629 UINT8 MaximumDsdtPointLength;
630
631 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
632 UINT32 HpetBaseAdress;
633 UINT32 LocalApicCounter;
634 //UINT32 GcsRegister;
635 SA_SETUP SaSetup;
636 UINTN VariableSize;
637
638
639 CurrPtr = NULL;
640 EndPtr = NULL;
641 ApicPtr = NULL;
642
643 LocalApicCounter = 0;
644 MaximumDsdtPointLength = 20;
645
646 VariableSize = sizeof (SA_SETUP);
647 Status = gRT->GetVariable (
648 L"SaSetup",
649 &gSaSetupVariableGuid,
650 NULL,
651 &VariableSize,
652 &SaSetup
653 );
654 //
655 // This will be accurate except for FACS structure
656 //
657 TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
658
659 //
660 // Update the OEM and creator information for every table except FACS.
661 //
662 if (Table->Signature != EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {
663 if ((Table->Signature == EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) &&
664 (CompareMem (&TableHeader->OemId, "Rtd3", 4) == 0)) {
665 // For SsdtRtd3 table, "OemId" update is done later
666 } else {
667 CopyMem (TableHeader->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (TableHeader->OemId));
668 }
669
670 //
671 // Skip OEM table ID and creator information for SSDT tables, since these are
672 // created by an ASL compiler and the creator information is useful.
673 //
674 if (Table->Signature != EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
675 //
676 // Set through patchable PCD value
677 //
678 TableHeader->OemTableId = PcdGet64 (PcdAcpiDefaultOemTableId);
679 TableHeader->OemRevision = PcdGet32(PcdAcpiDefaultOemRevision);
680
681 //
682 // Update creator information
683 //
684 TableHeader->CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId);
685 TableHeader->CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision) ;
686 }
687 }
688
689 //
690 // Locate the PCI IO protocol
691 //
692 Status = gBS->LocateProtocol (
693 &gEfiPciRootBridgeIoProtocolGuid,
694 NULL,
695 (VOID **) &PciRootBridgeIo
696 );
697 ASSERT_EFI_ERROR (Status);
698
699 //
700 // Locate the MP services protocol
701 // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
702 //
703 Status = gBS->LocateProtocol (
704 &gEfiMpServiceProtocolGuid,
705 NULL,
706 (VOID **) &MpService
707 );
708 ASSERT_EFI_ERROR (Status);
709
710 //
711 // Get supported CPU Interrupt model (xApic or x2Apic)
712 //
713 IsX2ApicMode = (GetApicMode() == LOCAL_APIC_MODE_X2APIC) ? TRUE : FALSE;
714
715 //
716 // By default, a table belongs in all ACPI table versions published.
717 // Some tables will override this because they have different versions of the table.
718 //
719 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
720
721 //
722 // Update the various table types with the necessary updates
723 //
724 switch (Table->Signature) {
725
726 case EFI_ACPI_1_0_APIC_SIGNATURE:
727 //
728 // if not MP and not APIC then don't publish the APIC tables.
729 //
730 //@todo mSystemConfiguration.ApicEnabled default value is 1. So, the following logic is not executed.
731 //if (mSystemConfiguration.ApicEnabled == 0) {
732 // *Version = EFI_ACPI_TABLE_VERSION_NONE;
733 // break;
734 //}
735 CurrPtr = (UINT8 *) &((EFI_ACPI_DESCRIPTION_HEADER *) Table)[1];
736 CurrPtr = CurrPtr + 8;
737 //
738 // Size of Local APIC Address & Flag
739 //
740 EndPtr = (UINT8 *) Table;
741 EndPtr = EndPtr + Table->Length;
742
743 ApicPtr = (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) CurrPtr;
744 DEBUG((DEBUG_INFO, "ApicPtr Type = %x \n ", ApicPtr->Type));
745 if ((IsX2ApicMode && ApicPtr->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) ||(!IsX2ApicMode && ApicPtr->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC)) {
746 // Lets skip the MADT table in below cases:
747 // 1. MADT table with Local APIC records when X2Apic Mode is enabled.
748 // 2. MADT table with x2Apic records when xApic Mode is enabled.
749
750 *Version = EFI_ACPI_TABLE_VERSION_NONE;
751 break;
752 }
753
754 //
755 // Call for Local APIC ID Reorder
756 //
757 SortCpuLocalApicInTable(MpService);
758
759 while (CurrPtr < EndPtr) {
760 ApicPtr = (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) CurrPtr;
761
762 //
763 // Check table entry type
764 //
765 if ((ApicPtr->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) || (ApicPtr->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC)) {
766 AppendCpuMapTableEntry (
767 ApicPtr,
768 LocalApicCounter
769 );
770 LocalApicCounter++;
771 }
772
773 //
774 // Go to the next structure in the APIC table
775 //
776 CurrPtr = CurrPtr + ApicPtr->Length;
777 }
778 break;
779
780 case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
781 //
782 // Fix up all FACP Table values if configuration requires it.
783 // This code fixes up the following Table values:
784 // (1) C2/C3/CST Enable FACP values
785 // (2) RTC S4 Flag
786 //
787 {
788 EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
789
790 FadtPointer = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
791
792 //
793 // Check the version of the table
794 //
795 *Version = EFI_ACPI_TABLE_VERSION_NONE;
796 if (FadtPointer->Header.Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
797 *Version = EFI_ACPI_TABLE_VERSION_NONE;
798 } else if (FadtPointer->Header.Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
799 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0;
800 } else if (FadtPointer->Header.Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
801 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_3_0;
802 } else if (FadtPointer->Header.Revision == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
803 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_5_0;
804 } else if (FadtPointer->Header.Revision == EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
805 *Version = EFI_ACPI_TABLE_VERSION_5_0;
806 } else if (FadtPointer->Header.Revision == EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
807 *Version = EFI_ACPI_TABLE_VERSION_5_0;
808 }
809
810 //
811 // Modify MSI capability based on setup
812 //
813 if (mSystemConfiguration.EnableMsiInFadt == 0) {
814 FadtPointer->IaPcBootArch |= (1 << 3);
815 }
816
817 //
818 // Modify Preferred_PM_Profile field based on Board SKU's. Default is set to Mobile
819 //
820 FadtPointer->PreferredPmProfile = PcdGet8 (PcdPreferredPmProfile);
821
822 //
823 // if Native ASPM is disabled, set FACP table to skip Native ASPM
824 //
825 if (!IsNativeAspmSupported (&mSystemConfiguration)) {
826 FadtPointer->IaPcBootArch |= 0x10;
827 }
828
829 //
830 // PME WAKE supported, set PCI_EXP_WAK, BIT14 of Fixed feature flags.
831 //
832 FadtPointer->Flags |= (EFI_ACPI_6_0_PCI_EXP_WAK);
833
834 if (mSystemConfiguration.LowPowerS0Idle) {
835 //
836 // The Flags field within the FADT (offset 112)
837 // 1) will have a new Low Power S0 Idle Capable ACPI flag (bit offset 21).
838 //
839 FadtPointer->Flags = (BIT21 | FadtPointer->Flags);
840 //
841 //Only passive docking available in Conected Standby mode. Clear Docking capability Bit
842 //
843 FadtPointer->Flags &= ~BIT9;
844 //
845 // set indicates the power button is handled as a control method device.
846 //
847 FadtPointer->Flags |= EFI_ACPI_2_0_PWR_BUTTON;
848 } else {
849 FadtPointer->Flags &= ~(EFI_ACPI_2_0_PWR_BUTTON); // clear indicates the power button is handled as a fixed feature programming model
850 }
851
852 //
853 // 1. set header revision.
854 //
855 FadtPointer->Header.Revision = EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION;
856
857 //
858 // 2. set all GAR register AccessSize to valid value.
859 //
860 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->ResetReg.AccessSize = EFI_ACPI_6_3_BYTE;
861 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aEvtBlk.AccessSize = EFI_ACPI_6_3_WORD;
862 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bEvtBlk.AccessSize = EFI_ACPI_6_3_WORD;
863 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aCntBlk.AccessSize = EFI_ACPI_6_3_WORD;
864 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bCntBlk.AccessSize = EFI_ACPI_6_3_WORD;
865 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm2CntBlk.AccessSize = EFI_ACPI_6_3_BYTE;
866 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPmTmrBlk.AccessSize = EFI_ACPI_6_3_DWORD;
867 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe0Blk.AccessSize = EFI_ACPI_6_3_BYTE;
868 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe1Blk.AccessSize = EFI_ACPI_6_3_BYTE;
869
870 //
871 // SLEEP_CONTROL_REG and SLEEP_STATUS_REG are optional
872 // Only implement in HW-Reduced ACPI system
873 // In non-HW-Reduced system will remain all 0 as default
874 //
875 if ((FadtPointer->Flags & EFI_ACPI_6_3_HW_REDUCED_ACPI) != 0) {
876 //
877 // If the HW_REDUCED_ACPI flag in the table is set, OSPM will ignore fields related to the ACPI HW
878 //
879 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AddressSpaceId = 0x1;
880 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitWidth = 0x8;
881 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitOffset = 0;
882 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AccessSize = EFI_ACPI_6_3_DWORD;
883 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 4;
884
885 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AddressSpaceId = 0x1;
886 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitWidth = 0x8;
887 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitOffset = 0;
888 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AccessSize = EFI_ACPI_6_3_DWORD;
889 ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS;
890 }
891
892 //
893 // Set the S4BiosReq to 0 as we don't support it in the FACS for TGL.
894 //
895 FadtPointer->S4BiosReq = 0;
896
897 //@todo RtcS4WakeEnable and PmTimerEnable default value is 1. So, the following logic is not executed.
898 ////
899 //// Check if RTC S4 is enabled
900 ////
901 //if (!mSystemConfiguration.RtcS4WakeEnable) {
902
903 // //
904 // // Clear the S4 RTC flag
905 // //
906 // FadtPointer->Flags &= ~EFI_ACPI_2_0_RTC_S4;
907 //}
908
909 ////
910 //// Check if PM timer is enabled
911 ////
912 //if (!mSystemConfiguration.PmTimerEnable) {
913
914 // //
915 // // Clear the PM timer flag
916 // //
917 // FadtPointer->Flags &= ~EFI_ACPI_3_0_USE_PLATFORM_CLOCK;
918 //}
919 }
920 break;
921
922 case EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
923 //
924 // These items only belong in the 1.0 tables.
925 //
926 *Version = EFI_ACPI_TABLE_VERSION_1_0B;
927 break;
928
929 case EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
930 //
931 // Fix up the AML code in the DSDT affected by end user options.
932 // Fix up the following ASL Code:
933 // (1) ACPI Global NVS Memory Base and Size.
934 // (2) ACPI Graphics NVS Memory Base and Size.
935 // (3) SMBus I/O Base.
936 // (4) Thermal Management Methods.
937 //
938 {
939 UINT8 *DsdtPointer;
940 UINT32 *Signature;
941 UINT8 *Operation;
942 UINT32 *Address;
943 UINT8 *Value;
944 UINT16 *Size;
945 BOOLEAN EnterDock = FALSE;
946 //
947 // Loop through the ASL looking for values that we must fix up.
948 //
949 CurrPtr = (UINT8 *) Table;
950 for (DsdtPointer = CurrPtr;
951 DsdtPointer < (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length - sizeof (UINT32));
952 DsdtPointer++
953 ) {
954 Signature = (UINT32 *) DsdtPointer;
955 switch (*Signature) {
956 //
957 // GNVS operation region
958 //
959 case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
960 //
961 // Conditional match. For Region Objects, the Operator will always be the
962 // byte immediately before the specific name. Therefore, subtract 1 to check
963 // the Operator.
964 //
965 Operation = DsdtPointer - 1;
966 if (*Operation == AML_EXT_REGION_OP) {
967 Address = (UINT32 *) (DsdtPointer + 6);
968 *Address = (UINT32) (UINTN) mPlatformNvsAreaProtocol.Area;
969 Size = (UINT16 *) (DsdtPointer + 11);
970 *Size = sizeof (PLATFORM_NVS_AREA);
971 }
972 break;
973
974 //
975 // _AC0 method
976 //
977 case (SIGNATURE_32 ('_', 'A', 'C', '0')):
978 //
979 // Conditional match. _AC0 is >63 and <4095 bytes, so the package length is 2 bytes.
980 // Therefore, subtract 3 to check the Operator.
981 //
982 Operation = DsdtPointer - 3;
983 if (*Operation == AML_METHOD_OP) {
984 //
985 // Check if we want _AC0 enabled
986 //
987 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
988 Signature = (UINT32 *) DsdtPointer;
989 *Signature = SIGNATURE_32 ('X', 'A', 'C', '0');
990 }
991 }
992 break;
993
994 //
995 // _AL0 method
996 //
997 case (SIGNATURE_32 ('_', 'A', 'L', '0')):
998 //
999 // Conditional match. For Name Objects, the Operator will always be the byte
1000 // immediately before the specific name. Therefore, subtract 1 to check the
1001 // Operator.
1002 //
1003 Operation = DsdtPointer - 1;
1004 if (*Operation == AML_NAME_OP) {
1005
1006 //
1007 // Check if we want _AL0 enabled
1008 //
1009 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1010 Signature = (UINT32 *) DsdtPointer;
1011 *Signature = SIGNATURE_32 ('X', 'A', 'L', '0');
1012 }
1013 }
1014 break;
1015
1016 //
1017 // _AC1 method
1018 //
1019 case (SIGNATURE_32 ('_', 'A', 'C', '1')):
1020 //
1021 // Conditional match. _AC1 is < 63 bytes, so the package length is 1 byte.
1022 // Therefore, subtract 2 to check the Operator.
1023 //
1024 Operation = DsdtPointer - 2;
1025 if (*Operation == AML_METHOD_OP) {
1026
1027 //
1028 // Check if we want _AC1 enabled
1029 //
1030 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1031 Signature = (UINT32 *) DsdtPointer;
1032 *Signature = SIGNATURE_32 ('X', 'A', 'C', '1');
1033 }
1034 }
1035 break;
1036
1037 //
1038 // _AL1 method
1039 //
1040 case (SIGNATURE_32 ('_', 'A', 'L', '1')):
1041 //
1042 // Conditional match. For Name Objects, the Operator will always be the byte
1043 // immediately before the specific name. Therefore, subtract 1 to check the
1044 // Operator.
1045 //
1046 Operation = DsdtPointer - 1;
1047 if (*Operation == AML_NAME_OP) {
1048
1049 //
1050 // Check if we want _AL1 enabled
1051 //
1052 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1053 Signature = (UINT32 *) DsdtPointer;
1054 *Signature = SIGNATURE_32 ('X', 'A', 'L', '1');
1055 }
1056 }
1057 break;
1058
1059 //
1060 // _AC2 method
1061 //
1062 case (SIGNATURE_32 ('_', 'A', 'C', '2')):
1063 //
1064 // Conditional match. _AC2 is < 63 bytes, so the package length is 1 byte.
1065 // Therefore, subtract 2 to check the Operator.
1066 //
1067 Operation = DsdtPointer - 2;
1068 if (*Operation == AML_METHOD_OP) {
1069
1070 //
1071 // Check if we want _AC2 enabled
1072 //
1073 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1074 Signature = (UINT32 *) DsdtPointer;
1075 *Signature = SIGNATURE_32 ('X', 'A', 'C', '2');
1076 }
1077 }
1078 break;
1079
1080 //
1081 // _AL2 method
1082 //
1083 case (SIGNATURE_32 ('_', 'A', 'L', '2')):
1084 //
1085 // Conditional match. For Name Objects, the Operator will always be the byte
1086 // immediately before the specific name. Therefore, subtract 1 to check the
1087 // Operator.
1088 //
1089 Operation = DsdtPointer - 1;
1090 if (*Operation == AML_NAME_OP) {
1091
1092 //
1093 // Check if we want _AL2 enabled
1094 //
1095 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1096 Signature = (UINT32 *) DsdtPointer;
1097 *Signature = SIGNATURE_32 ('X', 'A', 'L', '2');
1098 }
1099 }
1100 break;
1101
1102 //
1103 // _AC3 method
1104 //
1105 case (SIGNATURE_32 ('_', 'A', 'C', '3')):
1106 //
1107 // Conditional match. _AC3 is < 63 bytes, so the package length is 1 byte.
1108 // Therefore, subtract 2 to check the Operator.
1109 //
1110 Operation = DsdtPointer - 2;
1111 if (*Operation == AML_METHOD_OP) {
1112
1113 //
1114 // Check if we want _AC3 enabled
1115 //
1116 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1117 Signature = (UINT32 *) DsdtPointer;
1118 *Signature = SIGNATURE_32 ('X', 'A', 'C', '3');
1119 }
1120 }
1121 break;
1122
1123 //
1124 // _AL3 method
1125 //
1126 case (SIGNATURE_32 ('_', 'A', 'L', '3')):
1127 //
1128 // Conditional match. For Name Objects, the Operator will always be the byte
1129 // immediately before the specific name. Therefore, subtract 1 to check the
1130 // Operator.
1131 //
1132 Operation = DsdtPointer - 1;
1133 if (*Operation == AML_NAME_OP) {
1134
1135 //
1136 // Check if we want _AL3 enabled
1137 //
1138 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1139 Signature = (UINT32 *) DsdtPointer;
1140 *Signature = SIGNATURE_32 ('X', 'A', 'L', '3');
1141 }
1142 }
1143 break;
1144
1145 //
1146 // _AC4 method
1147 //
1148 case (SIGNATURE_32 ('_', 'A', 'C', '4')):
1149 //
1150 // Conditional match. _AC4 is < 63 bytes, so the package length is 1 byte.
1151 // Therefore, subtract 2 to check the Operator.
1152 //
1153 Operation = DsdtPointer - 2;
1154 if (*Operation == AML_METHOD_OP) {
1155
1156 //
1157 // Check if we want _AC4 enabled
1158 //
1159 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1160 Signature = (UINT32 *) DsdtPointer;
1161 *Signature = SIGNATURE_32 ('X', 'A', 'C', '4');
1162 }
1163 }
1164 break;
1165
1166 //
1167 // _AL4 method
1168 //
1169 case (SIGNATURE_32 ('_', 'A', 'L', '4')):
1170 //
1171 // Conditional match. For Name Objects, the Operator will always be the byte
1172 // immediately before the specific name. Therefore, subtract 1 to check the
1173 // Operator.
1174 //
1175 Operation = DsdtPointer - 1;
1176 if (*Operation == AML_NAME_OP) {
1177
1178 //
1179 // Check if we want _AL4 enabled
1180 //
1181 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1182 Signature = (UINT32 *) DsdtPointer;
1183 *Signature = SIGNATURE_32 ('X', 'A', 'L', '4');
1184 }
1185 }
1186 break;
1187
1188 //
1189 // _AC5 method
1190 //
1191 case (SIGNATURE_32 ('_', 'A', 'C', '5')):
1192 //
1193 // Conditional match. _AC5 is < 63 bytes, so the package length is 1 byte.
1194 // Therefore, subtract 2 to check the Operator.
1195 //
1196 Operation = DsdtPointer - 2;
1197 if (*Operation == AML_METHOD_OP) {
1198
1199 //
1200 // Check if we want _AC5 enabled
1201 //
1202 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1203 Signature = (UINT32 *) DsdtPointer;
1204 *Signature = SIGNATURE_32 ('X', 'A', 'C', '5');
1205 }
1206 }
1207 break;
1208
1209 //
1210 // _AL5 method
1211 //
1212 case (SIGNATURE_32 ('_', 'A', 'L', '5')):
1213 //
1214 // Conditional match. For Name Objects, the Operator will always be the byte
1215 // immediately before the specific name. Therefore, subtract 1 to check the
1216 // Operator.
1217 //
1218 Operation = DsdtPointer - 1;
1219 if (*Operation == AML_NAME_OP) {
1220
1221 //
1222 // Check if we want _AL5 enabled
1223 //
1224 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1225 Signature = (UINT32 *) DsdtPointer;
1226 *Signature = SIGNATURE_32 ('X', 'A', 'L', '5');
1227 }
1228 }
1229 break;
1230
1231 //
1232 // _AC6 method
1233 //
1234 case (SIGNATURE_32 ('_', 'A', 'C', '6')):
1235 //
1236 // Conditional match. _AC6 is < 63 bytes, so the package length is 1 byte.
1237 // Therefore, subtract 2 to check the Operator.
1238 //
1239 Operation = DsdtPointer - 2;
1240 if (*Operation == AML_METHOD_OP) {
1241
1242 //
1243 // Check if we want _AC6 enabled
1244 //
1245 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1246 Signature = (UINT32 *) DsdtPointer;
1247 *Signature = SIGNATURE_32 ('X', 'A', 'C', '6');
1248 }
1249 }
1250 break;
1251
1252 //
1253 // _AL6 method
1254 //
1255 case (SIGNATURE_32 ('_', 'A', 'L', '6')):
1256 //
1257 // Conditional match. For Name Objects, the Operator will always be the byte
1258 // immediately before the specific name. Therefore, subtract 1 to check the
1259 // Operator.
1260 //
1261 Operation = DsdtPointer - 1;
1262 if (*Operation == AML_NAME_OP) {
1263
1264 //
1265 // Check if we want _AL6 enabled
1266 //
1267 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1268 Signature = (UINT32 *) DsdtPointer;
1269 *Signature = SIGNATURE_32 ('X', 'A', 'L', '6');
1270 }
1271 }
1272 break;
1273
1274 //
1275 // _AC7 method
1276 //
1277 case (SIGNATURE_32 ('_', 'A', 'C', '7')):
1278 //
1279 // Conditional match. _AC7 is < 63 bytes, so the package length is 1 byte.
1280 // Therefore, subtract 2 to check the Operator.
1281 //
1282 Operation = DsdtPointer - 2;
1283 if (*Operation == AML_METHOD_OP) {
1284
1285 //
1286 // Check if we want _AC7 enabled
1287 //
1288 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1289 Signature = (UINT32 *) DsdtPointer;
1290 *Signature = SIGNATURE_32 ('X', 'A', 'C', '7');
1291 }
1292 }
1293 break;
1294
1295 //
1296 // _AL7 method
1297 //
1298 case (SIGNATURE_32 ('_', 'A', 'L', '7')):
1299 //
1300 // Conditional match. For Name Objects, the Operator will always be the byte
1301 // immediately before the specific name. Therefore, subtract 1 to check the
1302 // Operator.
1303 //
1304 Operation = DsdtPointer - 1;
1305 if (*Operation == AML_NAME_OP) {
1306
1307 //
1308 // Check if we want _AL7 enabled
1309 //
1310 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1311 Signature = (UINT32 *) DsdtPointer;
1312 *Signature = SIGNATURE_32 ('X', 'A', 'L', '7');
1313 }
1314 }
1315 break;
1316
1317 //
1318 // _AC8 method
1319 //
1320 case (SIGNATURE_32 ('_', 'A', 'C', '8')):
1321 //
1322 // Conditional match. _AC8 is < 63 bytes, so the package length is 1 byte.
1323 // Therefore, subtract 2 to check the Operator.
1324 //
1325 Operation = DsdtPointer - 2;
1326 if (*Operation == AML_METHOD_OP) {
1327
1328 //
1329 // Check if we want _AC8 enabled
1330 //
1331 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1332 Signature = (UINT32 *) DsdtPointer;
1333 *Signature = SIGNATURE_32 ('X', 'A', 'C', '8');
1334 }
1335 }
1336 break;
1337
1338 //
1339 // _AL8 method
1340 //
1341 case (SIGNATURE_32 ('_', 'A', 'L', '8')):
1342 //
1343 // Conditional match. For Name Objects, the Operator will always be the byte
1344 // immediately before the specific name. Therefore, subtract 1 to check the
1345 // Operator.
1346 //
1347 Operation = DsdtPointer - 1;
1348 if (*Operation == AML_NAME_OP) {
1349
1350 //
1351 // Check if we want _AL8 enabled
1352 //
1353 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1354 Signature = (UINT32 *) DsdtPointer;
1355 *Signature = SIGNATURE_32 ('X', 'A', 'L', '8');
1356 }
1357 }
1358 break;
1359
1360 //
1361 // _AC9 method
1362 //
1363 case (SIGNATURE_32 ('_', 'A', 'C', '9')):
1364 //
1365 // Conditional match. _AC9 is < 63 bytes, so the package length is 1 byte.
1366 // Therefore, subtract 2 to check the Operator.
1367 //
1368 Operation = DsdtPointer - 2;
1369 if (*Operation == AML_METHOD_OP) {
1370
1371 //
1372 // Check if we want _AC9 enabled
1373 //
1374 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1375 Signature = (UINT32 *) DsdtPointer;
1376 *Signature = SIGNATURE_32 ('X', 'A', 'C', '9');
1377 }
1378 }
1379 break;
1380
1381 //
1382 // _AL9 method
1383 //
1384 case (SIGNATURE_32 ('_', 'A', 'L', '9')):
1385 //
1386 // Conditional match. For Name Objects, the Operator will always be the byte
1387 // immediately before the specific name. Therefore, subtract 1 to check the
1388 // Operator.
1389 //
1390 Operation = DsdtPointer - 1;
1391 if (*Operation == AML_NAME_OP) {
1392
1393 //
1394 // Check if we want _AL9 enabled
1395 //
1396 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1397 Signature = (UINT32 *) DsdtPointer;
1398 *Signature = SIGNATURE_32 ('X', 'A', 'L', '9');
1399 }
1400 }
1401 break;
1402
1403 //
1404 // _PSL method
1405 //
1406 case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
1407 //
1408 // Conditional match. _PSL is < 256 bytes, so the package length is 1 byte.
1409 // Therefore, subtract 2 to check the Operator.
1410 //
1411 Operation = DsdtPointer - 3;
1412 if (*Operation == AML_METHOD_OP) {
1413
1414 //
1415 // Check if we want _PSL enabled
1416 //
1417 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1418 Signature = (UINT32 *) DsdtPointer;
1419 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'L');
1420 }
1421 }
1422 break;
1423
1424 //
1425 // _PSV method
1426 //
1427 case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
1428 //
1429 // Conditional match. _PSV is < 256 bytes, so the package length is 1 byte.
1430 // Therefore, subtract 2 to check the Operator.
1431 //
1432 Operation = DsdtPointer - 3;
1433 if (*Operation == AML_METHOD_OP) {
1434
1435 //
1436 // Check if we want _PSV enabled
1437 //
1438 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1439 Signature = (UINT32 *) DsdtPointer;
1440 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'V');
1441 }
1442 }
1443 break;
1444
1445 //
1446 // _CRT method
1447 //
1448 case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
1449 //
1450 // Conditional match. _CRT is < 256 bytes, so the package length is 1 byte.
1451 // Subtract 3 to check the Operator for CRB, subract 2 for Harris Beach.
1452 //
1453 Operation = DsdtPointer - 3;
1454 if (*Operation == AML_METHOD_OP) {
1455
1456 //
1457 // Check if we want _CRT enabled
1458 //
1459 if (mSystemConfiguration.DisableCriticalTripPoints == 0) {
1460 Signature = (UINT32 *) DsdtPointer;
1461 *Signature = SIGNATURE_32 ('X', 'C', 'R', 'T');
1462 }
1463 }
1464 break;
1465
1466 //
1467 // _TC1 method
1468 //
1469 case (SIGNATURE_32 ('_', 'T', 'C', '1')):
1470 //
1471 // Conditional match. _TC1 is < 256 bytes, so the package length is 1 byte.
1472 // Therefore, subtract 2 to check the Operator.
1473 //
1474 Operation = DsdtPointer - 2;
1475 if (*Operation == AML_METHOD_OP) {
1476
1477 //
1478 // Check if we want _TC1 enabled
1479 //
1480 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1481 Signature = (UINT32 *) DsdtPointer;
1482 *Signature = SIGNATURE_32 ('X', 'T', 'C', '1');
1483 }
1484 }
1485 break;
1486
1487 //
1488 // _TC2 method
1489 //
1490 case (SIGNATURE_32 ('_', 'T', 'C', '2')):
1491 //
1492 // Conditional match. _TC2 is < 256 bytes, so the package length is 1 byte.
1493 // Therefore, subtract 2 to check the Operator.
1494 //
1495 Operation = DsdtPointer - 2;
1496 if (*Operation == AML_METHOD_OP) {
1497
1498 //
1499 // Check if we want _TC2 enabled
1500 //
1501 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1502 Signature = (UINT32 *) DsdtPointer;
1503 *Signature = SIGNATURE_32 ('X', 'T', 'C', '2');
1504 }
1505 }
1506 break;
1507
1508 //
1509 // _TSP method
1510 //
1511 case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
1512 //
1513 // Conditional match. _TSP is < 256 bytes, so the package length is 1 byte.
1514 // Therefore, subtract 2 to check the Operator.
1515 //
1516 Operation = DsdtPointer - 2;
1517 if (*Operation == AML_METHOD_OP) {
1518
1519 //
1520 // Check if we want _TSP enabled
1521 //
1522 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1523 Signature = (UINT32 *) DsdtPointer;
1524 *Signature = SIGNATURE_32 ('X', 'T', 'S', 'P');
1525 }
1526 }
1527 break;
1528
1529 //
1530 // Update SS3 Name with Setup value
1531 //
1532 case (SIGNATURE_32 ('S', 'S', '3', '_')):
1533 Operation = DsdtPointer - 1;
1534 if (*Operation == AML_NAME_OP) {
1535 Value = (UINT8 *) DsdtPointer + 4;
1536 *Value = (UINT8)mSystemConfiguration.AcpiSleepState;
1537 }
1538 break;
1539 //
1540 // Update SS4 Name with Setup value
1541 //
1542 case (SIGNATURE_32 ('S', 'S', '4', '_')):
1543 Operation = DsdtPointer - 1;
1544 if (*Operation == AML_NAME_OP) {
1545 Value = (UINT8 *) DsdtPointer + 4;
1546 *Value = mSystemConfiguration.AcpiHibernate;
1547 }
1548 break;
1549 //
1550 // _EJ0 method
1551 //
1552 case (SIGNATURE_32 ('_', 'E', 'J', '0')):
1553 if (mSystemConfiguration.LowPowerS0Idle) {
1554 //
1555 // Remove _EJ0 for SOC
1556 //
1557 if (*(DsdtPointer-3) == AML_METHOD_OP) {
1558 Signature = (UINT32 *) DsdtPointer;
1559 *Signature = SIGNATURE_32 ('X', 'E', 'J', '0');
1560 EnterDock = TRUE;
1561 }
1562 }
1563 break;
1564 //
1565 // _STA method for Device (\_SB.PC00.DOCK)
1566 //
1567 case (SIGNATURE_32 ('_', 'S', 'T', 'A')):
1568 if (mSystemConfiguration.LowPowerS0Idle) {
1569 //
1570 // Remove _STA in (\_SB.PC00.DOCK) for SOC
1571 //
1572 if ((*(DsdtPointer-3) == AML_METHOD_OP) && (EnterDock)) {
1573 Signature = (UINT32 *) DsdtPointer;
1574 *Signature = SIGNATURE_32 ('X', 'S', 'T', 'A');
1575 EnterDock = FALSE;
1576 }
1577 }
1578 break;
1579 //
1580 // _UPC method for Device (\_SB.PC00.XHCI.RHUB)
1581 //
1582 case (SIGNATURE_32('H', 'S', '1', '3')):
1583 for (TmpDsdtPointer = DsdtPointer;
1584 TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength;
1585 TmpDsdtPointer++){
1586 Signature = (UINT32 *) TmpDsdtPointer;
1587 switch (*Signature) {
1588 case(SIGNATURE_32('U', 'P', 'C', 'P')):
1589 Value = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
1590 break;
1591 default:
1592 //
1593 // Do nothing.
1594 //
1595 break;
1596 }
1597 }
1598 break;
1599
1600
1601 //
1602 // _DCK method
1603 //
1604 case (SIGNATURE_32 ('_', 'D', 'C', 'K')):
1605 if (mSystemConfiguration.LowPowerS0Idle) {
1606 //
1607 // Remove _DCK for SOC
1608 //
1609 if (*(DsdtPointer-3) == AML_METHOD_OP) {
1610 Signature = (UINT32 *) DsdtPointer;
1611 *Signature = SIGNATURE_32 ('X', 'D', 'C', 'K');
1612 }
1613 }
1614 break;
1615
1616 //
1617 // mask _DEP from CPU's scope if CS disabled.
1618 //
1619 case (SIGNATURE_32 ('P', 'R', '0', '0')):
1620 case (SIGNATURE_32 ('P', 'R', '0', '1')):
1621 case (SIGNATURE_32 ('P', 'R', '0', '2')):
1622 case (SIGNATURE_32 ('P', 'R', '0', '3')):
1623 case (SIGNATURE_32 ('P', 'R', '0', '4')):
1624 case (SIGNATURE_32 ('P', 'R', '0', '5')):
1625 case (SIGNATURE_32 ('P', 'R', '0', '6')):
1626 case (SIGNATURE_32 ('P', 'R', '0', '7')):
1627 case (SIGNATURE_32 ('P', 'R', '0', '8')):
1628 case (SIGNATURE_32 ('P', 'R', '0', '9')):
1629 case (SIGNATURE_32 ('P', 'R', '1', '0')):
1630 case (SIGNATURE_32 ('P', 'R', '1', '1')):
1631 case (SIGNATURE_32 ('P', 'R', '1', '2')):
1632 case (SIGNATURE_32 ('P', 'R', '1', '3')):
1633 case (SIGNATURE_32 ('P', 'R', '1', '4')):
1634 case (SIGNATURE_32 ('P', 'R', '1', '5')):
1635 if (mSystemConfiguration.LowPowerS0Idle == 0) {
1636 for (TmpDsdtPointer = DsdtPointer; TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength; TmpDsdtPointer++){
1637 Signature = (UINT32 *) TmpDsdtPointer;
1638 switch (*Signature) {
1639 case(SIGNATURE_32('_', 'D', 'E', 'P')):
1640 *(UINT8 *) TmpDsdtPointer = 'X';
1641 break;
1642 default:
1643 //
1644 // Do nothing.
1645 //
1646 break;
1647 }
1648 }
1649 }
1650 break;
1651
1652 //
1653 // _EDL name
1654 //
1655 case (SIGNATURE_32 ('_', 'E', 'D', 'L')):
1656 if (mSystemConfiguration.LowPowerS0Idle) {
1657 //
1658 // Remove _EDL for SOC
1659 //
1660 if (*(DsdtPointer-1) == AML_NAME_OP) {
1661 Signature = (UINT32 *) DsdtPointer;
1662 *Signature = SIGNATURE_32 ('X', 'E', 'D', 'L');
1663 }
1664 }
1665 break;
1666
1667 default:
1668 //
1669 // Do nothing.
1670 //
1671 break;
1672 }
1673 }
1674 }
1675 break;
1676
1677 case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
1678 //
1679 // If HPET is disabled in setup, don't publish the table.
1680 //
1681 if (mPchSetup.Hpet == FALSE) {
1682 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1683 } else {
1684 //
1685 // Get HPET base address
1686 //
1687 PchHpetBaseGet (&HpetBaseAdress);
1688 //
1689 // Adjust HPET Table to correct the Base Address
1690 //
1691 ((EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER*) Table)->BaseAddressLower32Bit.Address = HpetBaseAdress;
1692 }
1693 break;
1694
1695 case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
1696 //
1697 // Update MCFG base and end bus number
1698 //
1699 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].BaseAddress
1700 = PcdGet64 (PcdPciExpressBaseAddress);
1701
1702 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].EndBusNumber
1703 = (UINT8)(PcdGet32 (PcdPciExpressRegionLength) / 0x100000) - 1;
1704
1705 if ((((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].EndBusNumber > MAX_OS_VISIBLE_BUSES_WITH_VMD)
1706 && (SaSetup.VmdEnable == 1)) {
1707 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].EndBusNumber
1708 = MAX_OS_VISIBLE_BUSES_WITH_VMD;
1709 DEBUG((DEBUG_INFO,"VMD is enabled so restricting OS visible bus numbers to %d\n", MAX_OS_VISIBLE_BUSES_WITH_VMD));
1710 }
1711
1712 #if FixedPcdGetBool(PcdITbtEnable) == 1
1713 if (mTcssHob->TcssData.PcieMultipleSegmentEnabled) {
1714 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[1].BaseAddress
1715 = PcdGet64 (PcdPciExpressBaseAddress) + SIZE_256MB;
1716 } else
1717 #endif
1718 {
1719 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->Header.Length -= sizeof (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
1720 }
1721 break;
1722
1723 case EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:
1724 //
1725 // If EC is not present, don't publish the table.
1726 //
1727 if (mPlatformNvsAreaProtocol.Area->EcAvailable == PLATFORM_NVS_DEVICE_DISABLE) {
1728 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1729 } else {
1730 //
1731 // Update GPE Number
1732 //
1733 ((EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE *) Table)->GpeBit = (UINT8) GetEcGpeNumber ();
1734 }
1735 break;
1736
1737 /* @todo Need to uncomment once MSFT fully implements uPEP
1738 case SIGNATURE_32 ('L', 'P', 'I', 'T'):
1739 //
1740 // If L0s is disabled in setup, don't publish the table.
1741 //
1742 if (mSystemConfiguration.LowPowerS0Idle == 0) {
1743 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1744 }
1745 break;
1746 */
1747 case EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
1748 {
1749 UINT8 *TablePointer;
1750 UINT32 *Signature;
1751 UINT8 *Operation;
1752
1753 //
1754 // Do not load the xHCI table. It is handled by separate function.
1755 //
1756 if (CompareMem (&TableHeader->OemTableId, "xh_", 3) == 0) {
1757 DEBUG((DEBUG_INFO,"TableHeader->OemTableId = %x\n ", TableHeader->OemTableId));
1758 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1759 }
1760
1761 //
1762 // Load SSDT tables for the platforms based on boardID; default to RVP tables.
1763 // Load Ther_Rvp for all others.
1764 //
1765 if (CompareMem (&TableHeader->OemTableId, "Ther_Rvp", 8) == 0) {
1766 CurrPtr = (UINT8 *) Table;
1767 for (TablePointer = CurrPtr;TablePointer < (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length - sizeof (UINT32));TablePointer++)
1768 {
1769 Signature = (UINT32 *) TablePointer;
1770 switch (*Signature) {
1771 //
1772 // _AC0 method
1773 //
1774 case (SIGNATURE_32 ('_', 'A', 'C', '0')):
1775 //
1776 // Conditional match. _AC0 is >63 and <4095 bytes, so the package length is 2 bytes.
1777 // Therefore, subtract 3 to check the Operator.
1778 //
1779 Operation = TablePointer - 3;
1780 if (*Operation == AML_METHOD_OP) {
1781 //
1782 // Check if we want _AC0 enabled
1783 //
1784 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1785 Signature = (UINT32 *) TablePointer;
1786 *Signature = SIGNATURE_32 ('X', 'A', 'C', '0');
1787 }
1788 }
1789 break;
1790 //
1791 // _AL0 method
1792 //
1793 case (SIGNATURE_32 ('_', 'A', 'L', '0')):
1794 //
1795 // Conditional match. For Name Objects, the Operator will always be the byte
1796 // immediately before the specific name. Therefore, subtract 1 to check the
1797 // Operator.
1798 //
1799 Operation = TablePointer - 1;
1800 if (*Operation == AML_NAME_OP) {
1801 //
1802 // Check if we want _AL0 enabled
1803 //
1804 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1805 Signature = (UINT32 *) TablePointer;
1806 *Signature = SIGNATURE_32 ('X', 'A', 'L', '0');
1807 }
1808 }
1809 break;
1810 //
1811 // _AC1 method
1812 //
1813 case (SIGNATURE_32 ('_', 'A', 'C', '1')):
1814 //
1815 // Conditional match. _AC1 is < 63 bytes, so the package length is 1 byte.
1816 // Therefore, subtract 2 to check the Operator.
1817 //
1818 Operation = TablePointer - 2;
1819 if (*Operation == AML_METHOD_OP) {
1820 //
1821 // Check if we want _AC1 enabled
1822 //
1823 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1824 Signature = (UINT32 *) TablePointer;
1825 *Signature = SIGNATURE_32 ('X', 'A', 'C', '1');
1826 }
1827 }
1828 break;
1829 //
1830 // _AL1 method
1831 //
1832 case (SIGNATURE_32 ('_', 'A', 'L', '1')):
1833 //
1834 // Conditional match. For Name Objects, the Operator will always be the byte
1835 // immediately before the specific name. Therefore, subtract 1 to check the
1836 // Operator.
1837 //
1838 Operation = TablePointer - 1;
1839 if (*Operation == AML_NAME_OP) {
1840 //
1841 // Check if we want _AL1 enabled
1842 //
1843 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1844 Signature = (UINT32 *) TablePointer;
1845 *Signature = SIGNATURE_32 ('X', 'A', 'L', '1');
1846 }
1847 }
1848 break;
1849 //
1850 // _AC2 method
1851 //
1852 case (SIGNATURE_32 ('_', 'A', 'C', '2')):
1853 //
1854 // Conditional match. _AC2 is < 63 bytes, so the package length is 1 byte.
1855 // Therefore, subtract 2 to check the Operator.
1856 //
1857 Operation = TablePointer - 2;
1858 if (*Operation == AML_METHOD_OP) {
1859 //
1860 // Check if we want _AC2 enabled
1861 //
1862 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1863 Signature = (UINT32 *) TablePointer;
1864 *Signature = SIGNATURE_32 ('X', 'A', 'C', '2');
1865 }
1866 }
1867 break;
1868 //
1869 // _AL2 method
1870 //
1871 case (SIGNATURE_32 ('_', 'A', 'L', '2')):
1872 //
1873 // Conditional match. For Name Objects, the Operator will always be the byte
1874 // immediately before the specific name. Therefore, subtract 1 to check the
1875 // Operator.
1876 //
1877 Operation = TablePointer - 1;
1878 if (*Operation == AML_NAME_OP) {
1879 //
1880 // Check if we want _AL2 enabled
1881 //
1882 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1883 Signature = (UINT32 *) TablePointer;
1884 *Signature = SIGNATURE_32 ('X', 'A', 'L', '2');
1885 }
1886 }
1887 break;
1888 //
1889 // _AC3 method
1890 //
1891 case (SIGNATURE_32 ('_', 'A', 'C', '3')):
1892 //
1893 // Conditional match. _AC3 is < 63 bytes, so the package length is 1 byte.
1894 // Therefore, subtract 2 to check the Operator.
1895 //
1896 Operation = TablePointer - 2;
1897 if (*Operation == AML_METHOD_OP) {
1898 //
1899 // Check if we want _AC3 enabled
1900 //
1901 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1902 Signature = (UINT32 *) TablePointer;
1903 *Signature = SIGNATURE_32 ('X', 'A', 'C', '3');
1904 }
1905 }
1906 break;
1907 //
1908 // _AL3 method
1909 //
1910 case (SIGNATURE_32 ('_', 'A', 'L', '3')):
1911 //
1912 // Conditional match. For Name Objects, the Operator will always be the byte
1913 // immediately before the specific name. Therefore, subtract 1 to check the
1914 // Operator.
1915 //
1916 Operation = TablePointer - 1;
1917 if (*Operation == AML_NAME_OP) {
1918 //
1919 // Check if we want _AL3 enabled
1920 //
1921 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1922 Signature = (UINT32 *) TablePointer;
1923 *Signature = SIGNATURE_32 ('X', 'A', 'L', '3');
1924 }
1925 }
1926 break;
1927 //
1928 // _AC4 method
1929 //
1930 case (SIGNATURE_32 ('_', 'A', 'C', '4')):
1931 //
1932 // Conditional match. _AC4 is < 63 bytes, so the package length is 1 byte.
1933 // Therefore, subtract 2 to check the Operator.
1934 //
1935 Operation = TablePointer - 2;
1936 if (*Operation == AML_METHOD_OP) {
1937 //
1938 // Check if we want _AC4 enabled
1939 //
1940 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1941 Signature = (UINT32 *) TablePointer;
1942 *Signature = SIGNATURE_32 ('X', 'A', 'C', '4');
1943 }
1944 }
1945 break;
1946 //
1947 // _AL4 method
1948 //
1949 case (SIGNATURE_32 ('_', 'A', 'L', '4')):
1950 //
1951 // Conditional match. For Name Objects, the Operator will always be the byte
1952 // immediately before the specific name. Therefore, subtract 1 to check the
1953 // Operator.
1954 //
1955 Operation = TablePointer - 1;
1956 if (*Operation == AML_NAME_OP) {
1957 //
1958 // Check if we want _AL4 enabled
1959 //
1960 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1961 Signature = (UINT32 *) TablePointer;
1962 *Signature = SIGNATURE_32 ('X', 'A', 'L', '4');
1963 }
1964 }
1965 break;
1966 // _PSL method
1967 //
1968 case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
1969 //
1970 // Conditional match. _PSL is < 256 bytes, so the package length is 1 byte.
1971 // Therefore, subtract 2 to check the Operator.
1972 //
1973 Operation = TablePointer - 3;
1974 if (*Operation == AML_METHOD_OP) {
1975 //
1976 // Check if we want _PSL enabled
1977 //
1978 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1979 Signature = (UINT32 *) TablePointer;
1980 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'L');
1981 }
1982 }
1983 break;
1984 //
1985 // _PSV method
1986 //
1987 case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
1988 //
1989 // Conditional match. _PSV is < 256 bytes, so the package length is 1 byte.
1990 // Therefore, subtract 2 to check the Operator.
1991 //
1992 Operation = TablePointer - 3;
1993 if (*Operation == AML_METHOD_OP) {
1994 //
1995 // Check if we want _PSV enabled
1996 //
1997 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1998 Signature = (UINT32 *) TablePointer;
1999 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'V');
2000 }
2001 }
2002 break;
2003 //
2004 // _CRT method
2005 //
2006 case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
2007 //
2008 // Conditional match. _CRT is < 256 bytes, so the package length is 1 byte.
2009 // Subtract 3 to check the Operator for CRB, subract 2 for Harris Beach.
2010 //
2011 Operation = TablePointer - 3;
2012 if (*Operation == AML_METHOD_OP) {
2013 //
2014 // Check if we want _CRT enabled
2015 //
2016 if (mSystemConfiguration.DisableCriticalTripPoints == 0) {
2017 Signature = (UINT32 *) TablePointer;
2018 *Signature = SIGNATURE_32 ('X', 'C', 'R', 'T');
2019 }
2020 }
2021 break;
2022 //
2023 // _TC1 method
2024 //
2025 case (SIGNATURE_32 ('_', 'T', 'C', '1')):
2026 //
2027 // Conditional match. _TC1 is < 256 bytes, so the package length is 1 byte.
2028 // Therefore, subtract 2 to check the Operator.
2029 //
2030 Operation = TablePointer - 2;
2031 if (*Operation == AML_METHOD_OP) {
2032 //
2033 // Check if we want _TC1 enabled
2034 //
2035 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
2036 Signature = (UINT32 *) TablePointer;
2037 *Signature = SIGNATURE_32 ('X', 'T', 'C', '1');
2038 }
2039 }
2040 break;
2041 //
2042 // _TC2 method
2043 //
2044 case (SIGNATURE_32 ('_', 'T', 'C', '2')):
2045 //
2046 // Conditional match. _TC2 is < 256 bytes, so the package length is 1 byte.
2047 // Therefore, subtract 2 to check the Operator.
2048 //
2049 Operation = TablePointer - 2;
2050 if (*Operation == AML_METHOD_OP) {
2051 //
2052 // Check if we want _TC2 enabled
2053 //
2054 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
2055 Signature = (UINT32 *) TablePointer;
2056 *Signature = SIGNATURE_32 ('X', 'T', 'C', '2');
2057 }
2058 }
2059 break;
2060 //
2061 // _TSP method
2062 //
2063 case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
2064 //
2065 // Conditional match. _TSP is < 256 bytes, so the package length is 1 byte.
2066 // Therefore, subtract 2 to check the Operator.
2067 //
2068 Operation = TablePointer - 2;
2069 if (*Operation == AML_METHOD_OP) {
2070 //
2071 // Check if we want _TSP enabled
2072 //
2073 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
2074 Signature = (UINT32 *) TablePointer;
2075 *Signature = SIGNATURE_32 ('X', 'T', 'S', 'P');
2076 }
2077 }
2078 break;
2079 }
2080 }
2081 }
2082
2083 //
2084 // Load RTD3 SSDT table for ADL RVP SKUs
2085 // Note: "OemId" field is used to indentify whether SSDT table is for RTD3 usage
2086 //
2087 if ((CompareMem (&TableHeader->OemId, "Rtd3", 4) == 0)) {
2088 //
2089 // OemId should be replaced with PcdAcpiDefaultOemId
2090 //
2091 CopyMem (TableHeader->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (TableHeader->OemId));
2092 //
2093 // set default = none
2094 //
2095 *Version = EFI_ACPI_TABLE_VERSION_NONE;
2096
2097 //
2098 // check RTD3 enabled in setup
2099 //
2100 if (mSystemConfiguration.Rtd3Support == 1) {
2101 //
2102 // match table ID and BoardId
2103 //
2104
2105 if (TableHeader->OemTableId == PcdGet64 (PcdBoardRtd3TableSignature)) {
2106 DEBUG ((DEBUG_INFO, "Board SsdtRtd3 Table: %x\n", TableHeader->OemTableId));
2107 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
2108 }
2109 } // Rtd3Support
2110 } // Load RTD3 SSDT table
2111 }
2112 break;
2113
2114 default:
2115 break;
2116 }
2117 return EFI_SUCCESS;
2118 }
2119
2120 /**
2121 This function calculates RCR based on PCI Device ID and Vendor ID from the devices
2122 available on the platform.
2123 It also includes other instances of BIOS change to calculate CRC and provides as
2124 HWSignature filed in FADT table.
2125 **/
2126 VOID
2127 IsHardwareChange (
2128 VOID
2129 )
2130 {
2131 EFI_STATUS Status;
2132 UINTN Index;
2133 UINTN HandleCount;
2134 EFI_HANDLE *HandleBuffer;
2135 EFI_PCI_IO_PROTOCOL *PciIo;
2136 UINT32 CRC;
2137 UINT32 *HWChange;
2138 UINTN HWChangeSize;
2139 UINT32 PciId;
2140 UINTN Handle;
2141 EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
2142 EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
2143
2144 HandleCount = 0;
2145 HandleBuffer = NULL;
2146
2147 Status = gBS->LocateHandleBuffer (
2148 ByProtocol,
2149 &gEfiPciIoProtocolGuid,
2150 NULL,
2151 &HandleCount,
2152 &HandleBuffer
2153 );
2154 if (EFI_ERROR (Status)) {
2155 return; // PciIO protocol not installed yet!
2156 }
2157
2158 if (HandleCount > 0x1FFF) { // PCI config space max limit
2159 return;
2160 }
2161
2162 //
2163 // Allocate memory for HWChange and add additional entrie for
2164 // pFADT->XDsdt
2165 //
2166 HWChangeSize = HandleCount + 1;
2167 HWChange = AllocateZeroPool( sizeof(UINT32) * HWChangeSize );
2168 ASSERT( HWChange != NULL );
2169
2170 if (HWChange == NULL) return;
2171
2172 //
2173 // add HWChange inputs: PCI devices
2174 //
2175 for (Index = 0; HandleCount > 0; HandleCount--) {
2176 PciId = 0;
2177 Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **) &PciIo);
2178 if (!EFI_ERROR (Status)) {
2179 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0, 1, &PciId);
2180 if (EFI_ERROR (Status)) {
2181 continue;
2182 }
2183 HWChange[Index++] = PciId;
2184 }
2185 }
2186
2187 //
2188 // Locate FACP Table
2189 //
2190 Handle = 0;
2191 Status = LocateAcpiTableBySignature (
2192 EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
2193 (EFI_ACPI_DESCRIPTION_HEADER **) &pFADT,
2194 &Handle
2195 );
2196 if (EFI_ERROR (Status) || (pFADT == NULL)) {
2197 return; //Table not found or out of memory resource for pFADT table
2198 }
2199
2200 //
2201 // add HWChange inputs: others
2202 //
2203 HWChange[Index++] = (UINT32)pFADT->XDsdt;
2204
2205 //
2206 // Calculate CRC value with HWChange data.
2207 //
2208 Status = gBS->CalculateCrc32(HWChange, sizeof(UINT32) * HWChangeSize, &CRC);
2209 DEBUG((DEBUG_INFO,"CRC = %x and Status = %r\n", CRC, Status));
2210
2211 //
2212 // Set HardwareSignature value based on CRC value.
2213 //
2214 FacsPtr = (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT->FirmwareCtrl;
2215 FacsPtr->HardwareSignature = CRC;
2216 FreePool( HWChange );
2217 }
2218
2219 EFI_STATUS
2220 PublishAcpiTablesFromFv (
2221 IN EFI_GUID gEfiAcpiMultiTableStorageGuid
2222 )
2223 {
2224 EFI_STATUS Status;
2225 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
2226 EFI_ACPI_COMMON_HEADER *CurrentTable;
2227 UINT32 FvStatus;
2228 UINTN Size;
2229 EFI_ACPI_TABLE_VERSION Version;
2230 UINTN TableHandle;
2231 INTN Instance;
2232 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
2233
2234 Instance = 0;
2235 TableHandle = 0;
2236 CurrentTable = NULL;
2237 FwVol = NULL;
2238
2239 //
2240 // Find the AcpiSupport protocol
2241 //
2242 Status = LocateSupportProtocol (
2243 &gEfiAcpiTableProtocolGuid,
2244 gEfiAcpiMultiTableStorageGuid,
2245 (VOID **) &AcpiTable,
2246 FALSE
2247 );
2248 ASSERT_EFI_ERROR (Status);
2249
2250 //
2251 // Locate the firmware volume protocol
2252 //
2253 Status = LocateSupportProtocol (
2254 &gEfiFirmwareVolume2ProtocolGuid,
2255 gEfiAcpiMultiTableStorageGuid,
2256 (VOID **) &FwVol,
2257 TRUE
2258 );
2259
2260 /* TODO: Hang at native mode. Need to find the cause
2261 * when the related drivers are finished for native support. */
2262 //ASSERT_EFI_ERROR (Status);
2263
2264 //
2265 // Read tables from the storage file.
2266 //
2267 while (Status == EFI_SUCCESS) {
2268 Status = FwVol->ReadSection (
2269 FwVol,
2270 &gEfiAcpiMultiTableStorageGuid,
2271 EFI_SECTION_RAW,
2272 Instance,
2273 (VOID **) &CurrentTable,
2274 &Size,
2275 &FvStatus
2276 );
2277
2278 if (!EFI_ERROR (Status)) {
2279
2280 //
2281 // Perform any table specific updates.
2282 //
2283 PlatformUpdateTables (CurrentTable, &Version);
2284
2285 //
2286 // Add the table
2287 //
2288 TableHandle = 0;
2289
2290 if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
2291 DEBUG((DEBUG_INFO, "[Advanced ACPI] Installing table: %x : %x\n", CurrentTable->Signature, CurrentTable));
2292 Status = AcpiTable->InstallAcpiTable (
2293 AcpiTable,
2294 CurrentTable,
2295 CurrentTable->Length,
2296 &TableHandle
2297 );
2298 }
2299
2300 ASSERT_EFI_ERROR (Status);
2301
2302 //
2303 // Increment the instance
2304 //
2305 Instance++;
2306 gBS->FreePool (CurrentTable);
2307 CurrentTable = NULL;
2308 }
2309
2310 if (CurrentTable != NULL) {
2311 gBS->FreePool (CurrentTable);
2312 CurrentTable = NULL;
2313 }
2314 }
2315
2316 //
2317 // Finished
2318 //
2319 return EFI_SUCCESS;
2320 }
2321
2322
2323 /**
2324 Allocate MemoryType below 4G memory address.
2325
2326 @param[in] Size - Size of memory to allocate.
2327 @param[in] Buffer - Allocated address for output.
2328
2329 @retval EFI_SUCCESS - Memory successfully allocated.
2330 @retval Other - Other errors occur.
2331
2332 **/
2333 EFI_STATUS
2334 AllocateMemoryBelow4G (
2335 IN EFI_MEMORY_TYPE MemoryType,
2336 IN UINTN Size,
2337 OUT VOID **Buffer
2338 )
2339 {
2340 UINTN Pages;
2341 EFI_PHYSICAL_ADDRESS Address;
2342 EFI_STATUS Status;
2343
2344 Pages = EFI_SIZE_TO_PAGES (Size);
2345 Address = 0xffffffff;
2346
2347 Status = (gBS->AllocatePages) (
2348 AllocateMaxAddress,
2349 MemoryType,
2350 Pages,
2351 &Address
2352 );
2353
2354 *Buffer = (VOID *) (UINTN) Address;
2355
2356 return Status;
2357 }
2358
2359 EFI_STATUS
2360 ReserveS3Memory (
2361 VOID
2362 )
2363 {
2364 VOID *AcpiMemoryBase;
2365 UINT32 AcpiMemorySize;
2366 EFI_PEI_HOB_POINTERS Hob;
2367 UINT64 MemoryLength;
2368 S3_MEMORY_VARIABLE S3MemVariable;
2369 VOID *VariableData;
2370 UINTN VarSize;
2371 EFI_STATUS Status;
2372 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock;
2373
2374 DEBUG ((DEBUG_INFO, "ReserveS3Memory\n"));
2375
2376 //
2377 // Allocate ACPI reserved memory under 4G
2378 //
2379 Status = AllocateMemoryBelow4G (EfiReservedMemoryType, PcdGet32 (PcdS3AcpiReservedMemorySize), &AcpiMemoryBase);
2380 ASSERT (AcpiMemoryBase != 0);
2381 AcpiMemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);
2382
2383 //
2384 // Calculate the system memory length by memory hobs
2385 //
2386 MemoryLength = 0x100000;
2387 Hob.Raw = GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
2388 ASSERT (Hob.Raw != NULL);
2389 while ((Hob.Raw != NULL) && (!END_OF_HOB_LIST (Hob))) {
2390 if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
2391 //
2392 // Skip the memory region below 1MB
2393 //
2394 if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
2395 MemoryLength += Hob.ResourceDescriptor->ResourceLength;
2396 }
2397 }
2398 Hob.Raw = GET_NEXT_HOB (Hob);
2399 Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw);
2400 }
2401
2402 S3MemVariable.AcpiReservedMemoryBase = (EFI_PHYSICAL_ADDRESS)(UINTN) AcpiMemoryBase;
2403 S3MemVariable.AcpiReservedMemorySize = AcpiMemorySize;
2404 S3MemVariable.SystemMemoryLength = MemoryLength;
2405
2406 DEBUG((DEBUG_INFO, "ReserveS3Memory: AcpiMemoryBase is 0x%8x\n", S3MemVariable.AcpiReservedMemoryBase));
2407 DEBUG((DEBUG_INFO, "ReserveS3Memory: AcpiMemorySize is 0x%8x\n", S3MemVariable.AcpiReservedMemorySize));
2408 DEBUG((DEBUG_INFO, "ReserveS3Memory: SystemMemoryLength is 0x%8x\n", S3MemVariable.SystemMemoryLength));
2409
2410 VarSize = sizeof(S3_MEMORY_VARIABLE);
2411 Status = gBS->AllocatePool(
2412 EfiBootServicesData,
2413 VarSize,
2414 (VOID **) &VariableData
2415 );
2416 ASSERT_EFI_ERROR(Status);
2417 if (EFI_ERROR(Status)){
2418 return Status;
2419 }
2420 Status = gRT->GetVariable (
2421 S3_MEMORY_VARIABLE_NAME,
2422 &gS3MemoryVariableGuid,
2423 NULL,
2424 &VarSize,
2425 VariableData
2426 );
2427 if (EFI_ERROR (Status) || (0 != CompareMem (&S3MemVariable, VariableData, VarSize))) {
2428 DEBUG((DEBUG_INFO, "Update S3MemVariable.\n"));
2429 Status = gRT->SetVariable (
2430 S3_MEMORY_VARIABLE_NAME,
2431 &gS3MemoryVariableGuid,
2432 EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
2433 VarSize,
2434 &S3MemVariable
2435 );
2436 }
2437 gBS->FreePool(VariableData);
2438
2439 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
2440 if (!EFI_ERROR (Status)) {
2441 Status = VariableLock->RequestToLock (VariableLock, S3_MEMORY_VARIABLE_NAME, &gS3MemoryVariableGuid);
2442 ASSERT_EFI_ERROR (Status);
2443 }
2444
2445 return EFI_SUCCESS;
2446 }
2447
2448 VOID
2449 EFIAPI
2450 AcpiEndOfDxeEvent (
2451 EFI_EVENT Event,
2452 VOID *ParentImageHandle
2453 )
2454 {
2455
2456 if (Event != NULL) {
2457 gBS->CloseEvent(Event);
2458 }
2459
2460
2461 //
2462 // Install xHCI SSDT ACPI Table
2463 //
2464 InstallXhciAcpiTable ();
2465
2466 //
2467 // Install Soc Gpe SSDT ACPI Table
2468 //
2469 InstallSocAcpiTable (&gSocGpeSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'o', 'c', 'G', 'p', 'e', ' ', 0));
2470
2471 //
2472 // Install Soc Common SSDT ACPI Table
2473 //
2474 InstallSocAcpiTable (&gSocCmnSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'o', 'c', 'C', 'm', 'n', ' ', 0));
2475
2476 //
2477 // Calculate Hardware Signature value based on current platform configurations
2478 //
2479 IsHardwareChange();
2480
2481 //
2482 // Reserve memory for S3 resume
2483 //
2484 ReserveS3Memory ();
2485 }
2486
2487 /**
2488 Convert string containing GUID in the canonical form:
2489 "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp"
2490 where aa - pp are unicode hexadecimal digits
2491 to the buffer format to be used in ACPI, byte ordering:
2492 [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7]
2493 [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16]
2494
2495 @param[in] GuidString - GUID String null terminated (aligned on a 16-bit boundary)
2496 @param[out] AcpiGuidPart1 - First half of buffer (bytes 0 - 7)
2497 @param[out] AcpiGuidPart2 - Second half of buffer (bytes 8 - 16)
2498
2499 @retval EFI_SUCCESS - String converted successfully.
2500 @retval EFI_UNSUPPORTED - Wrong input string format.
2501
2502 **/
2503 EFI_STATUS
2504 GuidStringToAcpiBuffer (
2505 IN CHAR16 *GuidString,
2506 OUT UINT64 *AcpiGuidPart1,
2507 OUT UINT64 *AcpiGuidPart2
2508 )
2509 {
2510 UINT32 GuidTempPart32 = 0;
2511 UINT16 GuidTempPart16 = 0;
2512 UINT8 GuidPartIndex;
2513
2514 DEBUG((DEBUG_INFO,"GuidStringToAcpiBuffer() - GUID = %s\n", GuidString));
2515
2516 for (GuidPartIndex = 0; GuidPartIndex < 4; GuidPartIndex++) {
2517 switch (GuidPartIndex){
2518 case 0:
2519 GuidTempPart32 = SwapBytes32((UINT32)StrHexToUint64(GuidString));
2520 *AcpiGuidPart1 = ((UINT64)GuidTempPart32 << 0x20);
2521 break;
2522 case 1:
2523 GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
2524 *AcpiGuidPart1 += ((UINT64)GuidTempPart16 << 0x10);
2525 break;
2526 case 2:
2527 GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
2528 *AcpiGuidPart1 += ((UINT64)GuidTempPart16);
2529 break;
2530 case 3:
2531 GuidTempPart16 = (UINT16)StrHexToUint64(GuidString);
2532 break;
2533 default:
2534 return EFI_UNSUPPORTED;
2535 }
2536
2537 while ((*GuidString != L'-') && (*GuidString != L'\0')) {
2538 GuidString++;
2539 }
2540
2541 if (*GuidString == L'-') {
2542 GuidString++;
2543 } else {
2544 return EFI_UNSUPPORTED;
2545 }
2546 }
2547
2548 *AcpiGuidPart2 = ((UINT64)GuidTempPart16 << 0x30) + StrHexToUint64(GuidString);
2549
2550 // Switch endianess because it will be swapped again in ACPI Buffer object
2551 *AcpiGuidPart1 = SwapBytes64(*AcpiGuidPart1);
2552 *AcpiGuidPart2 = SwapBytes64(*AcpiGuidPart2);
2553
2554 return EFI_SUCCESS;
2555 }
2556
2557 /**
2558 Save Acpi Setup relatived variables.
2559 **/
2560 EFI_STATUS
2561 SetAcpiSetupVariables (
2562 VOID
2563 )
2564 {
2565 EFI_STATUS Status;
2566 UINTN Handle;
2567 SETUP_DATA SetupData;
2568 UINTN VariableSize;
2569 UINT32 VariableAttributes;
2570 EFI_ACPI_DESCRIPTION_HEADER *Table;
2571
2572 VariableSize = sizeof (SETUP_DATA);
2573 Status = gRT->GetVariable (
2574 L"Setup",
2575 &gSetupVariableGuid,
2576 &VariableAttributes,
2577 &VariableSize,
2578 &SetupData
2579 );
2580 if (EFI_ERROR (Status)) {
2581 return Status;
2582 }
2583
2584 ///
2585 /// Locate table with matching ID
2586 ///
2587 Handle = 0;
2588 Table = NULL;
2589 Status = LocateAcpiTableBySignature (
2590 EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
2591 (EFI_ACPI_DESCRIPTION_HEADER **) &Table,
2592 &Handle
2593 );
2594 if (EFI_ERROR (Status) || (Table == NULL)) {
2595 return Status;
2596 }
2597
2598 SetupData.AcpiTableRevision = Table->Revision;
2599 Status = gRT->SetVariable (
2600 L"Setup",
2601 &gSetupVariableGuid,
2602 VariableAttributes,
2603 VariableSize,
2604 &SetupData
2605 );
2606 ASSERT_EFI_ERROR(Status);
2607 DEBUG ((DEBUG_INFO, "Acpi table revision: 0x%x, saved successfully.\n", Table->Revision));
2608
2609 return Status;
2610 }
2611
2612 /**
2613 ACPI Platform driver installation function.
2614
2615 @param[in] ImageHandle Handle for this drivers loaded image protocol.
2616 @param[in] SystemTable EFI system table.
2617
2618 @retval EFI_SUCCESS The driver installed without error.
2619 @retval EFI_ABORTED The driver encountered an error and could not complete installation of
2620 the ACPI tables.
2621
2622 **/
2623 EFI_STATUS
2624 EFIAPI
2625 InstallAcpiPlatform (
2626 IN EFI_HANDLE ImageHandle,
2627 IN EFI_SYSTEM_TABLE *SystemTable
2628 )
2629 {
2630 EFI_STATUS Status;
2631 UINTN VarDataSize;
2632 EFI_HANDLE Handle;
2633 UINT8 PortData;
2634 //UINT8 BatteryNum;
2635 CPUID_VERSION_INFO_EAX CpuidVersionInfoEax;
2636 EFI_MP_SERVICES_PROTOCOL *MpService;
2637 UINTN Index;
2638 EFI_EVENT EndOfDxeEvent;
2639 SA_SETUP SaSetup;
2640 CPU_SETUP CpuSetup;
2641 UINT64 RpDeviceBaseAddress;
2642 UINT8 PreBootCmMode;
2643 UINT8 CmTbtMask;
2644 UINT8 Usb4CmSwitchEnable;
2645 VOID *HobPtr;
2646 USB4_PLATFORM_HOB *Usb4PlatformHob;
2647 USB4_PLATFORM_INFO *Usb4PlatformInfo;
2648
2649 UINT16 ModuleName[MIPICAM_MODULE_NAME_LENGTH];
2650 UINT64 AcpiGuidPart1;
2651 UINT64 AcpiGuidPart2;
2652 CHAR16 LocalGuidString[GUID_CHARS_NUMBER];
2653 UINT8 SerialIoIndex;
2654 UINT8 PepSerialIoI2c[PCH_MAX_SERIALIO_I2C_CONTROLLERS];
2655 UINT8 PepSerialIoSpi[PCH_MAX_SERIALIO_SPI_CONTROLLERS];
2656 UINT8 PepSerialIoUart[PCH_MAX_SERIALIO_UART_CONTROLLERS];
2657 UINT8 PepUfs[PCH_MAX_UFS_DEV_NUM];
2658 UINT8 UfsIndex;
2659
2660
2661 Handle = NULL;
2662 mCpuApicIdOrderTable = NULL;
2663 mCpuApicIdReorderTable = NULL;
2664
2665 AsmCpuid (
2666 CPUID_VERSION_INFO,
2667 &CpuidVersionInfoEax.Uint32,
2668 NULL,
2669 NULL,
2670 NULL
2671 );
2672
2673 PublishOverClockingAcpiTable ();
2674
2675 //
2676 // Locate the setup configuration data
2677 // We assert if it is not found because we have a dependency on PlatformCpu,
2678 // published by the platform setup driver.
2679 // This should ensure that we only get called after the setup has updated the
2680 // variable.
2681 //
2682 VarDataSize = sizeof (SETUP_DATA);
2683 Status = gRT->GetVariable (
2684 L"Setup",
2685 &gSetupVariableGuid,
2686 NULL,
2687 &VarDataSize,
2688 &mSystemConfiguration
2689 );
2690
2691 VarDataSize = sizeof (SA_SETUP);
2692 Status = gRT->GetVariable (
2693 L"SaSetup",
2694 &gSaSetupVariableGuid,
2695 NULL,
2696 &VarDataSize,
2697 &SaSetup
2698 );
2699
2700 VarDataSize = sizeof (ME_SETUP);
2701 Status = gRT->GetVariable (
2702 L"MeSetup",
2703 &gMeSetupVariableGuid,
2704 NULL,
2705 &VarDataSize,
2706 &mMeSetup
2707 );
2708
2709 VarDataSize = sizeof (CPU_SETUP);
2710 Status = gRT->GetVariable (
2711 L"CpuSetup",
2712 &gCpuSetupVariableGuid,
2713 NULL,
2714 &VarDataSize,
2715 &CpuSetup
2716 );
2717
2718 VarDataSize = sizeof (PCH_SETUP);
2719 Status = gRT->GetVariable (
2720 L"PchSetup",
2721 &gPchSetupVariableGuid,
2722 NULL,
2723 &VarDataSize,
2724 &mPchSetup
2725 );
2726 //
2727 // Locate the MP services protocol
2728 // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
2729 //
2730 Status = gBS->LocateProtocol (
2731 &gEfiMpServiceProtocolGuid,
2732 NULL,
2733 (VOID **) &MpService
2734 );
2735 if (EFI_ERROR (Status)) {
2736 return Status;
2737 }
2738
2739 //
2740 // Determine the number of processors
2741 //
2742 MpService->GetNumberOfProcessors (
2743 MpService,
2744 &mNumberOfCpus,
2745 &mNumberOfEnabledCpus
2746 );
2747
2748 DEBUG ((DEBUG_INFO, "mNumberOfCpus - %x,mNumberOfEnabledCpus - %x\n", mNumberOfCpus, mNumberOfEnabledCpus));
2749 mCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));
2750 if (mCpuApicIdOrderTable == NULL) {
2751 return EFI_UNSUPPORTED;
2752 }
2753 mCpuApicIdReorderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_APIC_ID_REORDER_MAP));
2754 if (mCpuApicIdReorderTable == NULL) {
2755 return EFI_UNSUPPORTED;
2756 }
2757
2758 //
2759 // Allocate and initialize the NVS area for SMM and ASL communication.
2760 //
2761 AcpiGnvsInit((VOID **) &mPlatformNvsAreaProtocol.Area);
2762
2763 //
2764 // Update global NVS area for ASL and SMM init code to use
2765 //
2766 //mPlatformNvsAreaProtocol.Area->EnableThermalOffset = mSystemConfiguration.EnableThermalOffset;
2767 mPlatformNvsAreaProtocol.Area->Ac1TripPoint = mSystemConfiguration.Ac1TripPoint;
2768 mPlatformNvsAreaProtocol.Area->Ac0TripPoint = mSystemConfiguration.Ac0TripPoint;
2769 mPlatformNvsAreaProtocol.Area->Ac1FanSpeed = mSystemConfiguration.Ac1FanSpeed;
2770 mPlatformNvsAreaProtocol.Area->Ac0FanSpeed = mSystemConfiguration.Ac0FanSpeed;
2771 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;
2772 mPlatformNvsAreaProtocol.Area->PassiveTc1Value = mSystemConfiguration.PassiveTc1Value;
2773 mPlatformNvsAreaProtocol.Area->PassiveTc2Value = mSystemConfiguration.PassiveTc2Value;
2774 mPlatformNvsAreaProtocol.Area->PassiveTspValue = mSystemConfiguration.PassiveTspValue;
2775 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;
2776 mPlatformNvsAreaProtocol.Area->EmaEnable = 0; //mSystemConfiguration.EmaEnable; //todo
2777 mPlatformNvsAreaProtocol.Area->ThreadCount = (UINT8) mNumberOfEnabledCpus;
2778 mPlatformNvsAreaProtocol.Area->MefEnable = 0; //mSystemConfiguration.MefEnable; //todo
2779
2780 //
2781 // Intel(R) Dynamic Tuning Technology Devices and trip points
2782 //
2783 mPlatformNvsAreaProtocol.Area->EnableDptf = mSystemConfiguration.EnableDptf;
2784
2785 if (mSystemConfiguration.EnableDptf == 1) {
2786
2787 mPlatformNvsAreaProtocol.Area->EnableDCFG = mSystemConfiguration.EnableDCFG;
2788 mPlatformNvsAreaProtocol.Area->EnableSaDevice = mSystemConfiguration.EnableSaDevice;
2789 mPlatformNvsAreaProtocol.Area->PpccStepSize = mSystemConfiguration.PpccStepSize;
2790
2791 //
2792 // Intel(R) Dynamic Tuning Technology Devices
2793 //
2794 mPlatformNvsAreaProtocol.Area->EnableFan1Device = mSystemConfiguration.EnableFan1Device;
2795 mPlatformNvsAreaProtocol.Area->EnableFan2Device = mSystemConfiguration.EnableFan2Device;
2796 mPlatformNvsAreaProtocol.Area->EnableFan3Device = mSystemConfiguration.EnableFan3Device;
2797
2798 //
2799 // Intel(R) Dynamic Tuning Technology Oem Design Variable
2800 //
2801
2802 mPlatformNvsAreaProtocol.Area->OemDesignVariable0 = mSystemConfiguration.OemDesignVariable0;
2803 mPlatformNvsAreaProtocol.Area->OemDesignVariable1 = mSystemConfiguration.OemDesignVariable1;
2804 mPlatformNvsAreaProtocol.Area->OemDesignVariable2 = mSystemConfiguration.OemDesignVariable2;
2805 mPlatformNvsAreaProtocol.Area->OemDesignVariable3 = mSystemConfiguration.OemDesignVariable3;
2806 mPlatformNvsAreaProtocol.Area->OemDesignVariable4 = mSystemConfiguration.OemDesignVariable4;
2807 mPlatformNvsAreaProtocol.Area->OemDesignVariable5 = mSystemConfiguration.OemDesignVariable5;
2808
2809 mPlatformNvsAreaProtocol.Area->EnableChargerParticipant = mSystemConfiguration.EnableChargerParticipant;
2810 mPlatformNvsAreaProtocol.Area->EnablePowerParticipant = mSystemConfiguration.EnablePowerParticipant;
2811 mPlatformNvsAreaProtocol.Area->PowerParticipantPollingRate = mSystemConfiguration.PowerParticipantPollingRate;
2812
2813 mPlatformNvsAreaProtocol.Area->EnableBatteryParticipant = mSystemConfiguration.EnableBatteryParticipant;
2814 mPlatformNvsAreaProtocol.Area->EnableInt3400Device = mSystemConfiguration.EnableInt3400Device;
2815
2816 mPlatformNvsAreaProtocol.Area->EnablePchFivrParticipant = mSystemConfiguration.EnablePchFivrParticipant;
2817
2818 mPlatformNvsAreaProtocol.Area->EnableSen1Participant = mSystemConfiguration.EnableSen1Participant;
2819 mPlatformNvsAreaProtocol.Area->EnableSen2Participant = mSystemConfiguration.EnableSen2Participant;
2820 mPlatformNvsAreaProtocol.Area->EnableSen3Participant = mSystemConfiguration.EnableSen3Participant;
2821 mPlatformNvsAreaProtocol.Area->EnableSen4Participant = mSystemConfiguration.EnableSen4Participant;
2822 mPlatformNvsAreaProtocol.Area->EnableSen5Participant = mSystemConfiguration.EnableSen5Participant;
2823 mPlatformNvsAreaProtocol.Area->EnableDgpuParticipant = mSystemConfiguration.EnableDgpuParticipant;
2824
2825 }
2826
2827 mPlatformNvsAreaProtocol.Area->HebcValue = mSystemConfiguration.HebcValue;
2828
2829 //
2830 // BIOS only version of CTDP. (CTDP without using Intel(R) Dynamic Tuning Technology)
2831 //
2832 if (CpuSetup.ConfigTdpLock == 1 || mSystemConfiguration.EnableDptf == 1) {
2833 mPlatformNvsAreaProtocol.Area->ConfigTdpBios = 0;
2834 } else {
2835 mPlatformNvsAreaProtocol.Area->ConfigTdpBios = CpuSetup.ConfigTdpBios;
2836 }
2837
2838 //
2839 // PECI Access Method
2840 //
2841 mPlatformNvsAreaProtocol.Area->PeciAccessMethod = mSystemConfiguration.PeciAccessMethod;
2842
2843 //
2844 // Wireless support
2845 //
2846 mPlatformNvsAreaProtocol.Area->PowerSharingManagerEnable = mSystemConfiguration.PowerSharingManagerEnable;
2847 mPlatformNvsAreaProtocol.Area->PsmSplcDomainType1 = mSystemConfiguration.PsmSplcDomainType1;
2848 mPlatformNvsAreaProtocol.Area->PsmSplcPowerLimit1 = mSystemConfiguration.PsmSplcPowerLimit1;
2849 mPlatformNvsAreaProtocol.Area->PsmSplcTimeWindow1 = mSystemConfiguration.PsmSplcTimeWindow1;
2850
2851 mPlatformNvsAreaProtocol.Area->PsmDplcDomainType1 = mSystemConfiguration.PsmDplcDomainType1;
2852 mPlatformNvsAreaProtocol.Area->PsmDplcDomainPreference1 = mSystemConfiguration.PsmDplcDomainPreference1;
2853 mPlatformNvsAreaProtocol.Area->PsmDplcPowerLimitIndex1 = mSystemConfiguration.PsmDplcPowerLimitIndex1;
2854 mPlatformNvsAreaProtocol.Area->PsmDplcDefaultPowerLimit1 = mSystemConfiguration.PsmDplcDefaultPowerLimit1;
2855 mPlatformNvsAreaProtocol.Area->PsmDplcDefaultTimeWindow1 = mSystemConfiguration.PsmDplcDefaultTimeWindow1;
2856 mPlatformNvsAreaProtocol.Area->PsmDplcMinimumPowerLimit1 = mSystemConfiguration.PsmDplcMinimumPowerLimit1;
2857 mPlatformNvsAreaProtocol.Area->PsmDplcMaximumPowerLimit1 = mSystemConfiguration.PsmDplcMaximumPowerLimit1;
2858 mPlatformNvsAreaProtocol.Area->PsmDplcMaximumTimeWindow1 = mSystemConfiguration.PsmDplcMaximumTimeWindow1;
2859
2860 mPlatformNvsAreaProtocol.Area->WifiEnable = mSystemConfiguration.WifiEnable;
2861 if (mSystemConfiguration.WifiEnable == 1) {
2862 mPlatformNvsAreaProtocol.Area->WifiDomainType1 = mSystemConfiguration.WifiDomainType1;
2863 mPlatformNvsAreaProtocol.Area->WifiPowerLimit1 = mSystemConfiguration.WifiPowerLimit1;
2864 mPlatformNvsAreaProtocol.Area->WifiTimeWindow1 = mSystemConfiguration.WifiTimeWindow1;
2865 mPlatformNvsAreaProtocol.Area->TRxDelay0 = mSystemConfiguration.TRxDelay0;
2866 mPlatformNvsAreaProtocol.Area->TRxCableLength0 = mSystemConfiguration.TRxCableLength0;
2867 mPlatformNvsAreaProtocol.Area->TRxDelay1 = mSystemConfiguration.TRxDelay1;
2868 mPlatformNvsAreaProtocol.Area->TRxCableLength1 = mSystemConfiguration.TRxCableLength1;
2869 mPlatformNvsAreaProtocol.Area->WrddDomainType1 = mSystemConfiguration.WrddDomainType1;
2870 mPlatformNvsAreaProtocol.Area->WrddCountryIndentifier1 = mSystemConfiguration.WrddCountryIndentifier1;
2871 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarEnable = mSystemConfiguration.WrdsWiFiSarEnable;
2872 mPlatformNvsAreaProtocol.Area->AntennaDiversity = mSystemConfiguration.AntennaDiversity;
2873
2874 if (mPlatformNvsAreaProtocol.Area->WrdsWiFiSarEnable == 1) {
2875 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit1 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit1;
2876 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit2 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit2;
2877 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit3 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit3;
2878 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit4 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit4;
2879 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit5 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit5;
2880 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit6 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit6;
2881 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit7 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit7;
2882 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit8 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit8;
2883 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit9 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit9;
2884 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit10 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit10;
2885 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit11 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit11;
2886 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit12 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit12;
2887 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit13 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit13;
2888 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit14 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit14;
2889 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit15 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit15;
2890 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit16 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit16;
2891 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit17 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit17;
2892 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit18 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit18;
2893 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit19 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit19;
2894 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit20 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit20;
2895 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit21 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit21;
2896 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit22 = mSystemConfiguration.WrdsWiFiSarTxPowerSet1Limit22;
2897
2898 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit1 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit1;
2899 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit2 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit2;
2900 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit3 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit3;
2901 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit4 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit4;
2902 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit5 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit5;
2903 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit6 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit6;
2904 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit7 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit7;
2905 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit8 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit8;
2906 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit9 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit9;
2907 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit10 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit10;
2908 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit11 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit11;
2909 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit12 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit12;
2910 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit13 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit13;
2911 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit14 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit14;
2912 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit15 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit15;
2913 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit16 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit16;
2914 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit17 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit17;
2915 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit18 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit18;
2916 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit19 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit19;
2917 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit20 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit20;
2918 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit21 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit21;
2919 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit22 = mSystemConfiguration.WrdsCdbWiFiSarTxPowerSet1Limit22;
2920 } else {
2921 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit1 = 0x0;
2922 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit2 = 0x0;
2923 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit3 = 0x0;
2924 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit4 = 0x0;
2925 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit5 = 0x0;
2926 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit6 = 0x0;
2927 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit7 = 0x0;
2928 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit8 = 0x0;
2929 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit9 = 0x0;
2930 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit10 = 0x0;
2931 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit11 = 0x0;
2932 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit12 = 0x0;
2933 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit13 = 0x0;
2934 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit14 = 0x0;
2935 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit15 = 0x0;
2936 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit16 = 0x0;
2937 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit17 = 0x0;
2938 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit18 = 0x0;
2939 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit19 = 0x0;
2940 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit20 = 0x0;
2941 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit21 = 0x0;
2942 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarTxPowerSet1Limit22 = 0x0;
2943
2944 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit1 = 0x00;
2945 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit2 = 0x00;
2946 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit3 = 0x00;
2947 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit4 = 0x00;
2948 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit5 = 0x00;
2949 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit6 = 0x00;
2950 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit7 = 0x00;
2951 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit8 = 0x00;
2952 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit9 = 0x00;
2953 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit10 = 0x00;
2954 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit11 = 0x00;
2955 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit12 = 0x00;
2956 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit13 = 0x00;
2957 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit14 = 0x00;
2958 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit15 = 0x00;
2959 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit16 = 0x00;
2960 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit17 = 0x00;
2961 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit18 = 0x00;
2962 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit19 = 0x00;
2963 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit20 = 0x00;
2964 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit21 = 0x00;
2965 mPlatformNvsAreaProtocol.Area->WrdsCdbWiFiSarTxPowerSet1Limit22 = 0x00;
2966 }
2967
2968 mPlatformNvsAreaProtocol.Area->EwrdWiFiDynamicSarEnable = mSystemConfiguration.EwrdWiFiDynamicSarEnable;
2969 mPlatformNvsAreaProtocol.Area->EwrdWiFiDynamicSarRangeSets = mSystemConfiguration.EwrdWiFiDynamicSarRangeSets;
2970 if (mPlatformNvsAreaProtocol.Area->EwrdWiFiDynamicSarEnable == 1) {
2971 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit1 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit1;
2972 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit2 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit2;
2973 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit3 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit3;
2974 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit4 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit4;
2975 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit5 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit5;
2976 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit6 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit6;
2977 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit7 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit7;
2978 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit8 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit8;
2979 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit9 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit9;
2980 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit10 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit10;
2981 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit11 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit11;
2982 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit12 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit12;
2983 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit13 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit13;
2984 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit14 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit14;
2985 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit15 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit15;
2986 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit16 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit16;
2987 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit17 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit17;
2988 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit18 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit18;
2989 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit19 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit19;
2990 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit20 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit20;
2991 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit21 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit21;
2992 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit22 = mSystemConfiguration.EwrdWiFiSarTxPowerSet2Limit22;
2993 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit1 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit1;
2994 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit2 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit2;
2995 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit3 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit3;
2996 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit4 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit4;
2997 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit5 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit5;
2998 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit6 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit6;
2999 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit7 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit7;
3000 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit8 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit8;
3001 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit9 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit9;
3002 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit10 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit10;
3003 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit11 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit11;
3004 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit12 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit12;
3005 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit13 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit13;
3006 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit14 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit14;
3007 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit15 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit15;
3008 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit16 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit16;
3009 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit17 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit17;
3010 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit18 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit18;
3011 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit19 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit19;
3012 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit20 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit20;
3013 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit21 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit21;
3014 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit22 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet2Limit22;
3015
3016 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit1 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit1;
3017 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit2 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit2;
3018 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit3 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit3;
3019 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit4 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit4;
3020 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit5 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit5;
3021 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit6 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit6;
3022 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit7 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit7;
3023 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit8 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit8;
3024 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit9 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit9;
3025 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit10 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit10;
3026 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit11 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit11;
3027 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit12 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit12;
3028 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit13 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit13;
3029 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit14 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit14;
3030 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit15 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit15;
3031 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit16 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit16;
3032 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit17 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit17;
3033 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit18 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit18;
3034 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit19 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit19;
3035 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit20 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit20;
3036 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit21 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit21;
3037 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit22 = mSystemConfiguration.EwrdWiFiSarTxPowerSet3Limit22;
3038 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit1 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit1;
3039 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit2 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit2;
3040 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit3 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit3;
3041 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit4 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit4;
3042 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit5 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit5;
3043 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit6 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit6;
3044 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit7 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit7;
3045 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit8 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit8;
3046 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit9 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit9;
3047 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit10 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit10;
3048 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit11 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit11;
3049 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit12 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit12;
3050 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit13 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit13;
3051 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit14 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit14;
3052 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit15 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit15;
3053 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit16 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit16;
3054 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit17 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit17;
3055 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit18 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit18;
3056 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit19 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit19;
3057 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit20 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit20;
3058 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit21 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit21;
3059 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit22 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet3Limit22;
3060
3061 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit1 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit1;
3062 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit2 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit2;
3063 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit3 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit3;
3064 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit4 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit4;
3065 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit5 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit5;
3066 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit6 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit6;
3067 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit7 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit7;
3068 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit8 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit8;
3069 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit9 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit9;
3070 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit10 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit10;
3071 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit11 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit11;
3072 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit12 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit12;
3073 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit13 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit13;
3074 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit14 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit14;
3075 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit15 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit15;
3076 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit16 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit16;
3077 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit17 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit17;
3078 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit18 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit18;
3079 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit19 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit19;
3080 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit20 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit20;
3081 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit21 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit21;
3082 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit22 = mSystemConfiguration.EwrdWiFiSarTxPowerSet4Limit22;
3083 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit1 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit1;
3084 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit2 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit2;
3085 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit3 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit3;
3086 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit4 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit4;
3087 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit5 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit5;
3088 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit6 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit6;
3089 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit7 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit7;
3090 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit8 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit8;
3091 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit9 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit9;
3092 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit10 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit10;
3093 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit11 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit11;
3094 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit12 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit12;
3095 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit13 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit13;
3096 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit14 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit14;
3097 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit15 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit15;
3098 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit16 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit16;
3099 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit17 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit17;
3100 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit18 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit18;
3101 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit19 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit19;
3102 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit20 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit20;
3103 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit21 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit21;
3104 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit22 = mSystemConfiguration.EwrdCdbWiFiSarTxPowerSet4Limit22;
3105
3106 } else {
3107 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit1 = 0x0;
3108 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit2 = 0x0;
3109 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit3 = 0x0;
3110 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit4 = 0x0;
3111 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit5 = 0x0;
3112 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit6 = 0x0;
3113 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit7 = 0x0;
3114 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit8 = 0x0;
3115 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit9 = 0x0;
3116 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit10 = 0x0;
3117 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit11 = 0x0;
3118 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit12 = 0x0;
3119 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit13 = 0x0;
3120 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit14 = 0x0;
3121 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit15 = 0x0;
3122 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit16 = 0x0;
3123 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit17 = 0x0;
3124 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit18 = 0x0;
3125 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit19 = 0x0;
3126 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit20 = 0x0;
3127 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit21 = 0x0;
3128 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet2Limit22 = 0x0;
3129 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit1 = 0x00;
3130 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit2 = 0x00;
3131 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit3 = 0x00;
3132 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit4 = 0x00;
3133 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit5 = 0x00;
3134 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit6 = 0x00;
3135 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit7 = 0x00;
3136 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit8 = 0x00;
3137 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit9 = 0x00;
3138 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit10 = 0x00;
3139 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit11 = 0x00;
3140 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit12 = 0x00;
3141 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit13 = 0x00;
3142 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit14 = 0x00;
3143 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit15 = 0x00;
3144 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit16 = 0x00;
3145 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit17 = 0x00;
3146 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit18 = 0x00;
3147 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit19 = 0x00;
3148 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit20 = 0x00;
3149 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit21 = 0x00;
3150 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet2Limit22 = 0x00;
3151
3152 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit1 = 0x0;
3153 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit2 = 0x0;
3154 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit3 = 0x0;
3155 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit4 = 0x0;
3156 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit5 = 0x0;
3157 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit6 = 0x0;
3158 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit7 = 0x0;
3159 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit8 = 0x0;
3160 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit9 = 0x0;
3161 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit10 = 0x0;
3162 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit11 = 0x0;
3163 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit12 = 0x0;
3164 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit13 = 0x0;
3165 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit14 = 0x0;
3166 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit15 = 0x0;
3167 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit16 = 0x0;
3168 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit17 = 0x0;
3169 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit18 = 0x0;
3170 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit19 = 0x0;
3171 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit20 = 0x0;
3172 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit21 = 0x0;
3173 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet3Limit22 = 0x0;
3174 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit1 = 0x00;
3175 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit2 = 0x00;
3176 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit3 = 0x00;
3177 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit4 = 0x00;
3178 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit5 = 0x00;
3179 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit6 = 0x00;
3180 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit7 = 0x00;
3181 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit8 = 0x00;
3182 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit9 = 0x00;
3183 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit10 = 0x00;
3184 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit11 = 0x00;
3185 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit12 = 0x00;
3186 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit13 = 0x00;
3187 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit14 = 0x00;
3188 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit15 = 0x00;
3189 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit16 = 0x00;
3190 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit17 = 0x00;
3191 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit18 = 0x00;
3192 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit19 = 0x00;
3193 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit20 = 0x00;
3194 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit21 = 0x00;
3195 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet3Limit22 = 0x00;
3196
3197 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit1 = 0x0;
3198 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit2 = 0x0;
3199 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit3 = 0x0;
3200 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit4 = 0x0;
3201 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit5 = 0x0;
3202 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit6 = 0x0;
3203 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit7 = 0x0;
3204 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit8 = 0x0;
3205 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit9 = 0x0;
3206 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit10 = 0x0;
3207 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit11 = 0x0;
3208 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit12 = 0x0;
3209 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit13 = 0x0;
3210 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit14 = 0x0;
3211 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit15 = 0x0;
3212 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit16 = 0x0;
3213 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit17 = 0x0;
3214 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit18 = 0x0;
3215 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit19 = 0x0;
3216 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit20 = 0x0;
3217 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit21 = 0x0;
3218 mPlatformNvsAreaProtocol.Area->EwrdWiFiSarTxPowerSet4Limit22 = 0x0;
3219 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit1 = 0x00;
3220 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit2 = 0x00;
3221 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit3 = 0x00;
3222 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit4 = 0x00;
3223 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit5 = 0x00;
3224 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit6 = 0x00;
3225 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit7 = 0x00;
3226 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit8 = 0x00;
3227 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit9 = 0x00;
3228 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit10 = 0x00;
3229 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit11 = 0x00;
3230 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit12 = 0x00;
3231 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit13 = 0x00;
3232 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit14 = 0x00;
3233 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit15 = 0x00;
3234 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit16 = 0x00;
3235 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit17 = 0x00;
3236 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit18 = 0x00;
3237 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit19 = 0x00;
3238 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit20 = 0x00;
3239 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit21 = 0x00;
3240 mPlatformNvsAreaProtocol.Area->EwrdCdbWiFiSarTxPowerSet4Limit22 = 0x00;
3241 }
3242 mPlatformNvsAreaProtocol.Area->WiFiDynamicSarAntennaACurrentSet = mSystemConfiguration.WiFiDynamicSarAntennaACurrentSet;
3243 mPlatformNvsAreaProtocol.Area->WiFiDynamicSarAntennaBCurrentSet = mSystemConfiguration.WiFiDynamicSarAntennaBCurrentSet;
3244
3245 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerMax1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerMax1;
3246 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerChainA1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerChainA1;
3247 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerChainB1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerChainB1;
3248 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerMax2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerMax2;
3249 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerChainA2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerChainA2;
3250 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerChainB2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerChainB2;
3251 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerMax3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerMax3;
3252 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerChainA3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerChainA3;
3253 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup1PowerChainB3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup1PowerChainB3;
3254 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerMax1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerMax1;
3255 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerChainA1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerChainA1;
3256 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerChainB1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerChainB1;
3257 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerMax2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerMax2;
3258 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerChainA2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerChainA2;
3259 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerChainB2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerChainB2;
3260 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerMax3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerMax3;
3261 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerChainA3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerChainA3;
3262 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup2PowerChainB3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup2PowerChainB3;
3263 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerMax1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerMax1;
3264 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerChainA1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerChainA1;
3265 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerChainB1 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerChainB1;
3266 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerMax2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerMax2;
3267 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerChainA2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerChainA2;
3268 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerChainB2 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerChainB2;
3269 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerMax3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerMax3;
3270 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerChainA3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerChainA3;
3271 mPlatformNvsAreaProtocol.Area->WgdsWiFiSarDeltaGroup3PowerChainB3 = mSystemConfiguration.WgdsWiFiSarDeltaGroup3PowerChainB3;
3272
3273
3274 mPlatformNvsAreaProtocol.Area->WifiAntGainEnale = mSystemConfiguration.WifiAntGainEnale;
3275 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA1 = mSystemConfiguration.WifiAntGain2400ChainA;
3276 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA2 = mSystemConfiguration.WifiAntGain5150ChainA;
3277 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA3 = mSystemConfiguration.WifiAntGain5350ChainA;
3278 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA4 = mSystemConfiguration.WifiAntGain5470ChainA;
3279 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA5 = mSystemConfiguration.WifiAntGain5725ChainA;
3280 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA6 = mSystemConfiguration.WifiAntGain5945ChainA;
3281 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA7 = mSystemConfiguration.WifiAntGain6165ChainA;
3282 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA8 = mSystemConfiguration.WifiAntGain6405ChainA;
3283 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA9 = mSystemConfiguration.WifiAntGain6525ChainA;
3284 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA10 = mSystemConfiguration.WifiAntGain6705ChainA;
3285 mPlatformNvsAreaProtocol.Area->WifiAntGainChainA11 = mSystemConfiguration.WifiAntGain6865ChainA;
3286 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB1 = mSystemConfiguration.WifiAntGain2400ChainB;
3287 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB2 = mSystemConfiguration.WifiAntGain5150ChainB;
3288 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB3 = mSystemConfiguration.WifiAntGain5350ChainB;
3289 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB4 = mSystemConfiguration.WifiAntGain5470ChainB;
3290 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB5 = mSystemConfiguration.WifiAntGain5725ChainB;
3291 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB6 = mSystemConfiguration.WifiAntGain5945ChainB;
3292 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB7 = mSystemConfiguration.WifiAntGain6165ChainB;
3293 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB8 = mSystemConfiguration.WifiAntGain6405ChainB;
3294 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB9 = mSystemConfiguration.WifiAntGain6525ChainB;
3295 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB10 = mSystemConfiguration.WifiAntGain6705ChainB;
3296 mPlatformNvsAreaProtocol.Area->WifiAntGainChainB11 = mSystemConfiguration.WifiAntGain6865ChainB;
3297 mPlatformNvsAreaProtocol.Area->AxSettingUkraine = mSystemConfiguration.AxSettingUkraine;
3298 mPlatformNvsAreaProtocol.Area->AxModeUkraine = mSystemConfiguration.AxModeUkraine;
3299 mPlatformNvsAreaProtocol.Area->AxSettingRussia = mSystemConfiguration.AxSettingRussia;
3300 mPlatformNvsAreaProtocol.Area->AxModeRussia = mSystemConfiguration.AxModeRussia;
3301
3302 mPlatformNvsAreaProtocol.Area->WifiActiveChannelSrd = mSystemConfiguration.WifiActiveChannelSrd;
3303 mPlatformNvsAreaProtocol.Area->WifiIndonesia5GhzSupport = mSystemConfiguration.WifiIndonesia5GhzSupport;
3304 mPlatformNvsAreaProtocol.Area->WifiUltraHighBandSupport = mSystemConfiguration.WifiUltraHighBandSupport;
3305 mPlatformNvsAreaProtocol.Area->WifiRegulatoryConfigurations = mSystemConfiguration.WifiRegulatoryConfigurations;
3306 mPlatformNvsAreaProtocol.Area->WifiUartConfigurations = mSystemConfiguration.WifiUartConfigurations;
3307 mPlatformNvsAreaProtocol.Area->WifiUnii4 = mSystemConfiguration.WifiUnii4;
3308 mPlatformNvsAreaProtocol.Area->WifiIndoorControl = mSystemConfiguration.WifiIndoorControl;
3309 mPlatformNvsAreaProtocol.Area->WifiTASSelection = mSystemConfiguration.WifiTASSelection;
3310 mPlatformNvsAreaProtocol.Area->WifiTASListEntries = mSystemConfiguration.WifiTASListEntries;
3311 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry1 = mSystemConfiguration.WTASBlockedList[0];
3312 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry2 = mSystemConfiguration.WTASBlockedList[1];
3313 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry3 = mSystemConfiguration.WTASBlockedList[2];
3314 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry4 = mSystemConfiguration.WTASBlockedList[3];
3315 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry5 = mSystemConfiguration.WTASBlockedList[4];
3316 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry6 = mSystemConfiguration.WTASBlockedList[5];
3317 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry7 = mSystemConfiguration.WTASBlockedList[6];
3318 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry8 = mSystemConfiguration.WTASBlockedList[7];
3319 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry9 = mSystemConfiguration.WTASBlockedList[8];
3320 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry10 = mSystemConfiguration.WTASBlockedList[9];
3321 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry11 = mSystemConfiguration.WTASBlockedList[10];
3322 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry12 = mSystemConfiguration.WTASBlockedList[11];
3323 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry13 = mSystemConfiguration.WTASBlockedList[12];
3324 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry14 = mSystemConfiguration.WTASBlockedList[13];
3325 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry15 = mSystemConfiguration.WTASBlockedList[14];
3326 mPlatformNvsAreaProtocol.Area->WTASBlockedListEntry16 = mSystemConfiguration.WTASBlockedList[15];
3327
3328
3329 mPlatformNvsAreaProtocol.Area->BluetoothSar = mSystemConfiguration.BluetoothSar;
3330 if (mPlatformNvsAreaProtocol.Area->BluetoothSar == 1) {
3331 mPlatformNvsAreaProtocol.Area->BluetoothSarBr = mSystemConfiguration.BluetoothSarBr;
3332 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr2 = mSystemConfiguration.BluetoothSarEdr2;
3333 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr3 = mSystemConfiguration.BluetoothSarEdr3;
3334 mPlatformNvsAreaProtocol.Area->BluetoothSarLe = mSystemConfiguration.BluetoothSarLe;
3335 mPlatformNvsAreaProtocol.Area->BluetoothSarLe2Mhz = mSystemConfiguration.BluetoothSarLe2Mhz;
3336 mPlatformNvsAreaProtocol.Area->BluetoothSarLeLr = mSystemConfiguration.BluetoothSarLeLr;
3337 } else {
3338 mPlatformNvsAreaProtocol.Area->BluetoothSarBr = 0x0;
3339 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr2 = 0x0;
3340 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr3 = 0x0;
3341 mPlatformNvsAreaProtocol.Area->BluetoothSarLe = 0x0;
3342 mPlatformNvsAreaProtocol.Area->BluetoothSarLe2Mhz = 0x0;
3343 mPlatformNvsAreaProtocol.Area->BluetoothSarLeLr = 0x0;
3344 }
3345 mPlatformNvsAreaProtocol.Area->CnvExtClock = mSystemConfiguration.CnvExtClock;
3346 }
3347
3348 mPlatformNvsAreaProtocol.Area->BtTileMode = mSystemConfiguration.BtTileMode;
3349 mPlatformNvsAreaProtocol.Area->TileS0 = mSystemConfiguration.TileS0;
3350 mPlatformNvsAreaProtocol.Area->TileS0ix = mSystemConfiguration.TileS0ix;
3351 mPlatformNvsAreaProtocol.Area->TileS4 = mSystemConfiguration.TileS4;
3352 mPlatformNvsAreaProtocol.Area->TileS5 = mSystemConfiguration.TileS5;
3353
3354 #if (FixedPcdGetBool(PcdAdlLpSupport) == 1)
3355 mPlatformNvsAreaProtocol.Area->BtLedConfig = mSystemConfiguration.BtLedConfig;
3356 mPlatformNvsAreaProtocol.Area->BtLedPulseDuration = mSystemConfiguration.BtLedPulseDuration;
3357 mPlatformNvsAreaProtocol.Area->BtLedPulseInterval = mSystemConfiguration.BtLedPulseInterval;
3358 #else
3359 mPlatformNvsAreaProtocol.Area->SpecialLedConfig = mSystemConfiguration.SpecialLedConfig;
3360 mPlatformNvsAreaProtocol.Area->LedDuration = mSystemConfiguration.LedDuration;
3361 mPlatformNvsAreaProtocol.Area->AirplaneMode = mSystemConfiguration.AirplaneMode;
3362 #endif
3363
3364 mPlatformNvsAreaProtocol.Area->SystemTimeAndAlarmSource = mSystemConfiguration.SystemTimeAndAlarmSource;
3365 mPlatformNvsAreaProtocol.Area->CoExistenceManager = mSystemConfiguration.CoExistenceManager;
3366 mPlatformNvsAreaProtocol.Area->XdciFnEnable = mPchSetup.PchXdciSupport;
3367 //
3368 // Initilize platform ID in Global NVS Area
3369 //
3370 mPlatformNvsAreaProtocol.Area->PlatformId = (UINT8) PcdGet16 (PcdBoardId);
3371 mPlatformNvsAreaProtocol.Area->GenerationId = PcdGet8 (PcdPlatformGeneration);
3372 mPlatformNvsAreaProtocol.Area->PlatformFlavor = PcdGet8 (PcdPlatformFlavor);
3373 mPlatformNvsAreaProtocol.Area->BoardRev = PcdGet16 (PcdBoardRev);
3374 mPlatformNvsAreaProtocol.Area->BoardType = PcdGet8 (PcdBoardType);
3375
3376
3377 mPlatformNvsAreaProtocol.Area->Rtd3Support = mSystemConfiguration.Rtd3Support;
3378 mPlatformNvsAreaProtocol.Area->Rtd3P0dl = mSystemConfiguration.Rtd3P0dl;
3379 mPlatformNvsAreaProtocol.Area->Rtd3AudioDelay = mSystemConfiguration.Rtd3AudioDelay;
3380 mPlatformNvsAreaProtocol.Area->Rtd3SensorHub = mSystemConfiguration.Rtd3SensorHub;
3381 mPlatformNvsAreaProtocol.Area->Rtd3TouchPanelDelay = mSystemConfiguration.Rtd3TouchPanelDelay;
3382 mPlatformNvsAreaProtocol.Area->Rtd3TouchPadDelay = mSystemConfiguration.Rtd3TouchPadDelay;
3383 mPlatformNvsAreaProtocol.Area->VRRampUpDelay = mSystemConfiguration.VRRampUpDelay;
3384 mPlatformNvsAreaProtocol.Area->PstateCapping = mSystemConfiguration.PstateCapping;
3385 mPlatformNvsAreaProtocol.Area->UsbPowerResourceTest = (mSystemConfiguration.Rtd3UsbPt2 << 4)
3386 | mSystemConfiguration.Rtd3UsbPt1;
3387 mPlatformNvsAreaProtocol.Area->SensorStandby = mSystemConfiguration.SensorStandby;
3388 mPlatformNvsAreaProtocol.Area->Rtd3Config0 = ((mSystemConfiguration.WwanEnable && (mSystemConfiguration.Rtd3WWAN != 0) ? 1:0) << 7)
3389 | (mSystemConfiguration.Rtd3I2CTouchPanel << 4); // Applicable for SKL SDS RTD3 SIP only
3390 mPlatformNvsAreaProtocol.Area->Rtd3Config1 = (mSystemConfiguration.Rtd3RemapCR3 << 10)
3391 | (mSystemConfiguration.Rtd3RemapCR2 << 9)
3392 | (mSystemConfiguration.Rtd3RemapCR1 << 8)
3393 | (mSystemConfiguration.Rtd3SataPort7 << 7)
3394 | (mSystemConfiguration.Rtd3SataPort6 << 6)
3395 | (mSystemConfiguration.Rtd3SataPort5 << 5)
3396 | (mSystemConfiguration.Rtd3SataPort4 << 4)
3397 | (mSystemConfiguration.Rtd3SataPort3 << 3)
3398 | (mSystemConfiguration.Rtd3SataPort2 << 2)
3399 | (mSystemConfiguration.Rtd3SataPort1 << 1)
3400 | mSystemConfiguration.Rtd3SataPort0;
3401 mPlatformNvsAreaProtocol.Area->StorageRtd3Support = mSystemConfiguration.StorageRtd3Support;
3402
3403 //
3404 // Enable PowerState
3405 //
3406 mPlatformNvsAreaProtocol.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c
3407
3408 //
3409 // These don't have setup controls yet
3410 //
3411 mPlatformNvsAreaProtocol.Area->IdeMode = 0;
3412
3413 if (PcdGetBool (PcdEcPresent) == TRUE) {
3414 //
3415 // Call EC lib to get PCIe dock status
3416 //
3417 PortData = 0;
3418 Status = GetPcieDockStatus (&PortData);
3419
3420 //
3421 // the bit0 is PCIe Dock Status, 1 = docked
3422 //
3423 mPlatformNvsAreaProtocol.Area->PcieDockStatus = (PortData & 1);
3424 }
3425
3426 mPlatformNvsAreaProtocol.Area->NativePCIESupport = mSystemConfiguration.PciExpNative;
3427 mPlatformNvsAreaProtocol.Area->PlatformCpuId = (CpuidVersionInfoEax.Uint32 & 0x0FFFFF);
3428
3429 //
3430 // Create an End of DXE event.
3431 //
3432 Status = gBS->CreateEventEx (
3433 EVT_NOTIFY_SIGNAL,
3434 TPL_CALLBACK,
3435 AcpiEndOfDxeEvent,
3436 NULL,
3437 &gEfiEndOfDxeEventGroupGuid,
3438 &EndOfDxeEvent
3439 );
3440 ASSERT_EFI_ERROR (Status);
3441
3442 //
3443 // SIO related option
3444 //
3445 Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) &mCpuIo);
3446 ASSERT_EFI_ERROR (Status);
3447
3448 mPlatformNvsAreaProtocol.Area->WPCN381U = PLATFORM_NVS_DEVICE_DISABLE;
3449
3450 mPlatformNvsAreaProtocol.Area->DockedSioPresent = PLATFORM_NVS_DEVICE_DISABLE;
3451 mPlatformNvsAreaProtocol.Area->DockComA = PLATFORM_NVS_DEVICE_DISABLE;
3452 mPlatformNvsAreaProtocol.Area->DockComB = PLATFORM_NVS_DEVICE_DISABLE;
3453 mPlatformNvsAreaProtocol.Area->DockLpt = PLATFORM_NVS_DEVICE_DISABLE;
3454 mPlatformNvsAreaProtocol.Area->DockFdc = PLATFORM_NVS_DEVICE_DISABLE;
3455
3456 //
3457 // Check ID for NS87393 SIO, which is connected to Thimble Peak.
3458 //
3459 PortData = 0x20;
3460 Status = mCpuIo->Io.Write (
3461 mCpuIo,
3462 EfiCpuIoWidthUint8,
3463 NAT_CONFIG_INDEX,
3464 1,
3465 &PortData
3466 );
3467 ASSERT_EFI_ERROR (Status);
3468
3469 Status = mCpuIo->Io.Read (
3470 mCpuIo,
3471 EfiCpuIoWidthUint8,
3472 NAT_CONFIG_DATA,
3473 1,
3474 &PortData
3475 );
3476 ASSERT_EFI_ERROR (Status);
3477
3478 if (PortData == 0xEA) {
3479 mPlatformNvsAreaProtocol.Area->DockedSioPresent = PLATFORM_NVS_DEVICE_ENABLE;
3480 mPlatformNvsAreaProtocol.Area->DockComA = PLATFORM_NVS_DEVICE_ENABLE;
3481 mPlatformNvsAreaProtocol.Area->DockComB = PLATFORM_NVS_DEVICE_ENABLE;
3482 }
3483
3484 if (mPlatformNvsAreaProtocol.Area->DockedSioPresent != PLATFORM_NVS_DEVICE_ENABLE) {
3485 //
3486 // Check ID for SIO WPCN381U
3487 //
3488 Status = mCpuIo->Io.Read (
3489 mCpuIo,
3490 EfiCpuIoWidthUint8,
3491 WPCN381U_CONFIG_INDEX,
3492 1,
3493 &PortData
3494 );
3495 ASSERT_EFI_ERROR (Status);
3496 if (PortData != 0xFF) {
3497 PortData = 0x20;
3498 Status = mCpuIo->Io.Write (
3499 mCpuIo,
3500 EfiCpuIoWidthUint8,
3501 WPCN381U_CONFIG_INDEX,
3502 1,
3503 &PortData
3504 );
3505 ASSERT_EFI_ERROR (Status);
3506 Status = mCpuIo->Io.Read (
3507 mCpuIo,
3508 EfiCpuIoWidthUint8,
3509 WPCN381U_CONFIG_DATA,
3510 1,
3511 &PortData
3512 );
3513 ASSERT_EFI_ERROR (Status);
3514 if ((PortData == WPCN381U_CHIP_ID) || (PortData == WDCP376_CHIP_ID)) {
3515 mPlatformNvsAreaProtocol.Area->WPCN381U = PLATFORM_NVS_DEVICE_ENABLE;
3516 }
3517 }
3518 }
3519
3520 //
3521 // Enable APIC
3522 //
3523 mPlatformNvsAreaProtocol.Area->ApicEnable = PLATFORM_NVS_DEVICE_ENABLE;
3524
3525 //
3526 // EC function
3527 //
3528 if (PcdGetBool (PcdEcPresent) == TRUE) {
3529 mPlatformNvsAreaProtocol.Area->EcAvailable = TRUE;
3530 mPlatformNvsAreaProtocol.Area->EcLowPowerMode = mSystemConfiguration.EcLowPowerMode;
3531 mPlatformNvsAreaProtocol.Area->EcSmiGpioPin = PcdGet32(PcdEcSmiGpio);
3532 mPlatformNvsAreaProtocol.Area->EcLowPowerModeGpioPin = PcdGet32(PcdEcLowPowerExitGpio);
3533 } else {
3534 mPlatformNvsAreaProtocol.Area->EcAvailable = FALSE;
3535 mPlatformNvsAreaProtocol.Area->EcLowPowerMode = 0;
3536 mPlatformNvsAreaProtocol.Area->EcSmiGpioPin = 0;
3537 mPlatformNvsAreaProtocol.Area->EcLowPowerModeGpioPin = 0;
3538 }
3539 mPlatformNvsAreaProtocol.Area->EnableVoltageMargining = PcdGetBool (PcdEnableVoltageMargining);
3540
3541 //
3542 // Comms Hub Support Enable/Disable
3543 //
3544 mPlatformNvsAreaProtocol.Area->CommsHubEnable = mMeSetup.CommsHubEnable;
3545
3546 mPlatformNvsAreaProtocol.Area->IuerButtonEnable = SaSetup.IuerButtonEnable;
3547
3548 //
3549 // Enable 10sec Power Button Override only if CS is enabled.
3550 //
3551 if (mSystemConfiguration.LowPowerS0Idle == 1) {
3552 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable |= BIT0; // Enable 10sec Power Button OVR.
3553 if (mSystemConfiguration.HidEventFilterDriverEnable) {
3554 mPlatformNvsAreaProtocol.Area->HidEventFilterEnable = 0x01; // Enable Hid Event Filter Driver
3555 } else {
3556 mPlatformNvsAreaProtocol.Area->HidEventFilterEnable = 0x00; // Disable Hid Event Filter Driver
3557 }
3558 } else {
3559 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable &= ~(BIT0); // Disable 10sec Power Button OVR.
3560 //
3561 // HID Event Filter Enable/Disable
3562 //
3563 mPlatformNvsAreaProtocol.Area->HidEventFilterEnable = mSystemConfiguration.HidEventFilterDriverEnable;
3564 }
3565 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable |= (SaSetup.SlateIndicatorRT << 3);
3566 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable |= (SaSetup.DockIndicatorRT << 4);
3567 mPlatformNvsAreaProtocol.Area->IuerConvertibleEnable = SaSetup.IuerConvertibleEnable;
3568 mPlatformNvsAreaProtocol.Area->IuerDockEnable = SaSetup.IuerDockEnable;
3569
3570 mPlatformNvsAreaProtocol.Area->VirtualGpioButtonSxBitmask = 0x00;
3571 mPlatformNvsAreaProtocol.Area->VirtualGpioButtonSxBitmask |= SaSetup.SlateIndicatorSx << 6;
3572 mPlatformNvsAreaProtocol.Area->VirtualGpioButtonSxBitmask |= SaSetup.DockIndicatorSx << 7;
3573
3574 //
3575 // Low Power S0 Idle - Enabled/Disabled
3576 //
3577 mPlatformNvsAreaProtocol.Area->LowPowerS0Idle = mSystemConfiguration.LowPowerS0Idle;
3578 mPlatformNvsAreaProtocol.Area->PseudoG3State = mSystemConfiguration.PseudoG3State;
3579 mPlatformNvsAreaProtocol.Area->PuisEnable = mSystemConfiguration.PuisEnable;
3580
3581 //
3582 // WWAN GPIO pin configuration
3583 //
3584 mPlatformNvsAreaProtocol.Area->WwanRtd3Option = mSystemConfiguration.Rtd3WWAN;
3585 mPlatformNvsAreaProtocol.Area->WwanPerstGpio = PcdGet32 (PcdWwanPerstGpio);
3586 mPlatformNvsAreaProtocol.Area->WwanPerstGpioPolarity = PcdGetBool (PcdWwanPerstGpioPolarity);
3587 mPlatformNvsAreaProtocol.Area->WwanBbrstGpio = PcdGet32 (PcdWwanBbrstGpio);
3588 mPlatformNvsAreaProtocol.Area->WwanBbrstGpioPolarity = PcdGetBool (PcdWwanBbrstGpioPolarity);
3589 mPlatformNvsAreaProtocol.Area->WwanWakeGpio = PcdGet32 (PcdWwanWakeGpio);
3590 mPlatformNvsAreaProtocol.Area->WwanFullCardPowerOffGpio = PcdGet32 (PcdWwanFullCardPowerOffGpio);
3591 mPlatformNvsAreaProtocol.Area->WwanFullCardPowerOffGpioPolarity = PcdGetBool (PcdWwanFullCardPowerOffGpioPolarity);
3592 mPlatformNvsAreaProtocol.Area->WwanSourceClock = PcdGet8 (PcdWwanSourceClock);
3593 mPlatformNvsAreaProtocol.Area->WwanRootPortNumber = PcdGet8 (PcdWwanRootPortNumber);
3594 mPlatformNvsAreaProtocol.Area->PcieDeviceOnWwanSlot = PcdGetBool (PcdPcieDeviceOnWwanSlot);
3595 mPlatformNvsAreaProtocol.Area->WwanFwFlashDevice = mSystemConfiguration.WwanFwFlashDevice;
3596 mPlatformNvsAreaProtocol.Area->WccdEnable = mSystemConfiguration.WirelessCnvConfigDevice;
3597 mPlatformNvsAreaProtocol.Area->WwanEnable = PcdGet8 (PcdPcieWwanEnable);
3598 mPlatformNvsAreaProtocol.Area->WwanTOn2ResDelayMs = PcdGet16 (PcdBoardWwanTOn2ResDelayMs);
3599 mPlatformNvsAreaProtocol.Area->WwanTOnRes2PerDelayMs = PcdGet16 (PcdBoardWwanTOnRes2PerDelayMs);
3600 mPlatformNvsAreaProtocol.Area->WwanTOnPer2PdsDelayMs = PcdGet16 (PcdBoardWwanTOnPer2PdsDelayMs);
3601 mPlatformNvsAreaProtocol.Area->WwanTRes2OffDelayMs = PcdGet16 (PcdBoardWwanTRes2OffDelayMs);
3602 mPlatformNvsAreaProtocol.Area->WwanTOffDisDelayMs = PcdGet16 (PcdBoardWwanTOffDisDelayMs);
3603 mPlatformNvsAreaProtocol.Area->WwanTResTogDelayMs = PcdGet16 (PcdBoardWwanTResTogDelayMs);
3604 mPlatformNvsAreaProtocol.Area->WwanTRes2PdsDelayMs = PcdGet16 (PcdBoardWwanTRes2PdsDelayMs);
3605 mPlatformNvsAreaProtocol.Area->WwanTPer2ResDelayMs = PcdGet16 (PcdBoardWwanTPer2ResDelayMs);
3606 mPlatformNvsAreaProtocol.Area->WwanOemSvid = mSystemConfiguration.WwanOemSvid;
3607 mPlatformNvsAreaProtocol.Area->WwanSvidTimeout = mSystemConfiguration.WwanSvidTimeout;
3608
3609 // SD card D3 cold support
3610 mPlatformNvsAreaProtocol.Area->Rp08D3ColdDisable = mSystemConfiguration.Rp08D3ColdDisable;
3611 mPlatformNvsAreaProtocol.Area->Rp08D3ColdSupport = 0;
3612
3613 //Wake on LAN AIC card support
3614 mPlatformNvsAreaProtocol.Area->Rp08WakeReworkDone = mSystemConfiguration.Rp08WakeReworkDone;
3615
3616 //
3617 // PCH PCIe x4 Slot 1 GPIO pin configuration
3618 //
3619 mPlatformNvsAreaProtocol.Area->PcieSlot1WakeGpio = PcdGet32 (PcdPcieSlot1WakeGpioPin);
3620 mPlatformNvsAreaProtocol.Area->PcieSlot1PowerEnableGpio = PcdGet32(PcdPcieSlot1PwrEnableGpioNo);
3621 mPlatformNvsAreaProtocol.Area->PcieSlot1PowerEnableGpioPolarity = PcdGetBool(PcdPcieSlot1PwrEnableGpioPolarity);
3622 mPlatformNvsAreaProtocol.Area->PcieSlot1RstGpio = PcdGet32(PcdPcieSlot1HoldRstGpioNo);
3623 mPlatformNvsAreaProtocol.Area->PcieSlot1RstGpioPolarity = PcdGetBool(PcdPcieSlot1HoldRstGpioPolarity);
3624 mPlatformNvsAreaProtocol.Area->PcieSlot1RpNumber = PcdGet8 (PcdPcieSlot1RootPort);
3625 mPlatformNvsAreaProtocol.Area->Dg1VramSRGpio = PcdGet32 (PcdDg1VramSRGpio);
3626 mPlatformNvsAreaProtocol.Area->DisplayMuxGpioNo = PcdGet32 (PcdDisplayMuxGpioNo);
3627
3628 //
3629 // PCH PCIe x4 Slot 2 GPIO pin configuration
3630 //
3631 mPlatformNvsAreaProtocol.Area->PcieSlot2WakeGpio = PcdGet32(PcdPcieSlot2WakeGpioPin);
3632 mPlatformNvsAreaProtocol.Area->PcieSlot2PowerEnableGpio = PcdGet32(PcdPchPCIeSlot2PwrEnableGpioNo);
3633 mPlatformNvsAreaProtocol.Area->PcieSlot2PowerEnableGpioPolarity = PcdGetBool(PcdPchPCIeSlot2PwrEnableGpioPolarity);
3634 mPlatformNvsAreaProtocol.Area->PcieSlot2RstGpio = PcdGet32(PcdPchPCIeSlot2RstGpioNo);
3635 mPlatformNvsAreaProtocol.Area->PcieSlot2RstGpioPolarity = PcdGetBool(PcdPchPCIeSlot2RstGpioPolarity);
3636 mPlatformNvsAreaProtocol.Area->PcieSlot2RpNumber = PcdGet8(PcdPcieSlot2RootPort);
3637
3638 //
3639 // PCH PCIe x2 Slot 3 GPIO pin configuration
3640 //
3641 mPlatformNvsAreaProtocol.Area->PcieSlot3WakeGpio = PcdGet32(PcdPcieSlot3WakeGpioPin);
3642 mPlatformNvsAreaProtocol.Area->PcieSlot3PowerEnableGpio = PcdGet32(PcdPchPCIeSlot3PwrEnableGpioNo);
3643 mPlatformNvsAreaProtocol.Area->PcieSlot3PowerEnableGpioPolarity = PcdGetBool(PcdPchPCIeSlot3PwrEnableGpioPolarity);
3644 mPlatformNvsAreaProtocol.Area->PcieSlot3RstGpio = PcdGet32(PcdPchPCIeSlot3RstGpioNo);
3645 mPlatformNvsAreaProtocol.Area->PcieSlot3RstGpioPolarity = PcdGetBool(PcdPchPCIeSlot3RstGpioPolarity);
3646 mPlatformNvsAreaProtocol.Area->PcieSlot3RpNumber = PcdGet8(PcdPcieSlot3RootPort);
3647
3648 //
3649 // CPU M.2 SSD GPIO pin configuration
3650 //
3651 mPlatformNvsAreaProtocol.Area->M2Ssd2PowerEnableGpio = PcdGet32(PcdPcieSsd2PwrEnableGpioNo);
3652 mPlatformNvsAreaProtocol.Area->M2Ssd2PowerEnableGpioPolarity = PcdGetBool(PcdPcieSsd2PwrEnableGpioPolarity);
3653 mPlatformNvsAreaProtocol.Area->M2Ssd2RstGpio = PcdGet32(PcdPcieSsd2RstGpioNo);
3654 mPlatformNvsAreaProtocol.Area->M2Ssd2RstGpioPolarity = PcdGetBool(PcdPcieSsd2RstGpioPolarity);
3655
3656 //
3657 // CPU M.2 SSD2 GPIO pin configuration
3658 //
3659 mPlatformNvsAreaProtocol.Area->M2Ssd3PowerEnableGpio = PcdGet32(PcdPcieSsd3PwrEnableGpioNo);
3660 mPlatformNvsAreaProtocol.Area->M2Ssd3PowerEnableGpioPolarity = PcdGetBool(PcdPcieSsd3PwrEnableGpioPolarity);
3661 mPlatformNvsAreaProtocol.Area->M2Ssd3RstGpio = PcdGet32(PcdPcieSsd3RstGpioNo);
3662 mPlatformNvsAreaProtocol.Area->M2Ssd3RstGpioPolarity = PcdGetBool(PcdPcieSsd3RstGpioPolarity);
3663
3664 //
3665 // CPU M.2 DG GPIO pin Configuration
3666 //
3667 mPlatformNvsAreaProtocol.Area->M2DG2PowerEnableGpio = PcdGet32(PcdPcieDG2PwrEnableGpioNo);
3668 mPlatformNvsAreaProtocol.Area->M2DG2PowerEnableGpioPolarity = PcdGetBool(PcdPcieDG2PwrEnableGpioPolarity);
3669 mPlatformNvsAreaProtocol.Area->M2DG2RstGpio= PcdGet32(PcdPcieDG2RstGpioNo);
3670 mPlatformNvsAreaProtocol.Area->M2DG2RstGpioPolarity = PcdGetBool(PcdPcieDG2RstGpioPolarity);
3671 mPlatformNvsAreaProtocol.Area->M2DG2WakeGpioPin = PcdGet32(PcdPcieDG2WakeGpioPin);
3672
3673 //
3674 // PCH M.2 SSD GPIO pin configuration
3675 //
3676 mPlatformNvsAreaProtocol.Area->PchM2SsdPowerEnableGpio = PcdGet32(PcdPchSsd1PwrEnableGpioNo);
3677 mPlatformNvsAreaProtocol.Area->PchM2SsdPowerEnableGpioPolarity = PcdGetBool(PcdPchSsd1PwrEnableGpioPolarity);
3678 mPlatformNvsAreaProtocol.Area->PchM2SsdRstGpio = PcdGet32(PcdPchSsd1RstGpioNo);
3679 mPlatformNvsAreaProtocol.Area->PchM2SsdRstGpioPolarity = PcdGetBool(PcdPchSsd1RstGpioPolarity);
3680
3681 //
3682 // PCH M.2 SSD2 GPIO pin configuration
3683 //
3684 mPlatformNvsAreaProtocol.Area->PchM2Ssd2PowerEnableGpio = PcdGet32(PcdPchSsd2PwrEnableGpioNo);
3685 mPlatformNvsAreaProtocol.Area->PchM2Ssd2PowerEnableGpioPolarity = PcdGetBool(PcdPchSsd2PwrEnableGpioPolarity);
3686 mPlatformNvsAreaProtocol.Area->PchM2Ssd2RstGpio = PcdGet32(PcdPchSsd2RstGpioNo);
3687 mPlatformNvsAreaProtocol.Area->PchM2Ssd2RstGpioPolarity = PcdGetBool(PcdPchSsd2RstGpioPolarity);
3688
3689 //
3690 // PCH M.2 SSD3 GPIO pin configuration
3691 //
3692 mPlatformNvsAreaProtocol.Area->PchM2Ssd3PowerEnableGpio = PcdGet32(PcdPchSsd3PwrEnableGpioNo);
3693 mPlatformNvsAreaProtocol.Area->PchM2Ssd3PowerEnableGpioPolarity = PcdGetBool(PcdPchSsd3PwrEnableGpioPolarity);
3694 mPlatformNvsAreaProtocol.Area->PchM2Ssd3RstGpio = PcdGet32(PcdPchSsd3RstGpioNo);
3695 mPlatformNvsAreaProtocol.Area->PchM2Ssd3RstGpioPolarity = PcdGetBool(PcdPchSsd3RstGpioPolarity);
3696
3697 //
3698 // Onboard MR 1 GPIO pin configuration (for ADL S8 only)
3699 //
3700 mPlatformNvsAreaProtocol.Area->OnBoardMr1PowerEnableGpio = PcdGet32 (PcdOnBoardMr1PowerEnableGpioNo);
3701 mPlatformNvsAreaProtocol.Area->OnBoardMr1PowerEnableGpioPolarity = PcdGetBool (PcdOnBoardMr1PowerEnableGpioPolarity);
3702 mPlatformNvsAreaProtocol.Area->OnBoardMr1RstGpio = PcdGet32 (PcdOnBoardMr1RstGpioNo);
3703 mPlatformNvsAreaProtocol.Area->OnBoardMr1RstGpioPolarity = PcdGetBool (PcdOnBoardMr1RstGpioPolarity);
3704 mPlatformNvsAreaProtocol.Area->OnBoardMr1WakeGpio = PcdGet32 (PcdOnBoardMr1WakeGpioPin);
3705 mPlatformNvsAreaProtocol.Area->OnBoardMr1RpNumber = PcdGet8 (PcdOnBoardMr1RootPort);
3706
3707 //
3708 // Onboard MR 2 GPIO pin configuration
3709 //
3710 mPlatformNvsAreaProtocol.Area->OnBoardMr2PowerEnableGpio = PcdGet32(PcdOnBoardMr2PowerEnableGpioNo);
3711 mPlatformNvsAreaProtocol.Area->OnBoardMr2PowerEnableGpioPolarity = PcdGetBool(PcdOnBoardMr2PowerEnableGpioPolarity);
3712 mPlatformNvsAreaProtocol.Area->OnBoardMr2RstGpio = PcdGet32(PcdOnBoardMr2RstGpioNo);
3713 mPlatformNvsAreaProtocol.Area->OnBoardMr2RstGpioPolarity = PcdGetBool(PcdOnBoardMr2RstGpioPolarity);
3714 mPlatformNvsAreaProtocol.Area->OnBoardMr2WakeGpio = PcdGet32(PcdOnBoardMr2WakeGpioPin);
3715 mPlatformNvsAreaProtocol.Area->OnBoardMr2RpNumber = PcdGet8(PcdOnBoardMr2RootPort);
3716
3717 //
3718 // PCH Sata ports GPIO pin configuration
3719 //
3720 mPlatformNvsAreaProtocol.Area->SataPortPowerEnableGpio = PcdGet32(PcdPchSataPortPwrEnableGpioNo);
3721 mPlatformNvsAreaProtocol.Area->SataPortPowerEnableGpioPolarity = PcdGetBool(PcdPchSataPortPwrEnableGpioPolarity);
3722
3723 //
3724 // CPU PEG1 GPIO pin configuration
3725 //
3726 mPlatformNvsAreaProtocol.Area->PegSlot1PwrEnableGpioNo = PcdGet32 (PcdPegSlot1PwrEnableGpioNo);
3727 mPlatformNvsAreaProtocol.Area->PegSlot1PwrEnableGpioPolarity = PcdGetBool (PcdPegSlot1PwrEnableGpioPolarity);
3728 mPlatformNvsAreaProtocol.Area->PegSlot1RstGpioNo = PcdGet32 (PcdPegSlot1RstGpioNo);
3729 mPlatformNvsAreaProtocol.Area->PegSlot1RstGpioPolarity = PcdGetBool (PcdPegSlot1RstGpioPolarity);
3730 mPlatformNvsAreaProtocol.Area->PegSlot1WakeGpioPin = PcdGet32 (PcdPegSlot1WakeGpioPin);
3731 mPlatformNvsAreaProtocol.Area->PegSlot1RootPort = PcdGet8 (PcdPegSlot1RootPort);
3732
3733 //
3734 // CPU PEG2 GPIO pin configuration
3735 //
3736 mPlatformNvsAreaProtocol.Area->PegSlot2PwrEnableGpioNo = PcdGet32 (PcdPegSlot2PwrEnableGpioNo);
3737 mPlatformNvsAreaProtocol.Area->PegSlot2PwrEnableGpioPolarity = PcdGetBool (PcdPegSlot2PwrEnableGpioPolarity);
3738 mPlatformNvsAreaProtocol.Area->PegSlot2RstGpioNo = PcdGet32 (PcdPegSlot2RstGpioNo);
3739 mPlatformNvsAreaProtocol.Area->PegSlot2RstGpioPolarity = PcdGetBool (PcdPegSlot2RstGpioPolarity);
3740 mPlatformNvsAreaProtocol.Area->PegSlot2WakeGpioPin = PcdGet32 (PcdPegSlot2WakeGpioPin);
3741 mPlatformNvsAreaProtocol.Area->PegSlot2RootPort = PcdGet8 (PcdPegSlot2RootPort);
3742
3743 //
3744 // Foxville I225 Lan GPIO pin configuration
3745 //
3746 mPlatformNvsAreaProtocol.Area->FoxLanWakeGpio = PcdGet32(PcdFoxLanWakeGpio);
3747 mPlatformNvsAreaProtocol.Area->FoxLanDisableNGpio = PcdGet32(PcdFoxLanDisableNGpio);
3748 mPlatformNvsAreaProtocol.Area->FoxLanDisableNGpioPolarity = PcdGetBool(PcdFoxLanDisableNGpioPolarity);
3749 mPlatformNvsAreaProtocol.Area->FoxLanRstGpio = PcdGet32(PcdFoxLanResetGpio);
3750 mPlatformNvsAreaProtocol.Area->FoxLanRstGpioPolarity = PcdGetBool(PcdFoxLanResetGpioPolarity);
3751 mPlatformNvsAreaProtocol.Area->FoxLanSupport = mPchSetup.FoxvilleLanSupport;
3752 mPlatformNvsAreaProtocol.Area->FoxLanRpNumber = PcdGet8(PcdFoxlanRootPortNumber);
3753 //
3754 // Touch Pad and Panel GPIO pin configuration
3755 //
3756 mPlatformNvsAreaProtocol.Area->TouchpadIrqGpio = PcdGet32(PcdTouchpadIrqGpio);
3757 mPlatformNvsAreaProtocol.Area->TouchpadIrqGpioPolarity = PcdGetBool(PcdTouchpadIrqGpioPolarity);
3758 mPlatformNvsAreaProtocol.Area->TouchpanelIrqGpio = PcdGet32(PcdTouchpanelIrqGpio);
3759 mPlatformNvsAreaProtocol.Area->TouchpanelPowerEnableGpio = PcdGet32(PcdTouchpanelPwrEnableGpio);
3760 mPlatformNvsAreaProtocol.Area->TouchpanelPowerRstGpio = PcdGet32(PcdTouchpanelRstGpio);
3761 mPlatformNvsAreaProtocol.Area->TouchpanelIrqGpioPolarity = PcdGetBool(PcdTouchpanelIrqGpioPolarity);
3762 mPlatformNvsAreaProtocol.Area->TouchpanelPowerEnableGpioPolarity = PcdGetBool(PcdTouchpanelPwrEnableGpioPolarity);
3763 mPlatformNvsAreaProtocol.Area->TouchpanelPowerRstGpioPolarity = PcdGetBool(PcdTouchpanelRstGpioPolarity);
3764 mPlatformNvsAreaProtocol.Area->Touchpanel1IrqGpio = PcdGet32(PcdTouchpanel1IrqGpio);
3765 mPlatformNvsAreaProtocol.Area->Touchpanel1PowerEnableGpio = PcdGet32(PcdTouchpanel1PwrEnableGpio);
3766 mPlatformNvsAreaProtocol.Area->Touchpanel1PowerRstGpio = PcdGet32(PcdTouchpanel1RstGpio);
3767 mPlatformNvsAreaProtocol.Area->Touchpanel1IrqGpioPolarity = PcdGetBool(PcdTouchpanel1IrqGpioPolarity);
3768 mPlatformNvsAreaProtocol.Area->Touchpanel1PowerEnableGpioPolarity = PcdGetBool(PcdTouchpanel1PwrEnableGpioPolarity);
3769 mPlatformNvsAreaProtocol.Area->Touchpanel1PowerRstGpioPolarity = PcdGetBool(PcdTouchpanel1RstGpioPolarity);
3770 // WLAN GPIO pin configuration
3771 //
3772 mPlatformNvsAreaProtocol.Area->WlanWakeGpio = PcdGet32(PcdWlanWakeGpio);
3773 mPlatformNvsAreaProtocol.Area->WlanRootPortNumber = PcdGet8 (PcdWlanRootPortNumber);
3774
3775 //
3776 // Lid Switch Wake Gpio Config
3777 //
3778 mPlatformNvsAreaProtocol.Area->LidSwitchWakeGpio = PcdGet32 (PcdLidSwitchWakeGpio);
3779
3780 //
3781 // Platform AUX power limit configuration
3782 //
3783 mPlatformNvsAreaProtocol.Area->AuxPowerLimit = mSystemConfiguration.AuxRailBudget * 1000;//Maximum power supported by the aux rail.
3784 DEBUG((DEBUG_INFO,"AuxPowerLimit = %d\n", mPlatformNvsAreaProtocol.Area->AuxPowerLimit));
3785
3786 //
3787 //Disable PEP constarints for devices which are not present in CNL-H platform
3788 //
3789 if (IsPchH ()) {
3790 // Note: I2c4 and I2c5 present on ADL-S platform
3791 // mSystemConfiguration.PepI2c4 = 0;
3792 // mSystemConfiguration.PepI2c5 = 0;
3793 }
3794 //
3795 // Disable PEP constraint if IPU B0:D5:F0 device is not preset
3796 //
3797 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, GetIpuBusNumber (), GetIpuDevNumber (), GetIpuFuncNumber (), PCI_VENDOR_ID_OFFSET)) == 0xFFFF) {
3798 mSystemConfiguration.PepIpu = 0;
3799 }
3800 //
3801 // Disable PEP constraint if GNA B0:D8:F0 device is not preset
3802 //
3803 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, GetGnaBusNumber (), GetGnaDevNumber (), GetGnaFuncNumber (), PCI_VENDOR_ID_OFFSET)) == 0xFFFF) {
3804 mSystemConfiguration.PepGna = 0;
3805 }
3806 //
3807 //Disable PEP constraint if VMD B0:D14:F0 device is not present
3808 //
3809 if (!IsVmdEnabled ()) {
3810 mSystemConfiguration.PepVmd = 0;
3811 }
3812 //
3813 // Disable PEP constraint if PEG B0:D1:F0 device is not preset
3814 //
3815 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_PEG_BUS_NUM, SA_PEG3_DEV_NUM, SA_PEG0_FUN_NUM, PCI_VENDOR_ID_OFFSET)) == 0xFFFF) {
3816 mSystemConfiguration.PepPeg0 = 0;
3817 }
3818
3819 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_PEG_BUS_NUM, SA_PEG1_DEV_NUM, SA_PEG0_FUN_NUM, PCI_VENDOR_ID_OFFSET)) == 0xFFFF) {
3820 mSystemConfiguration.PepPcieDg = 0;
3821 }
3822
3823 //
3824 // Disable PEP constraint if IGD B0:D2:F0 device is not preset
3825 //
3826 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, GetIgdBusNumber(), GetIgdDevNumber(), GetIgdFuncNumber(), PCI_VENDOR_ID_OFFSET)) == 0xFFFF) {
3827 mSystemConfiguration.PepGfx = 0;
3828 }
3829 //
3830 //Disable Gbe PEP constarints if it's not presented.
3831 //
3832 if (!IsGbePresent()) {
3833 mSystemConfiguration.PepGbe = 0;
3834 }
3835 //
3836 // Disable PEP constraint if PCH SATA B0:D23:F0 device is not preset
3837 //
3838 RpDeviceBaseAddress = SataPciCfgBase(SATA_1_CONTROLLER_INDEX);
3839 if ((PciSegmentRead16 (RpDeviceBaseAddress + PCI_VENDOR_ID_OFFSET) == 0xFFFF) || (PciSegmentRead16 (RpDeviceBaseAddress + PCI_DEVICE_ID_OFFSET) == VMD_DUMMY_DEVICE_ID)) {
3840 mSystemConfiguration.PepSataContraints = 0;
3841 }
3842
3843 //
3844 // Disable PEP Constrains for THC
3845 //
3846 if (mPchSetup.ThcPort0Assignment != ThcAssignmentThc0) {
3847 // Disable PEP for THC0
3848 mSystemConfiguration.PepThc0 = 0;
3849 }
3850 if (mPchSetup.ThcPort1Assignment != ThcAssignmentThc1) {
3851 // Disable PEP for THC1
3852 mSystemConfiguration.PepThc1 = 0; //THC1 is not used
3853 }
3854
3855 //
3856 // Disable PEP constraint if PCH HDA B0:D31:F3 device is not preset
3857 //
3858 if (PciSegmentRead16 (HdaPciCfgBase () + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
3859 mSystemConfiguration.PepAudio = 0;
3860 }
3861
3862 //
3863 // Disable PEP constraint if PCH XHCI B0:D20:F0 device is not preset
3864 //
3865 if (PciSegmentRead16 (PchXhciPciCfgBase () + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
3866 mSystemConfiguration.PepXhci = 0;
3867 }
3868
3869 //
3870 // Disable PEP constraint if PCH CSME device B0:D22:F0 is not preset
3871 //
3872 if (PciSegmentRead16 (PchHeci1PciCfgBase () + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
3873 mSystemConfiguration.PepCsme = 0;
3874 }
3875
3876 //
3877 // Disable PEP constraint for EMMC device if not preset
3878 //
3879 if (!IsPchEmmcSupported ()) {
3880 mSystemConfiguration.PepEmmc = 0;
3881 }
3882 //
3883 // Disable PEP constraint if HECI3 B0:D22:F4 device is not preset
3884 //
3885 if (PciSegmentRead16 (PchHeci3PciCfgBase () + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
3886 DEBUG((DEBUG_INFO,"HECI3 device is not present\n"));
3887 mSystemConfiguration.PepHeci3 = 0;
3888 }
3889
3890 //
3891 // Enable PEP constraints for Serial Io devices
3892 // Override Function 0 Enabled devices
3893 //
3894 ZeroMem (PepSerialIoSpi, sizeof (PepSerialIoSpi));
3895 for (SerialIoIndex = 0; SerialIoIndex < GetPchMaxSerialIoSpiControllersNum (); SerialIoIndex++) {
3896 PepSerialIoSpi[SerialIoIndex] = mPchSetup.PchSerialIoSpi[SerialIoIndex];
3897 if ((PepSerialIoSpi[SerialIoIndex] == 0) && IsSerialIoSpiFunction0Enabled (SerialIoIndex)) {
3898 PepSerialIoSpi[SerialIoIndex] = 1;
3899 }
3900 }
3901 ZeroMem (PepSerialIoI2c, sizeof (PepSerialIoI2c));
3902 for (SerialIoIndex = 0; SerialIoIndex < GetPchMaxSerialIoI2cControllersNum (); SerialIoIndex++) {
3903 PepSerialIoI2c[SerialIoIndex] = mPchSetup.PchSerialIoI2c[SerialIoIndex];
3904 if ((PepSerialIoI2c[SerialIoIndex] == 0) && IsSerialIoI2cFunction0Enabled (SerialIoIndex)) {
3905 PepSerialIoI2c[SerialIoIndex] = 1;
3906 }
3907 }
3908 ZeroMem (PepSerialIoUart, sizeof (PepSerialIoUart));
3909 for (SerialIoIndex = 0; SerialIoIndex < GetPchMaxSerialIoUartControllersNum (); SerialIoIndex++) {
3910 PepSerialIoUart[SerialIoIndex] = mPchSetup.PchSerialIoUart[SerialIoIndex];
3911 if ((PepSerialIoUart[SerialIoIndex] == 0) && IsSerialIoUartFunction0Enabled (SerialIoIndex)) {
3912 PepSerialIoUart[SerialIoIndex] = 1;
3913 }
3914 }
3915 ZeroMem (PepUfs, sizeof (PepUfs));
3916 for (UfsIndex = 0; UfsIndex < PchGetMaxUfsNum (); UfsIndex++) {
3917 PepUfs[UfsIndex] = mPchSetup.PchScsUfsEnable[UfsIndex];
3918 if(PciSegmentRead16 (ScsUfsPciCfgBase (UfsIndex) + PCI_VENDOR_ID_OFFSET) == 0xFFFF ) {
3919 PepUfs[UfsIndex] = 0;
3920 }
3921 }
3922
3923 //
3924 // Micro-PEP constraint list
3925 //
3926 mPlatformNvsAreaProtocol.Area->LowPowerS0IdleConstraint = (((mPchSetup.PchSata == 1 ? 0x3:0) & mSystemConfiguration.PepSataContraints) << 0) | // Bit[1:0] - Storage (0:None, 1:Adapter D0/F1, 2:Raid, 3:Adapter D3)
3927 ((PepSerialIoUart[0] && mSystemConfiguration.PepUart) << 2) | // Bit[2] - En/Dis UART0
3928 ((PepSerialIoUart[1] && mSystemConfiguration.PepUart) << 3) | // Bit[3] - En/Dis UART1
3929 ((PepSerialIoI2c[0] && mSystemConfiguration.PepI2c0) << 4) | // Bit[4] - En/Dis I2C0
3930 ((PepSerialIoI2c[1] && mSystemConfiguration.PepI2c1) << 5) | // Bit[5] - En/Dis I2C1
3931 ( mSystemConfiguration.PepXhci << 6) | // Bit[6] - En/Dis XHCI
3932 (((mPchSetup.PchHdAudio == 1 ? 0x3:0) & mSystemConfiguration.PepAudio) << 7) | // Bit[8:7] - HD Audio (includes ADSP) (0:No Constraint or 1: D0/F1 or 3:D3)
3933 ( mSystemConfiguration.PepGfx << 9) | // Bit[9] - En/Dis GFX
3934 ( mSystemConfiguration.PepCpu << 10) | // Bit[10] - En/Dis CPU
3935 ((mPchSetup.PchScsEmmcEnabled && mSystemConfiguration.PepEmmc) << 11) | // Bit[11] - En/Dis EMMC
3936 (0 << 12) | // Bit[12] - En/Dis SDXC
3937 ((PepSerialIoI2c[2] && mSystemConfiguration.PepI2c2) << 13) | // Bit[13] - En/Dis I2C2
3938 ((PepSerialIoI2c[3] && mSystemConfiguration.PepI2c3) << 14) | // Bit[14] - En/Dis I2C3
3939 ((PepSerialIoI2c[4] && mSystemConfiguration.PepI2c4) << 15) | // Bit[15] - En/Dis I2C4
3940 ((PepSerialIoI2c[5] && mSystemConfiguration.PepI2c5) << 16) | // Bit[16] - En/Dis I2C5
3941 ((PepSerialIoUart[2] && mSystemConfiguration.PepUart) << 17) | // Bit[17] - En/Dis UART2
3942 ((PepSerialIoSpi[0] && mSystemConfiguration.PepSpi) << 18) | // Bit[18] - En/Dis SPI0
3943 ((PepSerialIoSpi[1] && mSystemConfiguration.PepSpi) << 19) | // Bit[19] - En/Dis SPI1
3944 ((PepSerialIoSpi[2] && mSystemConfiguration.PepSpi) << 20) | // Bit[20] -En/Dis SPI2
3945 ((SaSetup.SaIpuEnable && mSystemConfiguration.PepIpu) << 21) | // Bit[21] - En/Dis IPU0
3946 ( mSystemConfiguration.PepCsme << 22) | // Bit[22] - En/Dis CSME
3947 ((mPchSetup.PchLan && mSystemConfiguration.PepGbe) << 23) | // Bit[23] - En/Dis LAN(GBE)
3948 ( 0 << 24) | // Bit[24] - En/Dis PEG0
3949 (mSystemConfiguration.PepThc0 << 25) | // Bit[25] - En/Dis THC0
3950 (mSystemConfiguration.PepThc1 << 26) | // Bit[26] - En/Dis THC1
3951 ( 0 << 27) | // Bit[27] - Reserved
3952 ((UINT64)(PepSerialIoI2c[6] && mSystemConfiguration.PepI2c6) << 28) | // Bit[28] - En/Dis I2C6
3953 ( mSystemConfiguration.PepTcss << 29) | // Bit[29] -En/Dis TCSS
3954 ((SaSetup.GnaEnable && mSystemConfiguration.PepGna) << 30) | // Bit[30] - En/Dis GNA0
3955 (UINT32)(mSystemConfiguration.PepVmd << 31) | // Bit[31] - En/Dis VMD
3956 (((UINT64)mSystemConfiguration.PepHeci3) << 32) | // Bit[32] - En/Dis HECI3
3957 (((UINT64)mSystemConfiguration.PepPcieStorage) << 33) | // Bit[34:33] - PCIE Storage RP (0:No Constraint or 1: D0/F1 or 3:D3)
3958 (((UINT64)mSystemConfiguration.PepPcieLan) << 35) | // Bit[36:35] - Pcie Lan (0:No Constraint or 1:D0/F1 or 3:D3)
3959 (((UINT64)mSystemConfiguration.PepPcieWlan) << 37) | // Bit[38:37] - Pcie Wlan (0:No Constraint or 1:D0/F1 or 3:D3)
3960 (((UINT64)mSystemConfiguration.PepPcieGfx) << 39) | // Bit[40:39] - Pcie Gfx (0:No Constraint or 1:D0/F1 or 3:D3)
3961 (((UINT64)mSystemConfiguration.PepPcieOther) << 41) | // Bit[42:41] - Pcie Other (0:No Constraint or 1:D0/F1 or 3:D3)
3962 (((UINT64)mSystemConfiguration.PepPcieDg) << 43) | // Bit[43] - En/Dis DG on x8 PEG port (PEG1)
3963 ((UINT64)(PepUfs[0] && mSystemConfiguration.PepUfs0) << 44) | // Bit[44] - En/Dis UFS0
3964 ((UINT64)(PepUfs[1] && mSystemConfiguration.PepUfs1) << 45) | // Bit[45] - En/Dis UFS1
3965 ((UINT64)(PepSerialIoI2c[7] && mSystemConfiguration.PepI2c7) << 46); // Bit[46] - En/Dis I2C7
3966 DEBUG((DEBUG_INFO, "ACPI NVS, LowPowerS0IdleConstraint(Micro-pep constraints) = 0x%lX \n", mPlatformNvsAreaProtocol.Area->LowPowerS0IdleConstraint ));
3967
3968 //
3969 // Don't enumerate D3 constraints if SATA is in RAID mode.
3970 // This is due to the fact that RST driver won't necessarily enumerate SATA ports according to the ACPI specification.
3971 // This might lead to unsatisfied PEP constraints while in RAID mode.
3972 //
3973 if (mPchSetup.PchSata && mSystemConfiguration.PepSataEnumeration && (mPchSetup.SataInterfaceMode != SATA_MODE_RAID)) {
3974 mPlatformNvsAreaProtocol.Area->EnumerateSataPortConstraints = TRUE;
3975 } else {
3976 mPlatformNvsAreaProtocol.Area->EnumerateSataPortConstraints = FALSE;
3977 }
3978
3979 //
3980 // Assign EPI device interrupt pin and Enable/Disable Device by using PCD and pass through NVS
3981 //
3982
3983 //
3984 // Disable / Enable Power meter device based on user settings
3985 //
3986 mPlatformNvsAreaProtocol.Area->PowermeterDeviceEnable = mSystemConfiguration.PowermeterDeviceEnable;
3987
3988 mPlatformNvsAreaProtocol.Area->CSNotifyEC = mSystemConfiguration.CSNotifyEC;
3989
3990 mPlatformNvsAreaProtocol.Area->PL1LimitCS = mSystemConfiguration.PL1LimitCS;
3991 mPlatformNvsAreaProtocol.Area->PL1LimitCSValue = mSystemConfiguration.PL1LimitCSValue;
3992
3993 //
3994 // I2C Touch Pad Data Update to I2cTouchPad.asl
3995 //
3996 mPlatformNvsAreaProtocol.Area->TPDT = mSystemConfiguration.PchI2cTouchPadType;
3997 mPlatformNvsAreaProtocol.Area->TPDM = mSystemConfiguration.PchI2cTouchPadIrqMode;
3998 mPlatformNvsAreaProtocol.Area->TPDB = mSystemConfiguration.PchI2cTouchPadBusAddress;
3999 mPlatformNvsAreaProtocol.Area->TPDH = mSystemConfiguration.PchI2cTouchPadHidAddress;
4000 mPlatformNvsAreaProtocol.Area->TPDS = mSystemConfiguration.PchI2cTouchPadSpeed;
4001
4002 //
4003 // I2C Touch Panel Data Update to I2cTouchPanel.asl
4004 //
4005 mPlatformNvsAreaProtocol.Area->TPLT = mSystemConfiguration.PchI2cTouchPanelType;
4006 mPlatformNvsAreaProtocol.Area->TPLM = mSystemConfiguration.PchI2cTouchPanelIrqMode;
4007 mPlatformNvsAreaProtocol.Area->TPLB = mSystemConfiguration.PchI2cTouchPanelBusAddress;
4008 mPlatformNvsAreaProtocol.Area->TPLH = mSystemConfiguration.PchI2cTouchPanelHidAddress;
4009 mPlatformNvsAreaProtocol.Area->TPLS = mSystemConfiguration.PchI2cTouchPanelSpeed;
4010
4011 //
4012 // SPI Finger Print Data Update to SerialIoFingerPrint.asl
4013 //
4014 mPlatformNvsAreaProtocol.Area->FPTT = mSystemConfiguration.PchSpiFingerPrintType;
4015 mPlatformNvsAreaProtocol.Area->FPTM = mSystemConfiguration.PchSpiSensorIrqMode;
4016
4017 mPlatformNvsAreaProtocol.Area->SDS0 = mSystemConfiguration.PchI2cSensorDevicePort[SERIAL_IO_I2C0];
4018 mPlatformNvsAreaProtocol.Area->SDS1 = mSystemConfiguration.PchI2cSensorDevicePort[SERIAL_IO_I2C1];
4019 mPlatformNvsAreaProtocol.Area->SDS2 = mSystemConfiguration.PchI2cSensorDevicePort[SERIAL_IO_I2C2];
4020 mPlatformNvsAreaProtocol.Area->SDS3 = mSystemConfiguration.PchI2cSensorDevicePort[SERIAL_IO_I2C3];
4021 mPlatformNvsAreaProtocol.Area->SDS4 = mSystemConfiguration.PchI2cSensorDevicePort[SERIAL_IO_I2C4];
4022 mPlatformNvsAreaProtocol.Area->SDS5 = mSystemConfiguration.PchI2cSensorDevicePort[SERIAL_IO_I2C5];
4023 //mPlatformNvsAreaProtocol.Area->SDS6 = mSystemConfiguration.PchSpi0SensorDevice;
4024 //mPlatformNvsAreaProtocol.Area->SDM6 = mSystemConfiguration.PchI2c0SensorIrqMode;
4025 mPlatformNvsAreaProtocol.Area->SDS7 = mSystemConfiguration.PchSpiSensorDevicePort[SERIAL_IO_SPI1];
4026 mPlatformNvsAreaProtocol.Area->SDS8 = mSystemConfiguration.PchSpiSensorDevicePort[SERIAL_IO_SPI2];
4027
4028 mPlatformNvsAreaProtocol.Area->SDS9 = mSystemConfiguration.DiscreteBtModule;
4029 mPlatformNvsAreaProtocol.Area->SDM9 = mSystemConfiguration.DiscreteBtModuleIrqMode;
4030
4031 mPlatformNvsAreaProtocol.Area->WTVX = mSystemConfiguration.PchI2cWittVersion;
4032 mPlatformNvsAreaProtocol.Area->WITX = mSystemConfiguration.PchI2cWittDevice;
4033 mPlatformNvsAreaProtocol.Area->UTKX = mSystemConfiguration.PchUartUtkDevice;
4034 mPlatformNvsAreaProtocol.Area->GDBT = mPchSetup.PchGpioDebounce;
4035 mPlatformNvsAreaProtocol.Area->GPTD = mPchSetup.PchGpioTestDevices;
4036 mPlatformNvsAreaProtocol.Area->SPTD = mPchSetup.PchAdditionalSerialIoDevices;
4037
4038
4039 #if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
4040 mPlatformNvsAreaProtocol.Area->TsnPcsEnabled = mPchSetup.TsnPcsEnabled;
4041 #else
4042 mPlatformNvsAreaProtocol.Area->TsnPcsEnabled = 0;
4043 #endif
4044
4045 //
4046 // UCMC support
4047 //
4048 mPlatformNvsAreaProtocol.Area->UCMS = mSystemConfiguration.TcssUcmDevice;
4049
4050 if (PcdGet32 (PcdBoardUcmcGpio1)) {
4051 mPlatformNvsAreaProtocol.Area->UcmcPort1Gpio = PcdGet32 (PcdBoardUcmcGpio1);
4052 }
4053 if (PcdGet32 (PcdBoardUcmcGpio2)) {
4054 mPlatformNvsAreaProtocol.Area->UcmcPort2Gpio = PcdGet32 (PcdBoardUcmcGpio2);
4055 }
4056 if (PcdGet32 (PcdBoardUcmcGpio3)) {
4057 mPlatformNvsAreaProtocol.Area->UcmcPort3Gpio = PcdGet32 (PcdBoardUcmcGpio3);
4058 }
4059 if (PcdGet32 (PcdBoardUcmcGpio4)) {
4060 mPlatformNvsAreaProtocol.Area->UcmcPort4Gpio = PcdGet32 (PcdBoardUcmcGpio4);
4061 }
4062
4063 //
4064 // Serial IO timing parameters
4065 //
4066 mPlatformNvsAreaProtocol.Area->USTP = mSystemConfiguration.PchSerialIoUseTimingParameters;
4067
4068 mPlatformNvsAreaProtocol.Area->SSH0 = mSystemConfiguration.PchSerialIoTimingSSH0; // [SSH0] SSCN-HIGH for I2C0
4069 mPlatformNvsAreaProtocol.Area->SSL0 = mSystemConfiguration.PchSerialIoTimingSSL0; // [SSL0] SSCN-LOW for I2C0
4070 mPlatformNvsAreaProtocol.Area->SSD0 = mSystemConfiguration.PchSerialIoTimingSSD0; // [SSD0] SSCN-HOLD for I2C0
4071 mPlatformNvsAreaProtocol.Area->FMH0 = mSystemConfiguration.PchSerialIoTimingFMH0; // [FMH0] FMCN-HIGH for I2C0
4072 mPlatformNvsAreaProtocol.Area->FML0 = mSystemConfiguration.PchSerialIoTimingFML0; // [FML0] FMCN-LOW for I2C0
4073 mPlatformNvsAreaProtocol.Area->FMD0 = mSystemConfiguration.PchSerialIoTimingFMD0; // [FMD0] FMCN-HOLD for I2C0
4074 mPlatformNvsAreaProtocol.Area->FPH0 = mSystemConfiguration.PchSerialIoTimingFPH0; // [FPH0] FPCN-HIGH for I2C0
4075 mPlatformNvsAreaProtocol.Area->FPL0 = mSystemConfiguration.PchSerialIoTimingFPL0; // [FPL0] FPCN-LOW for I2C0
4076 mPlatformNvsAreaProtocol.Area->FPD0 = mSystemConfiguration.PchSerialIoTimingFPD0; // [FPD0] FPCN-HOLD for I2C0
4077 mPlatformNvsAreaProtocol.Area->HSH0 = mSystemConfiguration.PchSerialIoTimingHSH0; // [HSH0] HSCN-HIGH for I2C0
4078 mPlatformNvsAreaProtocol.Area->HSL0 = mSystemConfiguration.PchSerialIoTimingHSL0; // [HSL0] HSCN-LOW for I2C0
4079 mPlatformNvsAreaProtocol.Area->HSD0 = mSystemConfiguration.PchSerialIoTimingHSD0; // [HSD0] HSCN-HOLD for I2C0
4080
4081 mPlatformNvsAreaProtocol.Area->SSH1 = mSystemConfiguration.PchSerialIoTimingSSH1; // [SSH1] SSCN-HIGH for I2C1
4082 mPlatformNvsAreaProtocol.Area->SSL1 = mSystemConfiguration.PchSerialIoTimingSSL1; // [SSL1] SSCN-LOW for I2C1
4083 mPlatformNvsAreaProtocol.Area->SSD1 = mSystemConfiguration.PchSerialIoTimingSSD1; // [SSD1] SSCN-HOLD for I2C1
4084 mPlatformNvsAreaProtocol.Area->FMH1 = mSystemConfiguration.PchSerialIoTimingFMH1; // [FMH1] FMCN-HIGH for I2C1
4085 mPlatformNvsAreaProtocol.Area->FML1 = mSystemConfiguration.PchSerialIoTimingFML1; // [FML1] FMCN-LOW for I2C1
4086 mPlatformNvsAreaProtocol.Area->FMD1 = mSystemConfiguration.PchSerialIoTimingFMD1; // [FMD1] FMCN-HOLD for I2C1
4087 mPlatformNvsAreaProtocol.Area->FPH1 = mSystemConfiguration.PchSerialIoTimingFPH1; // [FPH1] FPCN-HIGH for I2C1
4088 mPlatformNvsAreaProtocol.Area->FPL1 = mSystemConfiguration.PchSerialIoTimingFPL1; // [FPL1] FPCN-LOW for I2C1
4089 mPlatformNvsAreaProtocol.Area->FPD1 = mSystemConfiguration.PchSerialIoTimingFPD1; // [FPD1] FPCN-HOLD for I2C1
4090 mPlatformNvsAreaProtocol.Area->HSH1 = mSystemConfiguration.PchSerialIoTimingHSH1; // [HSH1] HSCN-HIGH for I2C1
4091 mPlatformNvsAreaProtocol.Area->HSL1 = mSystemConfiguration.PchSerialIoTimingHSL1; // [HSL1] HSCN-LOW for I2C1
4092 mPlatformNvsAreaProtocol.Area->HSD1 = mSystemConfiguration.PchSerialIoTimingHSD1; // [HSD1] HSCN-HOLD for I2C1
4093
4094 mPlatformNvsAreaProtocol.Area->SSH2 = mSystemConfiguration.PchSerialIoTimingSSH2; // [SSH2] SSCN-HIGH for I2C2
4095 mPlatformNvsAreaProtocol.Area->SSL2 = mSystemConfiguration.PchSerialIoTimingSSL2; // [SSL2] SSCN-LOW for I2C2
4096 mPlatformNvsAreaProtocol.Area->SSD2 = mSystemConfiguration.PchSerialIoTimingSSD2; // [SSD2] SSCN-HOLD for I2C2
4097 mPlatformNvsAreaProtocol.Area->FMH2 = mSystemConfiguration.PchSerialIoTimingFMH2; // [FMH2] FMCN-HIGH for I2C2
4098 mPlatformNvsAreaProtocol.Area->FML2 = mSystemConfiguration.PchSerialIoTimingFML2; // [FML2] FMCN-LOW for I2C2
4099 mPlatformNvsAreaProtocol.Area->FMD2 = mSystemConfiguration.PchSerialIoTimingFMD2; // [FMD2] FMCN-HOLD for I2C2
4100 mPlatformNvsAreaProtocol.Area->FPH2 = mSystemConfiguration.PchSerialIoTimingFPH2; // [FPH2] FPCN-HIGH for I2C2
4101 mPlatformNvsAreaProtocol.Area->FPL2 = mSystemConfiguration.PchSerialIoTimingFPL2; // [FPL2] FPCN-LOW for I2C2
4102 mPlatformNvsAreaProtocol.Area->FPD2 = mSystemConfiguration.PchSerialIoTimingFPD2; // [FPD2] FPCN-HOLD for I2C2
4103 mPlatformNvsAreaProtocol.Area->HSH2 = mSystemConfiguration.PchSerialIoTimingHSH2; // [HSH2] HSCN-HIGH for I2C2
4104 mPlatformNvsAreaProtocol.Area->HSL2 = mSystemConfiguration.PchSerialIoTimingHSL2; // [HSL2] HSCN-LOW for I2C2
4105 mPlatformNvsAreaProtocol.Area->HSD2 = mSystemConfiguration.PchSerialIoTimingHSD2; // [HSD2] HSCN-HOLD for I2C2
4106
4107 mPlatformNvsAreaProtocol.Area->SSH3 = mSystemConfiguration.PchSerialIoTimingSSH3; // [SSH3] SSCN-HIGH for I2C3
4108 mPlatformNvsAreaProtocol.Area->SSL3 = mSystemConfiguration.PchSerialIoTimingSSL3; // [SSL3] SSCN-LOW for I2C3
4109 mPlatformNvsAreaProtocol.Area->SSD3 = mSystemConfiguration.PchSerialIoTimingSSD3; // [SSD3] SSCN-HOLD for I2C3
4110 mPlatformNvsAreaProtocol.Area->FMH3 = mSystemConfiguration.PchSerialIoTimingFMH3; // [FMH3] FMCN-HIGH for I2C3
4111 mPlatformNvsAreaProtocol.Area->FML3 = mSystemConfiguration.PchSerialIoTimingFML3; // [FML3] FMCN-LOW for I2C3
4112 mPlatformNvsAreaProtocol.Area->FMD3 = mSystemConfiguration.PchSerialIoTimingFMD3; // [FMD3] FMCN-HOLD for I2C3
4113 mPlatformNvsAreaProtocol.Area->FPH3 = mSystemConfiguration.PchSerialIoTimingFPH3; // [FPH3] FPCN-HIGH for I2C3
4114 mPlatformNvsAreaProtocol.Area->FPL3 = mSystemConfiguration.PchSerialIoTimingFPL3; // [FPL3] FPCN-LOW for I2C3
4115 mPlatformNvsAreaProtocol.Area->FPD3 = mSystemConfiguration.PchSerialIoTimingFPD3; // [FPD3] FPCN-HOLD for I2C3
4116 mPlatformNvsAreaProtocol.Area->HSH3 = mSystemConfiguration.PchSerialIoTimingHSH3; // [HSH3] HSCN-HIGH for I2C3
4117 mPlatformNvsAreaProtocol.Area->HSL3 = mSystemConfiguration.PchSerialIoTimingHSL3; // [HSL3] HSCN-LOW for I2C3
4118 mPlatformNvsAreaProtocol.Area->HSD3 = mSystemConfiguration.PchSerialIoTimingHSD3; // [HSD3] HSCN-HOLD for I2C3
4119
4120 mPlatformNvsAreaProtocol.Area->SSH4 = mSystemConfiguration.PchSerialIoTimingSSH4; // [SSH4] SSCN-HIGH for I2C4
4121 mPlatformNvsAreaProtocol.Area->SSL4 = mSystemConfiguration.PchSerialIoTimingSSL4; // [SSL4] SSCN-LOW for I2C4
4122 mPlatformNvsAreaProtocol.Area->SSD4 = mSystemConfiguration.PchSerialIoTimingSSD4; // [SSD4] SSCN-HOLD for I2C4
4123 mPlatformNvsAreaProtocol.Area->FMH4 = mSystemConfiguration.PchSerialIoTimingFMH4; // [FMH4] FMCN-HIGH for I2C4
4124 mPlatformNvsAreaProtocol.Area->FML4 = mSystemConfiguration.PchSerialIoTimingFML4; // [FML4] FMCN-LOW for I2C4
4125 mPlatformNvsAreaProtocol.Area->FMD4 = mSystemConfiguration.PchSerialIoTimingFMD4; // [FMD4] FMCN-HOLD for I2C4
4126 mPlatformNvsAreaProtocol.Area->FPH4 = mSystemConfiguration.PchSerialIoTimingFPH4; // [FPH4] FPCN-HIGH for I2C4
4127 mPlatformNvsAreaProtocol.Area->FPL4 = mSystemConfiguration.PchSerialIoTimingFPL4; // [FPL4] FPCN-LOW for I2C4
4128 mPlatformNvsAreaProtocol.Area->FPD4 = mSystemConfiguration.PchSerialIoTimingFPD4; // [FPD4] FPCN-HOLD for I2C4
4129 mPlatformNvsAreaProtocol.Area->HSH4 = mSystemConfiguration.PchSerialIoTimingHSH4; // [HSH4] HSCN-HIGH for I2C4
4130 mPlatformNvsAreaProtocol.Area->HSL4 = mSystemConfiguration.PchSerialIoTimingHSL4; // [HSL4] HSCN-LOW for I2C4
4131 mPlatformNvsAreaProtocol.Area->HSD4 = mSystemConfiguration.PchSerialIoTimingHSD4; // [HSD4] HSCN-HOLD for I2C4
4132
4133 mPlatformNvsAreaProtocol.Area->SSH5 = mSystemConfiguration.PchSerialIoTimingSSH5; // [SSH5] SSCN-HIGH for I2C5
4134 mPlatformNvsAreaProtocol.Area->SSL5 = mSystemConfiguration.PchSerialIoTimingSSL5; // [SSL5] SSCN-LOW for I2C5
4135 mPlatformNvsAreaProtocol.Area->SSD5 = mSystemConfiguration.PchSerialIoTimingSSD5; // [SSD5] SSCN-HOLD for I2C5
4136 mPlatformNvsAreaProtocol.Area->FMH5 = mSystemConfiguration.PchSerialIoTimingFMH5; // [FMH5] FMCN-HIGH for I2C5
4137 mPlatformNvsAreaProtocol.Area->FML5 = mSystemConfiguration.PchSerialIoTimingFML5; // [FML5] FMCN-LOW for I2C5
4138 mPlatformNvsAreaProtocol.Area->FMD5 = mSystemConfiguration.PchSerialIoTimingFMD5; // [FMD5] FMCN-HOLD for I2C5
4139 mPlatformNvsAreaProtocol.Area->FPH5 = mSystemConfiguration.PchSerialIoTimingFPH5; // [FPH5] FPCN-HIGH for I2C5
4140 mPlatformNvsAreaProtocol.Area->FPL5 = mSystemConfiguration.PchSerialIoTimingFPL5; // [FPL5] FPCN-LOW for I2C5
4141 mPlatformNvsAreaProtocol.Area->FPD5 = mSystemConfiguration.PchSerialIoTimingFPD5; // [FPD5] FPCN-HOLD for I2C5
4142 mPlatformNvsAreaProtocol.Area->HSH5 = mSystemConfiguration.PchSerialIoTimingHSH5; // [HSH5] HSCN-HIGH for I2C5
4143 mPlatformNvsAreaProtocol.Area->HSL5 = mSystemConfiguration.PchSerialIoTimingHSL5; // [HSL5] HSCN-LOW for I2C5
4144 mPlatformNvsAreaProtocol.Area->HSD5 = mSystemConfiguration.PchSerialIoTimingHSD5; // [HSD5] HSCN-HOLD for I2C5
4145
4146 mPlatformNvsAreaProtocol.Area->SSH6 = mSystemConfiguration.PchSerialIoTimingSSH6; // [SSH6] SSCN-HIGH for I2C6
4147 mPlatformNvsAreaProtocol.Area->SSL6 = mSystemConfiguration.PchSerialIoTimingSSL6; // [SSL6] SSCN-LOW for I2C6
4148 mPlatformNvsAreaProtocol.Area->SSD6 = mSystemConfiguration.PchSerialIoTimingSSD6; // [SSD6] SSCN-HOLD for I2C6
4149 mPlatformNvsAreaProtocol.Area->FMH6 = mSystemConfiguration.PchSerialIoTimingFMH6; // [FMH6] FMCN-HIGH for I2C6
4150 mPlatformNvsAreaProtocol.Area->FML6 = mSystemConfiguration.PchSerialIoTimingFML6; // [FML6] FMCN-LOW for I2C6
4151 mPlatformNvsAreaProtocol.Area->FMD6 = mSystemConfiguration.PchSerialIoTimingFMD6; // [FMD6] FMCN-HOLD for I2C6
4152 mPlatformNvsAreaProtocol.Area->FPH6 = mSystemConfiguration.PchSerialIoTimingFPH6; // [FPH6] FPCN-HIGH for I2C6
4153 mPlatformNvsAreaProtocol.Area->FPL6 = mSystemConfiguration.PchSerialIoTimingFPL6; // [FPL6] FPCN-LOW for I2C6
4154 mPlatformNvsAreaProtocol.Area->FPD6 = mSystemConfiguration.PchSerialIoTimingFPD6; // [FPD6] FPCN-HOLD for I2C6
4155 mPlatformNvsAreaProtocol.Area->HSH6 = mSystemConfiguration.PchSerialIoTimingHSH6; // [HSH6] HSCN-HIGH for I2C6
4156 mPlatformNvsAreaProtocol.Area->HSL6 = mSystemConfiguration.PchSerialIoTimingHSL6; // [HSL6] HSCN-LOW for I2C6
4157 mPlatformNvsAreaProtocol.Area->HSD6 = mSystemConfiguration.PchSerialIoTimingHSD6; // [HSD6] HSCN-HOLD for I2C6
4158
4159 mPlatformNvsAreaProtocol.Area->SSH7 = mSystemConfiguration.PchSerialIoTimingSSH7; // [SSH7] SSCN-HIGH for I2C7
4160 mPlatformNvsAreaProtocol.Area->SSL7 = mSystemConfiguration.PchSerialIoTimingSSL7; // [SSL7] SSCN-LOW for I2C7
4161 mPlatformNvsAreaProtocol.Area->SSD7 = mSystemConfiguration.PchSerialIoTimingSSD7; // [SSD7] SSCN-HOLD for I2C7
4162 mPlatformNvsAreaProtocol.Area->FMH7 = mSystemConfiguration.PchSerialIoTimingFMH7; // [FMH7] FMCN-HIGH for I2C7
4163 mPlatformNvsAreaProtocol.Area->FML7 = mSystemConfiguration.PchSerialIoTimingFML7; // [FML7] FMCN-LOW for I2C7
4164 mPlatformNvsAreaProtocol.Area->FMD7 = mSystemConfiguration.PchSerialIoTimingFMD7; // [FMD7] FMCN-HOLD for I2C7
4165 mPlatformNvsAreaProtocol.Area->FPH7 = mSystemConfiguration.PchSerialIoTimingFPH7; // [FPH7] FPCN-HIGH for I2C7
4166 mPlatformNvsAreaProtocol.Area->FPL7 = mSystemConfiguration.PchSerialIoTimingFPL7; // [FPL7] FPCN-LOW for I2C7
4167 mPlatformNvsAreaProtocol.Area->FPD7 = mSystemConfiguration.PchSerialIoTimingFPD7; // [FPD7] FPCN-HOLD for I2C7
4168 mPlatformNvsAreaProtocol.Area->HSH7 = mSystemConfiguration.PchSerialIoTimingHSH7; // [HSH7] HSCN-HIGH for I2C7
4169 mPlatformNvsAreaProtocol.Area->HSL7 = mSystemConfiguration.PchSerialIoTimingHSL7; // [HSL7] HSCN-LOW for I2C7
4170 mPlatformNvsAreaProtocol.Area->HSD7 = mSystemConfiguration.PchSerialIoTimingHSD7; // [HSD7] HSCN-HOLD for I2C7
4171
4172 mPlatformNvsAreaProtocol.Area->M0C0 = mSystemConfiguration.PchSerialIoTimingM0C0; // [M0C0] M0D3 for I2C0
4173 mPlatformNvsAreaProtocol.Area->M1C0 = mSystemConfiguration.PchSerialIoTimingM1C0; // [M1C0] M1D3 for I2C0
4174 mPlatformNvsAreaProtocol.Area->M0C1 = mSystemConfiguration.PchSerialIoTimingM0C1; // [M0C1] M0D3 for I2C1
4175 mPlatformNvsAreaProtocol.Area->M1C1 = mSystemConfiguration.PchSerialIoTimingM1C1; // [M1C1] M1D3 for I2C1
4176 mPlatformNvsAreaProtocol.Area->M0C2 = mSystemConfiguration.PchSerialIoTimingM0C2; // [M0C2] M0D3 for I2C2
4177 mPlatformNvsAreaProtocol.Area->M1C2 = mSystemConfiguration.PchSerialIoTimingM1C2; // [M1C2] M1D3 for I2C2
4178 mPlatformNvsAreaProtocol.Area->M0C3 = mSystemConfiguration.PchSerialIoTimingM0C3; // [M0C3] M0D3 for I2C3
4179 mPlatformNvsAreaProtocol.Area->M1C3 = mSystemConfiguration.PchSerialIoTimingM1C3; // [M1C3] M1D3 for I2C3
4180 mPlatformNvsAreaProtocol.Area->M0C4 = mSystemConfiguration.PchSerialIoTimingM0C4; // [M0C4] M0D3 for I2C4
4181 mPlatformNvsAreaProtocol.Area->M1C4 = mSystemConfiguration.PchSerialIoTimingM1C4; // [M1C4] M1D3 for I2C4
4182 mPlatformNvsAreaProtocol.Area->M0C5 = mSystemConfiguration.PchSerialIoTimingM0C5; // [M0C5] M0D3 for I2C5
4183 mPlatformNvsAreaProtocol.Area->M1C5 = mSystemConfiguration.PchSerialIoTimingM1C5; // [M1C5] M1D3 for I2C5
4184 mPlatformNvsAreaProtocol.Area->M0CC = mSystemConfiguration.PchSerialIoTimingM0CC; // [M0CC] M0D3 for I2C6
4185 mPlatformNvsAreaProtocol.Area->M0CC = mSystemConfiguration.PchSerialIoTimingM0CC; // [M0CC] M1D3 for I2C6
4186 mPlatformNvsAreaProtocol.Area->M0CD = mSystemConfiguration.PchSerialIoTimingM0CD; // [M0CD] M0D3 for I2C7
4187 mPlatformNvsAreaProtocol.Area->M0CD = mSystemConfiguration.PchSerialIoTimingM0CD; // [M0CD] M1D3 for I2C7
4188 mPlatformNvsAreaProtocol.Area->M0C6 = mSystemConfiguration.PchSerialIoTimingM0C6; // [M0C6] M0D3 for SPI0
4189 mPlatformNvsAreaProtocol.Area->M1C6 = mSystemConfiguration.PchSerialIoTimingM1C6; // [M1C6] M1D3 for SPI0
4190 mPlatformNvsAreaProtocol.Area->M0C7 = mSystemConfiguration.PchSerialIoTimingM0C7; // [M0C7] M0D3 for SPI1
4191 mPlatformNvsAreaProtocol.Area->M1C7 = mSystemConfiguration.PchSerialIoTimingM1C7; // [M1C7] M1D3 for SPI1
4192 mPlatformNvsAreaProtocol.Area->M0C8 = mSystemConfiguration.PchSerialIoTimingM0C8; // [M0C8] M0D3 for SPI2
4193 mPlatformNvsAreaProtocol.Area->M1C8 = mSystemConfiguration.PchSerialIoTimingM1C8; // [M1C8] M1D3 for SPI2
4194 mPlatformNvsAreaProtocol.Area->M0C9 = mSystemConfiguration.PchSerialIoTimingM0C9; // [M0C9] M0D3 for UART0
4195 mPlatformNvsAreaProtocol.Area->M1C9 = mSystemConfiguration.PchSerialIoTimingM1C9; // [M1C9] M1D3 for UART0
4196 mPlatformNvsAreaProtocol.Area->M0CA = mSystemConfiguration.PchSerialIoTimingM0CA; // [M0CA] M0D3 for UART1
4197 mPlatformNvsAreaProtocol.Area->M1CA = mSystemConfiguration.PchSerialIoTimingM1CA; // [M1CA] M1D3 for UART1
4198 mPlatformNvsAreaProtocol.Area->M0CB = mSystemConfiguration.PchSerialIoTimingM0CB; // [M0CB] M0D3 for UART2
4199 mPlatformNvsAreaProtocol.Area->M1CB = mSystemConfiguration.PchSerialIoTimingM1CB; // [M1CB] M1D3 for UART2
4200
4201 mPlatformNvsAreaProtocol.Area->FingerPrintSleepGpio = PcdGet32 (PcdFingerPrintSleepGpio);
4202 mPlatformNvsAreaProtocol.Area->FingerPrintIrqGpio = PcdGet32 (PcdFingerPrintIrqGpio);
4203 mPlatformNvsAreaProtocol.Area->WwanModemBaseBandResetGpio = PcdGet32(PcdWwanModemBaseBandResetGpio);
4204 mPlatformNvsAreaProtocol.Area->DiscreteBtModuleRfKillGpio = PcdGet32 (PcdBtRfKillGpio);
4205 mPlatformNvsAreaProtocol.Area->DiscreteBtModuleIrqGpio = PcdGet32 (PcdBtIrqGpio);
4206 mPlatformNvsAreaProtocol.Area->TouchpadIrqGpio = PcdGet32 (PcdTouchpadIrqGpio);
4207 mPlatformNvsAreaProtocol.Area->TouchpanelIrqGpio = PcdGet32 (PcdTouchpanelIrqGpio);
4208
4209 mPlatformNvsAreaProtocol.Area->Revision = PLATFORM_NVS_AREA_REVISION_1; // for TPM related fields
4210 if (mSystemConfiguration.FastBoot == 0) {
4211 mPlatformNvsAreaProtocol.Area->Ps2MouseEnable = IsPs2MouseConnected ();
4212 } else {
4213 #if FixedPcdGetBool (PcdAdlLpSupport) == 1
4214 mPlatformNvsAreaProtocol.Area->Ps2MouseEnable = 0;
4215 #else
4216 mPlatformNvsAreaProtocol.Area->Ps2MouseEnable = 1;
4217 #endif
4218 }
4219 mPlatformNvsAreaProtocol.Area->Ps2KbMsEnable = mSystemConfiguration.Ps2KbMsEnable;
4220
4221 #if FixedPcdGetBool(PcdAdlLpSupport) == 1
4222 mPlatformNvsAreaProtocol.Area->ClosedLidWovLighting = mSystemConfiguration.ClosedLidWovLightingSupport;
4223 mPlatformNvsAreaProtocol.Area->ClwlI2cController = PcdGet8 (PcdClwlI2cController);
4224 mPlatformNvsAreaProtocol.Area->ClwlI2cSlaveAddress = PcdGet8 (PcdClwlI2cSlaveAddress);
4225 DEBUG ((DEBUG_INFO,"ClosedLidWovLighting support = %x\n", mPlatformNvsAreaProtocol.Area->ClosedLidWovLighting));
4226 DEBUG ((DEBUG_INFO,"ClwlI2cController = %x\n", mPlatformNvsAreaProtocol.Area->ClwlI2cController));
4227 DEBUG ((DEBUG_INFO,"ClwlI2cSlaveAddress = %x\n", mPlatformNvsAreaProtocol.Area->ClwlI2cSlaveAddress));
4228 #endif
4229
4230 //
4231 // Feature Specific RVP Details
4232 //
4233 mPlatformNvsAreaProtocol.Area->UsbTypeCSupport = PcdGetBool (PcdUsbTypeCSupport);
4234 mPlatformNvsAreaProtocol.Area->UsbTypeCEcLess = PcdGet8 (PcdUsbTypeCEcLess);
4235 mPlatformNvsAreaProtocol.Area->PcdTsOnDimmTemperature = PcdGetBool (PcdTsOnDimmTemperature);
4236 mPlatformNvsAreaProtocol.Area->PcdRealBattery1Control = PcdGet8 (PcdRealBattery1Control);
4237 mPlatformNvsAreaProtocol.Area->PcdRealBattery2Control = PcdGet8 (PcdRealBattery2Control);
4238 mPlatformNvsAreaProtocol.Area->PcdMipiCamSensor = PcdGetBool (PcdMipiCamSensor);
4239 mPlatformNvsAreaProtocol.Area->PcdNCT6776FCOM = PcdGetBool (PcdNCT6776FCOM);
4240 mPlatformNvsAreaProtocol.Area->PcdNCT6776FSIO = PcdGetBool (PcdNCT6776FSIO);
4241 mPlatformNvsAreaProtocol.Area->PcdNCT6776FHWMON = PcdGetBool (PcdNCT6776FHWMON);
4242 mPlatformNvsAreaProtocol.Area->PcdH8S2113SIO = PcdGetBool (PcdH8S2113SIO);
4243 mPlatformNvsAreaProtocol.Area->PcdH8S2113UAR = PcdGetBool (PcdH8S2113UAR);
4244 mPlatformNvsAreaProtocol.Area->PcdSmcRuntimeSciPin = PcdGet32 (PcdSmcRuntimeSciPin);
4245 mPlatformNvsAreaProtocol.Area->PcdConvertableDockSupport = PcdGetBool (PcdConvertableDockSupport);
4246 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF3Support = PcdGet8 (PcdEcHotKeyF3Support);
4247 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF4Support = PcdGet8 (PcdEcHotKeyF4Support);
4248 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF5Support = PcdGet8 (PcdEcHotKeyF5Support);
4249 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF6Support = PcdGet8 (PcdEcHotKeyF6Support);
4250 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF7Support = PcdGet8 (PcdEcHotKeyF7Support);
4251 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF8Support = PcdGet8 (PcdEcHotKeyF8Support);
4252 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonVolumeUpSupport = PcdGetBool (PcdVirtualButtonVolumeUpSupport);
4253 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonVolumeDownSupport = PcdGetBool (PcdVirtualButtonVolumeDownSupport);
4254 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonHomeButtonSupport = PcdGetBool (PcdVirtualButtonHomeButtonSupport);
4255 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonRotationLockSupport = PcdGetBool (PcdVirtualButtonRotationLockSupport);
4256 mPlatformNvsAreaProtocol.Area->PcdSlateModeSwitchSupport = PcdGetBool (PcdSlateModeSwitchSupport);
4257 mPlatformNvsAreaProtocol.Area->PcdAcDcAutoSwitchSupport = PcdGetBool (PcdAcDcAutoSwitchSupport);
4258 mPlatformNvsAreaProtocol.Area->PcdPmPowerButtonGpioPin = PcdGet32 (PcdPmPowerButtonGpioPin);
4259 mPlatformNvsAreaProtocol.Area->PcdAcpiEnableAllButtonSupport = PcdGetBool (PcdAcpiEnableAllButtonSupport);
4260 mPlatformNvsAreaProtocol.Area->PcdAcpiHidDriverButtonSupport = PcdGetBool (PcdAcpiHidDriverButtonSupport);
4261 mPlatformNvsAreaProtocol.Area->PcdBatteryPresent = PcdGet8 (PcdBatteryPresent);
4262
4263 // PD PS_ON GPIO
4264 mPlatformNvsAreaProtocol.Area->PPOE = mSystemConfiguration.TcssPdPsOnEnable;
4265 mPlatformNvsAreaProtocol.Area->POVP = PcdGet32 (PcdUsbCPsonOverrideN);
4266 mPlatformNvsAreaProtocol.Area->PSG1 = PcdGet32 (PcdUsbCPsonS0ixEntryReq);
4267 mPlatformNvsAreaProtocol.Area->PSG2 = PcdGet32 (PcdUsbCPsonS0ixEntryAck);
4268
4269 mPlatformNvsAreaProtocol.Area->DPIW = mSystemConfiguration.DpInExternalEn;
4270 mPlatformNvsAreaProtocol.Area->DPG1 = PcdGet32 (PcdDpMuxGpio);
4271
4272 // USBC DR_SWAP
4273 mPlatformNvsAreaProtocol.Area->UsbcDataRoleSwap = (mSystemConfiguration.UsbcDataRoleSwapPlatformDisable) ? 1 : 0;
4274
4275 //
4276 // Always report PS2MouseEnable for non-EC board
4277 //
4278 if (mPlatformNvsAreaProtocol.Area->EcAvailable == PLATFORM_NVS_DEVICE_DISABLE) {
4279 mPlatformNvsAreaProtocol.Area->Ps2MouseEnable = 1;
4280 }
4281
4282 mPlatformNvsAreaProtocol.Area->UsbSensorHub = mSystemConfiguration.UsbSensorHub;
4283
4284 //
4285 // CVF configuration
4286 //
4287
4288 mPlatformNvsAreaProtocol.Area->CvfSupport = mSystemConfiguration.CvfSupport;
4289 mPlatformNvsAreaProtocol.Area->CvfUsbPort = PcdGet8 (PcdCvfUsbPort);
4290 //
4291 // MipiCam sensor configuration
4292 //
4293
4294 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic0 = mSystemConfiguration.MipiCam_ControlLogic0;
4295 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic1 = mSystemConfiguration.MipiCam_ControlLogic1;
4296 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic2 = mSystemConfiguration.MipiCam_ControlLogic2;
4297 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic3 = mSystemConfiguration.MipiCam_ControlLogic3;
4298 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic4 = mSystemConfiguration.MipiCam_ControlLogic4;
4299 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic5 = mSystemConfiguration.MipiCam_ControlLogic5;
4300 mPlatformNvsAreaProtocol.Area->MipiCamLink0Enabled = mSystemConfiguration.MipiCam_Link0;
4301 mPlatformNvsAreaProtocol.Area->MipiCamLink1Enabled = mSystemConfiguration.MipiCam_Link1;
4302 mPlatformNvsAreaProtocol.Area->MipiCamLink2Enabled = mSystemConfiguration.MipiCam_Link2;
4303 mPlatformNvsAreaProtocol.Area->MipiCamLink3Enabled = mSystemConfiguration.MipiCam_Link3;
4304 mPlatformNvsAreaProtocol.Area->MipiCamLink4Enabled = mSystemConfiguration.MipiCam_Link4;
4305 mPlatformNvsAreaProtocol.Area->MipiCamLink5Enabled = mSystemConfiguration.MipiCam_Link5;
4306
4307 // MipiCam Control Logic 0 specific
4308 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Version = 1;
4309 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Type = mSystemConfiguration.MipiCam_ControlLogic0_Type;
4310 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic0_CrdVersion;
4311 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_InputClock = mSystemConfiguration.MipiCam_ControlLogic0_InputClock;
4312 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic0_GpioPinsEnabled;
4313 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_I2cBus = mSystemConfiguration.MipiCam_ControlLogic0_I2cChannel;
4314 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic0_I2cAddress;
4315 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Pld = mSystemConfiguration.MipiCam_ControlLogic0_Pld;
4316 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled1FlashMaxCurrent;
4317 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled1TorchMaxCurrent;
4318 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled2FlashMaxCurrent;
4319 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled2TorchMaxCurrent;
4320 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic0_SubPlatformId;
4321 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic0_Wled1Type;
4322 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic0_Wled2Type;
4323 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic0_PchClockSource;
4324
4325 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
4326 if (Index < mSystemConfiguration.MipiCam_ControlLogic0_GpioPinsEnabled) {
4327 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioGroupPadNumber[Index];
4328 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioGroupNumber[Index];
4329 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioFunction[Index];
4330 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioActiveValue[Index];
4331 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioInitialValue[Index];
4332 } else {
4333 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupPadNumber[Index] = 0;
4334 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupNumber[Index] = 0;
4335 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioFunction[Index] = 0;
4336 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioActiveValue[Index] = 1;
4337 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioInitialValue[Index] = 0;
4338 }
4339 }
4340
4341 // MipiCam Control Logic 1 specific
4342 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Version = 1;
4343 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Type = mSystemConfiguration.MipiCam_ControlLogic1_Type;
4344 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic1_CrdVersion;
4345 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_InputClock = mSystemConfiguration.MipiCam_ControlLogic1_InputClock;
4346 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic1_GpioPinsEnabled;
4347 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_I2cBus = mSystemConfiguration.MipiCam_ControlLogic1_I2cChannel;
4348 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic1_I2cAddress;
4349 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Pld = mSystemConfiguration.MipiCam_ControlLogic1_Pld;
4350 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled1FlashMaxCurrent;
4351 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled1TorchMaxCurrent;
4352 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled2FlashMaxCurrent;
4353 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled2TorchMaxCurrent;
4354 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic1_SubPlatformId;
4355 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic1_Wled1Type;
4356 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic1_Wled2Type;
4357 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic1_PchClockSource;
4358
4359 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
4360 if (Index < mSystemConfiguration.MipiCam_ControlLogic1_GpioPinsEnabled) {
4361 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioGroupPadNumber[Index];
4362 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioGroupNumber[Index];
4363 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioFunction[Index];
4364 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioActiveValue[Index];
4365 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioInitialValue[Index];
4366 } else {
4367 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupPadNumber[Index] = 0;
4368 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupNumber[Index] = 0;
4369 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioFunction[Index] = 0;
4370 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioActiveValue[Index] = 1;
4371 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioInitialValue[Index] = 0;
4372 }
4373 }
4374
4375 // MipiCam Control Logic 2 specific
4376 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Version = 1;
4377 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Type = mSystemConfiguration.MipiCam_ControlLogic2_Type;
4378 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic2_CrdVersion;
4379 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_InputClock = mSystemConfiguration.MipiCam_ControlLogic2_InputClock;
4380 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic2_GpioPinsEnabled;
4381 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_I2cBus = mSystemConfiguration.MipiCam_ControlLogic2_I2cChannel;
4382 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic2_I2cAddress;
4383 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Pld = mSystemConfiguration.MipiCam_ControlLogic2_Pld;
4384 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled1FlashMaxCurrent;
4385 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled1TorchMaxCurrent;
4386 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled2FlashMaxCurrent;
4387 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled2TorchMaxCurrent;
4388 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic2_SubPlatformId;
4389 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic2_Wled1Type;
4390 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic2_Wled2Type;
4391 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic2_PchClockSource;
4392
4393 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
4394 if (Index < mSystemConfiguration.MipiCam_ControlLogic2_GpioPinsEnabled) {
4395 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioGroupPadNumber[Index];
4396 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioGroupNumber[Index];
4397 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioFunction[Index];
4398 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioActiveValue[Index];
4399 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioInitialValue[Index];
4400 } else {
4401 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupPadNumber[Index] = 0;
4402 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupNumber[Index] = 0;
4403 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioFunction[Index] = 0;
4404 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioActiveValue[Index] = 1;
4405 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioInitialValue[Index] = 0;
4406 }
4407 }
4408
4409 // MipiCam Control Logic 3 specific
4410 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Version = 1;
4411 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Type = mSystemConfiguration.MipiCam_ControlLogic3_Type;
4412 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic3_CrdVersion;
4413 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_InputClock = mSystemConfiguration.MipiCam_ControlLogic3_InputClock;
4414 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic3_GpioPinsEnabled;
4415 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_I2cBus = mSystemConfiguration.MipiCam_ControlLogic3_I2cChannel;
4416 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic3_I2cAddress;
4417 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Pld = mSystemConfiguration.MipiCam_ControlLogic3_Pld;
4418 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled1FlashMaxCurrent;
4419 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled1TorchMaxCurrent;
4420 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled2FlashMaxCurrent;
4421 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled2TorchMaxCurrent;
4422 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic3_SubPlatformId;
4423 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic3_Wled1Type;
4424 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic3_Wled2Type;
4425 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic3_PchClockSource;
4426
4427 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
4428 if (Index < mSystemConfiguration.MipiCam_ControlLogic3_GpioPinsEnabled) {
4429 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioGroupPadNumber[Index];
4430 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioGroupNumber[Index];
4431 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioFunction[Index];
4432 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioActiveValue[Index];
4433 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioInitialValue[Index];
4434 } else {
4435 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupPadNumber[Index] = 0;
4436 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupNumber[Index] = 0;
4437 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioFunction[Index] = 0;
4438 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioActiveValue[Index] = 1;
4439 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioInitialValue[Index] = 0;
4440 }
4441 }
4442
4443 // MipiCam Control Logic 4 specific
4444 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Version = 1;
4445 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Type = mSystemConfiguration.MipiCam_ControlLogic4_Type;
4446 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic4_CrdVersion;
4447 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_InputClock = mSystemConfiguration.MipiCam_ControlLogic4_InputClock;
4448 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic4_GpioPinsEnabled;
4449 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_I2cBus = mSystemConfiguration.MipiCam_ControlLogic4_I2cChannel;
4450 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic4_I2cAddress;
4451 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Pld = mSystemConfiguration.MipiCam_ControlLogic4_Pld;
4452 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic4_Wled1FlashMaxCurrent;
4453 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic4_Wled1TorchMaxCurrent;
4454 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic4_Wled2FlashMaxCurrent;
4455 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic4_Wled2TorchMaxCurrent;
4456 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic4_SubPlatformId;
4457 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic4_Wled1Type;
4458 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic4_Wled2Type;
4459 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic4_PchClockSource;
4460
4461 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
4462 if (Index < mSystemConfiguration.MipiCam_ControlLogic4_GpioPinsEnabled) {
4463 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic4_GpioGroupPadNumber[Index];
4464 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic4_GpioGroupNumber[Index];
4465 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic4_GpioFunction[Index];
4466 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic4_GpioActiveValue[Index];
4467 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic4_GpioInitialValue[Index];
4468 } else {
4469 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioGroupPadNumber[Index] = 0;
4470 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioGroupNumber[Index] = 0;
4471 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioFunction[Index] = 0;
4472 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioActiveValue[Index] = 1;
4473 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic4_GpioInitialValue[Index] = 0;
4474 }
4475 }
4476
4477 // MipiCam Control Logic 5 specific
4478 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Version = 1;
4479 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Type = mSystemConfiguration.MipiCam_ControlLogic5_Type;
4480 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic5_CrdVersion;
4481 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_InputClock = mSystemConfiguration.MipiCam_ControlLogic5_InputClock;
4482 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic5_GpioPinsEnabled;
4483 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_I2cBus = mSystemConfiguration.MipiCam_ControlLogic5_I2cChannel;
4484 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic5_I2cAddress;
4485 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Pld = mSystemConfiguration.MipiCam_ControlLogic5_Pld;
4486 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic5_Wled1FlashMaxCurrent;
4487 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic5_Wled1TorchMaxCurrent;
4488 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic5_Wled2FlashMaxCurrent;
4489 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic5_Wled2TorchMaxCurrent;
4490 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic5_SubPlatformId;
4491 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic5_Wled1Type;
4492 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic5_Wled2Type;
4493 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic5_PchClockSource;
4494
4495 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
4496 if (Index < mSystemConfiguration.MipiCam_ControlLogic5_GpioPinsEnabled) {
4497 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic5_GpioGroupPadNumber[Index];
4498 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic5_GpioGroupNumber[Index];
4499 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic5_GpioFunction[Index];
4500 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic5_GpioActiveValue[Index];
4501 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic5_GpioInitialValue[Index];
4502 } else {
4503 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioGroupPadNumber[Index] = 0;
4504 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioGroupNumber[Index] = 0;
4505 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioFunction[Index] = 0;
4506 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioActiveValue[Index] = 1;
4507 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic5_GpioInitialValue[Index] = 0;
4508 }
4509 }
4510
4511 // MipiCam Link0 specific
4512 mPlatformNvsAreaProtocol.Area->MipiCamLink0SensorModel = mSystemConfiguration.MipiCam_Link0_SensorModel;
4513 mPlatformNvsAreaProtocol.Area->MipiCamLink0Pld = mSystemConfiguration.MipiCam_Link0_CameraPhysicalLocation;
4514 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4515 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
4516 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link0_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4517 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink0ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink0ModuleName));
4518 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4519 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link0_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
4520 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink0UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink0UserHid));
4521 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link0_I2cDevicesEnabled;
4522 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cBus = mSystemConfiguration.MipiCam_Link0_I2cChannel;
4523
4524 // MipiCam Link0 I2C Devices
4525 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
4526 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link0_I2cAddress[Index];
4527 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link0_I2cDeviceType[Index];
4528 }
4529
4530 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_Version = 1;
4531 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_CrdVersion = mSystemConfiguration.MipiCam_Link0_DriverData_CrdVersion;
4532 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_LanesClkDivision = mSystemConfiguration.MipiCam_Link0_LanesClkDiv;
4533 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_LinkUsed = mSystemConfiguration.MipiCam_Link0_DriverData_LinkUsed;
4534 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_LaneUsed = mSystemConfiguration.MipiCam_Link0_DriverData_LaneUsed;
4535 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_EepromType = mSystemConfiguration.MipiCam_Link0_DriverData_EepromType;
4536 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_VcmType = mSystemConfiguration.MipiCam_Link0_DriverData_VcmType;
4537 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_Mclk = mSystemConfiguration.MipiCam_Link0_DriverData_Mclk;
4538 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_ControlLogic = mSystemConfiguration.MipiCam_Link0_DriverData_ControlLogic;
4539 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_FlashSupport = mSystemConfiguration.MipiCam_Link0_DriverData_FlashSupport;
4540 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_PrivacyLed = mSystemConfiguration.MipiCam_Link0_DriverData_PrivacyLed;
4541 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_Degree = mSystemConfiguration.MipiCam_Link0_DriverData_Degree;
4542 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_PmicPosition = mSystemConfiguration.MipiCam_Link0_DriverData_PmicPosition;
4543 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_VoltageRail = mSystemConfiguration.MipiCam_Link0_DriverData_VoltageRail;
4544 mPlatformNvsAreaProtocol.Area->MipiCamLink0_FlashDriverSelection = mSystemConfiguration.MipiCam_Link0_FlashDriverSelection;
4545
4546 // MipiCam Link1 specific
4547 mPlatformNvsAreaProtocol.Area->MipiCamLink1SensorModel = mSystemConfiguration.MipiCam_Link1_SensorModel;
4548 mPlatformNvsAreaProtocol.Area->MipiCamLink1Pld = mSystemConfiguration.MipiCam_Link1_CameraPhysicalLocation;
4549 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4550 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
4551 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link1_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4552 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink1ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink1ModuleName));
4553 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4554 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link1_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
4555 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink1UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink1UserHid));
4556 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link1_I2cDevicesEnabled;
4557 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cBus = mSystemConfiguration.MipiCam_Link1_I2cChannel;
4558
4559 // MipiCam Link1 I2C Devices
4560 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
4561 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link1_I2cAddress[Index];
4562 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link1_I2cDeviceType[Index];
4563 }
4564 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_Version = 1;
4565 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_CrdVersion = mSystemConfiguration.MipiCam_Link1_DriverData_CrdVersion;
4566 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_LanesClkDivision = mSystemConfiguration.MipiCam_Link1_LanesClkDiv;
4567 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_LinkUsed = mSystemConfiguration.MipiCam_Link1_DriverData_LinkUsed;
4568 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_LaneUsed = mSystemConfiguration.MipiCam_Link1_DriverData_LaneUsed;
4569 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_EepromType = mSystemConfiguration.MipiCam_Link1_DriverData_EepromType;
4570 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_VcmType = mSystemConfiguration.MipiCam_Link1_DriverData_VcmType;
4571 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_Mclk = mSystemConfiguration.MipiCam_Link1_DriverData_Mclk;
4572 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_ControlLogic = mSystemConfiguration.MipiCam_Link1_DriverData_ControlLogic;
4573 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_FlashSupport = mSystemConfiguration.MipiCam_Link1_DriverData_FlashSupport;
4574 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_PrivacyLed = mSystemConfiguration.MipiCam_Link1_DriverData_PrivacyLed;
4575 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_Degree = mSystemConfiguration.MipiCam_Link1_DriverData_Degree;
4576 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_PmicPosition = mSystemConfiguration.MipiCam_Link1_DriverData_PmicPosition;
4577 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_VoltageRail = mSystemConfiguration.MipiCam_Link1_DriverData_VoltageRail;
4578 mPlatformNvsAreaProtocol.Area->MipiCamLink1_FlashDriverSelection = mSystemConfiguration.MipiCam_Link1_FlashDriverSelection;
4579
4580 // MipiCam Link2 specific
4581 mPlatformNvsAreaProtocol.Area->MipiCamLink2SensorModel = mSystemConfiguration.MipiCam_Link2_SensorModel;
4582 mPlatformNvsAreaProtocol.Area->MipiCamLink2Pld = mSystemConfiguration.MipiCam_Link2_CameraPhysicalLocation;
4583 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4584 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
4585 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link2_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4586 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink2ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink2ModuleName));
4587 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4588 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link2_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
4589 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink2UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink2UserHid));
4590 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link2_I2cDevicesEnabled;
4591 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cBus = mSystemConfiguration.MipiCam_Link2_I2cChannel;
4592
4593 // MipiCam Link2 I2C Devices
4594 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
4595 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link2_I2cAddress[Index];
4596 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link2_I2cDeviceType[Index];
4597 }
4598 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_Version = 1;
4599 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_CrdVersion = mSystemConfiguration.MipiCam_Link2_DriverData_CrdVersion;
4600 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_LanesClkDivision = mSystemConfiguration.MipiCam_Link2_LanesClkDiv;
4601 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_LinkUsed = mSystemConfiguration.MipiCam_Link2_DriverData_LinkUsed;
4602 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_LaneUsed = mSystemConfiguration.MipiCam_Link2_DriverData_LaneUsed;
4603 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_EepromType = mSystemConfiguration.MipiCam_Link2_DriverData_EepromType;
4604 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_VcmType = mSystemConfiguration.MipiCam_Link2_DriverData_VcmType;
4605 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_Mclk = mSystemConfiguration.MipiCam_Link2_DriverData_Mclk;
4606 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_ControlLogic = mSystemConfiguration.MipiCam_Link2_DriverData_ControlLogic;
4607 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_FlashSupport = mSystemConfiguration.MipiCam_Link2_DriverData_FlashSupport;
4608 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_PrivacyLed = mSystemConfiguration.MipiCam_Link2_DriverData_PrivacyLed;
4609 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_Degree = mSystemConfiguration.MipiCam_Link2_DriverData_Degree;
4610 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_PmicPosition = mSystemConfiguration.MipiCam_Link2_DriverData_PmicPosition;
4611 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_VoltageRail = mSystemConfiguration.MipiCam_Link2_DriverData_VoltageRail;
4612 mPlatformNvsAreaProtocol.Area->MipiCamLink2_FlashDriverSelection = mSystemConfiguration.MipiCam_Link2_FlashDriverSelection;
4613
4614 // MipiCam Link3 specific
4615 mPlatformNvsAreaProtocol.Area->MipiCamLink3SensorModel = mSystemConfiguration.MipiCam_Link3_SensorModel;
4616 mPlatformNvsAreaProtocol.Area->MipiCamLink3Pld = mSystemConfiguration.MipiCam_Link3_CameraPhysicalLocation;
4617 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4618 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
4619 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link3_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4620 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink3ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink3ModuleName));
4621 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4622 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link3_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
4623 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink3UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink3UserHid));
4624 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link3_I2cDevicesEnabled;
4625 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cBus = mSystemConfiguration.MipiCam_Link3_I2cChannel;
4626
4627 // MipiCam Link3 I2C Devices
4628 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
4629 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link3_I2cAddress[Index];
4630 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link3_I2cDeviceType[Index];
4631 }
4632 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_Version = 1;
4633 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_CrdVersion = mSystemConfiguration.MipiCam_Link3_DriverData_CrdVersion;
4634 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_LanesClkDivision = mSystemConfiguration.MipiCam_Link3_LanesClkDiv;
4635 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_LinkUsed = mSystemConfiguration.MipiCam_Link3_DriverData_LinkUsed;
4636 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_LaneUsed = mSystemConfiguration.MipiCam_Link3_DriverData_LaneUsed;
4637 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_EepromType = mSystemConfiguration.MipiCam_Link3_DriverData_EepromType;
4638 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_VcmType = mSystemConfiguration.MipiCam_Link3_DriverData_VcmType;
4639 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_Mclk = mSystemConfiguration.MipiCam_Link3_DriverData_Mclk;
4640 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_ControlLogic = mSystemConfiguration.MipiCam_Link3_DriverData_ControlLogic;
4641 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_FlashSupport = mSystemConfiguration.MipiCam_Link3_DriverData_FlashSupport;
4642 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_PrivacyLed = mSystemConfiguration.MipiCam_Link3_DriverData_PrivacyLed;
4643 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_Degree = mSystemConfiguration.MipiCam_Link3_DriverData_Degree;
4644 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_PmicPosition = mSystemConfiguration.MipiCam_Link3_DriverData_PmicPosition;
4645 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_VoltageRail = mSystemConfiguration.MipiCam_Link3_DriverData_VoltageRail;
4646 mPlatformNvsAreaProtocol.Area->MipiCamLink3_FlashDriverSelection = mSystemConfiguration.MipiCam_Link3_FlashDriverSelection;
4647
4648 // MipiCam Link4 specific
4649 mPlatformNvsAreaProtocol.Area->MipiCamLink4SensorModel = mSystemConfiguration.MipiCam_Link4_SensorModel;
4650 mPlatformNvsAreaProtocol.Area->MipiCamLink4Pld = mSystemConfiguration.MipiCam_Link4_CameraPhysicalLocation;
4651 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4652 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
4653 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link4_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4654 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink4ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink4ModuleName));
4655 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4656 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link4_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
4657 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink4UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink4UserHid));
4658 mPlatformNvsAreaProtocol.Area->MipiCamLink4I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link4_I2cDevicesEnabled;
4659 mPlatformNvsAreaProtocol.Area->MipiCamLink4I2cBus = mSystemConfiguration.MipiCam_Link4_I2cChannel;
4660
4661 // MipiCam Link4 I2C Devices
4662 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
4663 mPlatformNvsAreaProtocol.Area->MipiCamLink4I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link4_I2cAddress[Index];
4664 mPlatformNvsAreaProtocol.Area->MipiCamLink4I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link4_I2cDeviceType[Index];
4665 }
4666 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_Version = 1;
4667 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_CrdVersion = mSystemConfiguration.MipiCam_Link4_DriverData_CrdVersion;
4668 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_LanesClkDivision = mSystemConfiguration.MipiCam_Link4_LanesClkDiv;
4669 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_LinkUsed = mSystemConfiguration.MipiCam_Link4_DriverData_LinkUsed;
4670 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_LaneUsed = mSystemConfiguration.MipiCam_Link4_DriverData_LaneUsed;
4671 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_EepromType = mSystemConfiguration.MipiCam_Link4_DriverData_EepromType;
4672 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_VcmType = mSystemConfiguration.MipiCam_Link4_DriverData_VcmType;
4673 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_Mclk = mSystemConfiguration.MipiCam_Link4_DriverData_Mclk;
4674 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_ControlLogic = mSystemConfiguration.MipiCam_Link4_DriverData_ControlLogic;
4675 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_FlashSupport = mSystemConfiguration.MipiCam_Link4_DriverData_FlashSupport;
4676 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_PrivacyLed = mSystemConfiguration.MipiCam_Link4_DriverData_PrivacyLed;
4677 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_Degree = mSystemConfiguration.MipiCam_Link4_DriverData_Degree;
4678 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_PmicPosition = mSystemConfiguration.MipiCam_Link4_DriverData_PmicPosition;
4679 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_VoltageRail = mSystemConfiguration.MipiCam_Link4_DriverData_VoltageRail;
4680 mPlatformNvsAreaProtocol.Area->MipiCamLink4_FlashDriverSelection = mSystemConfiguration.MipiCam_Link4_FlashDriverSelection;
4681
4682 // MipiCam Link5 specific
4683 mPlatformNvsAreaProtocol.Area->MipiCamLink5SensorModel = mSystemConfiguration.MipiCam_Link5_SensorModel;
4684 mPlatformNvsAreaProtocol.Area->MipiCamLink5Pld = mSystemConfiguration.MipiCam_Link5_CameraPhysicalLocation;
4685 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4686 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
4687 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link5_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4688 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink5ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink5ModuleName));
4689 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
4690 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link5_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
4691 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink5UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink5UserHid));
4692 mPlatformNvsAreaProtocol.Area->MipiCamLink5I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link5_I2cDevicesEnabled;
4693 mPlatformNvsAreaProtocol.Area->MipiCamLink5I2cBus = mSystemConfiguration.MipiCam_Link5_I2cChannel;
4694
4695 // MipiCam Link5 I2C Devices
4696 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
4697 mPlatformNvsAreaProtocol.Area->MipiCamLink5I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link5_I2cAddress[Index];
4698 mPlatformNvsAreaProtocol.Area->MipiCamLink5I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link5_I2cDeviceType[Index];
4699 }
4700 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_Version = 1;
4701 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_CrdVersion = mSystemConfiguration.MipiCam_Link5_DriverData_CrdVersion;
4702 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_LanesClkDivision = mSystemConfiguration.MipiCam_Link5_LanesClkDiv;
4703 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_LinkUsed = mSystemConfiguration.MipiCam_Link5_DriverData_LinkUsed;
4704 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_LaneUsed = mSystemConfiguration.MipiCam_Link5_DriverData_LaneUsed;
4705 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_EepromType = mSystemConfiguration.MipiCam_Link5_DriverData_EepromType;
4706 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_VcmType = mSystemConfiguration.MipiCam_Link5_DriverData_VcmType;
4707 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_Mclk = mSystemConfiguration.MipiCam_Link5_DriverData_Mclk;
4708 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_ControlLogic = mSystemConfiguration.MipiCam_Link5_DriverData_ControlLogic;
4709 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_FlashSupport = mSystemConfiguration.MipiCam_Link5_DriverData_FlashSupport;
4710 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_PrivacyLed = mSystemConfiguration.MipiCam_Link5_DriverData_PrivacyLed;
4711 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_Degree = mSystemConfiguration.MipiCam_Link5_DriverData_Degree;
4712 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_PmicPosition = mSystemConfiguration.MipiCam_Link5_DriverData_PmicPosition;
4713 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_VoltageRail = mSystemConfiguration.MipiCam_Link5_DriverData_VoltageRail;
4714 mPlatformNvsAreaProtocol.Area->MipiCamLink5_FlashDriverSelection = mSystemConfiguration.MipiCam_Link5_FlashDriverSelection;
4715
4716 // MipiCam Flash0 specific
4717 mPlatformNvsAreaProtocol.Area->MipiCamFlash0Model = mSystemConfiguration.MipiCam_Flash0_Model;
4718 mPlatformNvsAreaProtocol.Area->MipiCamFlash0Mode = mSystemConfiguration.MipiCam_Flash0_Mode;
4719 ZeroMem(ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4720 // Need to copy to temporary aligned buffer due to pack(1) in SetupVariables.h
4721 CopyMem(ModuleName, mSystemConfiguration.MipiCam_Flash0_ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4722 UnicodeStrToAsciiStrS(ModuleName, (CHAR8 *)mPlatformNvsAreaProtocol.Area->MipiCamFlash0ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamFlash0ModuleName));
4723 mPlatformNvsAreaProtocol.Area->MipiCamFlash0I2cBus = mSystemConfiguration.MipiCam_Flash0_I2cChannel;
4724 mPlatformNvsAreaProtocol.Area->MipiCamFlash0I2cAddrDev = mSystemConfiguration.MipiCam_Flash0_I2cAddress;
4725 mPlatformNvsAreaProtocol.Area->MipiCamFlash0GpioGroupPadNumber = mSystemConfiguration.MipiCam_Flash0_GpioGroupPadNumber;
4726 mPlatformNvsAreaProtocol.Area->MipiCamFlash0GpioGroupNumber = mSystemConfiguration.MipiCam_Flash0_GpioGroupNumber;
4727 mPlatformNvsAreaProtocol.Area->MipiCamFlash0GpioActiveValue = mSystemConfiguration.MipiCam_Flash0_GpioActiveValue;
4728 mPlatformNvsAreaProtocol.Area->MipiCamFlash0GpioInitialValue = mSystemConfiguration.MipiCam_Flash0_GpioInitialValue;
4729 mPlatformNvsAreaProtocol.Area->MipiCamFlash0OperatingMode = mSystemConfiguration.MipiCam_Flash0_OperatingMode;
4730
4731 // MipiCam Flash1 specific
4732 mPlatformNvsAreaProtocol.Area->MipiCamFlash1Model = mSystemConfiguration.MipiCam_Flash1_Model;
4733 mPlatformNvsAreaProtocol.Area->MipiCamFlash1Mode = mSystemConfiguration.MipiCam_Flash1_Mode;
4734 ZeroMem(ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4735 // Need to copy to temporary aligned buffer due to pack(1) in SetupVariables.h
4736 CopyMem(ModuleName, mSystemConfiguration.MipiCam_Flash1_ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4737 UnicodeStrToAsciiStrS(ModuleName, (CHAR8 *)mPlatformNvsAreaProtocol.Area->MipiCamFlash1ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamFlash1ModuleName));
4738 mPlatformNvsAreaProtocol.Area->MipiCamFlash1I2cBus = mSystemConfiguration.MipiCam_Flash1_I2cChannel;
4739 mPlatformNvsAreaProtocol.Area->MipiCamFlash1I2cAddrDev = mSystemConfiguration.MipiCam_Flash1_I2cAddress;
4740 mPlatformNvsAreaProtocol.Area->MipiCamFlash1GpioGroupPadNumber = mSystemConfiguration.MipiCam_Flash1_GpioGroupPadNumber;
4741 mPlatformNvsAreaProtocol.Area->MipiCamFlash1GpioGroupNumber = mSystemConfiguration.MipiCam_Flash1_GpioGroupNumber;
4742 mPlatformNvsAreaProtocol.Area->MipiCamFlash1GpioActiveValue = mSystemConfiguration.MipiCam_Flash1_GpioActiveValue;
4743 mPlatformNvsAreaProtocol.Area->MipiCamFlash1GpioInitialValue = mSystemConfiguration.MipiCam_Flash1_GpioInitialValue;
4744 mPlatformNvsAreaProtocol.Area->MipiCamFlash1OperatingMode = mSystemConfiguration.MipiCam_Flash1_OperatingMode;
4745
4746 // MipiCam Flash2 specific
4747 mPlatformNvsAreaProtocol.Area->MipiCamFlash2Model = mSystemConfiguration.MipiCam_Flash2_Model;
4748 mPlatformNvsAreaProtocol.Area->MipiCamFlash2Mode = mSystemConfiguration.MipiCam_Flash2_Mode;
4749 ZeroMem(ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4750 // Need to copy to temporary aligned buffer due to pack(1) in SetupVariables.h
4751 CopyMem(ModuleName, mSystemConfiguration.MipiCam_Flash2_ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4752 UnicodeStrToAsciiStrS(ModuleName, (CHAR8 *)mPlatformNvsAreaProtocol.Area->MipiCamFlash2ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamFlash2ModuleName));
4753 mPlatformNvsAreaProtocol.Area->MipiCamFlash2I2cBus = mSystemConfiguration.MipiCam_Flash2_I2cChannel;
4754 mPlatformNvsAreaProtocol.Area->MipiCamFlash2I2cAddrDev = mSystemConfiguration.MipiCam_Flash2_I2cAddress;
4755 mPlatformNvsAreaProtocol.Area->MipiCamFlash2GpioGroupPadNumber = mSystemConfiguration.MipiCam_Flash2_GpioGroupPadNumber;
4756 mPlatformNvsAreaProtocol.Area->MipiCamFlash2GpioGroupNumber = mSystemConfiguration.MipiCam_Flash2_GpioGroupNumber;
4757 mPlatformNvsAreaProtocol.Area->MipiCamFlash2GpioActiveValue = mSystemConfiguration.MipiCam_Flash2_GpioActiveValue;
4758 mPlatformNvsAreaProtocol.Area->MipiCamFlash2GpioInitialValue = mSystemConfiguration.MipiCam_Flash2_GpioInitialValue;
4759 mPlatformNvsAreaProtocol.Area->MipiCamFlash2OperatingMode = mSystemConfiguration.MipiCam_Flash2_OperatingMode;
4760
4761 // MipiCam Flash3 specific
4762 mPlatformNvsAreaProtocol.Area->MipiCamFlash3Model = mSystemConfiguration.MipiCam_Flash3_Model;
4763 mPlatformNvsAreaProtocol.Area->MipiCamFlash3Mode = mSystemConfiguration.MipiCam_Flash3_Mode;
4764 ZeroMem(ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4765 // Need to copy to temporary aligned buffer due to pack(1) in SetupVariables.h
4766 CopyMem(ModuleName, mSystemConfiguration.MipiCam_Flash3_ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4767 UnicodeStrToAsciiStrS(ModuleName, (CHAR8 *)mPlatformNvsAreaProtocol.Area->MipiCamFlash3ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamFlash3ModuleName));
4768 mPlatformNvsAreaProtocol.Area->MipiCamFlash3I2cBus = mSystemConfiguration.MipiCam_Flash3_I2cChannel;
4769 mPlatformNvsAreaProtocol.Area->MipiCamFlash3I2cAddrDev = mSystemConfiguration.MipiCam_Flash3_I2cAddress;
4770 mPlatformNvsAreaProtocol.Area->MipiCamFlash3GpioGroupPadNumber = mSystemConfiguration.MipiCam_Flash3_GpioGroupPadNumber;
4771 mPlatformNvsAreaProtocol.Area->MipiCamFlash3GpioGroupNumber = mSystemConfiguration.MipiCam_Flash3_GpioGroupNumber;
4772 mPlatformNvsAreaProtocol.Area->MipiCamFlash3GpioActiveValue = mSystemConfiguration.MipiCam_Flash3_GpioActiveValue;
4773 mPlatformNvsAreaProtocol.Area->MipiCamFlash3GpioInitialValue = mSystemConfiguration.MipiCam_Flash3_GpioInitialValue;
4774 mPlatformNvsAreaProtocol.Area->MipiCamFlash3OperatingMode = mSystemConfiguration.MipiCam_Flash3_OperatingMode;
4775
4776 // MipiCam Flash4 specific
4777 mPlatformNvsAreaProtocol.Area->MipiCamFlash4Model = mSystemConfiguration.MipiCam_Flash4_Model;
4778 mPlatformNvsAreaProtocol.Area->MipiCamFlash4Mode = mSystemConfiguration.MipiCam_Flash4_Mode;
4779 ZeroMem(ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4780 // Need to copy to temporary aligned buffer due to pack(1) in SetupVariables.h
4781 CopyMem(ModuleName, mSystemConfiguration.MipiCam_Flash4_ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4782 UnicodeStrToAsciiStrS(ModuleName, (CHAR8 *)mPlatformNvsAreaProtocol.Area->MipiCamFlash4ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamFlash4ModuleName));
4783 mPlatformNvsAreaProtocol.Area->MipiCamFlash4I2cBus = mSystemConfiguration.MipiCam_Flash4_I2cChannel;
4784 mPlatformNvsAreaProtocol.Area->MipiCamFlash4I2cAddrDev = mSystemConfiguration.MipiCam_Flash4_I2cAddress;
4785 mPlatformNvsAreaProtocol.Area->MipiCamFlash4GpioGroupPadNumber = mSystemConfiguration.MipiCam_Flash4_GpioGroupPadNumber;
4786 mPlatformNvsAreaProtocol.Area->MipiCamFlash4GpioGroupNumber = mSystemConfiguration.MipiCam_Flash4_GpioGroupNumber;
4787 mPlatformNvsAreaProtocol.Area->MipiCamFlash4GpioActiveValue = mSystemConfiguration.MipiCam_Flash4_GpioActiveValue;
4788 mPlatformNvsAreaProtocol.Area->MipiCamFlash4GpioInitialValue = mSystemConfiguration.MipiCam_Flash4_GpioInitialValue;
4789 mPlatformNvsAreaProtocol.Area->MipiCamFlash4OperatingMode = mSystemConfiguration.MipiCam_Flash4_OperatingMode;
4790
4791 // MipiCam Flash5 specific
4792 mPlatformNvsAreaProtocol.Area->MipiCamFlash5Model = mSystemConfiguration.MipiCam_Flash5_Model;
4793 mPlatformNvsAreaProtocol.Area->MipiCamFlash5Mode = mSystemConfiguration.MipiCam_Flash5_Mode;
4794 ZeroMem(ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4795 // Need to copy to temporary aligned buffer due to pack(1) in SetupVariables.h
4796 CopyMem(ModuleName, mSystemConfiguration.MipiCam_Flash5_ModuleName, sizeof(UINT16)* MIPICAM_MODULE_NAME_LENGTH);
4797 UnicodeStrToAsciiStrS(ModuleName, (CHAR8 *)mPlatformNvsAreaProtocol.Area->MipiCamFlash5ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamFlash5ModuleName));
4798 mPlatformNvsAreaProtocol.Area->MipiCamFlash5I2cBus = mSystemConfiguration.MipiCam_Flash5_I2cChannel;
4799 mPlatformNvsAreaProtocol.Area->MipiCamFlash5I2cAddrDev = mSystemConfiguration.MipiCam_Flash5_I2cAddress;
4800 mPlatformNvsAreaProtocol.Area->MipiCamFlash5GpioGroupPadNumber = mSystemConfiguration.MipiCam_Flash5_GpioGroupPadNumber;
4801 mPlatformNvsAreaProtocol.Area->MipiCamFlash5GpioGroupNumber = mSystemConfiguration.MipiCam_Flash5_GpioGroupNumber;
4802 mPlatformNvsAreaProtocol.Area->MipiCamFlash5GpioActiveValue = mSystemConfiguration.MipiCam_Flash5_GpioActiveValue;
4803 mPlatformNvsAreaProtocol.Area->MipiCamFlash5GpioInitialValue = mSystemConfiguration.MipiCam_Flash5_GpioInitialValue;
4804 mPlatformNvsAreaProtocol.Area->MipiCamFlash5OperatingMode = mSystemConfiguration.MipiCam_Flash5_OperatingMode;
4805
4806 // Flash id Specific
4807 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_FlashID = mSystemConfiguration.MipiCam_Link0_DriverData_FlashID;
4808 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_FlashID = mSystemConfiguration.MipiCam_Link1_DriverData_FlashID;
4809 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_FlashID = mSystemConfiguration.MipiCam_Link2_DriverData_FlashID;
4810 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_FlashID = mSystemConfiguration.MipiCam_Link3_DriverData_FlashID;
4811 mPlatformNvsAreaProtocol.Area->MipiCamLink4DD_FlashID = mSystemConfiguration.MipiCam_Link4_DriverData_FlashID;
4812 mPlatformNvsAreaProtocol.Area->MipiCamLink5DD_FlashID = mSystemConfiguration.MipiCam_Link5_DriverData_FlashID;
4813 //
4814 // HDAudio Configuration
4815 //
4816 mPlatformNvsAreaProtocol.Area->I2SC = mPchSetup.PchHdAudioI2sCodecSelect;
4817 mPlatformNvsAreaProtocol.Area->I2SI = PcdGet32 (PcdHdaI2sCodecIrqGpio);
4818 mPlatformNvsAreaProtocol.Area->I2SB = mPchSetup.PchHdAudioI2sCodecBusNumber;
4819
4820 DEBUG((DEBUG_INFO,"HDA: I2S Codec Select [I2SC] = 0x%02x\n", mPlatformNvsAreaProtocol.Area->I2SC));
4821 DEBUG((DEBUG_INFO,"HDA: I2S Codec JD Int pin [I2SI] = 0x%08x\n", mPlatformNvsAreaProtocol.Area->I2SI));
4822 DEBUG((DEBUG_INFO,"HDA: I2S Codec I2C Bus Number [I2SB] = 0x%02x\n", mPlatformNvsAreaProtocol.Area->I2SB));
4823
4824 for (Index = 0; Index < HDAUDIO_PP_MODULES; Index++) {
4825 mPlatformNvsAreaProtocol.Area->HdaDspPpModuleMask |= (UINT32)(mPchSetup.PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0);
4826 }
4827 DEBUG((DEBUG_INFO,"HDA: HdaDspPpModuleMask [ADPM] = 0x%08x\n", mPlatformNvsAreaProtocol.Area->HdaDspPpModuleMask));
4828
4829 if (mPchSetup.PchHdAudioPostProcessingMod[29]){
4830 DEBUG((DEBUG_INFO,"HDA: AudioDSP Pre/Post-Processing custom module 'Alpha' enabled (BIT29)\n"));
4831
4832 CopyMem(LocalGuidString, mPchSetup.PchHdAudioPostProcessingModCustomGuid1, GUID_CHARS_NUMBER * sizeof(CHAR16));
4833 GuidStringToAcpiBuffer (LocalGuidString, &AcpiGuidPart1, &AcpiGuidPart2);
4834 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1Low = AcpiGuidPart1;
4835 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1High = AcpiGuidPart2;
4836 DEBUG((DEBUG_INFO,"HdaDspPpModCustomGuid1Low = 0x%016Lx\nHdaDspPpModCustomGuid2High = 0x%016Lx\n",
4837 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1Low, mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1High));
4838 }
4839
4840 if (mPchSetup.PchHdAudioPostProcessingMod[30]){
4841 DEBUG((DEBUG_INFO,"HDA: AudioDSP Pre/Post-Processing custom module 'Beta' enabled (BIT30)\n"));
4842
4843 CopyMem(LocalGuidString, mPchSetup.PchHdAudioPostProcessingModCustomGuid2, GUID_CHARS_NUMBER * sizeof(CHAR16));
4844 GuidStringToAcpiBuffer (LocalGuidString, &AcpiGuidPart1, &AcpiGuidPart2);
4845 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2Low = AcpiGuidPart1;
4846 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2High = AcpiGuidPart2;
4847 DEBUG((DEBUG_INFO,"HdaDspPpModCustomGuid2Low = 0x%016Lx\nHdaDspPpModCustomGuid2High = 0x%016Lx\n",
4848 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2Low, mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2High));
4849 }
4850
4851 if (mPchSetup.PchHdAudioPostProcessingMod[31]){
4852 DEBUG((DEBUG_INFO,"HDA: AudioDSP Pre/Post-Processing custom module 'Gamma' enabled (BIT31)\n"));
4853
4854 CopyMem(LocalGuidString, mPchSetup.PchHdAudioPostProcessingModCustomGuid3, GUID_CHARS_NUMBER * sizeof(CHAR16));
4855 GuidStringToAcpiBuffer (LocalGuidString, &AcpiGuidPart1, &AcpiGuidPart2);
4856 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3Low = AcpiGuidPart1;
4857 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3High = AcpiGuidPart2;
4858 DEBUG((DEBUG_INFO,"HdaDspPpModCustomGuid3Low = 0x%016Lx\nHdaDspPpModCustomGuid3High = 0x%016Lx\n",
4859 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3Low, mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3High));
4860 }
4861
4862 ///
4863 /// PMAX Configuration
4864 ///
4865 mPlatformNvsAreaProtocol.Area->PmaxDevice = mSystemConfiguration.PmaxDevice;
4866 mPlatformNvsAreaProtocol.Area->PmaxAudioCodec = mSystemConfiguration.PmaxAudioCodec;
4867 mPlatformNvsAreaProtocol.Area->PmaxWfCamera = mSystemConfiguration.PmaxWfCamera;
4868 mPlatformNvsAreaProtocol.Area->PmaxUfCamera = mSystemConfiguration.PmaxUfCamera;
4869 mPlatformNvsAreaProtocol.Area->PmaxFlashDevice = mSystemConfiguration.PmaxFlashDevice;
4870
4871 ///
4872 /// Get TcssHob HOB
4873 ///
4874 #if FixedPcdGetBool(PcdITbtEnable) == 1
4875 mTcssHob = (TCSS_DATA_HOB *) GetFirstGuidHob (&gTcssHobGuid);
4876 #endif
4877 mPlatformNvsAreaProtocol.Area->PciDelayOptimizationEcr = mSystemConfiguration.PciDelayOptimizationEcr;
4878
4879 if ((mSystemConfiguration.SdevXhciEntry == TRUE) && (mSystemConfiguration.SdevXhciNumberOfDevices > 0)) {
4880 mPlatformNvsAreaProtocol.Area->SdevXhciInterfaceNumber1 = mSystemConfiguration.SdevXhciInterfaceNumber[0];
4881 mPlatformNvsAreaProtocol.Area->SdevXhciRootPortNumber1 = mSystemConfiguration.SdevXhciRootPortNumber[0];
4882 if (mSystemConfiguration.SdevXhciNumberOfDevices > 1) {
4883 mPlatformNvsAreaProtocol.Area->SdevXhciInterfaceNumber2 = mSystemConfiguration.SdevXhciInterfaceNumber[1];
4884 mPlatformNvsAreaProtocol.Area->SdevXhciRootPortNumber2 = mSystemConfiguration.SdevXhciRootPortNumber[1];
4885 }
4886 }
4887 mPlatformNvsAreaProtocol.Area->SdevXhciEntry = mSystemConfiguration.SdevXhciEntry;
4888
4889 mPlatformNvsAreaProtocol.Area->DeepestUSBSleepWakeCapability = mSystemConfiguration.DeepestUSBSleepWakeCapability;
4890 mPlatformNvsAreaProtocol.Area->EnablePcieTunnelingOverUsb4 = mSystemConfiguration.EnablePcieTunnelingOverUsb4;
4891
4892 PreBootCmMode = 0;
4893 CmTbtMask = 0;
4894 Usb4CmSwitchEnable = 0;
4895
4896 //
4897 // Find USB4 Hob to get platform USB4 host router information
4898 //
4899 HobPtr = NULL;
4900 HobPtr = GetFirstGuidHob (&gUsb4PlatformHobGuid);
4901 if (HobPtr == NULL) {
4902 DEBUG ((DEBUG_ERROR, "Unable to find USB4 platform hob!\n"));
4903 } else {
4904 Usb4PlatformHob = GET_GUID_HOB_DATA (HobPtr);
4905 Usb4PlatformInfo = &(Usb4PlatformHob->Usb4PlatformInfo);
4906 //
4907 // Bit 7 - Valid bit
4908 // Bit 6:4 - Setup bit
4909 // Bit 3 - Reserved
4910 // Bit 2:0 - Pre-boot CM mode
4911 //
4912 PreBootCmMode = (Usb4PlatformInfo->CmModeOption & 0x07) << 4;
4913 PreBootCmMode |= (Usb4PlatformInfo->CmMode & 0x07);
4914 PreBootCmMode |= 0x80;
4915
4916 CmTbtMask = Usb4PlatformInfo->Usb4HrMask;
4917 Usb4CmSwitchEnable = Usb4PlatformInfo->CmSwitchSupport;
4918 }
4919
4920 mPlatformNvsAreaProtocol.Area->PreBootCmMode = PreBootCmMode;
4921 mPlatformNvsAreaProtocol.Area->CmTbtMask = CmTbtMask;
4922 mPlatformNvsAreaProtocol.Area->Usb4CmSwitchEnable = Usb4CmSwitchEnable;
4923 DEBUG ((DEBUG_INFO, "PreBootCmMode = 0x%x, CmTbtMask = 0x%x, Usb4CmSwitchEnable = 0x%x\n",
4924 mPlatformNvsAreaProtocol.Area->PreBootCmMode,
4925 mPlatformNvsAreaProtocol.Area->CmTbtMask,
4926 mPlatformNvsAreaProtocol.Area->Usb4CmSwitchEnable
4927 ));
4928
4929
4930 Status = gBS->InstallMultipleProtocolInterfaces (
4931 &Handle,
4932 &gPlatformNvsAreaProtocolGuid,
4933 &mPlatformNvsAreaProtocol,
4934 NULL
4935 );
4936 ASSERT_EFI_ERROR (Status);
4937
4938 //
4939 // Allocate NVS area for VBIOS. This is not currently used.
4940 //
4941 Status = AllocateMemoryBelow4G (
4942 EfiACPIMemoryNVS,
4943 0x10000,
4944 &mGfxNvsAddress
4945 );
4946 ASSERT_EFI_ERROR (Status);
4947
4948 //
4949 // Generate ACPI tables from configuration data
4950 //
4951 Status = GenerateSsdtFromConfigFile();
4952 ASSERT_EFI_ERROR (Status);
4953
4954 //
4955 // Platform ACPI Tables
4956 //
4957 PublishAcpiTablesFromFv(gAcpiTableStorageGuid);
4958
4959 //
4960 // Reference Code ACPI Tables
4961 //
4962 PublishAcpiTablesFromFv(gRcAcpiTableStorageGuid);
4963
4964 //
4965 // Save Acpi Setup Variables
4966 //
4967 Status = SetAcpiSetupVariables ();
4968 ASSERT_EFI_ERROR (Status);
4969
4970 //
4971 // Finished
4972 //
4973 return EFI_SUCCESS;
4974 }
4975
4976 /**
4977 Sort ordering of CPUs according to the priorities of cores and threads.
4978 ** ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core
4979
4980 @param[in] MpService The MP servicde protocol (used to retrievel MP info)
4981
4982 @retval EFI_SUCCESS The driver installed without error.
4983
4984 **/
4985 EFI_STATUS
4986 SortCpuLocalApicInTable (
4987 IN EFI_MP_SERVICES_PROTOCOL *MpService
4988 )
4989 {
4990 EFI_PROCESSOR_INFORMATION *MpContext;
4991 UINT8 Index;
4992 UINTN BspIndex;
4993 UINT8 CurrProcessor;
4994 EFI_STATUS Status;
4995 UINT8 MaxCpuCore;
4996 UINT8 MaxCpuThread;
4997
4998 MpContext = NULL;
4999 MaxCpuCore = 0;
5000 MaxCpuThread = 0;
5001
5002 Status = MpService->WhoAmI (
5003 MpService,
5004 &BspIndex
5005 );
5006
5007 //
5008 // Fill mCpuApicIdOrderTable
5009 //
5010 for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
5011
5012 MpContext = AllocatePool (sizeof(EFI_PROCESSOR_INFORMATION));
5013 ASSERT (MpContext != NULL);
5014 Status = MpService->GetProcessorInfo (
5015 MpService,
5016 CurrProcessor,
5017 MpContext
5018 );
5019 ASSERT_EFI_ERROR (Status);
5020
5021 if (MpContext == NULL) {
5022 return Status;
5023 }
5024 mCpuApicIdOrderTable[CurrProcessor].ApicId = (UINT32) MpContext->ProcessorId;
5025 DEBUG((DEBUG_INFO, "The CurrProcessor 0x%x ApicId is 0x%x\n", CurrProcessor, mCpuApicIdOrderTable[CurrProcessor].ApicId));
5026 mCpuApicIdOrderTable[CurrProcessor].Flags = (MpContext->StatusFlag & PROCESSOR_ENABLED_BIT)? 1: 0;
5027 mCpuApicIdOrderTable[CurrProcessor].Package = (UINT8) MpContext->Location.Package;
5028 mCpuApicIdOrderTable[CurrProcessor].Die = (UINT8) 0;
5029 mCpuApicIdOrderTable[CurrProcessor].Core = (UINT8) MpContext->Location.Core;
5030 mCpuApicIdOrderTable[CurrProcessor].Thread = (UINT8) MpContext->Location.Thread;
5031
5032 if (MaxCpuThread < (UINT8) MpContext->Location.Thread) {
5033 MaxCpuThread = (UINT8) MpContext->Location.Thread;
5034 }
5035
5036 if (MaxCpuCore < (UINT8) MpContext->Location.Core) {
5037 MaxCpuCore = (UINT8) MpContext->Location.Core;
5038 }
5039 }
5040
5041 //
5042 // Do some statistics about the SBSP package
5043 //
5044 for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
5045 if (CurrProcessor == BspIndex) {
5046 mSbspPackageInfo.BspApicId = mCpuApicIdOrderTable[CurrProcessor].ApicId;
5047 mSbspPackageInfo.PackageNo = mCpuApicIdOrderTable[CurrProcessor].Package;
5048 mSbspPackageInfo.TotalThreads = 0;
5049 mSbspPackageInfo.CoreNo = 0;
5050 mSbspPackageInfo.LogicalThreadNo = 0;
5051 }
5052 }
5053
5054 for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
5055 if (mCpuApicIdOrderTable[CurrProcessor].Package == mSbspPackageInfo.PackageNo) {
5056 mSbspPackageInfo.TotalThreads++;
5057 if (mCpuApicIdOrderTable[CurrProcessor].Thread == 0) {
5058 mSbspPackageInfo.CoreNo++;
5059 } else {
5060 mSbspPackageInfo.LogicalThreadNo++;
5061 }
5062 }
5063 }
5064
5065 //
5066 // Output debug info
5067 //
5068 for (Index = 0; Index < mNumberOfCpus; Index++) {
5069 DEBUG((DEBUG_INFO, "Package = %x, Die = %x, Core = %x, Thread = %x, ApicId = %x\n", \
5070 mCpuApicIdOrderTable[Index].Package, \
5071 mCpuApicIdOrderTable[Index].Die, \
5072 mCpuApicIdOrderTable[Index].Core, \
5073 mCpuApicIdOrderTable[Index].Thread, \
5074 mCpuApicIdOrderTable[Index].ApicId));
5075 }
5076
5077 DEBUG((DEBUG_INFO, "MaxCpuCore = %x\n", MaxCpuCore));
5078 DEBUG((DEBUG_INFO, "MaxCpuThread = %x\n\n", MaxCpuThread));
5079 DEBUG((DEBUG_INFO, "mSbspPackageInfo.BspApicId = %x\n", mSbspPackageInfo.BspApicId));
5080 DEBUG((DEBUG_INFO, "mSbspPackageInfo.TotalThreads = %x\n", mSbspPackageInfo.TotalThreads));
5081 DEBUG((DEBUG_INFO, "mSbspPackageInfo.PackageNo = %x\n", mSbspPackageInfo.PackageNo));
5082 DEBUG((DEBUG_INFO, "mSbspPackageInfo.CoreNo = %x\n", mSbspPackageInfo.CoreNo));
5083 DEBUG((DEBUG_INFO, "mSbspPackageInfo.LogicalThreadNo = %x\n", mSbspPackageInfo.LogicalThreadNo));
5084
5085 //
5086 // First entry is always SBSP
5087 //
5088 CurrProcessor = 0;
5089 mCpuApicIdReorderTable[CurrProcessor].ApicId = mSbspPackageInfo.BspApicId;
5090 mCpuApicIdReorderTable[CurrProcessor].Package = mSbspPackageInfo.PackageNo;
5091 mCpuApicIdReorderTable[CurrProcessor].Flags = 1;
5092 CurrProcessor++;
5093
5094 //
5095 // Output debug info
5096 //
5097 for (Index = 0; Index < mNumberOfCpus; Index++) {
5098 DEBUG((DEBUG_INFO, "Index = %x, ApicId = %x, Package = %x\n", \
5099 Index, \
5100 mCpuApicIdOrderTable[Index].ApicId, \
5101 mCpuApicIdOrderTable[Index].Package));
5102 }
5103
5104 FreePool (MpContext);
5105
5106 return EFI_SUCCESS;
5107 }
5108
5109
5110 EFI_STATUS
5111 AppendCpuMapTableEntry (
5112 IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
5113 IN UINT32 LocalApicCounter
5114 )
5115 {
5116 EFI_STATUS Status = EFI_SUCCESS;
5117 EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *LocalX2ApicPtr;
5118
5119 if (AcpiLocalApic->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) {
5120 if (LocalApicCounter < mNumberOfCpus) {
5121 AcpiLocalApic->Flags = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
5122 AcpiLocalApic->ApicId = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
5123 //
5124 // Make AcpiProcessorIds 0-based
5125 //
5126 AcpiLocalApic->AcpiProcessorId = (UINT8)LocalApicCounter;
5127 } else {
5128 AcpiLocalApic->Flags = 0;
5129 AcpiLocalApic->ApicId = 0xFF;
5130 //
5131 // Make AcpiProcessorIds 0-based
5132 //
5133 AcpiLocalApic->AcpiProcessorId = (UINT8)LocalApicCounter;
5134 Status = EFI_UNSUPPORTED;
5135 }
5136
5137 //
5138 // Display the results
5139 //
5140 DEBUG((DEBUG_INFO, "AcpiLocalApic: AcpiProcessorId=%x, ApicId=%x, Flags=%x\n", \
5141 AcpiLocalApic->AcpiProcessorId, \
5142 AcpiLocalApic->ApicId, \
5143 AcpiLocalApic->Flags));
5144 } else if (AcpiLocalApic->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
5145 LocalX2ApicPtr = (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *)AcpiLocalApic;
5146 if (LocalApicCounter < mNumberOfCpus) {
5147 LocalX2ApicPtr->Flags = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
5148 LocalX2ApicPtr->X2ApicId = mCpuApicIdOrderTable[LocalApicCounter].ApicId;
5149 LocalX2ApicPtr->AcpiProcessorUid = LocalApicCounter;
5150 } else {
5151 LocalX2ApicPtr->Flags = 0;
5152 LocalX2ApicPtr->X2ApicId = (UINT32)-1;
5153 LocalX2ApicPtr->AcpiProcessorUid = LocalApicCounter;
5154 Status = EFI_UNSUPPORTED;
5155 }
5156 //
5157 // Display the results
5158 //
5159 DEBUG((DEBUG_INFO, "AcpiLocalx2Apic: AcpiProcessorId=%x, ApicId=%x, Flags=%x\n", \
5160 LocalX2ApicPtr->AcpiProcessorUid, \
5161 LocalX2ApicPtr->X2ApicId, \
5162 LocalX2ApicPtr->Flags));
5163 } else {
5164 Status = EFI_UNSUPPORTED;
5165 }
5166 return Status;
5167 }
5168
5169 /**
5170 I/O work flow to wait input buffer empty in given time.
5171
5172 @param[in] Timeout Wating time.
5173
5174 @retval EFI_TIMEOUT if input is still not empty in given time.
5175 @retval EFI_SUCCESS input is empty.
5176 **/
5177 EFI_STATUS
5178 WaitInputEmpty (
5179 IN UINTN Timeout
5180 )
5181 {
5182 UINTN Delay;
5183 UINT8 Data;
5184
5185 Delay = Timeout / 50;
5186
5187 do {
5188 Data = IoRead8 (KBC_CMD_STS_PORT);
5189
5190 //
5191 // Check keyboard controller status bit 0 and 1 (Output Buffer and Input Buffer status)
5192 //
5193 if ((Data & KBC_OUTB) != 0) {
5194 IoRead8 (KBC_DATA_PORT);
5195 } else if ((Data & KBC_INPB) == 0) {
5196 break;
5197 }
5198
5199 gBS->Stall (50);
5200 Delay--;
5201 } while (Delay != 0);
5202
5203 if (Delay == 0) {
5204 return EFI_TIMEOUT;
5205 }
5206
5207 return EFI_SUCCESS;
5208 }
5209
5210 /**
5211 I/O work flow to wait output buffer full in given time.
5212
5213 @param[in] Timeout given time
5214
5215 @retval EFI_TIMEOUT output is not full in given time
5216 @retval EFI_SUCCESS output is full in given time.
5217 **/
5218 EFI_STATUS
5219 WaitOutputFull (
5220 IN UINTN Timeout
5221 )
5222 {
5223 UINTN Delay;
5224 UINT8 Data;
5225
5226 Delay = Timeout / 50;
5227
5228 do {
5229 Data = IoRead8 (KBC_CMD_STS_PORT);
5230
5231 //
5232 // Check keyboard controller status bit 0(output buffer status)
5233 // & bit5(output buffer for auxiliary device)
5234 //
5235 if ((Data & (KBC_OUTB | KBC_AUXB)) == (KBC_OUTB | KBC_AUXB)) {
5236 break;
5237 }
5238
5239 gBS->Stall (50);
5240 Delay--;
5241 } while (Delay != 0);
5242
5243 if (Delay == 0) {
5244 return EFI_TIMEOUT;
5245 }
5246
5247 return EFI_SUCCESS;
5248 }
5249
5250 /**
5251 I/O work flow of in 8042 Aux data.
5252
5253 @param Data Buffer holding return value.
5254
5255 @retval EFI_SUCCESS Success to excute I/O work flow
5256 @retval EFI_TIMEOUT Keyboard controller time out.
5257 **/
5258 EFI_STATUS
5259 In8042AuxData (
5260 IN OUT UINT8 *Data
5261 )
5262 {
5263 EFI_STATUS Status;
5264
5265 //
5266 // wait for output data
5267 //
5268 Status = WaitOutputFull (BAT_TIMEOUT);
5269 if (EFI_ERROR (Status)) {
5270 return Status;
5271 }
5272
5273 *Data = IoRead8 (KBC_DATA_PORT);
5274
5275 return EFI_SUCCESS;
5276 }
5277
5278 /**
5279 I/O work flow of outing 8042 Aux command.
5280
5281 @param Command Aux I/O command
5282
5283 @retval EFI_SUCCESS Success to excute I/O work flow
5284 @retval EFI_TIMEOUT Keyboard controller time out.
5285 **/
5286 EFI_STATUS
5287 Out8042AuxCommand (
5288 IN UINT8 Command
5289 )
5290 {
5291 EFI_STATUS Status;
5292 UINT8 Data;
5293
5294 //
5295 // Wait keyboard controller input buffer empty
5296 //
5297 Status = WaitInputEmpty (TIMEOUT);
5298 if (EFI_ERROR (Status)) {
5299 return Status;
5300 }
5301 //
5302 // Send write to auxiliary device command
5303 //
5304 Data = WRITE_AUX_DEV;
5305 IoWrite8 (KBC_CMD_STS_PORT, Data);
5306
5307 Status = WaitInputEmpty (TIMEOUT);
5308 if (EFI_ERROR (Status)) {
5309 return Status;
5310 }
5311 //
5312 // Send auxiliary device command
5313 //
5314 IoWrite8 (KBC_DATA_PORT, Command);
5315
5316 //
5317 // Read return code
5318 //
5319 Status = In8042AuxData (&Data);
5320 if (EFI_ERROR (Status)) {
5321 return Status;
5322 }
5323
5324 if (Data == PS2_ACK) {
5325 //
5326 // Receive mouse acknowledge, command send success
5327 //
5328 return EFI_SUCCESS;
5329
5330 } else if (Data == PS2_RESEND) {
5331 //
5332 // Resend command
5333 //
5334 Status = Out8042AuxCommand (Command);
5335 if (EFI_ERROR (Status)) {
5336 return Status;
5337 }
5338
5339 } else {
5340 //
5341 // Invalid return code
5342 //
5343 return EFI_DEVICE_ERROR;
5344
5345 }
5346
5347 return EFI_SUCCESS;
5348 }
5349
5350 /**
5351 Issue command to enable Ps2 mouse.
5352
5353 @return Status of command issuing.
5354 **/
5355 EFI_STATUS
5356 PS2MouseEnable (
5357 VOID
5358 )
5359 {
5360 //
5361 // Send auxiliary command to enable mouse
5362 //
5363 return Out8042AuxCommand (ENABLE_CMD);
5364 }
5365
5366 /**
5367 Check whether there is Ps/2 mouse device in system
5368
5369 @retval TRUE - Keyboard in System.
5370 @retval FALSE - Keyboard not in System.
5371
5372 **/
5373 BOOLEAN
5374 IsPs2MouseConnected (
5375 VOID
5376 )
5377 {
5378 EFI_STATUS Status;
5379
5380 Status = PS2MouseEnable ();
5381
5382 if (!EFI_ERROR (Status)) {
5383 return TRUE;
5384 }
5385
5386 return FALSE;
5387 }
LocateSupportProtocol
EFI_STATUS LocateSupportProtocol(IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol.
Definition: AcpiPlatform.c:451
Mcfg.h
This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG).
IsPs2MouseConnected
BOOLEAN IsPs2MouseConnected(VOID)
Check whether there is Ps/2 mouse device in system.
Definition: AcpiPlatform.c:5374
AllocateMemoryBelow4G
EFI_STATUS AllocateMemoryBelow4G(IN EFI_MEMORY_TYPE MemoryType, IN UINTN Size, OUT VOID **Buffer)
Allocate MemoryType below 4G memory address.
Definition: AcpiPlatform.c:2334
In8042AuxData
EFI_STATUS In8042AuxData(IN OUT UINT8 *Data)
I/O work flow of in 8042 Aux data.
Definition: AcpiPlatform.c:5259
InstallXhciAcpiTable
VOID InstallXhciAcpiTable(VOID)
Install Xhci ACPI Table.
Definition: AcpiPlatform.c:238
Out8042AuxCommand
EFI_STATUS Out8042AuxCommand(IN UINT8 Command)
I/O work flow of outing 8042 Aux command.
Definition: AcpiPlatform.c:5287
InstallAcpiPlatform
EFI_STATUS InstallAcpiPlatform(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
ACPI Platform driver installation function.
Definition: AcpiPlatform.c:2625
GetEcGpeNumber
UINT32 GetEcGpeNumber(VOID)
This function will provide the EC GPE number for ECDT update according to platform design.
Definition: AcpiPlatform.c:580
GenSsdtLib.h
This is an implementation of the ACPI platform driver.
IsHardwareChange
VOID IsHardwareChange(VOID)
This function calculates RCR based on PCI Device ID and Vendor ID from the devices available on the p...
Definition: AcpiPlatform.c:2127
WaitInputEmpty
EFI_STATUS WaitInputEmpty(IN UINTN Timeout)
I/O work flow to wait input buffer empty in given time.
Definition: AcpiPlatform.c:5178
WaitOutputFull
EFI_STATUS WaitOutputFull(IN UINTN Timeout)
I/O work flow to wait output buffer full in given time.
Definition: AcpiPlatform.c:5219
AcpiPlatform.h
This is an implementation of the Advanced ACPI driver.
AcpiGnvsInit
EFI_STATUS AcpiGnvsInit(IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize.
Definition: AcpiGnvsInit.c:56
InstallSocAcpiTable
VOID STATIC InstallSocAcpiTable(IN EFI_GUID *SsdtTableGuid, IN UINT64 Signature)
Install Soc ACPI Table.
Definition: AcpiPlatform.c:102
SetAcpiSetupVariables
EFI_STATUS SetAcpiSetupVariables(VOID)
Save Acpi Setup relatived variables.
Definition: AcpiPlatform.c:2561
PlatformUpdateTables
EFI_STATUS PlatformUpdateTables(IN OUT EFI_ACPI_COMMON_HEADER *Table, IN OUT EFI_ACPI_TABLE_VERSION *Version)
This function will update any runtime platform specific information.
Definition: AcpiPlatform.c:616
GuidStringToAcpiBuffer
EFI_STATUS GuidStringToAcpiBuffer(IN CHAR16 *GuidString, OUT UINT64 *AcpiGuidPart1, OUT UINT64 *AcpiGuidPart2)
Convert string containing GUID in the canonical form: "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp" where aa...
Definition: AcpiPlatform.c:2504
SortCpuLocalApicInTable
EFI_STATUS SortCpuLocalApicInTable(IN EFI_MP_SERVICES_PROTOCOL *MpService)
Sort ordering of CPUs according to the priorities of cores and threads.
Definition: AcpiPlatform.c:4986
GenerateSsdtFromConfigFile
EFI_STATUS GenerateSsdtFromConfigFile(VOID)
Generate SSDTs from ACPI data available in BIOS board files or ACPI data generated from PCT tool FVs.
Definition: GenSsdtLib.c:413
PS2MouseEnable
EFI_STATUS PS2MouseEnable(VOID)
Issue command to enable Ps2 mouse.
Definition: AcpiPlatform.c:5356


AlderLake Board Code: AcpiPlatform.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
AcpiPlatform.h
Go to the documentation of this file.
1 /** @file
2 This is an implementation of the Advanced ACPI driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ACPI_PLATFORM_H_
36 #define _ACPI_PLATFORM_H_
37
38 //
39 // Statements that include other header files
40 //
41
42 #include <IndustryStandard/Acpi.h>
43 #include <Guid/EventGroup.h>
44 #include <Guid/GlobalVariable.h>
45 #include <Library/UefiLib.h>
46 #include <Library/UefiBootServicesTableLib.h>
47 #include <Library/UefiRuntimeServicesTableLib.h>
48 #include <Library/DebugLib.h>
49 #include <Library/BaseMemoryLib.h>
50 #include <Library/MemoryAllocationLib.h>
51 #include <Library/IoLib.h>
52 #include <Library/PcdLib.h>
53 #include <Library/LocalApicLib.h>
54 #include <Protocol/CpuIo2.h>
55 #include <Protocol/AcpiTable.h>
56 #include <Protocol/PciRootBridgeIo.h>
57 #include <Protocol/MpService.h>
58 #include <Register/Cpuid.h>
59 #include <Protocol/PciIo.h>
60 #include <Library/PchCycleDecodingLib.h>
61
62 #include <IndustryStandard/HighPrecisionEventTimerTable.h>
63 #include <Library/DxeAcpiGnvsInitLib.h>
64
65 #include <Register/PchRegs.h>
66 #include <Register/SaRegsHostBridge.h>
67
68 //
69 // Produced protocols
70 //
71 #include <Protocol/PlatformNvsArea.h>
72
73 #include <Platform.h>
74 #include <Library/AslUpdateLib.h>
75 #include <SetupVariable.h>
76 #include <Library/EcMiscLib.h>
77
78 #include <Acpi/AcpiTables/Fadt/Fadt6.3.h>
79
80 //
81 // ACPI table information used to initialize tables.
82 //
83
84 #define NAT_CONFIG_INDEX 0x2E
85 #define NAT_CONFIG_DATA 0x2F
86 #define WPCN381U_CONFIG_INDEX 0x2E
87 #define WPCN381U_CONFIG_DATA 0x2F
88 #define WPCN381U_CHIP_ID 0xF4
89 #define WDCP376_CHIP_ID 0xF1
90 #define Smsc1007_CONFIG_INDEX 0x164E
91 #define SMSC1000_CONFIG_INDEX 0x4E
92
93 #define KBC_DATA_PORT 0x60
94 #define KBC_CMD_STS_PORT 0x64
95
96 #define ENABLE_CMD 0xf4
97 #define WRITE_AUX_DEV 0xd4
98
99 #define PS2_ACK 0xfa
100 #define PS2_RESEND 0xfe
101
102 #define KBC_INPB 0x02
103 #define KBC_OUTB 0x01
104 #define KBC_AUXB 0x20
105
106 #define TIMEOUT 50000
107 #define BAT_TIMEOUT 5000
108
109 #define IO_EXPANDER_DISABLED 0xFF
110
111 typedef struct {
112 UINT32 ApicId;
113 UINT32 Flags;
114 UINT8 Package;
115 UINT8 Die;
116 UINT8 Core;
117 UINT8 Thread;
118 } EFI_CPU_ID_ORDER_MAP;
119
120 typedef struct {
121 UINT8 Package;
122 UINT32 ApicId;
123 UINT32 Flags;
124 } EFI_CPU_APIC_ID_REORDER_MAP;
125
126 typedef struct {
127 UINT32 BspApicId;
128 UINT8 TotalThreads;
129 UINT8 PackageNo;
130 UINT8 CoreNo;
131 UINT8 LogicalThreadNo;
132 } EFI_CPU_PACKAGE_INFO;
133
134 //
135 // Function definitions
136 //
137 EFI_STATUS
138 LocateSupportProtocol (
139 IN EFI_GUID *Protocol,
140 IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
141 OUT VOID **Instance,
142 IN BOOLEAN Type
143 );
144
145 /**
146 Entry point of the ACPI platform driver.
147
148 @param[in] ImageHandle A handle for the image that is initializing this driver
149 @param[in] SystemTable A pointer to the EFI system table
150
151 @retval EFI_SUCCESS The driver installed without error.
152 @retval EFI_ABORTED The driver encountered an error and could not complete
153 installation of the ACPI tables.
154 **/
155 EFI_STATUS
156 EFIAPI
157 InstallAcpiPlatform (
158 IN EFI_HANDLE ImageHandle,
159 IN EFI_SYSTEM_TABLE *SystemTable
160 );
161
162 EFI_STATUS
163 SortCpuLocalApicInTable (
164 IN EFI_MP_SERVICES_PROTOCOL *MpService
165 );
166
167 EFI_STATUS
168 AppendCpuMapTableEntry (
169 IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
170 IN UINT32 LocalApicCounter
171 );
172
173 BOOLEAN
174 IsPs2MouseConnected (
175 VOID
176 );
177
178 #endif
SortCpuLocalApicInTable
EFI_STATUS SortCpuLocalApicInTable(IN EFI_MP_SERVICES_PROTOCOL *MpService)
Sort ordering of CPUs according to the priorities of cores and threads.
Definition: AcpiPlatform.c:4986
LocateSupportProtocol
EFI_STATUS LocateSupportProtocol(IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol.
Definition: AcpiPlatform.c:451
Fadt6.3.h
This file describes the contents of the ACPI Fixed ACPI Description Table (FADT).
IsPs2MouseConnected
BOOLEAN IsPs2MouseConnected(VOID)
Check whether there is Ps/2 mouse device in system.
Definition: AcpiPlatform.c:5374
InstallAcpiPlatform
EFI_STATUS InstallAcpiPlatform(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point of the ACPI platform driver.
Definition: AcpiPlatform.c:2625


AlderLake Board Code: AdvancedPmaxDxe.c Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
AdvancedPmaxDxe.c
Go to the documentation of this file.
1 /** @file
2 Advanced PMAX table install and update driver
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 **/
33
34 #include <Library/BaseLib.h>
35 #include <Library/BaseMemoryLib.h>
36 #include <Library/DebugLib.h>
37 #include <Library/MemoryAllocationLib.h>
38 #include <Library/UefiBootServicesTableLib.h>
39 #include <Protocol/FirmwareVolume2.h>
40 #include <IndustryStandard/AcpiAml.h>
41 #include <Library/AslUpdateLib.h>
42 #include <Library/PcdLib.h>
43 #include <PlatformBoardConfig.h>
44 #include <PmaxDevDef.h>
45
46 /**
47 Calculate the string length, will include NULL-terminated.
48
49 @param[in] StrPtr Point to the string.
50
51 @retval String length.
52 **/
53 UINTN
54 GetStrLength (
55 IN CHAR8 *StrPtr
56 )
57 {
58 UINTN StrLength;
59
60 StrLength = AsciiStrLen (StrPtr);
61
62 return (StrLength + 1);
63
64 }
65
66 /**
67 Install the PMAX table.
68
69 @param[in] Table Point to PMAX table..
70
71 @retval EFI_SUCCESS Install table success.
72 @retval Other The function encountered an error and could not complete process.
73 **/
74 EFI_STATUS
75 InstallTable (
76 IN EFI_ACPI_DESCRIPTION_HEADER *Table
77 )
78 {
79 EFI_STATUS Status;
80 EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;
81 UINTN TableKey;
82
83 mAcpiTable = NULL;
84 TableKey = 0;
85
86 //
87 // Locate ACPI Table protocol.
88 //
89 Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &mAcpiTable);
90 //
91 // Install table.
92 //
93 if (!EFI_ERROR (Status)) {
94 Status = mAcpiTable->InstallAcpiTable (mAcpiTable, Table, Table->Length, &TableKey);
95 }
96
97 FreePool (Table);
98
99 return Status;
100 }
101
102 /**
103 Get PCD and update the values.
104
105 @param[in, out] PmaxTable Point to PMAX table.
106
107 @retval EFI_SUCCESS The function completed successfully.
108 @retval Other The function encountered an error and could not complete process.
109 **/
110 EFI_STATUS
111 UpdatePmaxTable (
112 IN OUT EFI_ACPI_DESCRIPTION_HEADER *PmaxTable
113 )
114 {
115 VPD_PMAX_DEV *PmaxCfg;
116 UINT8 Index;
117 UINT8 *CurrPtr;
118 UINT8 *TableEndPtr;
119 UINT32 *NameStrPtr;
120 UINT8 *DataPtr;
121
122 CurrPtr = NULL;
123 TableEndPtr = NULL;
124 NameStrPtr = NULL;
125 DataPtr = NULL;
126
127 //
128 // Get PCD and check the values.
129 //
130 PmaxCfg = PcdGetPtr (VpdPcdPmaxDevices);
131 for (Index = 0; Index < 4; Index ++) {
132 if ((GetStrLength (PmaxCfg[Index].DevStr) > MAX_PMAX_DEVICE_STRING_LENGTH) ||
133 (PmaxCfg[Index].DevD0 > MAX_PEAK_POWER_VALUE) || (PmaxCfg[Index].DevDx > MAX_PEAK_POWER_VALUE)) {
134 return EFI_INVALID_PARAMETER;
135 }
136 }
137
138 CurrPtr = (UINT8 *) PmaxTable;
139 TableEndPtr = CurrPtr + PmaxTable->Length;
140
141 //
142 // Loop through the aml code looking for values that need to be updated.
143 //
144 for (; CurrPtr < TableEndPtr; CurrPtr++) {
145 //
146 // Find name aml op code and determine the values need to be updated.
147 //
148 if ((*CurrPtr) == AML_NAME_OP) {
149 NameStrPtr = (UINT32 *) (CurrPtr + 1);
150 DataPtr = CurrPtr + 6;
151
152 switch (*NameStrPtr) {
153 case (SIGNATURE_32 ('R','T','K','S')):
154 //
155 // To keep the PMAX table in fixed size, fill the vacancy of the string buffer with AML NO OP.
156 // This will makes PMAX table shows numerous "NoOp" after device name.
157 //
158 SetMem (DataPtr, MAX_PMAX_DEVICE_STRING_LENGTH, AML_NOOP_OP);
159 CopyMem (DataPtr, PmaxCfg[0].DevStr, GetStrLength (PmaxCfg[0].DevStr));
160 break;
161
162 case (SIGNATURE_32 ('R','T','K','0')):
163 CopyMem (DataPtr, &(PmaxCfg[0].DevD0), sizeof (UINT16));
164 break;
165
166 case (SIGNATURE_32 ('R','T','K','X')):
167 CopyMem (DataPtr, &(PmaxCfg[0].DevDx), sizeof (UINT16));
168 break;
169
170 case (SIGNATURE_32 ('W','F','C','S')):
171 //
172 // To keep the PMAX table in fixed size, fill the vacancy of the string buffer with AML NO OP.
173 // This will makes PMAX table shows numerous "NoOp" after device name.
174 //
175 SetMem (DataPtr, MAX_PMAX_DEVICE_STRING_LENGTH, AML_NOOP_OP);
176 CopyMem (DataPtr, PmaxCfg[1].DevStr, GetStrLength (PmaxCfg[1].DevStr));
177 break;
178
179 case (SIGNATURE_32 ('W','F','C','0')):
180 CopyMem (DataPtr, &(PmaxCfg[1].DevD0), sizeof (UINT16));
181 break;
182
183 case (SIGNATURE_32 ('W','F','C','X')):
184 CopyMem (DataPtr, &(PmaxCfg[1].DevDx), sizeof (UINT16));
185 break;
186
187 case (SIGNATURE_32 ('U','F','C','S')):
188 //
189 // To keep the PMAX table in fixed size, fill the vacancy of the string buffer with AML NO OP.
190 // This will makes PMAX table shows numerous "NoOp" after device name.
191 //
192 SetMem (DataPtr, MAX_PMAX_DEVICE_STRING_LENGTH, AML_NOOP_OP);
193 CopyMem (DataPtr, PmaxCfg[2].DevStr, GetStrLength (PmaxCfg[1].DevStr));
194 break;
195
196 case (SIGNATURE_32 ('U','F','C','0')):
197 CopyMem (DataPtr, &(PmaxCfg[2].DevD0), sizeof (UINT16));
198 break;
199
200 case (SIGNATURE_32 ('U','F','C','X')):
201 CopyMem (DataPtr, &(PmaxCfg[2].DevDx), sizeof (UINT16));
202 break;
203
204 case (SIGNATURE_32 ('F','L','D','S')):
205 //
206 // To keep the PMAX table in fixed size, fill the vacancy of the string buffer with AML NO OP.
207 // This will makes PMAX table shows numerous "NoOp" after device name.
208 //
209 SetMem (DataPtr, MAX_PMAX_DEVICE_STRING_LENGTH, AML_NOOP_OP);
210 CopyMem (DataPtr, PmaxCfg[3].DevStr, GetStrLength (PmaxCfg[1].DevStr));
211 break;
212
213 case (SIGNATURE_32 ('F','L','D','0')):
214 CopyMem (DataPtr, &(PmaxCfg[3].DevD0), sizeof (UINT16));
215 break;
216
217 case (SIGNATURE_32 ('F','L','D','X')):
218 CopyMem (DataPtr, &(PmaxCfg[3].DevDx), sizeof (UINT16));
219 break;
220
221 default:
222 break;
223 }
224 }
225 }
226
227 return EFI_SUCCESS;
228 }
229
230
231 /**
232 Find PMAX SSDT Table.
233
234 @param[out] PmaxTable Point to PMAX table.
235
236 @retval EFI_SUCCESS Find PMAX table successfully.
237 @retval Other The function encountered an error and could not complete process.
238 **/
239 EFI_STATUS
240 FindPmaxTable (
241 OUT EFI_ACPI_DESCRIPTION_HEADER **PmaxTable
242 )
243 {
244 EFI_STATUS Status;
245 EFI_HANDLE *HandleBuffer;
246 UINTN NumberOfHandles;
247 UINTN Index;
248 INTN Instance;
249 UINTN Size;
250 UINT32 FvStatus;
251 EFI_FV_FILETYPE FileType;
252 EFI_FV_FILE_ATTRIBUTES Attributes;
253 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
254 EFI_ACPI_COMMON_HEADER *Table;
255
256 Instance = 0;
257 FwVol = NULL;
258 Table = NULL;
259
260 //
261 // Locate FV protocol.
262 //
263 Status = gBS->LocateHandleBuffer (
264 ByProtocol,
265 &gEfiFirmwareVolume2ProtocolGuid,
266 NULL,
267 &NumberOfHandles,
268 &HandleBuffer
269 );
270
271 //
272 // Look for FV with ACPI storage file
273 //
274 for (Index = 0; Index < NumberOfHandles; Index++) {
275 //
276 // Get the protocol on this handle
277 //
278 Status = gBS->HandleProtocol (
279 HandleBuffer[Index],
280 &gEfiFirmwareVolume2ProtocolGuid,
281 (VOID **) &FwVol
282 );
283 if (FwVol == NULL) {
284 return EFI_NOT_FOUND;
285 }
286
287 //
288 // See if it has the ACPI storage file
289 //
290 Size = 0;
291 FvStatus = 0;
292 Status = FwVol->ReadFile (
293 FwVol,
294 &gPmaxAcpiTableStorageGuid,
295 NULL,
296 &Size,
297 &FileType,
298 &Attributes,
299 &FvStatus
300 );
301 if (!EFI_ERROR (Status)) {
302 break;
303 }
304 }
305 //
306 // Free any allocated buffers
307 //
308 FreePool (HandleBuffer);
309
310 //
311 // Check that we found the data file
312 //
313 if (FwVol == NULL) {
314 return EFI_NOT_FOUND;
315 }
316
317 //
318 // Read tables from the storage file.
319 //
320 while (Status == EFI_SUCCESS) {
321 //
322 // Read the ACPI tables
323 //
324 Status = FwVol->ReadSection (
325 FwVol,
326 &gPmaxAcpiTableStorageGuid,
327 EFI_SECTION_RAW,
328 Instance,
329 (VOID **) &Table,
330 &Size,
331 &FvStatus
332 );
333 if (!EFI_ERROR (Status)) {
334 *PmaxTable = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
335
336 if ((*PmaxTable)->OemTableId == SIGNATURE_64 ('P', 'm', 'a', 'x', '_', 'D', 'e', 'v')) {
337 return Status;
338 }
339
340 //
341 // Increase the instance
342 //
343 Instance++;
344 Table = NULL;
345 }
346 }
347 return Status;
348 }
349
350 /**
351 PMAX table installation driver.
352
353 @param[in] ImageHandle Handle for this drivers loaded image protocol.
354 @param[in] SystemTable EFI system table.
355
356 @retval EFI_SUCCESS The driver installed without error.
357 @retval Other The driver encountered an error and could not complete installation of
358 the ACPI tables.
359
360 **/
361 EFI_STATUS
362 EFIAPI
363 InstallPmaxTable (
364 IN EFI_HANDLE ImageHandle,
365 IN EFI_SYSTEM_TABLE *SystemTable
366 )
367 {
368 EFI_STATUS Status;
369 EFI_ACPI_DESCRIPTION_HEADER *PmaxTable;
370
371 PmaxTable = NULL;
372
373 //
374 // Find default PMAX table.
375 //
376 Status = FindPmaxTable (&PmaxTable);
377
378 //
379 // Update PMAX table.
380 //
381 if ((!EFI_ERROR (Status)) && (PmaxTable != NULL)) {
382 Status = UpdatePmaxTable (PmaxTable);
383 }
384
385 //
386 // Install PMAX table.
387 //
388 if ((!EFI_ERROR (Status)) && (PmaxTable != NULL)) {
389 Status = InstallTable (PmaxTable);
390 }
391
392 return Status;
393 }
394
395
InstallPmaxTable
EFI_STATUS InstallPmaxTable(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
PMAX table installation driver.
Definition: AdvancedPmaxDxe.c:363
GetStrLength
UINTN GetStrLength(IN CHAR8 *StrPtr)
Calculate the string length, will include NULL-terminated.
Definition: AdvancedPmaxDxe.c:54
InstallTable
EFI_STATUS InstallTable(IN EFI_ACPI_DESCRIPTION_HEADER *Table)
Install the PMAX table.
Definition: AdvancedPmaxDxe.c:75
FindPmaxTable
EFI_STATUS FindPmaxTable(OUT EFI_ACPI_DESCRIPTION_HEADER **PmaxTable)
Find PMAX SSDT Table.
Definition: AdvancedPmaxDxe.c:240
UpdatePmaxTable
EFI_STATUS UpdatePmaxTable(IN OUT EFI_ACPI_DESCRIPTION_HEADER *PmaxTable)
Get PCD and update the values.
Definition: AdvancedPmaxDxe.c:111


AlderLake Board Code: BoardAcpiDxe.c Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • BoardAcpiDxe
BoardAcpiDxe.c
Go to the documentation of this file.
1 /** @file
2 Board ACPI Driver
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Base.h>
36 #include <Uefi.h>
37 #include <IndustryStandard/Acpi.h>
38 #include <Library/UefiLib.h>
39 #include <Library/UefiBootServicesTableLib.h>
40 #include <Library/UefiRuntimeServicesTableLib.h>
41 #include <Library/DebugLib.h>
42 #include <Library/BaseMemoryLib.h>
43 #include <Library/IoLib.h>
44 #include <Library/PcdLib.h>
45 #include <Library/PciLib.h>
46 #include <Library/BoardAcpiTableLib.h>
47 #include <Library/MemoryAllocationLib.h>
48 #include <Library/AslUpdateLib.h>
49
50 #include <Protocol/PlatformNvsArea.h>
51 #include <Protocol/FirmwareVolume2.h>
52 #include <Protocol/AcpiTable.h>
53
54 GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL mPlatformNvsAreaProtocol;
55
56 /**
57 @brief
58 Global NVS initialize.
59
60 @param[in] PlatformNvsAreaPtr - Pointer of global NVS area
61
62 @retval EFI_SUCCESS - Allocate Global NVS completed.
63 @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS.
64 **/
65 EFI_STATUS
66 EFIAPI
67 AcpiGnvsInit (
68 IN OUT VOID **PlatformNvsAreaPtr
69 );
70
71 VOID
72 UpdateDsdt (
73 IN VOID *Table
74 );
75
76 //
77 // Function implementations
78 //
79
80 /**
81 Locate the first instance of a protocol. If the protocol requested is an
82 FV protocol, then it will return the first FV that contains the ACPI table
83 storage file.
84
85 @param[in] Protocol The protocol to find.
86 @param[in] Instance Return pointer to the first instance of the protocol.
87 @param[in] Type TRUE if the desired protocol is a FV protocol.
88
89 @retval EFI_SUCCESS The function completed successfully.
90 @retval EFI_NOT_FOUND The protocol could not be located.
91 @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
92 **/
93 EFI_STATUS
94 LocateSupportProtocol (
95 IN EFI_GUID *Protocol,
96 IN EFI_GUID *gEfiAcpiMultiTableStorageGuid,
97 OUT VOID **Instance,
98 IN BOOLEAN Type
99 )
100 {
101 EFI_STATUS Status;
102 EFI_HANDLE *HandleBuffer;
103 UINTN NumberOfHandles;
104 EFI_FV_FILETYPE FileType;
105 UINT32 FvStatus;
106 EFI_FV_FILE_ATTRIBUTES Attributes;
107 UINTN Size;
108 UINTN Index;
109
110 //
111 // Locate protocol.
112 //
113 Status = gBS->LocateHandleBuffer (
114 ByProtocol,
115 Protocol,
116 NULL,
117 &NumberOfHandles,
118 &HandleBuffer
119 );
120 if (EFI_ERROR (Status)) {
121 //
122 // Defined errors at this time are not found and out of resources.
123 //
124 return Status;
125 }
126
127 //
128 // Looking for FV with ACPI storage file
129 //
130 for (Index = 0; Index < NumberOfHandles; Index++) {
131
132 //
133 // Get the protocol on this handle
134 // This should not fail because of LocateHandleBuffer
135 //
136 Status = gBS->HandleProtocol (
137 HandleBuffer[Index],
138 Protocol,
139 Instance
140 );
141 ASSERT_EFI_ERROR (Status);
142
143 if (!Type) {
144
145 //
146 // Not looking for the FV protocol, so find the first instance of the
147 // protocol. There should not be any errors because our handle buffer
148 // should always contain at least one or LocateHandleBuffer would have
149 // returned not found.
150 //
151 break;
152 }
153
154 //
155 // See if it has the ACPI storage file
156 //
157 Size = 0;
158 FvStatus = 0;
159 Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
160 *Instance,
161 gEfiAcpiMultiTableStorageGuid,
162 NULL,
163 &Size,
164 &FileType,
165 &Attributes,
166 &FvStatus
167 );
168
169 //
170 // If we found it, then we are done
171 //
172 if (Status == EFI_SUCCESS) {
173 break;
174 }
175 }
176
177 //
178 // Our exit status is determined by the success of the previous operations
179 // If the protocol was found, Instance already points to it.
180 //
181 //
182 // Free any allocated buffers
183 //
184 FreePool (HandleBuffer);
185
186 return Status;
187 }
188
189 EFI_STATUS
190 PublishAcpiTablesFromFv (
191 IN EFI_GUID *gEfiAcpiMultiTableStorageGuid
192 )
193 {
194 EFI_STATUS Status;
195 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
196 EFI_ACPI_COMMON_HEADER *CurrentTable;
197 UINT32 FvStatus;
198 UINTN Size;
199 EFI_ACPI_TABLE_VERSION Version;
200 UINTN TableHandle;
201 INTN Instance;
202 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
203
204 Instance = 0;
205 TableHandle = 0;
206 CurrentTable = NULL;
207 FwVol = NULL;
208
209 //
210 // Find the AcpiSupport protocol
211 //
212 Status = LocateSupportProtocol (
213 &gEfiAcpiTableProtocolGuid,
214 gEfiAcpiMultiTableStorageGuid,
215 (VOID **) &AcpiTable,
216 FALSE
217 );
218 ASSERT_EFI_ERROR (Status);
219
220 //
221 // Locate the firmware volume protocol
222 //
223 Status = LocateSupportProtocol (
224 &gEfiFirmwareVolume2ProtocolGuid,
225 gEfiAcpiMultiTableStorageGuid,
226 (VOID **) &FwVol,
227 TRUE
228 );
229
230 //
231 // Read tables from the storage file.
232 //
233
234 while (Status == EFI_SUCCESS) {
235 Status = FwVol->ReadSection (
236 FwVol,
237 gEfiAcpiMultiTableStorageGuid,
238 EFI_SECTION_RAW,
239 Instance,
240 (VOID **) &CurrentTable,
241 &Size,
242 &FvStatus
243 );
244
245 if (!EFI_ERROR (Status)) {
246
247 //
248 // Perform any table specific updates.
249 //
250 if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
251 UpdateDsdt (CurrentTable);
252 }
253 BoardUpdateAcpiTable (CurrentTable, &Version);
254
255 //
256 // Add the table
257 //
258 TableHandle = 0;
259
260 if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
261 Status = AcpiTable->InstallAcpiTable (
262 AcpiTable,
263 CurrentTable,
264 CurrentTable->Length,
265 &TableHandle
266 );
267 }
268
269 ASSERT_EFI_ERROR (Status);
270
271 //
272 // Increment the instance
273 //
274 Instance++;
275 CurrentTable = NULL;
276 }
277 }
278
279 //
280 // Finished
281 //
282 return EFI_SUCCESS;
283 }
284
285 /**
286 ACPI Platform driver installation function.
287
288 @param[in] ImageHandle Handle for this drivers loaded image protocol.
289 @param[in] SystemTable EFI system table.
290
291 @retval EFI_SUCCESS The driver installed without error.
292 @retval EFI_ABORTED The driver encountered an error and could not complete installation of
293 the ACPI tables.
294
295 **/
296 EFI_STATUS
297 EFIAPI
298 InstallAcpiBoard (
299 IN EFI_HANDLE ImageHandle,
300 IN EFI_SYSTEM_TABLE *SystemTable
301 )
302 {
303 EFI_STATUS Status;
304 EFI_HANDLE Handle;
305
306 AcpiGnvsInit((VOID **) &mPlatformNvsAreaProtocol.Area);
307
308 //
309 // This PCD set must be done before PublishAcpiTablesFromFv.
310 // The PCD data will be used there.
311 //
312 PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mPlatformNvsAreaProtocol.Area);
313
314 //
315 // Platform ACPI Tables
316 //
317 PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
318
319 //
320 // This protocol publish must be done after PublishAcpiTablesFromFv.
321 // The NVS data is be updated there.
322 //
323 Handle = NULL;
324 Status = gBS->InstallMultipleProtocolInterfaces (
325 &Handle,
326 &gPlatformNvsAreaProtocolGuid,
327 &mPlatformNvsAreaProtocol,
328 NULL
329 );
330 ASSERT_EFI_ERROR (Status);
331
332 return EFI_SUCCESS;
333 }
LocateSupportProtocol
EFI_STATUS LocateSupportProtocol(IN EFI_GUID *Protocol, IN EFI_GUID *gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol.
Definition: BoardAcpiDxe.c:94
AcpiGnvsInit
EFI_STATUS AcpiGnvsInit(IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize.
Definition: AcpiGnvsInit.c:56
InstallAcpiBoard
EFI_STATUS InstallAcpiBoard(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
ACPI Platform driver installation function.
Definition: BoardAcpiDxe.c:298


AlderLake Board Code: Ecdt.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Ecdt
Ecdt.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Embedded Controller Boot
3 Resources Table (ECDT). All changes to the ECDT contents should be done
4 in this file.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 2016 - 2017 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _ECDT_H_
38 #define _ECDT_H_
39
40 //
41 // Statements that include other files
42 //
43
44 #include <IndustryStandard/Acpi.h>
45
46 //
47 // ECDT Definitions
48 //
49 #define EFI_ACPI_OEM_ECDT_REVISION 0x00000001
50
51 #endif


AlderLake Board Code: Facs.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Facs
Facs.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Firmware ACPI Control
3 Structure (FACS). All changes to the FACS contents should be done
4 in this file.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 1999 - 2017 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _FACS_H_
38 #define _FACS_H_
39
40 //
41 // Statements that include other files
42 //
43
44 #include <IndustryStandard/Acpi.h>
45
46 //
47 // FACS Definitions
48 //
49
50 #define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000
51 #define EFI_ACPI_GLOBAL_LOCK 0x00000000
52
53 //
54 // Firmware Control Structure Feature Flags are defined in AcpiX.0.h
55 //
56 #define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000
57
58 #define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000
59
60 #endif


AlderLake Board Code: Fadt6.3.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Fadt
Fadt6.3.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Fixed ACPI Description Table
3 (FADT). All changes to the FADT contents should be done in this file.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2020-2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _FADT_H_
37 #define _FADT_H_
38
39 //
40 // Statements that include other files
41 //
42
43 #include <IndustryStandard/Acpi.h>
44
45 #include "Register/PmcRegs.h"
46 #include "Register/TcoRegs.h"
47
48 //
49 // FADT Definitions
50 //
51 #ifndef EFI_ACPI_OEM_FADT_REVISION
52 #define EFI_ACPI_OEM_FADT_REVISION 0x00000000
53 #endif
54
55 //
56 // For ACPI 1.0 support
57 //
58 #define EFI_ACPI_INT_MODEL 0x00
59 /*
60 1 Desktop
61 2 Mobile
62 3 Workstation
63 4 Enterprise Server
64 5 SOHO Server
65 6 Appliance PC
66 7 Performance Server
67 */
68 #define EFI_ACPI_PREFERRED_PM_PROFILE 0x01
69 #define EFI_ACPI_SCI_INT 0x0009
70 #define EFI_ACPI_SMI_CMD 0x000000B2
71 #define EFI_ACPI_S4_BIOS_REQ 0xF2
72 #define EFI_ACPI_PSTATE_CNT 0x00
73 #define EFI_ACPI_GPE1_BASE 0x10
74 #define EFI_ACPI_CST_CNT 0x0
75 #define EFI_ACPI_P_LVL2_LAT 101
76 #define EFI_ACPI_P_LVL3_LAT 1001
77 #define EFI_ACPI_FLUSH_SIZE 0x0000
78 #define EFI_ACPI_FLUSH_STRIDE 0x0000
79 #define EFI_ACPI_DUTY_OFFSET 0x01
80 #define EFI_ACPI_DUTY_WIDTH 0x03
81 #define EFI_ACPI_DAY_ALRM 0x0D
82 #define EFI_ACPI_MON_ALRM 0x00
83 #define EFI_ACPI_CENTURY 0x32
84
85 //
86 // IA-PC Boot Architecture Flags, see ACPI 6.3 table specification and Acpi61.h
87 // We should not use EFI_ACPI_6_3_8042 for legacy free platform, or XP reset fail. No impact to mobile.
88 //
89 #define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_3_LEGACY_DEVICES)
90
91 //
92 // Fixed Feature Flags, see ACPI 6.3 table specification and Acpi6_3.h
93 //
94 #define EFI_ACPI_FIXED_FEATURE_FLAGS (\
95 EFI_ACPI_6_3_USE_PLATFORM_CLOCK | \
96 EFI_ACPI_6_3_WBINVD | \
97 EFI_ACPI_6_3_DCK_CAP | \
98 EFI_ACPI_6_3_FIX_RTC | \
99 EFI_ACPI_6_3_RTC_S4 | \
100 EFI_ACPI_6_3_SLP_BUTTON | \
101 EFI_ACPI_6_3_PROC_C1 | \
102 EFI_ACPI_6_3_RESET_REG_SUP \
103 )
104
105 //
106 // PM1A Event Register Block Generic Address Information
107 //
108 #define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
109 #define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
110 #define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
111 #define EFI_ACPI_PM1A_EVT_BLK_ADDRESS FixedPcdGet16 (PcdAcpiBaseAddress)
112
113 //
114 // PM1B Event Register Block Generic Address Information
115 //
116 #define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
117 #define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
118 #define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
119 #define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x0000000000000000
120
121 //
122 // PM1A Control Register Block Generic Address Information
123 //
124 #define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
125 #define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
126 #define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
127 #define EFI_ACPI_PM1A_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
128
129 //
130 // PM1B Control Register Block Generic Address Information
131 //
132 #define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
133 #define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
134 #define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
135 #define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x0000000000000000
136
137 //
138 // PM2 Control Register Block Generic Address Information
139 //
140 #define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
141 #define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
142 #define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
143 #define EFI_ACPI_PM2_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50)
144
145 //
146 // Power Management Timer Control Register Block Generic Address
147 // Information
148 //
149 #define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
150 #define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
151 #define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
152 #define EFI_ACPI_PM_TMR_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
153
154 //
155 // General Purpose Event 0 Register Block Generic Address
156 // Information
157 //
158 #define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
159 #define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0x100
160 #define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
161 #define EFI_ACPI_GPE0_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + R_ACPI_IO_GPE0_STS_31_0)
162
163 //
164 // General Purpose Event 1 Register Block Generic Address
165 // Information
166 //
167 #define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
168 #define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x00
169 #define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x00
170 #define EFI_ACPI_GPE1_BLK_ADDRESS 0x0000000000000000
171
172 //
173 // Reset Register Generic Address Information
174 //
175 #define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
176 #define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
177 #define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
178 #define EFI_ACPI_RESET_REG_ADDRESS 0x0000000000000CF9
179 #define EFI_ACPI_RESET_VALUE 0x06
180
181 //
182 // Number of bytes decoded by PM1 event blocks (a and b)
183 //
184 #define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
185
186 //
187 // Number of bytes decoded by PM1 control blocks (a and b)
188 //
189 #define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
190
191 //
192 // Number of bytes decoded by PM2 control block
193 //
194 #define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)
195
196 //
197 // Number of bytes decoded by PM timer block
198 //
199 #define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
200
201 //
202 // Number of bytes decoded by GPE0 block
203 //
204 #define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)
205
206 //
207 // Number of bytes decoded by GPE1 block
208 //
209 #define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)
210
211 #endif


AlderLake Board Code: GenSsdtLib.c Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
GenSsdtLib.c
Go to the documentation of this file.
1 /** @file
2 ACPI SSDT table generation library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include "AcpiByteStream.h"
36 #include <Base.h>
37 #include <Uefi.h>
38 #include <Library/BaseLib.h>
39 #include <Library/HobLib.h>
40 #include <Guid/HobList.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <IndustryStandard/Acpi.h>
43 #include <Library/DebugLib.h>
44 #include <Library/BaseMemoryLib.h>
45 #include <Protocol/AcpiTable.h>
46 #include <Protocol/AcpiSystemDescriptionTable.h>
47 #include <Library/MemoryAllocationLib.h>
48
49 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtHeader [] = {
50 0x53,0x53,0x44,0x54,0x08,0x01,0x00,0x00, /* 00000000 "SSDT...." */
51 0x02,0x06,0x49,0x6E,0x74,0x65,0x6C,0x20, /* 00000008 "..Intel " */
52 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, /* 00000010 " " */
53 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
54 0x27,0x05,0x16,0x20, /* 00000020 "'.. " */
55 0xA0,0x0F,0x00 /* 00000024 "..." */
56 };
57
58 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtExternalDualName [] = {
59 0x15,0x5C,0x2E,0x5F,0x53,0x42,0x5F,0x50, /* 00000000 ".\._SB_P" */
60 0x43,0x49,0x58,0x06,0x00 /* 00000008 "CIX.." */
61 };
62
63 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtScopePkgLengthEncoding [] = {
64 0x10, 0x00, 0x00, 0x00, 0x00 /* 00000000 "....." */
65 };
66
67 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtScopeDualName [] = {
68 0x5C,0x2E,0x5F,0x53,0x42, /* 00000000 "\._SB" */
69 0x5F,0x50,0x43,0x49,0x58 /* 00000008 "_PCIX" */
70 };
71
72 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtDevicePkgLengthEncoding [] = {
73 0x5B,0x82,0x00,0x00,0x00,0x00 /* 00000000 "......" */
74 };
75
76 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtDeviceName [] = {
77 0x54,0x4D,0x50,0x31 /* 00000000 "TMP1" */
78 };
79
80 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtHardwareId [] = {
81 0x08,0x5F,0x48,0x49,0x44,0x0D,0x49,0x4E, /* 00000000 "._HID.IN" */
82 0x54,0x30,0x30,0x30,0x30,0x30,0x00 /* 00000008 "T0000." */
83 };
84
85 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCompatibleId [] = {
86 0x08,0x5F,0x43,0x49,0x44,0x0D,0x49,0x4E, /* 00000000 "._CID.IN" */
87 0x54,0x30,0x30,0x30,0x30,0x30,0x00 /* 00000008 "T0000." */
88 };
89
90 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtUniqueId [] = {
91 0x08,0x5F,0x55,0x49,0x44,0x00 /* 00000000 "._UID." */
92 };
93
94 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCurrentResourceSettings [] = {
95 0x08,0x5F,0x43,0x52,0x53, /* 00000000 "._CRS" */
96 };
97
98 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtBufferPkgLengthEncoding [] = {
99 0x11,0x00,0x00
100 };
101
102 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCrsPkgLengthEncoding [] = {
103 0x00,0x00, 0x00 /* 00000000 "....." */
104 };
105
106 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtGpioResource [] = {
107 0x8C,0x20,0x00,0x01,0x01,0x01,0x00,0x02, /* 00000000 ". ......" */
108 0x00,0x00,0x00,0x00,0x00,0x00,0x17,0x00, /* 00000008 "........" */
109 0x00,0x19,0x00,0x23,0x00,0x00,0x00,0x03, /* 00000010 "...#...." */
110 0x00,0x5C,0x5F,0x53,0x42,0x2E,0x47,0x50, /* 00000018 ".\_SB.GP" */
111 0x49,0x30,0x00, /* 00000020 "I0." */
112 };
113
114 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtI2cSerialBusResource [] = {
115 0x8E,0x1E,0x00,0x01,0x00,0x01,0x02,0x00, /* 00000000 "........" */
116 0x00,0x01,0x06,0x00,0x80,0x1A,0x06,0x00, /* 00000008 "........" */
117 0x22,0x00,0x5C,0x5F,0x53,0x42,0x2E,0x50, /* 00000010 "".\_SB.P" */
118 0x43,0x49,0x30,0x2E,0x49,0x32,0x43,0x58, /* 00000018 "CI0.I2CX" */
119 0x00 /* 00000020 "." */
120 };
121
122 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtStatusMethod [] = {
123 0x14,0x09,0x5F,0x53,0x54,0x41,0x00, /* 00000000 ".._STA." */
124 0xA4,0x0A,0x0F /* 00000008 "..." */
125 };
126
127 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtResourceTemplateEndTag [] = {
128 0x79, 0x00
129 };
130
131 EFI_STATUS
132 GetTableSize(
133 IN UINT8 *AcpiDataBase,
134 OUT UINT32 *SsdtTableSize
135 )
136 {
137 UINTN GpioResources;
138 UINTN I2cResources;
139 UINT32 ResourceBufferLength;
140 UINT32 DevicePackageLength;
141 UINT32 ScopePackageLength;
142 UINT32 ResourceSize;
143 UINTN i;
144 UINTN ResourceOffset;
145 UINT8 ResourceType;
146 UINTN NextResource;
147 EFI_ACPI_SDT_HEADER *SsdtTableInfo;
148 SSDT_DEVICE_DATA *SsdtDeviceInfo;
149 UINT32 Size;
150 UINT8 *PrintData;
151
152 //
153 // Get table info from HOB
154 //
155 SsdtTableInfo = (EFI_ACPI_SDT_HEADER *) AcpiDataBase;
156 SsdtDeviceInfo = (SSDT_DEVICE_DATA *) (AcpiDataBase + sizeof(EFI_ACPI_SDT_HEADER));
157 ResourceOffset = sizeof(EFI_ACPI_SDT_HEADER) + sizeof(SSDT_DEVICE_DATA) - sizeof(UINT8);
158 NextResource = 0;
159 GpioResources = 0;
160 I2cResources = 0;
161 ResourceSize = 0;
162
163 Size = SsdtTableInfo->Length;
164
165 DEBUG_CODE_BEGIN();
166 DEBUG((DEBUG_INFO, "GenSsdt AcpiData print:\n"));
167 for (PrintData = AcpiDataBase; PrintData<(AcpiDataBase + Size); PrintData++) {
168 DEBUG((DEBUG_INFO, "%x ", *PrintData));
169 }
170 DEBUG((DEBUG_INFO, "\n"));
171 DEBUG_CODE_END();
172
173 DEBUG((DEBUG_INFO, "NumberOfResources: %x \n", SsdtDeviceInfo->NumberOfResources));
174
175 for (i = 0; i < SsdtDeviceInfo->NumberOfResources; i++) {
176 ResourceType = *(AcpiDataBase + ResourceOffset + NextResource);
177 DEBUG((DEBUG_INFO, "ResourceType: %x ", ResourceType));
178 switch (ResourceType) {
179 case ACPI_GPIO_RESOURCE_TYPE :
180 {
181 ResourceSize = ResourceSize + sizeof(GPIO_RESOURCE_DATA);
182 NextResource = NextResource + sizeof(GPIO_RESOURCE_DATA) - sizeof(UINT8);
183 GpioResources++;
184 break;
185 }
186 case ACPI_I2C_RESOURCE_TYPE :
187 {
188 ResourceSize = ResourceSize + sizeof(I2C_RESOURCE_DATA);
189 NextResource = NextResource + sizeof(I2C_RESOURCE_DATA) - sizeof(UINT8);
190 I2cResources++;
191 break;
192 }
193 default :
194 DEBUG ((DEBUG_INFO, "Unsupported resource type.\n"));
195 break;
196 }
197 }
198 DEBUG((DEBUG_INFO, "GenSsdt GpioResources:%d I2cResources:%d\n", GpioResources, I2cResources));
199 //
200 // Calculate the size of table to be generated
201 //
202 ResourceBufferLength = (UINT32) ((GpioResources * sizeof(SsdtGpioResource)) +
203 (I2cResources * sizeof(SsdtI2cSerialBusResource)) +
204 sizeof(SsdtResourceTemplateEndTag));
205 DEBUG((DEBUG_INFO, "GenSsdt ResourceBufferLength: 0x%x\n", ResourceBufferLength));
206
207 DevicePackageLength = (UINT32) (sizeof(SsdtDeviceName) + sizeof(SsdtHardwareId) +
208 sizeof(SsdtCompatibleId) + sizeof(SsdtUniqueId) +
209 sizeof(SsdtCurrentResourceSettings) + ResourceBufferLength +
210 sizeof(SsdtStatusMethod));
211 DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLength: 0x%x\n", DevicePackageLength));
212
213 if (ResourceBufferLength < 254) {
214 SsdtCrsPkgLengthEncoding[0] = ACPI_BYTE_PREFIX_OPCODE;
215 SsdtCrsPkgLengthEncoding[1] = (UINT8) ResourceBufferLength;
216 DevicePackageLength = DevicePackageLength + 2; //Adding Package length encoding size
217 DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding1: 0x%x\n", SsdtCrsPkgLengthEncoding[1]));
218 } else if (ResourceBufferLength < 65533) {
219 SsdtCrsPkgLengthEncoding[0] = ACPI_WORD_PREFIX_OPCODE;
220 SsdtCrsPkgLengthEncoding[1] = (UINT8) (ResourceBufferLength & 0x00FF);
221 SsdtCrsPkgLengthEncoding[2] = (UINT8) ((ResourceBufferLength & 0xFF00) >> 8);
222 DevicePackageLength = DevicePackageLength + 3; //Adding Package length encoding size
223 DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding1: 0x%x\n", SsdtCrsPkgLengthEncoding[1]));
224 DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding2: 0x%x\n", SsdtCrsPkgLengthEncoding[2]));
225 }
226
227 if (ResourceBufferLength < 61) {
228 SsdtBufferPkgLengthEncoding[1] = (UINT8) ResourceBufferLength + 3; //Taking CrsPackageLength encoding into account
229 DevicePackageLength = DevicePackageLength + 2; //Adding Package length encoding size
230 DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding1: 0x%x\n", SsdtBufferPkgLengthEncoding[1]));
231 } else if (ResourceBufferLength < 4095) {
232 SsdtBufferPkgLengthEncoding[1] = 0x40 | ((UINT8)((ResourceBufferLength + 5) & 0x00F)); //Taking CrsPackageLength encoding into account
233 SsdtBufferPkgLengthEncoding[2] = (UINT8) (((ResourceBufferLength + 5) & 0xFF0) >> 4); //Taking CrsPackageLength encoding into account
234 DevicePackageLength = DevicePackageLength + 3; //Adding Package length encoding size
235 DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding1: 0x%x\n", SsdtBufferPkgLengthEncoding[1]));
236 DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding2: 0x%x\n", SsdtBufferPkgLengthEncoding[2]));
237 }
238
239 ScopePackageLength = 0;
240 if (DevicePackageLength < 63) {
241 SsdtDevicePkgLengthEncoding[2] = (UINT8) DevicePackageLength;
242 ScopePackageLength = ScopePackageLength + 3;
243 DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding2: 0x%x\n", SsdtDevicePkgLengthEncoding[2]));
244 } else if (DevicePackageLength < 4094) {
245 SsdtDevicePkgLengthEncoding[2] = 0x40 | ((UINT8)((DevicePackageLength + 2) & 0x00F));
246 SsdtDevicePkgLengthEncoding[3] = (UINT8) (((DevicePackageLength + 2) & 0xFF0) >> 4);
247 ScopePackageLength = ScopePackageLength + 4;
248 DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding2: 0x%x\n", SsdtDevicePkgLengthEncoding[2]));
249 DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding3: 0x%x\n", SsdtDevicePkgLengthEncoding[3]));
250 }
251
252 ScopePackageLength = ScopePackageLength + sizeof(SsdtScopeDualName) + DevicePackageLength;
253 if (ScopePackageLength < 63) {
254 SsdtScopePkgLengthEncoding[1] = (UINT8) ScopePackageLength;
255 DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding1: 0x%x\n", SsdtScopePkgLengthEncoding[1]));
256 } else if (ScopePackageLength < 4094) {
257 ScopePackageLength = ScopePackageLength + 2;
258 SsdtScopePkgLengthEncoding[1] = 0x40 | ((UINT8)(ScopePackageLength & 0x00F));
259 SsdtScopePkgLengthEncoding[2] = (UINT8) ((ScopePackageLength & 0xFF0) >> 4);
260 DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding1: 0x%x\n", SsdtScopePkgLengthEncoding[1]));
261 DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding2: 0x%x\n", SsdtScopePkgLengthEncoding[2]));
262 }
263
264 *SsdtTableSize = (UINT32) (sizeof(SsdtHeader) + sizeof(SsdtExternalDualName) + ScopePackageLength + 1);
265
266 return EFI_SUCCESS;
267 }
268
269 EFI_STATUS
270 CreateAcpiTableInMemory (
271 IN UINT8 *AcpiDataBase,
272 IN UINT32 *SsdtTableSize,
273 OUT UINT8 *CurrentTable
274 )
275 {
276 UINT8 *CurrentTablePointer;
277 EFI_ACPI_SDT_HEADER *AcpiTableHeader;
278 EFI_ACPI_SDT_HEADER *SsdtTableInfo;
279 SSDT_DEVICE_DATA *SsdtDeviceInfo;
280 GPIO_RESOURCE_DATA *GpioResourceInfo;
281 I2C_RESOURCE_DATA *I2cResourceInfo;
282 GPIO_RESOURCE *TempGpioResource;
283 I2C_SERIAL_BUS_RESOURCE *TempI2cResource;
284 UINTN i;
285 UINTN ResourceOffset;
286 UINT8 ResourceType;
287 UINTN NextResource;
288 UINT32 Size;
289
290 SsdtTableInfo = (EFI_ACPI_SDT_HEADER *) AcpiDataBase;
291 SsdtDeviceInfo = (SSDT_DEVICE_DATA *) (AcpiDataBase + sizeof(EFI_ACPI_SDT_HEADER));
292 ResourceOffset = sizeof(EFI_ACPI_SDT_HEADER) + sizeof(SSDT_DEVICE_DATA) - sizeof(UINT8);
293 //
294 // Copy SSDT content to allocated space
295 //
296 CurrentTablePointer = (UINT8 *) CurrentTable;
297 CopyMem(CurrentTablePointer, &SsdtHeader, sizeof(SsdtHeader));
298 AcpiTableHeader = (EFI_ACPI_SDT_HEADER *) CurrentTablePointer;
299 AcpiTableHeader->Length = *SsdtTableSize;
300 CopyMem(AcpiTableHeader->OemId, SsdtTableInfo->OemId, 6);
301 CopyMem(AcpiTableHeader->OemTableId, SsdtTableInfo->OemTableId, 8);
302
303 CurrentTablePointer = (UINT8 *) (CurrentTable + sizeof(SsdtHeader));
304 CopyMem(CurrentTablePointer, &SsdtExternalDualName, sizeof(SsdtExternalDualName));
305 *(CHAR8 *) (CurrentTablePointer + ACPI_EXTERNAL_PCI_BUS_NUMBER_OFFSET) = '0'; //PCI bus 0
306
307 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtExternalDualName));
308 Size = ((SsdtScopePkgLengthEncoding[1] & 0xC0) >> 6) + 2;
309 CopyMem(CurrentTablePointer, &SsdtScopePkgLengthEncoding, Size);
310
311 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
312 CopyMem(CurrentTablePointer, &SsdtScopeDualName, sizeof(SsdtScopeDualName));
313 *(CHAR8 *) (CurrentTablePointer + ACPI_SCOPE_PCI_BUS_NUMBER_OFFSET) = '0'; //PCI bus 0
314
315 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtScopeDualName));
316 Size = ((SsdtDevicePkgLengthEncoding[2] & 0xC0) >> 6) + 3;
317 CopyMem(CurrentTablePointer, &SsdtDevicePkgLengthEncoding, Size);
318
319 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
320 CopyMem(&SsdtDeviceName, SsdtDeviceInfo->DeviceName, 4);
321 CopyMem(CurrentTablePointer, &SsdtDeviceName, sizeof(SsdtDeviceName));
322
323 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtDeviceName));
324 CopyMem(CurrentTablePointer, &SsdtHardwareId, sizeof(SsdtHardwareId));
325 CopyMem(CurrentTablePointer + ACPI_NAME_OBJECT_STRING_OFFSET, SsdtDeviceInfo->HardwareId, 8);
326
327 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtHardwareId));
328 CopyMem(CurrentTablePointer, &SsdtCompatibleId, sizeof(SsdtCompatibleId));
329 CopyMem(CurrentTablePointer + ACPI_NAME_OBJECT_STRING_OFFSET, SsdtDeviceInfo->CompatibilityId, 8);
330
331 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtCompatibleId));
332 SsdtUniqueId[ACPI_UNIQUE_ID_NUMBER_OFFSET] = (UINT8) SsdtDeviceInfo->UniqueId;
333 CopyMem(CurrentTablePointer, &SsdtUniqueId, sizeof(SsdtUniqueId));
334
335 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtUniqueId));
336 CopyMem(CurrentTablePointer, &SsdtCurrentResourceSettings, sizeof(SsdtCurrentResourceSettings));
337
338 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtCurrentResourceSettings));
339 Size = ((SsdtBufferPkgLengthEncoding[1] & 0xC0) >> 6) + 2;
340 CopyMem(CurrentTablePointer, &SsdtBufferPkgLengthEncoding, Size);
341
342 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
343 if (SsdtCrsPkgLengthEncoding[0] == ACPI_BYTE_PREFIX_OPCODE) {
344 Size = 2;
345 } else if (SsdtCrsPkgLengthEncoding[0] == ACPI_WORD_PREFIX_OPCODE) {
346 Size = 3;
347 }
348 CopyMem(CurrentTablePointer, &SsdtCrsPkgLengthEncoding, Size);
349
350 CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
351 NextResource = 0;
352 for (i = 0; i < SsdtDeviceInfo->NumberOfResources; i++) {
353 ResourceType = *(UINT8 *)(AcpiDataBase + ResourceOffset + NextResource);
354 switch (ResourceType) {
355 case ACPI_GPIO_RESOURCE_TYPE :
356 {
357 CopyMem(CurrentTablePointer, &SsdtGpioResource, sizeof(SsdtGpioResource));
358 TempGpioResource = (GPIO_RESOURCE *) CurrentTablePointer;
359 DEBUG((DEBUG_INFO, "TempGpioConnDesc: %x\n", TempGpioResource->GpioConnectionDescriptor));
360 DEBUG((DEBUG_INFO, "TempGpioResourceNumber1 before: %x\n", TempGpioResource->PinNumber1));
361 DEBUG((DEBUG_INFO, "TempGpioResourceNumber2 before: %x\n", TempGpioResource->PinNumber2));
362 GpioResourceInfo = (GPIO_RESOURCE_DATA *) (AcpiDataBase + ResourceOffset + NextResource);
363 if (GpioResourceInfo->GpioResourceType == ACPI_GPIO_RESOURCE_TYPE_INTERRUPT) {
364 TempGpioResource->GpioConnectionType = GpioInterrupt;
365 TempGpioResource->InterruptAndIoFlags1 |= 0x10;
366 TempGpioResource->PinNumber1 = GpioResourceInfo->GpioNumber & 0x00FF;
367 TempGpioResource->PinNumber2 = (GpioResourceInfo->GpioNumber & 0xFF00) >> 8;
368 } else if (GpioResourceInfo->GpioResourceType == ACPI_GPIO_RESOURCE_TYPE_IO) {
369 TempGpioResource->GpioConnectionType = GpioIo;
370 TempGpioResource->InterruptAndIoFlags1 &= 0x0F;
371 TempGpioResource->PinNumber1 = GpioResourceInfo->GpioNumber & 0x00FF;
372 TempGpioResource->PinNumber2 = (GpioResourceInfo->GpioNumber & 0xFF00) >> 8;
373 }
374 DEBUG((DEBUG_INFO, "TempGpioResourceNumber1 after: %x\n", TempGpioResource->PinNumber1));
375 DEBUG((DEBUG_INFO, "TempGpioResourceNumber2 after: %x\n", TempGpioResource->PinNumber2));
376 NextResource = NextResource + sizeof(GPIO_RESOURCE_DATA) - sizeof(UINT8);
377 CurrentTablePointer = CurrentTablePointer + sizeof(SsdtGpioResource);
378
379 break;
380 }
381 case ACPI_I2C_RESOURCE_TYPE :
382 {
383 CopyMem(CurrentTablePointer, &SsdtI2cSerialBusResource, sizeof(SsdtI2cSerialBusResource));
384 TempI2cResource = (I2C_SERIAL_BUS_RESOURCE *) CurrentTablePointer;
385 I2cResourceInfo = (I2C_RESOURCE_DATA *) (AcpiDataBase + ResourceOffset + NextResource);
386 TempI2cResource->SlaveAddress = (UINT16) I2cResourceInfo->I2cSlaveAddress;
387 TempI2cResource->ConnectionSpeed = I2cResourceInfo->ConnectionSpeed;
388 *(CurrentTablePointer + ACPI_I2C_RESOURCE_CONTROLLER_NUMBER_OFFSET) = I2cResourceInfo->I2cSliceNumber + ASCII_0_ORDINAL;
389 NextResource = NextResource + sizeof(I2C_RESOURCE_DATA) - sizeof(UINT8);
390 CurrentTablePointer = CurrentTablePointer + sizeof(SsdtI2cSerialBusResource);
391
392 break;
393 }
394 }
395 }
396 CopyMem(CurrentTablePointer, &SsdtResourceTemplateEndTag, sizeof(SsdtResourceTemplateEndTag));
397 CurrentTablePointer = CurrentTablePointer + sizeof(SsdtResourceTemplateEndTag);
398 if (SsdtDeviceInfo->EnableStatus == TRUE) {
399 SsdtStatusMethod[ACPI_STA_RETURN_VALUE_OFFSET] = ACPI_STA_RETURN_VALUE_DEVICE_ENABLED;
400 } else {
401 SsdtStatusMethod[ACPI_STA_RETURN_VALUE_OFFSET] = ACPI_STA_RETURN_VALUE_DEVICE_DISABLED;
402 }
403 CopyMem(CurrentTablePointer, &SsdtStatusMethod, sizeof(SsdtStatusMethod));
404
405 return EFI_SUCCESS;
406 }
407
408 /**
409 Generate SSDTs from ACPI data available in BIOS board files
410 or ACPI data generated from PCT tool FVs
411 **/
412 EFI_STATUS
413 GenerateSsdtFromConfigFile (
414 VOID
415 )
416 {
417 EFI_STATUS Status = EFI_SUCCESS;
418 UINTN Pages;
419 UINT8 *CurrentTable;
420 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
421 EFI_ACPI_SDT_HEADER *AcpiTableHeader;
422 UINT32 SsdtTableSize;
423 UINT8 *PctAcpiDataBase;
424 UINTN i,j;
425 UINT8 *PrintData;
426 UINTN TableHandle;
427 PCT_ACPI_BLOCK_HDR *PctAcpiDataHeader;
428 UINT16 TableCount;
429 UINT8 *AcpiDataPointer;
430
431 DEBUG((DEBUG_INFO, "GenSsdt start\n"));
432 Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
433 ASSERT_EFI_ERROR(Status);
434
435 //
436 // Look for ACPI data HOB from PCT
437 //
438 PctAcpiDataBase = (UINT8 *) PcdGetPtr(PcdBoardAcpiData);
439 if (*PctAcpiDataBase != 0) {
440 PctAcpiDataHeader = (PCT_ACPI_BLOCK_HDR *) PctAcpiDataBase;
441 AcpiDataPointer = (UINT8 *) (PctAcpiDataBase + sizeof(PCT_ACPI_BLOCK_HDR));
442 // Get number of tables to be generated
443 TableCount = PctAcpiDataHeader->Count;
444 for (i=0; i<TableCount; i++) {
445 // Calculate table size to be created
446 Status = GetTableSize(AcpiDataPointer, &SsdtTableSize);
447 ASSERT_EFI_ERROR (Status);
448
449 // Allocate memory for SSDT
450 Pages = EFI_SIZE_TO_PAGES(SsdtTableSize);
451 Status = (gBS->AllocatePages) (
452 AllocateMaxAddress,
453 EfiACPIMemoryNVS,
454 Pages,
455 (EFI_PHYSICAL_ADDRESS *) &CurrentTable
456 );
457 ASSERT_EFI_ERROR (Status);
458 ZeroMem ((VOID *) CurrentTable, SsdtTableSize);
459
460 //Copy SSDT content to allocated space
461 Status = CreateAcpiTableInMemory(AcpiDataPointer, &SsdtTableSize, CurrentTable);
462 ASSERT_EFI_ERROR (Status);
463
464 //
465 // Dump table content from memory
466 //
467 DEBUG_CODE_BEGIN();
468 PrintData = (UINT8 *)CurrentTable;
469 DEBUG((DEBUG_INFO, "GenSsdt TableDump:\n"));
470 for (j=0; j<SsdtTableSize; j++) {
471 DEBUG((DEBUG_INFO, "%02x ", *PrintData));
472 PrintData++;
473 }
474 DEBUG((DEBUG_INFO, "\n"));
475 DEBUG_CODE_END();
476
477 TableHandle = 0;
478 AcpiTableHeader = (EFI_ACPI_SDT_HEADER *)CurrentTable;
479
480 //
481 // Install SSDT
482 //
483 Status = AcpiTable->InstallAcpiTable (
484 AcpiTable,
485 CurrentTable,
486 AcpiTableHeader->Length,
487 &TableHandle
488 );
489
490 ASSERT_EFI_ERROR(Status);
491
492 AcpiDataPointer += ((EFI_ACPI_SDT_HEADER *) AcpiDataPointer)->Length;
493 }
494 }
495 return Status;
496 }
AcpiByteStream.h
Byte stream structures for ACPI.
GenerateSsdtFromConfigFile
EFI_STATUS GenerateSsdtFromConfigFile(VOID)
Generate SSDTs from ACPI data available in BIOS board files or ACPI data generated from PCT tool FVs.
Definition: GenSsdtLib.c:413


AlderLake Board Code: GenSsdtLib.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
GenSsdtLib.h
Go to the documentation of this file.
1 /** @file
2 This is an implementation of the ACPI platform driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _GEN_SSDT_LIB_H_
36 #define _GEN_SSDT_LIB_H_
37
38 EFI_STATUS
39 GenerateSsdtFromConfigFile (
40 VOID
41 );
42
43 #endif
GenerateSsdtFromConfigFile
EFI_STATUS GenerateSsdtFromConfigFile(VOID)
Generate SSDTs from ACPI data available in BIOS board files or ACPI data generated from PCT tool FVs.
Definition: GenSsdtLib.c:413


AlderLake Board Code: Hpet.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Hpet
Hpet.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI High Precision Event Timer Description Table
3 (HPET). All changes to the HPET contents should be done in this file.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 1999 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _HPET_H_
37 #define _HPET_H_
38
39 //
40 // Statements that include other files
41 //
42
43 #include <IndustryStandard/Acpi30.h>
44 #include <IndustryStandard/HighPrecisionEventTimerTable.h>
45
46 //
47 // HPET Definitions
48 //
49
50 #define EFI_ACPI_OEM_HPET_REVISION 0x00000001
51
52 #define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201
53
54 //
55 // Event Timer Block Base Address Information
56 //
57 #define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_3_0_SYSTEM_MEMORY
58 #define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x40
59 #define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00
60 #define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00
61 #define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS 0x00000000FED00000
62
63 #define EFI_ACPI_HPET_NUMBER 0x00
64
65 #define EFI_ACPI_MIN_CLOCK_TICK 0x0080
66
67 #define EFI_ACPI_HPET_ATTRIBUTES 0x00
68
69 #endif


AlderLake Board Code: Madt.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Madt
Madt.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Multiple APIC Description
3 Table (MADT).
4 To make changes to the MADT, it is necessary to update the count for the
5 APIC structure being updated, and to modify table found in Madt.c.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 1999 - 2021 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37
38 #ifndef _MADT_H_
39 #define _MADT_H_
40
41 //
42 // Statements that include other files
43 //
44
45 #include <IndustryStandard/Acpi.h>
46
47 //
48 // MADT Definitions
49 //
50
51 #define EFI_ACPI_OEM_MADT_REVISION 0x00000001
52
53
54 //
55 // Multiple APIC Flags are defined in AcpiX.0.h
56 //
57 #define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)
58 #define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT)
59 #define EFI_ACPI_6_3_MULTIPLE_APIC_FLAGS (EFI_ACPI_6_3_PCAT_COMPAT)
60
61 //
62 // Define the number of each table type.
63 // This is where the table layout is modified.
64 //
65
66 #define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 32
67 #define EFI_ACPI_IO_APIC_COUNT 1
68 #define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2
69 #define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0
70 #define EFI_ACPI_LOCAL_APIC_NMI_COUNT 24
71 #define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0
72 #define EFI_ACPI_IO_SAPIC_COUNT 0
73 #define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0
74 #define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0
75 #define EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT 32
76 #define EFI_ACPI_LOCAL_X2APIC_NMI_COUNT 1
77
78 //
79 // MADT structure
80 //
81
82 //
83 // Ensure proper structure formats
84 //
85 #pragma pack (1)
86
87 //
88 // ACPI 1.0 Table structure
89 //
90 typedef struct {
91 EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
92
93 #if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
94 EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
95 #endif
96
97 #if EFI_ACPI_IO_APIC_COUNT > 0
98 EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
99 #endif
100
101 #if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
102 EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
103 #endif
104
105 #if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
106 EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
107 #endif
108
109 #if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
110 EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
111 #endif
112
113 #if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
114 EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
115 #endif
116
117 } EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
118
119 //
120 // ACPI 2.0 Table structure
121 //
122 typedef struct {
123 EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
124
125 #if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
126 EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
127 #endif
128
129 #if EFI_ACPI_IO_APIC_COUNT > 0
130 EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
131 #endif
132
133 #if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
134 EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
135 #endif
136
137 #if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
138 EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
139 #endif
140
141 #if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
142 EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
143 #endif
144
145 #if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
146 EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
147 #endif
148
149 #if EFI_ACPI_IO_SAPIC_COUNT > 0
150 EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
151 #endif
152
153 #if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0
154 EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
155 #endif
156
157 #if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0
158 EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
159 #endif
160
161 } EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
162
163 //
164 // ACPI 6.3 APIC Table structure
165 //
166 typedef struct {
167 EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
168
169 #if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x09
170 EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
171 #endif
172
173 #if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01
174 EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
175 #endif
176
177 #if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02
178 EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
179 #endif
180
181 #if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03
182 EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
183 #endif
184
185 #if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x0A
186 EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
187 #endif
188
189 #if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05
190 EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
191 #endif
192
193 #if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06
194 EFI_ACPI_6_3_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
195 #endif
196
197 #if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0
198 EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
199 #endif
200
201 #if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08
202 EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
203 #endif
204
205 } EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE;
206
207
208 //
209 // ACPI 6.3 X2APIC Table structure
210 //
211 typedef struct {
212 EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
213
214 #if EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT > 0 // Type 0x09
215 EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE LocalX2Apic[EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT];
216 #endif
217
218 #if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01
219 EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
220 #endif
221
222 #if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02
223 EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
224 #endif
225
226 #if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03
227 EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
228 #endif
229
230 #if EFI_ACPI_LOCAL_X2APIC_NMI_COUNT > 0 // Type 0x0A
231 EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE X2ApicNmi[EFI_ACPI_LOCAL_X2APIC_NMI_COUNT];
232 #endif
233
234 #if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05
235 EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
236 #endif
237
238 #if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06
239 EFI_ACPI_6_3_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
240 #endif
241
242 #if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0
243 EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
244 #endif
245
246 #if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08
247 EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
248 #endif
249
250 } EFI_ACPI_6_3_MULTIPLE_X2APIC_DESCRIPTION_TABLE;
251
252 #pragma pack ()
253
254 #endif


AlderLake Board Code: Mcfg.h Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Mcfg
Mcfg.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Memory Mapped Configuration
3 Space Access Table (MCFG).
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2004 - 2017 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _MCFG_H_
37 #define _MCFG_H_
38
39 //
40 // Statements that include other files
41 //
42
43 #include <IndustryStandard/Acpi30.h>
44 #include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
45
46 //
47 // MCFG Definitions
48 //
49
50 #define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
51
52 //
53 // Define the number of allocation structures so that we can build the table structure.
54 //
55 #define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 2
56
57 //
58 // MCFG structure
59 //
60
61 //
62 // Ensure proper structure formats
63 //
64 #pragma pack (1)
65
66 //
67 // MCFG Table structure
68 //
69 typedef struct {
70 EFI_ACPI_DESCRIPTION_HEADER Header;
71 UINT64 Reserved;
72 #if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0
73 EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT];
74 #endif
75 } EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
76
77 #pragma pack ()
78
79 #endif


AlderLake Board Code: UpdateDsdt.c Source File

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • BoardAcpiDxe
UpdateDsdt.c
Go to the documentation of this file.
1 /** @file
2 ACPI Update DSDT Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Uefi.h>
36 #include <Library/IoLib.h>
37 #include <Library/PciLib.h>
38 #include <Library/DebugLib.h>
39 #include <Library/BaseMemoryLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41
42 #include <Protocol/PlatformNvsArea.h>
43 extern GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL mPlatformNvsAreaProtocol;
44
45 VOID
46 UpdateDsdt (
47 IN VOID *Table
48 )
49 {
50 UINT8 *CurrPtr;
51 UINT8 *TmpDsdtPointer;
52 UINT8 *DsdtPointer;
53 UINT32 *Signature;
54 UINT8 *Operation;
55 UINT32 *Address;
56 UINT8 *Value;
57 UINT16 *Size;
58 BOOLEAN EnterDock = FALSE;
59
60 UINT8 MaximumDsdtPointLength;
61
62 MaximumDsdtPointLength = 20;
63
64 //
65 // Fix up the AML code in the DSDT affected by end user options.
66 // Fix up the following ASL Code:
67 // (1) ACPI Global NVS Memory Base and Size.
68 // (2) ACPI Graphics NVS Memory Base and Size.
69 // (3) SMBus I/O Base.
70 // (4) Thermal Management Methods.
71 //
72 //
73 // Loop through the ASL looking for values that we must fix up.
74 //
75 CurrPtr = (UINT8 *) Table;
76 for (DsdtPointer = CurrPtr;
77 DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
78 DsdtPointer++
79 ) {
80 Signature = (UINT32 *) DsdtPointer;
81 switch (*Signature) {
82 //
83 // GNVS operation region
84 //
85 case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
86 //
87 // Conditional match. For Region Objects, the Operator will always be the
88 // byte immediately before the specific name. Therefore, subtract 1 to check
89 // the Operator.
90 //
91 Operation = DsdtPointer - 1;
92 if (*Operation == AML_EXT_REGION_OP) {
93 Address = (UINT32 *) (DsdtPointer + 6);
94 *Address = (UINT32) (UINTN) mPlatformNvsAreaProtocol.Area;
95 Size = (UINT16 *) (DsdtPointer + 11);
96 *Size = sizeof (PLATFORM_NVS_AREA);
97 }
98 break;
99
100 //
101 // _AC0 method
102 //
103 case (SIGNATURE_32 ('_', 'A', 'C', '0')):
104 //
105 // Conditional match. _AC0 is >63 and <4095 bytes, so the package length is 2 bytes.
106 // Therefore, subtract 3 to check the Operator.
107 //
108 Operation = DsdtPointer - 3;
109 if (*Operation == AML_METHOD_OP) {
110 //
111 // Check if we want _AC0 enabled
112 //
113 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
114 Signature = (UINT32 *) DsdtPointer;
115 *Signature = SIGNATURE_32 ('X', 'A', 'C', '0');
116 }
117 }
118 break;
119
120 //
121 // _AL0 method
122 //
123 case (SIGNATURE_32 ('_', 'A', 'L', '0')):
124 //
125 // Conditional match. For Name Objects, the Operator will always be the byte
126 // immediately before the specific name. Therefore, subtract 1 to check the
127 // Operator.
128 //
129 Operation = DsdtPointer - 1;
130 if (*Operation == AML_NAME_OP) {
131
132 //
133 // Check if we want _AL0 enabled
134 //
135 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
136 Signature = (UINT32 *) DsdtPointer;
137 *Signature = SIGNATURE_32 ('X', 'A', 'L', '0');
138 }
139 }
140 break;
141
142 //
143 // _AC1 method
144 //
145 case (SIGNATURE_32 ('_', 'A', 'C', '1')):
146 //
147 // Conditional match. _AC1 is < 63 bytes, so the package length is 1 byte.
148 // Therefore, subtract 2 to check the Operator.
149 //
150 Operation = DsdtPointer - 2;
151 if (*Operation == AML_METHOD_OP) {
152
153 //
154 // Check if we want _AC1 enabled
155 //
156 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
157 Signature = (UINT32 *) DsdtPointer;
158 *Signature = SIGNATURE_32 ('X', 'A', 'C', '1');
159 }
160 }
161 break;
162
163 //
164 // _AL1 method
165 //
166 case (SIGNATURE_32 ('_', 'A', 'L', '1')):
167 //
168 // Conditional match. For Name Objects, the Operator will always be the byte
169 // immediately before the specific name. Therefore, subtract 1 to check the
170 // Operator.
171 //
172 Operation = DsdtPointer - 1;
173 if (*Operation == AML_NAME_OP) {
174
175 //
176 // Check if we want _AL1 enabled
177 //
178 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
179 Signature = (UINT32 *) DsdtPointer;
180 *Signature = SIGNATURE_32 ('X', 'A', 'L', '1');
181 }
182 }
183 break;
184
185 //
186 // _AC2 method
187 //
188 case (SIGNATURE_32 ('_', 'A', 'C', '2')):
189 //
190 // Conditional match. _AC2 is < 63 bytes, so the package length is 1 byte.
191 // Therefore, subtract 2 to check the Operator.
192 //
193 Operation = DsdtPointer - 2;
194 if (*Operation == AML_METHOD_OP) {
195
196 //
197 // Check if we want _AC2 enabled
198 //
199 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
200 Signature = (UINT32 *) DsdtPointer;
201 *Signature = SIGNATURE_32 ('X', 'A', 'C', '2');
202 }
203 }
204 break;
205
206 //
207 // _AL2 method
208 //
209 case (SIGNATURE_32 ('_', 'A', 'L', '2')):
210 //
211 // Conditional match. For Name Objects, the Operator will always be the byte
212 // immediately before the specific name. Therefore, subtract 1 to check the
213 // Operator.
214 //
215 Operation = DsdtPointer - 1;
216 if (*Operation == AML_NAME_OP) {
217
218 //
219 // Check if we want _AL2 enabled
220 //
221 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
222 Signature = (UINT32 *) DsdtPointer;
223 *Signature = SIGNATURE_32 ('X', 'A', 'L', '2');
224 }
225 }
226 break;
227
228 //
229 // _AC3 method
230 //
231 case (SIGNATURE_32 ('_', 'A', 'C', '3')):
232 //
233 // Conditional match. _AC3 is < 63 bytes, so the package length is 1 byte.
234 // Therefore, subtract 2 to check the Operator.
235 //
236 Operation = DsdtPointer - 2;
237 if (*Operation == AML_METHOD_OP) {
238
239 //
240 // Check if we want _AC3 enabled
241 //
242 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
243 Signature = (UINT32 *) DsdtPointer;
244 *Signature = SIGNATURE_32 ('X', 'A', 'C', '3');
245 }
246 }
247 break;
248
249 //
250 // _AL3 method
251 //
252 case (SIGNATURE_32 ('_', 'A', 'L', '3')):
253 //
254 // Conditional match. For Name Objects, the Operator will always be the byte
255 // immediately before the specific name. Therefore, subtract 1 to check the
256 // Operator.
257 //
258 Operation = DsdtPointer - 1;
259 if (*Operation == AML_NAME_OP) {
260
261 //
262 // Check if we want _AL3 enabled
263 //
264 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
265 Signature = (UINT32 *) DsdtPointer;
266 *Signature = SIGNATURE_32 ('X', 'A', 'L', '3');
267 }
268 }
269 break;
270
271 //
272 // _AC4 method
273 //
274 case (SIGNATURE_32 ('_', 'A', 'C', '4')):
275 //
276 // Conditional match. _AC4 is < 63 bytes, so the package length is 1 byte.
277 // Therefore, subtract 2 to check the Operator.
278 //
279 Operation = DsdtPointer - 2;
280 if (*Operation == AML_METHOD_OP) {
281
282 //
283 // Check if we want _AC4 enabled
284 //
285 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
286 Signature = (UINT32 *) DsdtPointer;
287 *Signature = SIGNATURE_32 ('X', 'A', 'C', '4');
288 }
289 }
290 break;
291
292 //
293 // _AL4 method
294 //
295 case (SIGNATURE_32 ('_', 'A', 'L', '4')):
296 //
297 // Conditional match. For Name Objects, the Operator will always be the byte
298 // immediately before the specific name. Therefore, subtract 1 to check the
299 // Operator.
300 //
301 Operation = DsdtPointer - 1;
302 if (*Operation == AML_NAME_OP) {
303
304 //
305 // Check if we want _AL4 enabled
306 //
307 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
308 Signature = (UINT32 *) DsdtPointer;
309 *Signature = SIGNATURE_32 ('X', 'A', 'L', '4');
310 }
311 }
312 break;
313
314 //
315 // _AC5 method
316 //
317 case (SIGNATURE_32 ('_', 'A', 'C', '5')):
318 //
319 // Conditional match. _AC5 is < 63 bytes, so the package length is 1 byte.
320 // Therefore, subtract 2 to check the Operator.
321 //
322 Operation = DsdtPointer - 2;
323 if (*Operation == AML_METHOD_OP) {
324
325 //
326 // Check if we want _AC5 enabled
327 //
328 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
329 Signature = (UINT32 *) DsdtPointer;
330 *Signature = SIGNATURE_32 ('X', 'A', 'C', '5');
331 }
332 }
333 break;
334
335 //
336 // _AL5 method
337 //
338 case (SIGNATURE_32 ('_', 'A', 'L', '5')):
339 //
340 // Conditional match. For Name Objects, the Operator will always be the byte
341 // immediately before the specific name. Therefore, subtract 1 to check the
342 // Operator.
343 //
344 Operation = DsdtPointer - 1;
345 if (*Operation == AML_NAME_OP) {
346
347 //
348 // Check if we want _AL5 enabled
349 //
350 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
351 Signature = (UINT32 *) DsdtPointer;
352 *Signature = SIGNATURE_32 ('X', 'A', 'L', '5');
353 }
354 }
355 break;
356
357 //
358 // _AC6 method
359 //
360 case (SIGNATURE_32 ('_', 'A', 'C', '6')):
361 //
362 // Conditional match. _AC6 is < 63 bytes, so the package length is 1 byte.
363 // Therefore, subtract 2 to check the Operator.
364 //
365 Operation = DsdtPointer - 2;
366 if (*Operation == AML_METHOD_OP) {
367
368 //
369 // Check if we want _AC6 enabled
370 //
371 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
372 Signature = (UINT32 *) DsdtPointer;
373 *Signature = SIGNATURE_32 ('X', 'A', 'C', '6');
374 }
375 }
376 break;
377
378 //
379 // _AL6 method
380 //
381 case (SIGNATURE_32 ('_', 'A', 'L', '6')):
382 //
383 // Conditional match. For Name Objects, the Operator will always be the byte
384 // immediately before the specific name. Therefore, subtract 1 to check the
385 // Operator.
386 //
387 Operation = DsdtPointer - 1;
388 if (*Operation == AML_NAME_OP) {
389
390 //
391 // Check if we want _AL6 enabled
392 //
393 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
394 Signature = (UINT32 *) DsdtPointer;
395 *Signature = SIGNATURE_32 ('X', 'A', 'L', '6');
396 }
397 }
398 break;
399
400 //
401 // _AC7 method
402 //
403 case (SIGNATURE_32 ('_', 'A', 'C', '7')):
404 //
405 // Conditional match. _AC7 is < 63 bytes, so the package length is 1 byte.
406 // Therefore, subtract 2 to check the Operator.
407 //
408 Operation = DsdtPointer - 2;
409 if (*Operation == AML_METHOD_OP) {
410
411 //
412 // Check if we want _AC7 enabled
413 //
414 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
415 Signature = (UINT32 *) DsdtPointer;
416 *Signature = SIGNATURE_32 ('X', 'A', 'C', '7');
417 }
418 }
419 break;
420
421 //
422 // _AL7 method
423 //
424 case (SIGNATURE_32 ('_', 'A', 'L', '7')):
425 //
426 // Conditional match. For Name Objects, the Operator will always be the byte
427 // immediately before the specific name. Therefore, subtract 1 to check the
428 // Operator.
429 //
430 Operation = DsdtPointer - 1;
431 if (*Operation == AML_NAME_OP) {
432
433 //
434 // Check if we want _AL7 enabled
435 //
436 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
437 Signature = (UINT32 *) DsdtPointer;
438 *Signature = SIGNATURE_32 ('X', 'A', 'L', '7');
439 }
440 }
441 break;
442
443 //
444 // _AC8 method
445 //
446 case (SIGNATURE_32 ('_', 'A', 'C', '8')):
447 //
448 // Conditional match. _AC8 is < 63 bytes, so the package length is 1 byte.
449 // Therefore, subtract 2 to check the Operator.
450 //
451 Operation = DsdtPointer - 2;
452 if (*Operation == AML_METHOD_OP) {
453
454 //
455 // Check if we want _AC8 enabled
456 //
457 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
458 Signature = (UINT32 *) DsdtPointer;
459 *Signature = SIGNATURE_32 ('X', 'A', 'C', '8');
460 }
461 }
462 break;
463
464 //
465 // _AL8 method
466 //
467 case (SIGNATURE_32 ('_', 'A', 'L', '8')):
468 //
469 // Conditional match. For Name Objects, the Operator will always be the byte
470 // immediately before the specific name. Therefore, subtract 1 to check the
471 // Operator.
472 //
473 Operation = DsdtPointer - 1;
474 if (*Operation == AML_NAME_OP) {
475
476 //
477 // Check if we want _AL8 enabled
478 //
479 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
480 Signature = (UINT32 *) DsdtPointer;
481 *Signature = SIGNATURE_32 ('X', 'A', 'L', '8');
482 }
483 }
484 break;
485
486 //
487 // _AC9 method
488 //
489 case (SIGNATURE_32 ('_', 'A', 'C', '9')):
490 //
491 // Conditional match. _AC9 is < 63 bytes, so the package length is 1 byte.
492 // Therefore, subtract 2 to check the Operator.
493 //
494 Operation = DsdtPointer - 2;
495 if (*Operation == AML_METHOD_OP) {
496
497 //
498 // Check if we want _AC9 enabled
499 //
500 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
501 Signature = (UINT32 *) DsdtPointer;
502 *Signature = SIGNATURE_32 ('X', 'A', 'C', '9');
503 }
504 }
505 break;
506
507 //
508 // _AL9 method
509 //
510 case (SIGNATURE_32 ('_', 'A', 'L', '9')):
511 //
512 // Conditional match. For Name Objects, the Operator will always be the byte
513 // immediately before the specific name. Therefore, subtract 1 to check the
514 // Operator.
515 //
516 Operation = DsdtPointer - 1;
517 if (*Operation == AML_NAME_OP) {
518
519 //
520 // Check if we want _AL9 enabled
521 //
522 if (PcdGet8 (PcdDisableActiveTripPoints) == 0) {
523 Signature = (UINT32 *) DsdtPointer;
524 *Signature = SIGNATURE_32 ('X', 'A', 'L', '9');
525 }
526 }
527 break;
528
529 //
530 // _PSL method
531 //
532 case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
533 //
534 // Conditional match. _PSL is < 256 bytes, so the package length is 1 byte.
535 // Therefore, subtract 2 to check the Operator.
536 //
537 Operation = DsdtPointer - 3;
538 if (*Operation == AML_METHOD_OP) {
539
540 //
541 // Check if we want _PSL enabled
542 //
543 if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
544 Signature = (UINT32 *) DsdtPointer;
545 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'L');
546 }
547 }
548 break;
549
550 //
551 // _PSV method
552 //
553 case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
554 //
555 // Conditional match. _PSV is < 256 bytes, so the package length is 1 byte.
556 // Therefore, subtract 2 to check the Operator.
557 //
558 Operation = DsdtPointer - 3;
559 if (*Operation == AML_METHOD_OP) {
560
561 //
562 // Check if we want _PSV enabled
563 //
564 if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
565 Signature = (UINT32 *) DsdtPointer;
566 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'V');
567 }
568 }
569 break;
570
571 //
572 // _CRT method
573 //
574 case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
575 //
576 // Conditional match. _CRT is < 256 bytes, so the package length is 1 byte.
577 // Subtract 3 to check the Operator for CRB, subract 2 for Harris Beach.
578 //
579 Operation = DsdtPointer - 3;
580 if (*Operation == AML_METHOD_OP) {
581
582 //
583 // Check if we want _CRT enabled
584 //
585 if (PcdGet8 (PcdDisableCriticalTripPoints) == 0) {
586 Signature = (UINT32 *) DsdtPointer;
587 *Signature = SIGNATURE_32 ('X', 'C', 'R', 'T');
588 }
589 }
590 break;
591
592 //
593 // _TC1 method
594 //
595 case (SIGNATURE_32 ('_', 'T', 'C', '1')):
596 //
597 // Conditional match. _TC1 is < 256 bytes, so the package length is 1 byte.
598 // Therefore, subtract 2 to check the Operator.
599 //
600 Operation = DsdtPointer - 2;
601 if (*Operation == AML_METHOD_OP) {
602
603 //
604 // Check if we want _TC1 enabled
605 //
606 if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
607 Signature = (UINT32 *) DsdtPointer;
608 *Signature = SIGNATURE_32 ('X', 'T', 'C', '1');
609 }
610 }
611 break;
612
613 //
614 // _TC2 method
615 //
616 case (SIGNATURE_32 ('_', 'T', 'C', '2')):
617 //
618 // Conditional match. _TC2 is < 256 bytes, so the package length is 1 byte.
619 // Therefore, subtract 2 to check the Operator.
620 //
621 Operation = DsdtPointer - 2;
622 if (*Operation == AML_METHOD_OP) {
623
624 //
625 // Check if we want _TC2 enabled
626 //
627 if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
628 Signature = (UINT32 *) DsdtPointer;
629 *Signature = SIGNATURE_32 ('X', 'T', 'C', '2');
630 }
631 }
632 break;
633
634 //
635 // _TSP method
636 //
637 case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
638 //
639 // Conditional match. _TSP is < 256 bytes, so the package length is 1 byte.
640 // Therefore, subtract 2 to check the Operator.
641 //
642 Operation = DsdtPointer - 2;
643 if (*Operation == AML_METHOD_OP) {
644
645 //
646 // Check if we want _TSP enabled
647 //
648 if (PcdGet8 (PcdDisablePassiveTripPoints) == 0) {
649 Signature = (UINT32 *) DsdtPointer;
650 *Signature = SIGNATURE_32 ('X', 'T', 'S', 'P');
651 }
652 }
653 break;
654
655 //
656 // Update SS3 Name with Setup value
657 //
658 case (SIGNATURE_32 ('S', 'S', '3', '_')):
659 Operation = DsdtPointer - 1;
660 if (*Operation == AML_NAME_OP) {
661 Value = (UINT8 *) DsdtPointer + 4;
662 *Value = PcdGet8 (PcdAcpiSleepState);
663 }
664 break;
665 //
666 // Update SS4 Name with Setup value
667 //
668 case (SIGNATURE_32 ('S', 'S', '4', '_')):
669 Operation = DsdtPointer - 1;
670 if (*Operation == AML_NAME_OP) {
671 Value = (UINT8 *) DsdtPointer + 4;
672 *Value = PcdGet8 (PcdAcpiHibernate);
673 }
674 break;
675 //
676 // _EJ0 method
677 //
678 case (SIGNATURE_32 ('_', 'E', 'J', '0')):
679 if (PcdGet8 (PcdLowPowerS0Idle)) {
680 //
681 // Remove _EJ0 for SOC
682 //
683 if (*(DsdtPointer-3) == AML_METHOD_OP) {
684 Signature = (UINT32 *) DsdtPointer;
685 *Signature = SIGNATURE_32 ('X', 'E', 'J', '0');
686 EnterDock = TRUE;
687 }
688 }
689 break;
690 //
691 // _STA method for Device (\_SB.PCI0.DOCK)
692 //
693 case (SIGNATURE_32 ('_', 'S', 'T', 'A')):
694 if (PcdGet8 (PcdLowPowerS0Idle)) {
695 //
696 // Remove _STA in (\_SB.PCI0.DOCK) for SOC
697 //
698 if ((*(DsdtPointer-3) == AML_METHOD_OP) && (EnterDock)) {
699 Signature = (UINT32 *) DsdtPointer;
700 *Signature = SIGNATURE_32 ('X', 'S', 'T', 'A');
701 EnterDock = FALSE;
702 }
703 }
704 break;
705 //
706 // _UPC method for Device (\_SB.PCI0.XHC.RHUB)
707 //
708 case (SIGNATURE_32('H', 'S', '1', '3')):
709 for (TmpDsdtPointer = DsdtPointer;
710 TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength;
711 TmpDsdtPointer++){
712 Signature = (UINT32 *) TmpDsdtPointer;
713 switch (*Signature) {
714 case(SIGNATURE_32('U', 'P', 'C', 'P')):
715 Value = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
716 break;
717 default:
718 //
719 // Do nothing.
720 //
721 break;
722 }
723 }
724 break;
725
726
727 //
728 // _DCK method
729 //
730 case (SIGNATURE_32 ('_', 'D', 'C', 'K')):
731 if (PcdGet8 (PcdLowPowerS0Idle)) {
732 //
733 // Remove _DCK for SOC
734 //
735 if (*(DsdtPointer-3) == AML_METHOD_OP) {
736 Signature = (UINT32 *) DsdtPointer;
737 *Signature = SIGNATURE_32 ('X', 'D', 'C', 'K');
738 }
739 }
740 break;
741
742 //
743 // mask _DEP from CPU's scope if CS disabled.
744 //
745 case (SIGNATURE_32 ('P', 'R', '0', '0')):
746 case (SIGNATURE_32 ('P', 'R', '0', '1')):
747 case (SIGNATURE_32 ('P', 'R', '0', '2')):
748 case (SIGNATURE_32 ('P', 'R', '0', '3')):
749 case (SIGNATURE_32 ('P', 'R', '0', '4')):
750 case (SIGNATURE_32 ('P', 'R', '0', '5')):
751 case (SIGNATURE_32 ('P', 'R', '0', '6')):
752 case (SIGNATURE_32 ('P', 'R', '0', '7')):
753 case (SIGNATURE_32 ('P', 'R', '0', '8')):
754 case (SIGNATURE_32 ('P', 'R', '0', '9')):
755 case (SIGNATURE_32 ('P', 'R', '1', '0')):
756 case (SIGNATURE_32 ('P', 'R', '1', '1')):
757 case (SIGNATURE_32 ('P', 'R', '1', '2')):
758 case (SIGNATURE_32 ('P', 'R', '1', '3')):
759 case (SIGNATURE_32 ('P', 'R', '1', '4')):
760 case (SIGNATURE_32 ('P', 'R', '1', '5')):
761
762 if (PcdGet8 (PcdLowPowerS0Idle) == 0) {
763 for (TmpDsdtPointer = DsdtPointer; TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength; TmpDsdtPointer++){
764 Signature = (UINT32 *) TmpDsdtPointer;
765 switch (*Signature) {
766 case(SIGNATURE_32('_', 'D', 'E', 'P')):
767 *(UINT8 *) TmpDsdtPointer = 'X';
768 break;
769 default:
770 //
771 // Do nothing.
772 //
773 break;
774 }
775 }
776 }
777 break;
778
779 //
780 // _EDL name
781 //
782 case (SIGNATURE_32 ('_', 'E', 'D', 'L')):
783 if (PcdGet8 (PcdLowPowerS0Idle)) {
784 //
785 // Remove _EDL for SOC
786 //
787 if (*(DsdtPointer-1) == AML_NAME_OP) {
788 Signature = (UINT32 *) DsdtPointer;
789 *Signature = SIGNATURE_32 ('X', 'E', 'D', 'L');
790 }
791 }
792 break;
793
794 default:
795 //
796 // Do nothing.
797 //
798 break;
799 }
800 }
801 }
802


AlderLake Board Code: Mcfg Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Mcfg
Mcfg Directory Reference

Files

file Mcfg.h [code]
This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG).


AlderLake Board Code: AdvancedAcpiDxe -> AcpiTables Relation

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe

AdvancedAcpiDxe → AcpiTables Relation

File in Intel/AlderLakeBoardPkg/Acpi/AdvancedAcpiDxe | Includes file in Intel/AlderLakeBoardPkg/Acpi/AcpiTables
AcpiPlatform.c | Mcfg / Mcfg.h
AcpiPlatform.h | Fadt / Fadt6.3.h


AlderLake Board Code: Fadt Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Fadt
Fadt Directory Reference

Files

file Fadt6.3.h [code]
This file describes the contents of the ACPI Fixed ACPI Description Table (FADT).


AlderLake Board Code: Dsdt Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Dsdt
Dsdt Directory Reference


AlderLake Board Code: BoardAcpiDxe Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • BoardAcpiDxe
BoardAcpiDxe Directory Reference

Files

file | AcpiGnvsInit.c [code]
Acpi Gnvs Init Library.
file | BoardAcpiDxe.c [code]
Board ACPI Driver.
file | UpdateDsdt.c [code]
ACPI Update DSDT Library.


AlderLake Board Code: Intel Directory Reference

  • Intel
Intel Directory Reference
Directory dependency graph for Intel:


AlderLake Board Code: Facs Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Facs
Facs Directory Reference

Files

file Facs.h [code]
This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS).


AlderLake Board Code: Include Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Include
Include Directory Reference

Files

file AcpiCommon.h [code]
Header file for ACPI common Initialization Driver.


AlderLake Board Code: DoxygenInternalOnly Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • DoxygenInternalOnly
DoxygenInternalOnly Directory Reference


AlderLake Board Code: Madt Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Madt
Madt Directory Reference

Files

file Madt.h [code]
This file describes the contents of the ACPI Multiple APIC Description Table (MADT).


AlderLake Board Code: AdvancedAcpiDxe Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AdvancedAcpiDxe
AdvancedAcpiDxe Directory Reference
Directory dependency graph for AdvancedAcpiDxe:

Files

file | AcpiByteStream.h [code]
Byte stream structures for ACPI.
file | AcpiPlatform.c [code]
Advanced ACPI Driver.
file | AcpiPlatform.h [code]
This is an implementation of the Advanced ACPI driver.
file | AdvancedPmaxDxe.c [code]
Advanced PMAX table install and update driver.
file | GenSsdtLib.c [code]
ACPI SSDT table generation library.
file | GenSsdtLib.h [code]
This is an implementation of the ACPI platform driver.


AlderLake Board Code: AcpiTables Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
AcpiTables Directory Reference

Directories

Generated on Wed Jan 5 2022 01:27:52 for AlderLake Board Code by doxygen 1.8.20


AlderLake Board Code: Ecdt Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Ecdt
Ecdt Directory Reference

Files

file Ecdt.h [code]
This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT).


AlderLake Board Code: Hpet Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
  • AcpiTables
  • Hpet
Hpet Directory Reference

Files

file Hpet.h [code]
This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET).


AlderLake Board Code: AlderLakeBoardPkg Directory Reference

  • Intel
  • AlderLakeBoardPkg
AlderLakeBoardPkg Directory Reference
Directory dependency graph for AlderLakeBoardPkg:


AlderLake Board Code: Acpi Directory Reference

  • Intel
  • AlderLakeBoardPkg
  • Acpi
Acpi Directory Reference
Directory dependency graph for Acpi:

Directories

directory AcpiTables


AlderLake Board Code: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };
/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };
/* Class not documented with doxygen comments */
class Undocumented { };
/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };
/*! A template class */
template<class T> class Templ { };
/*! Class that is inherited using protected inheritance */
class ProtectedBase { };
/*! Class that is inherited using private inheritance */
class PrivateBase { };
/*! Class that is used by the Inherited class */
class Used { };
/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ<int>
{
private:
Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

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AlderLake Board Code: Related Pages

Related Pages
Here is a list of all related documentation pages: