AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 1 Introduction

AlderLake Intel® Firmware Support Package (FSP) Integration Guide
1 Introduction

1.1 Purpose

The purpose of this document is to describe the steps required to integrate the Intel® Firmware Support Package (FSP) into a boot loader solution. It supports AlderLake platforms with AlderLake processor and AlderLake Platform Controller Hub (PCH).

1.2 Intended Audience

This document is targeted at all platform and system developers who need to consume FSP binaries in their boot loader solutions. This includes, but is not limited to: system BIOS developers, boot loader developers, system integrators, as well as end users.

1.3 Related Documents

  • Platform Initialization (PI) Specification v1.7 located at http://www.uefi.org/specifications
  • Intel® Firmware Support Package: External Architecture Specification (EAS) v2.1 located at https://cdrdv2.intel.com/v1/dl/getContent/611786
  • Boot Setting File Specification (BSF) v1.0 https://firmware.intel.com/sites/default/files/BSF_1_0.pdf
  • Binary Configuration Tool for Intel® Firmware Support Package available at http://www.intel.com/fsp

1.4 Acronyms and Terminology

Acronym | Definition
BCT | Binary Configuration Tool
BDSM | Base Data Of Stolen Memory
BSF | Boot Setting File
BSP | Boot Strap Processor
BWG | BIOS Writer's Guide
CAR | Cache As Ram
CRB | Customer Reference Board
DPR | DMA Protected Range
FIT | Firmware Interface Table
FSP | Firmware Support Package
FSP API | Firmware Support Package Interface
FW | Firmware
GTT | Graphics Translation Table
IED | Intel Enhanced Debug
IFWI | Integrated Firmware Image
IOT | Internal Observation Trace
MRC | Memory Reference Code (Memory Init code encapsulated by FSP-M)
MOT | Memory Observation Trace
PCH | Platform Controller Hub
PMC | Power Management Controller
PMRR | Protected Memory Range Reporting
REMAP | Remapped Memory Area
RVP | Reference and Validation Platform
SBSP | System BSP
SMI | System Management Interrupt
SMM | System Management Mode
SMRAM | System Management Mode RAM
SPI | Serial Peripheral Interface
TOLUD | Top of Low Usable Memory
TOUUD | Top of Upper Usable Memory
TSEG | Memory Reserved at the Top of Memory to be used as SMRAM
UPD | Updatable Product Data
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 2 Overview

2 Overview

2.1 Technical Overview

The Intel® Firmware Support Package (FSP) provides chipset and processor initialization in a format that can easily be incorporated into many existing boot loaders.

The FSP will perform the necessary initialization steps as documented in the BWG including initialization of the CPU, memory controller, chipset and certain bus interfaces, if necessary.

FSP is not a stand-alone boot loader; therefore it needs to be integrated into a host boot loader to carry out other boot loader functions, such as: initializing non-Intel components, conducting bus enumeration, and discovering devices in the system and all industry standard initialization.

The FSP binary can be integrated easily into many different boot loaders, such as Coreboot, EDKII MinPlatform, Intel® Slim Bootloader, etc. and also into the embedded OS directly.

Below are some required steps for the integration:

  • Customizing The static FSP configuration parameters are part of the FSP binary and can be customized by tools provided by Intel. This step is optional as configuration data may also be provided at runtime.
  • Rebasing The FSP is not Position Independent Code (PIC) and the whole FSP has to be rebased if it is placed at a location which is different from the preferred address during build process.
  • Placing Once the FSP binary is ready for integration, the boot loader build process needs to be modified to place this FSP binary at the specific rebasing location identified above.
  • Interfacing The boot loader needs to add code to setup the operating environment for the FSP, call the FSP with correct parameters and parse the FSP output to retrieve the necessary information returned by the FSP.

2.2 FSP Distribution Package

  • The FSP distribution package contains the following:
    • FSP Binary
    • FSP Integration Guide
    • BSF Configuration File
    • Data Structure Header Files
  • The FSP configuration utility called BCT is available as a separate package. It can be downloaded from link mentioned in Section 1.3.

2.2.1 Package Layout

  • Docs (Auto generated)
    • FSP_Integration_Guide.pdf
    • FSP_Integration_Guide.chm
  • Include
    • FsptUpd.h, FspmUpd.h and FspsUpd.h (FSP UPD structure and related definitions)
    • GpioSampleDef.h (Sample enum definitions for GPIO table)
  • FspBinPkg.dec (EDKII declaration file for package)
  • Fsp.bsf (BSF file for configuring the data using BCT tool)
  • Fsp.fd (FSP Binary)
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 3 FSP Integration

3 FSP Integration

3.1 Assumptions Used in this Document

The FSP for this platform is built with a preferred base address given by PcdFspAreaBaseAddress and so the reference code provided in the document assumes that the FSP is placed at this base address during the final boot loader build. Users may rebase the FSP binary at a different location with Intel's Binary Configuration Tool (BCT) or SplitFspBin.py before integrating to the boot loader.

For other assumptions and conventions, please refer to Chapter 8 and 9 of the FSP External Architecture Specification version 2.2.

3.2 Boot Flow

Please refer Chapter 7 in the FSP External Architecture Specification version 2.2 for Boot flow chart. The FSP for this platform supports dispatch mode, see Chapter 7 and 9 of the FSP External Architecture Specification version 2.2 for a description of dispatch mode.

3.3 FSP INFO Header

The FSP has an Information Header that provides critical information that is required by the bootloader to successfully interface with the FSP. The structure of the FSP Information Header is documented in the FSP External Architecture Specification version 2.2 with a HeaderRevision of 5.

3.4 FSP Image ID and Revision

FSP information header contains an Image ID field and an Image Revision field that provide the identification and revision information of the FSP binary. It is important to verify these fields while integrating the FSP as API parameters could change over different FSP IDs and revisions. All the FSP FV segments(FSP-T, FSP-M and FSP-S) must have same FSP Image ID and revision number, using FV segments with different revision numbers in a single FSP image is not valid. The FSP API parameters documented in this integration guide are applicable for the Image ID and Revision specified as below.

The FSP ImageId string in the FSP information header is given by PcdFspImageIdString and the ImageRevision field is given by SiliconInitVersionMajor|Minor|FspVersionRevision|FspVersionBuild (Ex:0x0A001460).

3.5 FSP Global Data

FSP uses some amount of TempRam area to store FSP global data which contains some critical data like pointers to FSP information headers and UPD configuration regions, FSP/Bootloader stack pointers required for stack switching etc. HPET Timer register(2) PcdGlobalDataPointerAddress is reserved to store address of this global data, and hence boot loader should not use this register for any other purpose. If TempRAM initialization is done by boot loader, then HPET has to be initialized to the base so that access to the register will work fine.

3.6 Memory Map

Below diagram represents the memory map allocated by FSP including the FSP specific regions.

System Memory Map
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 4 FSP Dispatch Mode

4 FSP Dispatch Mode

Overview

The FSP for this platform supports dispatch mode. Support for dispatch mode can be detected by checking if FSP_INFO_HEADER->ImageAttribute[BIT1] == 1. Dispatch mode is intended to enable FSP to integrate well in to UEFI bootloader implementations. Dispatch mode implements a boot flow that is as close to a standard UEFI boot flow as possible. In dispatch mode, the FSP is exposed as standard Firmware Volumes (FVs) directly to the bootloader. The PEIMs in these FVs are executed in the same PEI environment as the boot loader. In dispatch mode, the PPI database, PCD database, and HOB list are shared between the boot loader and the FSP.

Blue blocks are from the FSP binary and green blocks are from the bootloader. Blocks with mixed colors indicate that both bootloader and FSP modules are dispatched during that phase of the boot flow. In dispatch mode, the NotifyPhase() API is not used. Instead, FSP-S contains DXE drivers that implement the native callbacks on equivalent events for each of the NotifyPhase() invocations.

In dispatch mode, the the PPI database and PCD database are used for providing policy data from the bootloader to FSP. Because these mechanisms provide a great deal of flexibility, dispatch mode does not constrain the method for passing policy data as strongly as API mode. The following sections describe the dispatch mode policy initialization flow used specifically for this platform.

CONFIG_BLOCK_HEADER
struct _CONFIG_BLOCK_HEADER CONFIG_BLOCK_HEADER
Config Block Header.
_CONFIG_BLOCK_HEADER::Reserved
UINT8 Reserved[2]
Offset 26-27 Reserved for future use.
Definition: ConfigBlock.h:34
_CONFIG_BLOCK_TABLE_STRUCT::NumberOfBlocks
UINT16 NumberOfBlocks
Offset 30-31 Number of config blocks (N)
Definition: ConfigBlock.h:53
_CONFIG_BLOCK_HEADER::Revision
UINT8 Revision
Offset 24 Revision of this config block.
Definition: ConfigBlock.h:32
_CONFIG_BLOCK_TABLE_STRUCT::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
Definition: ConfigBlock.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CONFIG_BLOCK_TABLE_HEADER
struct _CONFIG_BLOCK_TABLE_STRUCT CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
_CONFIG_BLOCK_HEADER::Attributes
UINT8 Attributes
Offset 25 The main revision for config block.
Definition: ConfigBlock.h:33
_CONFIG_BLOCK_TABLE_STRUCT::Rsvd0
UINT8 Rsvd0[2]
Offset 28-29 Reserved for future use.
Definition: ConfigBlock.h:52
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:338
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_CONFIG_BLOCK_TABLE_STRUCT::AvailableSize
UINT32 AvailableSize
Offset 32-35 Current config block table size.
Definition: ConfigBlock.h:54
_CONFIG_BLOCK_HEADER::GuidHob
EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
Definition: ConfigBlock.h:31
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:59 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 4.1 Dispatch Mode Policy Init

  • 4 FSP Dispatch Mode
4.1 Dispatch Mode Policy Init

For the plurality of platform designs, most of the policy options provided by FSP do not need to be modified by the bootloader.

To ease this common case, policy initialization has been broken in to two phases: 1. Policy Init and 2. Policy Update.

Policy Init creates the policy data structures with all default policy values pre-populated. Policy Init is implemented using the factory method pattern. The FSP provides an API to the bootloader for constructing the policy data structures. Because the factory method is provided by the FSP, backwards compatibility is made substantially easier. The FSP can be assured that the policy data structures match the definitions used at the time the FSP was compiled. As long as new fields are added to the bottom of policy structures, the bootloader may continue to use an older version of the policy data structures at compile time and retain compatibility with both new and old FSP binaries.

There are two factory methods, one for FSP-M and one for FSP-S. PeiPreMemPolicyInit() is provided by FSP-M, PeiPolicyInit() is provided by FSP-S. These methods are exposed to the bootloader using PPIs, PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI for FSP-M and PEI_SI_DEFAULT_POLICY_INIT_PPI for FSP-S. The usage of PPIs ensures ABI stability between the FSP and the bootloader.

While Policy Init is implemented by the FSP, Policy Update is implemented by the bootloader. Policy Update uses a read-modify-write operation to apply any motherboard specific settings to the policy data while leaving the default values intact when appropriate. After Policy Update is done, FSP may run its SOC initialization code.

4.1.1 FSP-M Policy Initialization Flow

The follow graph shows the policy initialization flow for FSP-M.

Note
The hollow arrow heads in the flow diagram below indicate that action by the PEI Foundation is required for the flow to proceed.
Note
The function names and PEIMs used by the UEFI PI boot loader are implementation dependent and may vary from those shown here. The function names and PEIMs used by MinPlatform are provided as an example.

Execution of FSP-M begins after FspmWrapperInit() in IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c installs a EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance for FSP-M. This causes the PEI foundation to become aware of the FV(s) in FSP-M, which schedules all PEIMs in FSP-M for dispatch by PEI. This results in the SiInitPreMem PEIM in FSP-M being executed.

One of the actions performed by the SiInitPreMem entry-point is calling the SiInitPrePolicy() function, which installs the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. The DEPEX for MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf requires PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI to exist in the PPI database before SiliconPolicyPeiPreMem can run. While SiliconPolicyPeiPreMem.inf does not directly add PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI to the DEPEX, SiliconPolicyPeiPreMem.inf does statically link against AlderlakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf, which adds PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI to the DEPEX. After the SiInitPreMem entry-point completes the dependency will be satisfied, making SiliconPolicyPeiPreMem eligible for dispatch.

Next SiliconPolicyPeiPreMem PEIM will run. SiliconPolicyPeiPreMemEntryPoint() in MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.c will call SiliconPolicyInitPreMem() in AlderlakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c. This function will locate the instance of PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI previously created by SiInitPreMem and use it to call PeiPreMemSiDefaultPolicyInit() in SiInitPreMem. PeiPreMemSiDefaultPolicyInit() will construct SI_PREMEM_POLICY_PPI, which contains all the policy data needed by FSP-M. SiliconPolicyInitPreMem() will then locate SI_PREMEM_POLICY_PPI and return it to SiliconPolicyPeiPreMemEntryPoint().

Next, SiliconPolicyPeiPreMemEntryPoint() takes the pointer to the policy data returned by SiliconPolicyInitPreMem() and passes it to SiliconPolicyUpdatePreMem(). SiliconPolicyUpdatePreMem() is part of SiliconPolicyUpdateLib, which is statically linked to SiliconPolicyPeiPreMem. SiliconPolicyUpdateLib is special since it is only piece of motherboard specific code in this flow. An example of SiliconPolicyUpdatePreMem() is seen in AlderlakeOpenBoardPkg/AlderlakeMRvp/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c. SiliconPolicyUpdatePreMem() uses a read-modify-write operation to apply any motherboard specific settings to the policy data while leaving the default values intact when appropriate.

After SiliconPolicyUpdatePreMem() applies any motherboard specific updates, SiliconPolicyPeiPreMemEntryPoint() calls SiliconPolicyDonePreMem() in AlderlakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitPreMem.c. SiliconPolicyDonePreMem() dumps the policy data to the debug log (on a DEBUG build of MinPlatform only) and installs the SI_PREMEM_POLICY_READY_PPI. SI_PREMEM_POLICY_READY_PPI tells FSP-M that everything is ready and that it can run the SOC init code now. Installing SI_PREMEM_POLICY_READY_PPI causes the PEI Foundation to signal a PeiServices->NotifyPpi() callback previously set up by SiInitPreMem. This callback invokes SiInitPreMemOnPolicyReady() in SiInitPreMem, which runs MRC and all the other SOC init code in FSP-M.

4.1.1 FSP-S Policy Initialization Flow

Policy Initialization for FSP-S follows essentially the same flow as FSP-M. The primary difference is function and PPI names do not include the "PreMem" qualifier.

Generated on Wed Jan 5 2022 01:25:59 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 4.2 Config Blocks

  • 4 FSP Dispatch Mode
4.2 Config Blocks

Overview

Config Blocks are a binary data serialization format with several unique properties that are useful for firmware implementations.

The serialization format is simple to implement in the C language, minimizing the code needed to implement it; this minimizes the size of the FSP binary. Second, the format is binary backwards compatible; enabling the bootloader to use an older version of the data structure at compile time and retain compatibility with both new and old FSP binaries. Third, the format is mutable in memory without requiring the data to be re-serialized. Finally, the format is position independent with no need for a base address or a rebase operation. This allows the data structure to be moved from pre-memory to post-memory without applying any fixups.

Data in SI_PREMEM_POLICY_PPI and SI_POLICY_PPI are stored using the Config Block format.

4.2.1 Config Block Data Format

In essence, Config Blocks are multiple C structures that are stored in a single continuous memory range using run length encoding.

The overall structure is termed a Config Block Table. The Config Block Table starts with a CONFIG_BLOCK_TABLE_HEADER structure. This header indicates the number of Config Blocks in the Config Block Table, the total size of the table, and the amount of free space remaining in the table. The table may be over-provisioned, which allows additional Config Blocks to be added after the table's initial creation.

The size of all Config Blocks must be an even multiple of 32-bits as all Config Blocks are DWORD aligned. When enumerating a Config Block Table one may assume that all Config Blocks are packed back-to-back, hence the enumeration algorithm can use the length of each config block to find the next config block in the table.

Each Config Block has a GUID that identifies which C structure the Config Block contains. All Config Blocks start with a standardized CONFIG_BLOCK_HEADER, which allows all the structures in the table to be enumerated even if the format of the data payload inside each Config Block is unknown.

typedef struct _CONFIG_BLOCK_HEADER {
EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
UINT8 Revision; ///< Offset 24 Revision of this config block
UINT8 Attributes; ///< Offset 25 The main revision for config block
UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
} CONFIG_BLOCK_HEADER;

The CONFIG_BLOCK_HEADER uses the header of a GUID HOB to store its length and GUID. This makes it easy to copy Config Blocks to the HOB list. Copying Config Blocks to the HOB list is a common use case. Often the ACPI code uses policies that were initially supplied by a Config Block. Copying the Config Block to the HOB list makes it easy for DXE phase to copy any needed policies to the ACPI global NVS memory later.

The Revision field assists with binary backward compatibility. Whenever a new field is added to a Config Block, the new field is added to the bottom of the Config Block and the Revision is incremented by 1. Thus if a bootloader wishes to retain compatibility with new and old versions of the FSP binary, it may do so by either by only using fields that are present in Revision 1 of the Config Block or by checking the Revision number before modifying fields added since Revision 1.

The CONFIG_BLOCK_TABLE_HEADER builds upon the CONFIG_BLOCK_HEADER:

typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
///
/// Individual Config Block Structures are added starting here
///
} CONFIG_BLOCK_TABLE_HEADER;

4.2.2 Config Block Library APIs

To assist in the creation and parsing of Config Blocks, Intel has provided an open source Config Block library in IntelSiliconPkg/Library/BaseConfigBlockLib. This library provides the following functions:

  • GetConfigBlock()
  • AddConfigBlock()
  • CreateConfigBlockTable()

In most cases, bootloaders will only need to call GetConfigBlock().

4.2.3 Config Blocks used by FSP-M

On AlderLake platforms SI_PREMEM_POLICY_PPI contains a Config Block Table. PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI will construct this Config Block Table with all the below Config Blocks pre-populated. Additionally, all the Config Blocks will be initialized with default policy values as described in section 4.1.

SI_PREMEM_POLICY_PPI contains the following Config Blocks:

Todo:
This list is from TigerLake, needs to be updated for AlderLake
  • SI_PREMEM_CONFIG
  • HOST_BRIDGE_PREMEM_CONFIG
  • CPU_CONFIG_LIB_PREMEM_CONFIG
  • CPU_DMI_PREMEM_CONFIG
  • CPU_PCIE_RP_PREMEM_CONFIG
  • CPU_SECURITY_PREMEM_CONFIG
  • CPU_TRACE_HUB_PREMEM_CONFIG
  • CPU_TXT_PREMEM_CONFIG
  • GRAPHICS_PEI_PREMEM_CONFIG
  • HDAUDIO_PREMEM_CONFIG
  • HYBRID_GRAPHICS_CONFIG
  • IPU_PREMEM_CONFIG
  • ISH_PREMEM_CONFIG
  • ME_PEI_PREMEM_CONFIG
  • MEMORY_CONFIG_NO_CRC
  • MEMORY_CONFIGURATION
  • OVERCLOCKING_PREMEM_CONFIG
  • PCH_DCI_PREMEM_CONFIG
  • PCH_GENERAL_PREMEM_CONFIG
  • PCH_HSIO_PCIE_PREMEM_CONFIG
  • PCH_HSIO_SATA_PREMEM_CONFIG
  • PCH_LPC_PREMEM_CONFIG
  • PCH_PCIE_RP_PREMEM_CONFIG
  • PCH_SMBUS_PREMEM_CONFIG
  • PCH_WDT_PREMEM_CONFIG
  • PCIE_PEI_PREMEM_CONFIG
  • PCIE_PREMEM_CONFIG
  • PRAM_PREMEM_CONFIG
  • SA_MISC_PEI_PREMEM_CONFIG
  • TCSS_PEI_PREMEM_CONFIG
  • TELEMETRY_PEI_PREMEM_CONFIG
  • TWOLM_PREMEM_CONFIG
  • VTD_CONFIG

4.2.4 Config Blocks used by FSP-S

On AlderLake platforms SI_POLICY_PPI contains a Config Block Table. PEI_SI_DEFAULT_POLICY_INIT_PPI will construct this Config Block Table with all the below Config Blocks pre-populated. Additionally, all the Config Blocks will be initialized with default policy values as described in section 4.1.

SI_POLICY_PPI contains the following Config Blocks:

Todo:
This list is from TigerLake, needs to be updated for AlderLake
  • SI_CONFIG
  • HOST_BRIDGE_PEI_CONFIG
  • ADR_CONFIG
  • AMT_PEI_CONFIG
  • BIOS_GUARD_CONFIG
  • CNVI_CONFIG
  • CPU_CONFIG
  • CPU_PCIE_CONFIG
  • CPU_PID_TEST_CONFIG
  • CPU_POWER_MGMT_BASIC_CONFIG
  • CPU_POWER_MGMT_CUSTOM_CONFIG
  • CPU_POWER_MGMT_PSYS_CONFIG
  • CPU_POWER_MGMT_TEST_CONFIG
  • CPU_POWER_MGMT_VR_CONFIG
  • CPU_TEST_CONFIG
  • GBE_CONFIG
  • GNA_CONFIG
  • GRAPHICS_PEI_CONFIG
  • HDAUDIO_CONFIG
  • HYBRID_STORAGE_CONFIG
  • IEH_CONFIG
  • ISH_CONFIG
  • ME_PEI_CONFIG
  • PCH_DMI_CONFIG
  • PCH_ESPI_CONFIG
  • PCH_FIVR_CONFIG
  • PCH_FLASH_PROTECTION_CONFIG
  • PCH_GENERAL_CONFIG
  • PCH_HSIO_CONFIG
  • PCH_INTERRUPT_CONFIG
  • PCH_IOAPIC_CONFIG
  • PCH_LOCK_DOWN_CONFIG
  • PCH_P2SB_CONFIG
  • PCH_PCIE_CONFIG
  • PCH_PM_CONFIG
  • PEI_ITBT_CONFIG
  • PSF_CONFIG
  • RST_CONFIG
  • RTC_CONFIG
  • SA_MISC_PEI_CONFIG
  • SATA_CONFIG
  • SERIAL_IO_CONFIG
  • TCSS_PEI_CONFIG
  • TELEMETRY_PEI_CONFIG
  • THC_CONFIG
  • THERMAL_CONFIG
  • TSN_CONFIG
  • USB_CONFIG
  • USB2_PHY_CONFIG
  • USB3_HSIO_CONFIG
  • VMD_PEI_CONFIG
CONFIG_BLOCK_HEADER
struct _CONFIG_BLOCK_HEADER CONFIG_BLOCK_HEADER
Config Block Header.
_CONFIG_BLOCK_HEADER::Reserved
UINT8 Reserved[2]
Offset 26-27 Reserved for future use.
Definition: ConfigBlock.h:34
_CONFIG_BLOCK_TABLE_STRUCT::NumberOfBlocks
UINT16 NumberOfBlocks
Offset 30-31 Number of config blocks (N)
Definition: ConfigBlock.h:53
_CONFIG_BLOCK_HEADER::Revision
UINT8 Revision
Offset 24 Revision of this config block.
Definition: ConfigBlock.h:32
_CONFIG_BLOCK_TABLE_STRUCT::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
Definition: ConfigBlock.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CONFIG_BLOCK_TABLE_HEADER
struct _CONFIG_BLOCK_TABLE_STRUCT CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.
_CONFIG_BLOCK_HEADER::Attributes
UINT8 Attributes
Offset 25 The main revision for config block.
Definition: ConfigBlock.h:33
_CONFIG_BLOCK_TABLE_STRUCT::Rsvd0
UINT8 Rsvd0[2]
Offset 28-29 Reserved for future use.
Definition: ConfigBlock.h:52
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:338
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_CONFIG_BLOCK_TABLE_STRUCT::AvailableSize
UINT32 AvailableSize
Offset 32-35 Current config block table size.
Definition: ConfigBlock.h:54
_CONFIG_BLOCK_HEADER::GuidHob
EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
Definition: ConfigBlock.h:31
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 4.3 FSP Error Information

  • 4 FSP Dispatch Mode
4.3 FSP Error Information

In the case of a fatal error occurring during the execution of the FSP, it may not be possible for the FSP to continue.

If a fatal error that prevents the successful completion of the FSP occurs, the FSP may use FSP_ERROR_INFO to report this error to the bootloader. During PEI phase, (*PeiServices)->ReportStatusCode() shall be used to transmit this error notification to the bootloader. During DXE phase, EFI_STATUS_CODE_PROTOCOL.ReportStatusCode() shall be used to transmit this error notification to the bootloader. The bootloader must ensure that ReportStatusCode() services are available before FSP-M begins execution.

typedef struct {
EFI_STATUS_CODE_DATA DataHeader;
EFI_GUID ErrorType;
EFI_STATUS Status;
} FSP_ERROR_INFO;

FSP_ERROR_INFO is provided as the optional EFI_STATUS_CODE_DATA parameter to ReportStatusCode(). EFI_STATUS_CODE_DATA provides a CallerId GUID, this CallerId combined with the ErrorType GUID describes the error to the bootloader. The FSP for this platform implements the following CallerId GUIDs:

CallerId | Description
{0x1f4dc7e9, 0x26ca, 0x4336, {0x8c, 0xe3, 0x39, 0x31, 0x03, 0xb5, 0xf3, 0xd7}} | ME
{0x98230916, 0xe632, 0x49ff, {0x81, 0x81, 0x55, 0xce, 0xe5, 0x10, 0x36, 0x89}} | System Agent
{0x5a47c211, 0x642f, 0x4f92, {0x9c, 0xb3, 0x7f, 0xeb, 0x93, 0xda, 0xdd, 0xba}} | MRC

If the CallerId parameter is not a GUID in the table above, then it should be the GUID that identifies the PEIM or DXE driver which was executing at the time of the error.

The following ErrorType GUIDs are implemented:

ErrorType | Description
{0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39, 0x61, 0xc3, 0xab, 0xde, 0x15}} | ME EOP failure
{0x8106a5cc, 0x30ba, 0x41cf, {0xa1, 0x78, 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}} | SA PEI GOP Init failure
{0x348cc7fe, 0x1e9a, 0x4c7a, {0x86, 0x28, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}} | SA PEI GOP GetMode failure
{0x5de1c071, 0x2c9c, 0x4a53, {0x80, 0x21, 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}} | MRC training failure

When the FSP calls ReportStatusCode(), the Type parameter's EFI_STATUS_CODE_TYPE_MASK must be EFI_ERROR_CODE with the EFI_STATUS_CODE_SEVERITY_MASK >= EFI_ERROR_UNRECOVERED. The Value and Instance parameters must be 0.

The bootloader must register a listener for this status code. This listener should check if DataHeader.Type == STATUS_CODE_DATA_TYPE_FSP_ERROR_GUID to detect an FSP_ERROR_INFO notification. If an FSP_ERROR_INFO notification is encountered, the bootloader should assume that normal operation is no longer possible. In debug scenarios, this notification should be considered an ASSERT.

EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:26:00 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 4.4 Dispatch Mode Integration

  • 4 FSP Dispatch Mode
4.4 Dispatch Mode Integration

Dispatch Mode Integration Notes:

  1. The FSP for this platform contains PEIMs compiled for the IA32 architecture. The boot loader therefore must utilize a PEI Foundation compiled for the IA32 architecture.
  2. Since the FSP binary can be integrated into flash at any address, the boot loader has to report FSP FVs to the PEI and DXE dispatcher using PI specification defined mechanisms so PEIMs and DXE drivers inside the FSP Binary can be dispatched. FspmWrapperPeim and FspsWrapperPeim from IntelFsp2WrapperPkg can aid in implementing this.
  3. For this platform, FSP-T, FSP-M, and FSP-S contain 1 FV each.
  4. The FSP distribution package will include a DSC file which contains all DynamicEx PCDs consumed by the FSP binary. The boot loader should include the DSC during its build process so that any PCDs defined by this DSC file are included in the boot loader's PCD database. This enables the boot loader and FSP to share a single PCD database.
    • A NULL library (FspPcdListLibNull.inf) is included in the FSP distribution package. This library should be included in one of the boot loader's PEIMs. This ensures all DynamicEx PCDs used by the FSP are included in the boot loader's PCD database. One can fulfill this requirement by including the following code snippet in *BoardPkg.dsc:
      IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {
      <LibraryClasses>
      !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0
      #
      # In FSP Dispatch mode below dummy library should be linked to bootloader PEIM
      # to build all DynamicEx PCDs that FSP consumes into bootloader PCD database.
      #
      NULL|$(PLATFORM_FSP_BIN_PACKAGE)/Library/FspPcdListLib/FspPcdListLibNull.inf
      !endif
      }
  5. The boot loader must provide at minimum 284KB of stack and 128KB of HOB heap to execute FSP on this platform.
  6. In dispatch mode, the boot loader should not use FSP API calls described in chapter 5 of this document or chapter 8 of the FSP External Architecture Specification version 2.2. The TempRamInit API is the only exception, it is supported in both API mode and dispatch mode. All other APIs (MemoryInit, SiliconInit, etc.) should not be invoked.
  7. For dispatch mode, FSP contains x64 DXE drivers to replace the NotifyPhase API. This eliminates thunking from 64bit to 32bit when using FSP dispatch mode. The boot loader should remove S3EndOfPeiNotify and FspWrapperNotifyDxe since they are no longer used in dispatch mode.
  8. EFI_PEI_CORE_FV_LOCATION_PPI should be installed by the boot loader's SEC phase. EFI_PEI_CORE_FV_LOCATION_PPI.PeiCoreFvLocation should point to the first Firmware Volume (FV) in FSP-M so the PeiCore inside FSP will be invoked. If EFI_PEI_CORE_FV_LOCATION_PPI is not installed or PeiCore cannot be found at the address specified by EFI_PEI_CORE_FV_LOCATION_PPI.PeiCoreFvLocation, the PeiCore from the Boot Firmware Volume (BFV) will be invoked instead.
  9. FSP-S requires multi-threaded code to complete silicon initialization on this platform. FSP-S includes the UefiCpuPkg/CpuMpPei/CpuMpPei.inf PEIM to provide multiprocessing. The bootloader can choose to either use the MP_SERVICES provided by the FSP for all PEIMs or the bootloader may provide an alternative implementation. In either case, only one MP_SERVICES implementation can be active at once. If the bootloader wishes to not use the FSP provided MP_SERVICES, then the bootloader must install the MP_SERVICES_PPI before installing the FV_INFO_PPI for FSP-S. If MP_SERVICES_PPI already exists, then FSP-S will use it and not execute its own implementation.
  10. If you are using the Intel Reference BIOS, some EDK2 overrides may be required for Dispatch Mode, please refer to override folders in reference code or the override EDK2 repo for more details. For open source MinPlatform based firmware, no EDK2 overrides are required.
  11. FSPM_ARCH_CONFIG_PPI->NvsBufferPtr is now a universal policy option (FSP Dispatch Mode and EDK2 native.) To enable the fast MRC training flow, the boot loader or platform code must to install this PPI to restore the previous MRC training data (SA_MISC_PEI_PREMEM_CONFIG->S3DataPtr is obsolete).
  12. Policy initialization Flow Changes:
    • PEIMs from FSP-M/FSP-S should be dispatched early in PEI to produce the DefaultPolicyInit PPIs. -> Bootloader consumes the DefaultPolicyInit PPIs produced by the FSP binary to create the policy PPIs with default settings. -> Bootloader then locates and updates the policy PPIs as needed. -> Bootloader installs the PolicyReadyPpi after policy updates are completed. This signals to the FSP that silicon initialization may proceed.
    • Bootloader shall consume two PPIs produced by FSP binary to create policy PPIs with default settings. These PPIs are:
      • PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
      • PEI_SI_DEFAULT_POLICY_INIT_PPI
    • The bootloader shall call the two functions below after the bootloader has completed any needed policy updates:
      • SiPreMemInstallPolicyReadyPpi()
      • SiInstallPolicyReadyPpi()
  13. Debug message handling in dispatch mode:
    • Before the ReportStatusCode service is ready, a debug built FSP will send debug messages using the FSP-T UPD configuration (passed as FSP-T API input parameter). FSP-T is recommended to be used regardless FSP API mode or Dispatch mode.
    • Once the ReportStatusCode service is ready, a debug built FSP will send debug messages using the ReportStatusCode service.
    • It is recommended that bootloader register a StatusCode listener immediately after the ReportStatusCode service is ready. It is important to register this listener as soon as possible so that all debug messages sent by the FSP are captured.
    • Please refer to section 9.4.7 in the Intel(R) Firmware Support Package External Architecture Specification v2.2 for details about the ReportStatusCode debug message format.
  14. Enable or Disable FSP S3BootScript functionality: Since edk2-stable201911 release the PiDxeS3BootScriptLib supports enabling or disabling S3BootScript functionality by PCD, and FSP consumes this PCD as DynamicEx type to enable or disable internal S3BootScript functionality. Bootloader must configure below PCD before entering DXE phase or before executing FSP DXE drivers.
    • gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable = TRUE if S3BootScript should be enabled.
    • gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable = FALSE if S3BootScript should be disabled.
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 5 FSP API Mode

5 FSP API Mode

Overview

This release of the FSP supports the all APIs required by the FSP External Architecture Specification version 2.2. These APIs are only used when running the FSP in API mode. In Dispatch mode, these APIs are not used (with the exception of TempRamInit.) The FSP information header contains the address offset for these APIs. Register usage is described in the FSP External Architecture Specification version 2.2. Any usage not described by the specification is described in the individual sections below.

The sections below will highlight any changes that are specific to this FSP release.

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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 5.1 FSP APIs

  • 5 FSP API Mode
5.1 FSP APIs

5.1.1 TempRamInit API

Please refer Chapter 8.6 in the FSP External Architecture Specification version 2.2 for complete details including the prototype, parameters and return value details for this API.

TempRamInit does basic early initialization primarily setting up temporary RAM using cache. It returns ECX pointing to beginning of temporary memory and EDX pointing to end of temporary memory + 1. The total temporary ram currently available is given by PcdTemporaryRamSize starting from the base address of PcdTemporaryRamBase. Out of the total temporary memory available, the last PcdFspReservedBufferSize bytes of space are reserved by the FSP for TempRamInit if temporary RAM initialization is done by the FSP. Any remaining space from TemporaryRamBase(ECX) to TemporaryRamBase+TemporaryRamSize-FspReservedBufferSize (EDX) is available for both bootloader and FSP use.

TempRamInit** also sets up the code caching of the region passed in through CodeCacheBase and CodeCacheLength, which are input parameters to TempRamInitApi. if 0 is passed in for CodeCacheBase, the base used will be (4 GB - 1 - CodeCacheLength).

Note
: When programming MTRRs CodeCacheLength will be reduced, if the LLC size on the current processor is smaller than the requested size.

It is a requirement for Firmware to have a Firmware Interface Table (FIT). The FIT contains pointers to each microcode update. The microcode update is loaded for all logical processors before executing the reset vector. If more than one microcode update for the CPU is present, the microcode update with the latest revision is loaded.

FSPT_UPD.MicrocodeRegionBase** and FSPT_UPD.MicrocodeRegionLength are input parameters to TempRamInit API. If these values are 0, FSP will not attempt to update microcode. If MicrocodeRegionBase != 0 and MicrocodeRegionLength != 0, then FSP will search that region for microcode updates. If a newer microcode update revision is found in the region, FSP will load it.

TempRamInit** will program MTRRs values to provide the following memory map:

Memory range | Cache Attribute
0xFEF00000 - 0x00040000 | Write back
CodeCacheBase - CodeCacheLength | Write protect

5.1.2 FspMemoryInit API

Please refer to Chapter 8.7 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

The variable FspmUpdPtr is a pointer to the FSPM_UPD structure which is described in the header file FspmUpd.h.

The bootloader must pass valid a CAR region for FSP through FSPM_UPD.FspmArchUpd.StackBase and FSPM_UPD.FspmArchUpd.StackSize UPDs.

The FSP for this platform will run FspMemoryInit top of the stack provided by the bootloader instead of establishing a separate stack as described by the FSP External Architecture Specification version 2.1/2.2. The memory region provided by the FSPM_UPD.FspmArchUpd.StackBase and FSPM_UPD.FspmArchUpd.StackSize UPDs is used to establish a HOB heap. The names StackBase and StackSize can be confusing since they are NOT used for stack. These names were retained for backwards compatibility with FSP v2.0.

Below are the heap and stack requirements for FSP on this platform:

HOB Heap requirement:

HOB Heap | UPD | Setting
Base | FSPM_UPD.FspmArchUpd.StackBase | Any non-conflict CAR region (0xFEF17F00 as default)
Size | FSPM_UPD.FspmArchUpd.StackSize | at least 128KB

Stack requirement: FSP's stack usage starts from the current stack pointer. The minimum stack size requirement for FSP-M is 284KB.

The bootloader must ensure that sufficient stack space is available to fulfill the FSP-M minimum stack size requirement at the point in execution where FspMemoryInit() is called. The stack allocated by the bootloader must be large enough for both FSP-M as well as any other parent function calls that are still on the stack at the point when FspMemoryInit() is called.

After FspMemoryInit() is completed, permanent memory is available. After this point, the memory pressure experienced early in boot is eliminated. Accordingly, right before FspMemoryInit() exits, any data that needs to be retained for later use by FspSiliconInit() will be copied to permanent memory. FspSiliconInit() will then execute on a second stack.

The base address of HECI device (Bus 0, Device 22, Function 0) is required to be initialized prior to calling FspMemoryInit(). The default address is programmed to 0xFED1A000.

FspMemoryInit() will calculate the memory map by taking into account the size of several memory regions: TSEG, IED, GTT, BDSM, ME stolen, Uncore PMRR, IOT, MOT, DPR, REMAP, TOLUD, TOUUD. These memory regions may not be initialized by FspMemoryInit(), but space will be reserved for them.

5.1.3 TempRamExit API

Please refer to Chapter 8.8 in the FSP external Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

If Boot Loader initializes the Temporary RAM (CAR) and skip calling TempRamInit API, it is expected that bootloader must skip calling this API and bootloader will tear down the temporary memory area setup in the cache and bring the cache to normal mode of operation.

The FSP for this platform doesn't have any input parameters for this API. The value of TempRamExitParamPtr should be NULL.

At the end of TempRamExit the original code and data cache are disabled. FSP will reconfigure all MTRRs as described in the table below. These MTRR values optimize performance in most scenarios. If the boot loader wishes to configure the MTRRs differently, they can be reprogrammed immediately after this API call.

Memory range | Cache Attribute
0xFF000000 - 0xFFFFFFFF (Flash region) | Write protect
0x00000000 - 0x0009FFFF | Write back
0x000C0000 - Top of Low Memory | Write back
xxxx - xxxx | x *Note1
0x100000000 - Top of High Memory | Write back *Note2

Stack requirement: 4KB of free stack space should be provided to execute TempRamExit.

Note1: Certain silicon features require specific cache types for specific memory ranges. These ranges will be configured by FSP when such features are enabled.

Note2: In some cases MTRRs might not be enough to cover all desired regions, in this case memory regions need to be adjusted for better alignment (e.g., adjust MmioSize or MmioSizeAdjustment UPD) Covering flash region and above 4GB memory is another case which may consume more MTRRs, when there is not enough MTRR available FSP will only cover above 4GB memory partially. In this case the boot loader can optimize MTRRs to remove flash from the cached regions after all needed data is loaded from flash and before booting the OS.

5.1.4 FspSiliconInit API

Please refer to Chapter 8.9 in the FSP external Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

The variable FspsUpdPtr is a pointer to the FSPS_UPD structure which is described in the header file FspsUpd.h.

It is expected that the boot loader will adjust MTRRs for SBSP if needed after TempRamExit but before entering FspSiliconInit. If the MTRRs are not programmed properly, boot performance can be impacted.

The region of 0x5_8000 - 0x5_8FFF is used by FspSiliconInit for starting APs. If this data is important to bootloader, then bootloader needs to preserve it before calling FspSiliconInit.

FspSiliconInit requires multi-threaded code to complete silicon initialization on this platform. FSP includes the UefiCpuPkg/CpuMpPei/CpuMpPei.inf PEIM to provide multiprocessing. Accordingly, the boot loader must expect FSP to perform an INIT-SIPI-SIPI during FspSiliconInit and NotifyPhase which will take control of all APs in the system and restart them. This will kill any background threads that were running on the APs. In some cases, this may not be desirable. As an alternative, the boot loader may provide an instance of the EFI_PEI_MP_SERVICES_PPI through the FspsUpd->FspsConfig.CpuMpPpi UPD for the FSP to use instead of the built-in implementation. This is entirely optional, if callbacks from FSP to the boot loader are not desired, one may set FspsUpd->FspsConfig.CpuMpPpi == NULL.

In summary, there are two methods that FSP can use for performing multiprocessing:

  1. Using the multiprocessing services built-in to the FSP.
  2. Using the boot loader's multiprocessing services.

Using method #1, the boot loader will set FspsUpd->FspsConfig.CpuMpPpi == NULL. If this UPD is NULL, then FSP will use its built-in MP services implementation for multiprocessing. Accordingly, the boot loader must expect FSP to perform an INIT-SIPI-SIPI during FspSiliconInit and NotifyPhase which will take control of all APs in the system and restart them. This will kill any background threads that were running on the APs.

Note: If bootloader needs to take control of APs back, a full AP re-initialization is required after FSP-S completed and control has been transferred back to bootloader.

Using method #2, the boot loader will set FspsUpd->FspsConfig.CpuMpPpi != NULL. If this UPD is not NULL, it must point to an instance of EFI_PEI_MP_SERVICES_PPI. When the FSP needs to perform multiprocessing, it will use the EFI_PEI_MP_SERVICES_PPI instance provided by the boot loader to do so. Accordingly, the boot loader must expect the function pointers in EFI_PEI_MP_SERVICES_PPI to be invoked in the middle of the execution of FspSiliconInit and NotifyPhase.

It is a requirement for the bootloader to have a Firmware Interface Table (FIT), which contains pointers to each microcode. The microcode is loaded for all cores before reset vector. If more than one microcode update for the CPU is present, the latest revision is loaded.

MicrocodeRegionBase and MicrocodeRegionLength are both input parameters to TempRamInit and UPD for SiliconInit API. UPD has priority and will be searched for a later revision than TempRamInit. If MicrocodeRegionBase and MicrocodeRegionLength values are 0, FSP will not attempt to update the microcode. If a microcode region is passed, FSP will search that region for microcode updates. If a newer microcode update revision is found in the region, FSP will load it.

FspSiliconInit initializes PCH audio. This includes selecting the HD Audio verb table and initializing the audio CODEC.

FspSiliconInit initializes the following PCH features: HECI, USB, HSIO, Integrated Sensor Hub, Camera, PCI Express, DMI, Vt-d.

FspSiliconInit initializes the following CPU features: XD, VMX, AES, IED, HDC, x(2)APIC, Intel® Processor Trace, Three Strike Counter, Machine Check, Cache Pre-fetchers, Core PMRR, and Power Management.

FspSiliconInit initializes Internal Graphics. During this initialization, FSP publishes the EFI_PEI_GRAPHICS_INFO_HOB and the EFI_PEI_GRAPHICS_DEVICE_INFO_HOB. These HOBs will not be published during S3 resume as FSP will not initialize the internal graphics frame buffer during S3 resume.

FspSiliconInit programs SA BARs: MchBar, DmiBar, EpBar, GdxcBar, EDRAM (if supported). Please refer to section 2.8 (MemoryMap) for the corresponding Bar values. GttMmadr (0xDF000000) and GmAdr(0xC0000000) are temporarily programmed and cleared after use in FSP.

Stack requirement: 4KB of free stack space should be provided to execute FspSiliconInit.

5.1.5 FspMultiPhaseSiInit API

Please refer Chapter 8.10 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

If the FspMultiPhaseSiInit API is enabled (by setting FSPS_ARCH_UPD->EnableMultiPhaseSiliconInit UPD to 1 before the FspSiliconInit API is invoked), the bootloader should call this API with the MultiPhaseAction parameter set to 0 to get the NumberOfPhases supported by this platform. FSP will return control back to the bootloader NumberOfPhases times and then the bootloader should call FspMultiPhaseSiInit API with the MultiPhaseAction parameter set to 1 by NumberOfPhases times.

Note
: Disable FSPS_ARCH_UPD->EnableMultiPhaseSiliconInit when we disable FSP_M_CONFIG->TcssXhciEn.

This platform supports the following MultiPhaseSiInit phase(s):

Phase | FSP return point | Purpose
1 | After TCSS initialization completed | for TCSS board specific initialization from bootloader side

5.1.6 NotifyPhase API

Please refer Chapter 8.11 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for this API.

Stack requirement: 4KB of free stack space should be provided to execute NotifyPhase.

5.1.6.1 PostPciEnumeration Notification

This phase EnumInitPhaseAfterPciEnumeration is to be called after PCI enumeration but before execution of third party code such as option ROMs. It includes powering down unused PCH SATA ports, locking registers in PMC, DMI, TCO, and SPI Flash (DLOCK + WRSDIS + FLOCKDN). It also includes enabling bus mastering for eSPI connected devices.

5.1.6.2 ReadyToBoot Notification

This phase EnumInitPhaseReadyToBoot is to be called before giving control to the operating system. It includes some final initialization steps recommended by the BWG, including power management settings, and sending ME Message EOP (End of Post).

5.1.6.3 EndOfFirmware Notification

This phase EnumInitEndOfFirmware is to be called before the firmware/preboot environment transfers management of all system resources to the OS or next level execution environment. It includes final locking of chipset registers.

5.1.7 FSP Events API

Please refer Chapter 8.5 in the FSP External Architecture Specification version 2.2 for the prototype, parameters and return value details for these APIs.

This platform supports FSP Events which re-direct debug messages to event handlers provided by bootloader. To enable this function the bootloader must provide event handler function pointers via UPDs.

FSP phase | UPD for bootloader to pass handler function pointer
FSP-T | FSPT_ARCH_UPD -> FspDebugHandler
FSP-M | FSPM_ARCH_UPD -> FspEventHandler
FSP-S | FSPS_ARCH_UPD -> FspEventHandler
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 5.2 Reset Return Codes

  • 5 FSP API Mode
5.2 Reset Return Codes

As per FSP External Architecture Specification version 2.0/2.1/2.2, any reset required in the FSP flow will be reported by returning one of the FSP_STATUS_RESET_REQUIRED* return codes.

It is the boot loader's responsibility to reset the system according to the reset type requested.

Below table specifies the return status returned by FSP API and the requested reset type.

FSP_STATUS_RESET_REQUIRED Code | Reset Type requested
0x40000001 | Cold Reset
0x40000002 | Warm Reset
0x40000003 | Global Reset - Puts the system through a Global Reset through HECI or a Full Reset through PCH
0x40000004 | Reserved
0x40000005 | Reserved
0x40000006 | Reserved
0x40000007 | Reserved
0x40000008 | Reserved
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 5.3 UPD Porting Guide

  • 5 FSP API Mode
5.3 UPD Porting Guide

Recommended values for UPDs:

UPD | Dependency | Description | Value
CstateLatencyControl1Irtl | Server platform | Server platform should has different setting | 0x6B
PchPcieHsioRxSetCtleEnable | Board design | Different board requires different value | tune
PchPcieHsioRxSetCtle | Board design | Different board requires different value | tune
PchSataHsioRxGen3EqBoostMagEnable | Board design | Different board requires different value | tune
PchSataHsioRxGen3EqBoostMag | Board design | Different board requires different value | tune
PchSataHsioTxGen1DownscaleAmpEnable | Board design | Different board requires different value | tune
PchSataHsioTxGen1DownscaleAmp | Board design | Different board requires different value | tune
PchSataHsioTxGen2DownscaleAmpEnable | Board design | Different board requires different value | tune
PchSataHsioTxGen2DownscaleAmp | Board design | Different board requires different value | tune
PchNumRsvdSmbusAddresses | Board design | Different board requires different value | tune
RsvdSmbusAddressTablePtr | Board design | Different board requires different value | tune
BiosSize | Board design | Different board requires different value | tune
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 6 Porting Recommendations

6 Porting Recommendations

Here are some notes and recommendations for adapting an existing boot loader to FSP.

6.1 Locking PAM register

FSP 2.0 introduced the EndOfFirmware Notify phase callback which is the recommended place for locking PAM registers. Accordingly, by default FSP locks the PAM registers during the EndOfFirmware Notify phase. If the EndOfFirmware Notify phase is too early to lock PAM registers, then the PAM locking code inside the FSP can be disabled by setting the UPD -> FSP_S_TEST_CONFIG -> SkipPamLock or SA policy -> _SI_PREMEM_POLICY_STRUCT -> SA_MISC_PEI_CONFIG -> SkipPamLock. If the PAM locking code inside the FSP is skipped, then the boot loader must lock the PAM registers before booting the OS. by programming one PCI config space register as below.

The PAM registers must be locked in all boot paths including S3 resume. To lock the PAM registers, program the following lock bit:

MmioOr32 (B0: D0: F0: Register 0x80, BIT0)

6.2 Locking SMRAM register

It is recommended that SMRAM be locked before any third party code (e.g. OpROM) execution. The point in execution where third party OpROMs begin executing can vary depending on the boot loader implementation. To provide flexibility, the FSP by default will not lock it. The boot loader should lock SMRAM by programming the following lock bit before any third party OpROM execution. Additionally, SMRAM should be locked before the EnumInitPhaseReadyToBoot notify phase is called. During S3 resume, the lock bit should be set right before the OS wake vector.

PciOr8 (B0: D0: F0: Register 0x88, BIT4);
Note: This register must be programmed using the legacy CF8/CFC PCI access mechanism. (MMIO access will not work)

6.3 Locking SMI register

It is recommended that the global SMI bit is locked before any third party code (e.g. OpROM) execution. SMM initialization flows may vary depending on boot loader implementation details. Accordingly, FSP will not lock it by default. The boot loader is responsible for locking the following registers after SMM configuration is complete. Set AcpiBase + 0x30[0] to 1b to enable global SMI. Set PMC PCI offset A0h[4] = 1b to lock SMI.

6.4 Verify below settings are correct for your platforms

PMC PCI configuration space is not PCI specification compliant. The FSP will hide the PMC controller to avoid external software or OS from corrupting the BAR addresses. FSP will program the PMC controller IO and MMIO BAR's with below addresses. Please use these addresses in the boot loader code instead of reading BAR addresses from the PMC controller.

Register | Values
ABASE | 0x1800
PWRMBASE | 0xFE000000
PCIEXBAR_BASE_ADDRESS | 0xE0000000
Note
:
  • Boot Loader can use a different value for PCIEXBAR_BASE_ADDRESS either by modifying the UPD (under FSP-T) or by overriding the PCIEXBAR (B0:D0:F0:R60h) before calling FspMemoryInit.
  • Boot Loader should avoid using conflicting address when reprogramming PCIEXBAR_BASE_ADDRESS than the recommended one.
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 7 FSP Output

7 FSP Output

The FSP builds a series of data structures called Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon.

Please refer to the Platform Initialization (PI) Specification - Volume 3: Shared Architectural Elements specification for PI Architectural HOBs. Please refer Chapter 10 in the FSP External Architecture Specification version 2.2 for details about FSP Architectural HOBs.

The sections below describe the HOBs not covered in the above two specifications.

7.1 SMRAM Resource Descriptor HOB

The FSP will report the system SMRAM T-SEG range through a generic resource HOB if T-SEG is enabled. The owner field of the HOB identifies the owner as T-SEG.

#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }

7.2 SMBIOS INFO HOB

The FSP will report the SMBIOS through a HOB with below GUID. This information can be consumed by the bootloader to produce the SMBIOS tables. These structures are included as part of MemInfoHob.h, SmbiosCacheInfoHob.h, SmbiosProcessorInfoHob.h, & FirmwareVersionInfoHob.h

#define SI_MEMORY_INFO_DATA_HOB_GUID \
{ 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } };
typedef struct {
MrcDimmStatus Status; ///< See MrcDimmStatus for the definition of this field.
UINT8 DimmId;
UINT32 DimmCapacity; ///< DIMM size in MBytes.
UINT16 MfgId;
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE_DATA]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
} DIMM_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this channel should be used.
UINT8 ChannelId;
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
MRC_CH_TIMING Timing[MAX_PROFILE]; ///< The channel timing values.
DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
} CHANNEL_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this controller should be used.
UINT16 DeviceId; ///< The PCI device id of this memory controller.
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
} CONTROLLER_INFO;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
UINT8 Revision;
UINT16 DataWidth;
/// As defined in SMBIOS 3.0 spec
/// Section 7.18.2 and Table 75
UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
/// As defined in SMBIOS 3.0 spec
/// Section 7.17.3 and Table 72
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
UINT32 FreqMax;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
UINT8 XmpProfileEnable;
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE];
CONTROLLER_INFO Controller[MAX_NODE];
} MEMORY_INFO_DATA_HOB;
#define SI_MEMORY_PLATFORM_DATA_HOB \
{ 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
typedef struct {
UINT8 Revision;
UINT8 Reserved[3];
UINT32 BootMode;
UINT32 TsegSize;
UINT32 TsegBase;
UINT32 PrmrrSize;
UINT32 PrmrrBase;
UINT32 GttBase;
UINT32 MmioSize;
UINT32 PciEBaseAddress;
} MEMORY_PLATFORM_DATA;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
MEMORY_PLATFORM_DATA Data;
UINT8 *Buffer;
} MEMORY_PLATFORM_DATA_HOB;
#define SMBIOS_CACHE_INFO_HOB_GUID \
{ 0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7} }
///
/// SMBIOS Cache Info HOB Structure
///
typedef struct {
UINT16 ProcessorSocketNumber;
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
///String Buffer - each string terminated by NULL "0x00"
///String buffer terminated by double NULL "0x0000"
} SMBIOS_CACHE_INFO;
#define SMBIOS_PROCESSOR_INFO_HOB_GUID \
{ 0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71} }
///
/// SMBIOS Processor Info HOB Structure
///
typedef struct {
UINT16 TotalNumberOfSockets;
UINT16 CurrentSocketNumber;
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
///This info is used for both ProcessorFamily and ProcessorFamily2 fields
///See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
UINT16 ProcessorFamily;
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
///This info is used for both CoreCount & CoreCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.6
UINT16 CoreCount;
///This info is used for both CoreEnabled & CoreEnabled2 fields
///See detailed description in SMBIOS Spec v3.0 Section 7.5.7
UINT16 EnabledCoreCount;
///This info is used for both ThreadCount & ThreadCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.8
UINT16 ThreadCount;
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
/// String Buffer - each string terminated by NULL "0x00"
/// String buffer terminated by double NULL "0x0000"
} SMBIOS_PROCESSOR_INFO;
#define SMBIOS_FIRMWARE_VERSION_INFO_HOB_GUID \
{ 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}
///
/// Firmware Version Structure
///
typedef struct {
UINT8 MajorVersion;
UINT8 MinorVersion;
UINT8 Revision;
UINT16 BuildNumber;
} FIRMWARE_VERSION;
///
/// Firmware Version Information Structure
///
typedef struct {
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
} FIRMWARE_VERSION_INFO;
///
/// The Smbios structure header.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Handle;
} SMBIOS_STRUCTURE;
///
/// Firmware Version Information HOB Structure
///
typedef struct {
SMBIOS_STRUCTURE Header; ///< SMBIOS structure header
UINT8 Count; ///< Number of FVI entries in this structure
INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s)
///
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
///
} FIRMWARE_VERSION_INFO_HOB;

7.3 CHIPSETINIT INFO HOB

The FSP will report the ChipsetInit CRC through a HOB with below GUID. This information can be consumed by the bootloader to check if ChipsetInit CRC is matched between BIOS and ME. These structures are included as part of FspsUpd.h

#define CHIPSETINIT_INFO_HOB_GUID \
{ 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
///
/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
///
typedef struct {
UINT8 Revision;
UINT8 Rsvd[3];
UINT16 MeChipInitCrc;
UINT16 BiosChipInitCrc;
} CHIPSET_INIT_INFO;

7.4 HOB USAGE INFO HOB

The FSP will report the Hob memory usage through a HOB with below GUID. This information can be consumed by the bootloader to check how much temporary RAM is left.

#define HOB_USAGE_DATA_HOB_GUID \
{0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
typedef struct {
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
UINTN FreeMemory;
} HOB_USAGE_DATA_HOB;

7.5 FSP_ERROR_INFO_HOB

In the case of an error occurring during the execution of the FSP, the FSP may produce this HOB which describes the error in more detail. FSP_ERROR_INFO_HOB is only used in FSP API Mode. In FSP Dispatch Mode, FSP may call ReportStatusCode() and provide a FSP_ERROR_INFO structure using the PI status code services.

#define FSP_ERROR_INFO_HOB_GUID \
{0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
typedef struct {
EFI_HOB_GUID_TYPE GuidHob;
EFI_STATUS_CODE_TYPE Type;
EFI_STATUS_CODE_VALUE Value;
UINT32 Instance;
EFI_GUID CallerId;
EFI_GUID ErrorType;
UINT32 Status;
} FSP_ERROR_INFO_HOB;

The FSP for this platform implements the following CallerId GUIDs:

CallerId | Description
{0x1f4dc7e9, 0x26ca, 0x4336, {0x8c, 0xe3, 0x39, 0x31, 0x03, 0xb5, 0xf3, 0xd7}} | ME
{0x98230916, 0xe632, 0x49ff, {0x81, 0x81, 0x55, 0xce, 0xe5, 0x10, 0x36, 0x89}} | System Agent
{0x5a47c211, 0x642f, 0x4f92, {0x9c, 0xb3, 0x7f, 0xeb, 0x93, 0xda, 0xdd, 0xba}} | MRC

The following ErrorType GUIDs are implemented:

ErrorType | Description
{0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39, 0x61, 0xc3, 0xab, 0xde, 0x15}} | ME EOP failure
{0x8106a5cc, 0x30ba, 0x41cf, {0xa1, 0x78, 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}} | SA PEI GOP Init failure
{0x348cc7fe, 0x1e9a, 0x4c7a, {0x86, 0x28, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}} | SA PEI GOP GetMode failure
{0x5de1c071, 0x2c9c, 0x4a53, {0x80, 0x21, 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}} | MRC training failure
SMBIOS_STRUCTURE
The Smbios structure header.
Definition: FirmwareVersionInfoHob.h:48
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
FSP_ERROR_INFO_HOB
FSP Error Information Block.
Definition: FspErrorInfo.h:60
FIRMWARE_VERSION_INFO_HOB
Firmware Version Information HOB Structure.
Definition: FirmwareVersionInfoHob.h:58
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:338
FIRMWARE_VERSION
Firmware Version Structure.
Definition: FirmwareVersionInfoHob.h:28
FIRMWARE_VERSION_INFO
Firmware Version Information Structure.
Definition: FirmwareVersionInfoHob.h:38
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:26:00 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: 8 POST Codes

8 POST Codes

The FSP outputs 16-bit POST codes to indicate which API and which module is currently executing.

Bit Range | Description
Bit15 - Bit12 (X) | used to indicate the phase/api under which the code is executing
Bit11 - Bit8 (Y) | used to indicate the module
Bit7 (ZZ bit 7) | reserved for error
Bit6 - Bit0 (ZZ) | individual codes

8.1 POST Code Info

The diagram below illustrates how sub-fields are encoded in the POST codes produced by the FSP.

8.1.1 TempRamInit API Status Codes (0xFxxx)

PostCode | Module | Description
0x0000 | FSP | TempRamInit API Entry (The change in upper byte is due to not enabling of the Port81 early in the boot)
0x007F | FSP | TempRamInit API Exit

8.1.2 FspMemoryInit API Status Codes (0xDxxx)

PostCode | Module | Description
0xD800 | FSP | FspMemoryInit API Entry
0xD87F | FSP | FSpMemoryInit API Exit
0xDA00 | SA | Pre-Mem SaInit Entry
0xDA02 | SA | OverrideDev0Did Start
0xDA04 | SA | OverrideDev2Did Start
0xDA06 | SA | Programming SA Bars
0xDA08 | SA | Install SA HOBs
0xDA0A | SA | Reporting SA PCIe code version
0xDA0C | SA | SaSvInit Start
0xDA10 | SA | Initializing DMI
0xDA15 | SA | Initialize TCSS PreMem
0xDA1F | SA | Initializing DMI/OPI Max PayLoad Size
0xDA20 | SA | Initializing SwitchableGraphics
0xDA30 | SA | Initializing SA PCIe
0xDA3F | SA | Programming PEG credit values Start
0xDA40 | SA | Initializing DMI Tc/Vc mapping
0xDA42 | SA | CheckOffboardPcieVga
0xDA44 | SA | CheckAndInitializePegVga
0xDA50 | SA | Initializing Graphics
0xDA52 | SA | Initializing System Agent Overclocking
0xDA7F | SA | Pre-Mem SaInit Exit
0xDB00 | PCH | Pre-Mem PchInit Entry
0xDB02 | PCH | Pre-Mem Disable PCH fused controllers
0xDB15 | PCH | Pre-Mem SMBUS configuration
0xDB48 | PCH | Pre-Mem PchOnPolicyInstalled Entry
0xDB49 | PCH | Pre-Mem Program HSIO
0xDB4A | PCH | Pre-Mem DCI configuration
0xDB4C | PCH | Pre-Mem Host DCI enabled
0xDB4D | PCH | Pre-Mem Trace Hub - Early configuration
0xDB4E | PCH | Pre-Mem Trace Hub - Device disabled
0xDB4F | PCH | Pre-Mem TraceHub - Programming MSR
0xDB50 | PCH | Pre-Mem Trace Hub - Power gating configuration
0xDB51 | PCH | Pre-Mem Trace Hub - Power gating Trace Hub device and locking HSWPGCR1 register
0xDB52 | PCH | Pre-Mem Initialize HPET timer
0xDB55 | PCH | Pre-Mem PchOnPolicyInstalled Exit
0xDB7F | PCH | Pre-Mem PchInit Exit
0xDC00 | CPU | CPU Pre-Mem Entry
0xDC0F | CPU | CpuAddPreMemConfigBlocks Done
0xDC20 | CPU | CpuOnPolicyInstalled Start
0xDC2F | CPU | XmmInit Start
0xDC3F | CPU | TxtInit Start
0xDC4F | CPU | Init CPU Straps
0xDC5F | CPU | Init Overclocking
0xDC6F | CPU | CPU Pre-Mem Exit
0x**55 | SA | MRC_MEM_INIT_DONE
0x**D5 | SA | MRC_MEM_INIT_DONE_WITH_ERRORS
0xDD00 | SA | MRC_INITIALIZATION_START
0xDD10 | SA | MRC_CMD_PLOT_2D
0xDD1B | SA | MRC_FAST_BOOT_PERMITTED
0xDD1C | SA | MRC_RESTORE_NON_TRAINING
0xDD1D | SA | MRC_PRINT_INPUT_PARAMS
0xDD1E | SA | MRC_SET_OVERRIDES_PSPD
0xDD20 | SA | MRC_SPD_PROCESSING
0xDD21 | SA | MRC_SET_OVERRIDES
0xDD22 | SA | MRC_MC_CAPABILITY
0xDD23 | SA | MRC_MC_CONFIG
0xDD24 | SA | MRC_MC_MEMORY_MAP
0xDD25 | SA | MRC_JEDEC_INIT_LPDDR3
0xDD26 | SA | MRC_RESET_SEQUENCE
0xDD27 | SA | MRC_PRE_TRAINING
0xDD28 | SA | MRC_EARLY_COMMAND
0xDD29 | SA | MRC_SENSE_AMP_OFFSET
0xDD2A | SA | MRC_READ_MPR
0xDD2B | SA | MRC_RECEIVE_ENABLE
0xDD2C | SA | MRC_JEDEC_WRITE_LEVELING
0xDD2D | SA | MRC_LPDDR_LATENCY_SET_B
0xDD2E | SA | MRC_WRITE_TIMING_1D
0xDD2F | SA | MRC_READ_TIMING_1D
0xDD30 | SA | MRC_DIMM_ODT
0xDD31 | SA | MRC_EARLY_WRITE_TIMING_2D
0xDD32 | SA | MRC_WRITE_DS
0xDD33 | SA | MRC_WRITE_EQ
0xDD34 | SA | MRC_EARLY_READ_TIMING_2D
0xDD35 | SA | MRC_READ_ODT
0xDD36 | SA | MRC_READ_EQ
0xDD37 | SA | MRC_READ_AMP_POWER
0xDD38 | SA | MRC_WRITE_TIMING_2D
0xDD39 | SA | MRC_READ_TIMING_2D
0xDD3A | SA | MRC_CMD_VREF
0xDD3B | SA | MRC_WRITE_VREF_2D
0xDD3C | SA | MRC_READ_VREF_2D
0xDD3D | SA | MRC_POST_TRAINING
0xDD3E | SA | MRC_LATE_COMMAND
0xDD3F | SA | MRC_ROUND_TRIP_LAT
0xDD40 | SA | MRC_TURN_AROUND
0xDD41 | SA | MRC_CMP_OPT
0xDD42 | SA | MRC_SAVE_MC_VALUES
0xDD43 | SA | MRC_RESTORE_TRAINING
0xDD44 | SA | MRC_RMT_TOOL
0xDD45 | SA | MRC_WRITE_SR
0xDD46 | SA | MRC_DIMM_RON
0xDD47 | SA | MRC_RCVEN_TIMING_1D
0xDD48 | SA | MRC_MR_FILL
0xDD49 | SA | MRC_PWR_MTR
0xDD4A | SA | MRC_DDR4_MAPPING
0xDD4B | SA | MRC_WRITE_VOLTAGE_1D
0xDD4C | SA | MRC_EARLY_RDMPR_TIMING_2D
0xDD4D | SA | MRC_FORCE_OLTM
0xDD50 | SA | MRC_MC_ACTIVATE
0xDD51 | SA | MRC_RH_PREVENTION
0xDD52 | SA | MRC_GET_MRC_DATA
0xDD53 | SA | Reserved
0xDD58 | SA | MRC_RETRAIN_CHECK
0xDD5A | SA | MRC_SA_GV_SWITCH
0xDD5B | SA | MRC_ALIAS_CHECK
0xDD5C | SA | MRC_ECC_CLEAN_START
0xDD5D | SA | MRC_DONE
0xDD5F | SA | MRC_CPGC_MEMORY_TEST
0xDD60 | SA | MRC_TXT_ALIAS_CHECK
0xDD61 | SA | MRC_ENG_PERF_GAIN
0xDD68 | SA | MRC_MEMORY_TEST
0xDD69 | SA | MRC_FILL_RMT_STRUCTURE
0xDD70 | SA | MRC_SELF_REFRESH_EXIT
0xDD71 | SA | MRC_NORMAL_MODE
0xDD7D | SA | MRC_SSA_PRE_STOP_POINT
0xDD7F | SA | MRC_SSA_STOP_POINT, MRC_INITIALIZATION_END
0xDD90 | SA | MRC_CMD_PLOT_2D_ERROR
0xDD9B | SA | MRC_FAST_BOOT_PERMITTED_ERROR
0xDD9C | SA | MRC_RESTORE_NON_TRAINING_ERROR
0xDD9D | SA | MRC_PRINT_INPUT_PARAMS_ERROR
0xDD9E | SA | MRC_SET_OVERRIDES_PSPD_ERROR
0xDDA0 | SA | MRC_SPD_PROCESSING_ERROR
0xDDA1 | SA | MRC_SET_OVERRIDES_ERROR
0xDDA2 | SA | MRC_MC_CAPABILITY_ERROR
0xDDA3 | SA | MRC_MC_CONFIG_ERROR
0xDDA4 | SA | MRC_MC_MEMORY_MAP_ERROR
0xDDA5 | SA | MRC_JEDEC_INIT_LPDDR3_ERROR
0xDDA6 | SA | MRC_RESET_ERROR
0xDDA7 | SA | MRC_PRE_TRAINING_ERROR
0xDDA8 | SA | MRC_EARLY_COMMAND_ERROR
0xDDA9 | SA | MRC_SENSE_AMP_OFFSET_ERROR
0xDDAA | SA | MRC_READ_MPR_ERROR
0xDDAB | SA | MRC_RECEIVE_ENABLE_ERROR
0xDDAC | SA | MRC_JEDEC_WRITE_LEVELING_ERROR
0xDDAD | SA | MRC_LPDDR_LATENCY_SET_B_ERROR
0xDDAE | SA | MRC_WRITE_TIMING_1D_ERROR
0xDDAF | SA | MRC_READ_TIMING_1D_ERROR
0xDDB0 | SA | MRC_DIMM_ODT_ERROR
0xDDB1 | SA | MRC_EARLY_WRITE_TIMING_ERROR
0xDDB2 | SA | MRC_WRITE_DS_ERROR
0xDDB3 | SA | MRC_WRITE_EQ_ERROR
0xDDB4 | SA | MRC_EARLY_READ_TIMING_ERROR
0xDDB5 | SA | MRC_READ_ODT_ERROR
0xDDB6 | SA | MRC_READ_EQ_ERROR
0xDDB7 | SA | MRC_READ_AMP_POWER_ERROR
0xDDB8 | SA | MRC_WRITE_TIMING_2D_ERROR
0xDDB9 | SA | MRC_READ_TIMING_2D_ERROR
0xDDBA | SA | MRC_CMD_VREF_ERROR
0xDDBB | SA | MRC_WRITE_VREF_2D_ERROR
0xDDBC | SA | MRC_READ_VREF_2D_ERROR
0xDDBD | SA | MRC_POST_TRAINING_ERROR
0xDDBE | SA | MRC_LATE_COMMAND_ERROR
0xDDBF | SA | MRC_ROUND_TRIP_LAT_ERROR
0xDDC0 | SA | MRC_TURN_AROUND_ERROR
0xDDC1 | SA | MRC_CMP_OPT_ERROR
0xDDC2 | SA | MRC_SAVE_MC_VALUES_ERROR
0xDDC3 | SA | MRC_RESTORE_TRAINING_ERROR
0xDDC4 | SA | MRC_RMT_TOOL_ERROR
0xDDC5 | SA | MRC_WRITE_SR_ERROR
0xDDC6 | SA | MRC_DIMM_RON_ERROR
0xDDC7 | SA | MRC_RCVEN_TIMING_1D_ERROR
0xDDC8 | SA | MRC_MR_FILL_ERROR
0xDDC9 | SA | MRC_PWR_MTR_ERROR
0xDDCA | SA | MRC_DDR4_MAPPING_ERROR
0xDDCB | SA | MRC_WRITE_VOLTAGE_1D_ERROR
0xDDCC | SA | MRC_EARLY_RDMPR_TIMING_2D_ERROR
0xDDCD | SA | MRC_FORCE_OLTM_ERROR
0xDDD0 | SA | MRC_MC_ACTIVATE_ERROR
0xDDD1 | SA | MRC_RH_PREVENTION_ERROR
0xDDD2 | SA | MRC_GET_MRC_DATA_ERROR
0xDDD3 | SA | Reserved
0xDDD8 | SA | MRC_RETRAIN_CHECK_ERROR
0xDDDA | SA | MRC_SA_GV_SWITCH_ERROR
0xDDDB | SA | MRC_ALIAS_CHECK_ERROR
0xDDDC | SA | MRC_ECC_CLEAN_ERROR
0xDDDD | SA | MRC_DONE_WITH_ERROR
0xDDDF | SA | MRC_CPGC_MEMORY_TEST_ERROR
0xDDE0 | SA | MRC_TXT_ALIAS_CHECK_ERROR
0xDDE1 | SA | MRC_ENG_PERF_GAIN_ERROR
0xDDE8 | SA | MRC_MEMORY_TEST_ERROR
0xDDE9 | SA | MRC_FILL_RMT_STRUCTURE_ERROR
0xDDF0 | SA | MRC_SELF_REFRESH_EXIT_ERROR
0xDDF1 | SA | MRC_MRC_NORMAL_MODE_ERROR
0xDDFD | SA | MRC_SSA_PRE_STOP_POINT_ERROR
0xDDFE | SA | MRC_NO_MEMORY_DETECTED

8.1.3 TempRamExit API Status Codes (0xBxxx)

PostCode | Module | Description
0xB800 | FSP | TempRamExit API Entry
0xB87F | FSP | TempRamExit API Exit

8.1.4 FspSiliconInit API Status Codes (0x9xxx)

PostCode | Module | Description
0x9800 | FSP | FspSiliconInit API Entry
0x987F | FSP | FspSiliconInit API Exit
0x9A00 | SA | PostMem SaInit Entry
0x9A01 | SA | DeviceConfigure Start
0x9A02 | SA | UpdateSaHobPostMem Start
0x9A03 | SA | Initializing Pei Display
0x9A04 | SA | PeiGraphicsNotifyCallback Entry
0x9A05 | SA | CallPpiAndFillFrameBuffer
0x9A06 | SA | GraphicsPpiInit
0x9A07 | SA | GraphicsPpiGetMode
0x9A08 | SA | FillFrameBufferAndShowLogo
0x9A0F | SA | PeiGraphicsNotifyCallback Exit
0x9A14 | SA | Initializing SA IPU device
0x9A16 | SA | Initializing SA GNA device
0x9A1A | SA | SaProgramLlcWays Start
0x9A20 | SA | Initializing PciExpressInitPostMem
0x9A22 | SA | Initializing ConfigureNorthIntelTraceHub
0x9A30 | SA | Initializing Vtd
0x9A31 | SA | Initializing TCSS
0x9A32 | SA | Initializing Pavp
0x9A34 | SA | PeiInstallSmmAccessPpi Start
0x9A36 | SA | EdramWa Start
0x9A4F | SA | Post-Mem SaInit Exit
0x9A50 | SA | SaSecurityLock Start
0x9A5F | SA | SaSecurityLock End
0x9A60 | SA | SaSResetComplete Entry
0x9A61 | SA | Set BIOS_RESET_CPL to indicate all configurations complete
0x9A62 | SA | SaSvInit2 Start
0x9A63 | SA | GraphicsPmInit Start
0x9A64 | SA | SaPciPrint Start
0x9A6F | SA | SaSResetComplete Exit
0x9A70 | SA | SaS3ResumeAtEndOfPei Callback Entry
0x9A7F | SA | SaS3ResumeAtEndOfPei Callback Exit
0x9B00 | PCH | Post-Mem PchInit Entry
0x9B03 | PCH | Post-Mem Tune the USB 2.0 high-speed signals quality
0x9B04 | PCH | Post-Mem Tune the USB 3.0 signals quality
0x9B05 | PCH | Post-Mem Configure PCH xHCI
0x9B06 | PCH | Post-Mem Performs configuration of PCH xHCI SSIC
0x9B07 | PCH | Post-Mem Configure PCH xHCI after init
0x9B08 | PCH | Post-Mem Configures PCH USB device (xDCI)
0x9B0A | PCH | Post-Mem DMI/OP-DMI configuration
0x9B0B | PCH | Post-Mem Initialize P2SB controller
0x9B0C | PCH | Post-Mem IOAPIC initialization
0x9B0D | PCH | Post-Mem PCH devices interrupt configuration
0x9B0E | PCH | Post-Mem HD Audio initizalization
0x9B0F | PCH | Post-Mem HD Audio Codec enumeration
0x9B10 | PCH | Post-Mem HD Audio Codec not detected
0x9B13 | PCH | Post-Mem SCS initizalization
0x9B14 | PCH | Post-Mem ISH initizalization
0x9B15 | PCH | Post-Mem Configure SMBUS power management
0x9B16 | PCH | Post-Mem Reserved
0x9B17 | PCH | Post-Mem Performing global reset
0x9B18 | PCH | Post-Mem Reserved
0x9B19 | PCH | Post-Mem Reserved
0x9B40 | PCH | Post-Mem OnEndOfPEI Entry
0x9B41 | PCH | Post-Mem Initialize Thermal controller
0x9B42 | PCH | Post-Mem Configure Memory Throttling
0x9B47 | PCH | Post-Mem OnEndOfPEI Exit
0x9B4D | PCH | Post-Mem Trace Hub - Memory configuration
0x9B4E | PCH | Post-Mem Trace Hub - MSC0 configured
0x9B4F | PCH | Post-Mem Trace Hub - MSC1 configured
0x9B7F | PCH | Post-Mem PchInit Exit
0x9C00 | CPU | CPU Post-Mem Entry
0x9C09 | CPU | CpuAddConfigBlocks Done
0x9C0A | CPU | SetCpuStrapAndEarlyPowerOnConfig Start
0x9C13 | CPU | SetCpuStrapAndEarlyPowerOnConfig Reset
0x9C14 | CPU | SetCpuStrapAndEarlyPowerOnConfig Done
0x9C15 | CPU | CpuInit Start
0x9C17 | CPU | CollectProcessorFeature Start
0x9C18 | CPU | ProgramProcessorFeature Start
0x9C19 | CPU | ProgramProcessorFeature Done
0x9C20 | CPU | CpuInitPreResetCpl Start
0x9C21 | CPU | ProcessorsPrefetcherInitialization Start
0x9C22 | CPU | InitRatl Start
0x9C23 | CPU | ConfigureSvidVrs Start
0x9C24 | CPU | ConfigurePidSettings Start
0x9C25 | CPU | SetBootFrequency Start
0x9C26 | CPU | CpuOcInitPreMem Start
0x9C27 | CPU | CpuOcInit Reset
0x9C28 | CPU | BiosGuardInit Start
0x9C29 | CPU | BiosGuardInit Reset
0x9C3F | CPU | CpuInitPreResetCpl Done
0x9C42 | CPU | ApSafePostMicrocodePatchInit Start
0x9C43 | CPU | InitializeCpuDataHob Start
0x9C44 | CPU | InitializeCpuDataHob Done
0x9C4F | CPU | CpuInit Done
0x9C50 | CPU | S3InitializeCpu Start
0x9C55 | CPU | MpRendezvousProcedure Start
0x9C56 | CPU | MpRendezvousProcedure Done
0x9C69 | CPU | S3InitializeCpu Done
0x9C6A | CPU | CpuPowerMgmtInit Start
0x9C71 | CPU | InitPpm
0x9C7F | CPU | CPU Post-Mem Exit
0x9C80 | CPU | ReloadMicrocodePatch Start
0x9C81 | CPU | ReloadMicrocodePatch Done
0x9C82 | CPU | ApSafePostMicrocodePatchInit Start
0x9C83 | CPU | ApSafePostMicrocodePatchInit Done

8.1.5 NotifyPhase API Status Codes (0x6xxx)

PostCode | Module | Description
0x6800 | FSP | NotifyPhase API Entry
0x687F | FSP | NotifyPhase API Exit
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Deprecated List

Deprecated List
Member CPU_CONFIG::Avx3Disable
Enable or Disable Avx3.
  • 1: Disable
  • 0: Enable
Member CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount
due to core active number limitaion.
Member CPU_CONFIG_LIB_PREMEM_CONFIG::PeciC10Reset
no longer used.
Member CPU_POWER_MGMT_BASIC_CONFIG::EnableItbmDriver
: Platform doesn't have Intel Turbo Boost Max Technology 3.0 Driver Enabling it will load the driver upon ACPI device with HID = INT3510. 0: Disable; 1: Enable;
Member CPU_POWER_MGMT_TEST_CONFIG::C3AutoDemotion
no longer used
Member CPU_POWER_MGMT_TEST_CONFIG::C3UnDemotion
no longer used
Member CPU_POWER_MGMT_TEST_CONFIG::ConfigTdpLevel
Move to premem phase.
Member CPU_SECURITY_PREMEM_CONFIG::EnableSgx
due to Non-POR feature.
Member AMT_PEI_CONFIG::ManageabilityMode
: Manageability Mode sync with Mebx, 0: Disabled; 1: AMT
Member AMT_PEI_CONFIG::RemoteAssistance
: Remote Assistance is enabled if platform is provisioned. 0: Disable, 1: Enable
Member AMT_PEI_CONFIG::AmtKvmEnabled
: KVM retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, 1: Enable
Member AMT_DXE_CONFIG::MebxDebugMsg
: OEMFlag Bit 14: Enable OEM debug menu in MEBx. 0: Disable; 1: Enable
Member AMT_DXE_CONFIG::HideUnConfigureMeConfirm
: OEMFlag Bit 6: Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration. 0: Don't hide; 1: Hide
Member AMT_DXE_CONFIG::AmtbxHotkeyPressed
: OEMFlag Bit 1: Enable automatic MEBx hotkey press. 0: Disable; 1: Enable
Member AMT_DXE_CONFIG::AmtbxSelectionScreen
Member AMT_DXE_CONFIG::CiraTimeout
Member AMT_DXE_CONFIG::CpuReplacementTimeout
Member AMT_DXE_CONFIG::MebxNonUiTextMode
: Resolution for non-UI text mode. 0: Auto; 1: 80x25; 2: 100x31
Member AMT_DXE_CONFIG::MebxUiTextMode
: Resolution for UI text mode. 0: Auto; 1: 80x25; 2: 100x31
Member AMT_DXE_CONFIG::MebxGraphicsMode
: Resolution for graphics mode. 0: Auto; 1: 640x480; 2: 800x600; 3: 1024x768
Member AMT_DXE_CONFIG::OemResolutionSettingsRsvd
: Reserved for future use & Config block alignment
Member CpuPcieEqDefault
since revision 3. Behaves as PchPcieEqHardware.
Member FIVR_EXT_RAIL_CONFIG::IccMax
THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD VR rail Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA The default is 0mA .
Member GRAPHICS_DXE_CONFIG::IgdDvmtMemSize
IGD DVMT Memory Size: 1=128MB, 2=256MB, 3=MAX
Member ME_PEI_CONFIG::Heci3Enabled
Member SI_CONFIG::CsmFlag
.
Member CPU_POWER_MGMT_VR_CONFIG::TdcTimeWindow [MAX_NUM_VRS]
. PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. 1ms default
Member SA_MISC_PEI_PREMEM_CONFIG::IedSize
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Todo List

Todo List
Member CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0TimeUnit
: The following enums have to be replaced with policies.
Page 4.2 Config Blocks

This list is from TigerLake, needs to be updated for AlderLake

This list is from TigerLake, needs to be updated for AlderLake

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class List

Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C _CONFIG_BLOCK | Config Block
C _CONFIG_BLOCK_HEADER | Config Block Header
C _CONFIG_BLOCK_TABLE_STRUCT | Config Block Table Header
C _EFI_MM_RESERVED_MMRAM_REGION | Structure describing a MMRAM region which cannot be used for the MMRAM heap
C _EFI_PEI_MP_SERVICES_PPI | This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support
C _ITBT_GENERIC_CONFIG | ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB
C _ITBT_ROOTPORT_CONFIG | ITBT RootPort Data Structure
C _LIST_ENTRY | _LIST_ENTRY structure definition
C _PEI_ITBT_CONFIG | ITBT PEI configuration Revision 1:
C _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI | This PPI provides function to install default silicon policy
C _PEI_SI_DEFAULT_POLICY_INIT_PPI | This PPI provides function to install default silicon policy
C _PPM_CUSTOM_CTDP_TABLE | PPM Custom ConfigTdp Settings
C _SI_POLICY_STRUCT | SI Policy PPI All SI config block change history will be listed here
C _SI_PREMEM_POLICY_STRUCT | SI Policy PPI in Pre-Mem All SI config block change history will be listed here
C ADR_CONFIG | ADR Configuration Revision 1: - Initial version
C ADR_SOURCE_ENABLE | ADR Source Enable
C AMT_DXE_CONFIG | AMT Dxe Configuration Structure
C AMT_PEI_CONFIG | AMT Pei Configuration Structure
C BCLK_CONFIG | BCLK configuration
C BIOS_GUARD_CONFIG | BIOS Guard Configuration Structure
C CNVI_CONFIG | The CNVI_CONFIG block describes the expected configuration of the CNVi IP
C CNVI_PIN_MUX | CNVi signals pin muxing settings
C CNVI_PREMEM_CONFIG | The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP
C CPU_CONFIG | CPU Configuration Structure
C CPU_CONFIG_LIB_PREMEM_CONFIG | CPU Config Library PreMemory Configuration Structure
C CPU_DMI_EQ_PARAM | Represent lane specific Dmi Gen3 equalization parameters
C CPU_DMI_PREMEM_CONFIG | The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI
C CPU_PCIE_CONFIG | The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version
C CPU_PCIE_EQ_LANE_PARAM | Represent lane specific PCIe Gen3 equalization parameters
C CPU_PCIE_GPIO_INFO | CPU PCIe GPIO Data Structure
C CPU_PCIE_ROOT_PORT_CONFIG | The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port
C CPU_PCIE_RP_PREMEM_CONFIG | CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version
C CPU_PCIE_RTD3_GPIO | CPU PCIE RTD3 GPIO Data Structure
C CPU_POWER_MGMT_BASIC_CONFIG | CPU Power Management Basic Configuration Structure
C CPU_POWER_MGMT_CUSTOM_CONFIG | CPU Power Management Custom Configuration Structure
C CPU_POWER_MGMT_PSYS_CONFIG | CPU Power Management Psys(Platform) Configuration Structure
C CPU_POWER_MGMT_TEST_CONFIG | CPU Power Management Test Configuration Structure
C CPU_POWER_MGMT_VR_CONFIG | CPU Power Management VR Configuration Structure
C CPU_SECURITY_PREMEM_CONFIG | CPU Security PreMemory Configuration Structure
C CPU_TEST_CONFIG | CPU Test Configuration Structure
C CPU_TRACE_HUB_PREMEM_CONFIG | CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version
C CPU_TXT_PREMEM_CONFIG | CPU TXT PreMemory Configuration Structure
C DDI_CONFIGURATION | This structure configures the Native GPIOs for DDI port per VBT settings
C DMI_HW_WIDTH_CONTROL | This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design
C EFI_HOB_CPU | Describes processor information, such as address space and I/O space capabilities
C EFI_HOB_FIRMWARE_VOLUME | Details the location of firmware volumes that contain firmware files
C EFI_HOB_FIRMWARE_VOLUME2 | Details the location of a firmware volume that was extracted from a file within another firmware volume
C EFI_HOB_FIRMWARE_VOLUME3 | Details the location of a firmware volume that was extracted from a file within another firmware volume
C EFI_HOB_GENERIC_HEADER | Describes the format and size of the data inside the HOB
C EFI_HOB_GUID_TYPE | Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID
C EFI_HOB_HANDOFF_INFO_TABLE | Contains general state information used by the HOB producer phase
C EFI_HOB_MEMORY_ALLOCATION | Describes all memory ranges used during the HOB producer phase that exist outside the HOB list
C EFI_HOB_MEMORY_ALLOCATION_BSP_STORE | Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store")
C EFI_HOB_MEMORY_ALLOCATION_HEADER | EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation
C EFI_HOB_MEMORY_ALLOCATION_MODULE | Defines the location and entry point of the HOB consumer phase
C EFI_HOB_MEMORY_ALLOCATION_STACK | Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing
C EFI_HOB_MEMORY_POOL | Describes pool memory allocations
C EFI_HOB_RESOURCE_DESCRIPTOR | Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase
C EFI_HOB_UEFI_CAPSULE | Each UEFI capsule HOB details the location of a UEFI capsule
C EFI_IP_ADDRESS | 16-byte buffer aligned on a 4-byte boundary
C EFI_MAC_ADDRESS | 32-byte buffer containing a network Media Access Control address
C EFI_MMRAM_DESCRIPTOR | Structure describing a MMRAM region and its accessibility attributes
C EFI_PEI_HOB_POINTERS | Union of all the possible HOB Types
C EFI_TIME | EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047
C FIRMWARE_VERSION | Firmware Version Structure
C FIRMWARE_VERSION_INFO | Firmware Version Information Structure
C FIRMWARE_VERSION_INFO_HOB | Firmware Version Information HOB Structure
C FIVR_EXT_RAIL_CONFIG | Structure for V1p05/Vnn VR rail configuration
C FIVR_VCCIN_AUX_CONFIG | Structure for VCCIN_AUX voltage rail configuration
C FSP_ERROR_INFO_HOB | FSP Error Information Block
C FSPM_ARCH_CONFIG_PPI | This PPI provides FSP-M Arch Config PPI
C GBE_CONFIG | PCH intergrated GBE controller configuration settings
C GNA_CONFIG | GNA config block for configuring GNA
C GPIO_CONFIG | GPIO configuration structure used for pin programming
C GRAPHICS_DXE_CONFIG | This configuration block is to configure IGD related variables used in DXE
C GRAPHICS_PEI_CONFIG | This configuration block is to configure IGD related variables used in PostMem PEI
C GRAPHICS_PEI_PREMEM_CONFIG | This Configuration block is to configure GT related PreMem data/variables
C GUID | 128 bit buffer containing a unique identifier value
C HDA_LINK_DMIC | HD Audio DMIC Interface Policies
C HDA_LINK_HDA | HD Audio Link Policies
C HDA_LINK_SNDW | HD Audio SNDW Interface Policies
C HDA_LINK_SSP | HD Audio SSP Interface Policies
C HDA_VERB_TABLE_HEADER | Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands
C HDAUDIO_CONFIG | This structure contains the policies which are related to HD Audio device (cAVS)
C HDAUDIO_DXE_CONFIG | This structure contains the DXE policies which are related to HD Audio device (cAVS)
C HDAUDIO_PREMEM_CONFIG | This structure contains the premem policies which are related to HD Audio device (cAVS)
C HSIO_PARAMETERS | This structure describes USB3 Port N configuration parameters
C HYBRID_GRAPHICS_CONFIG | This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port
C HYBRID_STORAGE_CONFIG | The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device
C I2C_PIN_MUX | I2C signals pin muxing settings
C IEH_CONFIG | The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler
C IOM_AUX_ORI_PAD_CONFIG | The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin
C IOM_INTERFACE_CONFIG | The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC
C IPU_PREMEM_CONFIG | IPU PreMem configuration Revision 1:
C IPv4_ADDRESS | 4-byte buffer
C IPv6_ADDRESS | 16-byte buffer
C ISH_CONFIG | The ISH_CONFIG block describes Integrated Sensor Hub device
C ISH_GP | Struct contains GPIO pins assigned and signal settings of GP
C ISH_GPIO_CONFIG | ISH GPIO settings
C ISH_I2C | Struct contains GPIO pins assigned and signal settings of I2C
C ISH_I2C_PIN_CONFIG | I2C signals settings
C ISH_I3C_CONFIG | The ISH_I3C_CONFIG block describes I3C in ISH device
C ISH_PREMEM_CONFIG | Premem Policy for Integrated Sensor Hub device
C ISH_SPI | Struct contains GPIO pins assigned and signal settings of SPI
C ISH_SPI_PIN_CONFIG | SPI signals settings
C ISH_UART | Struct contains GPIO pins assigned and signal settings of UART
C ISH_UART_PIN_CONFIG | UART signals settings
C ME_PEI_CONFIG | ME Pei Post-Memory Configuration Structure
C ME_PEI_PREMEM_CONFIG | ME Pei Pre-Memory Configuration Structure
C MEMORY_CONFIG_NO_CRC | Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection
C MEMORY_CONFIGURATION | Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection
C OVERCLOCKING_PREMEM_CONFIG | Overclocking Configuration Structure
C PCH_DCI_PREMEM_CONFIG | The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
C PCH_DEVICE_INTERRUPT_CONFIG | The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device
C PCH_DMI_CONFIG | The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI
C PCH_DMI_EQ_PARAM | Lane specific Dmi Gen3, Gen4 equalization parameters
C PCH_ESPI_CONFIG | This structure contains the policies which are related to ESPI
C PCH_FIVR_CONFIG | The PCH_FIVR_CONFIG block describes FIVR settings
C PCH_GENERAL_CONFIG | PCH General Configuration Revision 1: - Initial version
C PCH_GENERAL_PREMEM_CONFIG | PCH General Pre-Memory Configuration Revision 1: - Initial version
C PCH_INTERRUPT_CONFIG | The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH
C PCH_IOAPIC_CONFIG | The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE
C PCH_LOCK_DOWN_CONFIG | The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement
C PCH_MEMORY_THROTTLING | This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board)
C PCH_P2SB_CONFIG | This structure contains the policies which are related to P2SB device
C PCH_PCIE_CLOCK | PCH_PCIE_CLOCK describes PCIe source clock generated by PCH
C PCH_PCIE_CONFIG | The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1:
C PCH_PCIE_ROOT_PORT_CONFIG | The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port
C PCH_PCIE_RP_PREMEM_CONFIG | The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1:
C PCH_PM_CONFIG | The PCH_PM_CONFIG block describes expected miscellaneous power management settings
C PCH_SATA_PORT_CONFIG | This structure configures the features, property, and capability for each SATA port
C PCH_SMBUS_PREMEM_CONFIG | The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform
C PCH_TRACE_HUB_PREMEM_CONFIG | PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version
C PCH_WAKE_CONFIG | This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events
C PCH_WDT_PREMEM_CONFIG | This policy clears status bits and disable watchdog, then lock the WDT registers
C PCIE_COMMON_CONFIG | PCIe Common Config
C PCIE_DEVICE_OVERRIDE | PCIe device table entry entry
C PCIE_EQ_PARAM | Represent lane specific PCIe Gen3 equalization parameters
C PCIE_IMR_CONFIG | PCIe IMR Config
C PCIE_LINK_EQ_PLATFORM_SETTINGS | PCIe Link EQ Platform Settings
C PCIE_PEI_PREMEM_CONFIG | PCI Express and DMI controller configuration
C PCIE_PREMEM_CONFIG | PCIe Pre-Memory Configuration Revision 1: - Initial version
C PCIE_RP_DXE_CONFIG | The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
C PMC_GLOBAL_RESET_MASK | Description of Global Reset Trigger/Event Mask register
C PMC_INTERFACE_CONFIG | The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
C PMC_LPM_S0IX_SUB_STATE_EN | Low Power Mode Enable config
C PPM_CUSTOM_RATIO_TABLE | This structure is used to describe the custom processor ratio table desired by the platform
C PSF_CONFIG | The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric
C RST_CONFIG | Rapid Storage Technology settings
C RST_HARDWARE_REMAPPED_STORAGE_CONFIG | This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required
C RTC_CONFIG | The RTC_CONFIG block describes the expected configuration of RTC configuration
C SA_ADDRESS_DECODE | SA memory address decode
C SA_FUNCTION_CALLS | Function calls into the SA
C SA_MEMORY_DQDQS_MAPPING | DqDqs Mapping
C SA_MEMORY_FUNCTIONS | Function calls into the MRC
C SA_MEMORY_RCOMP | Rcomp Policies
C SA_MISC_PEI_CONFIG | This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem
C SA_MISC_PEI_PREMEM_CONFIG | This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc
C SA_XDCI_IRQ_INT_CONFIG | The SA XDCI INT Pin and IRQ number
C SATA_CONFIG | The SATA_CONFIG block describes the expected configuration of the SATA controllers
C SATA_THERMAL_THROTTLING | This structure lists PCH supported SATA thermal throttling register setting for customization
C SERIAL_IO_CONFIG | The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
C SERIAL_IO_I2C_CONFIG | Serial IO I2C Controller Configuration
C SERIAL_IO_SPI_CONFIG | The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
C SERIAL_IO_UART_ATTRIBUTES | UART Settings
C SERIAL_IO_UART_CONFIG | Serial IO UART Controller Configuration
C SI_CONFIG | The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware
C SI_PREMEM_CONFIG | The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware
C SMBIOS_STRUCTURE | The Smbios structure header
C SPD_DATA_BUFFER | SPD Data Buffer
C SPD_OFFSET_TABLE | SPD Offset Table
C SPI_PIN_MUX | SPI signals pin muxing settings
C SVID_SID_VALUE | Subsystem Vendor ID / Subsystem ID
C TCSS_DEVEN_PEI_PREMEM_CONFIG | The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS
C TCSS_IOM_ORI_OVERRIDE | The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS
C TCSS_IOM_PEI_CONFIG | The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS
C TCSS_MISC_PEI_CONFIG | The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS
C TCSS_MISC_PEI_PREMEM_CONFIG | The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS
C TCSS_PCIE_PEI_POLICY | TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS
C TCSS_PCIE_PORT_POLICY | The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS
C TCSS_PEI_CONFIG | The TCSS_PEI_CONFIG block describes TCSS settings for SA
C TCSS_PEI_PREMEM_CONFIG | This configuration block describes TCSS settings
C TCSS_USBTC_PEI_PERMEM_CONFIG | The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS
C TELEMETRY_PEI_CONFIG | This configuration block describes Telemetry settings in PostMem
C TELEMETRY_PEI_PREMEM_CONFIG | This configuration block describes Telemetry settings in PreMem
C THC_CONFIG | THC_CONFIG block provides the configurations forTouch Host Controllers
C THC_HID_OVER_SPI | THC Hid Over SPI mode related settings
C THC_PORT | Port Configuration structure required for each Port that THC might use
C THERMAL_CONFIG | The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block
C THERMAL_THROTTLE_LEVELS | This structure lists PCH supported throttling register setting for custimization
C TRACE_HUB_CONFIG | TRACE_HUB_CONFIG block describes TraceHub settings
C TS_GPIO_PIN_SETTING | This structure configures PCH memory throttling thermal sensor GPIO PIN settings
C TSN_CONFIG | The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)
C UART_PIN_MUX | UART signals pin muxing settings
C USB2_PHY_CONFIG | This structure holds info on how to tune electrical parameters of USB2 ports based on board layout
C USB2_PHY_PARAMETERS | This structure configures per USB2 AFE settings
C USB2_PORT_CONFIG | This structure configures per USB2.0 port settings like enabling and overcurrent protection
C USB3_HSIO_CONFIG | Structure for holding USB3 tuning parameters
C USB3_PORT_CONFIG | This structure configures per USB3.x port settings like enabling and overcurrent protection
C USB_CONFIG | This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field
C VMD_PEI_CONFIG | This configuration block is to configure VMD related variables used in PostMem PEI
C VTD_CONFIG | The data elements should be initialized by a Platform Module
C VTD_DXE_CONFIG | The data structure is for VT-d driver initialization in DXE Revision 1:
C XDCI_CONFIG | The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _CONFIG_BLOCK Struct Reference

Public Attributes | List of all members
_CONFIG_BLOCK Struct Reference

Config Block. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Header of config block.

Detailed Description

Config Block.

Definition at line 40 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

_CONFIG_BLOCK Member List

This is the complete list of members for _CONFIG_BLOCK, including all inherited members.

Header _CONFIG_BLOCK
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _CONFIG_BLOCK_HEADER Struct Reference

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_CONFIG_BLOCK_HEADER Struct Reference

Config Block Header. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK_HEADER:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
UINT8 | Revision
Offset 24 Revision of this config block.
UINT8 | Attributes
Offset 25 The main revision for config block.
UINT8 | Reserved [2]
Offset 26-27 Reserved for future use.

Detailed Description

Config Block Header.

Definition at line 30 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
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_CONFIG_BLOCK_HEADER Member List

This is the complete list of members for _CONFIG_BLOCK_HEADER, including all inherited members.

Attributes | _CONFIG_BLOCK_HEADER
GuidHob | _CONFIG_BLOCK_HEADER
Reserved | _CONFIG_BLOCK_HEADER
Revision | _CONFIG_BLOCK_HEADER
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _CONFIG_BLOCK_TABLE_STRUCT Struct Reference

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_CONFIG_BLOCK_TABLE_STRUCT Struct Reference

Config Block Table Header. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK_TABLE_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
UINT8 | Rsvd0 [2]
Offset 28-29 Reserved for future use.
UINT16 | NumberOfBlocks
Offset 30-31 Number of config blocks (N)
UINT32 | AvailableSize
Offset 32-35 Current config block table size.

Detailed Description

Config Block Table Header.

Definition at line 50 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
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_CONFIG_BLOCK_TABLE_STRUCT Member List

This is the complete list of members for _CONFIG_BLOCK_TABLE_STRUCT, including all inherited members.

AvailableSize | _CONFIG_BLOCK_TABLE_STRUCT
Header | _CONFIG_BLOCK_TABLE_STRUCT
NumberOfBlocks | _CONFIG_BLOCK_TABLE_STRUCT
Rsvd0 | _CONFIG_BLOCK_TABLE_STRUCT
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _EFI_MM_RESERVED_MMRAM_REGION Struct Reference

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_EFI_MM_RESERVED_MMRAM_REGION Struct Reference

Structure describing a MMRAM region which cannot be used for the MMRAM heap. More...

#include <PiMultiPhase.h>

Public Attributes

EFI_PHYSICAL_ADDRESS MmramReservedStart
Starting address of the reserved MMRAM area, as it appears while MMRAM is open. More...
UINT64 MmramReservedSize
Number of bytes occupied by the reserved MMRAM area. More...

Detailed Description

Structure describing a MMRAM region which cannot be used for the MMRAM heap.

Definition at line 139 of file PiMultiPhase.h.

Member Data Documentation

◆ MmramReservedSize

UINT64 _EFI_MM_RESERVED_MMRAM_REGION::MmramReservedSize

Number of bytes occupied by the reserved MMRAM area.

A size of zero indicates the last MMRAM area.

Definition at line 149 of file PiMultiPhase.h.

◆ MmramReservedStart

EFI_PHYSICAL_ADDRESS _EFI_MM_RESERVED_MMRAM_REGION::MmramReservedStart

Starting address of the reserved MMRAM area, as it appears while MMRAM is open.

Ignored if MmramReservedSize is 0.

Definition at line 144 of file PiMultiPhase.h.

The documentation for this struct was generated from the following file:
  • PiMultiPhase.h
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_EFI_MM_RESERVED_MMRAM_REGION Member List

This is the complete list of members for _EFI_MM_RESERVED_MMRAM_REGION, including all inherited members.

MmramReservedSize | _EFI_MM_RESERVED_MMRAM_REGION
MmramReservedStart | _EFI_MM_RESERVED_MMRAM_REGION
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _EFI_PEI_MP_SERVICES_PPI Struct Reference

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_EFI_PEI_MP_SERVICES_PPI Struct Reference

This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support. More...

#include <MpServices.h>

Collaboration diagram for _EFI_PEI_MP_SERVICES_PPI:
[legend]

Detailed Description

This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support.

Definition at line 265 of file MpServices.h.

The documentation for this struct was generated from the following file:
  • MpServices.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

_EFI_PEI_MP_SERVICES_PPI Member List

This is the complete list of members for _EFI_PEI_MP_SERVICES_PPI, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _ITBT_GENERIC_CONFIG Struct Reference

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_ITBT_GENERIC_CONFIG Struct Reference

ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB. More...

#include <PeiITbtGenericStructure.h>

Public Attributes

UINT16 | ITbtForcePowerOnTimeoutInMs
Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication. More...
UINT16 | ITbtConnectTopologyTimeoutInMs
Timeout value while sending connect topology mailbox command in order to bring all connected TBT devices are available on PCIe before BIOS will enumerate them in BDS (Test) default is 5000 ms
UINT8 | ITbtSecurityLevel
iTbt Security Level Deprecated
UINT8 | ITbtPcieTunnelingForUsb4
Disable/Enable PCIe tunneling for USB4. default is enable
UINT8 | Usb4CmMode
USB4 CM mode.
UINT8 | Reserved [1]
Reserved for DWORD alignment.

Detailed Description

ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB.

Definition at line 52 of file PeiITbtGenericStructure.h.

Member Data Documentation

◆ ITbtForcePowerOnTimeoutInMs

UINT16 _ITBT_GENERIC_CONFIG::ITbtForcePowerOnTimeoutInMs

Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication.

After applying Force Power Thunderbolt BIOS shall poll for iTBT readiness for mailbox communication If TBT cable is disconnected, iTBT microcontrollers are in lower power state. To ensure successful mailbox execution, independently on presence of TBT cable, TBT BIOS shall bring iTBT microcontrollers up by applying Force Power. iTBT microcontrollers will wake up either due to TBT cable presence or Force Power event. (Test) default is 500 ms

Definition at line 64 of file PeiITbtGenericStructure.h.

The documentation for this struct was generated from the following file:
  • PeiITbtGenericStructure.h
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_ITBT_GENERIC_CONFIG Member List

This is the complete list of members for _ITBT_GENERIC_CONFIG, including all inherited members.

ITbtConnectTopologyTimeoutInMs | _ITBT_GENERIC_CONFIG
ITbtForcePowerOnTimeoutInMs | _ITBT_GENERIC_CONFIG
ITbtPcieTunnelingForUsb4 | _ITBT_GENERIC_CONFIG
ITbtSecurityLevel | _ITBT_GENERIC_CONFIG
Reserved | _ITBT_GENERIC_CONFIG
Usb4CmMode | _ITBT_GENERIC_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _ITBT_ROOTPORT_CONFIG Struct Reference

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_ITBT_ROOTPORT_CONFIG Struct Reference

iTBT RootPort Data Structure More...

#include <PeiITbtGenericStructure.h>

Public Attributes

UINT8 | ITbtPcieRootPortEn
Disable/Enable iTBT PCIe Root Port.
UINT8 | Reserved [3]
Reserved for DWORD alignment.

Detailed Description

iTBT RootPort Data Structure

Definition at line 44 of file PeiITbtGenericStructure.h.

The documentation for this struct was generated from the following file:
  • PeiITbtGenericStructure.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


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_ITBT_ROOTPORT_CONFIG Member List

This is the complete list of members for _ITBT_ROOTPORT_CONFIG, including all inherited members.

ITbtPcieRootPortEn | _ITBT_ROOTPORT_CONFIG
Reserved | _ITBT_ROOTPORT_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _LIST_ENTRY Struct Reference

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_LIST_ENTRY Struct Reference

_LIST_ENTRY structure definition. More...

#include <Base.h>

Collaboration diagram for _LIST_ENTRY:
[legend]

Detailed Description

_LIST_ENTRY structure definition.

Definition at line 256 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h
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_LIST_ENTRY Member List

This is the complete list of members for _LIST_ENTRY, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _PEI_ITBT_CONFIG Struct Reference

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_PEI_ITBT_CONFIG Struct Reference

ITBT PEI configuration
Revision 1: More...

#include <PeiITbtConfig.h>

Collaboration diagram for _PEI_ITBT_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
ITBT_GENERIC_CONFIG ITbtGenericConfig
ITbt Common Configuration.
ITBT_ROOTPORT_CONFIG | ITbtRootPortConfig [MAX_ITBT_PCIE_PORT]
iTbt Root Port Configuration
UINT16 | ITbtDmaLtr [MAX_HOST_ITBT_DMA_NUMBER]
iTbt Host controller DMA LTR value

Detailed Description

ITBT PEI configuration
Revision 1:

  • Initial version. Revision 2:
  • Add ITbtPcieTunnelingForUsb4, deprecated ITbtSecurityLevel.

Definition at line 53 of file PeiITbtConfig.h.

The documentation for this struct was generated from the following file:
  • PeiITbtConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

_PEI_ITBT_CONFIG Member List

This is the complete list of members for _PEI_ITBT_CONFIG, including all inherited members.

Header | _PEI_ITBT_CONFIG
ITbtDmaLtr | _PEI_ITBT_CONFIG
ITbtGenericConfig | _PEI_ITBT_CONFIG
ITbtRootPortConfig | _PEI_ITBT_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

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_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

This PPI provides function to install default silicon policy. More...

#include <PeiPreMemSiDefaultPolicy.h>

Public Attributes

PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit
PeiPreMemPolicyInit()

Detailed Description

This PPI provides function to install default silicon policy.

Definition at line 55 of file PeiPreMemSiDefaultPolicy.h.

The documentation for this struct was generated from the following file:
  • PeiPreMemSiDefaultPolicy.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Member List

This is the complete list of members for _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI, including all inherited members.

PeiPreMemPolicyInit _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _PEI_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

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_PEI_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

This PPI provides function to install default silicon policy. More...

#include <PeiSiDefaultPolicy.h>

Public Attributes

PEI_POLICY_INIT PeiPolicyInit
PeiPolicyInit()

Detailed Description

This PPI provides function to install default silicon policy.

Definition at line 55 of file PeiSiDefaultPolicy.h.

The documentation for this struct was generated from the following file:
  • PeiSiDefaultPolicy.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

_PEI_SI_DEFAULT_POLICY_INIT_PPI Member List

This is the complete list of members for _PEI_SI_DEFAULT_POLICY_INIT_PPI, including all inherited members.

PeiPolicyInit _PEI_SI_DEFAULT_POLICY_INIT_PPI
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _PPM_CUSTOM_CTDP_TABLE Struct Reference

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_PPM_CUSTOM_CTDP_TABLE Struct Reference

PPM Custom ConfigTdp Settings. More...

#include <CpuPowerMgmtCustomConfig.h>

Public Attributes

UINT32 | CustomPowerLimit1Time: 8
Short term Power Limit time window value for custom cTDP level.
UINT32 | CustomTurboActivationRatio: 8
Turbo Activation Ratio for custom cTDP level.
UINT32 | RsvdBits: 16
Bits reserved for DWORD alignment.
UINT16 | CustomPowerLimit1
Short term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
UINT16 | CustomPowerLimit2
Long term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Detailed Description

PPM Custom ConfigTdp Settings.

Definition at line 79 of file CpuPowerMgmtCustomConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtCustomConfig.h
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_PPM_CUSTOM_CTDP_TABLE Member List

This is the complete list of members for _PPM_CUSTOM_CTDP_TABLE, including all inherited members.

CustomPowerLimit1 | _PPM_CUSTOM_CTDP_TABLE
CustomPowerLimit1Time | _PPM_CUSTOM_CTDP_TABLE
CustomPowerLimit2 | _PPM_CUSTOM_CTDP_TABLE
CustomTurboActivationRatio | _PPM_CUSTOM_CTDP_TABLE
RsvdBits | _PPM_CUSTOM_CTDP_TABLE
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _SI_POLICY_STRUCT Struct Reference

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_SI_POLICY_STRUCT Struct Reference

SI Policy PPI
All SI config block change history will be listed here

. More...

#include <SiPolicyStruct.h>

Collaboration diagram for _SI_POLICY_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.

Detailed Description

SI Policy PPI
All SI config block change history will be listed here

.

  • Revision 1:
    • Initial version.

Definition at line 85 of file SiPolicyStruct.h.

The documentation for this struct was generated from the following file:
  • SiPolicyStruct.h
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_SI_POLICY_STRUCT Member List

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TableHeader _SI_POLICY_STRUCT
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: _SI_PREMEM_POLICY_STRUCT Struct Reference

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_SI_PREMEM_POLICY_STRUCT Struct Reference

SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

. More...

#include <SiPolicyStruct.h>

Collaboration diagram for _SI_PREMEM_POLICY_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.

Detailed Description

SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

.

  • Revision 1:
    • Initial version.

Definition at line 71 of file SiPolicyStruct.h.

The documentation for this struct was generated from the following file:
  • SiPolicyStruct.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


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_SI_PREMEM_POLICY_STRUCT Member List

This is the complete list of members for _SI_PREMEM_POLICY_STRUCT, including all inherited members.

TableHeader _SI_PREMEM_POLICY_STRUCT
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ADR_CONFIG Struct Reference

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ADR_CONFIG Struct Reference

ADR Configuration Revision 1: - Initial version. More...

#include <AdrConfig.h>

Collaboration diagram for ADR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AdrEn: 2
Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrTimerEn: 2
Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrTimer1Val: 8
Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer.
UINT32 | AdrMultiplier1Val: 3
Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values.
UINT32 | AdrTimer2Val: 8
Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer.
UINT32 | AdrMultiplier2Val: 3
Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values.
UINT32 | AdrHostPartitionReset: 2
Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrSrcOverride: 1
Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten.
UINT32 | AdrPlatAckEn: 2
Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
ADR_SOURCE_ENABLE AdrSrcSel
Determine which ADR sources are enabled - 0: Enabled, 1: Disabled.

Detailed Description

ADR Configuration Revision 1: - Initial version.

Definition at line 97 of file AdrConfig.h.

The documentation for this struct was generated from the following file:
  • AdrConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ADR_CONFIG Member List

This is the complete list of members for ADR_CONFIG, including all inherited members.

AdrEn | ADR_CONFIG
AdrHostPartitionReset | ADR_CONFIG
AdrMultiplier1Val | ADR_CONFIG
AdrMultiplier2Val | ADR_CONFIG
AdrPlatAckEn | ADR_CONFIG
AdrSrcOverride | ADR_CONFIG
AdrSrcSel | ADR_CONFIG
AdrTimer1Val | ADR_CONFIG
AdrTimer2Val | ADR_CONFIG
AdrTimerEn | ADR_CONFIG
Header | ADR_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ADR_SOURCE_ENABLE Union Reference

List of all members
ADR_SOURCE_ENABLE Union Reference

ADR Source Enable. More...

#include <AdrConfig.h>

Detailed Description

ADR Source Enable.

Definition at line 59 of file AdrConfig.h.

The documentation for this union was generated from the following file:
  • AdrConfig.h
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ADR_SOURCE_ENABLE Member List

This is the complete list of members for ADR_SOURCE_ENABLE, including all inherited members.

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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AMT_DXE_CONFIG Struct Reference

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AMT_DXE_CONFIG Struct Reference

AMT Dxe Configuration Structure. More...

#include <AmtConfig.h>

Collaboration diagram for AMT_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | CiraRequest: 1
Trigger CIRA boot. 0: No CIRA request; 1: Trigger CIRA request.
UINT32 | UnConfigureMe: 1
OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. 0: No; 1: Un-configure ME without password.
UINT32 | MebxDebugMsg: 1
UINT32 | HideUnConfigureMeConfirm: 1
UINT32 | UsbProvision: 1
Enable/Disable of AMT USB Provisioning. 0: Disable; 1: Enable.
UINT32 | AmtbxHotkeyPressed: 1
UINT32 | AmtbxSelectionScreen: 1
OEMFlag Bit 2: Enable MEBx selection screen with 2 options: Press 1 to enter ME Configuration Screens Press 2 to initiate a remote connection. More...
UINT32 | RsvdBits: 25
Reserved for future use & Config block alignment.
UINT32 | CiraTimeout: 8
UINT32 | CpuReplacementTimeout: 8
CPU Replacement Timeout 0: 10 seconds 1: 30 seconds 2~5: Reserved 6: No delay 7: Unlimited delay. More...
UINT32 | MebxNonUiTextMode: 4
UINT32 | MebxUiTextMode: 4
UINT32 | MebxGraphicsMode: 4
UINT32 | OemResolutionSettingsRsvd: 4
AMT_REPORT_ERROR AmtReportError
Function pointer for displaying error message on screen.

Detailed Description

AMT Dxe Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 134 of file AmtConfig.h.

Member Data Documentation

◆ AmtbxHotkeyPressed

UINT32 AMT_DXE_CONFIG::AmtbxHotkeyPressed
Deprecated:
: OEMFlag Bit 1: Enable automatic MEBx hotkey press. 0: Disable; 1: Enable

Definition at line 141 of file AmtConfig.h.

◆ AmtbxSelectionScreen

UINT32 AMT_DXE_CONFIG::AmtbxSelectionScreen

OEMFlag Bit 2: Enable MEBx selection screen with 2 options: Press 1 to enter ME Configuration Screens Press 2 to initiate a remote connection.

  • 0: Disabled
  • 1: Enabled
    Deprecated:

Definition at line 149 of file AmtConfig.h.

◆ CiraTimeout

UINT32 AMT_DXE_CONFIG::CiraTimeout
Deprecated:

Definition at line 151 of file AmtConfig.h.

◆ CpuReplacementTimeout

UINT32 AMT_DXE_CONFIG::CpuReplacementTimeout

CPU Replacement Timeout 0: 10 seconds 1: 30 seconds 2~5: Reserved 6: No delay 7: Unlimited delay.

Deprecated:

Definition at line 160 of file AmtConfig.h.

◆ HideUnConfigureMeConfirm

UINT32 AMT_DXE_CONFIG::HideUnConfigureMeConfirm
Deprecated:
: OEMFlag Bit 6: Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration. 0: Don't hide; 1: Hide

Definition at line 139 of file AmtConfig.h.

◆ MebxDebugMsg

UINT32 AMT_DXE_CONFIG::MebxDebugMsg
Deprecated:
: OEMFlag Bit 14: Enable OEM debug menu in MEBx. 0: Disable; 1: Enable

Definition at line 138 of file AmtConfig.h.

◆ MebxGraphicsMode

UINT32 AMT_DXE_CONFIG::MebxGraphicsMode
Deprecated:
: Resolution for graphics mode. 0: Auto; 1: 640x480; 2: 800x600; 3: 1024x768

Definition at line 163 of file AmtConfig.h.

◆ MebxNonUiTextMode

UINT32 AMT_DXE_CONFIG::MebxNonUiTextMode
Deprecated:
: Resolution for non-UI text mode. 0: Auto; 1: 80x25; 2: 100x31

Definition at line 161 of file AmtConfig.h.

◆ MebxUiTextMode

UINT32 AMT_DXE_CONFIG::MebxUiTextMode
Deprecated:
: Resolution for UI text mode. 0: Auto; 1: 80x25; 2: 100x31

Definition at line 162 of file AmtConfig.h.

◆ OemResolutionSettingsRsvd

UINT32 AMT_DXE_CONFIG::OemResolutionSettingsRsvd
Deprecated:
: Reserved for future use & Config block alignment

Definition at line 164 of file AmtConfig.h.

The documentation for this struct was generated from the following file:
  • AmtConfig.h
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AMT_DXE_CONFIG Member List

This is the complete list of members for AMT_DXE_CONFIG, including all inherited members.

AmtbxHotkeyPressed | AMT_DXE_CONFIG
AmtbxSelectionScreen | AMT_DXE_CONFIG
AmtReportError | AMT_DXE_CONFIG
CiraRequest | AMT_DXE_CONFIG
CiraTimeout | AMT_DXE_CONFIG
CpuReplacementTimeout | AMT_DXE_CONFIG
Header | AMT_DXE_CONFIG
HideUnConfigureMeConfirm | AMT_DXE_CONFIG
MebxDebugMsg | AMT_DXE_CONFIG
MebxGraphicsMode | AMT_DXE_CONFIG
MebxNonUiTextMode | AMT_DXE_CONFIG
MebxUiTextMode | AMT_DXE_CONFIG
OemResolutionSettingsRsvd | AMT_DXE_CONFIG
RsvdBits | AMT_DXE_CONFIG
UnConfigureMe | AMT_DXE_CONFIG
UsbProvision | AMT_DXE_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AMT_PEI_CONFIG Struct Reference

Public Attributes | List of all members
AMT_PEI_CONFIG Struct Reference

AMT Pei Configuration Structure. More...

#include <AmtConfig.h>

Collaboration diagram for AMT_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AmtEnabled: 1
Enable or Disable Intel Active Management Technology feature. More...
UINT32 | WatchDogEnabled: 1
ME WatchDog timer feature. More...
UINT32 | FwProgress: 1
PET Events Progress to receive PET Events. 0: Disable; 1: Enable
UINT32 | ManageabilityMode: 1
UINT32 | AmtSolEnabled: 1
Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, 1: Enable
UINT32 | RemoteAssistance: 1
UINT32 | AmtKvmEnabled: 1
UINT32 | ForcMebxSyncUp: 1
0: No; 1: Force MEBX execution
UINT32 | RsvdBits: 24
Reserved for future use & Config block alignment.
UINT16 | WatchDogTimerOs
OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1. More...
UINT16 | WatchDogTimerBios
BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1. More...

Detailed Description

AMT Pei Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 89 of file AmtConfig.h.

Member Data Documentation

◆ AmtEnabled

UINT32 AMT_PEI_CONFIG::AmtEnabled

Enable or Disable Intel Active Management Technology feature.

If disabled, all Intel AMT features, including Alert Standard Format features, will not be supported. 0: Disable 1: Enable.

Definition at line 97 of file AmtConfig.h.

◆ AmtKvmEnabled

UINT32 AMT_PEI_CONFIG::AmtKvmEnabled
Deprecated:
: KVM retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, 1: Enable

Definition at line 109 of file AmtConfig.h.

◆ ManageabilityMode

UINT32 AMT_PEI_CONFIG::ManageabilityMode
Deprecated:
: Manageability Mode sync with Mebx, 0: Disabled; 1: AMT

Definition at line 106 of file AmtConfig.h.

◆ RemoteAssistance

UINT32 AMT_PEI_CONFIG::RemoteAssistance
Deprecated:
: Remote Assistance is enabled if platform is provisioned. 0: Disable, 1: Enable

Definition at line 108 of file AmtConfig.h.

◆ WatchDogEnabled

UINT32 AMT_PEI_CONFIG::WatchDogEnabled

ME WatchDog timer feature.

If disabled, below WatchDogTimerOs/WatchDogTimerBios will be irrelevant. See WatchDogTimerOs and WatchDogTimerBios description. 0: Disable 1: Enable ME WDT if corresponding timer value is not zero.

Definition at line 104 of file AmtConfig.h.

◆ WatchDogTimerBios

UINT16 AMT_PEI_CONFIG::WatchDogTimerBios

BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1.

Non zero value - The BIOS WDT is set according to the value and started if WatchDogEnabled is 1.

Definition at line 124 of file AmtConfig.h.

◆ WatchDogTimerOs

UINT16 AMT_PEI_CONFIG::WatchDogTimerOs

OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1.

Non zero value - OS WDT will be started after stopping BIOS WDT if WatchDogEnabled is 1. The timer is set according to the value.

Definition at line 118 of file AmtConfig.h.

The documentation for this struct was generated from the following file:
  • AmtConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

AMT_PEI_CONFIG Member List

This is the complete list of members for AMT_PEI_CONFIG, including all inherited members.

AmtEnabled | AMT_PEI_CONFIG
AmtKvmEnabled | AMT_PEI_CONFIG
AmtSolEnabled | AMT_PEI_CONFIG
ForcMebxSyncUp | AMT_PEI_CONFIG
FwProgress | AMT_PEI_CONFIG
Header | AMT_PEI_CONFIG
ManageabilityMode | AMT_PEI_CONFIG
RemoteAssistance | AMT_PEI_CONFIG
RsvdBits | AMT_PEI_CONFIG
WatchDogEnabled | AMT_PEI_CONFIG
WatchDogTimerBios | AMT_PEI_CONFIG
WatchDogTimerOs | AMT_PEI_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: BCLK_CONFIG Struct Reference

Public Attributes | List of all members
BCLK_CONFIG Struct Reference

BCLK configuration. More...

#include <PmConfig.h>

Collaboration diagram for BCLK_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | SocBclkPllOn
Controls enable status of SOC BCLK. More...
UINT8 | CpuBclkPllOn
Controls enable status of CPU BCLK. More...

Detailed Description

BCLK configuration.

Only available on projects with SOC and CPU BCLK supported.

Definition at line 468 of file PmConfig.h.

Member Data Documentation

◆ CpuBclkPllOn

UINT8 BCLK_CONFIG::CpuBclkPllOn

Controls enable status of CPU BCLK.

0: HW default, 1: Force enable, 2: Force disable

Definition at line 480 of file PmConfig.h.

◆ SocBclkPllOn

UINT8 BCLK_CONFIG::SocBclkPllOn

Controls enable status of SOC BCLK.

0: HW default, 1: Force enable, 2: Force disable

Definition at line 475 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

BCLK_CONFIG Member List

This is the complete list of members for BCLK_CONFIG, including all inherited members.

CpuBclkPllOn | BCLK_CONFIG
Header | BCLK_CONFIG
SocBclkPllOn | BCLK_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: BIOS_GUARD_CONFIG Struct Reference

Public Attributes | List of all members
BIOS_GUARD_CONFIG Struct Reference

BIOS Guard Configuration Structure. More...

#include <BiosGuardConfig.h>

Collaboration diagram for BIOS_GUARD_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
BIOSGUARD_ATTRIBUTES | BiosGuardAttr
BIT1 - EC Present, BIT2 - EC BIOS Guard protection, BIT3 - Descriptor Override policy, BIT4 - Flash wearout protection, BIT5 - FTU enable.
UINT64 | BgpdtHash [4]
Hash of the BGPDT that will be programmed to PLAT_FRMW_PROT_HASH_0/1/2/3 MSR.
EFI_PHYSICAL_ADDRESS BiosGuardModulePtr
Pointer to the BIOS Guard Module.
EFI_PHYSICAL_ADDRESS SendEcCmd
Platform code can provide interface to communicate with EC through this function.
UINT8 | EcCmdProvisionEav
EC Command Provision Eav.
UINT8 | EcCmdLock
EC Command Lock.
UINT8 | Reserved [6]
Reserved for future use and config block alignment.

Detailed Description

BIOS Guard Configuration Structure.

Platform policies for BIOS Guard Configuration for all processor security features configuration. Platform code can pass relevant configuration data through this structure.

Note
Optional. These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> BiosGuard is disabled, or PeiBiosGuardLibNull is used.

Revision 1:

  • Initial version.

Definition at line 55 of file BiosGuardConfig.h.

The documentation for this struct was generated from the following file:
  • BiosGuardConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

BIOS_GUARD_CONFIG Member List

This is the complete list of members for BIOS_GUARD_CONFIG, including all inherited members.

BgpdtHash | BIOS_GUARD_CONFIG
BiosGuardAttr | BIOS_GUARD_CONFIG
BiosGuardModulePtr | BIOS_GUARD_CONFIG
EcCmdLock | BIOS_GUARD_CONFIG
EcCmdProvisionEav | BIOS_GUARD_CONFIG
Header | BIOS_GUARD_CONFIG
Reserved | BIOS_GUARD_CONFIG
SendEcCmd | BIOS_GUARD_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CNVI_CONFIG Struct Reference

Public Attributes | List of all members
CNVI_CONFIG Struct Reference

The CNVI_CONFIG block describes the expected configuration of the CNVi IP. More...

#include <CnviConfig.h>

Collaboration diagram for CNVI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Mode: 1
This option allows for automatic detection of Connectivity Solution. More...
UINT32 | BtCore: 1
The option to turn ON or OFF the BT Core. 0: Disabled, 1: Enabled
UINT32 | BtAudioOffload: 1
The option to enable or disable BT Audio Offload. More...
UINT32 | WifiCore: 1
The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, 1: Enabled
CNVI_PIN_MUX PinMux
CNVi PinMux Configuration RESET#/CLKREQ to CRF, can have two alternative mappings, depending on board routing requirements.

Detailed Description

The CNVI_CONFIG block describes the expected configuration of the CNVi IP.

Revision 1: - Initial version. Revision 2: - Add DdrRfim. Revision 3: - Add WifiCore. Revision 4: - Move DdrRfim to Pre-Mem config.

Definition at line 73 of file CnviConfig.h.

Member Data Documentation

◆ BtAudioOffload

UINT32 CNVI_CONFIG::BtAudioOffload

The option to enable or disable BT Audio Offload.

0: Disabled, 1: Enabled

Note
This feature only support with Intel(R) Wireless-AX 22560

Definition at line 89 of file CnviConfig.h.

◆ Mode

UINT32 CNVI_CONFIG::Mode

This option allows for automatic detection of Connectivity Solution.

Auto Detection assumes that CNVi will be enabled when available; Disable allows for disabling CNVi. CnviModeDisabled = Disabled, CnviModeAuto = Auto Detection

Definition at line 82 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CNVI_CONFIG Member List

This is the complete list of members for CNVI_CONFIG, including all inherited members.

BtAudioOffload | CNVI_CONFIG
BtCore | CNVI_CONFIG
Header | CNVI_CONFIG
Mode | CNVI_CONFIG
PinMux | CNVI_CONFIG
WifiCore | CNVI_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CNVI_PIN_MUX Struct Reference

Public Attributes | List of all members
CNVI_PIN_MUX Struct Reference

CNVi signals pin muxing settings. More...

#include <CnviConfig.h>

Public Attributes

UINT32 | RfReset
RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*.
UINT32 | Clkreq
CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*.

Detailed Description

CNVi signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in GpioPins*.h for supported settings on a given platform

Definition at line 60 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CNVI_PIN_MUX Member List

This is the complete list of members for CNVI_PIN_MUX, including all inherited members.

Clkreq | CNVI_PIN_MUX
RfReset | CNVI_PIN_MUX
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CNVI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CNVI_PREMEM_CONFIG Struct Reference

The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP. More...

#include <CnviConfig.h>

Collaboration diagram for CNVI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 DdrRfim
The option to enable or disable DDR RFI Mitigation. 0: Disabled, 1: Enabled

Detailed Description

The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.

Revision 1: - Initial version.

Definition at line 105 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CNVI_PREMEM_CONFIG Member List

This is the complete list of members for CNVI_PREMEM_CONFIG, including all inherited members.

DdrRfim | CNVI_PREMEM_CONFIG
Header | CNVI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_CONFIG Struct Reference

Public Attributes | List of all members
CPU_CONFIG Struct Reference

CPU Configuration Structure. More...

#include <CpuConfig.h>

Collaboration diagram for CPU_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
EFI_PHYSICAL_ADDRESS MicrocodePatchAddress
Pointer to microcode patch that is suitable for this processor.
UINT32 | AesEnable: 1
Enable or Disable Advanced Encryption Standard (AES) feature. More...
UINT32 | TxtEnable: 1
Enable or Disable Trusted Execution Technology (TXT) feature. More...
UINT32 | SkipMpInit: 1
For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
UINT32 | PpinSupport: 2
Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number. More...
UINT32 | AcSplitLock: 1
Enable or Disable #AC machine check on split lock. More...
UINT32 | AvxDisable: 1
Enable or Disable Avx. More...
UINT32 | Avx3Disable: 1
UINT32 | X2ApicSupport: 1
Enable or Disable X2APIC Support. More...
UINT32 | RsvdBits: 23
Reserved for future use.
UINT16 | SmbiosType4MaxSpeedOverride
Provide the option for platform to override the MaxSpeed field of Smbios Type 4. More...
UINT8 | Reserved0 [2]
Reserved for future use.

Detailed Description

CPU Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Add SmbiosType4MaxSpeedOverride. Revision 3:
  • Add AvxDisable & Avx3Disable. Revision 4:
  • Add X2ApicSupport. Revision 5:
  • Deprecate Avx3Disable

Definition at line 58 of file CpuConfig.h.

Member Data Documentation

◆ AcSplitLock

UINT32 CPU_CONFIG::AcSplitLock

Enable or Disable #AC machine check on split lock.

  • 0: Disable
  • 1: Enable

Definition at line 88 of file CpuConfig.h.

◆ AesEnable

UINT32 CPU_CONFIG::AesEnable

Enable or Disable Advanced Encryption Standard (AES) feature.

For some countries, this should be disabled for legal reasons.

  • 0: Disable
  • 1: Enable

Definition at line 68 of file CpuConfig.h.

◆ Avx3Disable

UINT32 CPU_CONFIG::Avx3Disable
Deprecated:
Enable or Disable Avx3.
  • 1: Disable
  • 0: Enable

Definition at line 101 of file CpuConfig.h.

◆ AvxDisable

UINT32 CPU_CONFIG::AvxDisable

Enable or Disable Avx.

  • 1: Disable
  • 0: Enable

Definition at line 94 of file CpuConfig.h.

◆ PpinSupport

UINT32 CPU_CONFIG::PpinSupport

Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number.

  • 0: Disable
  • 1: Enable
  • 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM is set, it is disabled.

Definition at line 82 of file CpuConfig.h.

◆ SmbiosType4MaxSpeedOverride

UINT16 CPU_CONFIG::SmbiosType4MaxSpeedOverride

Provide the option for platform to override the MaxSpeed field of Smbios Type 4.

Value 4000 means 4000MHz. If this value is not zero, it dominates the field. If this value is zero, CPU RC will update the field according to the max radio. default is 0.

Definition at line 116 of file CpuConfig.h.

◆ TxtEnable

UINT32 CPU_CONFIG::TxtEnable

Enable or Disable Trusted Execution Technology (TXT) feature.

  • 0: Disable
  • 1: Enable

Definition at line 74 of file CpuConfig.h.

◆ X2ApicSupport

UINT32 CPU_CONFIG::X2ApicSupport

Enable or Disable X2APIC Support.

  • 0: Disable
  • 1: Enable

Definition at line 107 of file CpuConfig.h.

The documentation for this struct was generated from the following file:
  • CpuConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_CONFIG Member List

This is the complete list of members for CPU_CONFIG, including all inherited members.

AcSplitLock | CPU_CONFIG
AesEnable | CPU_CONFIG
Avx3Disable | CPU_CONFIG
AvxDisable | CPU_CONFIG
Header | CPU_CONFIG
MicrocodePatchAddress | CPU_CONFIG
PpinSupport | CPU_CONFIG
Reserved0 | CPU_CONFIG
RsvdBits | CPU_CONFIG
SkipMpInit | CPU_CONFIG
SmbiosType4MaxSpeedOverride | CPU_CONFIG
TxtEnable | CPU_CONFIG
X2ApicSupport | CPU_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_CONFIG_LIB_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_CONFIG_LIB_PREMEM_CONFIG Struct Reference

CPU Config Library PreMemory Configuration Structure. More...

#include <CpuConfigLibPreMemConfig.h>

Collaboration diagram for CPU_CONFIG_LIB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | HyperThreading: 1
Enable or Disable Hyper Threading; 0: Disable; 1: Enable.
UINT32 | BootFrequency: 2
Sets the boot frequency starting from reset vector. More...
UINT32 | ActiveCoreCount: 3
Number of processor cores to enable. More...
UINT32 | JtagC10PowerGateDisable: 1
False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False< >; 1: True.
UINT32 | BistOnReset: 1
(Test) Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
UINT32 | VmxEnable: 1
Enable or Disable Virtual Machine Extensions (VMX) feature. More...
UINT32 | FClkFrequency: 2
Processor Early Power On Configuration FCLK setting. More...
UINT32 | CrashLogEnable: 1
Enable or Disable CrashLog feature. More...
UINT32 | TmeEnable: 1
Enable or Disable Total Memory Encryption (TME) feature. More...
UINT32 | DebugInterfaceEnable: 2
Enable or Disable processor debug features; 0: Disable; 1: Enable; 2: No Change.
UINT32 | DebugInterfaceLockEnable: 1
Lock or Unlock debug interface features; 0: Disable; 1: Enable.
UINT32 | ActiveCoreCount1: 4
Number of big cores in processor to enable. More...
UINT32 | PeciSxReset: 1
Enables a mailbox command to resolve rare PECI related Sx issues. More...
UINT32 | PeciC10Reset: 1
Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit. More...
UINT32 | ActiveSmallCoreCount: 6
Number of small cores in processor to enable. More...
UINT32 | CrashLogGprs: 2
Enable or Disable CrashLog GPRs dump. More...
UINT32 | ComputeDieSscEnable: 1
Enable or Disable Compute Die SSC configuration. More...
UINT32 | SocDieSscEnable: 1
Enable or Disable Soc Die SSC configuration. More...
UINT8 | CpuRatio
CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio. More...
UINT8 | ActiveSocNorthAtomCoreCount
Number of enabled atom cores on SoC. More...
UINT8 | ComputeDieSscValue
SSC configuration value of Compute Die. More...
UINT8 | SocDieSscValue
SSC configuration value of Soc Die. More...
UINT32 | BclkSource: 2
Clock source of BCLK OC Frequency. More...
UINT8 | InfDfxPwrEnable
Determine whether to keep or shutdown INF_DFX power rail. More...
UINT8 | ConfigTdpLevel
Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up.

Detailed Description

CPU Config Library PreMemory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Expand the supported number of processor cores (ActiveCoreCount1). Revision 3:
  • Added PECI Sx and C10 Reset. Revision 4:
  • Added ActiveSmallCoreCount. Revision 5:
  • Added CrashLogGprs Revision 6:
  • Added ActiveSocNorthAtomCoreCount Revision 7:
  • Added ComputeDieSscEnable, SocDieSscEnable, ComputeDieSscValue, and SocDieSscValue Revision 8:
  • Added BclkSource. Revision 9:
  • Removed Elixir Springs Patch Revision 10
  • Add InfDfxPwrEnable Revision 11
  • Add ConfigTdpLevel, CustomPowerLimit1

Definition at line 61 of file CpuConfigLibPreMemConfig.h.

Member Data Documentation

◆ ActiveCoreCount

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount

Number of processor cores to enable.

  • 0: All cores
  • 1: 1 core
  • 2: 2 cores
  • 3: 3 cores
    Deprecated:
    due to core active number limitaion.

Definition at line 79 of file CpuConfigLibPreMemConfig.h.

◆ ActiveCoreCount1

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount1

Number of big cores in processor to enable.

And support up to 15 cores.

  • 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 16).
  • 1: 1 core
  • 2: 2 cores
  • 3: 3 cores

Definition at line 121 of file CpuConfigLibPreMemConfig.h.

◆ ActiveSmallCoreCount

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSmallCoreCount

Number of small cores in processor to enable.

And support up to 63 cores.

  • 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 64).
  • 1: 1 core
  • 2: 2 cores
  • 3: 3 cores

Definition at line 148 of file CpuConfigLibPreMemConfig.h.

◆ ActiveSocNorthAtomCoreCount

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSocNorthAtomCoreCount

Number of enabled atom cores on SoC.

Default is set to supported core number.

  • 0 - all core disabled
  • 1 - enable 1 core
  • 2 - enable 2 cores
  • others - reserved for future use

Definition at line 185 of file CpuConfigLibPreMemConfig.h.

◆ BclkSource

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::BclkSource

Clock source of BCLK OC Frequency.

  • 0: SOC
  • 1: CPU
  • 2: PCH
  • 3: Ext. Clock (optional)

Definition at line 214 of file CpuConfigLibPreMemConfig.h.

◆ BootFrequency

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::BootFrequency

Sets the boot frequency starting from reset vector.

  • 0: Maximum battery performance.
  • 1: Maximum non-turbo performance -2: Turbo performance.
    Note
    If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.

Definition at line 71 of file CpuConfigLibPreMemConfig.h.

◆ ComputeDieSscEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscEnable

Enable or Disable Compute Die SSC configuration.

  • 0: Disable
  • 1: Enable

Definition at line 163 of file CpuConfigLibPreMemConfig.h.

◆ ComputeDieSscValue

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscValue

SSC configuration value of Compute Die.

SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.

  • 0 : invalid
  • 1 : 0.01%
  • 2 : 0.02%
  • 100 : 1%

Definition at line 195 of file CpuConfigLibPreMemConfig.h.

◆ CpuRatio

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::CpuRatio

CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.

0: Disabled If disabled, doesn't override max-non turbo ratio.

Definition at line 175 of file CpuConfigLibPreMemConfig.h.

◆ CrashLogEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogEnable

Enable or Disable CrashLog feature.

  • 0: Disable
  • 1: Enable

Definition at line 101 of file CpuConfigLibPreMemConfig.h.

◆ CrashLogGprs

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogGprs

Enable or Disable CrashLog GPRs dump.

  • 0: Disable
  • 1: Gprs Enabled, Smm Gprs Enabled 2: Gprs Enabled, Smm Gprs Disabled

Definition at line 156 of file CpuConfigLibPreMemConfig.h.

◆ FClkFrequency

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::FClkFrequency

Processor Early Power On Configuration FCLK setting.

  • 0: 800 MHz (ULT/ULX).
  • 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.
  • 2: 400 MHz.
  • 3: Reserved.

Definition at line 95 of file CpuConfigLibPreMemConfig.h.

◆ InfDfxPwrEnable

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::InfDfxPwrEnable

Determine whether to keep or shutdown INF_DFX power rail.

INF_DFX power is up from cold boot.

  • 0 : INF_DFX shutdown
  • 1 : INF_DFX power up

Definition at line 221 of file CpuConfigLibPreMemConfig.h.

◆ PeciC10Reset

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::PeciC10Reset

Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.

If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value 0: Disable for CPU's

  • 0: Disable
  • 1: Enable
    Deprecated:
    no longer used.

Definition at line 138 of file CpuConfigLibPreMemConfig.h.

◆ PeciSxReset

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::PeciSxReset

Enables a mailbox command to resolve rare PECI related Sx issues.

Note
This should only be used on systems that observe PECI Sx issues.
  • 0: Disable
  • 1: Enable

Definition at line 129 of file CpuConfigLibPreMemConfig.h.

◆ SocDieSscEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscEnable

Enable or Disable Soc Die SSC configuration.

  • 0: Disable
  • 1: Enable

Definition at line 170 of file CpuConfigLibPreMemConfig.h.

◆ SocDieSscValue

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscValue

SSC configuration value of Soc Die.

SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.

  • 0 : invalid
  • 1 : 0.01%
  • 2 : 0.02%
  • 100 : 1%

Definition at line 205 of file CpuConfigLibPreMemConfig.h.

◆ TmeEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::TmeEnable

Enable or Disable Total Memory Encryption (TME) feature.

  • 0: Disable
  • 1: Enable

Definition at line 108 of file CpuConfigLibPreMemConfig.h.

◆ VmxEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::VmxEnable

Enable or Disable Virtual Machine Extensions (VMX) feature.

  • 0: Disable
  • 1: Enable

Definition at line 87 of file CpuConfigLibPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuConfigLibPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_CONFIG_LIB_PREMEM_CONFIG Member List

This is the complete list of members for CPU_CONFIG_LIB_PREMEM_CONFIG, including all inherited members.

ActiveCoreCount | CPU_CONFIG_LIB_PREMEM_CONFIG
ActiveCoreCount1 | CPU_CONFIG_LIB_PREMEM_CONFIG
ActiveSmallCoreCount | CPU_CONFIG_LIB_PREMEM_CONFIG
ActiveSocNorthAtomCoreCount | CPU_CONFIG_LIB_PREMEM_CONFIG
BclkSource | CPU_CONFIG_LIB_PREMEM_CONFIG
BistOnReset | CPU_CONFIG_LIB_PREMEM_CONFIG
BootFrequency | CPU_CONFIG_LIB_PREMEM_CONFIG
ComputeDieSscEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
ComputeDieSscValue | CPU_CONFIG_LIB_PREMEM_CONFIG
ConfigTdpLevel | CPU_CONFIG_LIB_PREMEM_CONFIG
CpuRatio | CPU_CONFIG_LIB_PREMEM_CONFIG
CrashLogEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
CrashLogGprs | CPU_CONFIG_LIB_PREMEM_CONFIG
DebugInterfaceEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
DebugInterfaceLockEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
FClkFrequency | CPU_CONFIG_LIB_PREMEM_CONFIG
Header | CPU_CONFIG_LIB_PREMEM_CONFIG
HyperThreading | CPU_CONFIG_LIB_PREMEM_CONFIG
InfDfxPwrEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
JtagC10PowerGateDisable | CPU_CONFIG_LIB_PREMEM_CONFIG
PeciC10Reset | CPU_CONFIG_LIB_PREMEM_CONFIG
PeciSxReset | CPU_CONFIG_LIB_PREMEM_CONFIG
SocDieSscEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
SocDieSscValue | CPU_CONFIG_LIB_PREMEM_CONFIG
TmeEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
VmxEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_DMI_EQ_PARAM Struct Reference

Public Attributes | List of all members
CPU_DMI_EQ_PARAM Struct Reference

Represent lane specific Dmi Gen3 equalization parameters. More...

#include <CpuDmiPreMemConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | Rsvd0 [2]
Reserved bytes.

Detailed Description

Represent lane specific Dmi Gen3 equalization parameters.

Definition at line 61 of file CpuDmiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuDmiPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_DMI_EQ_PARAM Member List

This is the complete list of members for CPU_DMI_EQ_PARAM, including all inherited members.

Cm | CPU_DMI_EQ_PARAM
Cp | CPU_DMI_EQ_PARAM
Rsvd0 | CPU_DMI_EQ_PARAM
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_DMI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_DMI_PREMEM_CONFIG Struct Reference

The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI. More...

#include <CpuDmiPreMemConfig.h>

Collaboration diagram for CPU_DMI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | DmiMaxLinkSpeed
UINT8 | DmiGen3EqPh2Enable
(Test) DMI Equalization Phase 2 Enable Control More...
UINT8 | DmiGen3EqPh3Method
(Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI More...
UINT8 | DmiGen3ProgramStaticEq
(Test) Program DMI Gen3 EQ Phase1 Static Presets More...
UINT8 | DmiDeEmphasis
DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
UINT8 | DmiAspmCtrl
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
UINT8 | DmiAspmL1ExitLatency
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
UINT8 | DmiGen3RootPortPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3EndPointPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane.
UINT8 | DmiGen3EndPointHint [SA_DMI_MAX_LANE]
Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane.
UINT8 | DmiGen3RxCtlePeaking [SA_DMI_MAX_BUNDLE]
DMI Gen3 RxCTLEp per-Bundle control. More...
UINT8 | DmiGen3DsPortRxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3DsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3UsPortRxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3UsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3Ltcpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3Ltcpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3RtcoCpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3RtcoCpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | Rsvd0 [1]
Reserved bytes.
UINT8 | DmiGen4Ltcpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4Ltcpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4DsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4UsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4RtcoCpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4RtcoCpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiNewFom
Used for programming DMI New FOM.
UINT8 | DmiCdrRelock
Used for programming DMI CDR Relock.

Detailed Description

The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI.

Revision 1:

  • Initial version. Revision 2:
  • Added Policies for Dmi Higer Speed Training. Revision 3:
  • Added DmiCdrRelock Policy.

Definition at line 76 of file CpuDmiPreMemConfig.h.

Member Data Documentation

◆ DmiGen3EqPh2Enable

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh2Enable

(Test) DMI Equalization Phase 2 Enable Control

  • Disabled (0x0) : Disable phase 2
  • Enabled (0x1) : Enable phase 2
  • Auto (0x2) : Use the current default method (Default)

Definition at line 92 of file CpuDmiPreMemConfig.h.

◆ DmiGen3EqPh3Method

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh3Method

(Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI

  • Auto (0x0) : Use the current default method (Default)
  • HwEq (0x1) : Use Adaptive Hardware Equalization
  • SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
  • Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
  • Disabled (0x4) : Bypass Equalization Phase 3

Definition at line 101 of file CpuDmiPreMemConfig.h.

◆ DmiGen3ProgramStaticEq

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3ProgramStaticEq

(Test) Program DMI Gen3 EQ Phase1 Static Presets

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 107 of file CpuDmiPreMemConfig.h.

◆ DmiGen3RxCtlePeaking

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]

DMI Gen3 RxCTLEp per-Bundle control.

The range of the setting is (0-15). This setting has to be specified based upon platform design and must follow the guideline. Default is 12.

Definition at line 121 of file CpuDmiPreMemConfig.h.

◆ DmiMaxLinkSpeed

UINT8 CPU_DMI_PREMEM_CONFIG::DmiMaxLinkSpeed
  • Auto (0x0) : Maximum possible link speed (Default)
  • Gen1 (0x1) : Limit Link to Gen1 Speed
  • Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig
  • Gen3 (0x3) : Limit Link to Gen3 Speed

Definition at line 85 of file CpuDmiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuDmiPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_DMI_PREMEM_CONFIG Member List

This is the complete list of members for CPU_DMI_PREMEM_CONFIG, including all inherited members.

DmiAspmCtrl | CPU_DMI_PREMEM_CONFIG
DmiAspmL1ExitLatency | CPU_DMI_PREMEM_CONFIG
DmiCdrRelock | CPU_DMI_PREMEM_CONFIG
DmiDeEmphasis | CPU_DMI_PREMEM_CONFIG
DmiGen3DsPortRxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3DsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3EndPointHint | CPU_DMI_PREMEM_CONFIG
DmiGen3EndPointPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3EqPh2Enable | CPU_DMI_PREMEM_CONFIG
DmiGen3EqPh3Method | CPU_DMI_PREMEM_CONFIG
DmiGen3Ltcpo | CPU_DMI_PREMEM_CONFIG
DmiGen3Ltcpre | CPU_DMI_PREMEM_CONFIG
DmiGen3ProgramStaticEq | CPU_DMI_PREMEM_CONFIG
DmiGen3RootPortPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3RtcoCpo | CPU_DMI_PREMEM_CONFIG
DmiGen3RtcoCpre | CPU_DMI_PREMEM_CONFIG
DmiGen3RxCtlePeaking | CPU_DMI_PREMEM_CONFIG
DmiGen3UsPortRxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3UsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen4DsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen4Ltcpo | CPU_DMI_PREMEM_CONFIG
DmiGen4Ltcpre | CPU_DMI_PREMEM_CONFIG
DmiGen4RtcoCpo | CPU_DMI_PREMEM_CONFIG
DmiGen4RtcoCpre | CPU_DMI_PREMEM_CONFIG
DmiGen4UsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiMaxLinkSpeed | CPU_DMI_PREMEM_CONFIG
DmiNewFom | CPU_DMI_PREMEM_CONFIG
Header | CPU_DMI_PREMEM_CONFIG
Rsvd0 | CPU_DMI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_PCIE_CONFIG Struct Reference

Public Attributes | List of all members
CPU_PCIE_CONFIG Struct Reference

The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version. More...

#include <CpuPcieConfig.h>

Collaboration diagram for CPU_PCIE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
CPU_PCIE_ROOT_PORT_CONFIG | RootPort [CPU_PCIE_MAX_ROOT_PORTS]
These members describe the configuration of each SA PCIe root port.
CPU_PCIE_EQ_LANE_PARAM | EqPh3LaneParam [SA_PEG_MAX_LANE]
Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc. More...
PCIE_EQ_PARAM | HwEqGen4CoeffList [PCIE_HWEQ_COEFFS_MAX]
List of coefficients used during equalization (applicable to both software and hardware EQ)
UINT32 | FiaProgramming: 1
< (Test) Includes policies which are common to both SA and PCH PCIe
UINT32 | PegGen3ProgramStaticEq: 1
< Skip Fia Configuration and lock if enable More...
UINT32 | PegGen4ProgramStaticEq: 1
(Test) Program PEG Gen4 EQ Phase1 Static Presets More...
UINT32 | SetSecuredRegisterLock: 1
(Test) Cpu Pcie Secure Register Lock More...
UINT32 | SlotSelection: 1
This member allows to select between the PCI Express M2 or CEMx4 slot 1: PCIe M2; 0: CEMx4 slot.
UINT32 | PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings. More...

Detailed Description

The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version.

Revision 2:

  • SlotSelection policy added Revision 3
  • Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq Revision 4:
  • Deprecating SetSecuredRegisterLock Revision 5:
  • Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
  • Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
  • Deprecate VcEnabled policy Revision 7:
  • Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection Revision 8:
  • Added Serl policy Revision 9:
  • Align revision with CPU_PCIE_CONFIG_REVISION value Revision 10:
  • Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp

Definition at line 367 of file CpuPcieConfig.h.

Member Data Documentation

◆ EqPh3LaneParam

CPU_PCIE_EQ_LANE_PARAM CPU_PCIE_CONFIG::EqPh3LaneParam[SA_PEG_MAX_LANE]

Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.

Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).

Definition at line 377 of file CpuPcieConfig.h.

◆ PcieDeviceOverrideTablePtr

UINT32 CPU_PCIE_CONFIG::PcieDeviceOverrideTablePtr

PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.

This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0. The prototype of this policy is: PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;

Definition at line 425 of file CpuPcieConfig.h.

◆ PegGen3ProgramStaticEq

UINT32 CPU_PCIE_CONFIG::PegGen3ProgramStaticEq

< Skip Fia Configuration and lock if enable

(Test) Program PEG Gen3 EQ Phase1 Static Presets

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 392 of file CpuPcieConfig.h.

◆ PegGen4ProgramStaticEq

UINT32 CPU_PCIE_CONFIG::PegGen4ProgramStaticEq

(Test) Program PEG Gen4 EQ Phase1 Static Presets

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 400 of file CpuPcieConfig.h.

◆ SetSecuredRegisterLock

UINT32 CPU_PCIE_CONFIG::SetSecuredRegisterLock

(Test) Cpu Pcie Secure Register Lock

  • Disabled (0x0)
  • Enabled (0x1)

Definition at line 406 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_PCIE_CONFIG Member List

This is the complete list of members for CPU_PCIE_CONFIG, including all inherited members.

EqPh3LaneParam | CPU_PCIE_CONFIG
FiaProgramming | CPU_PCIE_CONFIG
Header | CPU_PCIE_CONFIG
HwEqGen4CoeffList | CPU_PCIE_CONFIG
PcieDeviceOverrideTablePtr | CPU_PCIE_CONFIG
PegGen3ProgramStaticEq | CPU_PCIE_CONFIG
PegGen4ProgramStaticEq | CPU_PCIE_CONFIG
RootPort | CPU_PCIE_CONFIG
SetSecuredRegisterLock | CPU_PCIE_CONFIG
SlotSelection | CPU_PCIE_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_PCIE_EQ_LANE_PARAM Struct Reference

Public Attributes | List of all members
CPU_PCIE_EQ_LANE_PARAM Struct Reference

Represent lane specific PCIe Gen3 equalization parameters. More...

#include <CpuPcieConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | PegGen3RootPortPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
UINT8 | PegGen3EndPointPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
UINT8 | PegGen3EndPointHint
(Test) Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
UINT8 | PegGen4RootPortPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
UINT8 | PegGen4EndPointPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
UINT8 | PegGen4EndPointHint
(Test) Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane

Detailed Description

Represent lane specific PCIe Gen3 equalization parameters.

Definition at line 288 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_PCIE_EQ_LANE_PARAM Member List

This is the complete list of members for CPU_PCIE_EQ_LANE_PARAM, including all inherited members.

Cm | CPU_PCIE_EQ_LANE_PARAM
Cp | CPU_PCIE_EQ_LANE_PARAM
PegGen3EndPointHint | CPU_PCIE_EQ_LANE_PARAM
PegGen3EndPointPreset | CPU_PCIE_EQ_LANE_PARAM
PegGen3RootPortPreset | CPU_PCIE_EQ_LANE_PARAM
PegGen4EndPointHint | CPU_PCIE_EQ_LANE_PARAM
PegGen4EndPointPreset | CPU_PCIE_EQ_LANE_PARAM
PegGen4RootPortPreset | CPU_PCIE_EQ_LANE_PARAM
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_PCIE_GPIO_INFO Struct Reference

Public Attributes | List of all members
CPU_PCIE_GPIO_INFO Struct Reference

CPU PCIe GPIO Data Structure. More...

#include <HybridGraphicsConfig.h>

Public Attributes

UINT8 | ExpanderNo
Offset 0 Expander No For I2C based GPIO.
BOOLEAN | Active
Offset 1 0=Active Low; 1=Active High.
UINT8 | Rsvd0 [2]
Offset 2 Reserved.
UINT32 | GpioNo
Offset 4 GPIO pad.

Detailed Description

CPU PCIe GPIO Data Structure.

Definition at line 53 of file HybridGraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • HybridGraphicsConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_PCIE_GPIO_INFO Member List

This is the complete list of members for CPU_PCIE_GPIO_INFO, including all inherited members.

Active | CPU_PCIE_GPIO_INFO
ExpanderNo | CPU_PCIE_GPIO_INFO
GpioNo | CPU_PCIE_GPIO_INFO
Rsvd0 | CPU_PCIE_GPIO_INFO
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_PCIE_ROOT_PORT_CONFIG Struct Reference

Public Attributes | List of all members
CPU_PCIE_ROOT_PORT_CONFIG Struct Reference

The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port. More...

#include <CpuPcieConfig.h>

Public Attributes

UINT32 | ExtSync: 1
Indicate whether the extended synch is enabled. 0: Disable; 1: Enable.
UINT32 | MultiVcEnabled: 1
Multiple Virtual Channel. 0: Disable; 1: Enable
UINT32 | RsvdBits0: 30
Reserved bits.
UINT8 | Gen4EqPh3Method
PCIe Gen4 Equalization Method. More...
UINT8 | FomsCp
FOM Score Board Control Policy.
UINT8 | RsvdBytes0 [2]
Reserved bytes.
UINT32 | Gen3Uptp: 4
(Test) Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen3Dptp: 4
(Test) Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen4Uptp: 4
(Test) Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen4Dptp: 4
(Test) Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen5Uptp: 4
(Test) Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is 5.
UINT32 | Gen5Dptp: 4
(Test) Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is 7.
UINT32 | RsvdBits1: 8
Reserved Bits.
PCIE_ROOT_PORT_COMMON_CONFIG | PcieRpCommonConfig
(Test) Includes policies which are common to both SA and PCH RootPort

Detailed Description

The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.

Definition at line 302 of file CpuPcieConfig.h.

Member Data Documentation

◆ Gen4EqPh3Method

UINT8 CPU_PCIE_ROOT_PORT_CONFIG::Gen4EqPh3Method

PCIe Gen4 Equalization Method.

  • HwEq (0x1) : Hardware Equalization (Default)
  • StaticEq (0x2) : Static Equalization

Definition at line 312 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_PCIE_ROOT_PORT_CONFIG Member List

This is the complete list of members for CPU_PCIE_ROOT_PORT_CONFIG, including all inherited members.

ExtSync | CPU_PCIE_ROOT_PORT_CONFIG
FomsCp | CPU_PCIE_ROOT_PORT_CONFIG
Gen3Dptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen3Uptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen4Dptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen4EqPh3Method | CPU_PCIE_ROOT_PORT_CONFIG
Gen4Uptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen5Dptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen5Uptp | CPU_PCIE_ROOT_PORT_CONFIG
MultiVcEnabled | CPU_PCIE_ROOT_PORT_CONFIG
PcieRpCommonConfig | CPU_PCIE_ROOT_PORT_CONFIG
RsvdBits0 | CPU_PCIE_ROOT_PORT_CONFIG
RsvdBits1 | CPU_PCIE_ROOT_PORT_CONFIG
RsvdBytes0 | CPU_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_PCIE_RP_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_PCIE_RP_PREMEM_CONFIG Struct Reference

CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version. More...

#include <CpuPcieConfig.h>

Collaboration diagram for CPU_PCIE_RP_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | RpEnabledMask
Root Port enabling mask. More...
UINT8 | LinkDownGpios
Assertion on Link Down GPIOs. More...
UINT8 | ClkReqMsgEnable
Enable ClockReq Messaging. More...
UINT8 | DekelSquelchWa
Dekel Recipe Workaround 2 1=Minimal, 9=Maximum,.
UINT8 | PcieSpeed [CPU_PCIE_MAX_ROOT_PORTS]
Determines each PCIE Port speed capability. More...
UINT8 | ClkReqMsgEnableRp [CPU_PCIE_MAX_ROOT_PORTS]
Enable ClockReq Messaging Policy is for all Rootports. More...
UINT8 | NewFom [CPU_PCIE_MAX_ROOT_PORTS]
To Enable/Disable New FOM 0: Disable; 1: Enable.
UINT8 | CdrRelock [CPU_PCIE_MAX_ROOT_PORTS]
To Enable/Disable CDR Relock 0: Disable; 1: Enable.

Detailed Description

CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version.

Revision 2: - Adding Dekel Suqelch Workaround Setup Variable Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable Revision 4: - Adding New FOM Setup Variable Revision 5: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.

Definition at line 156 of file CpuPcieConfig.h.

Member Data Documentation

◆ ClkReqMsgEnable

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::ClkReqMsgEnable

Enable ClockReq Messaging.

  • Disabled</> (0x0) : Disable ClockReq Messaging(Default)
  • Enabled (0x1) : Enable ClockReq Messaging

Definition at line 175 of file CpuPcieConfig.h.

◆ ClkReqMsgEnableRp

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS]

Enable ClockReq Messaging Policy is for all Rootports.

  • Disabled</> (0x0) : Disable ClockReq Messaging(Default)
  • Enabled (0x1) : Enable ClockReq Messaging

Definition at line 194 of file CpuPcieConfig.h.

◆ LinkDownGpios

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::LinkDownGpios

Assertion on Link Down GPIOs.

  • Disabled (0x0) : Disable assertion on Link Down GPIOs(Default)
  • Enabled (0x1) : Enable assertion on Link Down GPIOs

Definition at line 169 of file CpuPcieConfig.h.

◆ PcieSpeed

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS]

Determines each PCIE Port speed capability.

0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)

Definition at line 187 of file CpuPcieConfig.h.

◆ RpEnabledMask

UINT32 CPU_PCIE_RP_PREMEM_CONFIG::RpEnabledMask

Root Port enabling mask.

Bit0 presents RP1, Bit1 presents RP2, and so on. 0: Disable; 1: Enable.

Definition at line 163 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_PCIE_RP_PREMEM_CONFIG Member List

This is the complete list of members for CPU_PCIE_RP_PREMEM_CONFIG, including all inherited members.

CdrRelock | CPU_PCIE_RP_PREMEM_CONFIG
ClkReqMsgEnable | CPU_PCIE_RP_PREMEM_CONFIG
ClkReqMsgEnableRp | CPU_PCIE_RP_PREMEM_CONFIG
DekelSquelchWa | CPU_PCIE_RP_PREMEM_CONFIG
Header | CPU_PCIE_RP_PREMEM_CONFIG
LinkDownGpios | CPU_PCIE_RP_PREMEM_CONFIG
NewFom | CPU_PCIE_RP_PREMEM_CONFIG
PcieSpeed | CPU_PCIE_RP_PREMEM_CONFIG
RpEnabledMask | CPU_PCIE_RP_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_PCIE_RTD3_GPIO Struct Reference

Public Attributes | List of all members
CPU_PCIE_RTD3_GPIO Struct Reference

CPU PCIE RTD3 GPIO Data Structure. More...

#include <HybridGraphicsConfig.h>

Collaboration diagram for CPU_PCIE_RTD3_GPIO:
[legend]

Public Attributes

CPU_PCIE_GPIO_INFO HoldRst
Offset 0 This field contain PCIe HLD RESET GPIO value and level information.
CPU_PCIE_GPIO_INFO PwrEnable
Offset 8 This field contain PCIe PWR Enable GPIO value and level information.
UINT32 | WakeGpioNo
Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number.
UINT8 | GpioSupport
Offset 20 Depends on board design the GPIO configuration may be different: 0=Not Supported, 1=PCH Based, 2=I2C based.
UINT8 | Rsvd0 [3]
Offset 21.

Detailed Description

CPU PCIE RTD3 GPIO Data Structure.

Definition at line 63 of file HybridGraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • HybridGraphicsConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_PCIE_RTD3_GPIO Member List

This is the complete list of members for CPU_PCIE_RTD3_GPIO, including all inherited members.

GpioSupport | CPU_PCIE_RTD3_GPIO
HoldRst | CPU_PCIE_RTD3_GPIO
PwrEnable | CPU_PCIE_RTD3_GPIO
Rsvd0 | CPU_PCIE_RTD3_GPIO
WakeGpioNo | CPU_PCIE_RTD3_GPIO
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_POWER_MGMT_BASIC_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_BASIC_CONFIG Struct Reference

CPU Power Management Basic Configuration Structure. More...

#include <CpuPowerMgmtBasicConfig.h>

Collaboration diagram for CPU_POWER_MGMT_BASIC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | BootFrequency: 2
Sets the boot frequency starting from reset vector. More...
UINT32 | SkipSetBootPState: 1
Choose whether to skip SetBootPState function for all APs; 0: Do not skip; 1: Skip.
UINT32 | Hwp: 2
Enable or Disable Intel Speed Shift Technology. More...
UINT32 | HdcControl: 2
Hardware Duty Cycle Control configuration. More...
UINT32 | PowerLimit2: 1
Enable or Disable short duration Power Limit (PL2). 0: Disable; 1: Enable
UINT32 | TurboPowerLimitLock: 1
MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; 0: Disable; 1: Enable (Lock).
UINT32 | PowerLimit3DutyCycle: 8
Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0.
UINT32 | PowerLimit3Lock: 1
Package PL3 MSR 615h lock; 0: Disable; 1: Enable (Lock).
UINT32 | PowerLimit4Lock: 1
Package PL4 MSR 601h lock; 0: Disable; 1: Enable (Lock).
UINT32 | TccOffsetClamp: 1
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1. More...
UINT32 | TccOffsetLock: 1
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: Disabled; 1: Enabled (Lock).
UINT32 | TurboMode: 1
Enable or Disable Turbo Mode. Disable; 1: Enable
UINT32 | HwpInterruptControl: 1
Set HW P-State Interrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: Enable.
UINT32 | ApplyConfigTdp: 1
Switch TDP applied setting based on non-cTDP or TDP; 0: non-cTDP; 1: cTDP.
UINT32 | HwpLock: 1
HWP Lock in MISC PWR MGMT MSR 1AAh; 0: Disable; 1: Enable (Lock).
UINT32 | DualTauBoost: 1
Dual Tau Base Performance Boost support. More...
UINT32 | RsvdBits: 6
Reserved for future use.
UINT8 | OneCoreRatioLimit
1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. More...
UINT8 | TwoCoreRatioLimit
2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins. More...
UINT8 | ThreeCoreRatioLimit
3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins. More...
UINT8 | FourCoreRatioLimit
4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins. More...
UINT8 | FiveCoreRatioLimit
5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins. More...
UINT8 | SixCoreRatioLimit
6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins. More...
UINT8 | SevenCoreRatioLimit
7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins. More...
UINT8 | EightCoreRatioLimit
8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins. More...
UINT8 | TccActivationOffset
TCC Activation Offset. More...
UINT8 | EnableItbm: 1
Intel Turbo Boost Max Technology 3.0 Enabling it on processors with OS support will allow OS to exploit the diversity in max turbo frequency of the cores. More...
UINT8 | EnableItbmDriver: 1
UINT8 | EnablePerCorePState: 1
Per Core P State OS control mode Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1. More...
UINT8 | EnableHwpAutoPerCorePstate: 1
HwP Autonomous Per Core P State Disabling will set Bit 30 = 1, command 0x11. More...
UINT8 | EnableHwpAutoEppGrouping: 1
HwP Autonomous EPP grouping. More...
UINT8 | EnableEpbPeciOverride: 1
EPB override over PECI Enable by sending pcode command 0x2b , subcommand 0x3 to 1. More...
UINT8 | EnableFastMsrHwpReq: 1
Support for Fast MSR for IA32_HWP_REQUEST. More...
UINT8 | ReservedBits1: 1
Reserved for future use.
UINT8 | MinRingRatioLimit
Minimum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
UINT8 | MaxRingRatioLimit
Maximum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
UINT16 | PowerLimit1
Package Long duration turbo mode power limit (PL1). More...
UINT16 | PowerLimit2Power
Package Short duration turbo mode power limit (PL2). More...
UINT16 | PowerLimit3
Package PL3 power limit. More...
UINT16 | PowerLimit4
Package PL4 power limit. More...
UINT32 | PowerLimit1Time
Package Long duration turbo mode power limit (PL1) time window in seconds. More...
UINT32 | PowerLimit3Time
Package PL3 time window. Range from 3ms to 64ms.
UINT32 | TccOffsetTimeWindowForRatl
Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL). More...
UINT8 | TurboRatioLimitRatio [TURBO_RATIO_LIMIT_ARRAY_SIZE]
Turbo Ratio Limit Ratio array, TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point. More...
UINT8 | TurboRatioLimitNumCore [TURBO_RATIO_LIMIT_ARRAY_SIZE]
Turbo Ratio Limit Num Core array, TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point. More...
UINT8 | AtomTurboRatioLimitRatio [TURBO_RATIO_LIMIT_ARRAY_SIZE]
ATOM Turbo Ratio Limit Ratio array, AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point. More...
UINT8 | AtomTurboRatioLimitNumCore [TURBO_RATIO_LIMIT_ARRAY_SIZE]
ATOM Turbo Ratio Limit Num Core array, AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point. More...

Detailed Description

CPU Power Management Basic Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Changed EnableItbm default to be disable
  • Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS driver Revision 3:
  • Add ApplyConfigTdp for TDP initialization settings based on non-cTDP or cTDP Revision 4:
  • Add Hwp Lock support Revision 5:
  • Add TurboRatioLimitRatio, TurboRatioLimitNumCore, AtomTurboRatioLimitRatio and AtomTurboRatioLimitNumCore Revision 6:
  • Add DualTauBoost Revision 7:
  • Changed EnableItbm default to be enable

Definition at line 67 of file CpuPowerMgmtBasicConfig.h.

Member Data Documentation

◆ AtomTurboRatioLimitNumCore

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::AtomTurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE]

ATOM Turbo Ratio Limit Num Core array, AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x651. Note:

  • These policies are for platforms support ATOM MSR pair 0x650 and 0x651.

Definition at line 305 of file CpuPowerMgmtBasicConfig.h.

◆ AtomTurboRatioLimitRatio

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::AtomTurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE]

ATOM Turbo Ratio Limit Ratio array, AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x650. Note:

  • These policies are for platforms support ATOM MSR pair 0x650 and 0x651.

Definition at line 297 of file CpuPowerMgmtBasicConfig.h.

◆ BootFrequency

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::BootFrequency

Sets the boot frequency starting from reset vector.

  • 0: Maximum battery performance.
  • 1: Maximum non-turbo performance.
  • 2: Turbo performance.
    Note
    If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.

Definition at line 76 of file CpuPowerMgmtBasicConfig.h.

◆ DualTauBoost

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::DualTauBoost

Dual Tau Base Performance Boost support.

This will improve platform performance for desktop sku. When enabled, it exposes 2 MMIO PL1 and MMIO Tau registers, and also provides the default value.

Note
: This is only applicable for Desktop 35W/65W/125W sku.
: When this is enabled, it will override the settings in policys PowerLimit1, PowerLimit1Time, PowerLimit2Power. 0: Disable; 1: Enable

Definition at line 115 of file CpuPowerMgmtBasicConfig.h.

◆ EightCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EightCoreRatioLimit

8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 180 of file CpuPowerMgmtBasicConfig.h.

◆ EnableEpbPeciOverride

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableEpbPeciOverride

EPB override over PECI Enable by sending pcode command 0x2b , subcommand 0x3 to 1.

This will allow OOB EPB PECI override control. 0: Disable; 1: Enable;

Definition at line 228 of file CpuPowerMgmtBasicConfig.h.

◆ EnableFastMsrHwpReq

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableFastMsrHwpReq

Support for Fast MSR for IA32_HWP_REQUEST.

On systems with HwP enabled, if this feature is available as indicated by MSR 0x65F[0] = 1, set MSR 0x657[0] = 1. 0: Disable; 1: Enable;

Definition at line 235 of file CpuPowerMgmtBasicConfig.h.

◆ EnableHwpAutoEppGrouping

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoEppGrouping

HwP Autonomous EPP grouping.

Disabling will set Bit 29 = 1, command 0x11. When set, autonomous will not necesarrily request the same value for all cores with same EPP. Enabling will clean Bit 29 = 0, command 0x11. Autonomous will request same values for all cores with same EPP. 0: Disable; 1: Enable;

Definition at line 221 of file CpuPowerMgmtBasicConfig.h.

◆ EnableHwpAutoPerCorePstate

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoPerCorePstate

HwP Autonomous Per Core P State Disabling will set Bit 30 = 1, command 0x11.

When set, autonomous will request the same value for all cores all the time. 0: Disable; 1: Enable;

Definition at line 213 of file CpuPowerMgmtBasicConfig.h.

◆ EnableItbm

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableItbm

Intel Turbo Boost Max Technology 3.0 Enabling it on processors with OS support will allow OS to exploit the diversity in max turbo frequency of the cores.

0: Disable; 1: Enable;

Definition at line 194 of file CpuPowerMgmtBasicConfig.h.

◆ EnableItbmDriver

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableItbmDriver
Deprecated:
: Platform doesn't have Intel Turbo Boost Max Technology 3.0 Driver Enabling it will load the driver upon ACPI device with HID = INT3510. 0: Disable; 1: Enable;

Definition at line 200 of file CpuPowerMgmtBasicConfig.h.

◆ EnablePerCorePState

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnablePerCorePState

Per Core P State OS control mode Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1.

When set, the highest core request is used for all other core requests. 0: Disable; 1: Enable;

Definition at line 206 of file CpuPowerMgmtBasicConfig.h.

◆ FiveCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::FiveCoreRatioLimit

5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.

Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 156 of file CpuPowerMgmtBasicConfig.h.

◆ FourCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::FourCoreRatioLimit

4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 149 of file CpuPowerMgmtBasicConfig.h.

◆ HdcControl

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::HdcControl

Hardware Duty Cycle Control configuration.

0: Disabled; 1: Enabled 2-3:Reserved HDC enables the processor to autonomously force components to enter into an idle state to lower effective frequency. This allows for increased package level C6 residency.

Note
Currently this feature is recommended to be enabled only on win10

Definition at line 91 of file CpuPowerMgmtBasicConfig.h.

◆ Hwp

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::Hwp

Enable or Disable Intel Speed Shift Technology.

Enabling allows for processor control of P-state transitions. 0: Disable; 1: Enable; Bit 1 is ignored.

Note
Currently this feature is recommended to be enabled only on win10

Definition at line 84 of file CpuPowerMgmtBasicConfig.h.

◆ OneCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::OneCoreRatioLimit

1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit.

For overclocking parts: LFM to Fused 1-Core Ratio Limit + OC Bins. Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 125 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit1

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1

Package Long duration turbo mode power limit (PL1).

Default is the TDP power limit of processor. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 243 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit1Time

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1Time

Package Long duration turbo mode power limit (PL1) time window in seconds.

Used in calculating the average power over time. Mobile: 28s Desktop: 8s Range: 0 - 128s

Definition at line 267 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit2Power

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit2Power

Package Short duration turbo mode power limit (PL2).

Allows for short excursions above TDP power limit. Default = 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 248 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit3

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3

Package PL3 power limit.

PL3 is the CPU Peak Power Occurences Limit. Default: 0. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 253 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit4

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit4

Package PL4 power limit.

PL4 is a Preemptive CPU Package Peak Power Limit, it will never be exceeded. Power is premptively lowered before limit is reached. Default: 0. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 259 of file CpuPowerMgmtBasicConfig.h.

◆ SevenCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::SevenCoreRatioLimit

7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 172 of file CpuPowerMgmtBasicConfig.h.

◆ SixCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::SixCoreRatioLimit

6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 164 of file CpuPowerMgmtBasicConfig.h.

◆ TccActivationOffset

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TccActivationOffset

TCC Activation Offset.

Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at (TCC Activation Temperature - TCC Activation Offset), in degrees Celcius. For Y SKU, the recommended default for this policy is 10 For all other SKUs the recommended default are 0, causing TCC to activate at TCC Activation temperature.

Note
The policy is recommended for validation purpose only.

Definition at line 188 of file CpuPowerMgmtBasicConfig.h.

◆ TccOffsetClamp

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetClamp

Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.

For Y SKU, the recommended default for this policy is 1: Enabled, which indicates throttling below P1 is allowed. For all other SKUs the recommended default are 0: Disabled.

Definition at line 102 of file CpuPowerMgmtBasicConfig.h.

◆ TccOffsetTimeWindowForRatl

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetTimeWindowForRatl

Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).

For Y SKU, the recommended default for this policy is 5000: 5 seconds, For all other SKUs the recommended default are 0: Disabled

Definition at line 273 of file CpuPowerMgmtBasicConfig.h.

◆ ThreeCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::ThreeCoreRatioLimit

3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 141 of file CpuPowerMgmtBasicConfig.h.

◆ TurboRatioLimitNumCore

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE]

Turbo Ratio Limit Num Core array, TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x1AE. Note:

  • These policies are for platforms support MSR pair 0x1AD and 0x1AE.

Definition at line 289 of file CpuPowerMgmtBasicConfig.h.

◆ TurboRatioLimitRatio

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE]

Turbo Ratio Limit Ratio array, TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x1AD. Note:

  • These policies are for platforms support MSR pair 0x1AD and 0x1AE.

Definition at line 281 of file CpuPowerMgmtBasicConfig.h.

◆ TwoCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TwoCoreRatioLimit

2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 133 of file CpuPowerMgmtBasicConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtBasicConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_POWER_MGMT_BASIC_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_BASIC_CONFIG, including all inherited members.

ApplyConfigTdp | CPU_POWER_MGMT_BASIC_CONFIG
AtomTurboRatioLimitNumCore | CPU_POWER_MGMT_BASIC_CONFIG
AtomTurboRatioLimitRatio | CPU_POWER_MGMT_BASIC_CONFIG
BootFrequency | CPU_POWER_MGMT_BASIC_CONFIG
DualTauBoost | CPU_POWER_MGMT_BASIC_CONFIG
EightCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
EnableEpbPeciOverride | CPU_POWER_MGMT_BASIC_CONFIG
EnableFastMsrHwpReq | CPU_POWER_MGMT_BASIC_CONFIG
EnableHwpAutoEppGrouping | CPU_POWER_MGMT_BASIC_CONFIG
EnableHwpAutoPerCorePstate | CPU_POWER_MGMT_BASIC_CONFIG
EnableItbm | CPU_POWER_MGMT_BASIC_CONFIG
EnableItbmDriver | CPU_POWER_MGMT_BASIC_CONFIG
EnablePerCorePState | CPU_POWER_MGMT_BASIC_CONFIG
FiveCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
FourCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
HdcControl | CPU_POWER_MGMT_BASIC_CONFIG
Header | CPU_POWER_MGMT_BASIC_CONFIG
Hwp | CPU_POWER_MGMT_BASIC_CONFIG
HwpInterruptControl | CPU_POWER_MGMT_BASIC_CONFIG
HwpLock | CPU_POWER_MGMT_BASIC_CONFIG
MaxRingRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
MinRingRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
OneCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit1 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit1Time | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit2 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit2Power | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3DutyCycle | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3Lock | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3Time | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit4 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit4Lock | CPU_POWER_MGMT_BASIC_CONFIG
ReservedBits1 | CPU_POWER_MGMT_BASIC_CONFIG
RsvdBits | CPU_POWER_MGMT_BASIC_CONFIG
SevenCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
SixCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
SkipSetBootPState | CPU_POWER_MGMT_BASIC_CONFIG
TccActivationOffset | CPU_POWER_MGMT_BASIC_CONFIG
TccOffsetClamp | CPU_POWER_MGMT_BASIC_CONFIG
TccOffsetLock | CPU_POWER_MGMT_BASIC_CONFIG
TccOffsetTimeWindowForRatl | CPU_POWER_MGMT_BASIC_CONFIG
ThreeCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
TurboMode | CPU_POWER_MGMT_BASIC_CONFIG
TurboPowerLimitLock | CPU_POWER_MGMT_BASIC_CONFIG
TurboRatioLimitNumCore | CPU_POWER_MGMT_BASIC_CONFIG
TurboRatioLimitRatio | CPU_POWER_MGMT_BASIC_CONFIG
TwoCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_POWER_MGMT_CUSTOM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_CUSTOM_CONFIG Struct Reference

CPU Power Management Custom Configuration Structure. More...

#include <CpuPowerMgmtCustomConfig.h>

Collaboration diagram for CPU_POWER_MGMT_CUSTOM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PPM_CUSTOM_RATIO_TABLE CustomRatioTable
Custom Processor Ratio Table Instance.
PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable [MAX_CUSTOM_CTDP_ENTRIES]
Custom ConfigTdp Settings Instance.
UINT32 | ConfigTdpLock: 1
Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable.
UINT32 | ConfigTdpBios: 1
Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.
UINT32 | RsvdBits: 30
Reserved for future use.

Detailed Description

CPU Power Management Custom Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 93 of file CpuPowerMgmtCustomConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtCustomConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_POWER_MGMT_CUSTOM_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_CUSTOM_CONFIG, including all inherited members.

ConfigTdpBios | CPU_POWER_MGMT_CUSTOM_CONFIG
ConfigTdpLock | CPU_POWER_MGMT_CUSTOM_CONFIG
CustomConfigTdpTable | CPU_POWER_MGMT_CUSTOM_CONFIG
CustomRatioTable | CPU_POWER_MGMT_CUSTOM_CONFIG
Header | CPU_POWER_MGMT_CUSTOM_CONFIG
RsvdBits | CPU_POWER_MGMT_CUSTOM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_POWER_MGMT_PSYS_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_PSYS_CONFIG Struct Reference

CPU Power Management Psys(Platform) Configuration Structure. More...

#include <CpuPowerMgmtPsysConfig.h>

Collaboration diagram for CPU_POWER_MGMT_PSYS_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PsysPowerLimit1: 1
MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power.
UINT32 | PsysPowerLimit1Time: 8
MSR 0x65C[23:17]: PL1 timewindow in seconds.
UINT32 | PsysPowerLimit2: 1
MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power.
UINT32 | RsvdBits: 22
Reserved for future use.
UINT16 | PsysPowerLimit1Power
MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
UINT16 | PsysPowerLimit2Power
MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
UINT16 | PsysPmax
PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. 0-1024 Watts. Value of 800 = 100W.
UINT8 | Rsvd [2]
Reserved for future use and config block alignment.

Detailed Description

CPU Power Management Psys(Platform) Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 50 of file CpuPowerMgmtPsysConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtPsysConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_POWER_MGMT_PSYS_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_PSYS_CONFIG, including all inherited members.

Header | CPU_POWER_MGMT_PSYS_CONFIG
PsysPmax | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit1 | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit1Power | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit1Time | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit2 | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit2Power | CPU_POWER_MGMT_PSYS_CONFIG
Rsvd | CPU_POWER_MGMT_PSYS_CONFIG
RsvdBits | CPU_POWER_MGMT_PSYS_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_POWER_MGMT_TEST_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_TEST_CONFIG Struct Reference

CPU Power Management Test Configuration Structure. More...

#include <CpuPowerMgmtTestConfig.h>

Collaboration diagram for CPU_POWER_MGMT_TEST_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | Eist: 1
Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable
UINT32 | EnergyEfficientPState: 1
Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable
UINT32 | EnergyEfficientTurbo: 1
Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable.
UINT32 | TStates: 1
Enable or Disable T states; 0: Disable; 1: Enable.
UINT32 | BiProcHot: 1
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable.
UINT32 | DisableProcHotOut: 1
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.
UINT32 | ProcHotResponse: 1
Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.
UINT32 | DisableVrThermalAlert: 1
Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.
UINT32 | EnableAllThermalFunctions: 1
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.
UINT32 | ThermalMonitor: 1
Enable or Disable Thermal Monitor; 0: Disable; 1: Enable.
UINT32 | Cx: 1
Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable
UINT32 | PmgCstCfgCtrlLock: 1
If enabled, sets MSR 0xE2[15]; 0: Disable; 1: Enable.
UINT32 | C1e: 1
Enable or Disable Enhanced C-states. 0: Disable; 1: Enable
UINT32 | C1AutoDemotion: 1
Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; 1: C1 Auto demotion
UINT32 | C1UnDemotion: 1
Enable or Disable C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion
UINT32 | C3AutoDemotion: 1
UINT32 | C3UnDemotion: 1
UINT32 | PkgCStateDemotion: 1
Enable or Disable Package Cstate Demotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
UINT32 | PkgCStateUnDemotion: 1
Enable or Disable Package Cstate UnDemotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
UINT32 | CStatePreWake: 1
Enable or Disable CState-Pre wake. Disable; 1: Enable
UINT32 | TimedMwait: 1
Enable or Disable TimedMwait Support. Disable; 1: Enable.
UINT32 | CstCfgCtrIoMwaitRedirection: 1
Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.
UINT32 | ProcHotLock: 1
If enabled, sets MSR 0x1FC[23]; 0: Disable; 1: Enable.
UINT32 | RaceToHalt: 1
Enable or Disable Race To Halt feature; 0: Disable; 1: Enable . RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)
UINT32 | ConfigTdpLevel: 8
UINT16 | CstateLatencyControl1Irtl
Offset 32-33 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].0 is Auto.
UINT16 | CstateLatencyControl2Irtl
Offset 34-35 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].0 is Auto.
UINT16 | CstateLatencyControl3Irtl
Offset 36-37 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].0 is Auto.
UINT16 | CstateLatencyControl4Irtl
Offset 38-39 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].0 is Auto.
UINT16 | CstateLatencyControl5Irtl
Offset 40-41 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].0 is Auto.
UINT16 | CstateLatencyControl0Irtl
Offset 42-43 Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].0 is Auto.
MAX_PKG_C_STATE PkgCStateLimit
Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit
Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; 2: 1024ns. More...
C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit
Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit
Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit
Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit
Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit
Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; 2: 1024ns.
CUSTOM_POWER_UNIT CustomPowerUnit
Offset 51 Default power unit in watts or in 125 milliwatt increments. More...
PPM_IRM_SETTING PpmIrmSetting
Offset 52 Interrupt Redirection Mode Select. More...
UINT8 | Rsvd [4]
Offset 53-56 Reserved for future use and config block alignment.

Detailed Description

CPU Power Management Test Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Add CstateLatencyControl0TimeUnit for WHL only
  • Add CstateLatencyControl0Irtl for WHL only Revision 3:
  • Change C State LatencyContol to Auto as default. Revision 4:
  • Add CstateLatencyControl0TimeUnit and CstateLatencyControl0Irtl. Revision 5:
  • Change EnergyEfficientTurbo to Disable as default. Revision 6:
  • Change ProcHotResponse and ProcHotLock to Enable as default. Revision 7:
  • Deprecate ConfigTdpLevel. Move to premem.

Definition at line 117 of file CpuPowerMgmtTestConfig.h.

Member Data Documentation

◆ C3AutoDemotion

UINT32 CPU_POWER_MGMT_TEST_CONFIG::C3AutoDemotion
Deprecated:
no longer used

Definition at line 134 of file CpuPowerMgmtTestConfig.h.

◆ C3UnDemotion

UINT32 CPU_POWER_MGMT_TEST_CONFIG::C3UnDemotion
Deprecated:
no longer used

Definition at line 135 of file CpuPowerMgmtTestConfig.h.

◆ ConfigTdpLevel

UINT32 CPU_POWER_MGMT_TEST_CONFIG::ConfigTdpLevel
Deprecated:
Move to premem phase.

Definition at line 143 of file CpuPowerMgmtTestConfig.h.

◆ CstateLatencyControl0TimeUnit

C_STATE_TIME_UNIT CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0TimeUnit

Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; 2: 1024ns.

Todo:
: The following enums have to be replaced with policies.

Definition at line 154 of file CpuPowerMgmtTestConfig.h.

◆ CustomPowerUnit

CUSTOM_POWER_UNIT CPU_POWER_MGMT_TEST_CONFIG::CustomPowerUnit

Offset 51 Default power unit in watts or in 125 milliwatt increments.

  • 0: PowerUnitWatts.
  • 1: PowerUnit125MilliWatts.

Definition at line 165 of file CpuPowerMgmtTestConfig.h.

◆ PpmIrmSetting

PPM_IRM_SETTING CPU_POWER_MGMT_TEST_CONFIG::PpmIrmSetting

Offset 52 Interrupt Redirection Mode Select.

  • 0: Fixed priority. //Default under CNL.
  • 1: Round robin.
  • 2: Hash vector.
  • 4: PAIR with fixed priority. //Default under KBL, not available under CNL.
  • 5: PAIR with round robin. //Not available under CNL.
  • 6: PAIR with hash vector. //Not available under CNL.
  • 7: No change.

Definition at line 176 of file CpuPowerMgmtTestConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtTestConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_POWER_MGMT_TEST_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_TEST_CONFIG, including all inherited members.

BiProcHot | CPU_POWER_MGMT_TEST_CONFIG
C1AutoDemotion | CPU_POWER_MGMT_TEST_CONFIG
C1e | CPU_POWER_MGMT_TEST_CONFIG
C1UnDemotion | CPU_POWER_MGMT_TEST_CONFIG
C3AutoDemotion | CPU_POWER_MGMT_TEST_CONFIG
C3UnDemotion | CPU_POWER_MGMT_TEST_CONFIG
ConfigTdpLevel | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl0Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl0TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl1Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl1TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl2Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl2TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl3Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl3TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl4Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl4TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl5Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl5TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CStatePreWake | CPU_POWER_MGMT_TEST_CONFIG
CstCfgCtrIoMwaitRedirection | CPU_POWER_MGMT_TEST_CONFIG
CustomPowerUnit | CPU_POWER_MGMT_TEST_CONFIG
Cx | CPU_POWER_MGMT_TEST_CONFIG
DisableProcHotOut | CPU_POWER_MGMT_TEST_CONFIG
DisableVrThermalAlert | CPU_POWER_MGMT_TEST_CONFIG
Eist | CPU_POWER_MGMT_TEST_CONFIG
EnableAllThermalFunctions | CPU_POWER_MGMT_TEST_CONFIG
EnergyEfficientPState | CPU_POWER_MGMT_TEST_CONFIG
EnergyEfficientTurbo | CPU_POWER_MGMT_TEST_CONFIG
Header | CPU_POWER_MGMT_TEST_CONFIG
PkgCStateDemotion | CPU_POWER_MGMT_TEST_CONFIG
PkgCStateLimit | CPU_POWER_MGMT_TEST_CONFIG
PkgCStateUnDemotion | CPU_POWER_MGMT_TEST_CONFIG
PmgCstCfgCtrlLock | CPU_POWER_MGMT_TEST_CONFIG
PpmIrmSetting | CPU_POWER_MGMT_TEST_CONFIG
ProcHotLock | CPU_POWER_MGMT_TEST_CONFIG
ProcHotResponse | CPU_POWER_MGMT_TEST_CONFIG
RaceToHalt | CPU_POWER_MGMT_TEST_CONFIG
Rsvd | CPU_POWER_MGMT_TEST_CONFIG
ThermalMonitor | CPU_POWER_MGMT_TEST_CONFIG
TimedMwait | CPU_POWER_MGMT_TEST_CONFIG
TStates | CPU_POWER_MGMT_TEST_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_POWER_MGMT_VR_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_VR_CONFIG Struct Reference

CPU Power Management VR Configuration Structure. More...

#include <CpuPowerMgmtVrConfig.h>

Collaboration diagram for CPU_POWER_MGMT_VR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AcousticNoiseMitigation: 1
Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled.
UINT32 | SendVrMbxCmd: 2
Deprecated.
UINT32 | EnableMinVoltageOverride: 1
Enable or disable Minimum Voltage override for minimum voltage runtime and minimum voltage C8. 0: Disabled 1: Enabled.
UINT32 | RfiMitigation: 1
Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1: Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
UINT32 | RsvdBits: 27
Reserved for future use.
UINT8 | PsysSlope
PCODE MMIO Mailbox: Platform Psys slope correction. 0: Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25.
UINT8 | PsysOffset
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. Deprecated.
UINT8 | FivrSpreadSpectrum
PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range. More...
UINT16 | FivrRfiFrequency
PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. More...
UINT16 | MinVoltageRuntime
PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 .Range 0 to 1999mV. 0: 0mV
UINT16 | MinVoltageC8
PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV
UINT16 | PsysOffset1
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348.
UINT32 | TdcTimeWindow1 [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. 1ms default
UINT8 | Irms [MAX_NUM_VRS]
PCODE MMIO Mailbox: Current root mean square. 0: Disable; 1: Enable.
UINT8 | FivrSpectrumEnable
Enable or Disable FIVR Spread Spectrum 0: Disable; 1: Enable.
UINT8 | DlvrSpreadSpectrumPercentage
PCODE MMIO Mailbox: Encoded DLVR SSC value. 0x0 = Disabled. u3.2 value from 0% - 7.75%.
UINT8 | DlvrRfiEnable
PCODE MMIO Mailbox: Enable/Disable RFI frequency hopping. 0: Disable. 1:Disable.
UINT8 | PreWake
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.Default Value = 0 micro ticks Defines the max pre-wake randomization time in micro ticks. Range is 0-255.
UINT8 | RampUp
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.Default Value = 0 micro ticks Defines the max ramp up randomization time in micro ticks. Range is 0-255.
UINT8 | RampDown
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.Default Value = 0 micro ticks Defines the max ramp down randomization time in micro ticks. Range is 0-255.
UINT16 | VccInAuxImonIccImax
PCODE MMIO Mailbox: VccIn Aux Imon IccMax. 0 - Auto Values are in 1/4 Amp increments. Range is 0-128A8.
UINT16 | VccInAuxImonSlope
PCODE MMIO Mailbox: VccInAuxImon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto
INT16 | VccInAuxImonOffset
PCODE MMIO Mailbox: VccinAuxImon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto
UINT16 | DlvrRfiFrequency
PCODE MMIO Mailbox: DLVR clock frequency in MHz. Default is 0x55A MHz.
UINT8 | PS1toPS0DynamicCutoffEnable [MAX_NUM_VRS]
Enable/Disable PS1 to PS0 Dynamic Cutoff; 0: Disable; 1: Enable.
UINT8 | PS2toPS1DynamicCutoffEnable [MAX_NUM_VRS]
Enable/Disable:PS2 to PS1 Dynamic Cutoff; 0: Disable; 1: Enable.
UINT16 | PS1toPS0MCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS1 to PS0 M Coef. This number is in M*100 units. Default: 100 Range: 0-4096.
INT16 | PS1toPS0CCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS1 to PS0 C Coef. This number is in C*100 units. Default: 2000 Range: 0-4096.
UINT16 | PS2toPS1MCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS2 to PS1 M Coef. This number is in M*100 units. Default: 100 Range: 0-4096.
INT16 | PS2toPS1CCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS2 to PS1 C Coef. This number is in C*100 units. Default: 500 Range: 0-4096.
UINT8 | VrPowerDeliveryDesign
This field is required to be non-zero on Desktop platforms. More...
UINT8 | VccInDemotionEnable [MAX_NUM_VRS]
Enable VCC Demotion. More...
UINT8 | VccInDemotionQuiescentPowerInMw [MAX_NUM_VRS]
User configured platform quiescent threshold in milli-watt when VCC Demotion is enabled with user configured threshold. More...
UINT8 | Rsvd5 [2]
Make next field 4-byte aligned.
UINT32 | VccInDemotionCapacitanceInUf [MAX_NUM_VRS]
User configured VR's quiescent power threshold in micro-farad when VCC Demotion is enabled with user configured threshold. More...
UINT8 | EnableVsysCritical
PCODE MMIO Mailbox: Enable/Disable Vsys Critical; 0: Disable; 1: Enable.
UINT8 | VsysFullScale
Set VSYS Critical [0x4A] Write to 0x4A to program Vsys Critical Threshold which is a linear fractional value of the Vsys input full scale voltage where minimun is 0 and maximum is 255. More...
UINT8 | VsysAssertionDeglitchMantissa
Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49] Provide 2 fields in BIOS Menu for Assertion/De-Assertion Deglitch: Mantissa and Exponent. More...
UINT16 | IccLimit [MAX_NUM_VRS]
PCODE VR Mailbox: Voltage Regulator Fast Vmode ICC Limit. More...
VR Settings

The VR related settings are sorted in an array where each index maps to the VR domain as defined below:

  • 0 = System Agent VR
  • 1 = IA Core VR
  • 2 = Ring Vr
  • 3 = GT VR
  • 4 = FIVR VR

The VR settings for a given domain must be populated in the appropriate index.

UINT16 | TdcCurrentLimit [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: 0 Amps
UINT16 | AcLoadline [MAX_NUM_VRS]
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU.
UINT16 | DcLoadline [MAX_NUM_VRS]
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU.
UINT16 | Psi1Threshold [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
UINT16 | Psi2Threshold [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
UINT16 | Psi3Threshold [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
INT16 | ImonOffset [MAX_NUM_VRS]
PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto
UINT16 | IccMax [MAX_NUM_VRS]
PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A. Default: 0 - Auto, no override
UINT16 | VrVoltageLimit [MAX_NUM_VRS]
PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
UINT16 | ImonSlope [MAX_NUM_VRS]
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto
UINT8 | Psi3Enable [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable.
UINT8 | Psi4Enable [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.
UINT8 | VrConfigEnable [MAX_NUM_VRS]
Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.
UINT8 | TdcEnable [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.
UINT8 | TdcTimeWindow [MAX_NUM_VRS]
UINT8 | TdcLock [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.
UINT8 | FastPkgCRampDisable [MAX_NUM_VRS]
Disable Fast Slew Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True.
UINT8 | SlowSlewRate [MAX_NUM_VRS]
Slew Rate configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16.

Detailed Description

CPU Power Management VR Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Updated Acoustic Noise Mitigation. Revision 3:
  • Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction Revision 4:
  • Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time Added Irms support. Revision 5:
  • Add RfiMitigation. Revision 6:
  • Add Dynamic Periodicity Alteration (DPA) tuning feature Revision 7:
  • Add VccIn Aux Imon feature Revision 8:
  • Deprecate SendVrMbxCmd Revision 9:
  • Added an option to Enable/Disable FIVR Spread Spectrum Revision 10:
  • Add DlvrRfiEnable, DlvrSpreadSpectrumPercentage and DlvrRfiFrequency for RFI control. Revision 11:
  • Added an option to Enable/Disable PS1 to PS0/PS2 to PS1 dynamic cutoff Revision 12:
  • Added an option for Vr Power Delivery design Revision 13:
  • Add VccInDemotionEnable, VccInDemotionQuiescentPowerInMw and VccInDemotionCapacitanceInUf Revision 14:
  • Add EnableVsysCritical, VsysFullScale,VsysCriticalThreshold, VsysAssertionDeglitchMantissa
  • VsysAssertionDeglitchExponent, VsysDeassertionDeglitchMantissa, VsysDeassertionDeglitchExponent Revision 15:
  • Add Voltage Regulator Fast Vmode ICC Limit Revision 16:
  • Modified IccMax range up to 512A

Definition at line 88 of file CpuPowerMgmtVrConfig.h.

Member Data Documentation

◆ FivrRfiFrequency

UINT16 CPU_POWER_MGMT_VR_CONFIG::FivrRfiFrequency

PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.

0: Auto Range varies based on XTAL clock:

  • 0-1918 (Up to 191.8HMz) for 24MHz clock.
  • 0-1535 (Up to 153.5MHz) for 19MHz clock.

Definition at line 114 of file CpuPowerMgmtVrConfig.h.

◆ FivrSpreadSpectrum

UINT8 CPU_POWER_MGMT_VR_CONFIG::FivrSpreadSpectrum

PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range.

1.5% Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.

Definition at line 105 of file CpuPowerMgmtVrConfig.h.

◆ IccLimit

UINT16 CPU_POWER_MGMT_VR_CONFIG::IccLimit[MAX_NUM_VRS]

PCODE VR Mailbox: Voltage Regulator Fast Vmode ICC Limit.

This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled. A value of 0 corresponds to feature disabled (no reactive protection). Default: 0 - Disable, no override

Definition at line 227 of file CpuPowerMgmtVrConfig.h.

◆ TdcTimeWindow

UINT8 CPU_POWER_MGMT_VR_CONFIG::TdcTimeWindow[MAX_NUM_VRS]
Deprecated:
. PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. 1ms default

Definition at line 141 of file CpuPowerMgmtVrConfig.h.

◆ VccInDemotionCapacitanceInUf

UINT32 CPU_POWER_MGMT_VR_CONFIG::VccInDemotionCapacitanceInUf[MAX_NUM_VRS]

User configured VR's quiescent power threshold in micro-farad when VCC Demotion is enabled with user configured threshold.

Range: 0-2000.

Definition at line 200 of file CpuPowerMgmtVrConfig.h.

◆ VccInDemotionEnable

UINT8 CPU_POWER_MGMT_VR_CONFIG::VccInDemotionEnable[MAX_NUM_VRS]

Enable VCC Demotion.

0: Disable; 1: Enable with default threshold; 2: Enable with user configured threshold.

Definition at line 187 of file CpuPowerMgmtVrConfig.h.

◆ VccInDemotionQuiescentPowerInMw

UINT8 CPU_POWER_MGMT_VR_CONFIG::VccInDemotionQuiescentPowerInMw[MAX_NUM_VRS]

User configured platform quiescent threshold in milli-watt when VCC Demotion is enabled with user configured threshold.

Range: 0-255.

Definition at line 193 of file CpuPowerMgmtVrConfig.h.

◆ VrPowerDeliveryDesign

UINT8 CPU_POWER_MGMT_VR_CONFIG::VrPowerDeliveryDesign

This field is required to be non-zero on Desktop platforms.

Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. This is required due to CPU socket compatibility across different board designs. Without this field populated, the system may experience VR OCP/OVP shutdowns, hangs, thermal and performance loss. 0 - Disable

Definition at line 179 of file CpuPowerMgmtVrConfig.h.

◆ VsysAssertionDeglitchMantissa

UINT8 CPU_POWER_MGMT_VR_CONFIG::VsysAssertionDeglitchMantissa

Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49] Provide 2 fields in BIOS Menu for Assertion/De-Assertion Deglitch: Mantissa and Exponent.

The format for Assertion/De-Assertion Deglitch: 0.002ms * Mantissa * 2^(Exponent).

Definition at line 216 of file CpuPowerMgmtVrConfig.h.

◆ VsysFullScale

UINT8 CPU_POWER_MGMT_VR_CONFIG::VsysFullScale

Set VSYS Critical [0x4A] Write to 0x4A to program Vsys Critical Threshold which is a linear fractional value of the Vsys input full scale voltage where minimun is 0 and maximum is 255.

Default 0 For example: Vsys_Crit (0x4A) = (Critical Threshold/Full Scale) * 0xFF

Definition at line 209 of file CpuPowerMgmtVrConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtVrConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_POWER_MGMT_VR_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_VR_CONFIG, including all inherited members.

AcLoadline | CPU_POWER_MGMT_VR_CONFIG
AcousticNoiseMitigation | CPU_POWER_MGMT_VR_CONFIG
DcLoadline | CPU_POWER_MGMT_VR_CONFIG
DlvrRfiEnable | CPU_POWER_MGMT_VR_CONFIG
DlvrRfiFrequency | CPU_POWER_MGMT_VR_CONFIG
DlvrSpreadSpectrumPercentage | CPU_POWER_MGMT_VR_CONFIG
EnableMinVoltageOverride | CPU_POWER_MGMT_VR_CONFIG
EnableVsysCritical | CPU_POWER_MGMT_VR_CONFIG
FastPkgCRampDisable | CPU_POWER_MGMT_VR_CONFIG
FivrRfiFrequency | CPU_POWER_MGMT_VR_CONFIG
FivrSpectrumEnable | CPU_POWER_MGMT_VR_CONFIG
FivrSpreadSpectrum | CPU_POWER_MGMT_VR_CONFIG
Header | CPU_POWER_MGMT_VR_CONFIG
IccLimit | CPU_POWER_MGMT_VR_CONFIG
IccMax | CPU_POWER_MGMT_VR_CONFIG
ImonOffset | CPU_POWER_MGMT_VR_CONFIG
ImonSlope | CPU_POWER_MGMT_VR_CONFIG
Irms | CPU_POWER_MGMT_VR_CONFIG
MinVoltageC8 | CPU_POWER_MGMT_VR_CONFIG
MinVoltageRuntime | CPU_POWER_MGMT_VR_CONFIG
PreWake | CPU_POWER_MGMT_VR_CONFIG
PS1toPS0CCoef | CPU_POWER_MGMT_VR_CONFIG
PS1toPS0DynamicCutoffEnable | CPU_POWER_MGMT_VR_CONFIG
PS1toPS0MCoef | CPU_POWER_MGMT_VR_CONFIG
PS2toPS1CCoef | CPU_POWER_MGMT_VR_CONFIG
PS2toPS1DynamicCutoffEnable | CPU_POWER_MGMT_VR_CONFIG
PS2toPS1MCoef | CPU_POWER_MGMT_VR_CONFIG
Psi1Threshold | CPU_POWER_MGMT_VR_CONFIG
Psi2Threshold | CPU_POWER_MGMT_VR_CONFIG
Psi3Enable | CPU_POWER_MGMT_VR_CONFIG
Psi3Threshold | CPU_POWER_MGMT_VR_CONFIG
Psi4Enable | CPU_POWER_MGMT_VR_CONFIG
PsysOffset | CPU_POWER_MGMT_VR_CONFIG
PsysOffset1 | CPU_POWER_MGMT_VR_CONFIG
PsysSlope | CPU_POWER_MGMT_VR_CONFIG
RampDown | CPU_POWER_MGMT_VR_CONFIG
RampUp | CPU_POWER_MGMT_VR_CONFIG
RfiMitigation | CPU_POWER_MGMT_VR_CONFIG
Rsvd5 | CPU_POWER_MGMT_VR_CONFIG
RsvdBits | CPU_POWER_MGMT_VR_CONFIG
SendVrMbxCmd | CPU_POWER_MGMT_VR_CONFIG
SlowSlewRate | CPU_POWER_MGMT_VR_CONFIG
TdcCurrentLimit | CPU_POWER_MGMT_VR_CONFIG
TdcEnable | CPU_POWER_MGMT_VR_CONFIG
TdcLock | CPU_POWER_MGMT_VR_CONFIG
TdcTimeWindow | CPU_POWER_MGMT_VR_CONFIG
TdcTimeWindow1 | CPU_POWER_MGMT_VR_CONFIG
VccInAuxImonIccImax | CPU_POWER_MGMT_VR_CONFIG
VccInAuxImonOffset | CPU_POWER_MGMT_VR_CONFIG
VccInAuxImonSlope | CPU_POWER_MGMT_VR_CONFIG
VccInDemotionCapacitanceInUf | CPU_POWER_MGMT_VR_CONFIG
VccInDemotionEnable | CPU_POWER_MGMT_VR_CONFIG
VccInDemotionQuiescentPowerInMw | CPU_POWER_MGMT_VR_CONFIG
VrConfigEnable | CPU_POWER_MGMT_VR_CONFIG
VrPowerDeliveryDesign | CPU_POWER_MGMT_VR_CONFIG
VrVoltageLimit | CPU_POWER_MGMT_VR_CONFIG
VsysAssertionDeglitchMantissa | CPU_POWER_MGMT_VR_CONFIG
VsysFullScale | CPU_POWER_MGMT_VR_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_SECURITY_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_SECURITY_PREMEM_CONFIG Struct Reference

CPU Security PreMemory Configuration Structure. More...

#include <CpuSecurityPreMemConfig.h>

Collaboration diagram for CPU_SECURITY_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PrmrrSize
PRMRR Size.Software Control: 0x0 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000, 256 MB: 0x10000000, 512 MB: 0x20000000.
UINT16 | BiosSize
Flash information for BIOS Guard: BIOS Size in KB.
UINT8 | Reserved [2]
Reserved for future use.
UINT32 | BiosGuard: 1
Enable or Disable BIOS Guard; 0: Disable; 1: Enable. More...
UINT32 | BiosGuardToolsInterface: 1
BIOS Guard Tools Interface; 0: Disable, 1:Enable.
UINT32 | EnableSgx: 1
Enable or Disable Software Guard Extensions; 0: Disable; 1: Enable. More...
UINT32 | Txt: 1
Enable or Disable Trusted Execution Technology; 0: Disable; 1: Enable. More...
UINT32 | SkipStopPbet: 1
(Test) Skip Stop PBET Timer; 0: Disable; 1: Enable.
UINT32 | EnableC6Dram: 1
(Test) This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature. More...
UINT32 | ResetAux: 1
(Test) Reset Auxiliary content, 0: Disabled, 1: Enabled
UINT32 | TxtAcheckRequest: 1
(Test) AcheckRequest 0: Disabled, 1: Enabled. When Enabled, it will call Acheck regardless of crashcode value
UINT32 | RsvdBits: 24
Reserved for future use.

Detailed Description

CPU Security PreMemory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Deprecated SGx

Definition at line 52 of file CpuSecurityPreMemConfig.h.

Member Data Documentation

◆ BiosGuard

UINT32 CPU_SECURITY_PREMEM_CONFIG::BiosGuard

Enable or Disable BIOS Guard; 0: Disable; 1: Enable.

  • This is an optional feature and can be opted out.
  • If this policy is set to Disabled, the policies in the BIOS_GUARD_CONFIG will be ignored.
  • If PeiBiosGuardLibNull is used, this policy will have no effect.

Definition at line 63 of file CpuSecurityPreMemConfig.h.

◆ EnableC6Dram

UINT32 CPU_SECURITY_PREMEM_CONFIG::EnableC6Dram

(Test) This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.

  • 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.
  • 1: Allocate PRMRR memory for C6DRAM power gating feature.

Definition at line 85 of file CpuSecurityPreMemConfig.h.

◆ EnableSgx

UINT32 CPU_SECURITY_PREMEM_CONFIG::EnableSgx

Enable or Disable Software Guard Extensions; 0: Disable; 1: Enable.

  • This is an optional feature and can be opted out.
  • If this policy is set to Disabled, the policies in the CPU_SGX_CONFIG will be ignored.
  • If BaseSoftwareGuardLibNull is used, this policy will have no effect.
    Deprecated:
    due to Non-POR feature.

Definition at line 71 of file CpuSecurityPreMemConfig.h.

◆ Txt

UINT32 CPU_SECURITY_PREMEM_CONFIG::Txt

Enable or Disable Trusted Execution Technology; 0: Disable; 1: Enable.

  • This is an optional feature and can be opted out.
  • If this policy is set to Disabled, the policies in the CPU_TXT_PREMEM_CONFIG will be ignored.
  • If PeiTxtLibNull is used, this policy will have no effect.

Definition at line 78 of file CpuSecurityPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuSecurityPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_SECURITY_PREMEM_CONFIG Member List

This is the complete list of members for CPU_SECURITY_PREMEM_CONFIG, including all inherited members.

BiosGuard | CPU_SECURITY_PREMEM_CONFIG
BiosGuardToolsInterface | CPU_SECURITY_PREMEM_CONFIG
BiosSize | CPU_SECURITY_PREMEM_CONFIG
EnableC6Dram | CPU_SECURITY_PREMEM_CONFIG
EnableSgx | CPU_SECURITY_PREMEM_CONFIG
Header | CPU_SECURITY_PREMEM_CONFIG
PrmrrSize | CPU_SECURITY_PREMEM_CONFIG
Reserved | CPU_SECURITY_PREMEM_CONFIG
ResetAux | CPU_SECURITY_PREMEM_CONFIG
RsvdBits | CPU_SECURITY_PREMEM_CONFIG
SkipStopPbet | CPU_SECURITY_PREMEM_CONFIG
Txt | CPU_SECURITY_PREMEM_CONFIG
TxtAcheckRequest | CPU_SECURITY_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_TEST_CONFIG Struct Reference

Public Attributes | List of all members
CPU_TEST_CONFIG Struct Reference

CPU Test Configuration Structure. More...

#include <CpuTestConfig.h>

Collaboration diagram for CPU_TEST_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | MlcStreamerPrefetcher: 1
Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.
UINT32 | MlcSpatialPrefetcher: 1
Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable.
UINT32 | MonitorMwaitEnable: 1
Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.
UINT32 | MachineCheckEnable: 1
Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.
UINT32 | ProcessorTraceOutputScheme: 1
Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.
UINT32 | ProcessorTraceEnable: 1
Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.
UINT32 | ThreeStrikeCounterDisable: 1
Disable Three strike counter; 0: FALSE; 1: TRUE.
UINT32 | RsvdBits: 25
Reserved for future use.
UINT32 | ProcessorTraceMemSize
Memory size per thread for Processor Trace. More...

Detailed Description

CPU Test Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Removed Voltage Optimization feature. Revision 3:
  • Add PostedInterruptCapability

Definition at line 54 of file CpuTestConfig.h.

Member Data Documentation

◆ ProcessorTraceMemSize

UINT32 CPU_TEST_CONFIG::ProcessorTraceMemSize

Memory size per thread for Processor Trace.

Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.

  • 0: Disable

Definition at line 69 of file CpuTestConfig.h.

The documentation for this struct was generated from the following file:
  • CpuTestConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_TEST_CONFIG Member List

This is the complete list of members for CPU_TEST_CONFIG, including all inherited members.

Header | CPU_TEST_CONFIG
MachineCheckEnable | CPU_TEST_CONFIG
MlcSpatialPrefetcher | CPU_TEST_CONFIG
MlcStreamerPrefetcher | CPU_TEST_CONFIG
MonitorMwaitEnable | CPU_TEST_CONFIG
ProcessorTraceEnable | CPU_TEST_CONFIG
ProcessorTraceMemSize | CPU_TEST_CONFIG
ProcessorTraceOutputScheme | CPU_TEST_CONFIG
RsvdBits | CPU_TEST_CONFIG
ThreeStrikeCounterDisable | CPU_TEST_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_TRACE_HUB_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_TRACE_HUB_PREMEM_CONFIG Struct Reference

CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version. More...

#include <TraceHubConfig.h>

Collaboration diagram for CPU_TRACE_HUB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.

Detailed Description

CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version.

Definition at line 112 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_TRACE_HUB_PREMEM_CONFIG Member List

This is the complete list of members for CPU_TRACE_HUB_PREMEM_CONFIG, including all inherited members.

Header | CPU_TRACE_HUB_PREMEM_CONFIG
TraceHub | CPU_TRACE_HUB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CPU_TXT_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_TXT_PREMEM_CONFIG Struct Reference

CPU TXT PreMemory Configuration Structure. More...

#include <CpuTxtConfig.h>

Collaboration diagram for CPU_TXT_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | SinitMemorySize
Size of SINIT module if installed in flash part. Zero otherwise.
UINT32 | TxtHeapMemorySize
Size of memory reserved for TXT Heap. This memory is used by MLE.
UINT32 | TxtDprMemorySize
Size of DPR protected memory reserved for Intel TXT component.
EFI_PHYSICAL_ADDRESS TxtDprMemoryBase
Base address of DPR protected memory reserved for Intel TXT component.
UINT64 | TxtLcpPdSize
Size of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
EFI_PHYSICAL_ADDRESS TxtLcpPdBase
Base address of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
EFI_PHYSICAL_ADDRESS ApStartupBase
Base address of TXT AP Startup code.
EFI_PHYSICAL_ADDRESS BiosAcmBase
Base address of BIOS ACM in flash part.
UINT32 | BiosAcmSize
Size of ACM Binary.
UINT32 | TgaSize
Size of Trusted Graphics Aperture if supported by chipset.

Detailed Description

CPU TXT PreMemory Configuration Structure.

Note
Optional. These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> Txt is disabled, or PeiTxtLibNull is used.

Revision 1:

  • Initial version.

Definition at line 51 of file CpuTxtConfig.h.

The documentation for this struct was generated from the following file:
  • CpuTxtConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

CPU_TXT_PREMEM_CONFIG Member List

This is the complete list of members for CPU_TXT_PREMEM_CONFIG, including all inherited members.

ApStartupBase | CPU_TXT_PREMEM_CONFIG
BiosAcmBase | CPU_TXT_PREMEM_CONFIG
BiosAcmSize | CPU_TXT_PREMEM_CONFIG
Header | CPU_TXT_PREMEM_CONFIG
SinitMemorySize | CPU_TXT_PREMEM_CONFIG
TgaSize | CPU_TXT_PREMEM_CONFIG
TxtDprMemoryBase | CPU_TXT_PREMEM_CONFIG
TxtDprMemorySize | CPU_TXT_PREMEM_CONFIG
TxtHeapMemorySize | CPU_TXT_PREMEM_CONFIG
TxtLcpPdBase | CPU_TXT_PREMEM_CONFIG
TxtLcpPdSize | CPU_TXT_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: DDI_CONFIGURATION Struct Reference

Public Attributes | List of all members
DDI_CONFIGURATION Struct Reference

This structure configures the Native GPIOs for DDI port per VBT settings. More...

#include <GraphicsConfig.h>

Public Attributes

UINT8 | DdiPortBConfig
The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, DdiPortEdp - Set DdiPortA to eDP, DdiPortMipiDsi - Set DdiPortA to MIPI DSI.
UINT8 | DdiPortAHpd
The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, DdiPortEdp - Set DdiPortB to eDP, DdiPortMipiDsi - Set DdiPortB to MIPI DSI.
UINT8 | DdiPortBHpd
The HPD setting of DDI Port A, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPortCHpd
The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD
UINT8 | DdiPort1Hpd
The HPD setting of DDI Port C, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPort2Hpd
The HPD setting of DDI Port 1, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPort3Hpd
The HPD setting of DDI Port 2, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPort4Hpd
The HPD setting of DDI Port 3, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPortADdc
The HPD setting of DDI Port 4, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPortBDdc
The DDC setting of DDI Port A, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPortCDdc
The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC
UINT8 | DdiPort1Ddc
The DDC setting of DDI Port C, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPort2Ddc
The DDC setting of DDI Port 1, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPort3Ddc
The DDC setting of DDI Port 2, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPort4Ddc
The DDC setting of DDI Port 3, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.

Detailed Description

This structure configures the Native GPIOs for DDI port per VBT settings.

Definition at line 69 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

DDI_CONFIGURATION Member List

This is the complete list of members for DDI_CONFIGURATION, including all inherited members.

DdiPort1Ddc | DDI_CONFIGURATION
DdiPort1Hpd | DDI_CONFIGURATION
DdiPort2Ddc | DDI_CONFIGURATION
DdiPort2Hpd | DDI_CONFIGURATION
DdiPort3Ddc | DDI_CONFIGURATION
DdiPort3Hpd | DDI_CONFIGURATION
DdiPort4Ddc | DDI_CONFIGURATION
DdiPort4Hpd | DDI_CONFIGURATION
DdiPortADdc | DDI_CONFIGURATION
DdiPortAHpd | DDI_CONFIGURATION
DdiPortBConfig | DDI_CONFIGURATION
DdiPortBDdc | DDI_CONFIGURATION
DdiPortBHpd | DDI_CONFIGURATION
DdiPortCDdc | DDI_CONFIGURATION
DdiPortCHpd | DDI_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: DMI_HW_WIDTH_CONTROL Struct Reference

Public Attributes | List of all members
DMI_HW_WIDTH_CONTROL Struct Reference

This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | DmiTsawEn: 1
DMI Thermal Sensor Autonomous Width Enable.
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values
UINT32 | RsvdBits0: 6
Reserved bits.
UINT32 | TS0TW: 3
Thermal Sensor 0 Target Width (DmiThermSensWidthx8)
UINT32 | TS1TW: 3
Thermal Sensor 1 Target Width (DmiThermSensWidthx4)
UINT32 | TS2TW: 3
Thermal Sensor 2 Target Width (DmiThermSensWidthx2)
UINT32 | TS3TW: 3
Thermal Sensor 3 Target Width (DmiThermSensWidthx1)
UINT32 | RsvdBits1: 12
Reserved bits.

Detailed Description

This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.

When the SuggestedSetting is enabled, the customized values are ignored. Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values

Definition at line 89 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

DMI_HW_WIDTH_CONTROL Member List

This is the complete list of members for DMI_HW_WIDTH_CONTROL, including all inherited members.

DmiTsawEn | DMI_HW_WIDTH_CONTROL
RsvdBits0 | DMI_HW_WIDTH_CONTROL
RsvdBits1 | DMI_HW_WIDTH_CONTROL
SuggestedSetting | DMI_HW_WIDTH_CONTROL
TS0TW | DMI_HW_WIDTH_CONTROL
TS1TW | DMI_HW_WIDTH_CONTROL
TS2TW | DMI_HW_WIDTH_CONTROL
TS3TW | DMI_HW_WIDTH_CONTROL
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_CPU Struct Reference

Public Attributes | List of all members
EFI_HOB_CPU Struct Reference

Describes processor information, such as address space and I/O space capabilities. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_CPU:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
UINT8 | SizeOfMemorySpace
Identifies the maximum physical memory addressability of the processor.
UINT8 | SizeOfIoSpace
Identifies the maximum physical I/O addressability of the processor.
UINT8 | Reserved [6]
This field will always be set to zero.

Detailed Description

Describes processor information, such as address space and I/O space capabilities.

Definition at line 438 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_CPU::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_CPU.

Definition at line 442 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_CPU Member List

This is the complete list of members for EFI_HOB_CPU, including all inherited members.

Header | EFI_HOB_CPU
Reserved | EFI_HOB_CPU
SizeOfIoSpace | EFI_HOB_CPU
SizeOfMemorySpace | EFI_HOB_CPU
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_FIRMWARE_VOLUME Struct Reference

Public Attributes | List of all members
EFI_HOB_FIRMWARE_VOLUME Struct Reference

Details the location of firmware volumes that contain firmware files. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_FIRMWARE_VOLUME:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
UINT64 Length
The length in bytes of the firmware volume.

Detailed Description

Details the location of firmware volumes that contain firmware files.

Definition at line 355 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_FIRMWARE_VOLUME::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_FV.

Definition at line 359 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_FIRMWARE_VOLUME2 Struct Reference

Public Attributes | List of all members
EFI_HOB_FIRMWARE_VOLUME2 Struct Reference

Details the location of a firmware volume that was extracted from a file within another firmware volume. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_FIRMWARE_VOLUME2:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
UINT64 Length
The length in bytes of the firmware volume.
EFI_GUID FvName
The name of the firmware volume.
EFI_GUID FileName
The name of the firmware file that contained this firmware volume.

Detailed Description

Details the location of a firmware volume that was extracted from a file within another firmware volume.

Definition at line 374 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_FIRMWARE_VOLUME2::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_FV2.

Definition at line 378 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_FIRMWARE_VOLUME2 Member List

This is the complete list of members for EFI_HOB_FIRMWARE_VOLUME2, including all inherited members.

BaseAddress | EFI_HOB_FIRMWARE_VOLUME2
FileName | EFI_HOB_FIRMWARE_VOLUME2
FvName | EFI_HOB_FIRMWARE_VOLUME2
Header | EFI_HOB_FIRMWARE_VOLUME2
Length | EFI_HOB_FIRMWARE_VOLUME2
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_FIRMWARE_VOLUME3 Struct Reference

Public Attributes | List of all members
EFI_HOB_FIRMWARE_VOLUME3 Struct Reference

Details the location of a firmware volume that was extracted from a file within another firmware volume. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_FIRMWARE_VOLUME3:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
UINT64 | Length
The length in bytes of the firmware volume.
UINT32 | AuthenticationStatus
The authentication status.
BOOLEAN | ExtractedFv
TRUE if the FV was extracted as a file within another firmware volume. More...
EFI_GUID FvName
The name of the firmware volume. More...
EFI_GUID FileName
The name of the firmware file that contained this firmware volume. More...

Detailed Description

Details the location of a firmware volume that was extracted from a file within another firmware volume.

Definition at line 401 of file PiHob.h.

Member Data Documentation

◆ ExtractedFv

BOOLEAN EFI_HOB_FIRMWARE_VOLUME3::ExtractedFv

TRUE if the FV was extracted as a file within another firmware volume.

FALSE otherwise.

Definition at line 422 of file PiHob.h.

◆ FileName

EFI_GUID EFI_HOB_FIRMWARE_VOLUME3::FileName

The name of the firmware file that contained this firmware volume.

Valid only if IsExtractedFv is TRUE.

Definition at line 432 of file PiHob.h.

◆ FvName

EFI_GUID EFI_HOB_FIRMWARE_VOLUME3::FvName

The name of the firmware volume.

Valid only if IsExtractedFv is TRUE.

Definition at line 427 of file PiHob.h.

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_FIRMWARE_VOLUME3::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_FV3.

Definition at line 405 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_FIRMWARE_VOLUME3 Member List

This is the complete list of members for EFI_HOB_FIRMWARE_VOLUME3, including all inherited members.

AuthenticationStatus | EFI_HOB_FIRMWARE_VOLUME3
BaseAddress | EFI_HOB_FIRMWARE_VOLUME3
ExtractedFv | EFI_HOB_FIRMWARE_VOLUME3
FileName | EFI_HOB_FIRMWARE_VOLUME3
FvName | EFI_HOB_FIRMWARE_VOLUME3
Header | EFI_HOB_FIRMWARE_VOLUME3
Length | EFI_HOB_FIRMWARE_VOLUME3
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_GENERIC_HEADER Struct Reference

Public Attributes | List of all members
EFI_HOB_GENERIC_HEADER Struct Reference

Describes the format and size of the data inside the HOB. More...

#include <PiHob.h>

Public Attributes

UINT16 | HobType
Identifies the HOB data structure type.
UINT16 | HobLength
The length in bytes of the HOB.
UINT32 | Reserved
This field must always be set to zero.

Detailed Description

Describes the format and size of the data inside the HOB.

All HOBs must contain this generic HOB header.

Definition at line 36 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_GENERIC_HEADER Member List

This is the complete list of members for EFI_HOB_GENERIC_HEADER, including all inherited members.

HobLength | EFI_HOB_GENERIC_HEADER
HobType | EFI_HOB_GENERIC_HEADER
Reserved | EFI_HOB_GENERIC_HEADER
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_GUID_TYPE Struct Reference

Public Attributes | List of all members
EFI_HOB_GUID_TYPE Struct Reference

Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_GUID_TYPE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_GUID Name
A GUID that defines the contents of this HOB.

Detailed Description

Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID.

Definition at line 338 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_GUID_TYPE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.

Definition at line 342 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_GUID_TYPE Member List

This is the complete list of members for EFI_HOB_GUID_TYPE, including all inherited members.

Header | EFI_HOB_GUID_TYPE
Name | EFI_HOB_GUID_TYPE
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_HANDOFF_INFO_TABLE Struct Reference

Public Attributes | List of all members
EFI_HOB_HANDOFF_INFO_TABLE Struct Reference

Contains general state information used by the HOB producer phase. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_HANDOFF_INFO_TABLE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
UINT32 | Version
The version number pertaining to the PHIT HOB definition. More...
EFI_BOOT_MODE | BootMode
The system boot mode as determined during the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiMemoryTop
The highest address location of memory that is allocated for use by the HOB producer phase. More...
EFI_PHYSICAL_ADDRESS EfiMemoryBottom
The lowest address location of memory that is allocated for use by the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop
The highest address location of free memory that is currently available for use by the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom
The lowest address location of free memory that is available for use by the HOB producer phase.
EFI_PHYSICAL_ADDRESS EfiEndOfHobList
The end of the HOB list.

Detailed Description

Contains general state information used by the HOB producer phase.

This HOB must be the first one in the HOB list.

Definition at line 61 of file PiHob.h.

Member Data Documentation

◆ EfiMemoryTop

EFI_PHYSICAL_ADDRESS EFI_HOB_HANDOFF_INFO_TABLE::EfiMemoryTop

The highest address location of memory that is allocated for use by the HOB producer phase.

This address must be 4-KB aligned to meet page restrictions of UEFI.

Definition at line 80 of file PiHob.h.

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_HANDOFF_INFO_TABLE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_HANDOFF.

Definition at line 65 of file PiHob.h.

◆ Version

UINT32 EFI_HOB_HANDOFF_INFO_TABLE::Version

The version number pertaining to the PHIT HOB definition.

This value is four bytes in length to provide an 8-byte aligned entry when it is combined with the 4-byte BootMode.

Definition at line 71 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_HANDOFF_INFO_TABLE Member List

This is the complete list of members for EFI_HOB_HANDOFF_INFO_TABLE, including all inherited members.

BootMode | EFI_HOB_HANDOFF_INFO_TABLE
EfiEndOfHobList | EFI_HOB_HANDOFF_INFO_TABLE
EfiFreeMemoryBottom | EFI_HOB_HANDOFF_INFO_TABLE
EfiFreeMemoryTop | EFI_HOB_HANDOFF_INFO_TABLE
EfiMemoryBottom | EFI_HOB_HANDOFF_INFO_TABLE
EfiMemoryTop | EFI_HOB_HANDOFF_INFO_TABLE
Header | EFI_HOB_HANDOFF_INFO_TABLE
Version | EFI_HOB_HANDOFF_INFO_TABLE
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION Struct Reference

Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION Struct Reference

Describes all memory ranges used during the HOB producer phase that exist outside the HOB list. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.

Detailed Description

Describes all memory ranges used during the HOB producer phase that exist outside the HOB list.

This HOB type describes how memory is used, not the physical attributes of memory.

Definition at line 145 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 149 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_MEMORY_ALLOCATION Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION, including all inherited members.

AllocDescriptor | EFI_HOB_MEMORY_ALLOCATION
Header | EFI_HOB_MEMORY_ALLOCATION
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_BSP_STORE Struct Reference

Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE Struct Reference

Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store"). More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_BSP_STORE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.

Detailed Description

Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store").

This HOB is valid for the Itanium processor family only register overflow store.

Definition at line 185 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION_BSP_STORE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 189 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_MEMORY_ALLOCATION_BSP_STORE Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION_BSP_STORE, including all inherited members.

AllocDescriptor | EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Header | EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_HEADER Struct Reference

Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION_HEADER Struct Reference

EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_HEADER:
[legend]

Public Attributes

EFI_GUID Name
A GUID that defines the memory allocation region's type and purpose, as well as other fields within the memory allocation HOB. More...
EFI_PHYSICAL_ADDRESS MemoryBaseAddress
The base address of memory allocated by this HOB. More...
UINT64 | MemoryLength
The length in bytes of memory allocated by this HOB.
EFI_MEMORY_TYPE | MemoryType
Defines the type of memory allocated by this HOB. More...
UINT8 | Reserved [4]
Padding for Itanium processor family.

Detailed Description

EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation.

The type field will be used for subsequent inclusion in the UEFI memory map.

Definition at line 105 of file PiHob.h.

Member Data Documentation

◆ MemoryBaseAddress

EFI_PHYSICAL_ADDRESS EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryBaseAddress

The base address of memory allocated by this HOB.

Type EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0 specification.

Definition at line 120 of file PiHob.h.

◆ MemoryType

EFI_MEMORY_TYPE EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryType

Defines the type of memory allocated by this HOB.

The memory type definition follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0 specification.

Definition at line 132 of file PiHob.h.

◆ Name

EFI_GUID EFI_HOB_MEMORY_ALLOCATION_HEADER::Name

A GUID that defines the memory allocation region's type and purpose, as well as other fields within the memory allocation HOB.

This GUID is used to define the additional data within the HOB that may be present for the memory allocation HOB. Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0 specification.

Definition at line 113 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_MEMORY_ALLOCATION_HEADER Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION_HEADER, including all inherited members.

MemoryBaseAddress | EFI_HOB_MEMORY_ALLOCATION_HEADER
MemoryLength | EFI_HOB_MEMORY_ALLOCATION_HEADER
MemoryType | EFI_HOB_MEMORY_ALLOCATION_HEADER
Name | EFI_HOB_MEMORY_ALLOCATION_HEADER
Reserved | EFI_HOB_MEMORY_ALLOCATION_HEADER
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_MODULE Struct Reference

Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION_MODULE Struct Reference

Defines the location and entry point of the HOB consumer phase. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_MODULE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.
EFI_GUID ModuleName
The GUID specifying the values of the firmware file system name that contains the HOB consumer phase component.
EFI_PHYSICAL_ADDRESS EntryPoint
The address of the memory-mapped firmware volume that contains the HOB consumer phase firmware file.

Detailed Description

Defines the location and entry point of the HOB consumer phase.

Definition at line 200 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION_MODULE::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 204 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_MEMORY_ALLOCATION_MODULE Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION_MODULE, including all inherited members.

EntryPoint | EFI_HOB_MEMORY_ALLOCATION_MODULE
Header | EFI_HOB_MEMORY_ALLOCATION_MODULE
MemoryAllocationHeader | EFI_HOB_MEMORY_ALLOCATION_MODULE
ModuleName | EFI_HOB_MEMORY_ALLOCATION_MODULE
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_ALLOCATION_STACK Struct Reference

Public Attributes | List of all members
EFI_HOB_MEMORY_ALLOCATION_STACK Struct Reference

Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_ALLOCATION_STACK:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logical memory allocation.

Detailed Description

Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing.

Definition at line 167 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_ALLOCATION_STACK::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.

Definition at line 171 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_MEMORY_ALLOCATION_STACK Member List

This is the complete list of members for EFI_HOB_MEMORY_ALLOCATION_STACK, including all inherited members.

AllocDescriptor | EFI_HOB_MEMORY_ALLOCATION_STACK
Header | EFI_HOB_MEMORY_ALLOCATION_STACK
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_MEMORY_POOL Struct Reference

Public Attributes | List of all members
EFI_HOB_MEMORY_POOL Struct Reference

Describes pool memory allocations. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_MEMORY_POOL:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...

Detailed Description

Describes pool memory allocations.

Definition at line 461 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_MEMORY_POOL::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_MEMORY_POOL.

Definition at line 465 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_MEMORY_POOL Member List

This is the complete list of members for EFI_HOB_MEMORY_POOL, including all inherited members.

Header EFI_HOB_MEMORY_POOL
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_RESOURCE_DESCRIPTOR Struct Reference

Public Attributes | List of all members
EFI_HOB_RESOURCE_DESCRIPTOR Struct Reference

Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_RESOURCE_DESCRIPTOR:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header. More...
EFI_GUID Owner
A GUID representing the owner of the resource. More...
EFI_RESOURCE_TYPE ResourceType
The resource type enumeration as defined by EFI_RESOURCE_TYPE.
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute
Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
EFI_PHYSICAL_ADDRESS PhysicalStart
The physical start address of the resource region.
UINT64 ResourceLength
The number of bytes of the resource region.

Detailed Description

Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase.

Definition at line 306 of file PiHob.h.

Member Data Documentation

◆ Header

EFI_HOB_GENERIC_HEADER EFI_HOB_RESOURCE_DESCRIPTOR::Header

The HOB generic header.

Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.

Definition at line 310 of file PiHob.h.

◆ Owner

EFI_GUID EFI_HOB_RESOURCE_DESCRIPTOR::Owner

A GUID representing the owner of the resource.

This GUID is used by HOB consumer phase components to correlate device ownership of a resource.

Definition at line 315 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_RESOURCE_DESCRIPTOR Member List

This is the complete list of members for EFI_HOB_RESOURCE_DESCRIPTOR, including all inherited members.

Header | EFI_HOB_RESOURCE_DESCRIPTOR
Owner | EFI_HOB_RESOURCE_DESCRIPTOR
PhysicalStart | EFI_HOB_RESOURCE_DESCRIPTOR
ResourceAttribute | EFI_HOB_RESOURCE_DESCRIPTOR
ResourceLength | EFI_HOB_RESOURCE_DESCRIPTOR
ResourceType | EFI_HOB_RESOURCE_DESCRIPTOR
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_HOB_UEFI_CAPSULE Struct Reference

Public Attributes | List of all members
EFI_HOB_UEFI_CAPSULE Struct Reference

Each UEFI capsule HOB details the location of a UEFI capsule. More...

#include <PiHob.h>

Collaboration diagram for EFI_HOB_UEFI_CAPSULE:
[legend]

Public Attributes

EFI_HOB_GENERIC_HEADER Header
The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of an UEFI capsule. More...

Detailed Description

Each UEFI capsule HOB details the location of a UEFI capsule.

It includes a base address and length which is based upon memory blocks with a EFI_CAPSULE_HEADER and the associated CapsuleImageSize-based payloads. These HOB's shall be created by the PEI PI firmware sometime after the UEFI UpdateCapsule service invocation with the CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE flag set in the EFI_CAPSULE_HEADER.

Definition at line 475 of file PiHob.h.

Member Data Documentation

◆ BaseAddress

EFI_PHYSICAL_ADDRESS EFI_HOB_UEFI_CAPSULE::BaseAddress

The physical memory-mapped base address of an UEFI capsule.

This value is set to point to the base of the contiguous memory of the UEFI capsule. The length of the contiguous memory in bytes.

Definition at line 486 of file PiHob.h.

The documentation for this struct was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_UEFI_CAPSULE Member List

This is the complete list of members for EFI_HOB_UEFI_CAPSULE, including all inherited members.

BaseAddress | EFI_HOB_UEFI_CAPSULE
Header | EFI_HOB_UEFI_CAPSULE
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_IP_ADDRESS Union Reference

List of all members
EFI_IP_ADDRESS Union Reference

16-byte buffer aligned on a 4-byte boundary. More...

#include <UefiBaseType.h>

Collaboration diagram for EFI_IP_ADDRESS:
[legend]

Detailed Description

16-byte buffer aligned on a 4-byte boundary.

An IPv4 or IPv6 internet protocol address.

Definition at line 103 of file UefiBaseType.h.

The documentation for this union was generated from the following file:
  • UefiBaseType.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_IP_ADDRESS Member List

This is the complete list of members for EFI_IP_ADDRESS, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_MAC_ADDRESS Struct Reference

List of all members
EFI_MAC_ADDRESS Struct Reference

32-byte buffer containing a network Media Access Control address. More...

#include <UefiBaseType.h>

Detailed Description

32-byte buffer containing a network Media Access Control address.

Definition at line 95 of file UefiBaseType.h.

The documentation for this struct was generated from the following file:
  • UefiBaseType.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_MAC_ADDRESS Member List

This is the complete list of members for EFI_MAC_ADDRESS, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_MMRAM_DESCRIPTOR Struct Reference

Public Attributes | List of all members
EFI_MMRAM_DESCRIPTOR Struct Reference

Structure describing a MMRAM region and its accessibility attributes. More...

#include <PiMultiPhase.h>

Public Attributes

EFI_PHYSICAL_ADDRESS PhysicalStart
Designates the physical address of the MMRAM in memory. More...
EFI_PHYSICAL_ADDRESS CpuStart
Designates the address of the MMRAM, as seen by software executing on the processors. More...
UINT64 | PhysicalSize
Describes the number of bytes in the MMRAM region.
UINT64 | RegionState
Describes the accessibility attributes of the MMRAM. More...

Detailed Description

Structure describing a MMRAM region and its accessibility attributes.

Definition at line 109 of file PiMultiPhase.h.

Member Data Documentation

◆ CpuStart

EFI_PHYSICAL_ADDRESS EFI_MMRAM_DESCRIPTOR::CpuStart

Designates the address of the MMRAM, as seen by software executing on the processors.

This address may or may not match PhysicalStart.

Definition at line 120 of file PiMultiPhase.h.

◆ PhysicalStart

EFI_PHYSICAL_ADDRESS EFI_MMRAM_DESCRIPTOR::PhysicalStart

Designates the physical address of the MMRAM in memory.

This view of memory is the same as seen by I/O-based agents, for example, but it may not be the address seen by the processors.

Definition at line 115 of file PiMultiPhase.h.

◆ RegionState

UINT64 EFI_MMRAM_DESCRIPTOR::RegionState

Describes the accessibility attributes of the MMRAM.

These attributes include the hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC initialization).

Definition at line 131 of file PiMultiPhase.h.

The documentation for this struct was generated from the following file:
  • PiMultiPhase.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_MMRAM_DESCRIPTOR Member List

This is the complete list of members for EFI_MMRAM_DESCRIPTOR, including all inherited members.

CpuStart | EFI_MMRAM_DESCRIPTOR
PhysicalSize | EFI_MMRAM_DESCRIPTOR
PhysicalStart | EFI_MMRAM_DESCRIPTOR
RegionState | EFI_MMRAM_DESCRIPTOR
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_PEI_HOB_POINTERS Union Reference

List of all members
EFI_PEI_HOB_POINTERS Union Reference

Union of all the possible HOB Types. More...

#include <PiHob.h>

Collaboration diagram for EFI_PEI_HOB_POINTERS:
[legend]

Detailed Description

Union of all the possible HOB Types.

Definition at line 493 of file PiHob.h.

The documentation for this union was generated from the following file:
  • PiHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_PEI_HOB_POINTERS Member List

This is the complete list of members for EFI_PEI_HOB_POINTERS, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EFI_TIME Struct Reference

List of all members
EFI_TIME Struct Reference

EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047. More...

#include <UefiBaseType.h>

Detailed Description

EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047.

Definition at line 67 of file UefiBaseType.h.

The documentation for this struct was generated from the following file:
  • UefiBaseType.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_TIME Member List

This is the complete list of members for EFI_TIME, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FIRMWARE_VERSION Struct Reference

List of all members
FIRMWARE_VERSION Struct Reference

Firmware Version Structure. More...

#include <FirmwareVersionInfoHob.h>

Detailed Description

Firmware Version Structure.

Definition at line 28 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

FIRMWARE_VERSION Member List

This is the complete list of members for FIRMWARE_VERSION, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FIRMWARE_VERSION_INFO Struct Reference

Public Attributes | List of all members
FIRMWARE_VERSION_INFO Struct Reference

Firmware Version Information Structure. More...

#include <FirmwareVersionInfoHob.h>

Collaboration diagram for FIRMWARE_VERSION_INFO:
[legend]

Public Attributes

UINT8 | ComponentNameIndex
Offset 0 Index of Component Name.
UINT8 | VersionStringIndex
Offset 1 Index of Version String.
FIRMWARE_VERSION Version
Offset 2-6 Firmware version.

Detailed Description

Firmware Version Information Structure.

Definition at line 38 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

FIRMWARE_VERSION_INFO Member List

This is the complete list of members for FIRMWARE_VERSION_INFO, including all inherited members.

ComponentNameIndex | FIRMWARE_VERSION_INFO
Version | FIRMWARE_VERSION_INFO
VersionStringIndex | FIRMWARE_VERSION_INFO
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FIRMWARE_VERSION_INFO_HOB Struct Reference

Public Attributes | List of all members
FIRMWARE_VERSION_INFO_HOB Struct Reference

Firmware Version Information HOB Structure. More...

#include <FirmwareVersionInfoHob.h>

Collaboration diagram for FIRMWARE_VERSION_INFO_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE Header
Offset 0-23 The header of FVI HOB.
SMBIOS_STRUCTURE SmbiosData
Offset 24-27 The SMBIOS header of FVI HOB.
UINT8 Count
Offset 28 Number of FVI elements included.

Detailed Description

Firmware Version Information HOB Structure.

Definition at line 58 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

FIRMWARE_VERSION_INFO_HOB Member List

This is the complete list of members for FIRMWARE_VERSION_INFO_HOB, including all inherited members.

Count | FIRMWARE_VERSION_INFO_HOB
Header | FIRMWARE_VERSION_INFO_HOB
SmbiosData | FIRMWARE_VERSION_INFO_HOB
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FIVR_EXT_RAIL_CONFIG Struct Reference

Public Attributes | List of all members
FIVR_EXT_RAIL_CONFIG Struct Reference

Structure for V1p05/Vnn VR rail configuration. More...

#include <FivrConfig.h>

Public Attributes

UINT32 | EnabledStates: 6
Mask to enable the usage of external VR rail in specific S0ix or Sx states Use values from FIVR_RAIL_SX_STATE The default is FivrRailDisabled.
UINT32 | Voltage: 11
VR rail voltage value that will be used in S0i2/S0i3 states. More...
UINT32 | IccMax: 8
UINT32 | RsvdBits1: 7
UINT32 Alignement.
UINT32 | CtrlRampTmr: 8
This register holds the control hold off values to be used when changing the rail control for external bypass value in us.
UINT32 | SupportedVoltageStates: 4
Mask to set the supported configuration in VR rail. More...
UINT32 | IccMaximum: 16
VR rail Icc Maximum Value Granularity of this setting is 1mA and maximal possible value is 500mA The default is 0mA .
UINT32 | RsvdBits2: 4
UINT32 Alignment.

Detailed Description

Structure for V1p05/Vnn VR rail configuration.

Definition at line 73 of file FivrConfig.h.

Member Data Documentation

◆ IccMax

UINT32 FIVR_EXT_RAIL_CONFIG::IccMax
Deprecated:
THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD VR rail Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA The default is 0mA .

Definition at line 94 of file FivrConfig.h.

◆ SupportedVoltageStates

UINT32 FIVR_EXT_RAIL_CONFIG::SupportedVoltageStates

Mask to set the supported configuration in VR rail.

Use values from FIVR_RAIL_SUPPORTED_VOLTAGE

Definition at line 109 of file FivrConfig.h.

◆ Voltage

UINT32 FIVR_EXT_RAIL_CONFIG::Voltage

VR rail voltage value that will be used in S0i2/S0i3 states.

This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) The default for Vnn is set to 420 - 1050 mV.

Definition at line 86 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

FIVR_EXT_RAIL_CONFIG Member List

This is the complete list of members for FIVR_EXT_RAIL_CONFIG, including all inherited members.

CtrlRampTmr | FIVR_EXT_RAIL_CONFIG
EnabledStates | FIVR_EXT_RAIL_CONFIG
IccMax | FIVR_EXT_RAIL_CONFIG
IccMaximum | FIVR_EXT_RAIL_CONFIG
RsvdBits1 | FIVR_EXT_RAIL_CONFIG
RsvdBits2 | FIVR_EXT_RAIL_CONFIG
SupportedVoltageStates | FIVR_EXT_RAIL_CONFIG
Voltage | FIVR_EXT_RAIL_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FIVR_VCCIN_AUX_CONFIG Struct Reference

Public Attributes | List of all members
FIVR_VCCIN_AUX_CONFIG Struct Reference

Structure for VCCIN_AUX voltage rail configuration. More...

#include <FivrConfig.h>

Public Attributes

UINT8 | LowToHighCurModeVolTranTime
Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage. More...
UINT8 | RetToHighCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage. More...
UINT8 | RetToLowCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage. More...
UINT32 | OffToHighCurModeVolTranTime: 11
Transition time in microseconds from Off (0V) to High Current Mode Voltage. More...

Detailed Description

Structure for VCCIN_AUX voltage rail configuration.

Definition at line 128 of file FivrConfig.h.

Member Data Documentation

◆ LowToHighCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::LowToHighCurModeVolTranTime

Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. The default is 0xC .

Definition at line 137 of file FivrConfig.h.

◆ OffToHighCurModeVolTranTime

UINT32 FIVR_VCCIN_AUX_CONFIG::OffToHighCurModeVolTranTime

Transition time in microseconds from Off (0V) to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from 0V to the high current mode voltage. This field has 1us resolution. 0 = Transition to 0V is disabled Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on in all S0 & Sx power states after initial start up on G3 exit The default is 0x96 .

Definition at line 169 of file FivrConfig.h.

◆ RetToHighCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::RetToHighCurModeVolTranTime

Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention voltage. The default is 0x36 .

Definition at line 147 of file FivrConfig.h.

◆ RetToLowCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::RetToLowCurModeVolTranTime

Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention voltage. The default is 0x2B .

Definition at line 157 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

FIVR_VCCIN_AUX_CONFIG Member List

This is the complete list of members for FIVR_VCCIN_AUX_CONFIG, including all inherited members.

LowToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
OffToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
RetToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
RetToLowCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FSP_ERROR_INFO_HOB Struct Reference

Public Attributes | List of all members
FSP_ERROR_INFO_HOB Struct Reference

FSP Error Information Block. More...

#include <FspErrorInfo.h>

Collaboration diagram for FSP_ERROR_INFO_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE GuidHob
GUID HOB header.
EFI_STATUS_CODE_TYPE | Type
ReportStatusCode () type identifier.
EFI_STATUS_CODE_VALUE | Value
ReportStatusCode () value.
UINT32 | Instance
ReportStatusCode () Instance number.
EFI_GUID CallerId
Optional GUID which may be used to identify which internal component of the FSP was executing at the time of the error.
EFI_GUID ErrorType
GUID identifying the nature of the fatal error.
UINT32 | Status
EFI_STATUS code describing the error encountered.

Detailed Description

FSP Error Information Block.

Definition at line 60 of file FspErrorInfo.h.

The documentation for this struct was generated from the following file:
  • FspErrorInfo.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

FSP_ERROR_INFO_HOB Member List

This is the complete list of members for FSP_ERROR_INFO_HOB, including all inherited members.

CallerId | FSP_ERROR_INFO_HOB
ErrorType | FSP_ERROR_INFO_HOB
GuidHob | FSP_ERROR_INFO_HOB
Instance | FSP_ERROR_INFO_HOB
Status | FSP_ERROR_INFO_HOB
Type | FSP_ERROR_INFO_HOB
Value | FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FSPM_ARCH_CONFIG_PPI Struct Reference

List of all members
FSPM_ARCH_CONFIG_PPI Struct Reference

This PPI provides FSP-M Arch Config PPI. More...

#include <FspmArchConfigPpi.h>

Detailed Description

This PPI provides FSP-M Arch Config PPI.

Definition at line 32 of file FspmArchConfigPpi.h.

The documentation for this struct was generated from the following file:
  • FspmArchConfigPpi.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

FSPM_ARCH_CONFIG_PPI Member List

This is the complete list of members for FSPM_ARCH_CONFIG_PPI, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GBE_CONFIG Struct Reference

Public Attributes | List of all members
GBE_CONFIG Struct Reference

PCH intergrated GBE controller configuration settings. More...

#include <GbeConfig.h>

Collaboration diagram for GBE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
Determines if enable PCH internal GBE, 0: Disable; 1: Enable. More...
UINT32 | LtrEnable: 1
0: Disable; 1: Enable LTR capabilty of PCH internal LAN.
UINT32 | RsvdBits0: 30
Reserved bits.

Detailed Description

PCH intergrated GBE controller configuration settings.

Definition at line 46 of file GbeConfig.h.

Member Data Documentation

◆ Enable

UINT32 GBE_CONFIG::Enable

Determines if enable PCH internal GBE, 0: Disable; 1: Enable.

When Enable is changed (from disabled to enabled or from enabled to disabled), it needs to set LAN Disable regsiter, which might be locked by FDSWL register. So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.

Definition at line 54 of file GbeConfig.h.

The documentation for this struct was generated from the following file:
  • GbeConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

GBE_CONFIG Member List

This is the complete list of members for GBE_CONFIG, including all inherited members.

Enable | GBE_CONFIG
Header | GBE_CONFIG
LtrEnable | GBE_CONFIG
RsvdBits0 | GBE_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GNA_CONFIG Struct Reference

Public Attributes | List of all members
GNA_CONFIG Struct Reference

GNA config block for configuring GNA. More...

#include <GnaConfig.h>

Collaboration diagram for GNA_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | GnaEnable: 1
Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported. More...
UINT32 | RsvdBits0: 31
Offset 28:1 :Reserved for future use.

Detailed Description

GNA config block for configuring GNA.

Revision 1:

  • Initial version.

Definition at line 45 of file GnaConfig.h.

Member Data Documentation

◆ GnaEnable

UINT32 GNA_CONFIG::GnaEnable

Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported.

If FALSE, all other policies in this config block will be ignored. 1=TRUE; 0=FALSE.

Definition at line 54 of file GnaConfig.h.

The documentation for this struct was generated from the following file:
  • GnaConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

GNA_CONFIG Member List

This is the complete list of members for GNA_CONFIG, including all inherited members.

GnaEnable | GNA_CONFIG
Header | GNA_CONFIG
RsvdBits0 | GNA_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GPIO_CONFIG Struct Reference

Public Attributes | List of all members
GPIO_CONFIG Struct Reference

GPIO configuration structure used for pin programming. More...

#include <GpioConfig.h>

Public Attributes

UINT32 | PadMode: 5
Pad Mode Pad can be set as GPIO or one of its native functions. More...
UINT32 | HostSoftPadOwn: 2
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode. More...
UINT32 | Direction: 6
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. More...
UINT32 | OutputState: 2
Output State Set Pad output value. More...
UINT32 | InterruptConfig: 9
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). More...
UINT32 | PowerConfig: 8
GPIO Power Configuration. More...
UINT32 | ElectricalConfig: 9
GPIO Electrical Configuration This setting controls pads termination and voltage tolerance. More...
UINT32 | LockConfig: 4
GPIO Lock Configuration This setting controls pads lock. More...
UINT32 | OtherSettings: 2
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
UINT32 | RsvdBits: 17
Reserved bits for future extension.

Detailed Description

GPIO configuration structure used for pin programming.

Structure contains fields that can be used to configure pad.

Definition at line 55 of file GpioConfig.h.

Member Data Documentation

◆ Direction

UINT32 GPIO_CONFIG::Direction

GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.

Refer to definition of GPIO_DIRECTION for supported settings.

Definition at line 76 of file GpioConfig.h.

◆ ElectricalConfig

UINT32 GPIO_CONFIG::ElectricalConfig

GPIO Electrical Configuration This setting controls pads termination and voltage tolerance.

Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.

Definition at line 102 of file GpioConfig.h.

◆ HostSoftPadOwn

UINT32 GPIO_CONFIG::HostSoftPadOwn

Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.

Refer to definition of GPIO_HOSTSW_OWN.

Definition at line 70 of file GpioConfig.h.

◆ InterruptConfig

UINT32 GPIO_CONFIG::InterruptConfig

GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).

This setting is applicable only if GPIO is in GpioMode with input enabled. Refer to definition of GPIO_INT_CONFIG for supported settings.

Definition at line 90 of file GpioConfig.h.

◆ LockConfig

UINT32 GPIO_CONFIG::LockConfig

GPIO Lock Configuration This setting controls pads lock.

Refer to definition of GPIO_LOCK_CONFIG for supported settings.

Definition at line 108 of file GpioConfig.h.

◆ OutputState

UINT32 GPIO_CONFIG::OutputState

Output State Set Pad output value.

Refer to definition of GPIO_OUTPUT_STATE for supported settings. This setting takes place when output is enabled.

Definition at line 83 of file GpioConfig.h.

◆ PadMode

UINT32 GPIO_CONFIG::PadMode

Pad Mode Pad can be set as GPIO or one of its native functions.

When in native mode setting Direction (except Inversion), OutputState, InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. Refer to definition of GPIO_PAD_MODE. Refer to EDS for each native mode according to the pad.

Definition at line 64 of file GpioConfig.h.

◆ PowerConfig

UINT32 GPIO_CONFIG::PowerConfig

GPIO Power Configuration.

This setting controls Pad Reset Configuration. Refer to definition of GPIO_RESET_CONFIG for supported settings.

Definition at line 96 of file GpioConfig.h.

The documentation for this struct was generated from the following file:
  • GpioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

GPIO_CONFIG Member List

This is the complete list of members for GPIO_CONFIG, including all inherited members.

Direction | GPIO_CONFIG
ElectricalConfig | GPIO_CONFIG
HostSoftPadOwn | GPIO_CONFIG
InterruptConfig | GPIO_CONFIG
LockConfig | GPIO_CONFIG
OtherSettings | GPIO_CONFIG
OutputState | GPIO_CONFIG
PadMode | GPIO_CONFIG
PowerConfig | GPIO_CONFIG
RsvdBits | GPIO_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GRAPHICS_DXE_CONFIG Struct Reference

Public Attributes | List of all members
GRAPHICS_DXE_CONFIG Struct Reference

This configuration block is to configure IGD related variables used in DXE. More...

#include <GraphicsConfig.h>

Collaboration diagram for GRAPHICS_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27: Config Block Header.
UINT32 | Size
Offset 28 - 31: This field gives the size of the GOP VBT Data buffer.
EFI_PHYSICAL_ADDRESS VbtAddress
Offset 32 - 39: This field points to the GOP VBT data buffer.
UINT8 | PlatformConfig
Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, 1=Platform is not S0ix Capable, 2=Force Platform is S0ix Capable for All SKUs)
UINT8 | AlsEnable
Offset 41: Ambient Light Sensor Enable: 0=Disable, 2=Enable.
UINT8 | BacklightControlSupport
Offset 42: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
UINT8 | IgdBootType
Offset 43: IGD Boot Type CMOS option: 0=Default, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2.
UINT32 | IuerStatusVal
Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
CHAR16 | GopVersion [0x10]
Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code.
UINT8 | IgdPanelType
Offset 80: IGD Panel Type CMOS option
0=Default, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1
6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS
14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS.
UINT8 | IgdPanelScaling
Offset 81: IGD Panel Scaling: 0=AUTO, 1=OFF, 6=Force scaling.
UINT8 | IgdBlcConfig
Offset 82: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
UINT8 | IgdDvmtMemSize
Offset 83: More...
UINT8 | GfxTurboIMON
Offset 84: IMON Current Value: 14=Minimal, 31=Maximum
UINT8 | Reserved [3]
Offset 85: Reserved for DWORD alignment.
UINT16 | BCLM [MAX_BCLM_ENTRIES]
Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.

Detailed Description

This configuration block is to configure IGD related variables used in DXE.

If Intel Gfx Device is not supported or disabled, all policies will be ignored. The data elements should be initialized by a Platform Module.
Revision 1:

  • Initial version. Revision 2:
  • Removed IgdDvmtMemSize.

Definition at line 229 of file GraphicsConfig.h.

Member Data Documentation

◆ IgdDvmtMemSize

UINT8 GRAPHICS_DXE_CONFIG::IgdDvmtMemSize

Offset 83:

Deprecated:
IGD DVMT Memory Size: 1=128MB, 2=256MB, 3=MAX

Definition at line 248 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

GRAPHICS_DXE_CONFIG Member List

This is the complete list of members for GRAPHICS_DXE_CONFIG, including all inherited members.

AlsEnable | GRAPHICS_DXE_CONFIG
BacklightControlSupport | GRAPHICS_DXE_CONFIG
BCLM | GRAPHICS_DXE_CONFIG
GfxTurboIMON | GRAPHICS_DXE_CONFIG
GopVersion | GRAPHICS_DXE_CONFIG
Header | GRAPHICS_DXE_CONFIG
IgdBlcConfig | GRAPHICS_DXE_CONFIG
IgdBootType | GRAPHICS_DXE_CONFIG
IgdDvmtMemSize | GRAPHICS_DXE_CONFIG
IgdPanelScaling | GRAPHICS_DXE_CONFIG
IgdPanelType | GRAPHICS_DXE_CONFIG
IuerStatusVal | GRAPHICS_DXE_CONFIG
PlatformConfig | GRAPHICS_DXE_CONFIG
Reserved | GRAPHICS_DXE_CONFIG
Size | GRAPHICS_DXE_CONFIG
VbtAddress | GRAPHICS_DXE_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GRAPHICS_PEI_CONFIG Struct Reference

Public Attributes | List of all members
GRAPHICS_PEI_CONFIG Struct Reference

This configuration block is to configure IGD related variables used in PostMem PEI. More...

#include <GraphicsConfig.h>

Collaboration diagram for GRAPHICS_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | RenderStandby
Offset 28 :(Test) This field is used to enable or disable RC6 (Render Standby): 0=FALSE, 1=TRUE
UINT8 | PmSupport
Offset 29 :(Test) Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, 1=TRUE
UINT16 | CdClock
Offset 30 CdClock Frequency select
0xFF = Auto. More...
UINT8 | PeiGraphicsPeimInit
Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable.
UINT8 | CdynmaxClampEnable
Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable, 0- Disable.
UINT16 | GtFreqMax
Offset 34 : (Test) Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is 0xFF
UINT8 | DisableTurboGt
Offset 36 : This policy is used to enable/disable DisableTurboGt 0- Disable, 1- Enable.
UINT8 | SkipCdClockInit
Offset 37 : SKip full CD clock initialization. 0- Disable, 1- Enable.
UINT8 | RC1pFreqEnable
Offset 38 : This policy is used to enable/disable RC1p Frequency. 0- Disable, 1- Enable.
UINT8 | PavpEnable
Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, 1=TRUE
VOID * LogoPtr
Offset 40 Address of Intel Gfx PEIM Logo to be displayed.
UINT32 | LogoSize
Offset 44 Intel Gfx PEIM Logo Size.
VOID * GraphicsConfigPtr
Offset 48 Address of the Graphics Configuration Table.
VOID * BltBufferAddress
Offset 52 Address of Blt buffer for PEIM Logo use.
UINT32 | BltBufferSize
Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
UINT8 | ProgramGtChickenBits
Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
UINT8 | SkipFspGop
Offset 61 This policy is used to skip PEIM GOP in FSP.0- Use FSP provided GOP driver, 1- Skip FSP provided GOP driver.
UINT8 | Rsvd1 [2]
Offset 62 Reserved for 4 bytes alignment.
UINT32 | LogoPixelHeight
Offset 64 Address of LogoPixelHeight for PEIM Logo use.
UINT32 | LogoPixelWidth
Offset 68 Address of LogoPixelWidth for PEIM Logo use.
UINT32 | VerticalResolution
Offset 72 Address of VerticalResolution for PEIM Logo use.
UINT32 | HorizontalResolution
Offset 76 Address of HorizontalResolution for PEIM Logo use.

Detailed Description

This configuration block is to configure IGD related variables used in PostMem PEI.

If Intel Gfx Device is not supported, all policies can be ignored. Revision 1:

  • Initial version. Revision 2:
  • Removed DfdRestoreEnable. Revision 3:
  • Removed DdiConfiguration. Revision 4:
  • Added new CdClock frequency Revision 5:
  • Added GT Chicket bits Revision 6:
  • Added LogoPixelHeight and LogoPixelWidth Revision 7:
  • Added SkipFspGop Revision 8:
  • Added VerticalResolution and HorizontalResolution

Definition at line 187 of file GraphicsConfig.h.

Member Data Documentation

◆ CdClock

UINT16 GRAPHICS_PEI_CONFIG::CdClock

Offset 30 CdClock Frequency select
0xFF = Auto.

Max CdClock freq based on Reference Clk
0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz

Definition at line 198 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

GRAPHICS_PEI_CONFIG Member List

This is the complete list of members for GRAPHICS_PEI_CONFIG, including all inherited members.

BltBufferAddress | GRAPHICS_PEI_CONFIG
BltBufferSize | GRAPHICS_PEI_CONFIG
CdClock | GRAPHICS_PEI_CONFIG
CdynmaxClampEnable | GRAPHICS_PEI_CONFIG
DisableTurboGt | GRAPHICS_PEI_CONFIG
GraphicsConfigPtr | GRAPHICS_PEI_CONFIG
GtFreqMax | GRAPHICS_PEI_CONFIG
Header | GRAPHICS_PEI_CONFIG
HorizontalResolution | GRAPHICS_PEI_CONFIG
LogoPixelHeight | GRAPHICS_PEI_CONFIG
LogoPixelWidth | GRAPHICS_PEI_CONFIG
LogoPtr | GRAPHICS_PEI_CONFIG
LogoSize | GRAPHICS_PEI_CONFIG
PavpEnable | GRAPHICS_PEI_CONFIG
PeiGraphicsPeimInit | GRAPHICS_PEI_CONFIG
PmSupport | GRAPHICS_PEI_CONFIG
ProgramGtChickenBits | GRAPHICS_PEI_CONFIG
RC1pFreqEnable | GRAPHICS_PEI_CONFIG
RenderStandby | GRAPHICS_PEI_CONFIG
Rsvd1 | GRAPHICS_PEI_CONFIG
SkipCdClockInit | GRAPHICS_PEI_CONFIG
SkipFspGop | GRAPHICS_PEI_CONFIG
VerticalResolution | GRAPHICS_PEI_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GRAPHICS_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
GRAPHICS_PEI_PREMEM_CONFIG Struct Reference

This Configuration block is to configure GT related PreMem data/variables. More...

#include <GraphicsConfig.h>

Collaboration diagram for GRAPHICS_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | PrimaryDisplay
Offset 28 Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3=AUTO, 4=Switchable Graphics
When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX.
UINT8 | InternalGraphics
Offset 29 Intel Gfx Support. More...
UINT16 | IgdDvmt50PreAlloc
Offset 30 Pre-allocated memory for iGFX
0 = 0MB,1 or 247 = 32MB,
2 = 64MB,
240 = 4MB, 241 = 8MB,
242 = 12MB, 243 = 16MB,
244 = 20MB, 245 = 24MB,
246 = 28MB, 248 = 36MB,
249 = 40MB, 250 = 44MB,
251 = 48MB, 252 = 52MB,
253 = 56MB, 254 = 60MB,
Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation
UINT8 | PanelPowerEnable
Offset 32 :(Test) Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, 1=TRUE
UINT8 | ApertureSize
Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, 1=256MB, 3=512MB, 7=1024MB, 15=2048MB.
UINT8 | GtPsmiSupport
Offset 34 :PSMI support On/Off: 0=FALSE, 1=TRUE.
UINT8 | PsmiRegionSize
Offset 35 :Psmi region size: 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1056MB.
UINT8 | DismSize
Offset 36 :DiSM Size for 2LM Sku: 0=0GB, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB.
UINT8 | DfdRestoreEnable
Offset 37 :(Deprecated) Display memory map programming for DFD Restore 0- Disable, 1- Enable.
UINT16 | GttSize
Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, 3=8MB
UINT32 | GttMmAdr
Offset 40 Temp Address of System Agent GTTMMADR: Default is 0xAF000000
UINT32 | GmAdr
Offset 44 Obsolete not to be used, use GmAdr64.
DDI_CONFIGURATION DdiConfiguration
Offset 48 DDI configuration, need to match with VBT settings.
UINT8 | GtClosEnable
Offset 50 Gt ClOS.
UINT8 | Rsvd0 [7]
Offset 51 Reserved for 4 bytes of alignment.
UINT64 | GmAdr64
Offset 58 Temp Address of System Agent GMADR: Default is 0xB0000000
UINT16 | DeltaT12PowerCycleDelay
Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, 0xFFFF - Auto calculate to max 500 ms< >
UINT8 | DisplayAudioLink
Offset 68 Enable/Disable Display Audio Links in Pre-OS.0- Disable, 1- Enable.
UINT8 | OemT12DelayOverride
Offset 69 :Oem T12 Delay Override Disable< >,Enable-Enable T12 Time.
UINT8 | Rsvd2 [4]
Offset 70 Reserved for 4 bytes of alignment.

Detailed Description

This Configuration block is to configure GT related PreMem data/variables.

Revision 1:

  • Initial version. Revision 2:
  • Added DfdRestoreEnable. Revision 3:
  • Added DdiConfiguration. Revision 4:
  • Added GmAdr64 and made GmAdr obselete Revision 5:
  • Added DeltaT12PowerCycleDelay Revision 6:
  • Added DisplayAudioLink Revision 7:
  • Added OemT12DelayOverride

Definition at line 105 of file GraphicsConfig.h.

Member Data Documentation

◆ InternalGraphics

UINT8 GRAPHICS_PEI_PREMEM_CONFIG::InternalGraphics

Offset 29 Intel Gfx Support.

It controls enabling/disabling iGfx device. When AUTO mode selected, iGFX will be turned off when external graphics detected. If FALSE, all other polices can be ignored. 2 = AUTO; 0 = FALSE; 1 = TRUE.

Definition at line 122 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

GRAPHICS_PEI_PREMEM_CONFIG Member List

This is the complete list of members for GRAPHICS_PEI_PREMEM_CONFIG, including all inherited members.

ApertureSize | GRAPHICS_PEI_PREMEM_CONFIG
DdiConfiguration | GRAPHICS_PEI_PREMEM_CONFIG
DeltaT12PowerCycleDelay | GRAPHICS_PEI_PREMEM_CONFIG
DfdRestoreEnable | GRAPHICS_PEI_PREMEM_CONFIG
DismSize | GRAPHICS_PEI_PREMEM_CONFIG
DisplayAudioLink | GRAPHICS_PEI_PREMEM_CONFIG
GmAdr | GRAPHICS_PEI_PREMEM_CONFIG
GmAdr64 | GRAPHICS_PEI_PREMEM_CONFIG
GtClosEnable | GRAPHICS_PEI_PREMEM_CONFIG
GtPsmiSupport | GRAPHICS_PEI_PREMEM_CONFIG
GttMmAdr | GRAPHICS_PEI_PREMEM_CONFIG
GttSize | GRAPHICS_PEI_PREMEM_CONFIG
Header | GRAPHICS_PEI_PREMEM_CONFIG
IgdDvmt50PreAlloc | GRAPHICS_PEI_PREMEM_CONFIG
InternalGraphics | GRAPHICS_PEI_PREMEM_CONFIG
OemT12DelayOverride | GRAPHICS_PEI_PREMEM_CONFIG
PanelPowerEnable | GRAPHICS_PEI_PREMEM_CONFIG
PrimaryDisplay | GRAPHICS_PEI_PREMEM_CONFIG
PsmiRegionSize | GRAPHICS_PEI_PREMEM_CONFIG
Rsvd0 | GRAPHICS_PEI_PREMEM_CONFIG
Rsvd2 | GRAPHICS_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GUID Struct Reference

List of all members
GUID Struct Reference

128 bit buffer containing a unique identifier value. More...

#include <Base.h>

Detailed Description

128 bit buffer containing a unique identifier value.

Unless otherwise specified, aligned on a 64 bit boundary.

Definition at line 222 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

GUID Member List

This is the complete list of members for GUID, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_DMIC Struct Reference

Public Attributes | List of all members
HDA_LINK_DMIC Struct Reference

HD Audio DMIC Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 | Enable: 1
HDA DMIC interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.
UINT32 | DmicClockSelect: 2
DMIC link clock select: 0: Both, 1: ClkA, 2: ClkB; default is "Both".
HDA_DMIC_PIN_MUX | PinMux
Pin mux configuration.

Detailed Description

HD Audio DMIC Interface Policies.

Definition at line 115 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDA_LINK_DMIC Member List

This is the complete list of members for HDA_LINK_DMIC, including all inherited members.

DmicClockSelect | HDA_LINK_DMIC
Enable | HDA_LINK_DMIC
PinMux | HDA_LINK_DMIC
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_HDA Struct Reference

Public Attributes | List of all members
HDA_LINK_HDA Struct Reference

HD Audio Link Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 | Enable: 1
HDA interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.
UINT8 | SdiEnable [PCH_MAX_HDA_SDI]
HDA SDI signal enable. When enabled related SDI pins will be switched to appropriate native mode: 0: Disable; 1: Enable.
UINT8 | Reserved [(4 -(PCH_MAX_HDA_SDI % 4)) % 4]
Padding for SDI enable table.

Detailed Description

HD Audio Link Policies.

Definition at line 105 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDA_LINK_HDA Member List

This is the complete list of members for HDA_LINK_HDA, including all inherited members.

Enable | HDA_LINK_HDA
Reserved | HDA_LINK_HDA
SdiEnable | HDA_LINK_HDA
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_SNDW Struct Reference

Public Attributes | List of all members
HDA_LINK_SNDW Struct Reference

HD Audio SNDW Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 Enable: 1
HDA SNDW interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.

Detailed Description

HD Audio SNDW Interface Policies.

Definition at line 133 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDA_LINK_SNDW Member List

This is the complete list of members for HDA_LINK_SNDW, including all inherited members.

Enable HDA_LINK_SNDW
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_LINK_SSP Struct Reference

Public Attributes | List of all members
HDA_LINK_SSP Struct Reference

HD Audio SSP Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 Enable: 1
HDA SSP interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.

Detailed Description

HD Audio SSP Interface Policies.

Definition at line 125 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDA_LINK_SSP Member List

This is the complete list of members for HDA_LINK_SSP, including all inherited members.

Enable HDA_LINK_SSP
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDA_VERB_TABLE_HEADER Struct Reference

Public Attributes | List of all members
HDA_VERB_TABLE_HEADER Struct Reference

Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands. More...

#include <HdAudioConfig.h>

Public Attributes

UINT16 | VendorId
Codec Vendor ID.
UINT16 | DeviceId
Codec Device ID.
UINT8 | RevisionId
Revision ID of the codec. 0xFF matches any revision.
UINT8 | SdiNum
SDI number, 0xFF matches any SDI.
UINT16 | DataDwords
Number of data DWORDs following the header.

Detailed Description

Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands.

Definition at line 72 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDA_VERB_TABLE_HEADER Member List

This is the complete list of members for HDA_VERB_TABLE_HEADER, including all inherited members.

DataDwords | HDA_VERB_TABLE_HEADER
DeviceId | HDA_VERB_TABLE_HEADER
RevisionId | HDA_VERB_TABLE_HEADER
SdiNum | HDA_VERB_TABLE_HEADER
VendorId | HDA_VERB_TABLE_HEADER
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDAUDIO_CONFIG Struct Reference

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HDAUDIO_CONFIG Struct Reference

This structure contains the policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Pme: 1
Azalia wake-on-ring, 0: Disable; 1: Enable.
UINT32 | CodecSxWakeCapability: 1
Capability to detect wake initiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Enable.
UINT32 | HdAudioLinkFrequency: 4
HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz.
UINT32 | RsvdBits0: 26
Reserved bits 0.
UINT8 | VerbTableEntryNum
Number of the verb table entry defined in VerbTablePtr. More...
UINT8 | Rsvd0 [3]
Reserved bytes, align to multiple 4.
UINT32 | VerbTablePtr
Pointer to a verb table array. More...

Detailed Description

This structure contains the policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version.

Definition at line 146 of file HdAudioConfig.h.

Member Data Documentation

◆ VerbTableEntryNum

UINT8 HDAUDIO_CONFIG::VerbTableEntryNum

Number of the verb table entry defined in VerbTablePtr.

Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.

Definition at line 156 of file HdAudioConfig.h.

◆ VerbTablePtr

UINT32 HDAUDIO_CONFIG::VerbTablePtr

Pointer to a verb table array.

This pointer points to 32bits address, and is only eligible and consumed in post mem phase. Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks. The prototype of this is: HDAUDIO_VERB_TABLE **VerbTablePtr;

Definition at line 165 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDAUDIO_CONFIG Member List

This is the complete list of members for HDAUDIO_CONFIG, including all inherited members.

CodecSxWakeCapability | HDAUDIO_CONFIG
HdAudioLinkFrequency | HDAUDIO_CONFIG
Header | HDAUDIO_CONFIG
Pme | HDAUDIO_CONFIG
Rsvd0 | HDAUDIO_CONFIG
RsvdBits0 | HDAUDIO_CONFIG
VerbTableEntryNum | HDAUDIO_CONFIG
VerbTablePtr | HDAUDIO_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDAUDIO_DXE_CONFIG Struct Reference

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HDAUDIO_DXE_CONFIG Struct Reference

This structure contains the DXE policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
HDAUDIO_SNDW_CONFIG | SndwConfig [PCH_MAX_HDA_SNDW_LINK_NUM]
SNDW configuration for exposed via SNDW ACPI tables:
UINT32 | DspFeatureMask
Bitmask of supported DSP features: [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation Default is zero.

Detailed Description

This structure contains the DXE policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version. Revision 2:
  • Add IoControlEnabled Revision 3:
  • Remove IoControlEnabled

Definition at line 244 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDAUDIO_DXE_CONFIG Member List

This is the complete list of members for HDAUDIO_DXE_CONFIG, including all inherited members.

DspFeatureMask | HDAUDIO_DXE_CONFIG
Header | HDAUDIO_DXE_CONFIG
SndwConfig | HDAUDIO_DXE_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HDAUDIO_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
HDAUDIO_PREMEM_CONFIG Struct Reference

This structure contains the premem policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
Intel HD Audio (Azalia) enablement: 0: Disable, 1: Enable
UINT32 | DspEnable: 1
DSP enablement: 0: Disable; 1: Enable
UINT32 | VcType: 1
Virtual Channel Type Select: 0: VC0, 1: VC1.
UINT32 | DspUaaCompliance: 1
Universal Audio Architecture compliance for DSP enabled system: 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)
UINT32 | IDispLinkFrequency: 4
iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz
UINT32 | IDispLinkTmode: 3
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T
UINT32 | IDispCodecDisconnect: 1
iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not enumerable
UINT32 | PowerGatingSupported: 1
Power Gating supported: 0: Not supported, 1: Supported.
UINT32 | RsvdBits: 19
Reserved bits 0.
HDA_LINK_HDA AudioLinkHda
Audio Link Mode configuration bitmask. More...
HDA_LINK_DMIC | AudioLinkDmic [PCH_MAX_HDA_DMIC_LINK_NUM]
DMIC link enablement: 0: Disable; 1: Enable. More...
HDA_LINK_SSP | AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM]
I2S/SSP link enablement: 0: Disable; 1: Enable. More...
HDA_LINK_SNDW | AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM]
SoundWire link enablement: 0: Disable; 1: Enable. More...
UINT16 | ResetWaitTimer
(Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
UINT8 | Rsvd0 [2]
Reserved bytes, align to multiple 4.
UINT32 | SubSystemIds
Value for SID and SVID. If its set to 0 then default value is used.

Detailed Description

This structure contains the premem policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version. Revision 2:
  • Add DmicClockSelect Revision 3:
  • Add AudioFpgaSocVer Revision 4:
  • Remove AudioFpgaSocVer

Definition at line 180 of file HdAudioConfig.h.

Member Data Documentation

◆ AudioLinkDmic

HDA_LINK_DMIC HDAUDIO_PREMEM_CONFIG::AudioLinkDmic[PCH_MAX_HDA_DMIC_LINK_NUM]

DMIC link enablement: 0: Disable; 1: Enable.

DMIC0 LKF: Muxed with SNDW2/SNDW4.

Definition at line 207 of file HdAudioConfig.h.

◆ AudioLinkHda

HDA_LINK_HDA HDAUDIO_PREMEM_CONFIG::AudioLinkHda

Audio Link Mode configuration bitmask.

Allows to configure enablement of the following interfaces: HDA-Link, DMIC, SSP, SoundWire. HDA-Link enablement: 0: Disable; 1: Enable.

Definition at line 202 of file HdAudioConfig.h.

◆ AudioLinkSndw

HDA_LINK_SNDW HDAUDIO_PREMEM_CONFIG::AudioLinkSndw[PCH_MAX_HDA_SNDW_LINK_NUM]

SoundWire link enablement: 0: Disable; 1: Enable.

SNDW2 LKF: Muxed with DMIC0/DMIC1. SNDW3 LKF: Muxed with DMIC1. SNDW4 LKF: Muxed with DMIC0.

Definition at line 221 of file HdAudioConfig.h.

◆ AudioLinkSsp

HDA_LINK_SSP HDAUDIO_PREMEM_CONFIG::AudioLinkSsp[PCH_MAX_HDA_SSP_LINK_NUM]

I2S/SSP link enablement: 0: Disable; 1: Enable.

SSP0/1 LKF: Muxed with HDA.

Note
Since the I2S/SSP2 pin set contains pads which are also used for CNVi purpose, enabling AudioLinkSsp2 is exclusive with CNVi is present.

Definition at line 214 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HDAUDIO_PREMEM_CONFIG Member List

This is the complete list of members for HDAUDIO_PREMEM_CONFIG, including all inherited members.

AudioLinkDmic | HDAUDIO_PREMEM_CONFIG
AudioLinkHda | HDAUDIO_PREMEM_CONFIG
AudioLinkSndw | HDAUDIO_PREMEM_CONFIG
AudioLinkSsp | HDAUDIO_PREMEM_CONFIG
DspEnable | HDAUDIO_PREMEM_CONFIG
DspUaaCompliance | HDAUDIO_PREMEM_CONFIG
Enable | HDAUDIO_PREMEM_CONFIG
Header | HDAUDIO_PREMEM_CONFIG
IDispCodecDisconnect | HDAUDIO_PREMEM_CONFIG
IDispLinkFrequency | HDAUDIO_PREMEM_CONFIG
IDispLinkTmode | HDAUDIO_PREMEM_CONFIG
PowerGatingSupported | HDAUDIO_PREMEM_CONFIG
ResetWaitTimer | HDAUDIO_PREMEM_CONFIG
Rsvd0 | HDAUDIO_PREMEM_CONFIG
RsvdBits | HDAUDIO_PREMEM_CONFIG
SubSystemIds | HDAUDIO_PREMEM_CONFIG
VcType | HDAUDIO_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HSIO_PARAMETERS Struct Reference

Public Attributes | List of all members
HSIO_PARAMETERS Struct Reference

This structure describes USB3 Port N configuration parameters. More...

#include <Usb3HsioConfig.h>

Public Attributes

UINT8 | HsioTxDownscaleAmp
USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) HSIO_TX_DWORD8[21:16] Default = 00h
UINT8 | HsioTxDeEmph
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) HSIO_TX_DWORD5[21:16] Default = 29h (approximately -3.5dB De-Emphasis)
UINT8 | HsioCtrlAdaptOffsetCfg
Signed Magnatude number added to the CTLE code. More...
UINT8 | HsioFilterSelN
LFPS filter select for n (filter_sel_n_2_0) HSIO_RX_DWORD51 [29:27] 0h:1.6ns 1h:2.4ns 2h:3.2ns 3h:4.0ns 4h:4.8ns 5h:5.6ns 6h:6.4ns Default = 0h
UINT8 | HsioFilterSelP
LFPS filter select for p (filter_sel_p_2_0) HSIO_RX_DWORD51 [26:24] 0h:1.6ns 1h:2.4ns 2h:3.2ns 3h:4.0ns 4h:4.8ns 5h:5.6ns 6h:6.4ns Default = 0h
UINT8 | HsioOlfpsCfgPullUpDwnRes
Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) HSIO_RX_DWORD51 [2:0] 000 Prohibited 001 45K 010 Prohibited 011 31K 100 36K 101 36K 110 36K 111 36K Default = 3h
UINT8 | HsioTxDeEmphEnable
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable.
UINT8 | HsioTxDownscaleAmpEnable
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable.
UINT8 | HsioCtrlAdaptOffsetCfgEnable
Enable the write to Signed Magnatude number added to the CTLE code, 0: Disable; 1: Enable.
UINT8 | HsioFilterSelNEnable
Enable the write to LFPS filter select for n, 0: Disable; 1: Enable.
UINT8 | HsioFilterSelPEnable
Enable the write to LFPS filter select for p, 0: Disable; 1: Enable.
UINT8 | HsioOlfpsCfgPullUpDwnResEnable
Enable the write to olfpscfgpullupdwnres, 0: Disable; 1: Enable.
UINT8 | HsioTxRate3UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale) HSIO_TX_DWORD9[6:0] Default = 4Ch
UINT8 | HsioTxRate2UniqTran
USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale) HSIO_TX_DWORD9[14:8] Default = 4Ch
UINT8 | HsioTxRate1UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale) HSIO_TX_DWORD9[22:16] Default = 4Ch
UINT8 | HsioTxRate0UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale) HSIO_TX_DWORD9[30:24] Default = 4Ch
UINT8 | HsioTxRate3UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, 0: Disable; 1: Enable.
UINT8 | HsioTxRate2UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, 0: Disable; 1: Enable.
UINT8 | HsioTxRate1UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, 0: Disable; 1: Enable.
UINT8 | HsioTxRate0UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, 0: Disable; 1: Enable.

Detailed Description

This structure describes USB3 Port N configuration parameters.

Definition at line 49 of file Usb3HsioConfig.h.

Member Data Documentation

◆ HsioCtrlAdaptOffsetCfg

UINT8 HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfg

Signed Magnatude number added to the CTLE code.

(ctle_adapt_offset_cfg_4_0) HSIO_RX_DWORD25 [20:16] Ex: -1 – 1_0001. +1: 0_0001 Default = 0h

Definition at line 68 of file Usb3HsioConfig.h.

The documentation for this struct was generated from the following file:
  • Usb3HsioConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HSIO_PARAMETERS Member List

This is the complete list of members for HSIO_PARAMETERS, including all inherited members.

HsioCtrlAdaptOffsetCfg | HSIO_PARAMETERS
HsioCtrlAdaptOffsetCfgEnable | HSIO_PARAMETERS
HsioFilterSelN | HSIO_PARAMETERS
HsioFilterSelNEnable | HSIO_PARAMETERS
HsioFilterSelP | HSIO_PARAMETERS
HsioFilterSelPEnable | HSIO_PARAMETERS
HsioOlfpsCfgPullUpDwnRes | HSIO_PARAMETERS
HsioOlfpsCfgPullUpDwnResEnable | HSIO_PARAMETERS
HsioTxDeEmph | HSIO_PARAMETERS
HsioTxDeEmphEnable | HSIO_PARAMETERS
HsioTxDownscaleAmp | HSIO_PARAMETERS
HsioTxDownscaleAmpEnable | HSIO_PARAMETERS
HsioTxRate0UniqTran | HSIO_PARAMETERS
HsioTxRate0UniqTranEnable | HSIO_PARAMETERS
HsioTxRate1UniqTran | HSIO_PARAMETERS
HsioTxRate1UniqTranEnable | HSIO_PARAMETERS
HsioTxRate2UniqTran | HSIO_PARAMETERS
HsioTxRate2UniqTranEnable | HSIO_PARAMETERS
HsioTxRate3UniqTran | HSIO_PARAMETERS
HsioTxRate3UniqTranEnable | HSIO_PARAMETERS
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HYBRID_GRAPHICS_CONFIG Struct Reference

Public Attributes | List of all members
HYBRID_GRAPHICS_CONFIG Struct Reference

This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port. More...

#include <HybridGraphicsConfig.h>

Collaboration diagram for HYBRID_GRAPHICS_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio
Offset 28 RTD3 GPIOs used for PCIe.
UINT8 | RootPortIndex
Offset 52 Root Port Index number used for HG.
UINT8 | HgMode
Offset 53 HgMode: 0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=PEG.
UINT16 | HgSubSystemId
Offset 54 Hybrid Graphics Subsystem ID: 2212
UINT16 | HgDelayAfterPwrEn
Offset 56 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum, 300=300 microseconds
UINT16 | HgDelayAfterHoldReset
Offset 58 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum, 100=100 microseconds
CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio
Offset 60 RTD3 GPIOs used for PCIe.
CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio
Offset 84 RTD3 GPIOs used for PCIe.
CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio
Offset 108 RTD3 GPIOs used for PCIe.
UINT8 | HgSupport
Offset 132 HgSupport on specific port.
UINT8 | Rsvd0 [3]
Offset 133 Reserved bytes for future use.

Detailed Description

This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port.

Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3. Revision 1:

  • Initial version. Revision 2:
  • Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics Revision 3:
  • Removed HgSlot Policy: As there is no selection between PEG or PCH Slot for Hybrid Graphics Revision 4:
  • Added HgSupport Policy: To support HG support on other PEG ports

Definition at line 83 of file HybridGraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • HybridGraphicsConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HYBRID_GRAPHICS_CONFIG Member List

This is the complete list of members for HYBRID_GRAPHICS_CONFIG, including all inherited members.

CpuPcie0Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
CpuPcie1Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
CpuPcie2Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
CpuPcie3Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
Header | HYBRID_GRAPHICS_CONFIG
HgDelayAfterHoldReset | HYBRID_GRAPHICS_CONFIG
HgDelayAfterPwrEn | HYBRID_GRAPHICS_CONFIG
HgMode | HYBRID_GRAPHICS_CONFIG
HgSubSystemId | HYBRID_GRAPHICS_CONFIG
HgSupport | HYBRID_GRAPHICS_CONFIG
RootPortIndex | HYBRID_GRAPHICS_CONFIG
Rsvd0 | HYBRID_GRAPHICS_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HYBRID_STORAGE_CONFIG Struct Reference

Public Attributes | List of all members
HYBRID_STORAGE_CONFIG Struct Reference

The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device. More...

#include <HybridStorageConfig.h>

Collaboration diagram for HYBRID_STORAGE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 HybridStorageMode
Hybrid Storage Mode 0: Disable, 1: Enable Dynamic Configuration.

Detailed Description

The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device.

Revision 1:

  • Init version Revision 2:
  • Added support for cpu attached hybrid storage

Definition at line 54 of file HybridStorageConfig.h.

The documentation for this struct was generated from the following file:
  • HybridStorageConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

HYBRID_STORAGE_CONFIG Member List

This is the complete list of members for HYBRID_STORAGE_CONFIG, including all inherited members.

Header | HYBRID_STORAGE_CONFIG
HybridStorageMode | HYBRID_STORAGE_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: I2C_PIN_MUX Struct Reference

Public Attributes | List of all members
I2C_PIN_MUX Struct Reference

I2C signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Sda
SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*.
UINT32 | Scl
SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*.

Detailed Description

I2C signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h for supported settings on a given platform

Definition at line 228 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

I2C_PIN_MUX Member List

This is the complete list of members for I2C_PIN_MUX, including all inherited members.

Scl | I2C_PIN_MUX
Sda | I2C_PIN_MUX
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IEH_CONFIG Struct Reference

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IEH_CONFIG Struct Reference

The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler. More...

#include <IehConfig.h>

Collaboration diagram for IEH_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Mode: 1
IEH mode 0: Bypass Mode; 1: Enable.
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler.

Definition at line 53 of file IehConfig.h.

The documentation for this struct was generated from the following file:
  • IehConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

IEH_CONFIG Member List

This is the complete list of members for IEH_CONFIG, including all inherited members.

Header | IEH_CONFIG
Mode | IEH_CONFIG
RsvdBits0 | IEH_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IOM_AUX_ORI_PAD_CONFIG Struct Reference

Public Attributes | List of all members
IOM_AUX_ORI_PAD_CONFIG Struct Reference

The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT32 | GpioPullN
GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
UINT32 | GpioPullP
GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.

Detailed Description

The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.

Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer. IOM needs know Pull-Up and Pull-Down pin for Bias control

Definition at line 55 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

IOM_AUX_ORI_PAD_CONFIG Member List

This is the complete list of members for IOM_AUX_ORI_PAD_CONFIG, including all inherited members.

GpioPullN | IOM_AUX_ORI_PAD_CONFIG
GpioPullP | IOM_AUX_ORI_PAD_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IOM_INTERFACE_CONFIG Struct Reference

Public Attributes | List of all members
IOM_INTERFACE_CONFIG Struct Reference

The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT32 | VccSt
IOM VCCST request. (Not equal to actual VCCST value)
UINT32 | UsbOverride
IOM to override USB connection.
UINT32 | D3ColdEnable
Enable/disable D3 Cold support in TCSS.
UINT32 | D3HotEnable
Enable/disable D3 Hot support in TCSS.

Detailed Description

The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.

Definition at line 64 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

IOM_INTERFACE_CONFIG Member List

This is the complete list of members for IOM_INTERFACE_CONFIG, including all inherited members.

D3ColdEnable | IOM_INTERFACE_CONFIG
D3HotEnable | IOM_INTERFACE_CONFIG
UsbOverride | IOM_INTERFACE_CONFIG
VccSt | IOM_INTERFACE_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IPU_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
IPU_PREMEM_CONFIG Struct Reference

IPU PreMem configuration
Revision 1: More...

#include <IpuPreMemConfig.h>

Collaboration diagram for IPU_PREMEM_CONFIG:
[legend]

Public Attributes

UINT8 | IpuEnable
Config Block Header. More...
UINT8 | IpuImrConfiguration
Deprecate.
UINT8 | ImguClkOutEn [GPIO_IMGUCLK_NUMBER_OF_PINS]
It enable the IMGU CLKOUT. More...
UINT8 | LaneUsed [MAX_CSI_PORT]
Indicate laneUsed of each CSI port 0: Not configured; 1: x1; 2:x2; 3:x3; 4:x4.
UINT8 | CsiSpeed [MAX_CSI_PORT]
Indicate speed of each CSI port 0: Sensor default; 1: <416Mbps; 2:<1.5Gbps; 3:<2Gbps; 4:<2.5Gbps; 5:<4Gbps; 6>4Gbps.

Detailed Description

IPU PreMem configuration
Revision 1:

  • Initial version. Revision 2:
  • Change Bit-wise to Byte-wise. Revision 3:
  • Add LaneUsed and Speed of each Port configuration for Mcd10 support. Revision 4:
  • Change GPIO_IMGUCLK_NUMBER_OF_PINS to 6 Revision 5:
  • Deprecate IpuImrConfiguration.

Definition at line 70 of file IpuPreMemConfig.h.

Member Data Documentation

◆ ImguClkOutEn

UINT8 IPU_PREMEM_CONFIG::ImguClkOutEn[GPIO_IMGUCLK_NUMBER_OF_PINS]

It enable the IMGU CLKOUT.

TRUE FALSE

Definition at line 88 of file IpuPreMemConfig.h.

◆ IpuEnable

UINT8 IPU_PREMEM_CONFIG::IpuEnable

Config Block Header.

(Test) It enables the SA IPU Device if supported and not fused off. If FALSE, all other policies in this config block will be ignored. 1=TRUE; 0=FALSE.

Definition at line 78 of file IpuPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • IpuPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

IPU_PREMEM_CONFIG Member List

This is the complete list of members for IPU_PREMEM_CONFIG, including all inherited members.

CsiSpeed | IPU_PREMEM_CONFIG
ImguClkOutEn | IPU_PREMEM_CONFIG
IpuEnable | IPU_PREMEM_CONFIG
IpuImrConfiguration | IPU_PREMEM_CONFIG
LaneUsed | IPU_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IPv4_ADDRESS Struct Reference

List of all members
IPv4_ADDRESS Struct Reference

4-byte buffer. More...

#include <Base.h>

Detailed Description

4-byte buffer.

An IPv4 internet protocol address.

Definition at line 232 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

IPv4_ADDRESS Member List

This is the complete list of members for IPv4_ADDRESS, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IPv6_ADDRESS Struct Reference

List of all members
IPv6_ADDRESS Struct Reference

16-byte buffer. More...

#include <Base.h>

Detailed Description

16-byte buffer.

An IPv6 internet protocol address.

Definition at line 239 of file Base.h.

The documentation for this struct was generated from the following file:
  • Base.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

IPv6_ADDRESS Member List

This is the complete list of members for IPv6_ADDRESS, including all inherited members.

Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_CONFIG Struct Reference

Public Attributes | List of all members
ISH_CONFIG Struct Reference

The ISH_CONFIG block describes Integrated Sensor Hub device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PdtUnlock: 1
ISH PDT Unlock Msg: 0: False 1: True.
UINT32 | MsiInterrupt: 1
ISH MSI Interrupts: 0: False 1: True.
UINT32 | RsvdBits0: 30
Reserved Bits.

Detailed Description

The ISH_CONFIG block describes Integrated Sensor Hub device.

Definition at line 137 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_CONFIG Member List

This is the complete list of members for ISH_CONFIG, including all inherited members.

Header | ISH_CONFIG
MsiInterrupt | ISH_CONFIG
PdtUnlock | ISH_CONFIG
RsvdBits0 | ISH_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_GP Struct Reference

Public Attributes | List of all members
ISH_GP Struct Reference

Struct contains GPIO pins assigned and signal settings of GP. More...

#include <IshConfig.h>

Collaboration diagram for ISH_GP:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH GP GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of GP.

Definition at line 128 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_GP Member List

This is the complete list of members for ISH_GP, including all inherited members.

Enable | ISH_GP
RsvdBits0 | ISH_GP
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_GPIO_CONFIG Struct Reference

Public Attributes | List of all members
ISH_GPIO_CONFIG Struct Reference

ISH GPIO settings. More...

#include <IshConfig.h>

Public Attributes

UINT32 | PinMux
GPIO signals pin muxing settings. More...
UINT32 | PadTermination
GPIO Pads Internal Termination. More...

Detailed Description

ISH GPIO settings.

Definition at line 50 of file IshConfig.h.

Member Data Documentation

◆ PadTermination

UINT32 ISH_GPIO_CONFIG::PadTermination

GPIO Pads Internal Termination.

For more information please see Platform Design Guide. Check GPIO_ELECTRICAL_CONFIG for reference

Definition at line 62 of file IshConfig.h.

◆ PinMux

UINT32 ISH_GPIO_CONFIG::PinMux

GPIO signals pin muxing settings.

If signal can be enable only on a single pin then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_* in GpioPins*.h for supported settings on a given platform GPIO Pin mux configuration. Refer to GPIO_*_MUXING_ISH_*x_MOSI_*

Definition at line 56 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_GPIO_CONFIG Member List

This is the complete list of members for ISH_GPIO_CONFIG, including all inherited members.

PadTermination | ISH_GPIO_CONFIG
PinMux | ISH_GPIO_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_I2C Struct Reference

Public Attributes | List of all members
ISH_I2C Struct Reference

Struct contains GPIO pins assigned and signal settings of I2C. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I2C:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH I2C GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of I2C.

Definition at line 119 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_I2C Member List

This is the complete list of members for ISH_I2C, including all inherited members.

Enable | ISH_I2C
RsvdBits0 | ISH_I2C
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_I2C_PIN_CONFIG Struct Reference

Public Attributes | List of all members
ISH_I2C_PIN_CONFIG Struct Reference

I2C signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I2C_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Sda
SDA Pin configuration.
ISH_GPIO_CONFIG Scl
SCL Pin configuration.

Detailed Description

I2C signals settings.

Definition at line 90 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_I2C_PIN_CONFIG Member List

This is the complete list of members for ISH_I2C_PIN_CONFIG, including all inherited members.

Scl | ISH_I2C_PIN_CONFIG
Sda | ISH_I2C_PIN_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_I3C_CONFIG Struct Reference

Public Attributes | List of all members
ISH_I3C_CONFIG Struct Reference

The ISH_I3C_CONFIG block describes I3C in ISH device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I3C_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
ISH_I3C Controller
ISH I3C Controller.

Detailed Description

The ISH_I3C_CONFIG block describes I3C in ISH device.

Definition at line 154 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_I3C_CONFIG Member List

This is the complete list of members for ISH_I3C_CONFIG, including all inherited members.

Controller | ISH_I3C_CONFIG
Header | ISH_I3C_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
ISH_PREMEM_CONFIG Struct Reference

Premem Policy for Integrated Sensor Hub device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
ISH Controler 0: Disable; 1: Enable. More...
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Premem Policy for Integrated Sensor Hub device.

Definition at line 163 of file IshConfig.h.

Member Data Documentation

◆ Enable

UINT32 ISH_PREMEM_CONFIG::Enable

ISH Controler 0: Disable; 1: Enable.

For Desktop sku, the ISH POR should be disabled. 0:Disable .

Definition at line 169 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_PREMEM_CONFIG Member List

This is the complete list of members for ISH_PREMEM_CONFIG, including all inherited members.

Enable | ISH_PREMEM_CONFIG
Header | ISH_PREMEM_CONFIG
RsvdBits0 | ISH_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_SPI Struct Reference

Public Attributes | List of all members
ISH_SPI Struct Reference

Struct contains GPIO pins assigned and signal settings of SPI. More...

#include <IshConfig.h>

Collaboration diagram for ISH_SPI:
[legend]

Public Attributes

UINT8 | Enable
ISH SPI GPIO pins assigned: 0: False 1: True.
UINT8 | CsEnable [PCH_MAX_ISH_SPI_CS_PINS]
ISH SPI CS pins assigned: 0: False 1: True.
UINT16 | RsvdField0
Reserved field.

Detailed Description

Struct contains GPIO pins assigned and signal settings of SPI.

Definition at line 99 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_SPI Member List

This is the complete list of members for ISH_SPI, including all inherited members.

CsEnable | ISH_SPI
Enable | ISH_SPI
RsvdField0 | ISH_SPI
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_SPI_PIN_CONFIG Struct Reference

Public Attributes | List of all members
ISH_SPI_PIN_CONFIG Struct Reference

SPI signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_SPI_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Mosi
MOSI Pin configuration.
ISH_GPIO_CONFIG Miso
MISO Pin configuration.
ISH_GPIO_CONFIG Clk
CLK Pin configuration.
ISH_GPIO_CONFIG Cs [PCH_MAX_ISH_SPI_CS_PINS]
CS Pin configuration.

Detailed Description

SPI signals settings.

Definition at line 68 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_SPI_PIN_CONFIG Member List

This is the complete list of members for ISH_SPI_PIN_CONFIG, including all inherited members.

Clk | ISH_SPI_PIN_CONFIG
Cs | ISH_SPI_PIN_CONFIG
Miso | ISH_SPI_PIN_CONFIG
Mosi | ISH_SPI_PIN_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_UART Struct Reference

Public Attributes | List of all members
ISH_UART Struct Reference

Struct contains GPIO pins assigned and signal settings of UART. More...

#include <IshConfig.h>

Collaboration diagram for ISH_UART:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH UART GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of UART.

Definition at line 110 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_UART Member List

This is the complete list of members for ISH_UART, including all inherited members.

Enable | ISH_UART
RsvdBits0 | ISH_UART
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ISH_UART_PIN_CONFIG Struct Reference

Public Attributes | List of all members
ISH_UART_PIN_CONFIG Struct Reference

UART signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_UART_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Rx
RXD Pin configuration.
ISH_GPIO_CONFIG Tx
TXD Pin configuration.
ISH_GPIO_CONFIG Rts
RTS Pin configuration.
ISH_GPIO_CONFIG Cts
CTS Pin configuration.

Detailed Description

UART signals settings.

Definition at line 79 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ISH_UART_PIN_CONFIG Member List

This is the complete list of members for ISH_UART_PIN_CONFIG, including all inherited members.

Cts | ISH_UART_PIN_CONFIG
Rts | ISH_UART_PIN_CONFIG
Rx | ISH_UART_PIN_CONFIG
Tx | ISH_UART_PIN_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ME_PEI_CONFIG Struct Reference

Public Attributes | List of all members
ME_PEI_CONFIG Struct Reference

ME Pei Post-Memory Configuration Structure. More...

#include <MePeiConfig.h>

Collaboration diagram for ME_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | EndOfPostMessage: 2
0: Disabled; 1: Send in PEI; 2: Send in DXE - Send EOP at specific phase.
UINT32 | Heci3Enabled: 1
UINT32 | DisableD0I3SettingForHeci: 1
(Test) 0: Disable; 1: Enable - Enable/Disable D0i3 for HECI.
UINT32 | MeUnconfigOnRtcClear: 2
Enable/Disable Me Unconfig On Rtc Clear. More...
UINT32 | MctpBroadcastCycle: 1
(Test) 0: Disable; 1: Enable - Program registers for MCTP Cycle.
UINT32 | EnforceEDebugMode: 1
0: Disable; 1: Enable - Enforces ME to enter Enhanced Debug Mode
UINT32 | CseDataResilience: 1
0: Disable; 1: Enable - CSE data resilience support
UINT32 | RsvdBits: 23
Reserved for future use & Config block alignment.

Detailed Description

ME Pei Post-Memory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Deprecated Heci3Enabled. Revision 3
  • Added EnforceEDebugMode. Revision 4
  • Added CseDataResilience.

Definition at line 128 of file MePeiConfig.h.

Member Data Documentation

◆ Heci3Enabled

UINT32 ME_PEI_CONFIG::Heci3Enabled
Deprecated:

Definition at line 132 of file MePeiConfig.h.

◆ MeUnconfigOnRtcClear

UINT32 ME_PEI_CONFIG::MeUnconfigOnRtcClear

Enable/Disable Me Unconfig On Rtc Clear.

If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0. It will cause ME to unconfig if RTC is cleared.

  • 0: Disable
  • 1: Enable
  • 2: Cmos is clear, status unkonwn
  • 3: Reserved

Definition at line 142 of file MePeiConfig.h.

The documentation for this struct was generated from the following file:
  • MePeiConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ME_PEI_CONFIG Member List

This is the complete list of members for ME_PEI_CONFIG, including all inherited members.

CseDataResilience | ME_PEI_CONFIG
DisableD0I3SettingForHeci | ME_PEI_CONFIG
EndOfPostMessage | ME_PEI_CONFIG
EnforceEDebugMode | ME_PEI_CONFIG
Header | ME_PEI_CONFIG
Heci3Enabled | ME_PEI_CONFIG
MctpBroadcastCycle | ME_PEI_CONFIG
MeUnconfigOnRtcClear | ME_PEI_CONFIG
RsvdBits | ME_PEI_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ME_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
ME_PEI_PREMEM_CONFIG Struct Reference

ME Pei Pre-Memory Configuration Structure. More...

#include <MePeiConfig.h>

Collaboration diagram for ME_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | HeciTimeouts: 1
0: Disable; 1: Enable - HECI Send/Receive Timeouts.
UINT32 | DidInitStat: 2
(Test) 0: Disabled 1: ME DID init stat 0 - Success 2: ME DID init stat 1 - No Memory in Channels 3: ME DID init stat 2 - Memory Init Error
UINT32 | DisableCpuReplacedPolling: 1
(Test) 0: Set to 0 to enable polling for CPU replacement 1: Set to 1 will disable polling for CPU replacement
UINT32 | SendDidMsg: 1
(Deprecated) 0: Disable; 1: Enable - Enable/Disable to send DID message.
UINT32 | DisableMessageCheck: 1
(Test) 0: ME BIOS will check each messages before sending 1: ME BIOS always sends messages without checking
UINT32 | SkipMbpHob: 1
(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot in a MBP message. More...
UINT32 | HeciCommunication2: 1
(Test) 0: Disable; 1: Enable - Enable/Disable HECI2.
UINT32 | KtDeviceEnable: 1
(Test) 0: Disable; 1: Enable - Enable/Disable Kt Device.
UINT32 | SkipCpuReplacementCheck: 1
(Test) 0: Disable; 1: Enable - Enable/Disable to skip CPU replacement check.
UINT32 | HeciFullTrace: 1
(Test) 0: Disable; 1: Enable - Enable/Disable Full HECI communication information logged to serial
UINT32 | RsvdBits: 21
Reserved for future use & Config block alignment.
UINT32 | Heci1BarAddress
HECI1 BAR address.
UINT32 | Heci2BarAddress
HECI2 BAR address.
UINT32 | Heci3BarAddress
HECI3 BAR address.

Detailed Description

ME Pei Pre-Memory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Add SkipCpuReplacementCheck Option. Revision 3:
  • Deprecate SendDidMsg. Revision 4:
  • Add HeciFullTrace Option.

Definition at line 65 of file MePeiConfig.h.

Member Data Documentation

◆ SkipMbpHob

UINT32 ME_PEI_PREMEM_CONFIG::SkipMbpHob

(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot in a MBP message.

If set to 1, BIOS will send the MBP message with SkipMbp flag set causing CSME to respond with MKHI header only and no MBP data 0: ME BIOS will keep MBP and create HOB for MBP data 1: ME BIOS will skip MBP data

Definition at line 97 of file MePeiConfig.h.

The documentation for this struct was generated from the following file:
  • MePeiConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

ME_PEI_PREMEM_CONFIG Member List

This is the complete list of members for ME_PEI_PREMEM_CONFIG, including all inherited members.

DidInitStat | ME_PEI_PREMEM_CONFIG
DisableCpuReplacedPolling | ME_PEI_PREMEM_CONFIG
DisableMessageCheck | ME_PEI_PREMEM_CONFIG
Header | ME_PEI_PREMEM_CONFIG
Heci1BarAddress | ME_PEI_PREMEM_CONFIG
Heci2BarAddress | ME_PEI_PREMEM_CONFIG
Heci3BarAddress | ME_PEI_PREMEM_CONFIG
HeciCommunication2 | ME_PEI_PREMEM_CONFIG
HeciFullTrace | ME_PEI_PREMEM_CONFIG
HeciTimeouts | ME_PEI_PREMEM_CONFIG
KtDeviceEnable | ME_PEI_PREMEM_CONFIG
RsvdBits | ME_PEI_PREMEM_CONFIG
SendDidMsg | ME_PEI_PREMEM_CONFIG
SkipCpuReplacementCheck | ME_PEI_PREMEM_CONFIG
SkipMbpHob | ME_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MEMORY_CONFIG_NO_CRC Struct Reference

Public Attributes | List of all members
MEMORY_CONFIG_NO_CRC Struct Reference

Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection. More...

#include <MemoryConfig.h>

Collaboration diagram for MEMORY_CONFIG_NO_CRC:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
SA_FUNCTION_CALLS SaCall
Offset 28 Function calls into the SA.
SA_MEMORY_FUNCTIONS MrcCall
Offset 212 Function calls into the MRC.
SPD_DATA_BUFFER * SpdData
Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
SA_MEMORY_DQDQS_MAPPING * DqDqsMap
Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
SA_MEMORY_RCOMP * RcompData
Offset 244 DDR RCOMP resistors and target values.
UINT64 | PlatformMemorySize
Offset 248 The minimum platform memory size required to pass control into DXE.
UINT32 | CleanMemory:1
Offset 256 Ask MRC to clear memory content: FALSE=Do not Clear Memory; TRUE=Clear Memory.
UINT8 | SerialDebugLevel
Sets the serial debug message level
0x00 = Disabled
0x01 = Errors only
0x02 = Errors and Warnings
0x03 = Errors, Warnings, and Info
0x04 = Errors, Warnings, Info, and Events
0x05 = Displays Memory Init Execution Time Summary only
. More...
UINT8 | MemTestOnWarmBoot
Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, 1=Enabled
UINT8 | Reserved11 [2]
Offset 262 - 263 Reserved.

Detailed Description

Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection.

Revision 1: - Initial version. Revision 2: - Added MemTestOnWarmBoot

Definition at line 558 of file MemoryConfig.h.

Member Data Documentation

◆ SerialDebugLevel

UINT8 MEMORY_CONFIG_NO_CRC::SerialDebugLevel

Sets the serial debug message level
0x00 = Disabled
0x01 = Errors only
0x02 = Errors and Warnings
0x03 = Errors, Warnings, and Info
0x04 = Errors, Warnings, Info, and Events
0x05 = Displays Memory Init Execution Time Summary only
.

Offset 260

Definition at line 577 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MEMORY_CONFIG_NO_CRC Member List

This is the complete list of members for MEMORY_CONFIG_NO_CRC, including all inherited members.

CleanMemory | MEMORY_CONFIG_NO_CRC
DqDqsMap | MEMORY_CONFIG_NO_CRC
Header | MEMORY_CONFIG_NO_CRC
MemTestOnWarmBoot | MEMORY_CONFIG_NO_CRC
MrcCall | MEMORY_CONFIG_NO_CRC
PlatformMemorySize | MEMORY_CONFIG_NO_CRC
RcompData | MEMORY_CONFIG_NO_CRC
Reserved11 | MEMORY_CONFIG_NO_CRC
SaCall | MEMORY_CONFIG_NO_CRC
SerialDebugLevel | MEMORY_CONFIG_NO_CRC
SpdData | MEMORY_CONFIG_NO_CRC
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MEMORY_CONFIGURATION Struct Reference

Public Attributes | List of all members
MEMORY_CONFIGURATION Struct Reference

Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection. More...

#include <MemoryConfig.h>

Collaboration diagram for MEMORY_CONFIGURATION:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT16 | Size
Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
UINT8 | HobBufferSize
Offset 30 Size of HOB buffer for MRC.
UINT8 | SpdProfileSelected
Offset 31 SPD XMP profile selection - for XMP supported DIMM: 0=Default DIMM profile, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5.
UINT16 | tCL
Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 31=Maximum.
UINT16 | tRCDtRP
Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 63=Maximum.
UINT16 | tRAS
Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 64=Maximum.
UINT16 | tWR
Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
UINT16 | tRFC
Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 1023=Maximum.
UINT16 | tRRD
Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 15=Maximum.
UINT16 | tWTR
Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRTP
Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12.
UINT16 | tFAW
Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 63=Maximum.
UINT16 | tCWL
Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 20=Maximum.
UINT16 | tREFI
Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 65535=Maximum.
UINT16 | PciIndex
Offset 54 Pci index register address: 0xCF8=Default
UINT16 | PciData
Offset 56 Pci data register address: 0xCFC=Default
UINT16 | VddVoltage
Offset 58 DRAM voltage (Vdd) in millivolts: 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
UINT16 | Idd3n
Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
UINT16 | Idd3p
Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
UINT32 | EccSupport:1
Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, 1=Enable
UINT32 | MrcSafeConfig:1
Bit 1 - MRC Safe Mode: 0=Disable, 1=Enable.
UINT32 | RemapEnable:1
Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, 1=Enable.
UINT32 | ScramblerSupport:1
Bit 3 - Memory scrambler support: 0=Disable, 1=Enable
UINT32 | Vc1ReadMeter:1
Bit 4 - VC1 Read Metering Enable: 0=Disable, 1=Enable
UINT32 | ForceSingleSubchannel:1
Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): 0=Disable, 1=Enable.
UINT32 | SimicsFlag:1
Bit 6 - Option to Enable SIMICS: 0=Disable, 1=Enable
UINT32 | Ddr4DdpSharedClock:1
Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. 0=Not shared, 1=Shared.
UINT32 | SharedZqPin:1
Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=Not Shared, 1=Shared.
UINT32 | LpDqsOscEn:1
Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, 1=Enable
UINT32 | RmtPerTask:1
Bit 10 - Rank Margin Tool Per Task. 0 = Disabled, 1 = Enabled.
UINT32 | TrainTrace:1
Bit 11 - Trained state tracing debug. 0 = Disabled, 1 = Enabled.
UINT32 | SafeMode:1
Bit 12 - Define if safe mode is enabled for MC/IO.
UINT32 | MsHashEnable:1
Bit 13 - Controller Hash Enable: 0=Disable, 1=Enable
UINT32 | DisPgCloseIdleTimeout:1
Bit 14 - Disable Page Close Idle Timeout: 0=Enable, 1=Disable
UINT32 | Ibecc:1
Bit 15 - In-band ECC: 0=Disable, 1=Enable.
UINT32 | IbeccOperationMode:2
Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, 2=Makes all requests protected and ignore range checks
UINT32 | ChHashOverride:1
Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
UINT32 | EccDftEn:1
Bit 19 - ECC DFT support option.
UINT32 | Write0:1
Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, 1=Enable
UINT32 | ReuseAdlSDdr5Board:1
Bit 21 - Indicate whether adl ddr5 board is reused.
UINT32 | PeriodicDcc:1
Bit 22 - Periodic DCC: 0=Disable, 1=Enable.
UINT32 | LpMode:2
Bit 23:24 - LPMode: 0=Auto, 1=Enabled, 2=Disabled, 3=Reserved.
UINT32 | RsvdO64B25to31:7
Bits 25:31 reserved.
UINT8 | DisableChannel [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]
Offset 68-75.
UINT8 | Ratio
Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. 0 = Auto
UINT8 | ProbelessTrace
Offset 77 Probeless Trace: 0=Disabled, 1=Enabled
UINT8 | ChHashInterleaveBit
Channel Hash Enable. More...
UINT8 | SmramMask
Offset 79 Reserved memory ranges for SMRAM.
UINT32 | BClkFrequency
Offset 80 Base reference clock value, in Hertz: 100000000 = 100Hz, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz.
UINT32 | ECT:1
Training Algorithms 1 Offset 84. More...
UINT32 | SOT:1
Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | ERDMPRTC2D:1
Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDMPRT:1
Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RCVET:1
Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | JWRL:1
Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | EWRTC2D:1
Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | ERDTC2D:1
Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRTC1D:1
Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRVC1D:1
Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDTC1D:1
Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | DIMMODTT:1
Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | DIMMRONT:1
Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRDSEQT:1
Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRSRT:1
Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDODTT:1
Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDEQT:1
Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDAPT:1
Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRTC2D:1
Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDTC2D:1
Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRVC2D:1
Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDVC2D:1
Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | CMDVC:1
Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, 1=Enable.
UINT32 | LCT:1
Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RTL:1
Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | TAT:1
Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RMT:1
Bit 26 - Enable/Disable Rank Margin Tool function: 0=Disable, 1=Enable.
UINT32 | MEMTST:1
Bit 27 - Enable/Disable Memory Test function: 0=Disable, 1=Enable.
UINT32 | ALIASCHK:1
Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, 1=Enable
UINT32 | RCVENC1D:1
Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RMC:1
Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRDSUDT:1
Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. More...
UINT32 | DCC: 1
Training Algorithms 2 Offset 88. More...
UINT32 | RDVC1D: 1
Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
UINT32 | TXTCO: 1
Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
UINT32 | CLKTCO: 1
Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
UINT32 | CMDSR: 1
Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
UINT32 | CMDDSEQ: 1
Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
UINT32 | DIMMODTCA: 1
Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
UINT32 | TXTCODQS: 1
Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
UINT32 | CMDDRUD: 1
Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
UINT32 | VCCDLLBP: 1
Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
UINT32 | PVTTDNLP: 1
Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
UINT32 | RDVREFDC: 1
Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
UINT32 | VDDQT: 1
Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
UINT32 | RMTBIT: 1
Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
UINT32 | PDA: 1
BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | DIMMDFE: 1
BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, 1=Enable.
UINT32 | TXDQSDCC: 1
BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, 1=Enable.
UINT32 | DRAMDCA: 1
BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, 1=Enable.
UINT32 | WRDS: 1
BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, 1=Enable.
UINT32 | ReservedBits2:13
Bits 19:31 - Reserved.
UINT32 | MrcTimeMeasure:1
Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: 0=Disable, 1=Enable.
UINT32 | MrcFastBoot:1
Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, 1=Enable
UINT32 | DqPinsInterleaved:1
Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: 0=Disable, 1=Enable.
UINT32 | RankInterleave:1
Bit 3 - Rank Interleave Mode: 0=Disable, 1=Enable
UINT32 | EnhancedInterleave:1
Bit 4 - Enhanced Interleave Mode: 0=Disable, 1=Enable
UINT32 | WeaklockEn:1
Bit 5 - Weak Lock Enable: 0=Disable, 1=Enable
UINT32 | ChHashEnable:1
Bit 6 - Channel Hash Enable: 0=Disable, 1=Enable
UINT32 | EnablePwrDn:1
Bit 7 - Enable Power Down control for DDR: 0=PCODE control, 1=BIOS control
UINT32 | EnablePwrDnLpddr:1
Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, 1=BIOS control
UINT32 | SrefCfgEna:1
Bit 9 - Enable Self Refresh: 0=Disable, 1=Enable
UINT32 | ThrtCkeMinDefeatLpddr:1
Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, 1=Enable
UINT32 | ThrtCkeMinDefeat:1
Bit 11 - Throttler CKE min defeature: 0=Disable, 1=Enable.
UINT32 | AutoSelfRefreshSupport:1
Bit 12 - FALSE = No auto self refresh support, TRUE = auto self refresh support
UINT32 | ExtTemperatureSupport:1
Bit 13 - FALSE = No extended temperature support, TRUE = extended temperature support
UINT32 | MobilePlatform:1
Bit 14 - Memory controller device id indicates: TRUE if mobile, FALSE if not. Note: This will be auto-detected and updated.
UINT32 | Force1Dpc:1
Bit 15 - TRUE means force one DIMM per channel, FALSE means no limit
UINT32 | ForceSingleRank:1
Bit 16 - TRUE means use Rank0 only (in each DIMM): 0=Disable, 1=Enable.
UINT32 | VttTermination:1
Bit 17 - Vtt Termination for Data ODT: 0=Disable, 1=Enable.
UINT32 | VttCompForVsshi:1
Bit 18 - Enable/Disable Vtt Comparator For Vsshi: 0=Disable, 1=Enable.
UINT32 | ExitOnFailure:1
Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, 1=Enable
UINT32 | NewFeatureEnable1:1
Bit 20 - Generic enable knob for new feature set 1 0: Disable ; 1: Enable.
UINT32 | NewFeatureEnable2:1
Bit 21 - Generic enable knob for new feature set 2 0: Disable ; 1: Enable.
UINT32 | RhSelect:2
Bit 22-23 - RH Select: 0=Disable, 1=RFM, 2=pTRR.
UINT32 | RefreshPanicWm:4
Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
UINT32 | RefreshHpWm:4
Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
UINT32 | VddSettleWaitTime
Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: Default=0
UINT16 | SrefCfgIdleTmr
Offset 100 Self Refresh idle timer: 512=Minimal, 65535=Maximum.
UINT16 | ChHashMask
Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), 0x30CE= BIT[19:18, 13:12 ,9:7] set
UINT16 | DdrFreqLimit
Offset 104 Memory Frequency limit: 0 = Auto, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h.
UINT8 | MaxRttWr
Offset 106 Maximum DIMM RTT_WR to use in power training: 0=ODT Off, 1 = 120 ohms.
UINT8 | ThrtCkeMinTmr
Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, 0x00=Default
UINT8 | ThrtCkeMinTmrLpddr
Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default
BOOLEAN | PerBankRefresh
Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, TRUE=Enabled
UINT8 | SaGv
Offset 110 SA GV: 0=Disabled, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled.
UINT8 | NModeSupport
Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: 0=AUTO, 1=1N, 2=2N.
UINT8 | RefClk
Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, 0x00 = 133MHz
UINT8 | EnCmdRate
Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, 7=3 CMDs, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs.
UINT8 | Refresh2X
Offset 114 Refresh 2x: 0=Disable, 1=Enable for WARM or HOT, 2=Enable for HOT only.
UINT8 | EpgEnable
Offset 115 Enable Energy Performance Gain.
UINT8 | UserThresholdEnable
Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, 0=Default
UINT8 | UserBudgetEnable
Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, 0=Default
UINT8 | RetrainOnFastFail
Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, 1 = Enabled
UINT8 | PowerDownMode
Offset 119 CKE Power Down Mode: 0xFF=AUTO, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode.
UINT8 | PwdwnIdleCounter
Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, 0x80=0x80 DCLK
UINT8 | CmdRanksTerminated
Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating
UINT16 | MsHashMask
Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), 0x30CE= BIT[19:18, 13:12 ,9:7] set
UINT32 | Lp5CccConfig
Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
UINT8 | RMTLoopCount
Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, 0=Default
UINT8 | MsHashInterleaveBit
Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9.
UINT8 | GearRatio
Offset 130 Gear mode when SAGV is disabled: 0=Auto, 1 - Gear1, 2 - Gear2, 4 - Gear4.
UINT8 | Ddr4OneDpc
Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
UINT32 | BclkRfiFreq [MEM_MAX_SAGV_POINTS]
Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No RFI Tuning. Range is 98Mhz-100Mhz.
UINT16 | SaGvFreq [MEM_MAX_SAGV_POINTS]
Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: 0=Default, 1067, 1333, 1600, 1800, 1867, etc.
UINT8 | SaGvGear [MEM_MAX_SAGV_POINTS]
Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: 0=Auto, 1, 2, 4.
UINT8 | IbeccProtectedRangeEnable [MEM_MAX_IBECC_REGIONS]
Offset 160 Enable use of address range for ECC Protection: 0=Disabled, 1=Enabled.
UINT32 | IbeccProtectedRangeBase [MEM_MAX_IBECC_REGIONS]
Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF].
UINT32 | IbeccProtectedRangeMask [MEM_MAX_IBECC_REGIONS]
Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF].
UINT8 | McRefresh2X
Offset 232 Deprecated from revision 19, use McRefreshRate instead.
UINT8 | Lfsr0Mask
Offset 233 RH pTRR LFSR0 Mask.
UINT8 | Lfsr1Mask
Offset 234 RH pTRR LFSR1 Mask.
UINT8 | CmdMirror
Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
UINT8 | AllowOppRefBelowWriteThrehold
Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
UINT8 | WriteThreshold
Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
UINT8 | PprEnable
Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR.
UINT8 | MarginLimitCheck
Offset 239 Margin limit check enable: 0=Disable, 1=L1 only, 2=L2 only, 3=Both L1 and L2.
UINT16 | MarginLimitL2
Offset 240 Margin limit check L2 threshold: 100=Default
UINT8 | LpddrRttWr
Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto.
UINT8 | LpddrRttCa
Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto.
UINT16 | VddqVoltage
Offset 244 DRAM voltage (Vddq) in millivolts: 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
UINT16 | VppVoltage
Offset 246 DRAM voltage (Vpp) in millivolts: 0=Platform Default (no override), 1800=1.8V, 2050=2.05V etc.
UINT8 | ExtendedBankHashing
Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; 1 = Enabled
UINT8 | DynamicMemoryBoost
Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled.
UINT8 | IbeccErrInjControl
Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter.
UINT8 | RealtimeMemoryFrequency
Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled.
UINT32 | IbeccErrInjCount
Offset 252 Number of transactions between ECC error injection.
UINT64 | IbeccErrInjAddress
Offset 256 Address to match against for ECC error injection.
UINT64 | IbeccErrInjMask
Offset 264 Mask to match against for ECC error injection.
UINT8 | RefreshWm
Offset 272 Refresh Watermarks, 0 = Low, 1 = High
UINT8 | McRefreshRate
Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x.
UINT8 | Reserved274 [2]
Offset 274-275 Reserved for natural alignment.
UINT32 | DebugValue
Offset 276 Debug Value for general use.
UINT16 | tRFCpb
Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRFC2
Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRFC4
Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRRD_L
Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRRD_S
Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tWTR_L
Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tCCD_L
Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tWTR_S
Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT64 | EccErrInjAddress
Offset 296 Address to match against for ECC error injection.
UINT64 | EccErrInjMask
Offset 304 Mask to match against for ECC error injection.
UINT32 | EccErrInjCount
Offset 312 Number of transactions between ECC error injection.
UINT16 | FreqLimitMixedConfig
Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. 0=Auto, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h.
UINT8 | FirstDimmBitMask
Offset 318 Defines which DIMM should be populated first on a 2DPC board. More...
UINT8 | UserBd
Offset 319 MrcBoardType 1 - Desktop 1DPC 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order 5 - ULT Mobile.
UINT8 | SagvSwitchFactorIA
Offset 320 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvSwitchFactorGT
Offset 321 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvSwitchFactorIO
Offset 322 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvSwitchFactorStall
Offset 323 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvHeuristicsUpControl
Offset 324 Sagv duration in ms before heuristics up: 1 , 50=Maximum, default 1ms.
UINT8 | SagvHeuristicsDownControl
Offset 325 Sagv duration in ms before heuristics down: 1 , 50=Maximum, default 1ms.
UINT16 | FreqLimitMixedConfig_1R1R_8GB
Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel). More...
UINT16 | FreqLimitMixedConfig_1R1R_16GB
Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel). More...
UINT16 | FreqLimitMixedConfig_1R1R_8GB_16GB
Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel). More...
UINT16 | FreqLimitMixedConfig_2R2R
Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel). More...
UINT16 | LctCmdEyeWidth
Offset 334 LCT Command eyewidth.
UINT8 | FirstDimmBitMaskEcc
Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board. More...
UINT8 | Lp5BankMode
Offset 337 LP5 Bank Mode.
UINT8 | Reserved336 [6]
Offset 338-343 Reserved for natural alignment.

Detailed Description

Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection.

This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure. Revision history is at the top of this file

Definition at line 307 of file MemoryConfig.h.

Member Data Documentation

◆ ChHashInterleaveBit

UINT8 MEMORY_CONFIGURATION::ChHashInterleaveBit

Channel Hash Enable.

NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8
0=BIT6, 1=BIT7, 2=BIT8, 3=BIT9 Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)

Definition at line 364 of file MemoryConfig.h.

◆ DCC

UINT32 MEMORY_CONFIGURATION::DCC

Training Algorithms 2 Offset 88.

Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.

Definition at line 402 of file MemoryConfig.h.

◆ ECT

UINT32 MEMORY_CONFIGURATION::ECT

Training Algorithms 1 Offset 84.

Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.

Definition at line 369 of file MemoryConfig.h.

◆ FirstDimmBitMask

UINT8 MEMORY_CONFIGURATION::FirstDimmBitMask

Offset 318 Defines which DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. Note: this mask is only for non-ECC DIMM.

Definition at line 519 of file MemoryConfig.h.

◆ FirstDimmBitMaskEcc

UINT8 MEMORY_CONFIGURATION::FirstDimmBitMaskEcc

Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be be populated firstly. Note: this mask is only for ECC DIMM, not for non-ECC DIMM.

Definition at line 544 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_1R1R_16GB

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_16GB

Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 537 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_1R1R_8GB

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB

Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 535 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_1R1R_8GB_16GB

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB_16GB

Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 539 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_2R2R

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_2R2R

Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 541 of file MemoryConfig.h.

◆ WRDSUDT

UINT32 MEMORY_CONFIGURATION::WRDSUDT

Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently.

Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable

Definition at line 400 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

MEMORY_CONFIGURATION Member List

This is the complete list of members for MEMORY_CONFIGURATION, including all inherited members.

ALIASCHK | MEMORY_CONFIGURATION
AllowOppRefBelowWriteThrehold | MEMORY_CONFIGURATION
AutoSelfRefreshSupport | MEMORY_CONFIGURATION
BClkFrequency | MEMORY_CONFIGURATION
BclkRfiFreq | MEMORY_CONFIGURATION
ChHashEnable | MEMORY_CONFIGURATION
ChHashInterleaveBit | MEMORY_CONFIGURATION
ChHashMask | MEMORY_CONFIGURATION
ChHashOverride | MEMORY_CONFIGURATION
CLKTCO | MEMORY_CONFIGURATION
CMDDRUD | MEMORY_CONFIGURATION
CMDDSEQ | MEMORY_CONFIGURATION
CmdMirror | MEMORY_CONFIGURATION
CmdRanksTerminated | MEMORY_CONFIGURATION
CMDSR | MEMORY_CONFIGURATION
CMDVC | MEMORY_CONFIGURATION
DCC | MEMORY_CONFIGURATION
Ddr4DdpSharedClock | MEMORY_CONFIGURATION
Ddr4OneDpc | MEMORY_CONFIGURATION
DdrFreqLimit | MEMORY_CONFIGURATION
DebugValue | MEMORY_CONFIGURATION
DIMMDFE | MEMORY_CONFIGURATION
DIMMODTCA | MEMORY_CONFIGURATION
DIMMODTT | MEMORY_CONFIGURATION
DIMMRONT | MEMORY_CONFIGURATION
DisableChannel | MEMORY_CONFIGURATION
DisPgCloseIdleTimeout | MEMORY_CONFIGURATION
DqPinsInterleaved | MEMORY_CONFIGURATION
DRAMDCA | MEMORY_CONFIGURATION
DynamicMemoryBoost | MEMORY_CONFIGURATION
EccDftEn | MEMORY_CONFIGURATION
EccErrInjAddress | MEMORY_CONFIGURATION
EccErrInjCount | MEMORY_CONFIGURATION
EccErrInjMask | MEMORY_CONFIGURATION
EccSupport | MEMORY_CONFIGURATION
ECT | MEMORY_CONFIGURATION
EnablePwrDn | MEMORY_CONFIGURATION
EnablePwrDnLpddr | MEMORY_CONFIGURATION
EnCmdRate | MEMORY_CONFIGURATION
EnhancedInterleave | MEMORY_CONFIGURATION
EpgEnable | MEMORY_CONFIGURATION
ERDMPRTC2D | MEMORY_CONFIGURATION
ERDTC2D | MEMORY_CONFIGURATION
EWRTC2D | MEMORY_CONFIGURATION
ExitOnFailure | MEMORY_CONFIGURATION
ExtendedBankHashing | MEMORY_CONFIGURATION
ExtTemperatureSupport | MEMORY_CONFIGURATION
FirstDimmBitMask | MEMORY_CONFIGURATION
FirstDimmBitMaskEcc | MEMORY_CONFIGURATION
Force1Dpc | MEMORY_CONFIGURATION
ForceSingleRank | MEMORY_CONFIGURATION
ForceSingleSubchannel | MEMORY_CONFIGURATION
FreqLimitMixedConfig | MEMORY_CONFIGURATION
FreqLimitMixedConfig_1R1R_16GB | MEMORY_CONFIGURATION
FreqLimitMixedConfig_1R1R_8GB | MEMORY_CONFIGURATION
FreqLimitMixedConfig_1R1R_8GB_16GB | MEMORY_CONFIGURATION
FreqLimitMixedConfig_2R2R | MEMORY_CONFIGURATION
GearRatio | MEMORY_CONFIGURATION
Header | MEMORY_CONFIGURATION
HobBufferSize | MEMORY_CONFIGURATION
Ibecc | MEMORY_CONFIGURATION
IbeccErrInjAddress | MEMORY_CONFIGURATION
IbeccErrInjControl | MEMORY_CONFIGURATION
IbeccErrInjCount | MEMORY_CONFIGURATION
IbeccErrInjMask | MEMORY_CONFIGURATION
IbeccOperationMode | MEMORY_CONFIGURATION
IbeccProtectedRangeBase | MEMORY_CONFIGURATION
IbeccProtectedRangeEnable | MEMORY_CONFIGURATION
IbeccProtectedRangeMask | MEMORY_CONFIGURATION
Idd3n | MEMORY_CONFIGURATION
Idd3p | MEMORY_CONFIGURATION
JWRL | MEMORY_CONFIGURATION
LCT | MEMORY_CONFIGURATION
LctCmdEyeWidth | MEMORY_CONFIGURATION
Lfsr0Mask | MEMORY_CONFIGURATION
Lfsr1Mask | MEMORY_CONFIGURATION
Lp5BankMode | MEMORY_CONFIGURATION
Lp5CccConfig | MEMORY_CONFIGURATION
LpddrRttCa | MEMORY_CONFIGURATION
LpddrRttWr | MEMORY_CONFIGURATION
LpDqsOscEn | MEMORY_CONFIGURATION
LpMode | MEMORY_CONFIGURATION
MarginLimitCheck | MEMORY_CONFIGURATION
MarginLimitL2 | MEMORY_CONFIGURATION
MaxRttWr | MEMORY_CONFIGURATION
McRefresh2X | MEMORY_CONFIGURATION
McRefreshRate | MEMORY_CONFIGURATION
MEMTST | MEMORY_CONFIGURATION
MobilePlatform | MEMORY_CONFIGURATION
MrcFastBoot | MEMORY_CONFIGURATION
MrcSafeConfig | MEMORY_CONFIGURATION
MrcTimeMeasure | MEMORY_CONFIGURATION
MsHashEnable | MEMORY_CONFIGURATION
MsHashInterleaveBit | MEMORY_CONFIGURATION
MsHashMask | MEMORY_CONFIGURATION
NewFeatureEnable1 | MEMORY_CONFIGURATION
NewFeatureEnable2 | MEMORY_CONFIGURATION
NModeSupport | MEMORY_CONFIGURATION
PciData | MEMORY_CONFIGURATION
PciIndex | MEMORY_CONFIGURATION
PDA | MEMORY_CONFIGURATION
PerBankRefresh | MEMORY_CONFIGURATION
PeriodicDcc | MEMORY_CONFIGURATION
PowerDownMode | MEMORY_CONFIGURATION
PprEnable | MEMORY_CONFIGURATION
ProbelessTrace | MEMORY_CONFIGURATION
PVTTDNLP | MEMORY_CONFIGURATION
PwdwnIdleCounter | MEMORY_CONFIGURATION
RankInterleave | MEMORY_CONFIGURATION
Ratio | MEMORY_CONFIGURATION
RCVENC1D | MEMORY_CONFIGURATION
RCVET | MEMORY_CONFIGURATION
RDAPT | MEMORY_CONFIGURATION
RDEQT | MEMORY_CONFIGURATION
RDMPRT | MEMORY_CONFIGURATION
RDODTT | MEMORY_CONFIGURATION
RDTC1D | MEMORY_CONFIGURATION
RDTC2D | MEMORY_CONFIGURATION
RDVC1D | MEMORY_CONFIGURATION
RDVC2D | MEMORY_CONFIGURATION
RDVREFDC | MEMORY_CONFIGURATION
RealtimeMemoryFrequency | MEMORY_CONFIGURATION
RefClk | MEMORY_CONFIGURATION
Refresh2X | MEMORY_CONFIGURATION
RefreshHpWm | MEMORY_CONFIGURATION
RefreshPanicWm | MEMORY_CONFIGURATION
RefreshWm | MEMORY_CONFIGURATION
RemapEnable | MEMORY_CONFIGURATION
Reserved274 | MEMORY_CONFIGURATION
Reserved336 | MEMORY_CONFIGURATION
ReservedBits2 | MEMORY_CONFIGURATION
RetrainOnFastFail | MEMORY_CONFIGURATION
ReuseAdlSDdr5Board | MEMORY_CONFIGURATION
RhSelect | MEMORY_CONFIGURATION
RMC | MEMORY_CONFIGURATION
RMT | MEMORY_CONFIGURATION
RMTBIT | MEMORY_CONFIGURATION
RMTLoopCount | MEMORY_CONFIGURATION
RmtPerTask | MEMORY_CONFIGURATION
RsvdO64B25to31 | MEMORY_CONFIGURATION
RTL | MEMORY_CONFIGURATION
SafeMode | MEMORY_CONFIGURATION
SaGv | MEMORY_CONFIGURATION
SaGvFreq | MEMORY_CONFIGURATION
SaGvGear | MEMORY_CONFIGURATION
SagvHeuristicsDownControl | MEMORY_CONFIGURATION
SagvHeuristicsUpControl | MEMORY_CONFIGURATION
SagvSwitchFactorGT | MEMORY_CONFIGURATION
SagvSwitchFactorIA | MEMORY_CONFIGURATION
SagvSwitchFactorIO | MEMORY_CONFIGURATION
SagvSwitchFactorStall | MEMORY_CONFIGURATION
ScramblerSupport | MEMORY_CONFIGURATION
SharedZqPin | MEMORY_CONFIGURATION
SimicsFlag | MEMORY_CONFIGURATION
Size | MEMORY_CONFIGURATION
SmramMask | MEMORY_CONFIGURATION
SOT | MEMORY_CONFIGURATION
SpdProfileSelected | MEMORY_CONFIGURATION
SrefCfgEna | MEMORY_CONFIGURATION
SrefCfgIdleTmr | MEMORY_CONFIGURATION
TAT | MEMORY_CONFIGURATION
tCCD_L | MEMORY_CONFIGURATION
tCL | MEMORY_CONFIGURATION
tCWL | MEMORY_CONFIGURATION
tFAW | MEMORY_CONFIGURATION
ThrtCkeMinDefeat | MEMORY_CONFIGURATION
ThrtCkeMinDefeatLpddr | MEMORY_CONFIGURATION
ThrtCkeMinTmr | MEMORY_CONFIGURATION
ThrtCkeMinTmrLpddr | MEMORY_CONFIGURATION
TrainTrace | MEMORY_CONFIGURATION
tRAS | MEMORY_CONFIGURATION
tRCDtRP | MEMORY_CONFIGURATION
tREFI | MEMORY_CONFIGURATION
tRFC | MEMORY_CONFIGURATION
tRFC2 | MEMORY_CONFIGURATION
tRFC4 | MEMORY_CONFIGURATION
tRFCpb | MEMORY_CONFIGURATION
tRRD | MEMORY_CONFIGURATION
tRRD_L | MEMORY_CONFIGURATION
tRRD_S | MEMORY_CONFIGURATION
tRTP | MEMORY_CONFIGURATION
tWR | MEMORY_CONFIGURATION
tWTR | MEMORY_CONFIGURATION
tWTR_L | MEMORY_CONFIGURATION
tWTR_S | MEMORY_CONFIGURATION
TXDQSDCC | MEMORY_CONFIGURATION
TXTCO | MEMORY_CONFIGURATION
TXTCODQS | MEMORY_CONFIGURATION
UserBd | MEMORY_CONFIGURATION
UserBudgetEnable | MEMORY_CONFIGURATION
UserThresholdEnable | MEMORY_CONFIGURATION
Vc1ReadMeter | MEMORY_CONFIGURATION
VCCDLLBP | MEMORY_CONFIGURATION
VDDQT | MEMORY_CONFIGURATION
VddqVoltage | MEMORY_CONFIGURATION
VddSettleWaitTime | MEMORY_CONFIGURATION
VddVoltage | MEMORY_CONFIGURATION
VppVoltage | MEMORY_CONFIGURATION
VttCompForVsshi | MEMORY_CONFIGURATION
VttTermination | MEMORY_CONFIGURATION
WeaklockEn | MEMORY_CONFIGURATION
WRDS | MEMORY_CONFIGURATION
WRDSEQT | MEMORY_CONFIGURATION
WRDSUDT | MEMORY_CONFIGURATION
Write0 | MEMORY_CONFIGURATION
WriteThreshold | MEMORY_CONFIGURATION
WRSRT | MEMORY_CONFIGURATION
WRTC1D | MEMORY_CONFIGURATION
WRTC2D | MEMORY_CONFIGURATION
WRVC1D | MEMORY_CONFIGURATION
WRVC2D | MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: OVERCLOCKING_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
OVERCLOCKING_PREMEM_CONFIG Struct Reference

Overclocking Configuration Structure. More...

#include <OverclockingConfig.h>

Collaboration diagram for OVERCLOCKING_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | OcSupport: 1
Overclocking support. More...
UINT32 | OcLock: 1
If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; 0: Disable; 1: Enable (Lock).
UINT32 | CoreVoltageMode: 1
Core voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | CorePllVoltageOffset: 6
Core PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | Avx2RatioOffset: 5
AVX2 Ratio Offset. 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
UINT32 | Avx3RatioOffset: 5
deprecated from version 28
UINT32 | BclkAdaptiveVoltage: 1
Bclk Adaptive Voltage enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
UINT32 | RingDownBin: 1
Ring Downbin enable/disable. More...
UINT32 | RingVoltageMode: 1
Ring voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | GtVoltageMode: 1
Specifies whether GT voltage is operating in Adaptive or Override mode: 0=Adaptive, 1=Override.
UINT32 | RealtimeMemoryTiming: 1
Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE. 0=Disable, 1=Enable.
UINT32 | FivrEfficiency: 1
Deprecated < Fivr Faults. Enable or Disable FIVR Faults. 0: Disabled, 1: Enabled.
UINT32 | CoreVfPointOffsetMode: 1
Deprecated < Fivr Efficiency Management. 0: Disabled, 1: Enabled. More...
UINT32 | CoreVfConfigScope: 1
Core VF Configuration Scope. More...
UINT32 | PerCoreRatioOverride: 1
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. 0: Disable, 1: enable.
UINT32 | UnlimitedIccMax: 1
deprecated from version 32
UINT32 | SaVoltageMode: 1
SA/Uncore voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | CoreRatioExtensionMode: 1
Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable.
UINT8 | CoreMaxOcRatio
Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0). More...
UINT8 | GtMaxOcRatio
Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, 0=AUTO
UINT8 | RingMaxOcRatio
Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit. More...
UINT8 | AtomL2MaxOcRatio
Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0). More...
UINT16 | CoreVoltageOverride
The core voltage override which is applied to the entire range of cpu core frequencies. More...
UINT16 | CoreVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range. More...
INT16 | CoreVoltageOffset
The core voltage offset applied on top of all other voltage modes. More...
UINT16 | RingVoltageOverride
The ring voltage override which is applied to the entire range of cpu ring frequencies. More...
UINT16 | RingVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range. More...
INT16 | RingVoltageOffset
The ring voltage offset applied on top of all other voltage modes. More...
INT16 | GtVoltageOffset
The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: 0=Minimal, 1000=Maximum.
UINT16 | GtVoltageOverride
The GT voltage override which is applied to the entire range of GT frequencies 0=Default
UINT16 | GtExtraTurboVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal, 2000=Maximum.
INT16 | SaVoltageOffset
The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: 0=Default
UINT32 | GtPllVoltageOffset: 6
GT PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | RingPllVoltageOffset: 6
Ring PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | SaPllVoltageOffset: 6
System Agent PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | McPllVoltageOffset: 6
Memory Controller PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | IaCepEnable: 1
Enable IA Current Excursion Protection. 1: Enable. 0: Disable.
UINT32 | GtCepEnable: 1
Enable GT Current Excursion Protection. 1: Enable. 0: Disable.
UINT32 | SaCepEnable: 1
Enable SA Current Excursion Protection. 1: Enable. 0: Disable.
UINT32 | IaSirpEnable: 1
Enable IA SoC Iccmax Reactive Protector. 1: Enable. 0: Disable.
UINT32 | ItdThrottleEnable: 1
Enable Inverse Temperature Dependency Throttle Support. 1: Enable. 0: Disable.
UINT32 | DlvrBypassModeEnable: 1
Enable CPU DLVR bypass mode support, 0: Disable. 0: Enable.
UINT32 | SaPllFreqOverride: 1
Sa PLL Frequecy Override. 0: 3200MHz. 1: 1600MHz.
UINT32 | TscDisableHwFixup: 1
Core HW Fixup disable during TSC copy from PMA to APIC, 0: Enable. 1: Disable.
UINT8 | TjMaxOffset
TjMax Offset. More...
UINT8 | RsvdByte2 [3]
Reserved for dword alignment.
UINT32 | TvbRatioClipping: 1
This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature. More...
UINT32 | TvbVoltageOptimization: 1
This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature. More...
UINT32 | IaIccUnlimitedMode: 1
Support IA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
UINT32 | GtIccUnlimitedMode: 1
Support GT Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
UINT32 | FllOcModeEn: 1
Enable FLL Mode override with the value in FllOcMode. 0: Disable. 1: Enable.
UINT32 | Etvb: 1
Enhanced Thermal Turbo Mode (eTVB). 0:eTVB is disabled on supporting products 1:eTVB is enabled on supporting products.
UINT16 | PerCoreHtDisable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. More...
UINT8 | Avx2VoltageScaleFactor
Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. More...
UINT8 | Avx512VoltageScaleFactor
Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. More...
INT16 | CoreVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the Core Voltage Offset applied to the each selected VF Point. More...
UINT8 | RsvdByte3 [2]
Reserved for dword alignment.
UINT8 | CoreVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the Core Ration.
UINT8 | CoreVfPointCount
Number of supported Core Voltage & Frequency Point.
INT16 | PerCoreVoltageOffset [CPU_MAX_BIG_CORES]
Array used to specifies the selected Core Offset Voltage. More...
UINT8 | AtomClusterRatio [CPU_MAX_ATOM_CLUSTERS]
The Atom cluster max ratio overrides. More...
UINT8 | AtomL2VoltageMode
Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating. More...
UINT8 | RsvdByte4
Reserved for dword alignment.
UINT16 | AtomL2VoltageOverride
The atom L2 voltage override which is applied to the entire range of atom core frequencies. More...
UINT16 | AtomL2VoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operating in turbo mode range. More...
INT16 | AtomL2VoltageOffset
The atom L2 voltage offset applied on top of all other voltage modes. More...
UINT16 | SaVoltageOverride
The SA/Uncore voltage override which is applied to the entire range of uncore frequencies. More...
UINT16 | SaExtraTurboVoltage
Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is operating in turbo mode range. More...
UINT8 | RingVfPointOffsetMode
Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes. More...
UINT8 | RingVfPointCount
Number of supported Ring Voltage & Frequency Point.
UINT8 | RsvdByte5 [2]
Reserved for dword alignment.
INT16 | RingVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the Ring Voltage Offset applied to the each selected VF Point. More...
UINT8 | RsvdByte6 [2]
Reserved for dword alignment.
UINT8 | RingVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the Ring Ration.
UINT8 | AtomPllVoltageOffset
Atom PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | CpuBclkOcFrequency
CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto. Range is 8000-50000 (10KHz)
UINT32 | DisablePerCoreMask
Core disable mask is a bitwise indication of which core should be disabled. More...
UINT32 | DisablePerAtomMask
Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCoreCount is to set the number of active atoms. More...
UINT8 | PvdRatioThreshold
The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range. More...
UINT8 | PvdMode
PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0). More...
UINT8 | FllOverclockMode
FLL_OVERCLOCK_MODE: 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63.
UINT8 | PllMaxBandingRatio
The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains. More...
INT16 | PerAtomClusterVoltageOffset [CPU_MAX_ATOM_CLUSTERS]
Deprecated from revision 34.
UINT32 | SocBclkOcFrequency
SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto. Range is 4000-100000 (10KHz)
UINT16 | IaIccMax
Voltage Regulator Current Limit (Icc Max) for IA and GT. More...
UINT8 | TvbDownBinsTempThreshold0
Down Bins (delta) for Temperature Threshold 0. More...
UINT8 | TvbTempThreshold0
TVB Temp (degrees C) - Temperature Threshold 0. More...
UINT8 | TvbTempThreshold1
TVB Temp (degrees C) - Temperature Threshold 1. More...
UINT8 | TvbDownBinsTempThreshold1
Down Bins (delta) for Temperature Threshold 1. More...

Detailed Description

Overclocking Configuration Structure.

Revision 1:

  • Initial version. Revision 2
  • Add PerCoreHtDisable Revision 3
  • Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor Revision 4
  • Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & CoreVfPointCount Revision 5
  • Change OcLock default to 'Enabled' Revision 6
  • Add CoreVfScope & PerCoreVoltageOffset Revision 7
  • Add AtomMaxOcRatio Revision 8
  • Add PerCoreRatioOverride and PerCoreRatio for Per Core PState overclocking. Revision 9 Add UnlimitedIccMax Revision 10 Add Atom Voltage configurations Revision 11 Add SA Voltage adaptive and override configurations Revision 12 Add RingVfPointOffsetMode & RingVfPointOffset & RingVfPointRatio & RingVfPointCount Revision 13 Add CpuBclkOcFrequency Revision 14:
  • Add DisablePerCoreMask & DisablePerAtomMask. Revision 15 Add CoreRatioExtensionMode Revision 16 Add PvdRatioThreshold Revision 17 Add IaCepEnable & GtCepEnable & SaCepEnable & IaSirpEnable Revision 18 Add Per Atom Cluster VF support Corrected the policy name of AtomMaxOcRatio to be AtomL2MaxOcRatio Revision 19 Modify PllVoltageOffset of each Domain Range in 0 - 15 instead of 0 - 63 Revision 20 Add ItdThrottleEnable Revision 21 Add AtomClusterRatio & Correct max big core number to be 8 Revision 22 Add SocBclkOcFrequency Revision 23 Add AtomPllVoltageOffset Revision 24 Deprecated FivrFaults, FivrEfficiency. Revision 25 Add DlvrBypassModeEnable. Revision 26 Add PvdMode and FllOverclockMode Revision 27 Deprecated AtomL2MaxOcRatio Revision 28 Deprecated Avx512VoltageScaleFactor and Avx3RatioOffset Revision 29 Add SaPllFreqOverride Revision 30 Add PllMaxBandingRatio Revision 31 Add TscDisableHwFixup Revision 32 Add IaIccUnlimitedMode & IaIccMax & GtIccUnlimitedMode & GtIccMax and deprecated UnlimitedIccMax Revision 33 Add TvbDownBinsTempThreshold0, TvbDownBinsTempThreshold1, TvbTempThreshold0, TvbTempThreshold1 Revision 34 Deprecated PllMaxBandingRatio Revision 35 Add FllOcModeEn Revision 36 Deprecated DisablePerAtomMask (DisablePerCoreMask is used for both the cores) Revision 37 Add Etvb

Definition at line 132 of file OverclockingConfig.h.

Member Data Documentation

◆ AtomClusterRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::AtomClusterRatio[CPU_MAX_ATOM_CLUSTERS]

The Atom cluster max ratio overrides.

Default: 0 Range: 0 to 120.

Definition at line 342 of file OverclockingConfig.h.

◆ AtomL2MaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::AtomL2MaxOcRatio

Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).

0. no override/HW defaults.. non-turbo max - 120. deprecated from version 27

Definition at line 210 of file OverclockingConfig.h.

◆ AtomL2VoltageAdaptive

UINT16 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageAdaptive

Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operating in turbo mode range.

Used when AtomL2VoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 361 of file OverclockingConfig.h.

◆ AtomL2VoltageMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageMode

Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating.

0: Adaptive Mode allows the atom processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 348 of file OverclockingConfig.h.

◆ AtomL2VoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOffset

The atom L2 voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 366 of file OverclockingConfig.h.

◆ AtomL2VoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOverride

The atom L2 voltage override which is applied to the entire range of atom core frequencies.

Used when AtomL2VoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 355 of file OverclockingConfig.h.

◆ Avx2VoltageScaleFactor

UINT8 OVERCLOCKING_PREMEM_CONFIG::Avx2VoltageScaleFactor

Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads.

Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. A value of 0 means no scale factor applied (no change to voltage on AVX commands) A value of 100 applies the default voltage guardband values (1.0 factor). A value > 100 will increase the voltage guardband on AVX2 workloads. A value < 100 will decrease the voltage guardband on AVX2 workloads.

0. No scale factor applied

Definition at line 304 of file OverclockingConfig.h.

◆ Avx512VoltageScaleFactor

UINT8 OVERCLOCKING_PREMEM_CONFIG::Avx512VoltageScaleFactor

Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads.

Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. A value of 0 means no scale factor applied (no change to voltage on AVX commands) A value of 100 applies the default voltage guardband values (1.0 factor). A value > 100 will increase the voltage guardband on AVX512 workloads. A value < 100 will decrease the voltage guardband on AVX512 workloads.

0. No scale factor applied deprecated from version 28

Definition at line 316 of file OverclockingConfig.h.

◆ CoreMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::CoreMaxOcRatio

Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).

0. no override/HW defaults.. Range non-turbo max - 120 (Previously max turbo is 83).

Definition at line 199 of file OverclockingConfig.h.

◆ CoreVfConfigScope

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVfConfigScope

Core VF Configuration Scope.

Alows both all-core VF curve or per-core VF curve configuration. 0: All-core Scope, setting the VF curve for all cores. 1: Per-core Scope, setting the VF curve per-core.

Definition at line 184 of file OverclockingConfig.h.

◆ CoreVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the Core Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts.

Definition at line 321 of file OverclockingConfig.h.

◆ CoreVfPointOffsetMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffsetMode

Deprecated < Fivr Efficiency Management. 0: Disabled, 1: Enabled.

Selects Core Voltage & Frequency Offset between Legacy and Selection modes. Need Reset System after enabling OverClocking Feature to Initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection Mode, setting a selected VF point.

Definition at line 177 of file OverclockingConfig.h.

◆ CoreVoltageAdaptive

UINT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageAdaptive

Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.

Used when CoreVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 222 of file OverclockingConfig.h.

◆ CoreVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageMode

Core voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 148 of file OverclockingConfig.h.

◆ CoreVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOffset

The core voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 227 of file OverclockingConfig.h.

◆ CoreVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOverride

The core voltage override which is applied to the entire range of cpu core frequencies.

Used when CoreVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 216 of file OverclockingConfig.h.

◆ DisablePerAtomMask

UINT32 OVERCLOCKING_PREMEM_CONFIG::DisablePerAtomMask

Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCoreCount is to set the number of active atoms.

Each bit represents logical core id: 1 - Disable 0 - Ignored Defalut is 0, means no Small Core disable mask setting.

Definition at line 418 of file OverclockingConfig.h.

◆ DisablePerCoreMask

UINT32 OVERCLOCKING_PREMEM_CONFIG::DisablePerCoreMask

Core disable mask is a bitwise indication of which core should be disabled.

Each bit represents physical core id for both P-core and E-core: 1 - Disable 0 - Ignored Default is 0, means no Core disable mask setting.

Definition at line 410 of file OverclockingConfig.h.

◆ IaIccMax

UINT16 OVERCLOCKING_PREMEM_CONFIG::IaIccMax

Voltage Regulator Current Limit (Icc Max) for IA and GT.

This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 4. Range is 4-2047.

Definition at line 450 of file OverclockingConfig.h.

◆ OcSupport

UINT32 OVERCLOCKING_PREMEM_CONFIG::OcSupport

Overclocking support.

This controls whether OC mailbox transactions are sent. If disabled, all policies in this config block besides OcSupport and OcLock will be ignored. 0: Disable; 1: Enable.

Note
If PcdOverclockEnable is disabled, this should also be disabled.

Definition at line 141 of file OverclockingConfig.h.

◆ PerCoreHtDisable

UINT16 OVERCLOCKING_PREMEM_CONFIG::PerCoreHtDisable

Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.

Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.

Definition at line 292 of file OverclockingConfig.h.

◆ PerCoreVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::PerCoreVoltageOffset[CPU_MAX_BIG_CORES]

Array used to specifies the selected Core Offset Voltage.

This voltage is specified in millivolts.

Definition at line 335 of file OverclockingConfig.h.

◆ PllMaxBandingRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::PllMaxBandingRatio

The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains.

0. Hardware Default/No Override. Minimum must be greater than P0 and maximum is 120.

Definition at line 443 of file OverclockingConfig.h.

◆ PvdMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::PvdMode

PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0).

0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock) 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)

Definition at line 431 of file OverclockingConfig.h.

◆ PvdRatioThreshold

UINT8 OVERCLOCKING_PREMEM_CONFIG::PvdRatioThreshold

The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range.

This threshold is applied to all the domains (Cores, Ring, SA, Memory and GT). 0. Default/No Override. Range 1-63.

Definition at line 425 of file OverclockingConfig.h.

◆ RingDownBin

UINT32 OVERCLOCKING_PREMEM_CONFIG::RingDownBin

Ring Downbin enable/disable.

When enabled, the CPU will force the ring ratio to be lower than the core ratio. Disabling will allow the ring and core ratios to run at the same frequency. Uses OC Mailbox command 0x19. 0: Disables Ring Downbin feature. 1: Enables Ring downbin feature.

Definition at line 160 of file OverclockingConfig.h.

◆ RingMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::RingMaxOcRatio

Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.

0. no override/HW defaults.. Range non-turbo max - 85.

Definition at line 205 of file OverclockingConfig.h.

◆ RingVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the Ring Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts.

Definition at line 395 of file OverclockingConfig.h.

◆ RingVfPointOffsetMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffsetMode

Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.

Need Reset System after enabling OverClocking Feature to Initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection modes, setting a selected VF point.

Definition at line 385 of file OverclockingConfig.h.

◆ RingVoltageAdaptive

UINT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageAdaptive

Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range.

Used when RingVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 239 of file OverclockingConfig.h.

◆ RingVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::RingVoltageMode

Ring voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 166 of file OverclockingConfig.h.

◆ RingVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageOffset

The ring voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 244 of file OverclockingConfig.h.

◆ RingVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageOverride

The ring voltage override which is applied to the entire range of cpu ring frequencies.

Used when RingVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 233 of file OverclockingConfig.h.

◆ SaExtraTurboVoltage

UINT16 OVERCLOCKING_PREMEM_CONFIG::SaExtraTurboVoltage

Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is operating in turbo mode range.

Used when SaVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 378 of file OverclockingConfig.h.

◆ SaVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::SaVoltageMode

SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 192 of file OverclockingConfig.h.

◆ SaVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::SaVoltageOverride

The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.

Used when SaVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 372 of file OverclockingConfig.h.

◆ TjMaxOffset

UINT8 OVERCLOCKING_PREMEM_CONFIG::TjMaxOffset

TjMax Offset.

Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Default: 0 Hardware Defaults Range 10 to 63. 0 = No offset / Keep HW default.

Definition at line 267 of file OverclockingConfig.h.

◆ TvbDownBinsTempThreshold0

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold0

Down Bins (delta) for Temperature Threshold 0.

When running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 1 . Range 0-10.

Definition at line 457 of file OverclockingConfig.h.

◆ TvbDownBinsTempThreshold1

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold1

Down Bins (delta) for Temperature Threshold 1.

When running above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 0-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 2 . Range 0-10.

Definition at line 475 of file OverclockingConfig.h.

◆ TvbRatioClipping

UINT32 OVERCLOCKING_PREMEM_CONFIG::TvbRatioClipping

This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature.

It is required to be disabled for supporting overclocking at frequencies higher than the default max turbo frequency. 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping.

Definition at line 275 of file OverclockingConfig.h.

◆ TvbTempThreshold0

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold0

TVB Temp (degrees C) - Temperature Threshold 0.

Running ABOVE this temperature will clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 70 . Range 0-100.

Definition at line 463 of file OverclockingConfig.h.

◆ TvbTempThreshold1

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold1

TVB Temp (degrees C) - Temperature Threshold 1.

Running ABOVE this temperature, clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 100 . Range 0-100.

Definition at line 469 of file OverclockingConfig.h.

◆ TvbVoltageOptimization

UINT32 OVERCLOCKING_PREMEM_CONFIG::TvbVoltageOptimization

This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature.

0: Disables TVB voltage optimization. 1: Enables TVB voltage optimization.

Definition at line 281 of file OverclockingConfig.h.

The documentation for this struct was generated from the following file:
  • OverclockingConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

OVERCLOCKING_PREMEM_CONFIG Member List

This is the complete list of members for OVERCLOCKING_PREMEM_CONFIG, including all inherited members.

AtomClusterRatio | OVERCLOCKING_PREMEM_CONFIG
AtomL2MaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageAdaptive | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageMode | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageOffset | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageOverride | OVERCLOCKING_PREMEM_CONFIG
AtomPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
Avx2RatioOffset | OVERCLOCKING_PREMEM_CONFIG
Avx2VoltageScaleFactor | OVERCLOCKING_PREMEM_CONFIG
Avx3RatioOffset | OVERCLOCKING_PREMEM_CONFIG
Avx512VoltageScaleFactor | OVERCLOCKING_PREMEM_CONFIG
BclkAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
CoreMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
CorePllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
CoreRatioExtensionMode | OVERCLOCKING_PREMEM_CONFIG
CoreVfConfigScope | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointCount | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageAdaptive | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageMode | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
CpuBclkOcFrequency | OVERCLOCKING_PREMEM_CONFIG
DisablePerAtomMask | OVERCLOCKING_PREMEM_CONFIG
DisablePerCoreMask | OVERCLOCKING_PREMEM_CONFIG
DlvrBypassModeEnable | OVERCLOCKING_PREMEM_CONFIG
Etvb | OVERCLOCKING_PREMEM_CONFIG
FivrEfficiency | OVERCLOCKING_PREMEM_CONFIG
FllOcModeEn | OVERCLOCKING_PREMEM_CONFIG
FllOverclockMode | OVERCLOCKING_PREMEM_CONFIG
GtCepEnable | OVERCLOCKING_PREMEM_CONFIG
GtExtraTurboVoltage | OVERCLOCKING_PREMEM_CONFIG
GtIccUnlimitedMode | OVERCLOCKING_PREMEM_CONFIG
GtMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
GtPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
GtVoltageMode | OVERCLOCKING_PREMEM_CONFIG
GtVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
GtVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
Header | OVERCLOCKING_PREMEM_CONFIG
IaCepEnable | OVERCLOCKING_PREMEM_CONFIG
IaIccMax | OVERCLOCKING_PREMEM_CONFIG
IaIccUnlimitedMode | OVERCLOCKING_PREMEM_CONFIG
IaSirpEnable | OVERCLOCKING_PREMEM_CONFIG
ItdThrottleEnable | OVERCLOCKING_PREMEM_CONFIG
McPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
OcLock | OVERCLOCKING_PREMEM_CONFIG
OcSupport | OVERCLOCKING_PREMEM_CONFIG
PerAtomClusterVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
PerCoreHtDisable | OVERCLOCKING_PREMEM_CONFIG
PerCoreRatioOverride | OVERCLOCKING_PREMEM_CONFIG
PerCoreVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
PllMaxBandingRatio | OVERCLOCKING_PREMEM_CONFIG
PvdMode | OVERCLOCKING_PREMEM_CONFIG
PvdRatioThreshold | OVERCLOCKING_PREMEM_CONFIG
RealtimeMemoryTiming | OVERCLOCKING_PREMEM_CONFIG
RingDownBin | OVERCLOCKING_PREMEM_CONFIG
RingMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
RingPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
RingVfPointCount | OVERCLOCKING_PREMEM_CONFIG
RingVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
RingVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
RingVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
RingVoltageAdaptive | OVERCLOCKING_PREMEM_CONFIG
RingVoltageMode | OVERCLOCKING_PREMEM_CONFIG
RingVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
RingVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
RsvdByte2 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte3 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte4 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte5 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte6 | OVERCLOCKING_PREMEM_CONFIG
SaCepEnable | OVERCLOCKING_PREMEM_CONFIG
SaExtraTurboVoltage | OVERCLOCKING_PREMEM_CONFIG
SaPllFreqOverride | OVERCLOCKING_PREMEM_CONFIG
SaPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
SaVoltageMode | OVERCLOCKING_PREMEM_CONFIG
SaVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
SaVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
SocBclkOcFrequency | OVERCLOCKING_PREMEM_CONFIG
TjMaxOffset | OVERCLOCKING_PREMEM_CONFIG
TscDisableHwFixup | OVERCLOCKING_PREMEM_CONFIG
TvbDownBinsTempThreshold0 | OVERCLOCKING_PREMEM_CONFIG
TvbDownBinsTempThreshold1 | OVERCLOCKING_PREMEM_CONFIG
TvbRatioClipping | OVERCLOCKING_PREMEM_CONFIG
TvbTempThreshold0 | OVERCLOCKING_PREMEM_CONFIG
TvbTempThreshold1 | OVERCLOCKING_PREMEM_CONFIG
TvbVoltageOptimization | OVERCLOCKING_PREMEM_CONFIG
UnlimitedIccMax | OVERCLOCKING_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_DCI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_DCI_PREMEM_CONFIG Struct Reference

The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI) More...

#include <DciConfig.h>

Collaboration diagram for PCH_DCI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | DciEn
DCI enable. More...
UINT8 | DciDbcMode
USB DbC enable mode. More...
UINT8 | DciModphyPg
Deprecated.
UINT8 | DciUsb3TypecUfpDbg
USB3 Type-C UFP2DFP kenel / platform debug support. More...
UINT8 | DciClkEnable
Determine if to enable or disable DCI clock request in lowest power state. More...
UINT8 | KeepEarlyTrace
Early trace is activated by default. More...

Detailed Description

The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)

Revision 1:

  • Initial version. Revision 2:
  • Added DciModphyPg
  • change to use data in byte unit rather than bit-field Revision 3:
  • Deprecated DciModphyPg
  • Added DciClkEnable, KeepEarlyTrace

Definition at line 71 of file DciConfig.h.

Member Data Documentation

◆ DciClkEnable

UINT8 PCH_DCI_PREMEM_CONFIG::DciClkEnable

Determine if to enable or disable DCI clock request in lowest power state.

0:Disabled; 1:Enabled

Definition at line 99 of file DciConfig.h.

◆ DciDbcMode

UINT8 PCH_DCI_PREMEM_CONFIG::DciDbcMode

USB DbC enable mode.

Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value Refer to definition of DCI_USB_DBC_MODE for supported settings. 0:Disabled; 1:USB2; 2:USB3; 3:Both; 4:No Change

Definition at line 85 of file DciConfig.h.

◆ DciEn

UINT8 PCH_DCI_PREMEM_CONFIG::DciEn

DCI enable.

Determine if to enable DCI debug from host. 0:Disabled; 1:Enabled

Definition at line 78 of file DciConfig.h.

◆ DciUsb3TypecUfpDbg

UINT8 PCH_DCI_PREMEM_CONFIG::DciUsb3TypecUfpDbg

USB3 Type-C UFP2DFP kenel / platform debug support.

No change will do nothing to UFP2DFP configuration. When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP (downstream-facing port) for first connection. It must be enabled for USB3 kernel(kernel mode debug) and platform debug(DFx, DMA, Trace) over UFP Type-C receptacle. Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported settings. 0:Disabled; 1:Enabled; 2:No Change

Definition at line 94 of file DciConfig.h.

◆ KeepEarlyTrace

UINT8 PCH_DCI_PREMEM_CONFIG::KeepEarlyTrace

Early trace is activated by default.

Enable to keep early trace data and keep tracing; disable to stop tracing; When debug probe is connected and granted, force to no change, let host tool to set it. 0: Disable; 1: Enable early trace; 2:No Change;

Definition at line 106 of file DciConfig.h.

The documentation for this struct was generated from the following file:
  • DciConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_DCI_PREMEM_CONFIG Member List

This is the complete list of members for PCH_DCI_PREMEM_CONFIG, including all inherited members.

DciClkEnable | PCH_DCI_PREMEM_CONFIG
DciDbcMode | PCH_DCI_PREMEM_CONFIG
DciEn | PCH_DCI_PREMEM_CONFIG
DciModphyPg | PCH_DCI_PREMEM_CONFIG
DciUsb3TypecUfpDbg | PCH_DCI_PREMEM_CONFIG
Header | PCH_DCI_PREMEM_CONFIG
KeepEarlyTrace | PCH_DCI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

Public Attributes | List of all members
PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...

#include <InterruptConfig.h>

Public Attributes

UINT8 | Device
Device number.
UINT8 | Function
Device function.
UINT8 | IntX
Interrupt pin: INTA-INTD (see PCH_INT_PIN)
UINT8 | Irq
IRQ to be set for device.

Detailed Description

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.

Definition at line 57 of file InterruptConfig.h.

The documentation for this struct was generated from the following file:
  • InterruptConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_DEVICE_INTERRUPT_CONFIG Member List

This is the complete list of members for PCH_DEVICE_INTERRUPT_CONFIG, including all inherited members.

Device | PCH_DEVICE_INTERRUPT_CONFIG
Function | PCH_DEVICE_INTERRUPT_CONFIG
IntX | PCH_DEVICE_INTERRUPT_CONFIG
Irq | PCH_DEVICE_INTERRUPT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_DMI_CONFIG Struct Reference

Public Attributes | List of all members
PCH_DMI_CONFIG Struct Reference

The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. More...

#include <PchDmiConfig.h>

Collaboration diagram for PCH_DMI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PwrOptEnable: 1
0: Disable; 1: Enable DMI Power Optimizer on PCH side.
UINT32 | DmiAspmCtrl: 8
ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
UINT32 | CwbEnable: 1
0: Disable; 1: Enable Central Write Buffer feature configurable and enabled by default
UINT32 | L1RpCtl: 1
0: Disable; 1: Enable Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
UINT32 | DmiPowerReduction: 1
When set to TRUE turns on: More...
UINT32 | ClockGating: 1
0: Disable; 1: Enable clock gating.
UINT32 | Rsvdbits: 19
Reserved bits.

Detailed Description

The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.

Revision 1:

  • Initial version.

Definition at line 73 of file PchDmiConfig.h.

Member Data Documentation

◆ DmiPowerReduction

UINT32 PCH_DMI_CONFIG::DmiPowerReduction

When set to TRUE turns on:

  • L1 State Controller Power Gating
  • L1 State PHY Data Lane Power Gating
  • PHY Common Lane Power Gating
  • Hardware Autonomous Enable
  • PMC Request Enable and Sleep Enable

Definition at line 88 of file PchDmiConfig.h.

The documentation for this struct was generated from the following file:
  • PchDmiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_DMI_CONFIG Member List

This is the complete list of members for PCH_DMI_CONFIG, including all inherited members.

ClockGating | PCH_DMI_CONFIG
CwbEnable | PCH_DMI_CONFIG
DmiAspmCtrl | PCH_DMI_CONFIG
DmiPowerReduction | PCH_DMI_CONFIG
Header | PCH_DMI_CONFIG
L1RpCtl | PCH_DMI_CONFIG
PwrOptEnable | PCH_DMI_CONFIG
Rsvdbits | PCH_DMI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_DMI_EQ_PARAM Struct Reference

Public Attributes | List of all members
PCH_DMI_EQ_PARAM Struct Reference

Lane specific Dmi Gen3, Gen4 equalization parameters. More...

#include <PchDmiConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | Rsvd0 [2]
Reserved bytes.

Detailed Description

Lane specific Dmi Gen3, Gen4 equalization parameters.

Definition at line 54 of file PchDmiConfig.h.

The documentation for this struct was generated from the following file:
  • PchDmiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_DMI_EQ_PARAM Member List

This is the complete list of members for PCH_DMI_EQ_PARAM, including all inherited members.

Cm | PCH_DMI_EQ_PARAM
Cp | PCH_DMI_EQ_PARAM
Rsvd0 | PCH_DMI_EQ_PARAM
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_ESPI_CONFIG Struct Reference

Public Attributes | List of all members
PCH_ESPI_CONFIG Struct Reference

This structure contains the policies which are related to ESPI. More...

#include <EspiConfig.h>

Collaboration diagram for PCH_ESPI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | LgmrEnable: 1
LPC (eSPI) Memory Range Decode Enable. More...
UINT32 | BmeMasterSlaveEnabled: 1
eSPI host and device BME settings. More...
UINT32 | HostC10ReportEnable: 1
Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE) 0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ignored) 1b: Enable HOST_C10 reporting to device via eSPI Virtual Wire (upon receiving a HOST_C10 indication from PMC)
UINT32 | LockLinkConfiguration: 1
eSPI Link Configuration Lock (SBLCL) If set to TRUE then communication through SET_CONFIG/GET_CONFIG to eSPI device addresses from range 0x0 - 0x7FF 1: TRUE, 0: FALSE
UINT32 | EspiPmHAE: 1
Hardware Autonomous Enable (HAE) If set to TRUE, then the IP may request a PG whenever it is idle.
UINT32 | RsvdBits: 27
Reserved bits.

Detailed Description

This structure contains the policies which are related to ESPI.

Revision 1:

  • Initial revision Revision 2:
  • Added LockLinkConfiguration field to config block

Definition at line 51 of file EspiConfig.h.

Member Data Documentation

◆ BmeMasterSlaveEnabled

UINT32 PCH_ESPI_CONFIG::BmeMasterSlaveEnabled

eSPI host and device BME settings.

When TRUE, then the BME bit enabled in eSPI host and device. 0: FALSE, 1: TRUE

Definition at line 64 of file EspiConfig.h.

◆ LgmrEnable

UINT32 PCH_ESPI_CONFIG::LgmrEnable

LPC (eSPI) Memory Range Decode Enable.

When TRUE, then the range specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI). 0: FALSE, 1: TRUE

Definition at line 58 of file EspiConfig.h.

The documentation for this struct was generated from the following file:
  • EspiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_ESPI_CONFIG Member List

This is the complete list of members for PCH_ESPI_CONFIG, including all inherited members.

BmeMasterSlaveEnabled | PCH_ESPI_CONFIG
EspiPmHAE | PCH_ESPI_CONFIG
Header | PCH_ESPI_CONFIG
HostC10ReportEnable | PCH_ESPI_CONFIG
LgmrEnable | PCH_ESPI_CONFIG
LockLinkConfiguration | PCH_ESPI_CONFIG
RsvdBits | PCH_ESPI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_FIVR_CONFIG Struct Reference

Public Attributes | List of all members
PCH_FIVR_CONFIG Struct Reference

The PCH_FIVR_CONFIG block describes FIVR settings. More...

#include <FivrConfig.h>

Collaboration diagram for PCH_FIVR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
FIVR_EXT_RAIL_CONFIG ExtV1p05Rail
External V1P05 VR rail configuration.
FIVR_EXT_RAIL_CONFIG ExtVnnRail
External Vnn VR rail configuration.
FIVR_EXT_RAIL_CONFIG ExtVnnRailSx
Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback. More...
FIVR_VCCIN_AUX_CONFIG VccinAux
VCCIN_AUX voltage rail configuration.
UINT32 | FivrDynPm: 1
Enable/Disable FIVR Dynamic Power Management Default is 1 .
UINT32 | BypassFivrConfig: 1
Enable/Disable Bypass of FIVR configuration Default is 0 .

Detailed Description

The PCH_FIVR_CONFIG block describes FIVR settings.

Definition at line 176 of file FivrConfig.h.

Member Data Documentation

◆ ExtVnnRailSx

FIVR_EXT_RAIL_CONFIG PCH_FIVR_CONFIG::ExtVnnRailSx

Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback.

Required only if External Vnn VR needs different settings for Sx than those specified in ExtVnnRail.

Definition at line 191 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_FIVR_CONFIG Member List

This is the complete list of members for PCH_FIVR_CONFIG, including all inherited members.

BypassFivrConfig | PCH_FIVR_CONFIG
ExtV1p05Rail | PCH_FIVR_CONFIG
ExtVnnRail | PCH_FIVR_CONFIG
ExtVnnRailSx | PCH_FIVR_CONFIG
FivrDynPm | PCH_FIVR_CONFIG
Header | PCH_FIVR_CONFIG
VccinAux | PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_GENERAL_CONFIG Struct Reference

Public Attributes | List of all members
PCH_GENERAL_CONFIG Struct Reference

PCH General Configuration Revision 1: - Initial version. More...

#include <PchGeneralConfig.h>

Collaboration diagram for PCH_GENERAL_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Crid: 1
This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be enabled. More...
UINT32 | LegacyIoLowLatency: 1
Set to enable low latency of legacy IO. More...
UINT32 | AcpiL6dPmeHandling: 1
Enables _L6D ACPI handler. More...
UINT32 | RsvdBits0: 29
Reserved bits.

Detailed Description

PCH General Configuration Revision 1: - Initial version.

Revision 2: - Added AcpiL6dPmeHandling

Definition at line 56 of file PchGeneralConfig.h.

Member Data Documentation

◆ AcpiL6dPmeHandling

UINT32 PCH_GENERAL_CONFIG::AcpiL6dPmeHandling

Enables _L6D ACPI handler.

PME GPE is shared by multiple devices So BIOS must verify the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit 0: Disable, 1: Enable

Definition at line 77 of file PchGeneralConfig.h.

◆ Crid

UINT32 PCH_GENERAL_CONFIG::Crid

This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be enabled.

0: Disable; 1: Enable

Definition at line 62 of file PchGeneralConfig.h.

◆ LegacyIoLowLatency

UINT32 PCH_GENERAL_CONFIG::LegacyIoLowLatency

Set to enable low latency of legacy IO.

Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency.

Note
: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent and ITSS Clock Gating are forced to disabled. 0: Disable, 1: Enable

Definition at line 71 of file PchGeneralConfig.h.

The documentation for this struct was generated from the following file:
  • PchGeneralConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_GENERAL_CONFIG Member List

This is the complete list of members for PCH_GENERAL_CONFIG, including all inherited members.

AcpiL6dPmeHandling | PCH_GENERAL_CONFIG
Crid | PCH_GENERAL_CONFIG
Header | PCH_GENERAL_CONFIG
LegacyIoLowLatency | PCH_GENERAL_CONFIG
RsvdBits0 | PCH_GENERAL_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_GENERAL_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_GENERAL_PREMEM_CONFIG Struct Reference

PCH General Pre-Memory Configuration Revision 1: - Initial version. More...

#include <PchGeneralConfig.h>

Collaboration diagram for PCH_GENERAL_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Port80Route: 1
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
UINT32 | IotgPllSscEn: 1
Need to disable CPU Side SSC for A0 PO.
UINT32 | GpioOverride: 3
Gpio override Level – 0: Disable;. More...
UINT32 | IoeDebugEn: 1
Enable/Disable IOE Debug. More...
UINT32 | PmodeClkEn: 1
Enable/Disable PMODE clock. More...
UINT32 | RsvdBits0: 25
Reserved bits.

Detailed Description

PCH General Pre-Memory Configuration Revision 1: - Initial version.

Revision 2: - Added GpioOverride. Revision 3: - Added IoeDebugEn, PmodeClkEn

Definition at line 87 of file PchGeneralConfig.h.

Member Data Documentation

◆ GpioOverride

UINT32 PCH_GENERAL_PREMEM_CONFIG::GpioOverride

Gpio override Level – 0: Disable;.

  • 1: Override Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase
  • 2: Override Level 2 - Reserved for future use

Definition at line 100 of file PchGeneralConfig.h.

◆ IoeDebugEn

UINT32 PCH_GENERAL_PREMEM_CONFIG::IoeDebugEn

Enable/Disable IOE Debug.

When enabled, IOE D2D Dfx link and clock will keep up for debug 0: Disable; 1: Enable

Definition at line 105 of file PchGeneralConfig.h.

◆ PmodeClkEn

UINT32 PCH_GENERAL_PREMEM_CONFIG::PmodeClkEn

Enable/Disable PMODE clock.

When enabled, Pmode clock will toggle for XDP use 0: Disable; 1: Enable

Definition at line 110 of file PchGeneralConfig.h.

The documentation for this struct was generated from the following file:
  • PchGeneralConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_GENERAL_PREMEM_CONFIG Member List

This is the complete list of members for PCH_GENERAL_PREMEM_CONFIG, including all inherited members.

GpioOverride | PCH_GENERAL_PREMEM_CONFIG
Header | PCH_GENERAL_PREMEM_CONFIG
IoeDebugEn | PCH_GENERAL_PREMEM_CONFIG
IotgPllSscEn | PCH_GENERAL_PREMEM_CONFIG
PmodeClkEn | PCH_GENERAL_PREMEM_CONFIG
Port80Route | PCH_GENERAL_PREMEM_CONFIG
RsvdBits0 | PCH_GENERAL_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_INTERRUPT_CONFIG Struct Reference

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PCH_INTERRUPT_CONFIG Struct Reference

The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. More...

#include <InterruptConfig.h>

Collaboration diagram for PCH_INTERRUPT_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | NumOfDevIntConfig
Number of entries in DevIntConfig table.
UINT8 | Rsvd0 [3]
Reserved bytes, align to multiple 4.
PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig [PCH_MAX_DEVICE_INTERRUPT_CONFIG]
Array which stores PCH devices interrupts settings.
UINT8 | GpioIrqRoute
Interrupt routing for GPIO. Default is 14.
UINT8 | SciIrqSelect
Interrupt select for SCI. Default is 9.
UINT8 | TcoIrqSelect
Interrupt select for TCO. Default is 9.
UINT8 | TcoIrqEnable
Enable IRQ generation for TCO. 0: Disable; 1: Enable.

Detailed Description

The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.

Definition at line 73 of file InterruptConfig.h.

The documentation for this struct was generated from the following file:
  • InterruptConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_INTERRUPT_CONFIG Member List

This is the complete list of members for PCH_INTERRUPT_CONFIG, including all inherited members.

DevIntConfig | PCH_INTERRUPT_CONFIG
GpioIrqRoute | PCH_INTERRUPT_CONFIG
Header | PCH_INTERRUPT_CONFIG
NumOfDevIntConfig | PCH_INTERRUPT_CONFIG
Rsvd0 | PCH_INTERRUPT_CONFIG
SciIrqSelect | PCH_INTERRUPT_CONFIG
TcoIrqEnable | PCH_INTERRUPT_CONFIG
TcoIrqSelect | PCH_INTERRUPT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_IOAPIC_CONFIG Struct Reference

Public Attributes | List of all members
PCH_IOAPIC_CONFIG Struct Reference

The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE. More...

#include <IoApicConfig.h>

Collaboration diagram for PCH_IOAPIC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | IoApicEntry24_119: 1
0: Disable; 1: Enable IOAPIC Entry 24-119
UINT32 | Enable8254ClockGating: 1
Enable 8254 Static Clock Gating during early POST time. More...
UINT32 | Enable8254ClockGatingOnS3: 1
Enable 8254 Static Clock Gating on S3 resume path. More...
UINT32 | RsvdBits1: 29
Reserved bits.
UINT8 | IoApicId
This member determines IOAPIC ID. Default is 0x02.
UINT8 | Rsvd0 [3]
Reserved bytes.

Detailed Description

The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE.

Bus:device:function fields will be programmed to the register P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose: As the Requester ID when initiating Interrupt Messages to the processor. As the Completer ID when responding to the reads targeting the IOxAPI's Memory-Mapped I/O registers. This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this field to provide a unique Bus:Device:Function number for the internal IOxAPIC. The address resource range of IOAPIC must be reserved in E820 and ACPI as system resource.

Definition at line 57 of file IoApicConfig.h.

Member Data Documentation

◆ Enable8254ClockGating

UINT32 PCH_IOAPIC_CONFIG::Enable8254ClockGating

Enable 8254 Static Clock Gating during early POST time.

0: Disable, 1: Enable Setting 8254CGE is required to support SLP_S0. Enable this if 8254 timer is not used. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer.

Note
: For some OS environment that it needs to set 8254CGE in late state it should set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in SMM later. This is also required during S3 resume. To avoid SMI requirement in S3 reusme path, it can enable the Enable8254ClockGatingOnS3 and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_SAI.

Definition at line 73 of file IoApicConfig.h.

◆ Enable8254ClockGatingOnS3

UINT32 PCH_IOAPIC_CONFIG::Enable8254ClockGatingOnS3

Enable 8254 Static Clock Gating on S3 resume path.

0: Disable, 1: Enable This is only applicable when Enable8254ClockGating is disabled. If Enable8254ClockGating is enabled, RC will do the 8254 CGE programming on S3 resume path as well.

Definition at line 80 of file IoApicConfig.h.

The documentation for this struct was generated from the following file:
  • IoApicConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_IOAPIC_CONFIG Member List

This is the complete list of members for PCH_IOAPIC_CONFIG, including all inherited members.

Enable8254ClockGating | PCH_IOAPIC_CONFIG
Enable8254ClockGatingOnS3 | PCH_IOAPIC_CONFIG
Header | PCH_IOAPIC_CONFIG
IoApicEntry24_119 | PCH_IOAPIC_CONFIG
IoApicId | PCH_IOAPIC_CONFIG
Rsvd0 | PCH_IOAPIC_CONFIG
RsvdBits1 | PCH_IOAPIC_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_LOCK_DOWN_CONFIG Struct Reference

Public Attributes | List of all members
PCH_LOCK_DOWN_CONFIG Struct Reference

The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement. More...

#include <LockDownConfig.h>

Collaboration diagram for PCH_LOCK_DOWN_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | GlobalSmi: 1
(Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. More...
UINT32 | BiosInterface: 1
(Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register Top Swap bit and the General Control and Status Registers Boot BIOS Straps. More...
UINT32 | BiosLock: 1
Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. More...
UINT32 | SpiEiss: 1
Separate EISS policy to be handled separately from BiosLock.
UINT32 | UnlockGpioPads: 1
(Test) This test option when set will force all GPIO pads to be unlocked before BIOS transitions to POSTBOOT_SAI. More...
UINT32 | RsvdBits0: 27
Reserved bits.

Detailed Description

The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement.

Definition at line 47 of file LockDownConfig.h.

Member Data Documentation

◆ BiosInterface

UINT32 PCH_LOCK_DOWN_CONFIG::BiosInterface

(Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register Top Swap bit and the General Control and Status Registers Boot BIOS Straps.

Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit will mitigate malicious software attempts to replace the system BIOS with its own code. 0: Disable; 1: Enable.

Definition at line 60 of file LockDownConfig.h.

◆ BiosLock

UINT32 PCH_LOCK_DOWN_CONFIG::BiosLock

Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection.

When it is enabled, the BIOS Region can only be modified from SMM. If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also in order to write to BIOS regions of SPI Flash. If this EISS bit is clear, then the InSMM.STS is a don't care. The BIOS must set the EISS bit while BIOS Guard support is enabled. In recovery path, platform can temporary disable EISS for SPI programming in PEI phase or early DXE phase. When PcdSmmVariableEnable is FALSE, to support BIOS regions update outside of SMM, the BiosLock must be set to Disabled by platform. 0: Disable; 1: Enable.

Definition at line 75 of file LockDownConfig.h.

◆ GlobalSmi

UINT32 PCH_LOCK_DOWN_CONFIG::GlobalSmi

(Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.

0: Disable; 1: Enable.

Definition at line 52 of file LockDownConfig.h.

◆ UnlockGpioPads

UINT32 PCH_LOCK_DOWN_CONFIG::UnlockGpioPads

(Test) This test option when set will force all GPIO pads to be unlocked before BIOS transitions to POSTBOOT_SAI.

This option should not be enabled in production configuration and used only for debug purpose when free runtime reconfiguration of GPIO pads is needed. 0: Disable; 1: Enable.

Definition at line 84 of file LockDownConfig.h.

The documentation for this struct was generated from the following file:
  • LockDownConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_LOCK_DOWN_CONFIG Member List

This is the complete list of members for PCH_LOCK_DOWN_CONFIG, including all inherited members.

BiosInterface | PCH_LOCK_DOWN_CONFIG
BiosLock | PCH_LOCK_DOWN_CONFIG
GlobalSmi | PCH_LOCK_DOWN_CONFIG
Header | PCH_LOCK_DOWN_CONFIG
RsvdBits0 | PCH_LOCK_DOWN_CONFIG
SpiEiss | PCH_LOCK_DOWN_CONFIG
UnlockGpioPads | PCH_LOCK_DOWN_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_MEMORY_THROTTLING Struct Reference

Public Attributes | List of all members
PCH_MEMORY_THROTTLING Struct Reference

This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board). More...

#include <ThermalConfig.h>

Collaboration diagram for PCH_MEMORY_THROTTLING:
[legend]

Public Attributes

UINT32 | Enable: 1
This will enable PCH memory throttling. More...
TS_GPIO_PIN_SETTING | TsGpioPinSetting [2]
GPIO_C and GPIO_D selection for memory throttling. More...

Detailed Description

This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).

Definition at line 126 of file ThermalConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_MEMORY_THROTTLING::Enable

This will enable PCH memory throttling.

While this policy is enabled, must also enable EnableExtts in SA policy. 0: Disable; 1: Enable

Definition at line 132 of file ThermalConfig.h.

◆ TsGpioPinSetting

TS_GPIO_PIN_SETTING PCH_MEMORY_THROTTLING::TsGpioPinSetting[2]

GPIO_C and GPIO_D selection for memory throttling.

It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature, and route EXTTS# accordingly.

Definition at line 139 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_MEMORY_THROTTLING Member List

This is the complete list of members for PCH_MEMORY_THROTTLING, including all inherited members.

Enable | PCH_MEMORY_THROTTLING
TsGpioPinSetting | PCH_MEMORY_THROTTLING
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_P2SB_CONFIG Struct Reference

Public Attributes | List of all members
PCH_P2SB_CONFIG Struct Reference

This structure contains the policies which are related to P2SB device. More...

#include <P2sbConfig.h>

Collaboration diagram for PCH_P2SB_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | SbAccessUnlock: 1
(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execution. More...
UINT32 | Rsvdbits: 31
Reserved bits.

Detailed Description

This structure contains the policies which are related to P2SB device.

Definition at line 46 of file P2sbConfig.h.

Member Data Documentation

◆ SbAccessUnlock

UINT32 PCH_P2SB_CONFIG::SbAccessUnlock

(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execution.

Currently it disables PSFx access. This policy unlocks the sideband MMIO space for those IPs. 0: Lock sideband access ; 1: Unlock sideband access. NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.

Definition at line 56 of file P2sbConfig.h.

The documentation for this struct was generated from the following file:
  • P2sbConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_P2SB_CONFIG Member List

This is the complete list of members for PCH_P2SB_CONFIG, including all inherited members.

Header | PCH_P2SB_CONFIG
Rsvdbits | PCH_P2SB_CONFIG
SbAccessUnlock | PCH_P2SB_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_CLOCK Struct Reference

Public Attributes | List of all members
PCH_PCIE_CLOCK Struct Reference

PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. More...

#include <PchPcieRpConfig.h>

Public Attributes

UINT8 | Usage
Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF.
UINT8 | ClkReq
ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers.
UINT8 | RsvdBytes [2]
Reserved byte.

Detailed Description

PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.

Definition at line 177 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_PCIE_CLOCK Member List

This is the complete list of members for PCH_PCIE_CLOCK, including all inherited members.

ClkReq | PCH_PCIE_CLOCK
RsvdBytes | PCH_PCIE_CLOCK
Usage | PCH_PCIE_CLOCK
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PCIE_CONFIG Struct Reference

The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1: More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCH_PCIE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCIE_COMMON_CONFIG PcieCommonConfig
These members describe the configuration of each PCH PCIe root port.
UINT8 PchPciePort8xhDecodePortIndex
(Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based)

Detailed Description

The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1:

  • Initial version. Revision 2:
  • Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG

Definition at line 221 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_PCIE_CONFIG Member List

This is the complete list of members for PCH_PCIE_CONFIG, including all inherited members.

Header | PCH_PCIE_CONFIG
PchPciePort8xhDecodePortIndex | PCH_PCIE_CONFIG
PcieCommonConfig | PCH_PCIE_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_ROOT_PORT_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PCIE_ROOT_PORT_CONFIG Struct Reference

The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. More...

#include <PchPcieRpConfig.h>

Public Attributes

UINT8 | ExtSync
an instance of Pcie Common Config More...
UINT8 | SystemErrorEnable
Indicate whether the System Error is enabled. 0: Disable; 1: Enable.
UINT8 | MvcEnabled
The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC. More...
UINT8 | VppPort
Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins expansion is needed. More...
UINT8 | VppAddress
PCIe Hot Plug VPP SMBus Address. Default is zero.
UINT8 | RsvdBytes0 [3]
Reserved bytes.

Detailed Description

The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.

Definition at line 188 of file PchPcieRpConfig.h.

Member Data Documentation

◆ ExtSync

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::ExtSync

an instance of Pcie Common Config

Indicate whether the extended synch is enabled. 0: Disable; 1: Enable.

Definition at line 190 of file PchPcieRpConfig.h.

◆ MvcEnabled

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::MvcEnabled

The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.

Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0, RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be disabled. 0: Disable; 1: Enable

Definition at line 203 of file PchPcieRpConfig.h.

◆ VppPort

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::VppPort

Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins expansion is needed.

It is server specific feature. 0x00: Default; 0xFF: Disabled

Definition at line 209 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_PCIE_ROOT_PORT_CONFIG Member List

This is the complete list of members for PCH_PCIE_ROOT_PORT_CONFIG, including all inherited members.

ExtSync | PCH_PCIE_ROOT_PORT_CONFIG
MvcEnabled | PCH_PCIE_ROOT_PORT_CONFIG
RsvdBytes0 | PCH_PCIE_ROOT_PORT_CONFIG
SystemErrorEnable | PCH_PCIE_ROOT_PORT_CONFIG
VppAddress | PCH_PCIE_ROOT_PORT_CONFIG
VppPort | PCH_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PCIE_RP_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PCIE_RP_PREMEM_CONFIG Struct Reference

The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1: More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCH_PCIE_RP_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | RpEnabledMask
Root Port enabling mask. More...
PCH_PCIE_CLOCK | PcieClock [PCH_MAX_PCIE_CLOCKS]
Configuration of PCIe source clocks.
UINT8 | Bifurcation [PCH_MAX_PCIE_CONTROLLERS]
Per Controller Bifurcation Configuration 0: Disabled; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)

Detailed Description

The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1:

  • Initial version.

Definition at line 243 of file PchPcieRpConfig.h.

Member Data Documentation

◆ RpEnabledMask

UINT32 PCH_PCIE_RP_PREMEM_CONFIG::RpEnabledMask

Root Port enabling mask.

Bit0 presents RP1, Bit1 presents RP2, and so on. 0: Disable; 1: Enable.

Definition at line 250 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_PCIE_RP_PREMEM_CONFIG Member List

This is the complete list of members for PCH_PCIE_RP_PREMEM_CONFIG, including all inherited members.

Bifurcation | PCH_PCIE_RP_PREMEM_CONFIG
Header | PCH_PCIE_RP_PREMEM_CONFIG
PcieClock | PCH_PCIE_RP_PREMEM_CONFIG
RpEnabledMask | PCH_PCIE_RP_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_PM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PM_CONFIG Struct Reference

The PCH_PM_CONFIG block describes expected miscellaneous power management settings. More...

#include <PmConfig.h>

Collaboration diagram for PCH_PM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCH_WAKE_CONFIG WakeConfig
Specify Wake Policy.
UINT32 | PchDeepSxPol: 4
Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxPolDisable.
UINT32 | PchSlpS3MinAssert: 4
SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is PchSlpS350ms.
UINT32 | PchSlpS4MinAssert: 4
SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is PchSlpS44s.
UINT32 | PchSlpSusMinAssert: 4
SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is PchSlpSus4s.
UINT32 | PchSlpAMinAssert: 4
SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is PchSlpA2s.
UINT32 | SlpStrchSusUp: 1
This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
UINT32 | SlpLanLowDc: 1
Enable/Disable SLP_LAN# Low on DC Power. More...
UINT32 | PwrBtnOverridePeriod: 3
PCH power button override period. More...
UINT32 | DisableEnergyReport: 1
(Test) Disable/Enable PCH to CPU enery report feature. More...
UINT32 | DisableDsxAcPresentPulldown: 1
When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
UINT32 | DisableNativePowerButton: 1
Power button native mode disable. More...
UINT32 | MeWakeSts: 1
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
UINT32 | WolOvrWkSts: 1
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
UINT32 | PsOnEnable: 1
Decide if PS_ON is to be enabled. More...
UINT32 | CpuC10GatePinEnable: 1
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. More...
UINT32 | PmcDbgMsgEn: 1
Control whether to enable PMC debug messages to Trace Hub. More...
UINT32 | ModPhySusPgEnable: 1
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. More...
UINT32 | Usb2PhySusPgEnable: 1
(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality. More...
UINT32 | OsIdleEnable: 1
Enable Os Idle Mode. More...
UINT32 | V1p05PhyExtFetControlEn: 1
Enable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY 0: Disable; 1: Enable.
UINT32 | V1p05IsExtFetControlEn: 1
Enable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply 0: Disable; 1: Enable.
UINT32 | S0ixAutoDemotion: 1
Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature. More...
UINT32 | LatchEventsC10Exit: 1
Enable/Disable Latch Events C10 Exit. More...
UINT8 | PchPwrCycDur
Reset Power Cycle Duration could be customized in the unit of second. More...
UINT8 | PciePllSsc
Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units. More...
UINT8 | C10DynamicThresholdAdjustment
Tells BIOS to enable C10 dynamic threshold adjustment mode. More...
UINT8 | Rsvd0 [1]
Reserved bytes.
PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable
(Test) Low Power Mode Enable/Disable config. More...
UINT8 | GlobalResetMasksOverride
Set true to enable override of Global Reset Event/Trigger masks. More...
UINT8 | Rsvd1 [3]
Reserved bytes.
UINT32 | ThermTimerDelay: 10
PMC Therm Timer Delay Register (THERM_TIMER_DELAY). More...

Detailed Description

The PCH_PM_CONFIG block describes expected miscellaneous power management settings.

The PowerResetStatusClear field would clear the Power/Reset status bits, please set the bits if you want PCH Init driver to clear it, if you want to check the status later then clear the bits.

Revision 1:

  • Initial version. Revision 2
  • Added C10DynamicThresholdAdjustment Revision 3:
  • Added SkipVccInConfig

Definition at line 229 of file PmConfig.h.

Member Data Documentation

◆ C10DynamicThresholdAdjustment

UINT8 PCH_PM_CONFIG::C10DynamicThresholdAdjustment

Tells BIOS to enable C10 dynamic threshold adjustment mode.

BIOS will only attemt to enable it on PCH SKUs which support it.

Definition at line 411 of file PmConfig.h.

◆ CpuC10GatePinEnable

UINT32 PCH_PM_CONFIG::CpuC10GatePinEnable

Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin.

This policy needs to be set if board design includes support for CPU_C10_GATE# pin. 0: Disable; 1: Enable

Definition at line 315 of file PmConfig.h.

◆ DisableDsxAcPresentPulldown

UINT32 PCH_PM_CONFIG::DisableDsxAcPresentPulldown

When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.

When set to Enable, PCH will not pull down AC_PRESENT. This setting is ignored when DeepSx is not supported. Default is 0:Disable

Definition at line 276 of file PmConfig.h.

◆ DisableEnergyReport

UINT32 PCH_PM_CONFIG::DisableEnergyReport

(Test) Disable/Enable PCH to CPU enery report feature.

0: Disable; 1: Enable. Enery Report is must have feature. Wihtout Energy Report, the performance report by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted in power/performance management algorithm. If for some reason PCH energy report is too high, which forces CPU to try to reduce its power by throttling, then it could try to disable Energy Report to do first debug. This might be due to energy scaling factors are not correct or the LPM settings are not kicking in.

Definition at line 269 of file PmConfig.h.

◆ DisableNativePowerButton

UINT32 PCH_PM_CONFIG::DisableNativePowerButton

Power button native mode disable.

While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal. While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted. Default is FALSE.

Definition at line 283 of file PmConfig.h.

◆ GlobalResetMasksOverride

UINT8 PCH_PM_CONFIG::GlobalResetMasksOverride

Set true to enable override of Global Reset Event/Trigger masks.

Values from GlobalResetTriggerMask and GlobalResetEventMask will be used as override value. 0: Disable, 1: Enable

Definition at line 445 of file PmConfig.h.

◆ LatchEventsC10Exit

UINT32 PCH_PM_CONFIG::LatchEventsC10Exit

Enable/Disable Latch Events C10 Exit.

When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default) 0: Disable; 1: Enable.

Definition at line 371 of file PmConfig.h.

◆ LpmS0ixSubStateEnable

PMC_LPM_S0IX_SUB_STATE_EN PCH_PM_CONFIG::LpmS0ixSubStateEnable

(Test) Low Power Mode Enable/Disable config.

Configure if respective S0i2/3 sub-states are to be supported by the platform. By default all sub-states are enabled but for test purpose respective states can be disabled. Default is 0xFF

Definition at line 421 of file PmConfig.h.

◆ ModPhySusPgEnable

UINT32 PCH_PM_CONFIG::ModPhySusPgEnable

Enable/Disable ModPHY SUS Power Domain Dynamic Gating.

EXT_PWR_GATE# signal (if supported on platform) can be used to control external FET for power gating ModPHY

Note
: This setting is not supported and ignored on PCH-H 0: Disable; 1: Enable.

Definition at line 331 of file PmConfig.h.

◆ OsIdleEnable

UINT32 PCH_PM_CONFIG::OsIdleEnable

Enable Os Idle Mode.

0: Disable; 1: Enable.

Definition at line 344 of file PmConfig.h.

◆ PchPwrCycDur

UINT8 PCH_PM_CONFIG::PchPwrCycDur

Reset Power Cycle Duration could be customized in the unit of second.

Please refer to EDS for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. And make sure the setting correct, which never less than the following register.

  • GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
  • GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
  • PWRM_CFG.SLP_A_MIN_ASST_WDTH
  • PWRM_CFG.SLP_LAN_MIN_ASST_WDTH

Definition at line 398 of file PmConfig.h.

◆ PciePllSsc

UINT8 PCH_PM_CONFIG::PciePllSsc

Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units.

Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% The default is 0xFF: AUTO - No BIOS override.

Definition at line 406 of file PmConfig.h.

◆ PmcDbgMsgEn

UINT32 PCH_PM_CONFIG::PmcDbgMsgEn

Control whether to enable PMC debug messages to Trace Hub.

When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub.

Note
: When enabled, system may not enter S0ix 0: Disable; 1: Enable.

Definition at line 323 of file PmConfig.h.

◆ PsOnEnable

UINT32 PCH_PM_CONFIG::PsOnEnable

Decide if PS_ON is to be enabled.

This is available on desktop only. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled.} 0: Disable; 1: Enable.

Definition at line 308 of file PmConfig.h.

◆ PwrBtnOverridePeriod

UINT32 PCH_PM_CONFIG::PwrBtnOverridePeriod

PCH power button override period.

000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s Default is 0: 4s

Definition at line 257 of file PmConfig.h.

◆ S0ixAutoDemotion

UINT32 PCH_PM_CONFIG::S0ixAutoDemotion

Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature.

This feature enables the PMC to autonomously manage the deepest allowed S0ix substate to combat thrashing between power management states. 0: Disable; 1: Enable.

Definition at line 364 of file PmConfig.h.

◆ SlpLanLowDc

UINT32 PCH_PM_CONFIG::SlpLanLowDc

Enable/Disable SLP_LAN# Low on DC Power.

0: Disable; 1: Enable. Configure On DC PHY Power Diable according to policy SlpLanLowDc. When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low. This indicates that LAN PHY should be powered off on battery mode. This will override the DC_PP_DIS setting by WolEnableOverride.

Definition at line 251 of file PmConfig.h.

◆ SlpStrchSusUp

UINT32 PCH_PM_CONFIG::SlpStrchSusUp

This member describes whether or not the LPC ClockRun feature of PCH should be enabled.

0: Disable; 1: Enable 0: Disable; 1: Enable SLP_X Stretching After SUS Well Power Up

Definition at line 243 of file PmConfig.h.

◆ ThermTimerDelay

UINT32 PCH_PM_CONFIG::ThermTimerDelay

PMC Therm Timer Delay Register (THERM_TIMER_DELAY).

Unit in us(microseconds). Adding delay time between CPU thermal trip propagating through PCH and PCH generating a Global Reset Default is 500

Definition at line 460 of file PmConfig.h.

◆ Usb2PhySusPgEnable

UINT32 PCH_PM_CONFIG::Usb2PhySusPgEnable

(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality.

Note
: This setting is not supported and ignored on PCH-H 0: disable USB2 PHY SUS Well Power Gating 1: enable USB2 PHY SUS Well Power Gating

Definition at line 339 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_PM_CONFIG Member List

This is the complete list of members for PCH_PM_CONFIG, including all inherited members.

C10DynamicThresholdAdjustment | PCH_PM_CONFIG
CpuC10GatePinEnable | PCH_PM_CONFIG
DisableDsxAcPresentPulldown | PCH_PM_CONFIG
DisableEnergyReport | PCH_PM_CONFIG
DisableNativePowerButton | PCH_PM_CONFIG
GlobalResetMasksOverride | PCH_PM_CONFIG
Header | PCH_PM_CONFIG
LatchEventsC10Exit | PCH_PM_CONFIG
LpmS0ixSubStateEnable | PCH_PM_CONFIG
MeWakeSts | PCH_PM_CONFIG
ModPhySusPgEnable | PCH_PM_CONFIG
OsIdleEnable | PCH_PM_CONFIG
PchDeepSxPol | PCH_PM_CONFIG
PchPwrCycDur | PCH_PM_CONFIG
PchSlpAMinAssert | PCH_PM_CONFIG
PchSlpS3MinAssert | PCH_PM_CONFIG
PchSlpS4MinAssert | PCH_PM_CONFIG
PchSlpSusMinAssert | PCH_PM_CONFIG
PciePllSsc | PCH_PM_CONFIG
PmcDbgMsgEn | PCH_PM_CONFIG
PsOnEnable | PCH_PM_CONFIG
PwrBtnOverridePeriod | PCH_PM_CONFIG
Rsvd0 | PCH_PM_CONFIG
Rsvd1 | PCH_PM_CONFIG
S0ixAutoDemotion | PCH_PM_CONFIG
SlpLanLowDc | PCH_PM_CONFIG
SlpStrchSusUp | PCH_PM_CONFIG
ThermTimerDelay | PCH_PM_CONFIG
Usb2PhySusPgEnable | PCH_PM_CONFIG
V1p05IsExtFetControlEn | PCH_PM_CONFIG
V1p05PhyExtFetControlEn | PCH_PM_CONFIG
WakeConfig | PCH_PM_CONFIG
WolOvrWkSts | PCH_PM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_SATA_PORT_CONFIG Struct Reference

Public Attributes | List of all members
PCH_SATA_PORT_CONFIG Struct Reference

This structure configures the features, property, and capability for each SATA port. More...

#include <SataConfig.h>

Public Attributes

UINT32 | Enable: 1
Enable SATA port. More...
UINT32 | HotPlug: 1
0: Disable; 1: Enable
UINT32 | InterlockSw: 1
0: Disable; 1: Enable
UINT32 | External: 1
0: Disable; 1: Enable
UINT32 | SpinUp: 1
0: Disable; 1: Enable the COMRESET initialization Sequence to the device
UINT32 | SolidStateDrive: 1
0: HDD; 1: SSD
UINT32 | DevSlp: 1
0: Disable; 1: Enable DEVSLP on the port
UINT32 | EnableDitoConfig: 1
0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
UINT32 | DmVal: 4
DITO multiplier. Default is 15.
UINT32 | DitoVal: 10
DEVSLP Idle Timeout (DITO), Default is 625.
UINT32 | ZpOdd: 1
Support zero power ODD 0: Disable, 1: Enable. More...
UINT32 | DevSlpResetConfig: 4
0: Hardware default; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: GpioDswReset
UINT32 | SataPmPtm: 1
Deprecated.
UINT32 | RxPolarity: 1
0: Disable; 1: Enable; Rx Polarity
UINT32 | RsvdBits0: 3
Reserved fields for future expansion w/o protocol change.

Detailed Description

This structure configures the features, property, and capability for each SATA port.

Definition at line 75 of file SataConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_SATA_PORT_CONFIG::Enable

Enable SATA port.

It is highly recommended to disable unused ports for power savings 0: Disable; 1: Enable

Definition at line 80 of file SataConfig.h.

◆ ZpOdd

UINT32 PCH_SATA_PORT_CONFIG::ZpOdd

Support zero power ODD 0: Disable, 1: Enable.

This is also used to disable ModPHY dynamic power gate.

Definition at line 94 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_SATA_PORT_CONFIG Member List

This is the complete list of members for PCH_SATA_PORT_CONFIG, including all inherited members.

DevSlp | PCH_SATA_PORT_CONFIG
DevSlpResetConfig | PCH_SATA_PORT_CONFIG
DitoVal | PCH_SATA_PORT_CONFIG
DmVal | PCH_SATA_PORT_CONFIG
Enable | PCH_SATA_PORT_CONFIG
EnableDitoConfig | PCH_SATA_PORT_CONFIG
External | PCH_SATA_PORT_CONFIG
HotPlug | PCH_SATA_PORT_CONFIG
InterlockSw | PCH_SATA_PORT_CONFIG
RsvdBits0 | PCH_SATA_PORT_CONFIG
RxPolarity | PCH_SATA_PORT_CONFIG
SataPmPtm | PCH_SATA_PORT_CONFIG
SolidStateDrive | PCH_SATA_PORT_CONFIG
SpinUp | PCH_SATA_PORT_CONFIG
ZpOdd | PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_SMBUS_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_SMBUS_PREMEM_CONFIG Struct Reference

The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. More...

#include <SmbusConfig.h>

Collaboration diagram for PCH_SMBUS_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Revision 1: Init version. More...
UINT32 | Enable: 1
This member describes whether or not the SMBus controller of PCH should be enabled. More...
UINT32 | ArpEnable: 1
Enable SMBus ARP support, 0: Disable; 1: Enable.
UINT32 | DynamicPowerGating: 1
(Test) Disable or Enable Smbus dynamic power gating.
UINT32 | SpdWriteDisable: 1
(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. More...
UINT32 | SmbAlertEnable: 1
Enable SMBus Alert pin (SMBALERT#). 0: Disabled, 1: Enabled.
UINT32 | RsvdBits0: 27
Reserved bits.
UINT16 | SmbusIoBase
SMBUS Base Address (IO space). Default is 0xEFA0.
UINT8 | Rsvd0
Reserved bytes.
UINT8 | NumRsvdSmbusAddresses
The number of elements in the RsvdSmbusAddressTable.
UINT8 | RsvdSmbusAddressTable [PCH_MAX_SMBUS_RESERVED_ADDRESS]
Array of addresses reserved for non-ARP-capable SMBus devices.

Detailed Description

The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.

Definition at line 48 of file SmbusConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_SMBUS_PREMEM_CONFIG::Enable

This member describes whether or not the SMBus controller of PCH should be enabled.

0: Disable; 1: Enable.

Definition at line 57 of file SmbusConfig.h.

◆ Header

CONFIG_BLOCK_HEADER PCH_SMBUS_PREMEM_CONFIG::Header

Revision 1: Init version.

Config Block Header

Definition at line 52 of file SmbusConfig.h.

◆ SpdWriteDisable

UINT32 PCH_SMBUS_PREMEM_CONFIG::SpdWriteDisable

(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit.

For security recommendations, SPD write disable bit must be set.

Definition at line 64 of file SmbusConfig.h.

The documentation for this struct was generated from the following file:
  • SmbusConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_SMBUS_PREMEM_CONFIG Member List

This is the complete list of members for PCH_SMBUS_PREMEM_CONFIG, including all inherited members.

ArpEnable | PCH_SMBUS_PREMEM_CONFIG
DynamicPowerGating | PCH_SMBUS_PREMEM_CONFIG
Enable | PCH_SMBUS_PREMEM_CONFIG
Header | PCH_SMBUS_PREMEM_CONFIG
NumRsvdSmbusAddresses | PCH_SMBUS_PREMEM_CONFIG
Rsvd0 | PCH_SMBUS_PREMEM_CONFIG
RsvdBits0 | PCH_SMBUS_PREMEM_CONFIG
RsvdSmbusAddressTable | PCH_SMBUS_PREMEM_CONFIG
SmbAlertEnable | PCH_SMBUS_PREMEM_CONFIG
SmbusIoBase | PCH_SMBUS_PREMEM_CONFIG
SpdWriteDisable | PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_TRACE_HUB_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_TRACE_HUB_PREMEM_CONFIG Struct Reference

PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version. More...

#include <TraceHubConfig.h>

Collaboration diagram for PCH_TRACE_HUB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.

Detailed Description

PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version.

Definition at line 122 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_TRACE_HUB_PREMEM_CONFIG Member List

This is the complete list of members for PCH_TRACE_HUB_PREMEM_CONFIG, including all inherited members.

Header | PCH_TRACE_HUB_PREMEM_CONFIG
TraceHub | PCH_TRACE_HUB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_WAKE_CONFIG Struct Reference

Public Attributes | List of all members
PCH_WAKE_CONFIG Struct Reference

This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. More...

#include <PmConfig.h>

Public Attributes

UINT32 | PmeB0S5Dis: 1
Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. More...
UINT32 | WolEnableOverride: 1
Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; 1: Enable.
UINT32 | PcieWakeFromDeepSx: 1
Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable.
UINT32 | WoWlanEnable: 1
Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable.
UINT32 | WoWlanDeepSxEnable: 1
Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable.
UINT32 | LanWakeFromDeepSx: 1
Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable.

Detailed Description

This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.

Definition at line 51 of file PmConfig.h.

Member Data Documentation

◆ PmeB0S5Dis

UINT32 PCH_WAKE_CONFIG::PmeB0S5Dis

Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.

When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. 0: Disable; 1: Enable.

Definition at line 57 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_WAKE_CONFIG Member List

This is the complete list of members for PCH_WAKE_CONFIG, including all inherited members.

LanWakeFromDeepSx | PCH_WAKE_CONFIG
PcieWakeFromDeepSx | PCH_WAKE_CONFIG
PmeB0S5Dis | PCH_WAKE_CONFIG
WolEnableOverride | PCH_WAKE_CONFIG
WoWlanDeepSxEnable | PCH_WAKE_CONFIG
WoWlanEnable | PCH_WAKE_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCH_WDT_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_WDT_PREMEM_CONFIG Struct Reference

This policy clears status bits and disable watchdog, then lock the WDT registers. More...

#include <WatchDogConfig.h>

Collaboration diagram for PCH_WDT_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 DisableAndLock: 1
(Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable.

Detailed Description

This policy clears status bits and disable watchdog, then lock the WDT registers.

while WDT is designed to be disabled and locked by Policy, bios should not enable WDT by WDT PPI. In such case, bios shows the warning message but not disable and lock WDT register to make sure WDT event trigger correctly.

Definition at line 51 of file WatchDogConfig.h.

The documentation for this struct was generated from the following file:
  • WatchDogConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCH_WDT_PREMEM_CONFIG Member List

This is the complete list of members for PCH_WDT_PREMEM_CONFIG, including all inherited members.

DisableAndLock | PCH_WDT_PREMEM_CONFIG
Header | PCH_WDT_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_COMMON_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_COMMON_CONFIG Struct Reference

PCIe Common Config. More...

#include <PcieConfig.h>

Collaboration diagram for PCIE_COMMON_CONFIG:
[legend]

Public Attributes

UINT32 | RpFunctionSwap: 1
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
UINT32 | ComplianceTestMode: 1
Compliance Test Mode shall be enabled when using Compliance Load Board. More...
UINT32 | RsvdBits0: 30
Reserved bits.
UINT8 | EnablePort8xhDecode
(Test) This member describes whether PCIE root port Port 8xh Decode is enabled. More...
PCIE_EQ_PARAM | HwEqGen3CoeffList [PCIE_HWEQ_COEFFS_MAX]
List of coefficients used during equalization (applicable to both software and hardware EQ) Deprecated Policy.

Detailed Description

PCIe Common Config.

Note
This structure will be expanded to hold all common PCIe policies between SA and PCH

Definition at line 287 of file PcieConfig.h.

Member Data Documentation

◆ ComplianceTestMode

UINT32 PCIE_COMMON_CONFIG::ComplianceTestMode

Compliance Test Mode shall be enabled when using Compliance Load Board.

0: Disable, 1: Enable

Definition at line 308 of file PcieConfig.h.

◆ EnablePort8xhDecode

UINT8 PCIE_COMMON_CONFIG::EnablePort8xhDecode

(Test) This member describes whether PCIE root port Port 8xh Decode is enabled.

0: Disable; 1: Enable.

Definition at line 313 of file PcieConfig.h.

◆ RpFunctionSwap

UINT32 PCIE_COMMON_CONFIG::RpFunctionSwap

RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.

A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement, BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.

  • Enabled: One of enabled root ports get assigned to Function0. This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
  • Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used. That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy In other words, it only affects ports that would become hidden because they have no device connected. NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY be used when each one of root ports 1, 9, 17:
    • is configured as PCIe and has correctly configured ClkReq signal, or
    • does not own any mPhy lanes (they are configured as SATA or USB)

Definition at line 303 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_COMMON_CONFIG Member List

This is the complete list of members for PCIE_COMMON_CONFIG, including all inherited members.

ComplianceTestMode | PCIE_COMMON_CONFIG
EnablePort8xhDecode | PCIE_COMMON_CONFIG
HwEqGen3CoeffList | PCIE_COMMON_CONFIG
RpFunctionSwap | PCIE_COMMON_CONFIG
RsvdBits0 | PCIE_COMMON_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_DEVICE_OVERRIDE Struct Reference

Public Attributes | List of all members
PCIE_DEVICE_OVERRIDE Struct Reference

PCIe device table entry entry. More...

#include <PcieConfig.h>

Public Attributes

UINT16 | VendorId
The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID.
UINT16 | DeviceId
The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID.
UINT8 | RevId
The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings.
UINT8 | BaseClassCode
The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class.
UINT8 | SubClassCode
The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class.
UINT8 | EndPointAspm
Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) Bit 1 must be set in OverrideConfig for this field to take effect.
UINT16 | OverrideConfig
The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
UINT16 | L1SubstatesCapOffset
The L1Substates Capability Offset Override. More...
UINT8 | L1SubstatesCapMask
L1 Substate Capability Mask. More...
UINT8 | L1sCommonModeRestoreTime
L1 Substate Port Common Mode Restore Time Override. More...
UINT8 | L1sTpowerOnScale
L1 Substate Port Tpower_on Scale Override. More...
UINT8 | L1sTpowerOnValue
L1 Substate Port Tpower_on Value Override. More...
UINT16 | SnoopLatency
SnoopLatency bit definition Note: All Reserved bits must be set to 0. More...
UINT16 | NonSnoopLatency
NonSnoopLatency bit definition Note: All Reserved bits must be set to 0. More...
UINT8 | ForceLtrOverride
Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message This settings allows force override of LTR mechanism. More...

Detailed Description

PCIe device table entry entry.

The PCIe device table is being used to override PCIe device ASPM settings. To take effect table consisting of such entries must be instelled as PPI on gPchPcieDeviceTablePpiGuid. Last entry VendorId must be 0.

Definition at line 337 of file PcieConfig.h.

Member Data Documentation

◆ ForceLtrOverride

UINT8 PCIE_DEVICE_OVERRIDE::ForceLtrOverride

Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message This settings allows force override of LTR mechanism.

If it's enabled, then: rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored

Definition at line 431 of file PcieConfig.h.

◆ L1sCommonModeRestoreTime

UINT8 PCIE_DEVICE_OVERRIDE::L1sCommonModeRestoreTime

L1 Substate Port Common Mode Restore Time Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 363 of file PcieConfig.h.

◆ L1sTpowerOnScale

UINT8 PCIE_DEVICE_OVERRIDE::L1sTpowerOnScale

L1 Substate Port Tpower_on Scale Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 370 of file PcieConfig.h.

◆ L1sTpowerOnValue

UINT8 PCIE_DEVICE_OVERRIDE::L1sTpowerOnValue

L1 Substate Port Tpower_on Value Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 377 of file PcieConfig.h.

◆ L1SubstatesCapMask

UINT8 PCIE_DEVICE_OVERRIDE::L1SubstatesCapMask

L1 Substate Capability Mask.

(applicable if bit 2 is set in OverrideConfig) Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override. Only bit [3:0] are applicable. Other bits are ignored.

Definition at line 356 of file PcieConfig.h.

◆ L1SubstatesCapOffset

UINT16 PCIE_DEVICE_OVERRIDE::L1SubstatesCapOffset

The L1Substates Capability Offset Override.

(applicable if bit 2 is set in OverrideConfig) This field can be zero if only the L1 Substate value is going to be override.

Definition at line 350 of file PcieConfig.h.

◆ NonSnoopLatency

UINT16 PCIE_DEVICE_OVERRIDE::NonSnoopLatency

NonSnoopLatency bit definition Note: All Reserved bits must be set to 0.

BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid When clear values in bits 9:0 will be ignored BITS[14:13] - Reserved BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 000b - 1 ns 001b - 32 ns 010b - 1024 ns 011b - 32,768 ns 100b - 1,048,576 ns 101b - 33,554,432 ns 110b - Reserved 111b - Reserved BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with the scale in bits 12:10

This field takes effect only if bit 3 is set in OverrideConfig.

Definition at line 422 of file PcieConfig.h.

◆ SnoopLatency

UINT16 PCIE_DEVICE_OVERRIDE::SnoopLatency

SnoopLatency bit definition Note: All Reserved bits must be set to 0.

BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid When clear values in bits 9:0 will be ignored BITS[14:13] - Reserved BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 000b - 1 ns 001b - 32 ns 010b - 1024 ns 011b - 32,768 ns 100b - 1,048,576 ns 101b - 33,554,432 ns 110b - Reserved 111b - Reserved BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with the scale in bits 12:10

This field takes effect only if bit 3 is set in OverrideConfig.

Definition at line 400 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_DEVICE_OVERRIDE Member List

This is the complete list of members for PCIE_DEVICE_OVERRIDE, including all inherited members.

BaseClassCode | PCIE_DEVICE_OVERRIDE
DeviceId | PCIE_DEVICE_OVERRIDE
EndPointAspm | PCIE_DEVICE_OVERRIDE
ForceLtrOverride | PCIE_DEVICE_OVERRIDE
L1sCommonModeRestoreTime | PCIE_DEVICE_OVERRIDE
L1sTpowerOnScale | PCIE_DEVICE_OVERRIDE
L1sTpowerOnValue | PCIE_DEVICE_OVERRIDE
L1SubstatesCapMask | PCIE_DEVICE_OVERRIDE
L1SubstatesCapOffset | PCIE_DEVICE_OVERRIDE
NonSnoopLatency | PCIE_DEVICE_OVERRIDE
OverrideConfig | PCIE_DEVICE_OVERRIDE
RevId | PCIE_DEVICE_OVERRIDE
SnoopLatency | PCIE_DEVICE_OVERRIDE
SubClassCode | PCIE_DEVICE_OVERRIDE
VendorId | PCIE_DEVICE_OVERRIDE
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_EQ_PARAM Struct Reference

Public Attributes | List of all members
PCIE_EQ_PARAM Struct Reference

Represent lane specific PCIe Gen3 equalization parameters. More...

#include <PcieConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | Rsvd0 [2]
Reserved bytes.

Detailed Description

Represent lane specific PCIe Gen3 equalization parameters.

Definition at line 76 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_EQ_PARAM Member List

This is the complete list of members for PCIE_EQ_PARAM, including all inherited members.

Cm | PCIE_EQ_PARAM
Cp | PCIE_EQ_PARAM
Rsvd0 | PCIE_EQ_PARAM
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_IMR_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_IMR_CONFIG Struct Reference

PCIe IMR Config. More...

#include <PciePreMemConfig.h>

Public Attributes

UINT8 | ImrEnabled
PCIe IMR. 0: Disable; 1: Enable.
UINT8 | ImrRpLocation
0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
UINT16 | ImrSize
PCIe IMR size in megabytes.
UINT8 | ImrRpSelection
Index of root port that is selected for PCIe IMR (0 based)

Detailed Description

PCIe IMR Config.

Definition at line 53 of file PciePreMemConfig.h.

The documentation for this struct was generated from the following file:
  • PciePreMemConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_IMR_CONFIG Member List

This is the complete list of members for PCIE_IMR_CONFIG, including all inherited members.

ImrEnabled | PCIE_IMR_CONFIG
ImrRpLocation | PCIE_IMR_CONFIG
ImrRpSelection | PCIE_IMR_CONFIG
ImrSize | PCIE_IMR_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_LINK_EQ_PLATFORM_SETTINGS Struct Reference

Public Attributes | List of all members
PCIE_LINK_EQ_PLATFORM_SETTINGS Struct Reference

PCIe Link EQ Platform Settings. More...

#include <PcieConfig.h>

Public Attributes

UINT8 | PcieLinkEqMethod
Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq.
UINT8 | PcieLinkEqMode
Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC.
UINT8 | LocalTransmitterOverrideEnable
Specifies if BIOS should perform local transmitter override during phase 2 of EQ process. More...
UINT8 | Ph3NumberOfPresetsOrCoefficients
Tells BIOS how many presets/coefficients should be used during link EQ. More...
PCIE_LINK_EQ_COEFFICIENTS | Ph3CoefficientsList [PCIE_LINK_EQ_COEFFICIENTS_MAX]
List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode.
UINT32 | Ph3PresetList [PCIE_LINK_EQ_PRESETS_MAX]
List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode.
UINT32 | Ph1DownstreamPortTransmitterPreset
Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes.
UINT32 | Ph1UpstreamPortTransmitterPreset
Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes.
UINT32 | Ph2LocalTransmitterOverridePreset
Specifies the preset that should be used during local transmitter override during phase 2 of EQ process. More...
UINT32 | PCETTimer
PCET Timer value for single PCIe speed.
UINT8 | RemotePresetCoeffoverride
Remote Transmitter Preset Coefficient Override for single PCIe speed.
UINT8 | EqPh3Bypass
PCIe Equalization Phase 3 Enable Control. More...
UINT8 | EqPh23Bypass
PCIe Equalization Phase 2-3 Enable Control. More...
UINT8 | TsLockTimer
8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer

Detailed Description

PCIe Link EQ Platform Settings.

Definition at line 132 of file PcieConfig.h.

Member Data Documentation

◆ EqPh23Bypass

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh23Bypass

PCIe Equalization Phase 2-3 Enable Control.

  • Disabled (0x0) : Disable Phase 2 - Phase 3 (Default)
  • Enabled (0x1) : Enable Phase 2 - Phase 3

Definition at line 170 of file PcieConfig.h.

◆ EqPh3Bypass

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh3Bypass

PCIe Equalization Phase 3 Enable Control.

  • Disabled (0x0) : Disable phase 3 (Default)
    • Enabled (0x1) : Enable phase 3

Definition at line 164 of file PcieConfig.h.

◆ LocalTransmitterOverrideEnable

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::LocalTransmitterOverrideEnable

Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.

If enabled value in Ph2LocalTransmitterOverridePreset must be valid. 0: Disabled; 1: Enabled

Definition at line 140 of file PcieConfig.h.

◆ Ph2LocalTransmitterOverridePreset

UINT32 PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph2LocalTransmitterOverridePreset

Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.

Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port. Valid up to the PCIE_LINK_EQ_PRESET_MAX value. Default: 0< >

Definition at line 156 of file PcieConfig.h.

◆ Ph3NumberOfPresetsOrCoefficients

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph3NumberOfPresetsOrCoefficients

Tells BIOS how many presets/coefficients should be used during link EQ.

Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.

Definition at line 145 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_LINK_EQ_PLATFORM_SETTINGS Member List

This is the complete list of members for PCIE_LINK_EQ_PLATFORM_SETTINGS, including all inherited members.

EqPh23Bypass | PCIE_LINK_EQ_PLATFORM_SETTINGS
EqPh3Bypass | PCIE_LINK_EQ_PLATFORM_SETTINGS
LocalTransmitterOverrideEnable | PCIE_LINK_EQ_PLATFORM_SETTINGS
PCETTimer | PCIE_LINK_EQ_PLATFORM_SETTINGS
PcieLinkEqMethod | PCIE_LINK_EQ_PLATFORM_SETTINGS
PcieLinkEqMode | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph1DownstreamPortTransmitterPreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph1UpstreamPortTransmitterPreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph2LocalTransmitterOverridePreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3CoefficientsList | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3NumberOfPresetsOrCoefficients | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3PresetList | PCIE_LINK_EQ_PLATFORM_SETTINGS
RemotePresetCoeffoverride | PCIE_LINK_EQ_PLATFORM_SETTINGS
TsLockTimer | PCIE_LINK_EQ_PLATFORM_SETTINGS
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_PEI_PREMEM_CONFIG Struct Reference

PCI Express and DMI controller configuration
. More...

#include <CpuPcieConfig.h>

Collaboration diagram for PCIE_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | DmiMaxLinkSpeed: 2
Offset 28:0 : (Test) DMI Link Speed Control. More...
UINT32 | DmiGen3EqPh2Enable: 2
Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control. More...
UINT32 | DmiGen3EqPh3Method: 3
Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI. More...
UINT32 | DmiGen3ProgramStaticEq: 1
Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets. More...
UINT32 | RsvdBits0: 24
Offset 28:8 :Reserved for future use.
UINT32 | InitPcieAspmAfterOprom: 1
Offset 32:0 : Select when PCIe ASPM programming will happen in relation to the Oprom. More...
UINT32 | RsvdBits1: 31
Offset 32:1 :Reserved for future use.
UINT8 | DmiGen3RootPortPreset [SA_DMI_MAX_LANE]
Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3EndPointPreset [SA_DMI_MAX_LANE]
Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane.
UINT8 | DmiGen3EndPointHint [SA_DMI_MAX_LANE]
Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane.
UINT8 | DmiGen3RxCtlePeaking [SA_DMI_MAX_BUNDLE]
Offset 48/60 : DMI Gen3 RxCTLEp per-Bundle control. More...
UINT8 | DmiDeEmphasis
Offset 64 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
UINT8 | Rsvd0 [3]
Offset 65.

Detailed Description

PCI Express and DMI controller configuration
.

Note
Optional. These policies will be ignored if there is no PEG port present on board. Revision 1:
  • Initial version.

Definition at line 84 of file CpuPcieConfig.h.

Member Data Documentation

◆ DmiGen3EqPh2Enable

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh2Enable

Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control.

  • Disabled (0x0) : Disable phase 2
  • Enabled (0x1) : Enable phase 2
  • Auto (0x2) : Use the current default method (Default)

Definition at line 102 of file CpuPcieConfig.h.

◆ DmiGen3EqPh3Method

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh3Method

Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI.

  • Auto (0x0) : Use the current default method (Default)
  • HwEq (0x1) : Use Adaptive Hardware Equalization
  • SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
  • Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
  • Disabled (0x4) : Bypass Equalization Phase 3

Definition at line 112 of file CpuPcieConfig.h.

◆ DmiGen3ProgramStaticEq

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiGen3ProgramStaticEq

Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets.

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 119 of file CpuPcieConfig.h.

◆ DmiGen3RxCtlePeaking

UINT8 PCIE_PEI_PREMEM_CONFIG::DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]

Offset 48/60 : DMI Gen3 RxCTLEp per-Bundle control.

The range of the setting is (0-15). This setting has to be specified based upon platform design and must follow the guideline. Default is 12.

Definition at line 140 of file CpuPcieConfig.h.

◆ DmiMaxLinkSpeed

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiMaxLinkSpeed

Offset 28:0 : (Test) DMI Link Speed Control.

  • Auto (0x0) : Maximum possible link speed (Default)
  • Gen1 (0x1) : Limit Link to Gen1 Speed
  • Gen2 (0x2) : Limit Link to Gen2 Speed
  • Gen3 (0x3) : Limit Link to Gen3 Speed

Definition at line 94 of file CpuPcieConfig.h.

◆ InitPcieAspmAfterOprom

UINT32 PCIE_PEI_PREMEM_CONFIG::InitPcieAspmAfterOprom

Offset 32:0 : Select when PCIe ASPM programming will happen in relation to the Oprom.

  • Before (0x0) : Do PCIe ASPM programming before Oprom. (Default)
  • After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.

Definition at line 128 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_PEI_PREMEM_CONFIG Member List

This is the complete list of members for PCIE_PEI_PREMEM_CONFIG, including all inherited members.

DmiDeEmphasis | PCIE_PEI_PREMEM_CONFIG
DmiGen3EndPointHint | PCIE_PEI_PREMEM_CONFIG
DmiGen3EndPointPreset | PCIE_PEI_PREMEM_CONFIG
DmiGen3EqPh2Enable | PCIE_PEI_PREMEM_CONFIG
DmiGen3EqPh3Method | PCIE_PEI_PREMEM_CONFIG
DmiGen3ProgramStaticEq | PCIE_PEI_PREMEM_CONFIG
DmiGen3RootPortPreset | PCIE_PEI_PREMEM_CONFIG
DmiGen3RxCtlePeaking | PCIE_PEI_PREMEM_CONFIG
DmiMaxLinkSpeed | PCIE_PEI_PREMEM_CONFIG
Header | PCIE_PEI_PREMEM_CONFIG
InitPcieAspmAfterOprom | PCIE_PEI_PREMEM_CONFIG
Rsvd0 | PCIE_PEI_PREMEM_CONFIG
RsvdBits0 | PCIE_PEI_PREMEM_CONFIG
RsvdBits1 | PCIE_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_PREMEM_CONFIG Struct Reference

PCIe Pre-Memory Configuration Revision 1: - Initial version. More...

#include <PciePreMemConfig.h>

Collaboration diagram for PCIE_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
PCIE_IMR_CONFIG PcieImr
IMR Configuration.

Detailed Description

PCIe Pre-Memory Configuration Revision 1: - Initial version.

Definition at line 65 of file PciePreMemConfig.h.

The documentation for this struct was generated from the following file:
  • PciePreMemConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_PREMEM_CONFIG Member List

This is the complete list of members for PCIE_PREMEM_CONFIG, including all inherited members.

Header | PCIE_PREMEM_CONFIG
PcieImr | PCIE_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PCIE_RP_DXE_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_RP_DXE_CONFIG Struct Reference

The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase. More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCIE_RP_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCIE_DEVICE_OVERRIDE * PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings. More...

Detailed Description

The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase.

Revision 1:

  • Init version

Definition at line 269 of file PchPcieRpConfig.h.

Member Data Documentation

◆ PcieDeviceOverrideTablePtr

PCIE_DEVICE_OVERRIDE* PCIE_RP_DXE_CONFIG::PcieDeviceOverrideTablePtr

PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.

And it's only used in DXE phase. Please refer to PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0.

Definition at line 279 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PCIE_RP_DXE_CONFIG Member List

This is the complete list of members for PCIE_RP_DXE_CONFIG, including all inherited members.

Header | PCIE_RP_DXE_CONFIG
PcieDeviceOverrideTablePtr | PCIE_RP_DXE_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PMC_GLOBAL_RESET_MASK Union Reference

List of all members
PMC_GLOBAL_RESET_MASK Union Reference

Description of Global Reset Trigger/Event Mask register. More...

#include <PmConfig.h>

Detailed Description

Description of Global Reset Trigger/Event Mask register.

Definition at line 152 of file PmConfig.h.

The documentation for this union was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PMC_GLOBAL_RESET_MASK Member List

This is the complete list of members for PMC_GLOBAL_RESET_MASK, including all inherited members.

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PMC_INTERFACE_CONFIG Struct Reference

Public Attributes | List of all members
PMC_INTERFACE_CONFIG Struct Reference

The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 PmcPdEnable
PMC PD Solution Enable.

Detailed Description

The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC.

Definition at line 74 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PMC_INTERFACE_CONFIG Member List

This is the complete list of members for PMC_INTERFACE_CONFIG, including all inherited members.

PmcPdEnable PMC_INTERFACE_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PMC_LPM_S0IX_SUB_STATE_EN Union Reference

List of all members
PMC_LPM_S0IX_SUB_STATE_EN Union Reference

Low Power Mode Enable config. More...

#include <PmConfig.h>

Detailed Description

Low Power Mode Enable config.

Used to configure if respective S0i2/3 sub-states are to be supported by the platform. Each bit corresponds to one LPM state - LPMx->BITx. Some sub-states will require external FETs controlled by EXT_PWR_GATE#/EXT_PWR_GATE2# pins to gate v1p05-PHY or v1p05-IS supplies

Definition at line 119 of file PmConfig.h.

Member Data Documentation

◆ S0i2p2En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i2p2En

LPM2 - S0i2.2 Enable.

Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. Refer to V1p05PhyExtFetControlEn.

Definition at line 128 of file PmConfig.h.

◆ S0i3p3En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i3p3En

LPM5 - S0i3.3 Enable.

Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. Refer to V1p05PhyExtFetControlEn.

Definition at line 137 of file PmConfig.h.

◆ S0i3p4En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i3p4En

LPM7 - S0i3.4 Enable.

Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK. Refer to V1p05IsExtFetControlEn.

Definition at line 143 of file PmConfig.h.

The documentation for this union was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PMC_LPM_S0IX_SUB_STATE_EN Member List

This is the complete list of members for PMC_LPM_S0IX_SUB_STATE_EN, including all inherited members.

Reserved | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p0En | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p1En | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p2En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p0En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p1En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p2En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p3En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p4En | PMC_LPM_S0IX_SUB_STATE_EN
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PPM_CUSTOM_RATIO_TABLE Struct Reference

Public Attributes | List of all members
PPM_CUSTOM_RATIO_TABLE Struct Reference

This structure is used to describe the custom processor ratio table desired by the platform. More...

#include <CpuPowerMgmtCustomConfig.h>

Public Attributes

UINT8 | MaxRatio
The maximum ratio of the custom ratio table.
UINT8 | NumberOfEntries
The number of custom ratio state entries, ranges from 2 to 40 for a valid custom ratio table.
UINT8 | Rsvd0 [2]
Reserved for DWORD alignment.
UINT32 | Cpuid
The CPU ID for which this custom ratio table applies.
UINT8 | StateRatio [MAX_CUSTOM_RATIO_TABLE_ENTRIES]
The processor ratios in the custom ratio table.
UINT8 | StateRatioMax16 [MAX_16_CUSTOM_RATIO_TABLE_ENTRIES]
If there are more than 16 total entries in the StateRatio table, then use these 16 entries to fill max 16 table. More...

Detailed Description

This structure is used to describe the custom processor ratio table desired by the platform.

Definition at line 59 of file CpuPowerMgmtCustomConfig.h.

Member Data Documentation

◆ StateRatioMax16

UINT8 PPM_CUSTOM_RATIO_TABLE::StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES]

If there are more than 16 total entries in the StateRatio table, then use these 16 entries to fill max 16 table.

Note
If NumberOfEntries is 16 or less, or the first entry of this table is 0, then this table is ignored, and up to the top 16 values from the StateRatio table is used instead.

Definition at line 70 of file CpuPowerMgmtCustomConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtCustomConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PPM_CUSTOM_RATIO_TABLE Member List

This is the complete list of members for PPM_CUSTOM_RATIO_TABLE, including all inherited members.

Cpuid | PPM_CUSTOM_RATIO_TABLE
MaxRatio | PPM_CUSTOM_RATIO_TABLE
NumberOfEntries | PPM_CUSTOM_RATIO_TABLE
Rsvd0 | PPM_CUSTOM_RATIO_TABLE
StateRatio | PPM_CUSTOM_RATIO_TABLE
StateRatioMax16 | PPM_CUSTOM_RATIO_TABLE
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PSF_CONFIG Struct Reference

Public Attributes | List of all members
PSF_CONFIG Struct Reference

The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric. More...

#include <PsfConfig.h>

Collaboration diagram for PSF_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | TccEnable: 1
Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable some psf power management features. More...
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric.

Definition at line 49 of file PsfConfig.h.

Member Data Documentation

◆ TccEnable

UINT32 PSF_CONFIG::TccEnable

Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable some psf power management features.

0: Disable; 1: Enable.

Definition at line 55 of file PsfConfig.h.

The documentation for this struct was generated from the following file:
  • PsfConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

PSF_CONFIG Member List

This is the complete list of members for PSF_CONFIG, including all inherited members.

Header | PSF_CONFIG
RsvdBits0 | PSF_CONFIG
TccEnable | PSF_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: RST_CONFIG Struct Reference

Public Attributes | List of all members
RST_CONFIG Struct Reference

Rapid Storage Technology settings. More...

#include <RstConfig.h>

Collaboration diagram for RST_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Raid0: 1
0 : Disable; 1 : Enable RAID0
UINT32 | Raid1: 1
0 : Disable; 1 : Enable RAID1
UINT32 | Raid10: 1
0 : Disable; 1 : Enable RAID10
UINT32 | Raid5: 1
0 : Disable; 1 : Enable RAID5
UINT32 | Irrt: 1
0 : Disable; 1 : Enable Intel Rapid Recovery Technology
UINT32 | OromUiBanner: 1
0 : Disable; 1 : Enable OROM UI and BANNER
UINT32 | OromUiDelay: 2
00b : 2 secs; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
UINT32 | HddUnlock: 1
0 : Disable; 1 : Enable. Indicates that the HDD password unlock in the OS is enabled
UINT32 | LedLocate: 1
0 : Disable; 1 : Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
UINT32 | IrrtOnly: 1
0 : Disable; 1 : Enable. Allow only IRRT drives to span internal and external ports
UINT32 | SmartStorage: 1
0 : Disable; 1 : Enable RST Smart Storage caching Bit
UINT32 | LegacyOrom: 1
0 : Disable; 1 : Enable RST Legacy OROM
UINT32 | OptaneMemory: 1
0: Disable; 1: Enable RST Optane(TM) Memory
UINT32 | CpuAttachedStorage: 1
0: Disable; 1: Enable CPU Attached Storage
UINT32 | RsvdBits0: 17
Reserved Bits.
RST_HARDWARE_REMAPPED_STORAGE_CONFIG | HardwareRemappedStorageConfig [PCH_MAX_RST_PCIE_STORAGE_CR]
This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required) Note: RST for PCIe Sorage remapping is supported only for first SATA controller if more controllers are available.

Detailed Description

Rapid Storage Technology settings.

Revision 1:

  • Initial version.

Definition at line 84 of file RstConfig.h.

The documentation for this struct was generated from the following file:
  • RstConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

RST_CONFIG Member List

This is the complete list of members for RST_CONFIG, including all inherited members.

CpuAttachedStorage | RST_CONFIG
HardwareRemappedStorageConfig | RST_CONFIG
HddUnlock | RST_CONFIG
Header | RST_CONFIG
Irrt | RST_CONFIG
IrrtOnly | RST_CONFIG
LedLocate | RST_CONFIG
LegacyOrom | RST_CONFIG
OptaneMemory | RST_CONFIG
OromUiBanner | RST_CONFIG
OromUiDelay | RST_CONFIG
Raid0 | RST_CONFIG
Raid1 | RST_CONFIG
Raid10 | RST_CONFIG
Raid5 | RST_CONFIG
RsvdBits0 | RST_CONFIG
SmartStorage | RST_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: RST_HARDWARE_REMAPPED_STORAGE_CONFIG Struct Reference

Public Attributes | List of all members
RST_HARDWARE_REMAPPED_STORAGE_CONFIG Struct Reference

This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required. More...

#include <RstConfig.h>

Public Attributes

UINT32 | Enable: 1
This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. More...
UINT32 | RstPcieStoragePort: 5
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) The supported ports for PCIe Storage remapping is different depend on the platform and cycle router.
UINT32 | DeviceResetDelay: 8
PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step. More...
UINT32 | RsvdBits0: 18
Reserved bits.

Detailed Description

This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required.

Definition at line 56 of file RstConfig.h.

Member Data Documentation

◆ DeviceResetDelay

UINT32 RST_HARDWARE_REMAPPED_STORAGE_CONFIG::DeviceResetDelay

PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.

Default value is 100ms.

Definition at line 73 of file RstConfig.h.

◆ Enable

UINT32 RST_HARDWARE_REMAPPED_STORAGE_CONFIG::Enable

This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled.

0: Disable; 1: Enable. Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID

Definition at line 62 of file RstConfig.h.

The documentation for this struct was generated from the following file:
  • RstConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

RST_HARDWARE_REMAPPED_STORAGE_CONFIG Member List

This is the complete list of members for RST_HARDWARE_REMAPPED_STORAGE_CONFIG, including all inherited members.

DeviceResetDelay | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
Enable | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
RstPcieStoragePort | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
RsvdBits0 | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: RTC_CONFIG Struct Reference

Public Attributes | List of all members
RTC_CONFIG Struct Reference

The RTC_CONFIG block describes the expected configuration of RTC configuration. More...

#include <RtcConfig.h>

Collaboration diagram for RTC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | BiosInterfaceLock: 1
When set, prevents RTC TS (BUC.TS) from being changed. More...
UINT32 | MemoryLock: 1
When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed. More...

Detailed Description

The RTC_CONFIG block describes the expected configuration of RTC configuration.

Definition at line 46 of file RtcConfig.h.

Member Data Documentation

◆ BiosInterfaceLock

UINT32 RTC_CONFIG::BiosInterfaceLock

When set, prevents RTC TS (BUC.TS) from being changed.

This BILD bit has different function compared to LPC/eSPI, SPI. 0: Disabled; 1: Enabled

Definition at line 53 of file RtcConfig.h.

◆ MemoryLock

UINT32 RTC_CONFIG::MemoryLock

When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed.

Writes will be droipped and reads will not return any guaranteed data. 0: Disabled; 1: Enabled

Definition at line 60 of file RtcConfig.h.

The documentation for this struct was generated from the following file:
  • RtcConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

RTC_CONFIG Member List

This is the complete list of members for RTC_CONFIG, including all inherited members.

BiosInterfaceLock | RTC_CONFIG
Header | RTC_CONFIG
MemoryLock | RTC_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_ADDRESS_DECODE Struct Reference

Public Attributes | List of all members
SA_ADDRESS_DECODE Struct Reference

SA memory address decode. More...

#include <MemoryConfig.h>

Public Attributes

UINT8 | Controller
Offset 0 Zero based Controller number.
UINT8 | Channel
Offset 1 Zero based Channel number.
UINT8 | Dimm
Offset 2 Zero based DIMM number.
UINT8 | Rank
Offset 3 Zero based Rank number.
UINT8 | BankGroup
Offset 4 Zero based Bank Group number.
UINT8 | Bank
Offset 5 Zero based Bank number.
UINT16 | Cas
Offset 6 Zero based CAS number.
UINT32 | Ras
Offset 8 Zero based RAS number.

Detailed Description

SA memory address decode.

Definition at line 168 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_ADDRESS_DECODE Member List

This is the complete list of members for SA_ADDRESS_DECODE, including all inherited members.

Bank | SA_ADDRESS_DECODE
BankGroup | SA_ADDRESS_DECODE
Cas | SA_ADDRESS_DECODE
Channel | SA_ADDRESS_DECODE
Controller | SA_ADDRESS_DECODE
Dimm | SA_ADDRESS_DECODE
Rank | SA_ADDRESS_DECODE
Ras | SA_ADDRESS_DECODE
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_FUNCTION_CALLS Struct Reference

Public Attributes | List of all members
SA_FUNCTION_CALLS Struct Reference

Function calls into the SA. More...

#include <MemoryConfig.h>

Public Attributes

SA_IO_READ_8 IoRead8
Offset 0: - CPU I/O port 8-bit read.
SA_IO_READ_16 IoRead16
Offset 4: - CPU I/O port 16-bit read.
SA_IO_READ_32 IoRead32
Offset 8: - CPU I/O port 32-bit read.
SA_IO_WRITE_8 IoWrite8
Offset 12: - CPU I/O port 8-bit write.
SA_IO_WRITE_16 IoWrite16
Offset 16: - CPU I/O port 16-bit write.
SA_IO_WRITE_32 IoWrite32
Offset 20: - CPU I/O port 32-bit write.
SA_MMIO_READ_8 MmioRead8
Offset 24: - Memory Mapped I/O port 8-bit read.
SA_MMIO_READ_16 MmioRead16
Offset 28: - Memory Mapped I/O port 16-bit read.
SA_MMIO_READ_32 MmioRead32
Offset 32: - Memory Mapped I/O port 32-bit read.
SA_MMIO_READ_64 MmioRead64
Offset 36: - Memory Mapped I/O port 64-bit read.
SA_MMIO_WRITE_8 MmioWrite8
Offset 40: - Memory Mapped I/O port 8-bit write.
SA_MMIO_WRITE_16 MmioWrite16
Offset 44: - Memory Mapped I/O port 16-bit write.
SA_MMIO_WRITE_32 MmioWrite32
Offset 48: - Memory Mapped I/O port 32-bit write.
SA_MMIO_WRITE_64 MmioWrite64
Offset 52: - Memory Mapped I/O port 64-bit write.
SA_SMBUS_READ_8 SmbusRead8
Offset 56: - Smbus 8-bit read.
SA_SMBUS_READ_16 SmbusRead16
Offset 60: - Smbus 16-bit read.
SA_SMBUS_WRITE_8 SmbusWrite8
Offset 64: - Smbus 8-bit write.
SA_SMBUS_WRITE_16 SmbusWrite16
Offset 68: - Smbus 16-bit write.
SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress
Offset 72: - Get PCI device address.
SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress
Offset 76: - Get PCI express device address.
SA_GET_RTC_TIME GetRtcTime
Offset 80: - Get the current time value.
SA_GET_CPU_TIME GetCpuTime
Offset 84: - The current CPU time in milliseconds.
SA_MEMORY_COPY CopyMem
Offset 88: - Perform byte copy operation.
SA_MEMORY_SET_BYTE SetMem
Offset 92: - Perform byte initialization operation.
SA_MEMORY_SET_WORD SetMemWord
Offset 96: - Perform word initialization operation.
SA_MEMORY_SET_DWORD SetMemDword
Offset 100: - Perform dword initialization operation.
SA_LEFT_SHIFT_64 LeftShift64
Offset 104: - Left shift the 64-bit data value by specified number of bits.
SA_RIGHT_SHIFT_64 RightShift64
Offset 108: - Right shift the 64-bit data value by specified number of bits.
SA_MULT_U64_U32 MultU64x32
Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
SA_DIV_U64_U64 DivU64x64
Offset 116: - Divide a 64-bit data value by a 64-bit data value.
SA_GET_SPD_DATA GetSpdData
Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
SA_GET_RANDOM_NUMBER GetRandomNumber
Offset 124: - Get the next random 32-bit number.
SA_CPU_MAILBOX_READ CpuMailboxRead
Offset 128: - Perform a CPU mailbox read.
SA_CPU_MAILBOX_WRITE CpuMailboxWrite
Offset 132: - Perform a CPU mailbox write.
SA_GET_MEMORY_VDD GetMemoryVdd
Offset 136: - Get the current memory voltage (VDD).
SA_SET_MEMORY_VDD SetMemoryVdd
Offset 140: - Set the memory voltage (VDD) to the given value.
SA_CHECKPOINT CheckPoint
Offset 144: - Check point that is called at various points in the MRC.
SA_DEBUG_HOOK DebugHook
Offset 148: - Typically used to display to the I/O port 80h.
SA_DEBUG_PRINT DebugPrint
Offset 152: - Output a string to the debug stream/device.
SA_GET_RTC_CMOS GetRtcCmos
Offset 156: - Get the current value of the specified RTC CMOS location.
SA_MSR_READ_64 ReadMsr64
Offset 160: - Get the current value of the specified MSR location.
SA_MSR_WRITE_64 WriteMsr64
Offset 164 - Set the current value of the specified MSR location.
SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc
Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
SA_MRC_DRAM_RESET MrcDramReset
Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
SA_DELAY_NS MrcDelayNs
Offset 176 - Delay (stall) for the given amount of nanoseconds.
SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage
Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.

Detailed Description

Function calls into the SA.

Definition at line 240 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_FUNCTION_CALLS Member List

This is the complete list of members for SA_FUNCTION_CALLS, including all inherited members.

CheckPoint | SA_FUNCTION_CALLS
CopyMem | SA_FUNCTION_CALLS
CpuMailboxRead | SA_FUNCTION_CALLS
CpuMailboxWrite | SA_FUNCTION_CALLS
DebugHook | SA_FUNCTION_CALLS
DebugPrint | SA_FUNCTION_CALLS
DivU64x64 | SA_FUNCTION_CALLS
GetCpuTime | SA_FUNCTION_CALLS
GetMemoryVdd | SA_FUNCTION_CALLS
GetPciDeviceAddress | SA_FUNCTION_CALLS
GetPcieDeviceAddress | SA_FUNCTION_CALLS
GetRandomNumber | SA_FUNCTION_CALLS
GetRtcCmos | SA_FUNCTION_CALLS
GetRtcTime | SA_FUNCTION_CALLS
GetSpdData | SA_FUNCTION_CALLS
IoRead16 | SA_FUNCTION_CALLS
IoRead32 | SA_FUNCTION_CALLS
IoRead8 | SA_FUNCTION_CALLS
IoWrite16 | SA_FUNCTION_CALLS
IoWrite32 | SA_FUNCTION_CALLS
IoWrite8 | SA_FUNCTION_CALLS
LeftShift64 | SA_FUNCTION_CALLS
MmioRead16 | SA_FUNCTION_CALLS
MmioRead32 | SA_FUNCTION_CALLS
MmioRead64 | SA_FUNCTION_CALLS
MmioRead8 | SA_FUNCTION_CALLS
MmioWrite16 | SA_FUNCTION_CALLS
MmioWrite32 | SA_FUNCTION_CALLS
MmioWrite64 | SA_FUNCTION_CALLS
MmioWrite8 | SA_FUNCTION_CALLS
MrcDelayNs | SA_FUNCTION_CALLS
MrcDramReset | SA_FUNCTION_CALLS
MrcReturnFromSmc | SA_FUNCTION_CALLS
MultU64x32 | SA_FUNCTION_CALLS
ReadMsr64 | SA_FUNCTION_CALLS
RightShift64 | SA_FUNCTION_CALLS
SetMem | SA_FUNCTION_CALLS
SetMemDword | SA_FUNCTION_CALLS
SetMemoryPmicVoltage | SA_FUNCTION_CALLS
SetMemoryVdd | SA_FUNCTION_CALLS
SetMemWord | SA_FUNCTION_CALLS
SmbusRead16 | SA_FUNCTION_CALLS
SmbusRead8 | SA_FUNCTION_CALLS
SmbusWrite16 | SA_FUNCTION_CALLS
SmbusWrite8 | SA_FUNCTION_CALLS
WriteMsr64 | SA_FUNCTION_CALLS
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_MEMORY_DQDQS_MAPPING Struct Reference

Public Attributes | List of all members
SA_MEMORY_DQDQS_MAPPING Struct Reference

DqDqs Mapping. More...

#include <MemoryConfig.h>

Public Attributes

UINT8 | DqsMapCpu2Dram [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]
DqsMapCpu2Dram.
UINT8 | DqMapCpu2Dram [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]
DqMapCpu2Dram.

Detailed Description

DqDqs Mapping.

Definition at line 140 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_MEMORY_DQDQS_MAPPING Member List

This is the complete list of members for SA_MEMORY_DQDQS_MAPPING, including all inherited members.

DqMapCpu2Dram | SA_MEMORY_DQDQS_MAPPING
DqsMapCpu2Dram | SA_MEMORY_DQDQS_MAPPING
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_MEMORY_FUNCTIONS Struct Reference

Public Attributes | List of all members
SA_MEMORY_FUNCTIONS Struct Reference

Function calls into the MRC. More...

#include <MemoryConfig.h>

Public Attributes

SA_CHANNEL_EXIST MrcChannelExist
Offset 0: - Returns whether Channel is or is not present.
SA_PRINTF MrcPrintf
Offset 4: - Print to output stream/device.
SA_CHANGE_MARGIN MrcChangeMargin
Offset 8: - Change the margin.
SA_SIGN_EXTEND MrcSignExtend
Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain
Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
SA_UPDATE_VREF MrcUpdateVref
Offset 20: - Update the Vref value and wait until it is stable.

Detailed Description

Function calls into the MRC.

Definition at line 292 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_MEMORY_FUNCTIONS Member List

This is the complete list of members for SA_MEMORY_FUNCTIONS, including all inherited members.

MrcChangeMargin | SA_MEMORY_FUNCTIONS
MrcChannelExist | SA_MEMORY_FUNCTIONS
MrcPrintf | SA_MEMORY_FUNCTIONS
MrcSignExtend | SA_MEMORY_FUNCTIONS
MrcUpdateVref | SA_MEMORY_FUNCTIONS
ShiftPiCommandTrain | SA_MEMORY_FUNCTIONS
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_MEMORY_RCOMP Struct Reference

Public Attributes | List of all members
SA_MEMORY_RCOMP Struct Reference

Rcomp Policies. More...

#include <MemoryConfig.h>

Public Attributes

UINT16 | RcompResistor
Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms.
UINT16 | RcompTarget [MRC_MAX_RCOMP_TARGETS]
Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv.

Detailed Description

Rcomp Policies.

Definition at line 149 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_MEMORY_RCOMP Member List

This is the complete list of members for SA_MEMORY_RCOMP, including all inherited members.

RcompResistor | SA_MEMORY_RCOMP
RcompTarget | SA_MEMORY_RCOMP
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_MISC_PEI_CONFIG Struct Reference

Public Attributes | List of all members
SA_MISC_PEI_CONFIG Struct Reference

This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem. More...

#include <SaMiscPeiConfig.h>

Collaboration diagram for SA_MISC_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.

Detailed Description

This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem.

Revision 1:

  • Initial version.

Definition at line 47 of file SaMiscPeiConfig.h.

The documentation for this struct was generated from the following file:
  • SaMiscPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_MISC_PEI_CONFIG Member List

This is the complete list of members for SA_MISC_PEI_CONFIG, including all inherited members.

Header SA_MISC_PEI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_MISC_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
SA_MISC_PEI_PREMEM_CONFIG Struct Reference

This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc. More...

#include <SaMiscPeiPreMemConfig.h>

Collaboration diagram for SA_MISC_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | SpdAddressTable [MEM_CFG_MAX_SOCKETS]
Offset 28 Memory DIMMs' SPD address for reading SPD data. More...
VOID * S3DataPtr
Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path.
UINT32 | SmbusBar
Offset 48 Address of System Agent SMBUS BAR: 0xEFA0
UINT32 | TsegSize
Offset 52 Size of TSEG in bytes. More...
UINT32 | IedSize
Offset 56 (Test) Size of IED region in bytes. More...
UINT32 | SkipExtGfxScan:1
(Test) OFfset 60:0 :1=Skip External Gfx Device Scan; 0=Scan for external graphics devices. Set this policy to skip External Graphics card scanning if the platform uses Internal Graphics only.
UINT32 | BdatEnable:1
Offset 60:1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE, 1=TRUE.
UINT32 | TxtImplemented:1
OFfset 60:2 :This field currently is used to tell MRC if it should run after TXT initializatoin completed: 0=Run without waiting for TXT, 1=Run after TXT initialization by callback.
UINT32 | ScanExtGfxForLegacyOpRom:1
Offset 60:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs. More...
UINT32 | RsvdBits0:28
Offset 60:4 :Reserved for future use.
UINT8 | UserBd
Offset 64 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server.
UINT8 | LockPTMregs
(Test) Offset 65 Lock PCU Thermal Management registers: 0=FALSE, 1=TRUE
UINT8 | BdatTestType
Offset 66 When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: 0=RMT, 1=RMT Per Bit, 2=Margin 2D.
UINT8 | CridEnable
Offset 67 For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibility Revision ID (CRID) feature: 0=FALSE, 1=TRUE.
UINT32 | AcpiReservedMemorySize
Offset 68 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT32 | OpRomScanTempMmioBar
(Test) Offset 72 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!
UINT32 | OpRomScanTempMmioLimit
(Test) Offset 76 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >= 16MB!
UINT64 | AcpiReservedMemoryBase
Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT64 | SystemMemoryLength
Offset 88 Total system memory length from previous boot, this is required for S3 resume. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT8 | WrcFeatureEnable
Offset 96: Enable/Disable WRC (Write Cache) feature of IOP. When enabled, supports IO devices allocating onto the ring and into LLC.
UINT8 | FirstDimmBitMask
Offset 97: Defines which DIMM should be populated first on a 2DPC board. More...
UINT8 | FirstDimmBitMaskEcc
Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board. More...
UINT8 | Reserved1 [1]
Reserved for config block alignment.
UINT8 | Rsvd [4]
Reserved for config block alignment.

Detailed Description

This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc.

Revision 1:

  • Initial version. Revision 2:
  • Deprecate IedSize. Revision 3:
  • Adding ResizableBarSupport.

Definition at line 56 of file SaMiscPeiPreMemConfig.h.

Member Data Documentation

◆ FirstDimmBitMask

UINT8 SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMask

Offset 97: Defines which DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. Note: this mask is only for non-ECC DIMM.

Definition at line 124 of file SaMiscPeiPreMemConfig.h.

◆ FirstDimmBitMaskEcc

UINT8 SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMaskEcc

Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be be populated firstly. Note: this mask is only for ECC DIMM, not for non-ECC DIMM.

Definition at line 128 of file SaMiscPeiPreMemConfig.h.

◆ IedSize

UINT32 SA_MISC_PEI_PREMEM_CONFIG::IedSize

Offset 56 (Test) Size of IED region in bytes.

0 : IED Disabled (no memory occupied) 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) Note: Enabling IED may also enlarge TsegSize together.

Deprecated:

Definition at line 91 of file SaMiscPeiPreMemConfig.h.

◆ ScanExtGfxForLegacyOpRom

UINT32 SA_MISC_PEI_PREMEM_CONFIG::ScanExtGfxForLegacyOpRom

Offset 60:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs.

When enabled, if the primary graphics device is an external discrete graphics device, Si will scan the graphics device for legacy only VGA OpROMs.

This is intended to ease the implementation of a BIOS feature to automatically enable CSM if the Primary Gfx device only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM won't result in no video being displayed. This is useful for platforms that implement PCIe slots that allow the end user to install an arbitrary Gfx device.

This setting will only take effect if SkipExtGfxScan == 0. It is ignored otherwise.

  • Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
  • Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM

Definition at line 111 of file SaMiscPeiPreMemConfig.h.

◆ SpdAddressTable

UINT8 SA_MISC_PEI_PREMEM_CONFIG::SpdAddressTable[MEM_CFG_MAX_SOCKETS]

Offset 28 Memory DIMMs' SPD address for reading SPD data.

TGL Mapping 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 1 - Controller 0 Channel 0 Dimm 1 - DDR4 2 - Controller 0 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 3 - Controller 0 Channel 1 Dimm 1 -----— DDR5 2DPC 4 - Controller 0 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 6 - Controller 0 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 9 - Controller 1 Channel 0 Dimm 1 - DDR4 10 - Controller 1 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 11 - Controller 1 Channel 1 Dimm 1 -----— DDR5 2DPC 12 - Controller 1 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 14 - Controller 1 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5

Definition at line 74 of file SaMiscPeiPreMemConfig.h.

◆ TsegSize

UINT32 SA_MISC_PEI_PREMEM_CONFIG::TsegSize

Offset 52 Size of TSEG in bytes.

(Must be power of 2) 0x400000: 4MB for Release build (When IED enabled, it will be 8MB) 0x1000000 : 16MB for Debug build (Regardless IED enabled or disabled)

Definition at line 82 of file SaMiscPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • SaMiscPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_MISC_PEI_PREMEM_CONFIG Member List

This is the complete list of members for SA_MISC_PEI_PREMEM_CONFIG, including all inherited members.

AcpiReservedMemoryBase | SA_MISC_PEI_PREMEM_CONFIG
AcpiReservedMemorySize | SA_MISC_PEI_PREMEM_CONFIG
BdatEnable | SA_MISC_PEI_PREMEM_CONFIG
BdatTestType | SA_MISC_PEI_PREMEM_CONFIG
CridEnable | SA_MISC_PEI_PREMEM_CONFIG
FirstDimmBitMask | SA_MISC_PEI_PREMEM_CONFIG
FirstDimmBitMaskEcc | SA_MISC_PEI_PREMEM_CONFIG
Header | SA_MISC_PEI_PREMEM_CONFIG
IedSize | SA_MISC_PEI_PREMEM_CONFIG
LockPTMregs | SA_MISC_PEI_PREMEM_CONFIG
OpRomScanTempMmioBar | SA_MISC_PEI_PREMEM_CONFIG
OpRomScanTempMmioLimit | SA_MISC_PEI_PREMEM_CONFIG
Reserved1 | SA_MISC_PEI_PREMEM_CONFIG
Rsvd | SA_MISC_PEI_PREMEM_CONFIG
RsvdBits0 | SA_MISC_PEI_PREMEM_CONFIG
S3DataPtr | SA_MISC_PEI_PREMEM_CONFIG
ScanExtGfxForLegacyOpRom | SA_MISC_PEI_PREMEM_CONFIG
SkipExtGfxScan | SA_MISC_PEI_PREMEM_CONFIG
SmbusBar | SA_MISC_PEI_PREMEM_CONFIG
SpdAddressTable | SA_MISC_PEI_PREMEM_CONFIG
SystemMemoryLength | SA_MISC_PEI_PREMEM_CONFIG
TsegSize | SA_MISC_PEI_PREMEM_CONFIG
TxtImplemented | SA_MISC_PEI_PREMEM_CONFIG
UserBd | SA_MISC_PEI_PREMEM_CONFIG
WrcFeatureEnable | SA_MISC_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SA_XDCI_IRQ_INT_CONFIG Struct Reference

Public Attributes | List of all members
SA_XDCI_IRQ_INT_CONFIG Struct Reference

The SA XDCI INT Pin and IRQ number. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 | IntPing
Int Pin Number.
UINT8 | Irq
Irq Number.

Detailed Description

The SA XDCI INT Pin and IRQ number.

Definition at line 82 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SA_XDCI_IRQ_INT_CONFIG Member List

This is the complete list of members for SA_XDCI_IRQ_INT_CONFIG, including all inherited members.

IntPing | SA_XDCI_IRQ_INT_CONFIG
Irq | SA_XDCI_IRQ_INT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SATA_CONFIG Struct Reference

Public Attributes | List of all members
SATA_CONFIG Struct Reference

The SATA_CONFIG block describes the expected configuration of the SATA controllers. More...

#include <SataConfig.h>

Collaboration diagram for SATA_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | Enable
This member describes whether or not the SATA controllers should be enabled. More...
UINT8 | TestMode
(Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes
UINT8 | SalpSupport
0: Disable; 1: Enable Aggressive Link Power Management
UINT8 | PwrOptEnable
0: Disable; 1: Enable SATA Power Optimizer on PCH side.
UINT8 | EsataSpeedLimit
EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
UINT8 | LedEnable
SATA LED indicates SATA controller activity. 0: Disable; 1: Enable SATA LED.
UINT8 | RaidDeviceId
This option allows to configure SATA controller device ID while in RAID mode. More...
UINT8 | SataRstInterrupt
Controlls which interrupts will be linked to SATA controller CAP list This option will take effect only if SATA controller is in RAID mode Default: PchSataMsix
UINT8 | SataMode
Determines the system will be configured to which SATA mode. More...
UINT8 | SpeedLimit
Indicates the maximum speed the SATA controller can support. More...
UINT8 | EnclosureSupport
Enclosure Management Support. 0: Disable; 1: Enable.
UINT8 | SgpioSupport
Controlls whenever Serial GPIO support is enabled for controller 0: Disable; 1: Enable.
PCH_SATA_PORT_CONFIG | PortSettings [PCH_MAX_SATA_PORTS]
This member configures the features, property, and capability for each SATA port.
SATA_THERMAL_THROTTLING ThermalThrottling
This field decides the settings of Sata thermal throttling. More...

Detailed Description

The SATA_CONFIG block describes the expected configuration of the SATA controllers.

Revision 1:

  • Initial version. Revision 2:
  • Added DevSlpGpioPinMux.

Definition at line 134 of file SataConfig.h.

Member Data Documentation

◆ Enable

UINT8 SATA_CONFIG::Enable

This member describes whether or not the SATA controllers should be enabled.

0: Disable; 1: Enable.

Definition at line 139 of file SataConfig.h.

◆ EsataSpeedLimit

UINT8 SATA_CONFIG::EsataSpeedLimit

EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.

Please be noted, this setting could be cleared by HBA reset, which might be issued by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST. To support the Speed Limitation when POST, the EFI AHCI driver should preserve the setting before and after initialization. For support it after POST, it's dependent on driver's behavior. 0: Disable; 1: Enable

Definition at line 153 of file SataConfig.h.

◆ RaidDeviceId

UINT8 SATA_CONFIG::RaidDeviceId

This option allows to configure SATA controller device ID while in RAID mode.

Refer to SATA_RAID_DEV_ID enumeration for supported options. Choosing Client will allow RST driver loading, RSTe driver will not be able to load Choosing Alternate will not allow RST inbox driver loading in Windows Choosing Server will allow RSTe driver loading, RST driver will not load 0: Client; 1: Alternate; 2: Server

Definition at line 163 of file SataConfig.h.

◆ SataMode

UINT8 SATA_CONFIG::SataMode

Determines the system will be configured to which SATA mode.

Refer to SATA_MODE enumeration for supported options. Default is SataModeAhci.

Definition at line 175 of file SataConfig.h.

◆ SpeedLimit

UINT8 SATA_CONFIG::SpeedLimit

Indicates the maximum speed the SATA controller can support.

Refer to SATA_SPEED enumeration for supported options. 0h: SataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)

Definition at line 181 of file SataConfig.h.

◆ ThermalThrottling

SATA_THERMAL_THROTTLING SATA_CONFIG::ThermalThrottling

This field decides the settings of Sata thermal throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 196 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SATA_CONFIG Member List

This is the complete list of members for SATA_CONFIG, including all inherited members.

Enable | SATA_CONFIG
EnclosureSupport | SATA_CONFIG
EsataSpeedLimit | SATA_CONFIG
Header | SATA_CONFIG
LedEnable | SATA_CONFIG
PortSettings | SATA_CONFIG
PwrOptEnable | SATA_CONFIG
RaidDeviceId | SATA_CONFIG
SalpSupport | SATA_CONFIG
SataMode | SATA_CONFIG
SataRstInterrupt | SATA_CONFIG
SgpioSupport | SATA_CONFIG
SpeedLimit | SATA_CONFIG
TestMode | SATA_CONFIG
ThermalThrottling | SATA_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SATA_THERMAL_THROTTLING Struct Reference

Public Attributes | List of all members
SATA_THERMAL_THROTTLING Struct Reference

This structure lists PCH supported SATA thermal throttling register setting for customization. More...

#include <SataConfig.h>

Public Attributes

UINT32 | P0T1M: 2
Port 0 T1 Multipler.
UINT32 | P0T2M: 2
Port 0 T2 Multipler.
UINT32 | P0T3M: 2
Port 0 T3 Multipler.
UINT32 | P0TDisp: 2
Port 0 Tdispatch.
UINT32 | P1T1M: 2
Port 1 T1 Multipler.
UINT32 | P1T2M: 2
Port 1 T2 Multipler.
UINT32 | P1T3M: 2
Port 1 T3 Multipler.
UINT32 | P1TDisp: 2
Port 1 Tdispatch.
UINT32 | P0Tinact: 2
Port 0 Tinactive.
UINT32 | P0TDispFinit: 1
Port 0 Alternate Fast Init Tdispatch.
UINT32 | P1Tinact: 2
Port 1 Tinactive.
UINT32 | P1TDispFinit: 1
Port 1 Alternate Fast Init Tdispatch.
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values
UINT32 | RsvdBits0: 9
Reserved bits.

Detailed Description

This structure lists PCH supported SATA thermal throttling register setting for customization.

The settings is programmed through SATA Index/Data registers. When the SuggestedSetting is enabled, the customized values are ignored.

Definition at line 107 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SATA_THERMAL_THROTTLING Member List

This is the complete list of members for SATA_THERMAL_THROTTLING, including all inherited members.

P0T1M | SATA_THERMAL_THROTTLING
P0T2M | SATA_THERMAL_THROTTLING
P0T3M | SATA_THERMAL_THROTTLING
P0TDisp | SATA_THERMAL_THROTTLING
P0TDispFinit | SATA_THERMAL_THROTTLING
P0Tinact | SATA_THERMAL_THROTTLING
P1T1M | SATA_THERMAL_THROTTLING
P1T2M | SATA_THERMAL_THROTTLING
P1T3M | SATA_THERMAL_THROTTLING
P1TDisp | SATA_THERMAL_THROTTLING
P1TDispFinit | SATA_THERMAL_THROTTLING
P1Tinact | SATA_THERMAL_THROTTLING
RsvdBits0 | SATA_THERMAL_THROTTLING
SuggestedSetting | SATA_THERMAL_THROTTLING
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_CONFIG Struct Reference

The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers. More...

#include <SerialIoConfig.h>

Collaboration diagram for SERIAL_IO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
SERIAL_IO_SPI_CONFIG | SpiDeviceConfig [PCH_MAX_SERIALIO_SPI_CONTROLLERS]
SPI Configuration.
SERIAL_IO_I2C_CONFIG | I2cDeviceConfig [PCH_MAX_SERIALIO_I2C_CONTROLLERS]
I2C Configuration.
SERIAL_IO_UART_CONFIG | UartDeviceConfig [PCH_MAX_SERIALIO_UART_CONTROLLERS]
UART Configuration.

Detailed Description

The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers.

Revision 1:

  • Inital version. Revision 2:
  • Modified SPI Config to support pinmux functionality.

Definition at line 53 of file SerialIoConfig.h.

The documentation for this struct was generated from the following file:
  • SerialIoConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SERIAL_IO_CONFIG Member List

This is the complete list of members for SERIAL_IO_CONFIG, including all inherited members.

Header | SERIAL_IO_CONFIG
I2cDeviceConfig | SERIAL_IO_CONFIG
SpiDeviceConfig | SERIAL_IO_CONFIG
UartDeviceConfig | SERIAL_IO_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_I2C_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_I2C_CONFIG Struct Reference

Serial IO I2C Controller Configuration. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_I2C_CONFIG:
[legend]

Public Attributes

UINT8 PadTermination
SerialIoI2cPci see SERIAL_IO_I2C_MODE More...
I2C_PIN_MUX PinMux
I2C pin mux configuration.

Detailed Description

Serial IO I2C Controller Configuration.

Definition at line 236 of file SerialIoDevices.h.

Member Data Documentation

◆ PadTermination

UINT8 SERIAL_IO_I2C_CONFIG::PadTermination

SerialIoI2cPci see SERIAL_IO_I2C_MODE

I2C Pads Internal Termination. For more information please see Platform Design Guide. Supported values (check GPIO_ELECTRICAL_CONFIG for reference): GpioTermNone: No termination, GpioTermWpu1K: 1kOhm weak pull-up, GpioTermWpu5K: 5kOhm weak pull-up, GpioTermWpu20K: 20kOhm weak pull-up

Definition at line 247 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SERIAL_IO_I2C_CONFIG Member List

This is the complete list of members for SERIAL_IO_I2C_CONFIG, including all inherited members.

PadTermination | SERIAL_IO_I2C_CONFIG
PinMux | SERIAL_IO_I2C_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_SPI_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_SPI_CONFIG Struct Reference

The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_SPI_CONFIG:
[legend]

Public Attributes

UINT8 | Mode
SerialIoSpiPci see SERIAL_IO_SPI_MODE
UINT8 | DefaultCsOutput
0 = CS0 CS1, CS2, CS3. Default CS used by the SPI HC
UINT8 | CsPolarity [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
Selects SPI ChipSelect signal polarity, 0 = low 1 = High
UINT8 | CsEnable [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
0 = Enable 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
UINT8 | CsMode
0 = HW Control 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
UINT8 | CsState
0 = CS is set to low 1 = CS is set to high
SPI_PIN_MUX PinMux
SPI Pinmux configuration.

Detailed Description

The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.

Definition at line 94 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SERIAL_IO_SPI_CONFIG Member List

This is the complete list of members for SERIAL_IO_SPI_CONFIG, including all inherited members.

CsEnable | SERIAL_IO_SPI_CONFIG
CsMode | SERIAL_IO_SPI_CONFIG
CsPolarity | SERIAL_IO_SPI_CONFIG
CsState | SERIAL_IO_SPI_CONFIG
DefaultCsOutput | SERIAL_IO_SPI_CONFIG
Mode | SERIAL_IO_SPI_CONFIG
PinMux | SERIAL_IO_SPI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_UART_ATTRIBUTES Struct Reference

Public Attributes | List of all members
SERIAL_IO_UART_ATTRIBUTES Struct Reference

UART Settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | BaudRate
115200 Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
UINT8 | Parity
1 - No Parity see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
UINT8 | DataBits
8 MdePkg.dec PcdUartDefaultDataBits
UINT8 | StopBits
1 - One Stop Bit see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
UINT8 | AutoFlow
FALSE IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake

Detailed Description

UART Settings.

Definition at line 151 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SERIAL_IO_UART_ATTRIBUTES Member List

This is the complete list of members for SERIAL_IO_UART_ATTRIBUTES, including all inherited members.

AutoFlow | SERIAL_IO_UART_ATTRIBUTES
BaudRate | SERIAL_IO_UART_ATTRIBUTES
DataBits | SERIAL_IO_UART_ATTRIBUTES
Parity | SERIAL_IO_UART_ATTRIBUTES
StopBits | SERIAL_IO_UART_ATTRIBUTES
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SERIAL_IO_UART_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_UART_CONFIG Struct Reference

Serial IO UART Controller Configuration. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_UART_CONFIG:
[legend]

Public Attributes

SERIAL_IO_UART_ATTRIBUTES Attributes
see SERIAL_IO_UART_ATTRIBUTES
UART_PIN_MUX PinMux
UART pin mux configuration.
UINT8 | Mode
SerialIoUartPci see SERIAL_IO_UART_MODE
UINT8 | DBG2
FALSE If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
UINT8 | PowerGating
SerialIoUartPgAuto Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
UINT8 | DmaEnable
TRUE Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode

Detailed Description

Serial IO UART Controller Configuration.

Definition at line 174 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SERIAL_IO_UART_CONFIG Member List

This is the complete list of members for SERIAL_IO_UART_CONFIG, including all inherited members.

Attributes | SERIAL_IO_UART_CONFIG
DBG2 | SERIAL_IO_UART_CONFIG
DmaEnable | SERIAL_IO_UART_CONFIG
Mode | SERIAL_IO_UART_CONFIG
PinMux | SERIAL_IO_UART_CONFIG
PowerGating | SERIAL_IO_UART_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SI_CONFIG Struct Reference

Public Attributes | List of all members
SI_CONFIG Struct Reference

The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

#include <SiConfig.h>

Collaboration diagram for SI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
UINT8 | CsmFlag
offset 28 CSM status flag. More...
UINT8 | SkipSsidProgramming
This is used to skip the SSID programming in silicon code. More...
UINT8 | RsvdBytes0 [2]
offset 30 - 31
UINT16 | CustomizedSvid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID for all internal devices. More...
UINT16 | CustomizedSsid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for all internal devices. More...
UINT32 * | SsidTablePtr
SsidTablePtr contains the SVID_SID_INIT_ENTRY table. More...
UINT16 | NumberOfSsidTableEntry
Number of valid enties in SsidTablePtr. More...
UINT8 | RsvdBytes1 [2]
offset 42 - 43
UINT8 | SkipBiosDoneWhenFwUpdate
This is used to skip setting BIOS_DONE MSR during firmware update boot mode. More...
UINT8 | RsvdBytes2 [3]
Offset 45 - 47.

Detailed Description

The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware.

Revision 1: - Initial version. Revision 2: - Deprecate CsmFlag

Definition at line 52 of file SiConfig.h.

Member Data Documentation

◆ CsmFlag

UINT8 SI_CONFIG::CsmFlag

offset 28 CSM status flag.

Deprecated:

Definition at line 57 of file SiConfig.h.

◆ CustomizedSsid

UINT16 SI_CONFIG::CustomizedSsid

When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for all internal devices.

0: use silicon default SSID 0x7270 , Non-zero: use customized SSID. offset 34 - 35

Definition at line 77 of file SiConfig.h.

◆ CustomizedSvid

UINT16 SI_CONFIG::CustomizedSvid

When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID for all internal devices.

0: use silicon default SVID 0x8086 , Non-zero: use customized SVID. offset 32 - 33

Definition at line 71 of file SiConfig.h.

◆ NumberOfSsidTableEntry

UINT16 SI_CONFIG::NumberOfSsidTableEntry

Number of valid enties in SsidTablePtr.

This is valid when SkipSsidProgramming is FALSE; Default is 0. offset 40 - 41

Definition at line 116 of file SiConfig.h.

◆ SkipBiosDoneWhenFwUpdate

UINT8 SI_CONFIG::SkipBiosDoneWhenFwUpdate

This is used to skip setting BIOS_DONE MSR during firmware update boot mode.

When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting BIOS_DONE MSR at EndofPei. 0: FALSE, 1: TRUE Offset 44

Definition at line 124 of file SiConfig.h.

◆ SkipSsidProgramming

UINT8 SI_CONFIG::SkipSsidProgramming

This is used to skip the SSID programming in silicon code.

When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. 0: FALSE, 1: TRUE offset 29

Definition at line 64 of file SiConfig.h.

◆ SsidTablePtr

UINT32* SI_CONFIG::SsidTablePtr

SsidTablePtr contains the SVID_SID_INIT_ENTRY table.

This is valid when SkipSsidProgramming is FALSE; It doesn't need to contain entries for all Intel internal devices. It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Func# which needs to be overridden. In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId are required. Default is NULL.

E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0:31:3 to CCCC:DDDD, it can be done in platform like this: STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] = {0};

VOID SiPolicyUpdate () { UINT32 EntryCount = 0; SiPolicy->SkipSsidProgramming = FALSE; SiPolicy->SsidTablePtr = mSsidTablePtr;

mSsidTablePtr[EntryCount].Address.Bits.Device = SpiDeviceNumber (); mSsidTablePtr[EntryCount].Address.Bits.Function = SpiFunctionNumber (); mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xAAAA; mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xBBBB; EntryCount ++; mSsidTablePtr[EntryCount].Address.Bits.Device = HdaDevNumber (); mSsidTablePtr[EntryCount].Address.Bits.Function = HdaFuncNumber (); mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xCCCC; mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xDDDD; EntryCount ++; ASSERT (EntryCount < SI_MAX_DEVICE_COUNT); SiPolicy->NumberOfSsidTableEntry = EntryCount; } offset 36 - 39

Definition at line 110 of file SiConfig.h.

The documentation for this struct was generated from the following file:
  • SiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


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SI_CONFIG Member List

This is the complete list of members for SI_CONFIG, including all inherited members.

CsmFlag | SI_CONFIG
CustomizedSsid | SI_CONFIG
CustomizedSvid | SI_CONFIG
Header | SI_CONFIG
NumberOfSsidTableEntry | SI_CONFIG
RsvdBytes0 | SI_CONFIG
RsvdBytes1 | SI_CONFIG
RsvdBytes2 | SI_CONFIG
SkipBiosDoneWhenFwUpdate | SI_CONFIG
SkipSsidProgramming | SI_CONFIG
SsidTablePtr | SI_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
SI_PREMEM_CONFIG Struct Reference

The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

#include <SiPreMemConfig.h>

Collaboration diagram for SI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
UINT32 | PlatformDebugConsent: 4
Platform Debug Consent As a main switch to enable platform debug capability and relevant settings with specified probe type. More...
UINT32 | RsvdBits: 28
offset 28 - 31
UINT8 | SkipOverrideBootModeWhenFwUpdate
This is used to skip override boot mode during firmware update boot mode. More...
UINT8 | RsvdBytes [3]
offset 32

Detailed Description

The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware.

Revision 1:

  • Initial version.

Definition at line 58 of file SiPreMemConfig.h.

Member Data Documentation

◆ PlatformDebugConsent

UINT32 SI_PREMEM_CONFIG::PlatformDebugConsent

Platform Debug Consent As a main switch to enable platform debug capability and relevant settings with specified probe type.

Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.

PDC-dependent policies are listed: DciPreMemConfig->DciEn CpuTraceHubConfig->EnableMode CpuTraceHubConfig->CpuTraceHubMemReg0Size CpuTraceHubConfig->CpuTraceHubMemReg1Size PchTraceHubPreMemConfig->EnableMode PchTraceHubPreMemConfig->MemReg0Size PchTraceHubPreMemConfig->MemReg1Size

Note: DCI OOB (aka BSSB) uses CCA probe. Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE 0:Disabled; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual

Definition at line 78 of file SiPreMemConfig.h.

◆ SkipOverrideBootModeWhenFwUpdate

UINT8 SI_PREMEM_CONFIG::SkipOverrideBootModeWhenFwUpdate

This is used to skip override boot mode during firmware update boot mode.

When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init. 0: FALSE, 1: TRUE

Definition at line 86 of file SiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • SiPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


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SI_PREMEM_CONFIG Member List

This is the complete list of members for SI_PREMEM_CONFIG, including all inherited members.

Header | SI_PREMEM_CONFIG
PlatformDebugConsent | SI_PREMEM_CONFIG
RsvdBits | SI_PREMEM_CONFIG
RsvdBytes | SI_PREMEM_CONFIG
SkipOverrideBootModeWhenFwUpdate | SI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SMBIOS_STRUCTURE Struct Reference

List of all members
SMBIOS_STRUCTURE Struct Reference

The Smbios structure header. More...

#include <FirmwareVersionInfoHob.h>

Detailed Description

The Smbios structure header.

Definition at line 48 of file FirmwareVersionInfoHob.h.

The documentation for this struct was generated from the following file:
  • FirmwareVersionInfoHob.h
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SMBIOS_STRUCTURE Member List

This is the complete list of members for SMBIOS_STRUCTURE, including all inherited members.

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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SPD_DATA_BUFFER Struct Reference

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SPD_DATA_BUFFER Struct Reference

SPD Data Buffer. More...

#include <MemoryConfig.h>

Public Attributes

UINT8 SpdData [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]
SpdData.

Detailed Description

SPD Data Buffer.

Definition at line 132 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SPD_DATA_BUFFER Member List

This is the complete list of members for SPD_DATA_BUFFER, including all inherited members.

SpdData SPD_DATA_BUFFER
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SPD_OFFSET_TABLE Struct Reference

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SPD_OFFSET_TABLE Struct Reference

SPD Offset Table. More...

#include <MemoryConfig.h>

Public Attributes

UINT16 | Start
Offset 0.
UINT16 | End
Offset 2.
UINT8 | BootMode
Offset 4.
UINT8 | Reserved3 [3]
Offset 5 Reserved for future use.

Detailed Description

SPD Offset Table.

Definition at line 158 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SPD_OFFSET_TABLE Member List

This is the complete list of members for SPD_OFFSET_TABLE, including all inherited members.

BootMode | SPD_OFFSET_TABLE
End | SPD_OFFSET_TABLE
Reserved3 | SPD_OFFSET_TABLE
Start | SPD_OFFSET_TABLE
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SPI_PIN_MUX Struct Reference

Public Attributes | List of all members
SPI_PIN_MUX Struct Reference

SPI signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Cs [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*.
UINT32 | Clk
CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*.
UINT32 | Miso
MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*.
UINT32 | Mosi
MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*.

Detailed Description

SPI signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h for supported settings on a given platform

Definition at line 84 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


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SPI_PIN_MUX Member List

This is the complete list of members for SPI_PIN_MUX, including all inherited members.

Clk | SPI_PIN_MUX
Cs | SPI_PIN_MUX
Miso | SPI_PIN_MUX
Mosi | SPI_PIN_MUX
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SVID_SID_VALUE Struct Reference

List of all members
SVID_SID_VALUE Struct Reference

Subsystem Vendor ID / Subsystem ID. More...

#include <SiConfig.h>

Detailed Description

Subsystem Vendor ID / Subsystem ID.

Definition at line 137 of file SiConfig.h.

The documentation for this struct was generated from the following file:
  • SiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

SVID_SID_VALUE Member List

This is the complete list of members for SVID_SID_VALUE, including all inherited members.

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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_DEVEN_PEI_PREMEM_CONFIG Union Reference

Public Attributes | List of all members
TCSS_DEVEN_PEI_PREMEM_CONFIG Union Reference

The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT32 TcssDevEn
Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH.

Detailed Description

The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.

Definition at line 48 of file TcssPeiPreMemConfig.h.

The documentation for this union was generated from the following file:
  • TcssPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_DEVEN_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_DEVEN_PEI_PREMEM_CONFIG, including all inherited members.

TcssDevEn TCSS_DEVEN_PEI_PREMEM_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_IOM_ORI_OVERRIDE Struct Reference

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TCSS_IOM_ORI_OVERRIDE Struct Reference

The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT16 | AuxOri
Bits defining value for IOM Aux Orientation Register.
UINT16 | HslOri
Bits defining value for IOM HSL Orientation Register.

Detailed Description

The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.

Definition at line 134 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_IOM_ORI_OVERRIDE Member List

This is the complete list of members for TCSS_IOM_ORI_OVERRIDE, including all inherited members.

AuxOri | TCSS_IOM_ORI_OVERRIDE
HslOri | TCSS_IOM_ORI_OVERRIDE
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_IOM_PEI_CONFIG Struct Reference

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TCSS_IOM_PEI_CONFIG Struct Reference

The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_IOM_PEI_CONFIG:
[legend]

Public Attributes

IOM_AUX_ORI_PAD_CONFIG | IomAuxPortPad [MAX_IOM_AUX_BIAS_COUNT]
The IOM_AUX_ORI_BIAS_CTRL port config setting.
IOM_INTERFACE_CONFIG IomInterface
Config settings are BIOS <-> IOM interface.
PMC_INTERFACE_CONFIG PmcInterface
Config settings for BIOS <-> PMC interface.
UINT8 | TcStateLimit
Tcss C-State deep stage.
UINT8 | Reserved [3]
Reserved bytes for future use.

Detailed Description

The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.

Definition at line 142 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_IOM_PEI_CONFIG Member List

This is the complete list of members for TCSS_IOM_PEI_CONFIG, including all inherited members.

IomAuxPortPad | TCSS_IOM_PEI_CONFIG
IomInterface | TCSS_IOM_PEI_CONFIG
PmcInterface | TCSS_IOM_PEI_CONFIG
Reserved | TCSS_IOM_PEI_CONFIG
TcStateLimit | TCSS_IOM_PEI_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_MISC_PEI_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_MISC_PEI_CONFIG Struct Reference

The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_MISC_PEI_CONFIG:
[legend]

Public Attributes

SA_XDCI_IRQ_INT_CONFIG SaXdci
System Agent Xdci Int Pin and Irq setting.
UINT8 | EnableTcssCovTypeA [MAX_TCSS_USB3_PORTS]
Enable / Disable Type C Port X Convert to TypeA.
UINT8 | MappingPchXhciUsbA [MAX_TCSS_USB3_PORTS]
PCH xhci port number for Type C Port x mapping.
UINT8 | IomStayInTCColdSeconds
Set IOM stay in TC cold seconds.
UINT8 | IomBeforeEnteringTCColdSeconds
Set IOM before entering TC cold seconds.
UINT8 | Rsvd [2]
Reserved bytes for future use.

Detailed Description

The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.

Definition at line 154 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_MISC_PEI_CONFIG Member List

This is the complete list of members for TCSS_MISC_PEI_CONFIG, including all inherited members.

EnableTcssCovTypeA | TCSS_MISC_PEI_CONFIG
IomBeforeEnteringTCColdSeconds | TCSS_MISC_PEI_CONFIG
IomStayInTCColdSeconds | TCSS_MISC_PEI_CONFIG
MappingPchXhciUsbA | TCSS_MISC_PEI_CONFIG
Rsvd | TCSS_MISC_PEI_CONFIG
SaXdci | TCSS_MISC_PEI_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_MISC_PEI_PREMEM_CONFIG Struct Reference

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TCSS_MISC_PEI_PREMEM_CONFIG Struct Reference

The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT8 | PcieMultipleSegmentEnabled
This is policy to control Multiple Segment setting. More...
UINT8 | Rsvd [3]
Deprecate. More...

Detailed Description

The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS.

Revision 1: - Initial version.

Definition at line 76 of file TcssPeiPreMemConfig.h.

Member Data Documentation

◆ PcieMultipleSegmentEnabled

UINT8 TCSS_MISC_PEI_PREMEM_CONFIG::PcieMultipleSegmentEnabled

This is policy to control Multiple Segment setting.

When Disabled all the iTBT PCIe RP are located at Segment0 When Enabled all the iTBT PCIe RP are located at Segment1, FSP Wrapper need to update PCIEXBAR and PcdPciExpressRegionLength to 512MB prior to FspmWrapperPeim. 0: Disable, 1: Enable

Definition at line 85 of file TcssPeiPreMemConfig.h.

◆ Rsvd

UINT8 TCSS_MISC_PEI_PREMEM_CONFIG::Rsvd[3]

Deprecate.

Reserved bytes for future use, align to multiple 4

Definition at line 86 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_MISC_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_MISC_PEI_PREMEM_CONFIG, including all inherited members.

PcieMultipleSegmentEnabled | TCSS_MISC_PEI_PREMEM_CONFIG
Rsvd | TCSS_MISC_PEI_PREMEM_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PCIE_PEI_POLICY Struct Reference

List of all members
TCSS_PCIE_PEI_POLICY Struct Reference

TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_PCIE_PEI_POLICY:
[legend]

Detailed Description

TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.

Definition at line 127 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_PCIE_PEI_POLICY Member List

This is the complete list of members for TCSS_PCIE_PEI_POLICY, including all inherited members.

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PCIE_PORT_POLICY Struct Reference

Public Attributes | List of all members
TCSS_PCIE_PORT_POLICY Struct Reference

The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 | AcsEnabled
Indicate whether the ACS is enabled. 0: Disable; 1: Enable.
UINT8 | DpcEnabled
Downstream Port Containment. 0: Disable; 1: Enable
UINT8 | RpDpcExtensionsEnabled
RP Extensions for Downstream Port Containment. 0: Disable; 1: Enable
UINT8 | LtrEnable
Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
UINT8 | PtmEnabled
Enables PTM capability.
UINT8 | Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
UINT8 | SlotNumber
Indicates the slot number for the root port. Default is the value as root port index.
UINT8 | SlotPowerLimitScale
(Test) Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is zero.
UINT16 | SlotPowerLimitValue
(Test) Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is zero.
UINT8 | AdvancedErrorReporting
Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable.
UINT8 | UnsupportedRequestReport
Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable.
UINT8 | FatalErrorReport
Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | NoFatalErrorReport
Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | CorrectableErrorReport
Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnFatalError
Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnNonFatalError
Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnCorrectableError
Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable.
UINT16 | LtrMaxSnoopLatency
Latency Tolerance Reporting, Max Snoop Latency.
UINT16 | LtrMaxNoSnoopLatency
Latency Tolerance Reporting, Max Non-Snoop Latency.
UINT8 | SnoopLatencyOverrideMode
Latency Tolerance Reporting, Snoop Latency Override Mode.
UINT8 | SnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
UINT16 | SnoopLatencyOverrideValue
Latency Tolerance Reporting, Snoop Latency Override Value.
UINT8 | NonSnoopLatencyOverrideMode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
UINT8 | NonSnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
UINT16 | NonSnoopLatencyOverrideValue
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
UINT8 | ForceLtrOverride
0: Disable; 1: Enable.
UINT8 | LtrConfigLock
0: Disable; 1: Enable.

Detailed Description

The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.

Definition at line 91 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_PCIE_PORT_POLICY Member List

This is the complete list of members for TCSS_PCIE_PORT_POLICY, including all inherited members.

AcsEnabled | TCSS_PCIE_PORT_POLICY
AdvancedErrorReporting | TCSS_PCIE_PORT_POLICY
Aspm | TCSS_PCIE_PORT_POLICY
CorrectableErrorReport | TCSS_PCIE_PORT_POLICY
DpcEnabled | TCSS_PCIE_PORT_POLICY
FatalErrorReport | TCSS_PCIE_PORT_POLICY
ForceLtrOverride | TCSS_PCIE_PORT_POLICY
LtrConfigLock | TCSS_PCIE_PORT_POLICY
LtrEnable | TCSS_PCIE_PORT_POLICY
LtrMaxNoSnoopLatency | TCSS_PCIE_PORT_POLICY
LtrMaxSnoopLatency | TCSS_PCIE_PORT_POLICY
NoFatalErrorReport | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideMode | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideMultiplier | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideValue | TCSS_PCIE_PORT_POLICY
PtmEnabled | TCSS_PCIE_PORT_POLICY
RpDpcExtensionsEnabled | TCSS_PCIE_PORT_POLICY
SlotNumber | TCSS_PCIE_PORT_POLICY
SlotPowerLimitScale | TCSS_PCIE_PORT_POLICY
SlotPowerLimitValue | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideMode | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideMultiplier | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideValue | TCSS_PCIE_PORT_POLICY
SystemErrorOnCorrectableError | TCSS_PCIE_PORT_POLICY
SystemErrorOnFatalError | TCSS_PCIE_PORT_POLICY
SystemErrorOnNonFatalError | TCSS_PCIE_PORT_POLICY
UnsupportedRequestReport | TCSS_PCIE_PORT_POLICY
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PEI_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_PEI_CONFIG Struct Reference

The TCSS_PEI_CONFIG block describes TCSS settings for SA. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
TCSS_PCIE_PEI_POLICY PciePolicy
The PCIe Config.
USB_CONFIG UsbConfig
USB config is shared between PCH and SA.
TCSS_IOM_PEI_CONFIG IomConfig
The Iom Config.
TCSS_MISC_PEI_CONFIG MiscConfig
The MISC Config.

Detailed Description

The TCSS_PEI_CONFIG block describes TCSS settings for SA.

Definition at line 166 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TCSS_PEI_CONFIG Member List

This is the complete list of members for TCSS_PEI_CONFIG, including all inherited members.

Header | TCSS_PEI_CONFIG
IomConfig | TCSS_PEI_CONFIG
MiscConfig | TCSS_PEI_CONFIG
PciePolicy | TCSS_PEI_CONFIG
UsbConfig | TCSS_PEI_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_PEI_PREMEM_CONFIG Struct Reference

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TCSS_PEI_PREMEM_CONFIG Struct Reference

This configuration block describes TCSS settings. More...

#include <TcssPeiPreMemConfig.h>

Collaboration diagram for TCSS_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig
TCSS DEVEN.
TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig
USB Type C Port Configuration.
TCSS_MISC_PEI_PREMEM_CONFIG MiscConfig
The MISC PreMem Config.

Detailed Description

This configuration block describes TCSS settings.

Revision 1:

  • Initial version. Revision 2:
  • Deprecate PcieMultipleSegmentEnabled

Definition at line 96 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h
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TCSS_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_PEI_PREMEM_CONFIG, including all inherited members.

DevEnConfig | TCSS_PEI_PREMEM_CONFIG
Header | TCSS_PEI_PREMEM_CONFIG
MiscConfig | TCSS_PEI_PREMEM_CONFIG
UsbTcConfig | TCSS_PEI_PREMEM_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TCSS_USBTC_PEI_PERMEM_CONFIG Struct Reference

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TCSS_USBTC_PEI_PERMEM_CONFIG Struct Reference

The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT32 | UsbTcPortEn: 4
bitmap for USB Type C enabled ports
UINT32 | Rsvd: 28
Reserved bytes for future use.

Detailed Description

The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.

Definition at line 67 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h
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TCSS_USBTC_PEI_PERMEM_CONFIG Member List

This is the complete list of members for TCSS_USBTC_PEI_PERMEM_CONFIG, including all inherited members.

Rsvd | TCSS_USBTC_PEI_PERMEM_CONFIG
UsbTcPortEn | TCSS_USBTC_PEI_PERMEM_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TELEMETRY_PEI_CONFIG Struct Reference

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TELEMETRY_PEI_CONFIG Struct Reference

This configuration block describes Telemetry settings in PostMem. More...

#include <TelemetryPeiConfig.h>

Collaboration diagram for TELEMETRY_PEI_CONFIG:
[legend]

Public Attributes

UINT32 CpuCrashLogEnable
Config Block Header.

Detailed Description

This configuration block describes Telemetry settings in PostMem.

Revision 1:

  • Initial version.

Definition at line 63 of file TelemetryPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TelemetryPeiConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TELEMETRY_PEI_CONFIG Member List

This is the complete list of members for TELEMETRY_PEI_CONFIG, including all inherited members.

CpuCrashLogEnable TELEMETRY_PEI_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TELEMETRY_PEI_PREMEM_CONFIG Struct Reference

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TELEMETRY_PEI_PREMEM_CONFIG Struct Reference

This configuration block describes Telemetry settings in PreMem. More...

#include <TelemetryPeiConfig.h>

Collaboration diagram for TELEMETRY_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

UINT32 CpuCrashLogDevice
Config Block Header.

Detailed Description

This configuration block describes Telemetry settings in PreMem.

Revision 1:

  • Initial version.

Definition at line 53 of file TelemetryPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TelemetryPeiConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TELEMETRY_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TELEMETRY_PEI_PREMEM_CONFIG, including all inherited members.

CpuCrashLogDevice TELEMETRY_PEI_PREMEM_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: THC_CONFIG Struct Reference

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THC_CONFIG Struct Reference

THC_CONFIG block provides the configurations forTouch Host Controllers. More...

#include <ThcConfig.h>

Collaboration diagram for THC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
THC_PORT ThcPort [2]
Port Configuration.

Detailed Description

THC_CONFIG block provides the configurations forTouch Host Controllers.

Assignment field in each THC port controlls the THC behavior.

Available scenarios: 1: Single Port 0 used by THC0

  • THC0 Enabled
  • Port0 assigned to THC0
  • Port1 unassigned
  • THC1 will be automatically Disabled. 2: Both ports used by THC0
  • THC0 Enabled
  • Port0 assigned to THC0
  • Port1 assigned to THC0
  • THC1 will be automatically Disabled. 3: Port 0 used by THC0 and Port 1 used by THC1
  • THC0 Enabled
  • Port0 assigned to THC0
  • THC1 Enabled
  • Port1 assigned to THC1. 4: Both Ports unassigned. Both THC Controllers will be disabled in that case.
Note
Invalid scenario that will cause ASSERT.
  1. Same port Number assigned to THC0 or THC1.
  2. Two Ports assigned to THC1.

Definition at line 125 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

THC_CONFIG Member List

This is the complete list of members for THC_CONFIG, including all inherited members.

Header | THC_CONFIG
ThcPort | THC_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: THC_HID_OVER_SPI Struct Reference

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THC_HID_OVER_SPI Struct Reference

THC Hid Over SPI mode related settings. More...

#include <ThcConfig.h>

Public Attributes

UINT32 | ResetPad
Reset Pad - 0x0 = THC HW default BIOS will pass Pad infromation to ACPI, this Pad is used in _RST function or by the BIOS Quick SPI driver.
UINT32 | ResetPadTrigger
Reset Pad Trigger.
UINT32 | Frequency
Connection Speed - SPI Frequency in Hz.
UINT32 | InputReportHeaderAddress
Input Report Header Address.
UINT32 | InputReportBodyAddress
Input Report Body Address.
UINT32 | OutputReportAddress
Output Report Address.
UINT32 | ReadOpcode
Read Opcode.
UINT32 | WriteOpcode
Write Opcode.
UINT32 | Flags
Flags.

Detailed Description

THC Hid Over SPI mode related settings.

Only applicable when HidOverSpi is enbled.

Definition at line 66 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

THC_HID_OVER_SPI Member List

This is the complete list of members for THC_HID_OVER_SPI, including all inherited members.

Flags | THC_HID_OVER_SPI
Frequency | THC_HID_OVER_SPI
InputReportBodyAddress | THC_HID_OVER_SPI
InputReportHeaderAddress | THC_HID_OVER_SPI
OutputReportAddress | THC_HID_OVER_SPI
ReadOpcode | THC_HID_OVER_SPI
ResetPad | THC_HID_OVER_SPI
ResetPadTrigger | THC_HID_OVER_SPI
WriteOpcode | THC_HID_OVER_SPI
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: THC_PORT Struct Reference

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THC_PORT Struct Reference

Port Configuration structure required for each Port that THC might use. More...

#include <ThcConfig.h>

Collaboration diagram for THC_PORT:
[legend]

Public Attributes

UINT32 | Assignment
Sets THCx assignment see THC_PORT_ASSIGNMENT.
UINT32 | InterruptPinMuxing
Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*.
UINT8 | WakeOnTouch
1 = Enable 0 = Disable. Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI
UINT8 | Mode
1 = Hid over SPI 0 = THC. Switch between Intel THC protcol and Industry standard HID Over SPI protocol.
UINT8 | Reserved [2]
Reserved.
THC_HID_OVER_SPI HidOverSpi
Hid Over Spi mode settings.
UINT32 | ActiveLtr
0xFFFFFFFF = Driver Default Active Ltr
UINT32 | IdleLtr
0xFFFFFFFF = Driver Default Idle Ltr
UINT32 | LimitPacketSize
Limit Packet Size.
UINT32 | PerformanceLimitation
Performance Limitation.

Detailed Description

Port Configuration structure required for each Port that THC might use.

Definition at line 82 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

THC_PORT Member List

This is the complete list of members for THC_PORT, including all inherited members.

ActiveLtr | THC_PORT
Assignment | THC_PORT
HidOverSpi | THC_PORT
IdleLtr | THC_PORT
InterruptPinMuxing | THC_PORT
LimitPacketSize | THC_PORT
Mode | THC_PORT
PerformanceLimitation | THC_PORT
Reserved | THC_PORT
WakeOnTouch | THC_PORT
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: THERMAL_CONFIG Struct Reference

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THERMAL_CONFIG Struct Reference

The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block. More...

#include <ThermalConfig.h>

Collaboration diagram for THERMAL_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PchHotEnable: 1
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: Disabled, 1: Enabled.
THERMAL_THROTTLE_LEVELS TTLevels
This field decides the settings of Thermal throttling. More...
DMI_HW_WIDTH_CONTROL DmiHaAWC
This field decides the settings of DMI throttling. More...
PCH_MEMORY_THROTTLING MemoryThrottling
Memory Thermal Management settings.
UINT16 | PchHotLevel
The recommendation is the same as Cat Trip point. More...

Detailed Description

The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.

Definition at line 145 of file ThermalConfig.h.

Member Data Documentation

◆ DmiHaAWC

DMI_HW_WIDTH_CONTROL THERMAL_CONFIG::DmiHaAWC

This field decides the settings of DMI throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 158 of file ThermalConfig.h.

◆ PchHotLevel

UINT16 THERMAL_CONFIG::PchHotLevel

The recommendation is the same as Cat Trip point.

This field decides the temperature, default is 120. Temperature value used for PCHHOT# pin assertion based on 2s complement format

  • 0x001 positive 1'C
  • 0x000 0'C
  • 0x1FF negative 1'C
  • 0x1D8 negative 40'C
  • and so on

Definition at line 173 of file ThermalConfig.h.

◆ TTLevels

THERMAL_THROTTLE_LEVELS THERMAL_CONFIG::TTLevels

This field decides the settings of Thermal throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 153 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

THERMAL_CONFIG Member List

This is the complete list of members for THERMAL_CONFIG, including all inherited members.

DmiHaAWC | THERMAL_CONFIG
Header | THERMAL_CONFIG
MemoryThrottling | THERMAL_CONFIG
PchHotEnable | THERMAL_CONFIG
PchHotLevel | THERMAL_CONFIG
TTLevels | THERMAL_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: THERMAL_THROTTLE_LEVELS Struct Reference

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THERMAL_THROTTLE_LEVELS Struct Reference

This structure lists PCH supported throttling register setting for custimization. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | T0Level: 9
Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | T1Level: 9
Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | T2Level: 9
Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | TTEnable: 1
Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
UINT32 | TTState13Enable: 1
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
UINT32 | TTLock: 1
When set to 1, this entire register (TL) is locked and remains locked until the next platform reset. More...
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values.
UINT32 | PchCrossThrottling: 1
ULT processors support thermal management and cross thermal throttling between the processor package and LP PCH. More...
UINT32 | Rsvd0
Reserved bytes.

Detailed Description

This structure lists PCH supported throttling register setting for custimization.

When the SuggestedSetting is enabled, the customized values are ignored.

Definition at line 47 of file ThermalConfig.h.

Member Data Documentation

◆ PchCrossThrottling

UINT32 THERMAL_THROTTLE_LEVELS::PchCrossThrottling

ULT processors support thermal management and cross thermal throttling between the processor package and LP PCH.

The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH thermal status to the processor which is factored into the processor throttling. Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled.

Definition at line 69 of file ThermalConfig.h.

◆ TTLock

UINT32 THERMAL_THROTTLE_LEVELS::TTLock

When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.

If SuggestedSetting is used, this setting is ignored.

Definition at line 61 of file ThermalConfig.h.

◆ TTState13Enable

UINT32 THERMAL_THROTTLE_LEVELS::TTState13Enable

When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.

If SuggestedSetting is used, this setting is ignored.

Definition at line 56 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
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THERMAL_THROTTLE_LEVELS Member List

This is the complete list of members for THERMAL_THROTTLE_LEVELS, including all inherited members.

PchCrossThrottling | THERMAL_THROTTLE_LEVELS
Rsvd0 | THERMAL_THROTTLE_LEVELS
SuggestedSetting | THERMAL_THROTTLE_LEVELS
T0Level | THERMAL_THROTTLE_LEVELS
T1Level | THERMAL_THROTTLE_LEVELS
T2Level | THERMAL_THROTTLE_LEVELS
TTEnable | THERMAL_THROTTLE_LEVELS
TTLock | THERMAL_THROTTLE_LEVELS
TTState13Enable | THERMAL_THROTTLE_LEVELS
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TRACE_HUB_CONFIG Struct Reference

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TRACE_HUB_CONFIG Struct Reference

TRACE_HUB_CONFIG block describes TraceHub settings. More...

#include <TraceHubConfig.h>

Public Attributes

UINT8 | EnableMode
Trace hub mode. More...
UINT8 | MemReg0Size
Trace hub memory buffer region size policy. More...
UINT8 | AetEnabled
AET Trace. More...

Detailed Description

TRACE_HUB_CONFIG block describes TraceHub settings.

Definition at line 78 of file TraceHubConfig.h.

Member Data Documentation

◆ AetEnabled

UINT8 TRACE_HUB_CONFIG::AetEnabled

AET Trace.

AET base address can be set to FW Base either from CPU trace hub or PCH one. AetEnabled must be exclusive, if AetEnabled = 1 for CPU trace hub, must AetEnabled = 0 for PCH one. The default is set to PCH. CPU Trace Hub 0 = Disabled; 1 = Enabled PCH Trace Hub 0 = Disabled; 1 = Enabled

Definition at line 104 of file TraceHubConfig.h.

◆ EnableMode

UINT8 TRACE_HUB_CONFIG::EnableMode

Trace hub mode.

Default is disabled. Target Debugger mode refers to debug tool running on target device itself and it works as a conventional PCI device; Host Debugger mode refers to SUT debugged via probe on host, configured as ACPI device with PCI configuration sapce hidden. 0 = Disable; 1 = Target Debugger mode; 2 = Host Debugger mode Refer to TRACE_HUB_ENABLE_MODE

Definition at line 86 of file TraceHubConfig.h.

◆ MemReg0Size

UINT8 TRACE_HUB_CONFIG::MemReg0Size

Trace hub memory buffer region size policy.

The avaliable memory size options are: 0:0MB (none), 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is enabled, the total size limits to 256 MB. Refer to TRACE_BUFFER_SIZE

Definition at line 93 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TRACE_HUB_CONFIG Member List

This is the complete list of members for TRACE_HUB_CONFIG, including all inherited members.

AetEnabled | TRACE_HUB_CONFIG
EnableMode | TRACE_HUB_CONFIG
MemReg0Size | TRACE_HUB_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TS_GPIO_PIN_SETTING Struct Reference

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TS_GPIO_PIN_SETTING Struct Reference

This structure configures PCH memory throttling thermal sensor GPIO PIN settings. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | PmsyncEnable: 1
GPIO PM_SYNC enable, 0:Diabled, 1:Enabled When enabled, RC will overrides the selected GPIO native mode. More...
UINT32 | C0TransmitEnable: 1
GPIO Transmit enable in C0 state, 0:Disabled, 1:Enabled
UINT32 | PinSelection: 1
GPIO Pin assignment selection, 0: default, 1: secondary.

Detailed Description

This structure configures PCH memory throttling thermal sensor GPIO PIN settings.

Definition at line 103 of file ThermalConfig.h.

Member Data Documentation

◆ PmsyncEnable

UINT32 TS_GPIO_PIN_SETTING::PmsyncEnable

GPIO PM_SYNC enable, 0:Diabled, 1:Enabled When enabled, RC will overrides the selected GPIO native mode.

For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.

Definition at line 111 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TS_GPIO_PIN_SETTING Member List

This is the complete list of members for TS_GPIO_PIN_SETTING, including all inherited members.

C0TransmitEnable | TS_GPIO_PIN_SETTING
PinSelection | TS_GPIO_PIN_SETTING
PmsyncEnable | TS_GPIO_PIN_SETTING
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TSN_CONFIG Struct Reference

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TSN_CONFIG Struct Reference

The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN) More...

#include <TsnConfig.h>

Collaboration diagram for TSN_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | Enable
Determines if enable PCH internal TSN, 0: Disable; 1: Enable.
UINT8 | TsnLinkSpeed
Refer to "TSN_LINK_SPEED_OPTIONS". Default is TSN_LINK_SPEED_2_5G_34MHZ
UINT8 | MultiVcEnable
Enable Multi-Vc via Tc to DMA mapping. Deafult is 0:disable
UINT8 | Rsvd0
Reserved bytes, align to multiple 4.
UINT32 | TsnMacAddressHigh
MAC Address High bits. Only two lower bytes are used.
UINT32 | TsnMacAddressLow
MAC Address Low bits.

Detailed Description

The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)

Revision 1:

  • Initial version. Revision 2:
  • Added MultiVcEnable

Definition at line 51 of file TsnConfig.h.

The documentation for this struct was generated from the following file:
  • TsnConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

TSN_CONFIG Member List

This is the complete list of members for TSN_CONFIG, including all inherited members.

Enable | TSN_CONFIG
Header | TSN_CONFIG
MultiVcEnable | TSN_CONFIG
Rsvd0 | TSN_CONFIG
TsnLinkSpeed | TSN_CONFIG
TsnMacAddressHigh | TSN_CONFIG
TsnMacAddressLow | TSN_CONFIG
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: UART_PIN_MUX Struct Reference

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UART_PIN_MUX Struct Reference

UART signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Rx
RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*.
UINT32 | Tx
TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*.
UINT32 | Rts
RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*.
UINT32 | Cts
CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*.

Detailed Description

UART signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h for supported settings on a given platform

Definition at line 164 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

UART_PIN_MUX Member List

This is the complete list of members for UART_PIN_MUX, including all inherited members.

Cts | UART_PIN_MUX
Rts | UART_PIN_MUX
Rx | UART_PIN_MUX
Tx | UART_PIN_MUX
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: USB2_PHY_CONFIG Struct Reference

Public Attributes | List of all members
USB2_PHY_CONFIG Struct Reference

This structure holds info on how to tune electrical parameters of USB2 ports based on board layout. More...

#include <Usb2PhyConfig.h>

Collaboration diagram for USB2_PHY_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
USB2_PHY_PARAMETERS Port [MAX_USB2_PORTS]
This structure configures per USB2 port physical settings. More...

Detailed Description

This structure holds info on how to tune electrical parameters of USB2 ports based on board layout.

Revision 1:

  • Initial version.

Definition at line 95 of file Usb2PhyConfig.h.

Member Data Documentation

◆ Port

USB2_PHY_PARAMETERS USB2_PHY_CONFIG::Port[MAX_USB2_PORTS]

This structure configures per USB2 port physical settings.

It allows to setup the port location and port length, and configures the port strength accordingly. Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating through Usb2PhySusPgEnable on PCH-LP

Definition at line 103 of file Usb2PhyConfig.h.

The documentation for this struct was generated from the following file:
  • Usb2PhyConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

USB2_PHY_CONFIG Member List

This is the complete list of members for USB2_PHY_CONFIG, including all inherited members.

Header | USB2_PHY_CONFIG
Port | USB2_PHY_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: USB2_PHY_PARAMETERS Struct Reference

Public Attributes | List of all members
USB2_PHY_PARAMETERS Struct Reference

This structure configures per USB2 AFE settings. More...

#include <Usb2PhyConfig.h>

Public Attributes

UINT8 | Petxiset
Per Port HS Preemphasis Bias (PERPORTPETXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28.15mV 100b - 28.15mV 101b - 39.35mV 110b - 45mV 111b - 56.3mV.
UINT8 | Txiset
Per Port HS Transmitter Bias (PERPORTTXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28.15mV 100b - 28.15mV 101b - 39.35mV 110b - 45mV 111b - 56.3mV.
UINT8 | Predeemp
Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) 00b - Emphasis OFF 01b - De-emphasis ON 10b - Pre-emphasis ON 11b - Pre-emphasis & De-emphasis ON.
UINT8 | Pehalfbit
Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) 1b - half-bit pre-emphasis 0b - full-bit pre-emphasis.

Detailed Description

This structure configures per USB2 AFE settings.

It allows to setup the port electrical parameters.

Definition at line 49 of file Usb2PhyConfig.h.

The documentation for this struct was generated from the following file:
  • Usb2PhyConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

USB2_PHY_PARAMETERS Member List

This is the complete list of members for USB2_PHY_PARAMETERS, including all inherited members.

Pehalfbit | USB2_PHY_PARAMETERS
Petxiset | USB2_PHY_PARAMETERS
Predeemp | USB2_PHY_PARAMETERS
Txiset | USB2_PHY_PARAMETERS
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: USB2_PORT_CONFIG Struct Reference

Public Attributes | List of all members
USB2_PORT_CONFIG Struct Reference

This structure configures per USB2.0 port settings like enabling and overcurrent protection. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | OverCurrentPin: 8
These members describe the specific over current pin number of USB 2.0 Port N. More...
UINT32 | Enable: 1
0: Disable; 1: Enable.
UINT32 | PortResetMessageEnable: 1
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
UINT32 | RsvdBits0: 22
Reserved bits.

Detailed Description

This structure configures per USB2.0 port settings like enabling and overcurrent protection.

Definition at line 54 of file UsbConfig.h.

Member Data Documentation

◆ OverCurrentPin

UINT32 USB2_PORT_CONFIG::OverCurrentPin

These members describe the specific over current pin number of USB 2.0 Port N.

It is SW's responsibility to ensure that a given port's bit map is set only for one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.

Definition at line 60 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

USB2_PORT_CONFIG Member List

This is the complete list of members for USB2_PORT_CONFIG, including all inherited members.

Enable | USB2_PORT_CONFIG
OverCurrentPin | USB2_PORT_CONFIG
PortResetMessageEnable | USB2_PORT_CONFIG
RsvdBits0 | USB2_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: USB3_HSIO_CONFIG Struct Reference

Public Attributes | List of all members
USB3_HSIO_CONFIG Struct Reference

Structure for holding USB3 tuning parameters. More...

#include <Usb3HsioConfig.h>

Collaboration diagram for USB3_HSIO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
HSIO_PARAMETERS Port [MAX_USB3_PORTS]
These members describe whether the USB3 Port N of PCH is enabled by platform modules.

Detailed Description

Structure for holding USB3 tuning parameters.

Revision 1:

  • Initial version. Revision 2:
  • USB 3.0 TX Output Unique Transition Bit Scale policies added

Definition at line 155 of file Usb3HsioConfig.h.

The documentation for this struct was generated from the following file:
  • Usb3HsioConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

USB3_HSIO_CONFIG Member List

This is the complete list of members for USB3_HSIO_CONFIG, including all inherited members.

Header | USB3_HSIO_CONFIG
Port | USB3_HSIO_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: USB3_PORT_CONFIG Struct Reference

Public Attributes | List of all members
USB3_PORT_CONFIG Struct Reference

This structure configures per USB3.x port settings like enabling and overcurrent protection. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | OverCurrentPin: 8
These members describe the specific over current pin number of USB 3.x Port N. More...
UINT32 | Enable: 1
0: Disable; 1: Enable.
UINT32 | RsvdBits0: 23
Reserved bits.

Detailed Description

This structure configures per USB3.x port settings like enabling and overcurrent protection.

Definition at line 69 of file UsbConfig.h.

Member Data Documentation

◆ OverCurrentPin

UINT32 USB3_PORT_CONFIG::OverCurrentPin

These members describe the specific over current pin number of USB 3.x Port N.

It is SW's responsibility to ensure that a given port's bit map is set only for one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.

Definition at line 75 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

USB3_PORT_CONFIG Member List

This is the complete list of members for USB3_PORT_CONFIG, including all inherited members.

Enable | USB3_PORT_CONFIG
OverCurrentPin | USB3_PORT_CONFIG
RsvdBits0 | USB3_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: USB_CONFIG Struct Reference

Public Attributes | List of all members
USB_CONFIG Struct Reference

This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field. More...

#include <UsbConfig.h>

Collaboration diagram for USB_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PdoProgramming: 1
This policy option when set will make BIOS program Port Disable Override register during PEI phase. More...
UINT32 | OverCurrentEnable: 1
This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI. More...
UINT32 | XhciOcLock: 1
(Test) If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. More...
UINT32 | LtrOverrideEnable: 1
Enabling this feature will allow for overriding LTR values for xHCI controller. More...
UINT32 | UaolEnable: 1
Enable/disable option for USB Audio Offload feture. More...
UINT32 | HsiiEnable: 1
Enable HS Interrupt IN Alarm 0: disable - Disable HSII 1: enable - Enable HSII
UINT32 | RsvdBits0: 26
Reserved bits.
UINT32 | LtrHighIdleTimeOverride
High Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
UINT32 | LtrMediumIdleTimeOverride
Medium Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
UINT32 | LtrLowIdleTimeOverride
Low Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
USB2_PORT_CONFIG | PortUsb20 [MAX_USB2_PORTS]
These members describe whether the USB2 Port N of PCH is enabled by platform modules.
USB3_PORT_CONFIG | PortUsb30 [MAX_USB3_PORTS]
These members describe whether the USB3 Port N of PCH is enabled by platform modules.
XDCI_CONFIG XdciConfig
This member describes whether or not the xDCI controller should be enabled.

Detailed Description

This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field.

The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring the schematic.

Revision 1:

  • Initial version. Revision 2:
  • Added UaolEnable to control USB Audio Offload Capability. Revision 3:
  • Add HsiiEnable enable option to control HSII feature

Definition at line 106 of file UsbConfig.h.

Member Data Documentation

◆ LtrOverrideEnable

UINT32 USB_CONFIG::LtrOverrideEnable

Enabling this feature will allow for overriding LTR values for xHCI controller.

Values used for programming will be taken from this config block and BIOS will disregard recommended ones. 0: disable - do not override recommended LTR values 1: enable - override recommended LTR values

Definition at line 141 of file UsbConfig.h.

◆ OverCurrentEnable

UINT32 USB_CONFIG::OverCurrentEnable

This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.

Disabling this feature will disable overcurrent detection functionality. Overcurrent Pin mapping data is contained in respective port structures (i.e. USB30_PORT_CONFIG) in OverCurrentPin field. By default this Overcurrent functionality should be enabled and disabled only for OBS debug usage. 1: Will program USB OC pin mapping in respective xHCI controller registers 0: Will clear OC pin mapping allow for OBS usage of OC pins

Definition at line 124 of file UsbConfig.h.

◆ PdoProgramming

UINT32 USB_CONFIG::PdoProgramming

This policy option when set will make BIOS program Port Disable Override register during PEI phase.

When disabled BIOS will not program the PDO during PEI phase and leave PDO register unlocked for later programming. If this is disabled, platform code MUST set it before booting into OS. 1: Enable 0: Disable

Definition at line 115 of file UsbConfig.h.

◆ UaolEnable

UINT32 USB_CONFIG::UaolEnable

Enable/disable option for USB Audio Offload feture.

Disabling this will disable UAOL capability in xHCI and UAOL ACPI definitions will be hidden. 0: disable UAOL 1: enable UAOL

Definition at line 148 of file UsbConfig.h.

◆ XhciOcLock

UINT32 USB_CONFIG::XhciOcLock

(Test) If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.

OverCurrent mapping data is taken from respective port data structure from OverCurrentPin field. If EnableOverCurrent policy is enabled this also should be enabled, otherwise xHCI won't consume OC mapping data. 1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping data 0: Do not program OCCFDONE bit making it possible to use OBS debug on OC pins.

Definition at line 134 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

USB_CONFIG Member List

This is the complete list of members for USB_CONFIG, including all inherited members.

Header | USB_CONFIG
HsiiEnable | USB_CONFIG
LtrHighIdleTimeOverride | USB_CONFIG
LtrLowIdleTimeOverride | USB_CONFIG
LtrMediumIdleTimeOverride | USB_CONFIG
LtrOverrideEnable | USB_CONFIG
OverCurrentEnable | USB_CONFIG
PdoProgramming | USB_CONFIG
PortUsb20 | USB_CONFIG
PortUsb30 | USB_CONFIG
RsvdBits0 | USB_CONFIG
UaolEnable | USB_CONFIG
XdciConfig | USB_CONFIG
XhciOcLock | USB_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VMD_PEI_CONFIG Struct Reference

Public Attributes | List of all members
VMD_PEI_CONFIG Struct Reference

This configuration block is to configure VMD related variables used in PostMem PEI. More...

#include <VmdPeiConfig.h>

Collaboration diagram for VMD_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | VmdEnable
Offset 28 This field used to enable VMD controller 1=Enable 0=Disable(default)
UINT8 | VmdPortBEnable
Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
UINT8 | VmdPortCEnable
Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
UINT8 | VmdPortDEnable
Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
UINT8 | VmdCfgBarSize
Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default) More...
UINT8 | VmdCfgBarAttr
Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, 2: VMD_64BIT_NONPREFETCH(Default)
UINT8 | VmdMemBarSize1
Offset 35 This is used to set the VMD Mem Bar1 size. 25 (32MB).
UINT8 | VmdMemBar1Attr
Offset 36 This is used to set VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default) 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH.
UINT8 | VmdMemBarSize2
Offset 37 This is used to set the VMD Mem Bar2 size. 20(1MB).
UINT8 | VmdMemBar2Attr
Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH.
UINT8 | VmdGlobalMapping
Offset 39 This field used to enable Global Mapping 1=Enable 0=Disable(default)
RP_BDF_DATA | VmdPortEnable [VMD_MAX_DEVICES]
Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable 0=Disable (default)
UINT32 | VmdCfgBarBase
This config block will be updated as per the EFI variable.
UINT32 | VmdMemBar1Base
Temp Address VMD CFG BAR Default is 0xA0000000
UINT32 | VmdMemBar2Base
Temp Address VMD CFG BAR Default is 0xA2000000

Detailed Description

This configuration block is to configure VMD related variables used in PostMem PEI.

If VMD Device is not supported, all policies can be ignored. Revision 1:

  • Initial version. Revision 2:
  • Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
  • Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details. (Added B/D/F fields along with Port Enable for up to max 31 devices). Revision 3: Added policy to get the Bar values from platform PCD. Revision 4: Added VmdGlobalMapping to map all the storage devices under VMD

Definition at line 67 of file VmdPeiConfig.h.

Member Data Documentation

◆ VmdCfgBarSize

UINT8 VMD_PEI_CONFIG::VmdCfgBarSize

Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)

Offset 33 This is used to set the VMD Config Bar Size. 25(32MB)

Definition at line 74 of file VmdPeiConfig.h.

The documentation for this struct was generated from the following file:
  • VmdPeiConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

VMD_PEI_CONFIG Member List

This is the complete list of members for VMD_PEI_CONFIG, including all inherited members.

Header | VMD_PEI_CONFIG
VmdCfgBarAttr | VMD_PEI_CONFIG
VmdCfgBarBase | VMD_PEI_CONFIG
VmdCfgBarSize | VMD_PEI_CONFIG
VmdEnable | VMD_PEI_CONFIG
VmdGlobalMapping | VMD_PEI_CONFIG
VmdMemBar1Attr | VMD_PEI_CONFIG
VmdMemBar1Base | VMD_PEI_CONFIG
VmdMemBar2Attr | VMD_PEI_CONFIG
VmdMemBar2Base | VMD_PEI_CONFIG
VmdMemBarSize1 | VMD_PEI_CONFIG
VmdMemBarSize2 | VMD_PEI_CONFIG
VmdPortBEnable | VMD_PEI_CONFIG
VmdPortCEnable | VMD_PEI_CONFIG
VmdPortDEnable | VMD_PEI_CONFIG
VmdPortEnable | VMD_PEI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VTD_CONFIG Struct Reference

Public Attributes | List of all members
VTD_CONFIG Struct Reference

The data elements should be initialized by a Platform Module. More...

#include <VtdConfig.h>

Collaboration diagram for VTD_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | VtdDisable
Offset 28: VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec. More...
UINT8 | X2ApicOptOut
Offset 29: This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and 0=Disable/Clear
UINT8 | DmaControlGuarantee
Offset 30: This field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1=Enable/Set and 0=Disable/Clear
UINT8 | VtdIgdEnable
Offset 31: This field is used to enable the VtdIgdEnable Policy. 1=Enable/Set and 0=Disable/Clear
UINT8 | VtdIpuEnable
Offset 32: This field is used to enable the VtdIpuEnable Policy. 1=Enable/Set and 0=Disable/Clear
UINT8 | VtdIopEnable
Offset 33: This field is used to enable the VtdIopEnable Policy. 1=Enable/Set and 0=Disable/Clear
UINT8 | PreBootDmaMask
Deprecate. More...
UINT32 | BaseAddress [VTD_ENGINE_NUMBER]
Offset 36: This field is used to describe the base addresses for VT-d function.
UINT32 | DmaBufferSize
Offset 48: Protect Memory Region (PMR) DMA buffer size.
UINT32 | Reserved
Offset 52: Reserved.
EFI_PHYSICAL_ADDRESS EnableDmaBuffer
Offset 56: Pointer to EnableDmaBuffer function. More...

Detailed Description

The data elements should be initialized by a Platform Module.

The data structure is for VT-d driver initialization
Revision 1:

  • Initial version. Revision 2:
  • Added field EnableDmaBuffer.

Definition at line 72 of file VtdConfig.h.

Member Data Documentation

◆ EnableDmaBuffer

EFI_PHYSICAL_ADDRESS VTD_CONFIG::EnableDmaBuffer

Offset 56: Pointer to EnableDmaBuffer function.

Platform code provides an interface to enable DMA buffer. VTD_ENABLE_DMA_BUFFER is a prototype for that interface.

Definition at line 93 of file VtdConfig.h.

◆ PreBootDmaMask

UINT8 VTD_CONFIG::PreBootDmaMask

Deprecate.

Offset 35: Convey PcdVTdPolicyPropertyMask value from EDK2 IntelSiliconPkg

Definition at line 89 of file VtdConfig.h.

◆ VtdDisable

UINT8 VTD_CONFIG::VtdDisable

Offset 28: VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.

This policy is for debug purpose only. If VT-D is not supported, all other policies in this config block will be ignored. 0 = To use Vt-d; 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.

Definition at line 82 of file VtdConfig.h.

The documentation for this struct was generated from the following file:
  • VtdConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

VTD_CONFIG Member List

This is the complete list of members for VTD_CONFIG, including all inherited members.

BaseAddress | VTD_CONFIG
DmaBufferSize | VTD_CONFIG
DmaControlGuarantee | VTD_CONFIG
EnableDmaBuffer | VTD_CONFIG
Header | VTD_CONFIG
PreBootDmaMask | VTD_CONFIG
Reserved | VTD_CONFIG
VtdDisable | VTD_CONFIG
VtdIgdEnable | VTD_CONFIG
VtdIopEnable | VTD_CONFIG
VtdIpuEnable | VTD_CONFIG
X2ApicOptOut | VTD_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VTD_DXE_CONFIG Struct Reference

Public Attributes | List of all members
VTD_DXE_CONFIG Struct Reference

The data structure is for VT-d driver initialization in DXE
Revision 1: More...

#include <VtdConfig.h>

Collaboration diagram for VTD_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.

Detailed Description

The data structure is for VT-d driver initialization in DXE
Revision 1:

  • Initial version. Revision 2:
  • Added TE Disable for Igd. Revision 3:
  • Removed TE Disable for Igd.

Definition at line 106 of file VtdConfig.h.

The documentation for this struct was generated from the following file:
  • VtdConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

VTD_DXE_CONFIG Member List

This is the complete list of members for VTD_DXE_CONFIG, including all inherited members.

Header VTD_DXE_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: XDCI_CONFIG Struct Reference

Public Attributes | List of all members
XDCI_CONFIG Struct Reference

The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | Enable: 1
This member describes whether or not the xDCI controller should be enabled. More...
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller.

Definition at line 84 of file UsbConfig.h.

Member Data Documentation

◆ Enable

UINT32 XDCI_CONFIG::Enable

This member describes whether or not the xDCI controller should be enabled.

0: Disable; 1: Enable.

Definition at line 89 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

XDCI_CONFIG Member List

This is the complete list of members for XDCI_CONFIG, including all inherited members.

Enable | XDCI_CONFIG
RsvdBits0 | XDCI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Index

Class Index
_ | a | b | c | d | e | f | g | h | i | m | o | p | r | s | t | u | v | x
_
CPU_TXT_PREMEM_CONFIG HDA_LINK_SNDW PCH_IOAPIC_CONFIG SI_CONFIG
d
HDA_LINK_SSP PCH_LOCK_DOWN_CONFIG SI_PREMEM_CONFIG
_CONFIG_BLOCK HDA_VERB_TABLE_HEADER PCH_MEMORY_THROTTLING SMBIOS_STRUCTURE
_CONFIG_BLOCK_HEADER DDI_CONFIGURATION HDAUDIO_CONFIG PCH_P2SB_CONFIG SPD_DATA_BUFFER
_CONFIG_BLOCK_TABLE_STRUCT DMI_HW_WIDTH_CONTROL HDAUDIO_DXE_CONFIG PCH_PCIE_CLOCK SPD_OFFSET_TABLE
_EFI_MM_RESERVED_MMRAM_REGION
e
HDAUDIO_PREMEM_CONFIG PCH_PCIE_CONFIG SPI_PIN_MUX
_EFI_PEI_MP_SERVICES_PPI HSIO_PARAMETERS PCH_PCIE_ROOT_PORT_CONFIG SVID_SID_VALUE
_ITBT_GENERIC_CONFIG EFI_HOB_CPU HYBRID_GRAPHICS_CONFIG PCH_PCIE_RP_PREMEM_CONFIG
t
_ITBT_ROOTPORT_CONFIG EFI_HOB_FIRMWARE_VOLUME HYBRID_STORAGE_CONFIG PCH_PM_CONFIG
_LIST_ENTRY EFI_HOB_FIRMWARE_VOLUME2
i
PCH_SATA_PORT_CONFIG TCSS_DEVEN_PEI_PREMEM_CONFIG
_PEI_ITBT_CONFIG EFI_HOB_FIRMWARE_VOLUME3 PCH_SMBUS_PREMEM_CONFIG TCSS_IOM_ORI_OVERRIDE
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI EFI_HOB_GENERIC_HEADER I2C_PIN_MUX PCH_TRACE_HUB_PREMEM_CONFIG TCSS_IOM_PEI_CONFIG
_PEI_SI_DEFAULT_POLICY_INIT_PPI EFI_HOB_GUID_TYPE IEH_CONFIG PCH_WAKE_CONFIG TCSS_MISC_PEI_CONFIG
_PPM_CUSTOM_CTDP_TABLE EFI_HOB_HANDOFF_INFO_TABLE IOM_AUX_ORI_PAD_CONFIG PCH_WDT_PREMEM_CONFIG TCSS_MISC_PEI_PREMEM_CONFIG
_SI_POLICY_STRUCT EFI_HOB_MEMORY_ALLOCATION IOM_INTERFACE_CONFIG PCIE_COMMON_CONFIG TCSS_PCIE_PEI_POLICY
_SI_PREMEM_POLICY_STRUCT EFI_HOB_MEMORY_ALLOCATION_BSP_STORE IPU_PREMEM_CONFIG PCIE_DEVICE_OVERRIDE TCSS_PCIE_PORT_POLICY
a
EFI_HOB_MEMORY_ALLOCATION_HEADER IPv4_ADDRESS PCIE_EQ_PARAM TCSS_PEI_CONFIG
EFI_HOB_MEMORY_ALLOCATION_MODULE IPv6_ADDRESS PCIE_IMR_CONFIG TCSS_PEI_PREMEM_CONFIG
ADR_CONFIG EFI_HOB_MEMORY_ALLOCATION_STACK ISH_CONFIG PCIE_LINK_EQ_PLATFORM_SETTINGS TCSS_USBTC_PEI_PERMEM_CONFIG
ADR_SOURCE_ENABLE EFI_HOB_MEMORY_POOL ISH_GP PCIE_PEI_PREMEM_CONFIG TELEMETRY_PEI_CONFIG
AMT_DXE_CONFIG EFI_HOB_RESOURCE_DESCRIPTOR ISH_GPIO_CONFIG PCIE_PREMEM_CONFIG TELEMETRY_PEI_PREMEM_CONFIG
AMT_PEI_CONFIG EFI_HOB_UEFI_CAPSULE ISH_I2C PCIE_RP_DXE_CONFIG THC_CONFIG
b
EFI_IP_ADDRESS ISH_I2C_PIN_CONFIG PMC_GLOBAL_RESET_MASK THC_HID_OVER_SPI
EFI_MAC_ADDRESS ISH_I3C_CONFIG PMC_INTERFACE_CONFIG THC_PORT
BCLK_CONFIG EFI_MMRAM_DESCRIPTOR ISH_PREMEM_CONFIG PMC_LPM_S0IX_SUB_STATE_EN THERMAL_CONFIG
BIOS_GUARD_CONFIG EFI_PEI_HOB_POINTERS ISH_SPI PPM_CUSTOM_RATIO_TABLE THERMAL_THROTTLE_LEVELS
c
EFI_TIME ISH_SPI_PIN_CONFIG PSF_CONFIG TRACE_HUB_CONFIG
f
ISH_UART
r
TS_GPIO_PIN_SETTING
CNVI_CONFIG ISH_UART_PIN_CONFIG TSN_CONFIG
CNVI_PIN_MUX FIRMWARE_VERSION
m
RST_CONFIG
u
CNVI_PREMEM_CONFIG FIRMWARE_VERSION_INFO RST_HARDWARE_REMAPPED_STORAGE_CONFIG
CPU_CONFIG FIRMWARE_VERSION_INFO_HOB ME_PEI_CONFIG RTC_CONFIG UART_PIN_MUX
CPU_CONFIG_LIB_PREMEM_CONFIG FIVR_EXT_RAIL_CONFIG ME_PEI_PREMEM_CONFIG
s
USB2_PHY_CONFIG
CPU_DMI_EQ_PARAM FIVR_VCCIN_AUX_CONFIG MEMORY_CONFIG_NO_CRC USB2_PHY_PARAMETERS
CPU_DMI_PREMEM_CONFIG FSP_ERROR_INFO_HOB MEMORY_CONFIGURATION SA_ADDRESS_DECODE USB2_PORT_CONFIG
CPU_PCIE_CONFIG FSPM_ARCH_CONFIG_PPI
o
SA_FUNCTION_CALLS USB3_HSIO_CONFIG
CPU_PCIE_EQ_LANE_PARAM
g
SA_MEMORY_DQDQS_MAPPING USB3_PORT_CONFIG
CPU_PCIE_GPIO_INFO OVERCLOCKING_PREMEM_CONFIG SA_MEMORY_FUNCTIONS USB_CONFIG
CPU_PCIE_ROOT_PORT_CONFIG GBE_CONFIG
p
SA_MEMORY_RCOMP
v
CPU_PCIE_RP_PREMEM_CONFIG GNA_CONFIG SA_MISC_PEI_CONFIG
CPU_PCIE_RTD3_GPIO GPIO_CONFIG PCH_DCI_PREMEM_CONFIG SA_MISC_PEI_PREMEM_CONFIG VMD_PEI_CONFIG
CPU_POWER_MGMT_BASIC_CONFIG GRAPHICS_DXE_CONFIG PCH_DEVICE_INTERRUPT_CONFIG SA_XDCI_IRQ_INT_CONFIG VTD_CONFIG
CPU_POWER_MGMT_CUSTOM_CONFIG GRAPHICS_PEI_CONFIG PCH_DMI_CONFIG SATA_CONFIG VTD_DXE_CONFIG
CPU_POWER_MGMT_PSYS_CONFIG GRAPHICS_PEI_PREMEM_CONFIG PCH_DMI_EQ_PARAM SATA_THERMAL_THROTTLING
x
CPU_POWER_MGMT_TEST_CONFIG GUID PCH_ESPI_CONFIG SERIAL_IO_CONFIG
CPU_POWER_MGMT_VR_CONFIG
h
PCH_FIVR_CONFIG SERIAL_IO_I2C_CONFIG XDCI_CONFIG
CPU_SECURITY_PREMEM_CONFIG PCH_GENERAL_CONFIG SERIAL_IO_SPI_CONFIG
CPU_TEST_CONFIG HDA_LINK_DMIC PCH_GENERAL_PREMEM_CONFIG SERIAL_IO_UART_ATTRIBUTES
CPU_TRACE_HUB_PREMEM_CONFIG HDA_LINK_HDA PCH_INTERRUPT_CONFIG SERIAL_IO_UART_CONFIG
_ | a | b | c | d | e | f | g | h | i | m | o | p | r | s | t | u | v | x
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • AcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • AcousticNoiseMitigation : CPU_POWER_MGMT_VR_CONFIG
  • AcpiL6dPmeHandling : PCH_GENERAL_CONFIG
  • AcpiReservedMemoryBase : SA_MISC_PEI_PREMEM_CONFIG
  • AcpiReservedMemorySize : SA_MISC_PEI_PREMEM_CONFIG
  • AcsEnabled : TCSS_PCIE_PORT_POLICY
  • AcSplitLock : CPU_CONFIG
  • Active : CPU_PCIE_GPIO_INFO
  • ActiveCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveCoreCount1 : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveLtr : THC_PORT
  • ActiveSmallCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveSocNorthAtomCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • AdrEn : ADR_CONFIG
  • AdrHostPartitionReset : ADR_CONFIG
  • AdrMultiplier1Val : ADR_CONFIG
  • AdrMultiplier2Val : ADR_CONFIG
  • AdrPlatAckEn : ADR_CONFIG
  • AdrSrcOverride : ADR_CONFIG
  • AdrSrcSel : ADR_CONFIG
  • AdrTimer1Val : ADR_CONFIG
  • AdrTimer2Val : ADR_CONFIG
  • AdrTimerEn : ADR_CONFIG
  • AdvancedErrorReporting : TCSS_PCIE_PORT_POLICY
  • AesEnable : CPU_CONFIG
  • AetEnabled : TRACE_HUB_CONFIG
  • ALIASCHK : MEMORY_CONFIGURATION
  • AllocDescriptor : EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_STACK
  • AllowOppRefBelowWriteThrehold : MEMORY_CONFIGURATION
  • AlsEnable : GRAPHICS_DXE_CONFIG
  • AmtbxHotkeyPressed : AMT_DXE_CONFIG
  • AmtbxSelectionScreen : AMT_DXE_CONFIG
  • AmtEnabled : AMT_PEI_CONFIG
  • AmtKvmEnabled : AMT_PEI_CONFIG
  • AmtReportError : AMT_DXE_CONFIG
  • AmtSolEnabled : AMT_PEI_CONFIG
  • ApertureSize : GRAPHICS_PEI_PREMEM_CONFIG
  • ApplyConfigTdp : CPU_POWER_MGMT_BASIC_CONFIG
  • ApStartupBase : CPU_TXT_PREMEM_CONFIG
  • ArpEnable : PCH_SMBUS_PREMEM_CONFIG
  • Aspm : TCSS_PCIE_PORT_POLICY
  • Assignment : THC_PORT
  • AtomClusterRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2MaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • AtomPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomTurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • AtomTurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • Attributes : _CONFIG_BLOCK_HEADER , SERIAL_IO_UART_CONFIG
  • AudioLinkDmic : HDAUDIO_PREMEM_CONFIG
  • AudioLinkHda : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSndw : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSsp : HDAUDIO_PREMEM_CONFIG
  • AuthenticationStatus : EFI_HOB_FIRMWARE_VOLUME3
  • AutoFlow : SERIAL_IO_UART_ATTRIBUTES
  • AutoSelfRefreshSupport : MEMORY_CONFIGURATION
  • AuxOri : TCSS_IOM_ORI_OVERRIDE
  • AvailableSize : _CONFIG_BLOCK_TABLE_STRUCT
  • Avx2RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx2VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • Avx3Disable : CPU_CONFIG
  • Avx3RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx512VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • AvxDisable : CPU_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- b -

  • BacklightControlSupport : GRAPHICS_DXE_CONFIG
  • Bank : SA_ADDRESS_DECODE
  • BankGroup : SA_ADDRESS_DECODE
  • BaseAddress : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_UEFI_CAPSULE , VTD_CONFIG
  • BaseClassCode : PCIE_DEVICE_OVERRIDE
  • BaudRate : SERIAL_IO_UART_ATTRIBUTES
  • BclkAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • BClkFrequency : MEMORY_CONFIGURATION
  • BclkRfiFreq : MEMORY_CONFIGURATION
  • BclkSource : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BCLM : GRAPHICS_DXE_CONFIG
  • BdatEnable : SA_MISC_PEI_PREMEM_CONFIG
  • BdatTestType : SA_MISC_PEI_PREMEM_CONFIG
  • BgpdtHash : BIOS_GUARD_CONFIG
  • Bifurcation : PCH_PCIE_RP_PREMEM_CONFIG
  • BiosAcmBase : CPU_TXT_PREMEM_CONFIG
  • BiosAcmSize : CPU_TXT_PREMEM_CONFIG
  • BiosGuard : CPU_SECURITY_PREMEM_CONFIG
  • BiosGuardAttr : BIOS_GUARD_CONFIG
  • BiosGuardModulePtr : BIOS_GUARD_CONFIG
  • BiosGuardToolsInterface : CPU_SECURITY_PREMEM_CONFIG
  • BiosInterface : PCH_LOCK_DOWN_CONFIG
  • BiosInterfaceLock : RTC_CONFIG
  • BiosLock : PCH_LOCK_DOWN_CONFIG
  • BiosSize : CPU_SECURITY_PREMEM_CONFIG
  • BiProcHot : CPU_POWER_MGMT_TEST_CONFIG
  • BistOnReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BltBufferAddress : GRAPHICS_PEI_CONFIG
  • BltBufferSize : GRAPHICS_PEI_CONFIG
  • BmeMasterSlaveEnabled : PCH_ESPI_CONFIG
  • BootFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG
  • BootMode : EFI_HOB_HANDOFF_INFO_TABLE , SPD_OFFSET_TABLE
  • BtAudioOffload : CNVI_CONFIG
  • BtCore : CNVI_CONFIG
  • BypassFivrConfig : PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- c -

  • C0TransmitEnable : TS_GPIO_PIN_SETTING
  • C10DynamicThresholdAdjustment : PCH_PM_CONFIG
  • C1AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C1e : CPU_POWER_MGMT_TEST_CONFIG
  • C1UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • CallerId : FSP_ERROR_INFO_HOB
  • Cas : SA_ADDRESS_DECODE
  • CdClock : GRAPHICS_PEI_CONFIG
  • CdrRelock : CPU_PCIE_RP_PREMEM_CONFIG
  • CdynmaxClampEnable : GRAPHICS_PEI_CONFIG
  • Channel : SA_ADDRESS_DECODE
  • CheckPoint : SA_FUNCTION_CALLS
  • ChHashEnable : MEMORY_CONFIGURATION
  • ChHashInterleaveBit : MEMORY_CONFIGURATION
  • ChHashMask : MEMORY_CONFIGURATION
  • ChHashOverride : MEMORY_CONFIGURATION
  • CiraRequest : AMT_DXE_CONFIG
  • CiraTimeout : AMT_DXE_CONFIG
  • CleanMemory : MEMORY_CONFIG_NO_CRC
  • Clk : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • Clkreq : CNVI_PIN_MUX
  • ClkReq : PCH_PCIE_CLOCK
  • ClkReqMsgEnable : CPU_PCIE_RP_PREMEM_CONFIG
  • ClkReqMsgEnableRp : CPU_PCIE_RP_PREMEM_CONFIG
  • CLKTCO : MEMORY_CONFIGURATION
  • ClockGating : PCH_DMI_CONFIG
  • Cm : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CMDDRUD : MEMORY_CONFIGURATION
  • CMDDSEQ : MEMORY_CONFIGURATION
  • CmdMirror : MEMORY_CONFIGURATION
  • CmdRanksTerminated : MEMORY_CONFIGURATION
  • CMDSR : MEMORY_CONFIGURATION
  • CMDVC : MEMORY_CONFIGURATION
  • CodecSxWakeCapability : HDAUDIO_CONFIG
  • ComplianceTestMode : PCIE_COMMON_CONFIG
  • ComponentNameIndex : FIRMWARE_VERSION_INFO
  • ComputeDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ComputeDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ConfigTdpBios : CPU_POWER_MGMT_CUSTOM_CONFIG
  • ConfigTdpLevel : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_TEST_CONFIG
  • ConfigTdpLock : CPU_POWER_MGMT_CUSTOM_CONFIG
  • Controller : ISH_I3C_CONFIG , SA_ADDRESS_DECODE
  • CopyMem : SA_FUNCTION_CALLS
  • CoreMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • CorePllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreRatioExtensionMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfConfigScope : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • CorrectableErrorReport : TCSS_PCIE_PORT_POLICY
  • Count : FIRMWARE_VERSION_INFO_HOB
  • Cp : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CpuAttachedStorage : RST_CONFIG
  • CpuBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkPllOn : BCLK_CONFIG
  • CpuC10GatePinEnable : PCH_PM_CONFIG
  • CpuCrashLogDevice : TELEMETRY_PEI_PREMEM_CONFIG
  • CpuCrashLogEnable : TELEMETRY_PEI_CONFIG
  • Cpuid : PPM_CUSTOM_RATIO_TABLE
  • CpuMailboxRead : SA_FUNCTION_CALLS
  • CpuMailboxWrite : SA_FUNCTION_CALLS
  • CpuPcie0Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie1Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie2Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie3Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuRatio : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CpuReplacementTimeout : AMT_DXE_CONFIG
  • CpuStart : EFI_MMRAM_DESCRIPTOR
  • CrashLogEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CrashLogGprs : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Crid : PCH_GENERAL_CONFIG
  • CridEnable : SA_MISC_PEI_PREMEM_CONFIG
  • Cs : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • CseDataResilience : ME_PEI_CONFIG
  • CsEnable : ISH_SPI , SERIAL_IO_SPI_CONFIG
  • CsiSpeed : IPU_PREMEM_CONFIG
  • CsmFlag : SI_CONFIG
  • CsMode : SERIAL_IO_SPI_CONFIG
  • CsPolarity : SERIAL_IO_SPI_CONFIG
  • CsState : SERIAL_IO_SPI_CONFIG
  • CstateLatencyControl0Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CStatePreWake : CPU_POWER_MGMT_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : CPU_POWER_MGMT_TEST_CONFIG
  • CtrlRampTmr : FIVR_EXT_RAIL_CONFIG
  • Cts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • CustomConfigTdpTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomizedSsid : SI_CONFIG
  • CustomizedSvid : SI_CONFIG
  • CustomPowerLimit1 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit1Time : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit2 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CustomRatioTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomTurboActivationRatio : _PPM_CUSTOM_CTDP_TABLE
  • CwbEnable : PCH_DMI_CONFIG
  • Cx : CPU_POWER_MGMT_TEST_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- d -

  • D3ColdEnable : IOM_INTERFACE_CONFIG
  • D3HotEnable : IOM_INTERFACE_CONFIG
  • DataBits : SERIAL_IO_UART_ATTRIBUTES
  • DataDwords : HDA_VERB_TABLE_HEADER
  • DBG2 : SERIAL_IO_UART_CONFIG
  • DCC : MEMORY_CONFIGURATION
  • DciClkEnable : PCH_DCI_PREMEM_CONFIG
  • DciDbcMode : PCH_DCI_PREMEM_CONFIG
  • DciEn : PCH_DCI_PREMEM_CONFIG
  • DciModphyPg : PCH_DCI_PREMEM_CONFIG
  • DciUsb3TypecUfpDbg : PCH_DCI_PREMEM_CONFIG
  • DcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • DdiConfiguration : GRAPHICS_PEI_PREMEM_CONFIG
  • DdiPort1Ddc : DDI_CONFIGURATION
  • DdiPort1Hpd : DDI_CONFIGURATION
  • DdiPort2Ddc : DDI_CONFIGURATION
  • DdiPort2Hpd : DDI_CONFIGURATION
  • DdiPort3Ddc : DDI_CONFIGURATION
  • DdiPort3Hpd : DDI_CONFIGURATION
  • DdiPort4Ddc : DDI_CONFIGURATION
  • DdiPort4Hpd : DDI_CONFIGURATION
  • DdiPortADdc : DDI_CONFIGURATION
  • DdiPortAHpd : DDI_CONFIGURATION
  • DdiPortBConfig : DDI_CONFIGURATION
  • DdiPortBDdc : DDI_CONFIGURATION
  • DdiPortBHpd : DDI_CONFIGURATION
  • DdiPortCDdc : DDI_CONFIGURATION
  • DdiPortCHpd : DDI_CONFIGURATION
  • Ddr4DdpSharedClock : MEMORY_CONFIGURATION
  • Ddr4OneDpc : MEMORY_CONFIGURATION
  • DdrFreqLimit : MEMORY_CONFIGURATION
  • DdrRfim : CNVI_PREMEM_CONFIG
  • DebugHook : SA_FUNCTION_CALLS
  • DebugInterfaceEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugInterfaceLockEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugPrint : SA_FUNCTION_CALLS
  • DebugValue : MEMORY_CONFIGURATION
  • DefaultCsOutput : SERIAL_IO_SPI_CONFIG
  • DekelSquelchWa : CPU_PCIE_RP_PREMEM_CONFIG
  • DeltaT12PowerCycleDelay : GRAPHICS_PEI_PREMEM_CONFIG
  • DevEnConfig : TCSS_PEI_PREMEM_CONFIG
  • Device : PCH_DEVICE_INTERRUPT_CONFIG
  • DeviceId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • DeviceResetDelay : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • DevIntConfig : PCH_INTERRUPT_CONFIG
  • DevSlp : PCH_SATA_PORT_CONFIG
  • DevSlpResetConfig : PCH_SATA_PORT_CONFIG
  • DfdRestoreEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • DidInitStat : ME_PEI_PREMEM_CONFIG
  • Dimm : SA_ADDRESS_DECODE
  • DIMMDFE : MEMORY_CONFIGURATION
  • DIMMODTCA : MEMORY_CONFIGURATION
  • DIMMODTT : MEMORY_CONFIGURATION
  • DIMMRONT : MEMORY_CONFIGURATION
  • Direction : GPIO_CONFIG
  • DisableAndLock : PCH_WDT_PREMEM_CONFIG
  • DisableChannel : MEMORY_CONFIGURATION
  • DisableCpuReplacedPolling : ME_PEI_PREMEM_CONFIG
  • DisableD0I3SettingForHeci : ME_PEI_CONFIG
  • DisableDsxAcPresentPulldown : PCH_PM_CONFIG
  • DisableEnergyReport : PCH_PM_CONFIG
  • DisableMessageCheck : ME_PEI_PREMEM_CONFIG
  • DisableNativePowerButton : PCH_PM_CONFIG
  • DisablePerAtomMask : OVERCLOCKING_PREMEM_CONFIG
  • DisablePerCoreMask : OVERCLOCKING_PREMEM_CONFIG
  • DisableProcHotOut : CPU_POWER_MGMT_TEST_CONFIG
  • DisableTurboGt : GRAPHICS_PEI_CONFIG
  • DisableVrThermalAlert : CPU_POWER_MGMT_TEST_CONFIG
  • DismSize : GRAPHICS_PEI_PREMEM_CONFIG
  • DisPgCloseIdleTimeout : MEMORY_CONFIGURATION
  • DisplayAudioLink : GRAPHICS_PEI_PREMEM_CONFIG
  • DitoVal : PCH_SATA_PORT_CONFIG
  • DivU64x64 : SA_FUNCTION_CALLS
  • DlvrBypassModeEnable : OVERCLOCKING_PREMEM_CONFIG
  • DlvrRfiEnable : CPU_POWER_MGMT_VR_CONFIG
  • DlvrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • DlvrSpreadSpectrumPercentage : CPU_POWER_MGMT_VR_CONFIG
  • DmaBufferSize : VTD_CONFIG
  • DmaControlGuarantee : VTD_CONFIG
  • DmaEnable : SERIAL_IO_UART_CONFIG
  • DmiAspmCtrl : CPU_DMI_PREMEM_CONFIG , PCH_DMI_CONFIG
  • DmiAspmL1ExitLatency : CPU_DMI_PREMEM_CONFIG
  • DmicClockSelect : HDA_LINK_DMIC
  • DmiCdrRelock : CPU_DMI_PREMEM_CONFIG
  • DmiDeEmphasis : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3DsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3EndPointHint : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3EndPointPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3EqPh2Enable : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3EqPh3Method : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3ProgramStaticEq : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3RootPortPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RxCtlePeaking : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3UsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiHaAWC : THERMAL_CONFIG
  • DmiMaxLinkSpeed : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiNewFom : CPU_DMI_PREMEM_CONFIG
  • DmiPowerReduction : PCH_DMI_CONFIG
  • DmiTsawEn : DMI_HW_WIDTH_CONTROL
  • DmVal : PCH_SATA_PORT_CONFIG
  • DpcEnabled : TCSS_PCIE_PORT_POLICY
  • DqDqsMap : MEMORY_CONFIG_NO_CRC
  • DqMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DqPinsInterleaved : MEMORY_CONFIGURATION
  • DqsMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DRAMDCA : MEMORY_CONFIGURATION
  • DspEnable : HDAUDIO_PREMEM_CONFIG
  • DspFeatureMask : HDAUDIO_DXE_CONFIG
  • DspUaaCompliance : HDAUDIO_PREMEM_CONFIG
  • DualTauBoost : CPU_POWER_MGMT_BASIC_CONFIG
  • DynamicMemoryBoost : MEMORY_CONFIGURATION
  • DynamicPowerGating : PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- e -

  • EccDftEn : MEMORY_CONFIGURATION
  • EccErrInjAddress : MEMORY_CONFIGURATION
  • EccErrInjCount : MEMORY_CONFIGURATION
  • EccErrInjMask : MEMORY_CONFIGURATION
  • EcCmdLock : BIOS_GUARD_CONFIG
  • EcCmdProvisionEav : BIOS_GUARD_CONFIG
  • EccSupport : MEMORY_CONFIGURATION
  • ECT : MEMORY_CONFIGURATION
  • EfiEndOfHobList : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • EightCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Eist : CPU_POWER_MGMT_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • Enable : GBE_CONFIG , HDA_LINK_DMIC , HDA_LINK_HDA , HDA_LINK_SNDW , HDA_LINK_SSP , HDAUDIO_PREMEM_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_SPI , ISH_UART , PCH_MEMORY_THROTTLING , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SATA_CONFIG , TSN_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • Enable8254ClockGating : PCH_IOAPIC_CONFIG
  • Enable8254ClockGatingOnS3 : PCH_IOAPIC_CONFIG
  • EnableAllThermalFunctions : CPU_POWER_MGMT_TEST_CONFIG
  • EnableC6Dram : CPU_SECURITY_PREMEM_CONFIG
  • EnableDitoConfig : PCH_SATA_PORT_CONFIG
  • EnableDmaBuffer : VTD_CONFIG
  • EnabledStates : FIVR_EXT_RAIL_CONFIG
  • EnableEpbPeciOverride : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableFastMsrHwpReq : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoEppGrouping : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoPerCorePstate : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbm : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbmDriver : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableMinVoltageOverride : CPU_POWER_MGMT_VR_CONFIG
  • EnableMode : TRACE_HUB_CONFIG
  • EnablePerCorePState : CPU_POWER_MGMT_BASIC_CONFIG
  • EnablePort8xhDecode : PCIE_COMMON_CONFIG
  • EnablePwrDn : MEMORY_CONFIGURATION
  • EnablePwrDnLpddr : MEMORY_CONFIGURATION
  • EnableSgx : CPU_SECURITY_PREMEM_CONFIG
  • EnableTcssCovTypeA : TCSS_MISC_PEI_CONFIG
  • EnableVsysCritical : CPU_POWER_MGMT_VR_CONFIG
  • EnclosureSupport : SATA_CONFIG
  • EnCmdRate : MEMORY_CONFIGURATION
  • End : SPD_OFFSET_TABLE
  • EndOfPostMessage : ME_PEI_CONFIG
  • EndPointAspm : PCIE_DEVICE_OVERRIDE
  • EnergyEfficientPState : CPU_POWER_MGMT_TEST_CONFIG
  • EnergyEfficientTurbo : CPU_POWER_MGMT_TEST_CONFIG
  • EnforceEDebugMode : ME_PEI_CONFIG
  • EnhancedInterleave : MEMORY_CONFIGURATION
  • EntryPoint : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • EpgEnable : MEMORY_CONFIGURATION
  • EqPh23Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3LaneParam : CPU_PCIE_CONFIG
  • ERDMPRTC2D : MEMORY_CONFIGURATION
  • ERDTC2D : MEMORY_CONFIGURATION
  • ErrorType : FSP_ERROR_INFO_HOB
  • EsataSpeedLimit : SATA_CONFIG
  • EspiPmHAE : PCH_ESPI_CONFIG
  • Etvb : OVERCLOCKING_PREMEM_CONFIG
  • EWRTC2D : MEMORY_CONFIGURATION
  • ExitOnFailure : MEMORY_CONFIGURATION
  • ExpanderNo : CPU_PCIE_GPIO_INFO
  • ExtendedBankHashing : MEMORY_CONFIGURATION
  • External : PCH_SATA_PORT_CONFIG
  • ExtractedFv : EFI_HOB_FIRMWARE_VOLUME3
  • ExtSync : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG
  • ExtTemperatureSupport : MEMORY_CONFIGURATION
  • ExtV1p05Rail : PCH_FIVR_CONFIG
  • ExtVnnRail : PCH_FIVR_CONFIG
  • ExtVnnRailSx : PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- f -

  • FastPkgCRampDisable : CPU_POWER_MGMT_VR_CONFIG
  • FatalErrorReport : TCSS_PCIE_PORT_POLICY
  • FClkFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG
  • FiaProgramming : CPU_PCIE_CONFIG
  • FileName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FirstDimmBitMask : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FirstDimmBitMaskEcc : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FiveCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FivrDynPm : PCH_FIVR_CONFIG
  • FivrEfficiency : OVERCLOCKING_PREMEM_CONFIG
  • FivrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpectrumEnable : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpreadSpectrum : CPU_POWER_MGMT_VR_CONFIG
  • Flags : THC_HID_OVER_SPI
  • FllOcModeEn : OVERCLOCKING_PREMEM_CONFIG
  • FllOverclockMode : OVERCLOCKING_PREMEM_CONFIG
  • FomsCp : CPU_PCIE_ROOT_PORT_CONFIG
  • Force1Dpc : MEMORY_CONFIGURATION
  • ForceLtrOverride : PCIE_DEVICE_OVERRIDE , TCSS_PCIE_PORT_POLICY
  • ForceSingleRank : MEMORY_CONFIGURATION
  • ForceSingleSubchannel : MEMORY_CONFIGURATION
  • ForcMebxSyncUp : AMT_PEI_CONFIG
  • FourCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FreqLimitMixedConfig : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_2R2R : MEMORY_CONFIGURATION
  • Frequency : THC_HID_OVER_SPI
  • Function : PCH_DEVICE_INTERRUPT_CONFIG
  • FvName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FwProgress : AMT_PEI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- g -

  • GearRatio : MEMORY_CONFIGURATION
  • Gen3Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen3Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4EqPh3Method : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • GetCpuTime : SA_FUNCTION_CALLS
  • GetMemoryVdd : SA_FUNCTION_CALLS
  • GetPciDeviceAddress : SA_FUNCTION_CALLS
  • GetPcieDeviceAddress : SA_FUNCTION_CALLS
  • GetRandomNumber : SA_FUNCTION_CALLS
  • GetRtcCmos : SA_FUNCTION_CALLS
  • GetRtcTime : SA_FUNCTION_CALLS
  • GetSpdData : SA_FUNCTION_CALLS
  • GfxTurboIMON : GRAPHICS_DXE_CONFIG
  • GlobalResetMasksOverride : PCH_PM_CONFIG
  • GlobalSmi : PCH_LOCK_DOWN_CONFIG
  • GmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GmAdr64 : GRAPHICS_PEI_PREMEM_CONFIG
  • GnaEnable : GNA_CONFIG
  • GopVersion : GRAPHICS_DXE_CONFIG
  • GpioIrqRoute : PCH_INTERRUPT_CONFIG
  • GpioNo : CPU_PCIE_GPIO_INFO
  • GpioOverride : PCH_GENERAL_PREMEM_CONFIG
  • GpioPullN : IOM_AUX_ORI_PAD_CONFIG
  • GpioPullP : IOM_AUX_ORI_PAD_CONFIG
  • GpioSupport : CPU_PCIE_RTD3_GPIO
  • GraphicsConfigPtr : GRAPHICS_PEI_CONFIG
  • GtCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • GtClosEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • GtExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • GtFreqMax : GRAPHICS_PEI_CONFIG
  • GtIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • GtMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtPsmiSupport : GRAPHICS_PEI_PREMEM_CONFIG
  • GttMmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GttSize : GRAPHICS_PEI_PREMEM_CONFIG
  • GtVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • GuidHob : _CONFIG_BLOCK_HEADER , FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- h -

  • HardwareRemappedStorageConfig : RST_CONFIG
  • HdAudioLinkFrequency : HDAUDIO_CONFIG
  • HdcControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HddUnlock : RST_CONFIG
  • Header : _CONFIG_BLOCK , _CONFIG_BLOCK_TABLE_STRUCT , _PEI_ITBT_CONFIG , ADR_CONFIG , AMT_DXE_CONFIG , AMT_PEI_CONFIG , BCLK_CONFIG , BIOS_GUARD_CONFIG , CNVI_CONFIG , CNVI_PREMEM_CONFIG , CPU_CONFIG , CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_CONFIG , CPU_PCIE_RP_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , CPU_TRACE_HUB_PREMEM_CONFIG , CPU_TXT_PREMEM_CONFIG , EFI_HOB_CPU , EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_GUID_TYPE , EFI_HOB_HANDOFF_INFO_TABLE , EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_MODULE , EFI_HOB_MEMORY_ALLOCATION_STACK , EFI_HOB_MEMORY_POOL , EFI_HOB_RESOURCE_DESCRIPTOR , EFI_HOB_UEFI_CAPSULE , FIRMWARE_VERSION_INFO_HOB , GBE_CONFIG , GNA_CONFIG , GRAPHICS_DXE_CONFIG , GRAPHICS_PEI_CONFIG , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , HYBRID_STORAGE_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_I3C_CONFIG , ISH_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG , MEMORY_CONFIG_NO_CRC , MEMORY_CONFIGURATION , OVERCLOCKING_PREMEM_CONFIG , PCH_DCI_PREMEM_CONFIG , PCH_DMI_CONFIG , PCH_ESPI_CONFIG , PCH_FIVR_CONFIG , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_LOCK_DOWN_CONFIG , PCH_P2SB_CONFIG , PCH_PCIE_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG , PCH_WDT_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PREMEM_CONFIG , PCIE_RP_DXE_CONFIG , PSF_CONFIG , RST_CONFIG , RTC_CONFIG , SA_MISC_PEI_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_CONFIG , SERIAL_IO_CONFIG , SI_CONFIG , SI_PREMEM_CONFIG , TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG , THC_CONFIG , THERMAL_CONFIG , TSN_CONFIG , USB2_PHY_CONFIG , USB3_HSIO_CONFIG , USB_CONFIG , VMD_PEI_CONFIG , VTD_CONFIG , VTD_DXE_CONFIG
  • Heci1BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci2BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3Enabled : ME_PEI_CONFIG
  • HeciCommunication2 : ME_PEI_PREMEM_CONFIG
  • HeciFullTrace : ME_PEI_PREMEM_CONFIG
  • HeciTimeouts : ME_PEI_PREMEM_CONFIG
  • HgDelayAfterHoldReset : HYBRID_GRAPHICS_CONFIG
  • HgDelayAfterPwrEn : HYBRID_GRAPHICS_CONFIG
  • HgMode : HYBRID_GRAPHICS_CONFIG
  • HgSubSystemId : HYBRID_GRAPHICS_CONFIG
  • HgSupport : HYBRID_GRAPHICS_CONFIG
  • HideUnConfigureMeConfirm : AMT_DXE_CONFIG
  • HidOverSpi : THC_PORT
  • HobBufferSize : MEMORY_CONFIGURATION
  • HobLength : EFI_HOB_GENERIC_HEADER
  • HobType : EFI_HOB_GENERIC_HEADER
  • HoldRst : CPU_PCIE_RTD3_GPIO
  • HorizontalResolution : GRAPHICS_PEI_CONFIG
  • HostC10ReportEnable : PCH_ESPI_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • HotPlug : PCH_SATA_PORT_CONFIG
  • HsiiEnable : USB_CONFIG
  • HsioCtrlAdaptOffsetCfg : HSIO_PARAMETERS
  • HsioCtrlAdaptOffsetCfgEnable : HSIO_PARAMETERS
  • HsioFilterSelN : HSIO_PARAMETERS
  • HsioFilterSelNEnable : HSIO_PARAMETERS
  • HsioFilterSelP : HSIO_PARAMETERS
  • HsioFilterSelPEnable : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnRes : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnResEnable : HSIO_PARAMETERS
  • HsioTxDeEmph : HSIO_PARAMETERS
  • HsioTxDeEmphEnable : HSIO_PARAMETERS
  • HsioTxDownscaleAmp : HSIO_PARAMETERS
  • HsioTxDownscaleAmpEnable : HSIO_PARAMETERS
  • HsioTxRate0UniqTran : HSIO_PARAMETERS
  • HsioTxRate0UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate1UniqTran : HSIO_PARAMETERS
  • HsioTxRate1UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate2UniqTran : HSIO_PARAMETERS
  • HsioTxRate2UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate3UniqTran : HSIO_PARAMETERS
  • HsioTxRate3UniqTranEnable : HSIO_PARAMETERS
  • HslOri : TCSS_IOM_ORI_OVERRIDE
  • HwEqGen3CoeffList : PCIE_COMMON_CONFIG
  • HwEqGen4CoeffList : CPU_PCIE_CONFIG
  • Hwp : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpInterruptControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpLock : CPU_POWER_MGMT_BASIC_CONFIG
  • HybridStorageMode : HYBRID_STORAGE_CONFIG
  • HyperThreading : CPU_CONFIG_LIB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- i -

  • I2cDeviceConfig : SERIAL_IO_CONFIG
  • IaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • IaIccMax : OVERCLOCKING_PREMEM_CONFIG
  • IaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • IaSirpEnable : OVERCLOCKING_PREMEM_CONFIG
  • Ibecc : MEMORY_CONFIGURATION
  • IbeccErrInjAddress : MEMORY_CONFIGURATION
  • IbeccErrInjControl : MEMORY_CONFIGURATION
  • IbeccErrInjCount : MEMORY_CONFIGURATION
  • IbeccErrInjMask : MEMORY_CONFIGURATION
  • IbeccOperationMode : MEMORY_CONFIGURATION
  • IbeccProtectedRangeBase : MEMORY_CONFIGURATION
  • IbeccProtectedRangeEnable : MEMORY_CONFIGURATION
  • IbeccProtectedRangeMask : MEMORY_CONFIGURATION
  • IccLimit : CPU_POWER_MGMT_VR_CONFIG
  • IccMax : CPU_POWER_MGMT_VR_CONFIG , FIVR_EXT_RAIL_CONFIG
  • IccMaximum : FIVR_EXT_RAIL_CONFIG
  • Idd3n : MEMORY_CONFIGURATION
  • Idd3p : MEMORY_CONFIGURATION
  • IDispCodecDisconnect : HDAUDIO_PREMEM_CONFIG
  • IDispLinkFrequency : HDAUDIO_PREMEM_CONFIG
  • IDispLinkTmode : HDAUDIO_PREMEM_CONFIG
  • IdleLtr : THC_PORT
  • IedSize : SA_MISC_PEI_PREMEM_CONFIG
  • IgdBlcConfig : GRAPHICS_DXE_CONFIG
  • IgdBootType : GRAPHICS_DXE_CONFIG
  • IgdDvmt50PreAlloc : GRAPHICS_PEI_PREMEM_CONFIG
  • IgdDvmtMemSize : GRAPHICS_DXE_CONFIG
  • IgdPanelScaling : GRAPHICS_DXE_CONFIG
  • IgdPanelType : GRAPHICS_DXE_CONFIG
  • ImguClkOutEn : IPU_PREMEM_CONFIG
  • ImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • ImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • ImrEnabled : PCIE_IMR_CONFIG
  • ImrRpLocation : PCIE_IMR_CONFIG
  • ImrRpSelection : PCIE_IMR_CONFIG
  • ImrSize : PCIE_IMR_CONFIG
  • InfDfxPwrEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • InitPcieAspmAfterOprom : PCIE_PEI_PREMEM_CONFIG
  • InputReportBodyAddress : THC_HID_OVER_SPI
  • InputReportHeaderAddress : THC_HID_OVER_SPI
  • Instance : FSP_ERROR_INFO_HOB
  • InterlockSw : PCH_SATA_PORT_CONFIG
  • InternalGraphics : GRAPHICS_PEI_PREMEM_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • InterruptPinMuxing : THC_PORT
  • IntPing : SA_XDCI_IRQ_INT_CONFIG
  • IntX : PCH_DEVICE_INTERRUPT_CONFIG
  • IoApicEntry24_119 : PCH_IOAPIC_CONFIG
  • IoApicId : PCH_IOAPIC_CONFIG
  • IoeDebugEn : PCH_GENERAL_PREMEM_CONFIG
  • IomAuxPortPad : TCSS_IOM_PEI_CONFIG
  • IomBeforeEnteringTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IomConfig : TCSS_PEI_CONFIG
  • IomInterface : TCSS_IOM_PEI_CONFIG
  • IomStayInTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IoRead16 : SA_FUNCTION_CALLS
  • IoRead32 : SA_FUNCTION_CALLS
  • IoRead8 : SA_FUNCTION_CALLS
  • IotgPllSscEn : PCH_GENERAL_PREMEM_CONFIG
  • IoWrite16 : SA_FUNCTION_CALLS
  • IoWrite32 : SA_FUNCTION_CALLS
  • IoWrite8 : SA_FUNCTION_CALLS
  • IpuEnable : IPU_PREMEM_CONFIG
  • IpuImrConfiguration : IPU_PREMEM_CONFIG
  • Irms : CPU_POWER_MGMT_VR_CONFIG
  • Irq : PCH_DEVICE_INTERRUPT_CONFIG , SA_XDCI_IRQ_INT_CONFIG
  • Irrt : RST_CONFIG
  • IrrtOnly : RST_CONFIG
  • ITbtConnectTopologyTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtDmaLtr : _PEI_ITBT_CONFIG
  • ITbtForcePowerOnTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtGenericConfig : _PEI_ITBT_CONFIG
  • ITbtPcieRootPortEn : _ITBT_ROOTPORT_CONFIG
  • ITbtPcieTunnelingForUsb4 : _ITBT_GENERIC_CONFIG
  • ITbtRootPortConfig : _PEI_ITBT_CONFIG
  • ITbtSecurityLevel : _ITBT_GENERIC_CONFIG
  • ItdThrottleEnable : OVERCLOCKING_PREMEM_CONFIG
  • IuerStatusVal : GRAPHICS_DXE_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- j -

  • JtagC10PowerGateDisable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • JWRL : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- k -

  • KeepEarlyTrace : PCH_DCI_PREMEM_CONFIG
  • KtDeviceEnable : ME_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- l -

  • L1RpCtl : PCH_DMI_CONFIG
  • L1sCommonModeRestoreTime : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnScale : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnValue : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapMask : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapOffset : PCIE_DEVICE_OVERRIDE
  • LaneUsed : IPU_PREMEM_CONFIG
  • LanWakeFromDeepSx : PCH_WAKE_CONFIG
  • LatchEventsC10Exit : PCH_PM_CONFIG
  • LCT : MEMORY_CONFIGURATION
  • LctCmdEyeWidth : MEMORY_CONFIGURATION
  • LedEnable : SATA_CONFIG
  • LedLocate : RST_CONFIG
  • LeftShift64 : SA_FUNCTION_CALLS
  • LegacyIoLowLatency : PCH_GENERAL_CONFIG
  • LegacyOrom : RST_CONFIG
  • Length : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME
  • Lfsr0Mask : MEMORY_CONFIGURATION
  • Lfsr1Mask : MEMORY_CONFIGURATION
  • LgmrEnable : PCH_ESPI_CONFIG
  • LimitPacketSize : THC_PORT
  • LinkDownGpios : CPU_PCIE_RP_PREMEM_CONFIG
  • LocalTransmitterOverrideEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • LockConfig : GPIO_CONFIG
  • LockLinkConfiguration : PCH_ESPI_CONFIG
  • LockPTMregs : SA_MISC_PEI_PREMEM_CONFIG
  • LogoPixelHeight : GRAPHICS_PEI_CONFIG
  • LogoPixelWidth : GRAPHICS_PEI_CONFIG
  • LogoPtr : GRAPHICS_PEI_CONFIG
  • LogoSize : GRAPHICS_PEI_CONFIG
  • LowToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • Lp5BankMode : MEMORY_CONFIGURATION
  • Lp5CccConfig : MEMORY_CONFIGURATION
  • LpddrRttCa : MEMORY_CONFIGURATION
  • LpddrRttWr : MEMORY_CONFIGURATION
  • LpDqsOscEn : MEMORY_CONFIGURATION
  • LpMode : MEMORY_CONFIGURATION
  • LpmS0ixSubStateEnable : PCH_PM_CONFIG
  • LtrConfigLock : TCSS_PCIE_PORT_POLICY
  • LtrEnable : GBE_CONFIG , TCSS_PCIE_PORT_POLICY
  • LtrHighIdleTimeOverride : USB_CONFIG
  • LtrLowIdleTimeOverride : USB_CONFIG
  • LtrMaxNoSnoopLatency : TCSS_PCIE_PORT_POLICY
  • LtrMaxSnoopLatency : TCSS_PCIE_PORT_POLICY
  • LtrMediumIdleTimeOverride : USB_CONFIG
  • LtrOverrideEnable : USB_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- m -

  • MachineCheckEnable : CPU_TEST_CONFIG
  • ManageabilityMode : AMT_PEI_CONFIG
  • MappingPchXhciUsbA : TCSS_MISC_PEI_CONFIG
  • MarginLimitCheck : MEMORY_CONFIGURATION
  • MarginLimitL2 : MEMORY_CONFIGURATION
  • MaxRatio : PPM_CUSTOM_RATIO_TABLE
  • MaxRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MaxRttWr : MEMORY_CONFIGURATION
  • McPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • McRefresh2X : MEMORY_CONFIGURATION
  • McRefreshRate : MEMORY_CONFIGURATION
  • MctpBroadcastCycle : ME_PEI_CONFIG
  • MebxDebugMsg : AMT_DXE_CONFIG
  • MebxGraphicsMode : AMT_DXE_CONFIG
  • MebxNonUiTextMode : AMT_DXE_CONFIG
  • MebxUiTextMode : AMT_DXE_CONFIG
  • MemoryAllocationHeader : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • MemoryBaseAddress : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLength : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLock : RTC_CONFIG
  • MemoryThrottling : THERMAL_CONFIG
  • MemoryType : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemReg0Size : TRACE_HUB_CONFIG
  • MemTestOnWarmBoot : MEMORY_CONFIG_NO_CRC
  • MEMTST : MEMORY_CONFIGURATION
  • MeUnconfigOnRtcClear : ME_PEI_CONFIG
  • MeWakeSts : PCH_PM_CONFIG
  • MicrocodePatchAddress : CPU_CONFIG
  • MinRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MinVoltageC8 : CPU_POWER_MGMT_VR_CONFIG
  • MinVoltageRuntime : CPU_POWER_MGMT_VR_CONFIG
  • MiscConfig : TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG
  • Miso : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MlcSpatialPrefetcher : CPU_TEST_CONFIG
  • MlcStreamerPrefetcher : CPU_TEST_CONFIG
  • MmioRead16 : SA_FUNCTION_CALLS
  • MmioRead32 : SA_FUNCTION_CALLS
  • MmioRead64 : SA_FUNCTION_CALLS
  • MmioRead8 : SA_FUNCTION_CALLS
  • MmioWrite16 : SA_FUNCTION_CALLS
  • MmioWrite32 : SA_FUNCTION_CALLS
  • MmioWrite64 : SA_FUNCTION_CALLS
  • MmioWrite8 : SA_FUNCTION_CALLS
  • MmramReservedSize : _EFI_MM_RESERVED_MMRAM_REGION
  • MmramReservedStart : _EFI_MM_RESERVED_MMRAM_REGION
  • MobilePlatform : MEMORY_CONFIGURATION
  • Mode : CNVI_CONFIG , IEH_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG , THC_PORT
  • ModPhySusPgEnable : PCH_PM_CONFIG
  • ModuleName : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • MonitorMwaitEnable : CPU_TEST_CONFIG
  • Mosi : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MrcCall : MEMORY_CONFIG_NO_CRC
  • MrcChangeMargin : SA_MEMORY_FUNCTIONS
  • MrcChannelExist : SA_MEMORY_FUNCTIONS
  • MrcDelayNs : SA_FUNCTION_CALLS
  • MrcDramReset : SA_FUNCTION_CALLS
  • MrcFastBoot : MEMORY_CONFIGURATION
  • MrcPrintf : SA_MEMORY_FUNCTIONS
  • MrcReturnFromSmc : SA_FUNCTION_CALLS
  • MrcSafeConfig : MEMORY_CONFIGURATION
  • MrcSignExtend : SA_MEMORY_FUNCTIONS
  • MrcTimeMeasure : MEMORY_CONFIGURATION
  • MrcUpdateVref : SA_MEMORY_FUNCTIONS
  • MsHashEnable : MEMORY_CONFIGURATION
  • MsHashInterleaveBit : MEMORY_CONFIGURATION
  • MsHashMask : MEMORY_CONFIGURATION
  • MsiInterrupt : ISH_CONFIG
  • MultiVcEnable : TSN_CONFIG
  • MultiVcEnabled : CPU_PCIE_ROOT_PORT_CONFIG
  • MultU64x32 : SA_FUNCTION_CALLS
  • MvcEnabled : PCH_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- n -

  • Name : EFI_HOB_GUID_TYPE , EFI_HOB_MEMORY_ALLOCATION_HEADER
  • NewFeatureEnable1 : MEMORY_CONFIGURATION
  • NewFeatureEnable2 : MEMORY_CONFIGURATION
  • NewFom : CPU_PCIE_RP_PREMEM_CONFIG
  • NModeSupport : MEMORY_CONFIGURATION
  • NoFatalErrorReport : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatency : PCIE_DEVICE_OVERRIDE
  • NonSnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • NumberOfBlocks : _CONFIG_BLOCK_TABLE_STRUCT
  • NumberOfEntries : PPM_CUSTOM_RATIO_TABLE
  • NumberOfSsidTableEntry : SI_CONFIG
  • NumOfDevIntConfig : PCH_INTERRUPT_CONFIG
  • NumRsvdSmbusAddresses : PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- o -

  • OcLock : OVERCLOCKING_PREMEM_CONFIG
  • OcSupport : OVERCLOCKING_PREMEM_CONFIG
  • OemResolutionSettingsRsvd : AMT_DXE_CONFIG
  • OemT12DelayOverride : GRAPHICS_PEI_PREMEM_CONFIG
  • OffToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • OneCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • OpRomScanTempMmioBar : SA_MISC_PEI_PREMEM_CONFIG
  • OpRomScanTempMmioLimit : SA_MISC_PEI_PREMEM_CONFIG
  • OptaneMemory : RST_CONFIG
  • OromUiBanner : RST_CONFIG
  • OromUiDelay : RST_CONFIG
  • OsIdleEnable : PCH_PM_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputReportAddress : THC_HID_OVER_SPI
  • OutputState : GPIO_CONFIG
  • OverCurrentEnable : USB_CONFIG
  • OverCurrentPin : USB2_PORT_CONFIG , USB3_PORT_CONFIG
  • OverrideConfig : PCIE_DEVICE_OVERRIDE
  • Owner : EFI_HOB_RESOURCE_DESCRIPTOR
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- p -

  • P0T1M : SATA_THERMAL_THROTTLING
  • P0T2M : SATA_THERMAL_THROTTLING
  • P0T3M : SATA_THERMAL_THROTTLING
  • P0TDisp : SATA_THERMAL_THROTTLING
  • P0TDispFinit : SATA_THERMAL_THROTTLING
  • P0Tinact : SATA_THERMAL_THROTTLING
  • P1T1M : SATA_THERMAL_THROTTLING
  • P1T2M : SATA_THERMAL_THROTTLING
  • P1T3M : SATA_THERMAL_THROTTLING
  • P1TDisp : SATA_THERMAL_THROTTLING
  • P1TDispFinit : SATA_THERMAL_THROTTLING
  • P1Tinact : SATA_THERMAL_THROTTLING
  • PadMode : GPIO_CONFIG
  • PadTermination : ISH_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG
  • PanelPowerEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • Parity : SERIAL_IO_UART_ATTRIBUTES
  • PavpEnable : GRAPHICS_PEI_CONFIG
  • PCETTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PchCrossThrottling : THERMAL_THROTTLE_LEVELS
  • PchDeepSxPol : PCH_PM_CONFIG
  • PchHotEnable : THERMAL_CONFIG
  • PchHotLevel : THERMAL_CONFIG
  • PchPciePort8xhDecodePortIndex : PCH_PCIE_CONFIG
  • PchPwrCycDur : PCH_PM_CONFIG
  • PchSlpAMinAssert : PCH_PM_CONFIG
  • PchSlpS3MinAssert : PCH_PM_CONFIG
  • PchSlpS4MinAssert : PCH_PM_CONFIG
  • PchSlpSusMinAssert : PCH_PM_CONFIG
  • PciData : MEMORY_CONFIGURATION
  • PcieClock : PCH_PCIE_RP_PREMEM_CONFIG
  • PcieCommonConfig : PCH_PCIE_CONFIG
  • PcieDeviceOverrideTablePtr : CPU_PCIE_CONFIG , PCIE_RP_DXE_CONFIG
  • PcieImr : PCIE_PREMEM_CONFIG
  • PcieLinkEqMethod : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieLinkEqMode : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieMultipleSegmentEnabled : TCSS_MISC_PEI_PREMEM_CONFIG
  • PciePllSsc : PCH_PM_CONFIG
  • PciePolicy : TCSS_PEI_CONFIG
  • PcieRpCommonConfig : CPU_PCIE_ROOT_PORT_CONFIG
  • PcieSpeed : CPU_PCIE_RP_PREMEM_CONFIG
  • PcieWakeFromDeepSx : PCH_WAKE_CONFIG
  • PciIndex : MEMORY_CONFIGURATION
  • PDA : MEMORY_CONFIGURATION
  • PdoProgramming : USB_CONFIG
  • PdtUnlock : ISH_CONFIG
  • PeciC10Reset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • PeciSxReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • PegGen3EndPointHint : CPU_PCIE_EQ_LANE_PARAM
  • PegGen3EndPointPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen3ProgramStaticEq : CPU_PCIE_CONFIG
  • PegGen3RootPortPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4EndPointHint : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4EndPointPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4ProgramStaticEq : CPU_PCIE_CONFIG
  • PegGen4RootPortPreset : CPU_PCIE_EQ_LANE_PARAM
  • Pehalfbit : USB2_PHY_PARAMETERS
  • PeiGraphicsPeimInit : GRAPHICS_PEI_CONFIG
  • PeiPolicyInit : _PEI_SI_DEFAULT_POLICY_INIT_PPI
  • PeiPreMemPolicyInit : _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  • PerAtomClusterVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerBankRefresh : MEMORY_CONFIGURATION
  • PerCoreHtDisable : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreRatioOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerformanceLimitation : THC_PORT
  • PeriodicDcc : MEMORY_CONFIGURATION
  • Petxiset : USB2_PHY_PARAMETERS
  • Ph1DownstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph1UpstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph2LocalTransmitterOverridePreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3CoefficientsList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3NumberOfPresetsOrCoefficients : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3PresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PhysicalSize : EFI_MMRAM_DESCRIPTOR
  • PhysicalStart : EFI_HOB_RESOURCE_DESCRIPTOR , EFI_MMRAM_DESCRIPTOR
  • PinMux : CNVI_CONFIG , HDA_LINK_DMIC , ISH_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG
  • PinSelection : TS_GPIO_PIN_SETTING
  • PkgCStateDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateLimit : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateUnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PlatformConfig : GRAPHICS_DXE_CONFIG
  • PlatformDebugConsent : SI_PREMEM_CONFIG
  • PlatformMemorySize : MEMORY_CONFIG_NO_CRC
  • PllMaxBandingRatio : OVERCLOCKING_PREMEM_CONFIG
  • PmcDbgMsgEn : PCH_PM_CONFIG
  • PmcInterface : TCSS_IOM_PEI_CONFIG
  • PmcPdEnable : PMC_INTERFACE_CONFIG
  • Pme : HDAUDIO_CONFIG
  • PmeB0S5Dis : PCH_WAKE_CONFIG
  • PmgCstCfgCtrlLock : CPU_POWER_MGMT_TEST_CONFIG
  • PmodeClkEn : PCH_GENERAL_PREMEM_CONFIG
  • PmSupport : GRAPHICS_PEI_CONFIG
  • PmsyncEnable : TS_GPIO_PIN_SETTING
  • Port : USB2_PHY_CONFIG , USB3_HSIO_CONFIG
  • Port80Route : PCH_GENERAL_PREMEM_CONFIG
  • PortResetMessageEnable : USB2_PORT_CONFIG
  • PortSettings : SATA_CONFIG
  • PortUsb20 : USB_CONFIG
  • PortUsb30 : USB_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerDownMode : MEMORY_CONFIGURATION
  • PowerGating : SERIAL_IO_UART_CONFIG
  • PowerGatingSupported : HDAUDIO_PREMEM_CONFIG
  • PowerLimit1 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit1Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2Power : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3DutyCycle : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PpinSupport : CPU_CONFIG
  • PpmIrmSetting : CPU_POWER_MGMT_TEST_CONFIG
  • PprEnable : MEMORY_CONFIGURATION
  • PreBootDmaMask : VTD_CONFIG
  • Predeemp : USB2_PHY_PARAMETERS
  • PreWake : CPU_POWER_MGMT_VR_CONFIG
  • PrimaryDisplay : GRAPHICS_PEI_PREMEM_CONFIG
  • PrmrrSize : CPU_SECURITY_PREMEM_CONFIG
  • ProbelessTrace : MEMORY_CONFIGURATION
  • ProcessorTraceEnable : CPU_TEST_CONFIG
  • ProcessorTraceMemSize : CPU_TEST_CONFIG
  • ProcessorTraceOutputScheme : CPU_TEST_CONFIG
  • ProcHotLock : CPU_POWER_MGMT_TEST_CONFIG
  • ProcHotResponse : CPU_POWER_MGMT_TEST_CONFIG
  • ProgramGtChickenBits : GRAPHICS_PEI_CONFIG
  • PS1toPS0CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0MCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1MCoef : CPU_POWER_MGMT_VR_CONFIG
  • Psi1Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi2Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Enable : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi4Enable : CPU_POWER_MGMT_VR_CONFIG
  • PsmiRegionSize : GRAPHICS_PEI_PREMEM_CONFIG
  • PsOnEnable : PCH_PM_CONFIG
  • PsysOffset : CPU_POWER_MGMT_VR_CONFIG
  • PsysOffset1 : CPU_POWER_MGMT_VR_CONFIG
  • PsysPmax : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Time : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysSlope : CPU_POWER_MGMT_VR_CONFIG
  • PtmEnabled : TCSS_PCIE_PORT_POLICY
  • PvdMode : OVERCLOCKING_PREMEM_CONFIG
  • PvdRatioThreshold : OVERCLOCKING_PREMEM_CONFIG
  • PVTTDNLP : MEMORY_CONFIGURATION
  • PwdwnIdleCounter : MEMORY_CONFIGURATION
  • PwrBtnOverridePeriod : PCH_PM_CONFIG
  • PwrEnable : CPU_PCIE_RTD3_GPIO
  • PwrOptEnable : PCH_DMI_CONFIG , SATA_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- r -

  • RaceToHalt : CPU_POWER_MGMT_TEST_CONFIG
  • Raid0 : RST_CONFIG
  • Raid1 : RST_CONFIG
  • Raid10 : RST_CONFIG
  • Raid5 : RST_CONFIG
  • RaidDeviceId : SATA_CONFIG
  • RampDown : CPU_POWER_MGMT_VR_CONFIG
  • RampUp : CPU_POWER_MGMT_VR_CONFIG
  • Rank : SA_ADDRESS_DECODE
  • RankInterleave : MEMORY_CONFIGURATION
  • Ras : SA_ADDRESS_DECODE
  • Ratio : MEMORY_CONFIGURATION
  • RC1pFreqEnable : GRAPHICS_PEI_CONFIG
  • RcompData : MEMORY_CONFIG_NO_CRC
  • RcompResistor : SA_MEMORY_RCOMP
  • RcompTarget : SA_MEMORY_RCOMP
  • RCVENC1D : MEMORY_CONFIGURATION
  • RCVET : MEMORY_CONFIGURATION
  • RDAPT : MEMORY_CONFIGURATION
  • RDEQT : MEMORY_CONFIGURATION
  • RDMPRT : MEMORY_CONFIGURATION
  • RDODTT : MEMORY_CONFIGURATION
  • RDTC1D : MEMORY_CONFIGURATION
  • RDTC2D : MEMORY_CONFIGURATION
  • RDVC1D : MEMORY_CONFIGURATION
  • RDVC2D : MEMORY_CONFIGURATION
  • RDVREFDC : MEMORY_CONFIGURATION
  • ReadMsr64 : SA_FUNCTION_CALLS
  • ReadOpcode : THC_HID_OVER_SPI
  • RealtimeMemoryFrequency : MEMORY_CONFIGURATION
  • RealtimeMemoryTiming : OVERCLOCKING_PREMEM_CONFIG
  • RefClk : MEMORY_CONFIGURATION
  • Refresh2X : MEMORY_CONFIGURATION
  • RefreshHpWm : MEMORY_CONFIGURATION
  • RefreshPanicWm : MEMORY_CONFIGURATION
  • RefreshWm : MEMORY_CONFIGURATION
  • RegionState : EFI_MMRAM_DESCRIPTOR
  • RemapEnable : MEMORY_CONFIGURATION
  • RemoteAssistance : AMT_PEI_CONFIG
  • RemotePresetCoeffoverride : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • RenderStandby : GRAPHICS_PEI_CONFIG
  • Reserved : _CONFIG_BLOCK_HEADER , _ITBT_GENERIC_CONFIG , _ITBT_ROOTPORT_CONFIG , BIOS_GUARD_CONFIG , CPU_SECURITY_PREMEM_CONFIG , EFI_HOB_CPU , EFI_HOB_GENERIC_HEADER , EFI_HOB_MEMORY_ALLOCATION_HEADER , GRAPHICS_DXE_CONFIG , HDA_LINK_HDA , PMC_LPM_S0IX_SUB_STATE_EN , TCSS_IOM_PEI_CONFIG , THC_PORT , VTD_CONFIG
  • Reserved0 : CPU_CONFIG
  • Reserved1 : SA_MISC_PEI_PREMEM_CONFIG
  • Reserved11 : MEMORY_CONFIG_NO_CRC
  • Reserved274 : MEMORY_CONFIGURATION
  • Reserved3 : SPD_OFFSET_TABLE
  • Reserved336 : MEMORY_CONFIGURATION
  • ReservedBits1 : CPU_POWER_MGMT_BASIC_CONFIG
  • ReservedBits2 : MEMORY_CONFIGURATION
  • ResetAux : CPU_SECURITY_PREMEM_CONFIG
  • ResetPad : THC_HID_OVER_SPI
  • ResetPadTrigger : THC_HID_OVER_SPI
  • ResetWaitTimer : HDAUDIO_PREMEM_CONFIG
  • ResourceAttribute : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceLength : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceType : EFI_HOB_RESOURCE_DESCRIPTOR
  • RetrainOnFastFail : MEMORY_CONFIGURATION
  • RetToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RetToLowCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • ReuseAdlSDdr5Board : MEMORY_CONFIGURATION
  • RevId : PCIE_DEVICE_OVERRIDE
  • Revision : _CONFIG_BLOCK_HEADER
  • RevisionId : HDA_VERB_TABLE_HEADER
  • RfiMitigation : CPU_POWER_MGMT_VR_CONFIG
  • RfReset : CNVI_PIN_MUX
  • RhSelect : MEMORY_CONFIGURATION
  • RightShift64 : SA_FUNCTION_CALLS
  • RingDownBin : OVERCLOCKING_PREMEM_CONFIG
  • RingMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • RMC : MEMORY_CONFIGURATION
  • RMT : MEMORY_CONFIGURATION
  • RMTBIT : MEMORY_CONFIGURATION
  • RMTLoopCount : MEMORY_CONFIGURATION
  • RmtPerTask : MEMORY_CONFIGURATION
  • RootPort : CPU_PCIE_CONFIG
  • RootPortIndex : HYBRID_GRAPHICS_CONFIG
  • RpDpcExtensionsEnabled : TCSS_PCIE_PORT_POLICY
  • RpEnabledMask : CPU_PCIE_RP_PREMEM_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG
  • RpFunctionSwap : PCIE_COMMON_CONFIG
  • RstPcieStoragePort : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • Rsvd : CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , TCSS_MISC_PEI_CONFIG , TCSS_MISC_PEI_PREMEM_CONFIG , TCSS_USBTC_PEI_PERMEM_CONFIG
  • Rsvd0 : _CONFIG_BLOCK_TABLE_STRUCT , CPU_DMI_EQ_PARAM , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_GPIO_INFO , CPU_PCIE_RTD3_GPIO , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , PCH_DMI_EQ_PARAM , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_EQ_PARAM , PCIE_PEI_PREMEM_CONFIG , PPM_CUSTOM_RATIO_TABLE , THERMAL_THROTTLE_LEVELS , TSN_CONFIG
  • Rsvd1 : GRAPHICS_PEI_CONFIG , PCH_PM_CONFIG
  • Rsvd2 : GRAPHICS_PEI_PREMEM_CONFIG
  • Rsvd5 : CPU_POWER_MGMT_VR_CONFIG
  • RsvdBits : _PPM_CUSTOM_CTDP_TABLE , AMT_DXE_CONFIG , AMT_PEI_CONFIG , CPU_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , GPIO_CONFIG , HDAUDIO_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG
  • Rsvdbits : PCH_DMI_CONFIG
  • RsvdBits : PCH_ESPI_CONFIG
  • Rsvdbits : PCH_P2SB_CONFIG
  • RsvdBits : SI_PREMEM_CONFIG
  • RsvdBits0 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , GBE_CONFIG , GNA_CONFIG , HDAUDIO_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_UART , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_LOCK_DOWN_CONFIG , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_COMMON_CONFIG , PCIE_PEI_PREMEM_CONFIG , PSF_CONFIG , RST_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_THERMAL_THROTTLING , USB2_PORT_CONFIG , USB3_PORT_CONFIG , USB_CONFIG , XDCI_CONFIG
  • RsvdBits1 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , FIVR_EXT_RAIL_CONFIG , PCH_IOAPIC_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • RsvdBits2 : FIVR_EXT_RAIL_CONFIG
  • RsvdByte2 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte3 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte4 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte5 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte6 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdBytes : PCH_PCIE_CLOCK , SI_PREMEM_CONFIG
  • RsvdBytes0 : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG , SI_CONFIG
  • RsvdBytes1 : SI_CONFIG
  • RsvdBytes2 : SI_CONFIG
  • RsvdField0 : ISH_SPI
  • RsvdO64B25to31 : MEMORY_CONFIGURATION
  • RsvdSmbusAddressTable : PCH_SMBUS_PREMEM_CONFIG
  • RTL : MEMORY_CONFIGURATION
  • Rts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • Rx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RxPolarity : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- s -

  • S0i2p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p3En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p4En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0ixAutoDemotion : PCH_PM_CONFIG
  • S3DataPtr : SA_MISC_PEI_PREMEM_CONFIG
  • SaCall : MEMORY_CONFIG_NO_CRC
  • SaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • SaExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • SafeMode : MEMORY_CONFIGURATION
  • SaGv : MEMORY_CONFIGURATION
  • SaGvFreq : MEMORY_CONFIGURATION
  • SaGvGear : MEMORY_CONFIGURATION
  • SagvHeuristicsDownControl : MEMORY_CONFIGURATION
  • SagvHeuristicsUpControl : MEMORY_CONFIGURATION
  • SagvSwitchFactorGT : MEMORY_CONFIGURATION
  • SagvSwitchFactorIA : MEMORY_CONFIGURATION
  • SagvSwitchFactorIO : MEMORY_CONFIGURATION
  • SagvSwitchFactorStall : MEMORY_CONFIGURATION
  • SalpSupport : SATA_CONFIG
  • SaPllFreqOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SataMode : SATA_CONFIG
  • SataPmPtm : PCH_SATA_PORT_CONFIG
  • SataRstInterrupt : SATA_CONFIG
  • SaVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaXdci : TCSS_MISC_PEI_CONFIG
  • SbAccessUnlock : PCH_P2SB_CONFIG
  • ScanExtGfxForLegacyOpRom : SA_MISC_PEI_PREMEM_CONFIG
  • SciIrqSelect : PCH_INTERRUPT_CONFIG
  • Scl : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • ScramblerSupport : MEMORY_CONFIGURATION
  • Sda : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • SdiEnable : HDA_LINK_HDA
  • SdiNum : HDA_VERB_TABLE_HEADER
  • SendDidMsg : ME_PEI_PREMEM_CONFIG
  • SendEcCmd : BIOS_GUARD_CONFIG
  • SendVrMbxCmd : CPU_POWER_MGMT_VR_CONFIG
  • SerialDebugLevel : MEMORY_CONFIG_NO_CRC
  • SetMem : SA_FUNCTION_CALLS
  • SetMemDword : SA_FUNCTION_CALLS
  • SetMemoryPmicVoltage : SA_FUNCTION_CALLS
  • SetMemoryVdd : SA_FUNCTION_CALLS
  • SetMemWord : SA_FUNCTION_CALLS
  • SetSecuredRegisterLock : CPU_PCIE_CONFIG
  • SevenCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • SgpioSupport : SATA_CONFIG
  • SharedZqPin : MEMORY_CONFIGURATION
  • ShiftPiCommandTrain : SA_MEMORY_FUNCTIONS
  • SimicsFlag : MEMORY_CONFIGURATION
  • SinitMemorySize : CPU_TXT_PREMEM_CONFIG
  • SixCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Size : GRAPHICS_DXE_CONFIG , MEMORY_CONFIGURATION
  • SizeOfIoSpace : EFI_HOB_CPU
  • SizeOfMemorySpace : EFI_HOB_CPU
  • SkipBiosDoneWhenFwUpdate : SI_CONFIG
  • SkipCdClockInit : GRAPHICS_PEI_CONFIG
  • SkipCpuReplacementCheck : ME_PEI_PREMEM_CONFIG
  • SkipExtGfxScan : SA_MISC_PEI_PREMEM_CONFIG
  • SkipFspGop : GRAPHICS_PEI_CONFIG
  • SkipMbpHob : ME_PEI_PREMEM_CONFIG
  • SkipMpInit : CPU_CONFIG
  • SkipOverrideBootModeWhenFwUpdate : SI_PREMEM_CONFIG
  • SkipSetBootPState : CPU_POWER_MGMT_BASIC_CONFIG
  • SkipSsidProgramming : SI_CONFIG
  • SkipStopPbet : CPU_SECURITY_PREMEM_CONFIG
  • SlotNumber : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitScale : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitValue : TCSS_PCIE_PORT_POLICY
  • SlotSelection : CPU_PCIE_CONFIG
  • SlowSlewRate : CPU_POWER_MGMT_VR_CONFIG
  • SlpLanLowDc : PCH_PM_CONFIG
  • SlpStrchSusUp : PCH_PM_CONFIG
  • SmartStorage : RST_CONFIG
  • SmbAlertEnable : PCH_SMBUS_PREMEM_CONFIG
  • SmbiosData : FIRMWARE_VERSION_INFO_HOB
  • SmbiosType4MaxSpeedOverride : CPU_CONFIG
  • SmbusBar : SA_MISC_PEI_PREMEM_CONFIG
  • SmbusIoBase : PCH_SMBUS_PREMEM_CONFIG
  • SmbusRead16 : SA_FUNCTION_CALLS
  • SmbusRead8 : SA_FUNCTION_CALLS
  • SmbusWrite16 : SA_FUNCTION_CALLS
  • SmbusWrite8 : SA_FUNCTION_CALLS
  • SmramMask : MEMORY_CONFIGURATION
  • SndwConfig : HDAUDIO_DXE_CONFIG
  • SnoopLatency : PCIE_DEVICE_OVERRIDE
  • SnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • SocBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • SocBclkPllOn : BCLK_CONFIG
  • SocDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SocDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SolidStateDrive : PCH_SATA_PORT_CONFIG
  • SOT : MEMORY_CONFIGURATION
  • SpdAddressTable : SA_MISC_PEI_PREMEM_CONFIG
  • SpdData : MEMORY_CONFIG_NO_CRC , SPD_DATA_BUFFER
  • SpdProfileSelected : MEMORY_CONFIGURATION
  • SpdWriteDisable : PCH_SMBUS_PREMEM_CONFIG
  • SpeedLimit : SATA_CONFIG
  • SpiDeviceConfig : SERIAL_IO_CONFIG
  • SpiEiss : PCH_LOCK_DOWN_CONFIG
  • SpinUp : PCH_SATA_PORT_CONFIG
  • SrefCfgEna : MEMORY_CONFIGURATION
  • SrefCfgIdleTmr : MEMORY_CONFIGURATION
  • SsidTablePtr : SI_CONFIG
  • Start : SPD_OFFSET_TABLE
  • StateRatio : PPM_CUSTOM_RATIO_TABLE
  • StateRatioMax16 : PPM_CUSTOM_RATIO_TABLE
  • Status : FSP_ERROR_INFO_HOB
  • StopBits : SERIAL_IO_UART_ATTRIBUTES
  • SubClassCode : PCIE_DEVICE_OVERRIDE
  • SubSystemIds : HDAUDIO_PREMEM_CONFIG
  • SuggestedSetting : DMI_HW_WIDTH_CONTROL , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS
  • SupportedVoltageStates : FIVR_EXT_RAIL_CONFIG
  • SystemErrorEnable : PCH_PCIE_ROOT_PORT_CONFIG
  • SystemErrorOnCorrectableError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnFatalError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnNonFatalError : TCSS_PCIE_PORT_POLICY
  • SystemMemoryLength : SA_MISC_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- t -

  • T0Level : THERMAL_THROTTLE_LEVELS
  • T1Level : THERMAL_THROTTLE_LEVELS
  • T2Level : THERMAL_THROTTLE_LEVELS
  • TableHeader : _SI_POLICY_STRUCT , _SI_PREMEM_POLICY_STRUCT
  • TAT : MEMORY_CONFIGURATION
  • TccActivationOffset : CPU_POWER_MGMT_BASIC_CONFIG
  • tCCD_L : MEMORY_CONFIGURATION
  • TccEnable : PSF_CONFIG
  • TccOffsetClamp : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetTimeWindowForRatl : CPU_POWER_MGMT_BASIC_CONFIG
  • tCL : MEMORY_CONFIGURATION
  • TcoIrqEnable : PCH_INTERRUPT_CONFIG
  • TcoIrqSelect : PCH_INTERRUPT_CONFIG
  • TcssDevEn : TCSS_DEVEN_PEI_PREMEM_CONFIG
  • TcStateLimit : TCSS_IOM_PEI_CONFIG
  • tCWL : MEMORY_CONFIGURATION
  • TdcCurrentLimit : CPU_POWER_MGMT_VR_CONFIG
  • TdcEnable : CPU_POWER_MGMT_VR_CONFIG
  • TdcLock : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow1 : CPU_POWER_MGMT_VR_CONFIG
  • TestMode : SATA_CONFIG
  • tFAW : MEMORY_CONFIGURATION
  • TgaSize : CPU_TXT_PREMEM_CONFIG
  • ThcPort : THC_CONFIG
  • ThermalMonitor : CPU_POWER_MGMT_TEST_CONFIG
  • ThermalThrottling : SATA_CONFIG
  • ThermTimerDelay : PCH_PM_CONFIG
  • ThreeCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • ThreeStrikeCounterDisable : CPU_TEST_CONFIG
  • ThrtCkeMinDefeat : MEMORY_CONFIGURATION
  • ThrtCkeMinDefeatLpddr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmrLpddr : MEMORY_CONFIGURATION
  • TimedMwait : CPU_POWER_MGMT_TEST_CONFIG
  • TjMaxOffset : OVERCLOCKING_PREMEM_CONFIG
  • TmeEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • TraceHub : CPU_TRACE_HUB_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG
  • TrainTrace : MEMORY_CONFIGURATION
  • tRAS : MEMORY_CONFIGURATION
  • tRCDtRP : MEMORY_CONFIGURATION
  • tREFI : MEMORY_CONFIGURATION
  • tRFC : MEMORY_CONFIGURATION
  • tRFC2 : MEMORY_CONFIGURATION
  • tRFC4 : MEMORY_CONFIGURATION
  • tRFCpb : MEMORY_CONFIGURATION
  • tRRD : MEMORY_CONFIGURATION
  • tRRD_L : MEMORY_CONFIGURATION
  • tRRD_S : MEMORY_CONFIGURATION
  • tRTP : MEMORY_CONFIGURATION
  • TS0TW : DMI_HW_WIDTH_CONTROL
  • TS1TW : DMI_HW_WIDTH_CONTROL
  • TS2TW : DMI_HW_WIDTH_CONTROL
  • TS3TW : DMI_HW_WIDTH_CONTROL
  • TscDisableHwFixup : OVERCLOCKING_PREMEM_CONFIG
  • TsegSize : SA_MISC_PEI_PREMEM_CONFIG
  • TsGpioPinSetting : PCH_MEMORY_THROTTLING
  • TsLockTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • TsnLinkSpeed : TSN_CONFIG
  • TsnMacAddressHigh : TSN_CONFIG
  • TsnMacAddressLow : TSN_CONFIG
  • TStates : CPU_POWER_MGMT_TEST_CONFIG
  • TTEnable : THERMAL_THROTTLE_LEVELS
  • TTLevels : THERMAL_CONFIG
  • TTLock : THERMAL_THROTTLE_LEVELS
  • TTState13Enable : THERMAL_THROTTLE_LEVELS
  • TurboMode : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboPowerLimitLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • TvbDownBinsTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbDownBinsTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbRatioClipping : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbVoltageOptimization : OVERCLOCKING_PREMEM_CONFIG
  • TwoCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • tWR : MEMORY_CONFIGURATION
  • tWTR : MEMORY_CONFIGURATION
  • tWTR_L : MEMORY_CONFIGURATION
  • tWTR_S : MEMORY_CONFIGURATION
  • Tx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • TXDQSDCC : MEMORY_CONFIGURATION
  • Txiset : USB2_PHY_PARAMETERS
  • Txt : CPU_SECURITY_PREMEM_CONFIG
  • TxtAcheckRequest : CPU_SECURITY_PREMEM_CONFIG
  • TXTCO : MEMORY_CONFIGURATION
  • TXTCODQS : MEMORY_CONFIGURATION
  • TxtDprMemoryBase : CPU_TXT_PREMEM_CONFIG
  • TxtDprMemorySize : CPU_TXT_PREMEM_CONFIG
  • TxtEnable : CPU_CONFIG
  • TxtHeapMemorySize : CPU_TXT_PREMEM_CONFIG
  • TxtImplemented : SA_MISC_PEI_PREMEM_CONFIG
  • TxtLcpPdBase : CPU_TXT_PREMEM_CONFIG
  • TxtLcpPdSize : CPU_TXT_PREMEM_CONFIG
  • Type : FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- u -

  • UaolEnable : USB_CONFIG
  • UartDeviceConfig : SERIAL_IO_CONFIG
  • UnConfigureMe : AMT_DXE_CONFIG
  • UnlimitedIccMax : OVERCLOCKING_PREMEM_CONFIG
  • UnlockGpioPads : PCH_LOCK_DOWN_CONFIG
  • UnsupportedRequestReport : TCSS_PCIE_PORT_POLICY
  • Usage : PCH_PCIE_CLOCK
  • Usb2PhySusPgEnable : PCH_PM_CONFIG
  • Usb4CmMode : _ITBT_GENERIC_CONFIG
  • UsbConfig : TCSS_PEI_CONFIG
  • UsbOverride : IOM_INTERFACE_CONFIG
  • UsbProvision : AMT_DXE_CONFIG
  • UsbTcConfig : TCSS_PEI_PREMEM_CONFIG
  • UsbTcPortEn : TCSS_USBTC_PEI_PERMEM_CONFIG
  • UserBd : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • UserBudgetEnable : MEMORY_CONFIGURATION
  • UserThresholdEnable : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- v -

  • V1p05IsExtFetControlEn : PCH_PM_CONFIG
  • V1p05PhyExtFetControlEn : PCH_PM_CONFIG
  • Value : FSP_ERROR_INFO_HOB
  • VbtAddress : GRAPHICS_DXE_CONFIG
  • Vc1ReadMeter : MEMORY_CONFIGURATION
  • VCCDLLBP : MEMORY_CONFIGURATION
  • VccinAux : PCH_FIVR_CONFIG
  • VccInAuxImonIccImax : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionCapacitanceInUf : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionEnable : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionQuiescentPowerInMw : CPU_POWER_MGMT_VR_CONFIG
  • VccSt : IOM_INTERFACE_CONFIG
  • VcType : HDAUDIO_PREMEM_CONFIG
  • VDDQT : MEMORY_CONFIGURATION
  • VddqVoltage : MEMORY_CONFIGURATION
  • VddSettleWaitTime : MEMORY_CONFIGURATION
  • VddVoltage : MEMORY_CONFIGURATION
  • VendorId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • VerbTableEntryNum : HDAUDIO_CONFIG
  • VerbTablePtr : HDAUDIO_CONFIG
  • Version : EFI_HOB_HANDOFF_INFO_TABLE , FIRMWARE_VERSION_INFO
  • VersionStringIndex : FIRMWARE_VERSION_INFO
  • VerticalResolution : GRAPHICS_PEI_CONFIG
  • VmdCfgBarAttr : VMD_PEI_CONFIG
  • VmdCfgBarBase : VMD_PEI_CONFIG
  • VmdCfgBarSize : VMD_PEI_CONFIG
  • VmdEnable : VMD_PEI_CONFIG
  • VmdGlobalMapping : VMD_PEI_CONFIG
  • VmdMemBar1Attr : VMD_PEI_CONFIG
  • VmdMemBar1Base : VMD_PEI_CONFIG
  • VmdMemBar2Attr : VMD_PEI_CONFIG
  • VmdMemBar2Base : VMD_PEI_CONFIG
  • VmdMemBarSize1 : VMD_PEI_CONFIG
  • VmdMemBarSize2 : VMD_PEI_CONFIG
  • VmdPortBEnable : VMD_PEI_CONFIG
  • VmdPortCEnable : VMD_PEI_CONFIG
  • VmdPortDEnable : VMD_PEI_CONFIG
  • VmdPortEnable : VMD_PEI_CONFIG
  • VmxEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Voltage : FIVR_EXT_RAIL_CONFIG
  • VppAddress : PCH_PCIE_ROOT_PORT_CONFIG
  • VppPort : PCH_PCIE_ROOT_PORT_CONFIG
  • VppVoltage : MEMORY_CONFIGURATION
  • VrConfigEnable : CPU_POWER_MGMT_VR_CONFIG
  • VrPowerDeliveryDesign : CPU_POWER_MGMT_VR_CONFIG
  • VrVoltageLimit : CPU_POWER_MGMT_VR_CONFIG
  • VsysAssertionDeglitchMantissa : CPU_POWER_MGMT_VR_CONFIG
  • VsysFullScale : CPU_POWER_MGMT_VR_CONFIG
  • VtdDisable : VTD_CONFIG
  • VtdIgdEnable : VTD_CONFIG
  • VtdIopEnable : VTD_CONFIG
  • VtdIpuEnable : VTD_CONFIG
  • VttCompForVsshi : MEMORY_CONFIGURATION
  • VttTermination : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- w -

  • WakeConfig : PCH_PM_CONFIG
  • WakeGpioNo : CPU_PCIE_RTD3_GPIO
  • WakeOnTouch : THC_PORT
  • WatchDogEnabled : AMT_PEI_CONFIG
  • WatchDogTimerBios : AMT_PEI_CONFIG
  • WatchDogTimerOs : AMT_PEI_CONFIG
  • WeaklockEn : MEMORY_CONFIGURATION
  • WifiCore : CNVI_CONFIG
  • WolEnableOverride : PCH_WAKE_CONFIG
  • WolOvrWkSts : PCH_PM_CONFIG
  • WoWlanDeepSxEnable : PCH_WAKE_CONFIG
  • WoWlanEnable : PCH_WAKE_CONFIG
  • WrcFeatureEnable : SA_MISC_PEI_PREMEM_CONFIG
  • WRDS : MEMORY_CONFIGURATION
  • WRDSEQT : MEMORY_CONFIGURATION
  • WRDSUDT : MEMORY_CONFIGURATION
  • Write0 : MEMORY_CONFIGURATION
  • WriteMsr64 : SA_FUNCTION_CALLS
  • WriteOpcode : THC_HID_OVER_SPI
  • WriteThreshold : MEMORY_CONFIGURATION
  • WRSRT : MEMORY_CONFIGURATION
  • WRTC1D : MEMORY_CONFIGURATION
  • WRTC2D : MEMORY_CONFIGURATION
  • WRVC1D : MEMORY_CONFIGURATION
  • WRVC2D : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- x -

  • X2ApicOptOut : VTD_CONFIG
  • X2ApicSupport : CPU_CONFIG
  • XdciConfig : USB_CONFIG
  • XhciOcLock : USB_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- z -

  • ZpOdd : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- a -

  • AcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • AcousticNoiseMitigation : CPU_POWER_MGMT_VR_CONFIG
  • AcpiL6dPmeHandling : PCH_GENERAL_CONFIG
  • AcpiReservedMemoryBase : SA_MISC_PEI_PREMEM_CONFIG
  • AcpiReservedMemorySize : SA_MISC_PEI_PREMEM_CONFIG
  • AcsEnabled : TCSS_PCIE_PORT_POLICY
  • AcSplitLock : CPU_CONFIG
  • Active : CPU_PCIE_GPIO_INFO
  • ActiveCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveCoreCount1 : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveLtr : THC_PORT
  • ActiveSmallCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveSocNorthAtomCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • AdrEn : ADR_CONFIG
  • AdrHostPartitionReset : ADR_CONFIG
  • AdrMultiplier1Val : ADR_CONFIG
  • AdrMultiplier2Val : ADR_CONFIG
  • AdrPlatAckEn : ADR_CONFIG
  • AdrSrcOverride : ADR_CONFIG
  • AdrSrcSel : ADR_CONFIG
  • AdrTimer1Val : ADR_CONFIG
  • AdrTimer2Val : ADR_CONFIG
  • AdrTimerEn : ADR_CONFIG
  • AdvancedErrorReporting : TCSS_PCIE_PORT_POLICY
  • AesEnable : CPU_CONFIG
  • AetEnabled : TRACE_HUB_CONFIG
  • ALIASCHK : MEMORY_CONFIGURATION
  • AllocDescriptor : EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_STACK
  • AllowOppRefBelowWriteThrehold : MEMORY_CONFIGURATION
  • AlsEnable : GRAPHICS_DXE_CONFIG
  • AmtbxHotkeyPressed : AMT_DXE_CONFIG
  • AmtbxSelectionScreen : AMT_DXE_CONFIG
  • AmtEnabled : AMT_PEI_CONFIG
  • AmtKvmEnabled : AMT_PEI_CONFIG
  • AmtReportError : AMT_DXE_CONFIG
  • AmtSolEnabled : AMT_PEI_CONFIG
  • ApertureSize : GRAPHICS_PEI_PREMEM_CONFIG
  • ApplyConfigTdp : CPU_POWER_MGMT_BASIC_CONFIG
  • ApStartupBase : CPU_TXT_PREMEM_CONFIG
  • ArpEnable : PCH_SMBUS_PREMEM_CONFIG
  • Aspm : TCSS_PCIE_PORT_POLICY
  • Assignment : THC_PORT
  • AtomClusterRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2MaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • AtomPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomTurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • AtomTurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • Attributes : _CONFIG_BLOCK_HEADER , SERIAL_IO_UART_CONFIG
  • AudioLinkDmic : HDAUDIO_PREMEM_CONFIG
  • AudioLinkHda : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSndw : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSsp : HDAUDIO_PREMEM_CONFIG
  • AuthenticationStatus : EFI_HOB_FIRMWARE_VOLUME3
  • AutoFlow : SERIAL_IO_UART_ATTRIBUTES
  • AutoSelfRefreshSupport : MEMORY_CONFIGURATION
  • AuxOri : TCSS_IOM_ORI_OVERRIDE
  • AvailableSize : _CONFIG_BLOCK_TABLE_STRUCT
  • Avx2RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx2VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • Avx3Disable : CPU_CONFIG
  • Avx3RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx512VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • AvxDisable : CPU_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- b -

  • BacklightControlSupport : GRAPHICS_DXE_CONFIG
  • Bank : SA_ADDRESS_DECODE
  • BankGroup : SA_ADDRESS_DECODE
  • BaseAddress : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_UEFI_CAPSULE , VTD_CONFIG
  • BaseClassCode : PCIE_DEVICE_OVERRIDE
  • BaudRate : SERIAL_IO_UART_ATTRIBUTES
  • BclkAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • BClkFrequency : MEMORY_CONFIGURATION
  • BclkRfiFreq : MEMORY_CONFIGURATION
  • BclkSource : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BCLM : GRAPHICS_DXE_CONFIG
  • BdatEnable : SA_MISC_PEI_PREMEM_CONFIG
  • BdatTestType : SA_MISC_PEI_PREMEM_CONFIG
  • BgpdtHash : BIOS_GUARD_CONFIG
  • Bifurcation : PCH_PCIE_RP_PREMEM_CONFIG
  • BiosAcmBase : CPU_TXT_PREMEM_CONFIG
  • BiosAcmSize : CPU_TXT_PREMEM_CONFIG
  • BiosGuard : CPU_SECURITY_PREMEM_CONFIG
  • BiosGuardAttr : BIOS_GUARD_CONFIG
  • BiosGuardModulePtr : BIOS_GUARD_CONFIG
  • BiosGuardToolsInterface : CPU_SECURITY_PREMEM_CONFIG
  • BiosInterface : PCH_LOCK_DOWN_CONFIG
  • BiosInterfaceLock : RTC_CONFIG
  • BiosLock : PCH_LOCK_DOWN_CONFIG
  • BiosSize : CPU_SECURITY_PREMEM_CONFIG
  • BiProcHot : CPU_POWER_MGMT_TEST_CONFIG
  • BistOnReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BltBufferAddress : GRAPHICS_PEI_CONFIG
  • BltBufferSize : GRAPHICS_PEI_CONFIG
  • BmeMasterSlaveEnabled : PCH_ESPI_CONFIG
  • BootFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG
  • BootMode : EFI_HOB_HANDOFF_INFO_TABLE , SPD_OFFSET_TABLE
  • BtAudioOffload : CNVI_CONFIG
  • BtCore : CNVI_CONFIG
  • BypassFivrConfig : PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- c -

  • C0TransmitEnable : TS_GPIO_PIN_SETTING
  • C10DynamicThresholdAdjustment : PCH_PM_CONFIG
  • C1AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C1e : CPU_POWER_MGMT_TEST_CONFIG
  • C1UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • CallerId : FSP_ERROR_INFO_HOB
  • Cas : SA_ADDRESS_DECODE
  • CdClock : GRAPHICS_PEI_CONFIG
  • CdrRelock : CPU_PCIE_RP_PREMEM_CONFIG
  • CdynmaxClampEnable : GRAPHICS_PEI_CONFIG
  • Channel : SA_ADDRESS_DECODE
  • CheckPoint : SA_FUNCTION_CALLS
  • ChHashEnable : MEMORY_CONFIGURATION
  • ChHashInterleaveBit : MEMORY_CONFIGURATION
  • ChHashMask : MEMORY_CONFIGURATION
  • ChHashOverride : MEMORY_CONFIGURATION
  • CiraRequest : AMT_DXE_CONFIG
  • CiraTimeout : AMT_DXE_CONFIG
  • CleanMemory : MEMORY_CONFIG_NO_CRC
  • Clk : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • Clkreq : CNVI_PIN_MUX
  • ClkReq : PCH_PCIE_CLOCK
  • ClkReqMsgEnable : CPU_PCIE_RP_PREMEM_CONFIG
  • ClkReqMsgEnableRp : CPU_PCIE_RP_PREMEM_CONFIG
  • CLKTCO : MEMORY_CONFIGURATION
  • ClockGating : PCH_DMI_CONFIG
  • Cm : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CMDDRUD : MEMORY_CONFIGURATION
  • CMDDSEQ : MEMORY_CONFIGURATION
  • CmdMirror : MEMORY_CONFIGURATION
  • CmdRanksTerminated : MEMORY_CONFIGURATION
  • CMDSR : MEMORY_CONFIGURATION
  • CMDVC : MEMORY_CONFIGURATION
  • CodecSxWakeCapability : HDAUDIO_CONFIG
  • ComplianceTestMode : PCIE_COMMON_CONFIG
  • ComponentNameIndex : FIRMWARE_VERSION_INFO
  • ComputeDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ComputeDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ConfigTdpBios : CPU_POWER_MGMT_CUSTOM_CONFIG
  • ConfigTdpLevel : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_TEST_CONFIG
  • ConfigTdpLock : CPU_POWER_MGMT_CUSTOM_CONFIG
  • Controller : ISH_I3C_CONFIG , SA_ADDRESS_DECODE
  • CopyMem : SA_FUNCTION_CALLS
  • CoreMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • CorePllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreRatioExtensionMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfConfigScope : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • CorrectableErrorReport : TCSS_PCIE_PORT_POLICY
  • Count : FIRMWARE_VERSION_INFO_HOB
  • Cp : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CpuAttachedStorage : RST_CONFIG
  • CpuBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkPllOn : BCLK_CONFIG
  • CpuC10GatePinEnable : PCH_PM_CONFIG
  • CpuCrashLogDevice : TELEMETRY_PEI_PREMEM_CONFIG
  • CpuCrashLogEnable : TELEMETRY_PEI_CONFIG
  • Cpuid : PPM_CUSTOM_RATIO_TABLE
  • CpuMailboxRead : SA_FUNCTION_CALLS
  • CpuMailboxWrite : SA_FUNCTION_CALLS
  • CpuPcie0Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie1Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie2Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie3Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuRatio : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CpuReplacementTimeout : AMT_DXE_CONFIG
  • CpuStart : EFI_MMRAM_DESCRIPTOR
  • CrashLogEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CrashLogGprs : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Crid : PCH_GENERAL_CONFIG
  • CridEnable : SA_MISC_PEI_PREMEM_CONFIG
  • Cs : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • CseDataResilience : ME_PEI_CONFIG
  • CsEnable : ISH_SPI , SERIAL_IO_SPI_CONFIG
  • CsiSpeed : IPU_PREMEM_CONFIG
  • CsmFlag : SI_CONFIG
  • CsMode : SERIAL_IO_SPI_CONFIG
  • CsPolarity : SERIAL_IO_SPI_CONFIG
  • CsState : SERIAL_IO_SPI_CONFIG
  • CstateLatencyControl0Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CStatePreWake : CPU_POWER_MGMT_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : CPU_POWER_MGMT_TEST_CONFIG
  • CtrlRampTmr : FIVR_EXT_RAIL_CONFIG
  • Cts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • CustomConfigTdpTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomizedSsid : SI_CONFIG
  • CustomizedSvid : SI_CONFIG
  • CustomPowerLimit1 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit1Time : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit2 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CustomRatioTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomTurboActivationRatio : _PPM_CUSTOM_CTDP_TABLE
  • CwbEnable : PCH_DMI_CONFIG
  • Cx : CPU_POWER_MGMT_TEST_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- d -

  • D3ColdEnable : IOM_INTERFACE_CONFIG
  • D3HotEnable : IOM_INTERFACE_CONFIG
  • DataBits : SERIAL_IO_UART_ATTRIBUTES
  • DataDwords : HDA_VERB_TABLE_HEADER
  • DBG2 : SERIAL_IO_UART_CONFIG
  • DCC : MEMORY_CONFIGURATION
  • DciClkEnable : PCH_DCI_PREMEM_CONFIG
  • DciDbcMode : PCH_DCI_PREMEM_CONFIG
  • DciEn : PCH_DCI_PREMEM_CONFIG
  • DciModphyPg : PCH_DCI_PREMEM_CONFIG
  • DciUsb3TypecUfpDbg : PCH_DCI_PREMEM_CONFIG
  • DcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • DdiConfiguration : GRAPHICS_PEI_PREMEM_CONFIG
  • DdiPort1Ddc : DDI_CONFIGURATION
  • DdiPort1Hpd : DDI_CONFIGURATION
  • DdiPort2Ddc : DDI_CONFIGURATION
  • DdiPort2Hpd : DDI_CONFIGURATION
  • DdiPort3Ddc : DDI_CONFIGURATION
  • DdiPort3Hpd : DDI_CONFIGURATION
  • DdiPort4Ddc : DDI_CONFIGURATION
  • DdiPort4Hpd : DDI_CONFIGURATION
  • DdiPortADdc : DDI_CONFIGURATION
  • DdiPortAHpd : DDI_CONFIGURATION
  • DdiPortBConfig : DDI_CONFIGURATION
  • DdiPortBDdc : DDI_CONFIGURATION
  • DdiPortBHpd : DDI_CONFIGURATION
  • DdiPortCDdc : DDI_CONFIGURATION
  • DdiPortCHpd : DDI_CONFIGURATION
  • Ddr4DdpSharedClock : MEMORY_CONFIGURATION
  • Ddr4OneDpc : MEMORY_CONFIGURATION
  • DdrFreqLimit : MEMORY_CONFIGURATION
  • DdrRfim : CNVI_PREMEM_CONFIG
  • DebugHook : SA_FUNCTION_CALLS
  • DebugInterfaceEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugInterfaceLockEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugPrint : SA_FUNCTION_CALLS
  • DebugValue : MEMORY_CONFIGURATION
  • DefaultCsOutput : SERIAL_IO_SPI_CONFIG
  • DekelSquelchWa : CPU_PCIE_RP_PREMEM_CONFIG
  • DeltaT12PowerCycleDelay : GRAPHICS_PEI_PREMEM_CONFIG
  • DevEnConfig : TCSS_PEI_PREMEM_CONFIG
  • Device : PCH_DEVICE_INTERRUPT_CONFIG
  • DeviceId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • DeviceResetDelay : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • DevIntConfig : PCH_INTERRUPT_CONFIG
  • DevSlp : PCH_SATA_PORT_CONFIG
  • DevSlpResetConfig : PCH_SATA_PORT_CONFIG
  • DfdRestoreEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • DidInitStat : ME_PEI_PREMEM_CONFIG
  • Dimm : SA_ADDRESS_DECODE
  • DIMMDFE : MEMORY_CONFIGURATION
  • DIMMODTCA : MEMORY_CONFIGURATION
  • DIMMODTT : MEMORY_CONFIGURATION
  • DIMMRONT : MEMORY_CONFIGURATION
  • Direction : GPIO_CONFIG
  • DisableAndLock : PCH_WDT_PREMEM_CONFIG
  • DisableChannel : MEMORY_CONFIGURATION
  • DisableCpuReplacedPolling : ME_PEI_PREMEM_CONFIG
  • DisableD0I3SettingForHeci : ME_PEI_CONFIG
  • DisableDsxAcPresentPulldown : PCH_PM_CONFIG
  • DisableEnergyReport : PCH_PM_CONFIG
  • DisableMessageCheck : ME_PEI_PREMEM_CONFIG
  • DisableNativePowerButton : PCH_PM_CONFIG
  • DisablePerAtomMask : OVERCLOCKING_PREMEM_CONFIG
  • DisablePerCoreMask : OVERCLOCKING_PREMEM_CONFIG
  • DisableProcHotOut : CPU_POWER_MGMT_TEST_CONFIG
  • DisableTurboGt : GRAPHICS_PEI_CONFIG
  • DisableVrThermalAlert : CPU_POWER_MGMT_TEST_CONFIG
  • DismSize : GRAPHICS_PEI_PREMEM_CONFIG
  • DisPgCloseIdleTimeout : MEMORY_CONFIGURATION
  • DisplayAudioLink : GRAPHICS_PEI_PREMEM_CONFIG
  • DitoVal : PCH_SATA_PORT_CONFIG
  • DivU64x64 : SA_FUNCTION_CALLS
  • DlvrBypassModeEnable : OVERCLOCKING_PREMEM_CONFIG
  • DlvrRfiEnable : CPU_POWER_MGMT_VR_CONFIG
  • DlvrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • DlvrSpreadSpectrumPercentage : CPU_POWER_MGMT_VR_CONFIG
  • DmaBufferSize : VTD_CONFIG
  • DmaControlGuarantee : VTD_CONFIG
  • DmaEnable : SERIAL_IO_UART_CONFIG
  • DmiAspmCtrl : CPU_DMI_PREMEM_CONFIG , PCH_DMI_CONFIG
  • DmiAspmL1ExitLatency : CPU_DMI_PREMEM_CONFIG
  • DmicClockSelect : HDA_LINK_DMIC
  • DmiCdrRelock : CPU_DMI_PREMEM_CONFIG
  • DmiDeEmphasis : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3DsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3EndPointHint : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3EndPointPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3EqPh2Enable : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3EqPh3Method : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3ProgramStaticEq : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3RootPortPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RxCtlePeaking : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiGen3UsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiHaAWC : THERMAL_CONFIG
  • DmiMaxLinkSpeed : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • DmiNewFom : CPU_DMI_PREMEM_CONFIG
  • DmiPowerReduction : PCH_DMI_CONFIG
  • DmiTsawEn : DMI_HW_WIDTH_CONTROL
  • DmVal : PCH_SATA_PORT_CONFIG
  • DpcEnabled : TCSS_PCIE_PORT_POLICY
  • DqDqsMap : MEMORY_CONFIG_NO_CRC
  • DqMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DqPinsInterleaved : MEMORY_CONFIGURATION
  • DqsMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DRAMDCA : MEMORY_CONFIGURATION
  • DspEnable : HDAUDIO_PREMEM_CONFIG
  • DspFeatureMask : HDAUDIO_DXE_CONFIG
  • DspUaaCompliance : HDAUDIO_PREMEM_CONFIG
  • DualTauBoost : CPU_POWER_MGMT_BASIC_CONFIG
  • DynamicMemoryBoost : MEMORY_CONFIGURATION
  • DynamicPowerGating : PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- e -

  • EccDftEn : MEMORY_CONFIGURATION
  • EccErrInjAddress : MEMORY_CONFIGURATION
  • EccErrInjCount : MEMORY_CONFIGURATION
  • EccErrInjMask : MEMORY_CONFIGURATION
  • EcCmdLock : BIOS_GUARD_CONFIG
  • EcCmdProvisionEav : BIOS_GUARD_CONFIG
  • EccSupport : MEMORY_CONFIGURATION
  • ECT : MEMORY_CONFIGURATION
  • EfiEndOfHobList : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiFreeMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryBottom : EFI_HOB_HANDOFF_INFO_TABLE
  • EfiMemoryTop : EFI_HOB_HANDOFF_INFO_TABLE
  • EightCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Eist : CPU_POWER_MGMT_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • Enable : GBE_CONFIG , HDA_LINK_DMIC , HDA_LINK_HDA , HDA_LINK_SNDW , HDA_LINK_SSP , HDAUDIO_PREMEM_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_SPI , ISH_UART , PCH_MEMORY_THROTTLING , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SATA_CONFIG , TSN_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • Enable8254ClockGating : PCH_IOAPIC_CONFIG
  • Enable8254ClockGatingOnS3 : PCH_IOAPIC_CONFIG
  • EnableAllThermalFunctions : CPU_POWER_MGMT_TEST_CONFIG
  • EnableC6Dram : CPU_SECURITY_PREMEM_CONFIG
  • EnableDitoConfig : PCH_SATA_PORT_CONFIG
  • EnableDmaBuffer : VTD_CONFIG
  • EnabledStates : FIVR_EXT_RAIL_CONFIG
  • EnableEpbPeciOverride : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableFastMsrHwpReq : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoEppGrouping : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoPerCorePstate : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbm : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbmDriver : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableMinVoltageOverride : CPU_POWER_MGMT_VR_CONFIG
  • EnableMode : TRACE_HUB_CONFIG
  • EnablePerCorePState : CPU_POWER_MGMT_BASIC_CONFIG
  • EnablePort8xhDecode : PCIE_COMMON_CONFIG
  • EnablePwrDn : MEMORY_CONFIGURATION
  • EnablePwrDnLpddr : MEMORY_CONFIGURATION
  • EnableSgx : CPU_SECURITY_PREMEM_CONFIG
  • EnableTcssCovTypeA : TCSS_MISC_PEI_CONFIG
  • EnableVsysCritical : CPU_POWER_MGMT_VR_CONFIG
  • EnclosureSupport : SATA_CONFIG
  • EnCmdRate : MEMORY_CONFIGURATION
  • End : SPD_OFFSET_TABLE
  • EndOfPostMessage : ME_PEI_CONFIG
  • EndPointAspm : PCIE_DEVICE_OVERRIDE
  • EnergyEfficientPState : CPU_POWER_MGMT_TEST_CONFIG
  • EnergyEfficientTurbo : CPU_POWER_MGMT_TEST_CONFIG
  • EnforceEDebugMode : ME_PEI_CONFIG
  • EnhancedInterleave : MEMORY_CONFIGURATION
  • EntryPoint : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • EpgEnable : MEMORY_CONFIGURATION
  • EqPh23Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3LaneParam : CPU_PCIE_CONFIG
  • ERDMPRTC2D : MEMORY_CONFIGURATION
  • ERDTC2D : MEMORY_CONFIGURATION
  • ErrorType : FSP_ERROR_INFO_HOB
  • EsataSpeedLimit : SATA_CONFIG
  • EspiPmHAE : PCH_ESPI_CONFIG
  • Etvb : OVERCLOCKING_PREMEM_CONFIG
  • EWRTC2D : MEMORY_CONFIGURATION
  • ExitOnFailure : MEMORY_CONFIGURATION
  • ExpanderNo : CPU_PCIE_GPIO_INFO
  • ExtendedBankHashing : MEMORY_CONFIGURATION
  • External : PCH_SATA_PORT_CONFIG
  • ExtractedFv : EFI_HOB_FIRMWARE_VOLUME3
  • ExtSync : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG
  • ExtTemperatureSupport : MEMORY_CONFIGURATION
  • ExtV1p05Rail : PCH_FIVR_CONFIG
  • ExtVnnRail : PCH_FIVR_CONFIG
  • ExtVnnRailSx : PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- f -

  • FastPkgCRampDisable : CPU_POWER_MGMT_VR_CONFIG
  • FatalErrorReport : TCSS_PCIE_PORT_POLICY
  • FClkFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG
  • FiaProgramming : CPU_PCIE_CONFIG
  • FileName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FirstDimmBitMask : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FirstDimmBitMaskEcc : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FiveCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FivrDynPm : PCH_FIVR_CONFIG
  • FivrEfficiency : OVERCLOCKING_PREMEM_CONFIG
  • FivrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpectrumEnable : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpreadSpectrum : CPU_POWER_MGMT_VR_CONFIG
  • Flags : THC_HID_OVER_SPI
  • FllOcModeEn : OVERCLOCKING_PREMEM_CONFIG
  • FllOverclockMode : OVERCLOCKING_PREMEM_CONFIG
  • FomsCp : CPU_PCIE_ROOT_PORT_CONFIG
  • Force1Dpc : MEMORY_CONFIGURATION
  • ForceLtrOverride : PCIE_DEVICE_OVERRIDE , TCSS_PCIE_PORT_POLICY
  • ForceSingleRank : MEMORY_CONFIGURATION
  • ForceSingleSubchannel : MEMORY_CONFIGURATION
  • ForcMebxSyncUp : AMT_PEI_CONFIG
  • FourCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FreqLimitMixedConfig : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_2R2R : MEMORY_CONFIGURATION
  • Frequency : THC_HID_OVER_SPI
  • Function : PCH_DEVICE_INTERRUPT_CONFIG
  • FvName : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3
  • FwProgress : AMT_PEI_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- g -

  • GearRatio : MEMORY_CONFIGURATION
  • Gen3Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen3Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4EqPh3Method : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • GetCpuTime : SA_FUNCTION_CALLS
  • GetMemoryVdd : SA_FUNCTION_CALLS
  • GetPciDeviceAddress : SA_FUNCTION_CALLS
  • GetPcieDeviceAddress : SA_FUNCTION_CALLS
  • GetRandomNumber : SA_FUNCTION_CALLS
  • GetRtcCmos : SA_FUNCTION_CALLS
  • GetRtcTime : SA_FUNCTION_CALLS
  • GetSpdData : SA_FUNCTION_CALLS
  • GfxTurboIMON : GRAPHICS_DXE_CONFIG
  • GlobalResetMasksOverride : PCH_PM_CONFIG
  • GlobalSmi : PCH_LOCK_DOWN_CONFIG
  • GmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GmAdr64 : GRAPHICS_PEI_PREMEM_CONFIG
  • GnaEnable : GNA_CONFIG
  • GopVersion : GRAPHICS_DXE_CONFIG
  • GpioIrqRoute : PCH_INTERRUPT_CONFIG
  • GpioNo : CPU_PCIE_GPIO_INFO
  • GpioOverride : PCH_GENERAL_PREMEM_CONFIG
  • GpioPullN : IOM_AUX_ORI_PAD_CONFIG
  • GpioPullP : IOM_AUX_ORI_PAD_CONFIG
  • GpioSupport : CPU_PCIE_RTD3_GPIO
  • GraphicsConfigPtr : GRAPHICS_PEI_CONFIG
  • GtCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • GtClosEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • GtExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • GtFreqMax : GRAPHICS_PEI_CONFIG
  • GtIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • GtMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtPsmiSupport : GRAPHICS_PEI_PREMEM_CONFIG
  • GttMmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GttSize : GRAPHICS_PEI_PREMEM_CONFIG
  • GtVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • GuidHob : _CONFIG_BLOCK_HEADER , FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- h -

  • HardwareRemappedStorageConfig : RST_CONFIG
  • HdAudioLinkFrequency : HDAUDIO_CONFIG
  • HdcControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HddUnlock : RST_CONFIG
  • Header : _CONFIG_BLOCK , _CONFIG_BLOCK_TABLE_STRUCT , _PEI_ITBT_CONFIG , ADR_CONFIG , AMT_DXE_CONFIG , AMT_PEI_CONFIG , BCLK_CONFIG , BIOS_GUARD_CONFIG , CNVI_CONFIG , CNVI_PREMEM_CONFIG , CPU_CONFIG , CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_CONFIG , CPU_PCIE_RP_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , CPU_TRACE_HUB_PREMEM_CONFIG , CPU_TXT_PREMEM_CONFIG , EFI_HOB_CPU , EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME , EFI_HOB_GUID_TYPE , EFI_HOB_HANDOFF_INFO_TABLE , EFI_HOB_MEMORY_ALLOCATION , EFI_HOB_MEMORY_ALLOCATION_BSP_STORE , EFI_HOB_MEMORY_ALLOCATION_MODULE , EFI_HOB_MEMORY_ALLOCATION_STACK , EFI_HOB_MEMORY_POOL , EFI_HOB_RESOURCE_DESCRIPTOR , EFI_HOB_UEFI_CAPSULE , FIRMWARE_VERSION_INFO_HOB , GBE_CONFIG , GNA_CONFIG , GRAPHICS_DXE_CONFIG , GRAPHICS_PEI_CONFIG , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , HYBRID_STORAGE_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_I3C_CONFIG , ISH_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG , MEMORY_CONFIG_NO_CRC , MEMORY_CONFIGURATION , OVERCLOCKING_PREMEM_CONFIG , PCH_DCI_PREMEM_CONFIG , PCH_DMI_CONFIG , PCH_ESPI_CONFIG , PCH_FIVR_CONFIG , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_LOCK_DOWN_CONFIG , PCH_P2SB_CONFIG , PCH_PCIE_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG , PCH_WDT_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PREMEM_CONFIG , PCIE_RP_DXE_CONFIG , PSF_CONFIG , RST_CONFIG , RTC_CONFIG , SA_MISC_PEI_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_CONFIG , SERIAL_IO_CONFIG , SI_CONFIG , SI_PREMEM_CONFIG , TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG , THC_CONFIG , THERMAL_CONFIG , TSN_CONFIG , USB2_PHY_CONFIG , USB3_HSIO_CONFIG , USB_CONFIG , VMD_PEI_CONFIG , VTD_CONFIG , VTD_DXE_CONFIG
  • Heci1BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci2BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3Enabled : ME_PEI_CONFIG
  • HeciCommunication2 : ME_PEI_PREMEM_CONFIG
  • HeciFullTrace : ME_PEI_PREMEM_CONFIG
  • HeciTimeouts : ME_PEI_PREMEM_CONFIG
  • HgDelayAfterHoldReset : HYBRID_GRAPHICS_CONFIG
  • HgDelayAfterPwrEn : HYBRID_GRAPHICS_CONFIG
  • HgMode : HYBRID_GRAPHICS_CONFIG
  • HgSubSystemId : HYBRID_GRAPHICS_CONFIG
  • HgSupport : HYBRID_GRAPHICS_CONFIG
  • HideUnConfigureMeConfirm : AMT_DXE_CONFIG
  • HidOverSpi : THC_PORT
  • HobBufferSize : MEMORY_CONFIGURATION
  • HobLength : EFI_HOB_GENERIC_HEADER
  • HobType : EFI_HOB_GENERIC_HEADER
  • HoldRst : CPU_PCIE_RTD3_GPIO
  • HorizontalResolution : GRAPHICS_PEI_CONFIG
  • HostC10ReportEnable : PCH_ESPI_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • HotPlug : PCH_SATA_PORT_CONFIG
  • HsiiEnable : USB_CONFIG
  • HsioCtrlAdaptOffsetCfg : HSIO_PARAMETERS
  • HsioCtrlAdaptOffsetCfgEnable : HSIO_PARAMETERS
  • HsioFilterSelN : HSIO_PARAMETERS
  • HsioFilterSelNEnable : HSIO_PARAMETERS
  • HsioFilterSelP : HSIO_PARAMETERS
  • HsioFilterSelPEnable : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnRes : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnResEnable : HSIO_PARAMETERS
  • HsioTxDeEmph : HSIO_PARAMETERS
  • HsioTxDeEmphEnable : HSIO_PARAMETERS
  • HsioTxDownscaleAmp : HSIO_PARAMETERS
  • HsioTxDownscaleAmpEnable : HSIO_PARAMETERS
  • HsioTxRate0UniqTran : HSIO_PARAMETERS
  • HsioTxRate0UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate1UniqTran : HSIO_PARAMETERS
  • HsioTxRate1UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate2UniqTran : HSIO_PARAMETERS
  • HsioTxRate2UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate3UniqTran : HSIO_PARAMETERS
  • HsioTxRate3UniqTranEnable : HSIO_PARAMETERS
  • HslOri : TCSS_IOM_ORI_OVERRIDE
  • HwEqGen3CoeffList : PCIE_COMMON_CONFIG
  • HwEqGen4CoeffList : CPU_PCIE_CONFIG
  • Hwp : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpInterruptControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpLock : CPU_POWER_MGMT_BASIC_CONFIG
  • HybridStorageMode : HYBRID_STORAGE_CONFIG
  • HyperThreading : CPU_CONFIG_LIB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- i -

  • I2cDeviceConfig : SERIAL_IO_CONFIG
  • IaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • IaIccMax : OVERCLOCKING_PREMEM_CONFIG
  • IaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • IaSirpEnable : OVERCLOCKING_PREMEM_CONFIG
  • Ibecc : MEMORY_CONFIGURATION
  • IbeccErrInjAddress : MEMORY_CONFIGURATION
  • IbeccErrInjControl : MEMORY_CONFIGURATION
  • IbeccErrInjCount : MEMORY_CONFIGURATION
  • IbeccErrInjMask : MEMORY_CONFIGURATION
  • IbeccOperationMode : MEMORY_CONFIGURATION
  • IbeccProtectedRangeBase : MEMORY_CONFIGURATION
  • IbeccProtectedRangeEnable : MEMORY_CONFIGURATION
  • IbeccProtectedRangeMask : MEMORY_CONFIGURATION
  • IccLimit : CPU_POWER_MGMT_VR_CONFIG
  • IccMax : CPU_POWER_MGMT_VR_CONFIG , FIVR_EXT_RAIL_CONFIG
  • IccMaximum : FIVR_EXT_RAIL_CONFIG
  • Idd3n : MEMORY_CONFIGURATION
  • Idd3p : MEMORY_CONFIGURATION
  • IDispCodecDisconnect : HDAUDIO_PREMEM_CONFIG
  • IDispLinkFrequency : HDAUDIO_PREMEM_CONFIG
  • IDispLinkTmode : HDAUDIO_PREMEM_CONFIG
  • IdleLtr : THC_PORT
  • IedSize : SA_MISC_PEI_PREMEM_CONFIG
  • IgdBlcConfig : GRAPHICS_DXE_CONFIG
  • IgdBootType : GRAPHICS_DXE_CONFIG
  • IgdDvmt50PreAlloc : GRAPHICS_PEI_PREMEM_CONFIG
  • IgdDvmtMemSize : GRAPHICS_DXE_CONFIG
  • IgdPanelScaling : GRAPHICS_DXE_CONFIG
  • IgdPanelType : GRAPHICS_DXE_CONFIG
  • ImguClkOutEn : IPU_PREMEM_CONFIG
  • ImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • ImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • ImrEnabled : PCIE_IMR_CONFIG
  • ImrRpLocation : PCIE_IMR_CONFIG
  • ImrRpSelection : PCIE_IMR_CONFIG
  • ImrSize : PCIE_IMR_CONFIG
  • InfDfxPwrEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • InitPcieAspmAfterOprom : PCIE_PEI_PREMEM_CONFIG
  • InputReportBodyAddress : THC_HID_OVER_SPI
  • InputReportHeaderAddress : THC_HID_OVER_SPI
  • Instance : FSP_ERROR_INFO_HOB
  • InterlockSw : PCH_SATA_PORT_CONFIG
  • InternalGraphics : GRAPHICS_PEI_PREMEM_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • InterruptPinMuxing : THC_PORT
  • IntPing : SA_XDCI_IRQ_INT_CONFIG
  • IntX : PCH_DEVICE_INTERRUPT_CONFIG
  • IoApicEntry24_119 : PCH_IOAPIC_CONFIG
  • IoApicId : PCH_IOAPIC_CONFIG
  • IoeDebugEn : PCH_GENERAL_PREMEM_CONFIG
  • IomAuxPortPad : TCSS_IOM_PEI_CONFIG
  • IomBeforeEnteringTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IomConfig : TCSS_PEI_CONFIG
  • IomInterface : TCSS_IOM_PEI_CONFIG
  • IomStayInTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IoRead16 : SA_FUNCTION_CALLS
  • IoRead32 : SA_FUNCTION_CALLS
  • IoRead8 : SA_FUNCTION_CALLS
  • IotgPllSscEn : PCH_GENERAL_PREMEM_CONFIG
  • IoWrite16 : SA_FUNCTION_CALLS
  • IoWrite32 : SA_FUNCTION_CALLS
  • IoWrite8 : SA_FUNCTION_CALLS
  • IpuEnable : IPU_PREMEM_CONFIG
  • IpuImrConfiguration : IPU_PREMEM_CONFIG
  • Irms : CPU_POWER_MGMT_VR_CONFIG
  • Irq : PCH_DEVICE_INTERRUPT_CONFIG , SA_XDCI_IRQ_INT_CONFIG
  • Irrt : RST_CONFIG
  • IrrtOnly : RST_CONFIG
  • ITbtConnectTopologyTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtDmaLtr : _PEI_ITBT_CONFIG
  • ITbtForcePowerOnTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtGenericConfig : _PEI_ITBT_CONFIG
  • ITbtPcieRootPortEn : _ITBT_ROOTPORT_CONFIG
  • ITbtPcieTunnelingForUsb4 : _ITBT_GENERIC_CONFIG
  • ITbtRootPortConfig : _PEI_ITBT_CONFIG
  • ITbtSecurityLevel : _ITBT_GENERIC_CONFIG
  • ItdThrottleEnable : OVERCLOCKING_PREMEM_CONFIG
  • IuerStatusVal : GRAPHICS_DXE_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- j -

  • JtagC10PowerGateDisable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • JWRL : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- k -

  • KeepEarlyTrace : PCH_DCI_PREMEM_CONFIG
  • KtDeviceEnable : ME_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- l -

  • L1RpCtl : PCH_DMI_CONFIG
  • L1sCommonModeRestoreTime : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnScale : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnValue : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapMask : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapOffset : PCIE_DEVICE_OVERRIDE
  • LaneUsed : IPU_PREMEM_CONFIG
  • LanWakeFromDeepSx : PCH_WAKE_CONFIG
  • LatchEventsC10Exit : PCH_PM_CONFIG
  • LCT : MEMORY_CONFIGURATION
  • LctCmdEyeWidth : MEMORY_CONFIGURATION
  • LedEnable : SATA_CONFIG
  • LedLocate : RST_CONFIG
  • LeftShift64 : SA_FUNCTION_CALLS
  • LegacyIoLowLatency : PCH_GENERAL_CONFIG
  • LegacyOrom : RST_CONFIG
  • Length : EFI_HOB_FIRMWARE_VOLUME2 , EFI_HOB_FIRMWARE_VOLUME3 , EFI_HOB_FIRMWARE_VOLUME
  • Lfsr0Mask : MEMORY_CONFIGURATION
  • Lfsr1Mask : MEMORY_CONFIGURATION
  • LgmrEnable : PCH_ESPI_CONFIG
  • LimitPacketSize : THC_PORT
  • LinkDownGpios : CPU_PCIE_RP_PREMEM_CONFIG
  • LocalTransmitterOverrideEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • LockConfig : GPIO_CONFIG
  • LockLinkConfiguration : PCH_ESPI_CONFIG
  • LockPTMregs : SA_MISC_PEI_PREMEM_CONFIG
  • LogoPixelHeight : GRAPHICS_PEI_CONFIG
  • LogoPixelWidth : GRAPHICS_PEI_CONFIG
  • LogoPtr : GRAPHICS_PEI_CONFIG
  • LogoSize : GRAPHICS_PEI_CONFIG
  • LowToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • Lp5BankMode : MEMORY_CONFIGURATION
  • Lp5CccConfig : MEMORY_CONFIGURATION
  • LpddrRttCa : MEMORY_CONFIGURATION
  • LpddrRttWr : MEMORY_CONFIGURATION
  • LpDqsOscEn : MEMORY_CONFIGURATION
  • LpMode : MEMORY_CONFIGURATION
  • LpmS0ixSubStateEnable : PCH_PM_CONFIG
  • LtrConfigLock : TCSS_PCIE_PORT_POLICY
  • LtrEnable : GBE_CONFIG , TCSS_PCIE_PORT_POLICY
  • LtrHighIdleTimeOverride : USB_CONFIG
  • LtrLowIdleTimeOverride : USB_CONFIG
  • LtrMaxNoSnoopLatency : TCSS_PCIE_PORT_POLICY
  • LtrMaxSnoopLatency : TCSS_PCIE_PORT_POLICY
  • LtrMediumIdleTimeOverride : USB_CONFIG
  • LtrOverrideEnable : USB_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- m -

  • MachineCheckEnable : CPU_TEST_CONFIG
  • ManageabilityMode : AMT_PEI_CONFIG
  • MappingPchXhciUsbA : TCSS_MISC_PEI_CONFIG
  • MarginLimitCheck : MEMORY_CONFIGURATION
  • MarginLimitL2 : MEMORY_CONFIGURATION
  • MaxRatio : PPM_CUSTOM_RATIO_TABLE
  • MaxRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MaxRttWr : MEMORY_CONFIGURATION
  • McPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • McRefresh2X : MEMORY_CONFIGURATION
  • McRefreshRate : MEMORY_CONFIGURATION
  • MctpBroadcastCycle : ME_PEI_CONFIG
  • MebxDebugMsg : AMT_DXE_CONFIG
  • MebxGraphicsMode : AMT_DXE_CONFIG
  • MebxNonUiTextMode : AMT_DXE_CONFIG
  • MebxUiTextMode : AMT_DXE_CONFIG
  • MemoryAllocationHeader : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • MemoryBaseAddress : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLength : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemoryLock : RTC_CONFIG
  • MemoryThrottling : THERMAL_CONFIG
  • MemoryType : EFI_HOB_MEMORY_ALLOCATION_HEADER
  • MemReg0Size : TRACE_HUB_CONFIG
  • MemTestOnWarmBoot : MEMORY_CONFIG_NO_CRC
  • MEMTST : MEMORY_CONFIGURATION
  • MeUnconfigOnRtcClear : ME_PEI_CONFIG
  • MeWakeSts : PCH_PM_CONFIG
  • MicrocodePatchAddress : CPU_CONFIG
  • MinRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MinVoltageC8 : CPU_POWER_MGMT_VR_CONFIG
  • MinVoltageRuntime : CPU_POWER_MGMT_VR_CONFIG
  • MiscConfig : TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG
  • Miso : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MlcSpatialPrefetcher : CPU_TEST_CONFIG
  • MlcStreamerPrefetcher : CPU_TEST_CONFIG
  • MmioRead16 : SA_FUNCTION_CALLS
  • MmioRead32 : SA_FUNCTION_CALLS
  • MmioRead64 : SA_FUNCTION_CALLS
  • MmioRead8 : SA_FUNCTION_CALLS
  • MmioWrite16 : SA_FUNCTION_CALLS
  • MmioWrite32 : SA_FUNCTION_CALLS
  • MmioWrite64 : SA_FUNCTION_CALLS
  • MmioWrite8 : SA_FUNCTION_CALLS
  • MmramReservedSize : _EFI_MM_RESERVED_MMRAM_REGION
  • MmramReservedStart : _EFI_MM_RESERVED_MMRAM_REGION
  • MobilePlatform : MEMORY_CONFIGURATION
  • Mode : CNVI_CONFIG , IEH_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG , THC_PORT
  • ModPhySusPgEnable : PCH_PM_CONFIG
  • ModuleName : EFI_HOB_MEMORY_ALLOCATION_MODULE
  • MonitorMwaitEnable : CPU_TEST_CONFIG
  • Mosi : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MrcCall : MEMORY_CONFIG_NO_CRC
  • MrcChangeMargin : SA_MEMORY_FUNCTIONS
  • MrcChannelExist : SA_MEMORY_FUNCTIONS
  • MrcDelayNs : SA_FUNCTION_CALLS
  • MrcDramReset : SA_FUNCTION_CALLS
  • MrcFastBoot : MEMORY_CONFIGURATION
  • MrcPrintf : SA_MEMORY_FUNCTIONS
  • MrcReturnFromSmc : SA_FUNCTION_CALLS
  • MrcSafeConfig : MEMORY_CONFIGURATION
  • MrcSignExtend : SA_MEMORY_FUNCTIONS
  • MrcTimeMeasure : MEMORY_CONFIGURATION
  • MrcUpdateVref : SA_MEMORY_FUNCTIONS
  • MsHashEnable : MEMORY_CONFIGURATION
  • MsHashInterleaveBit : MEMORY_CONFIGURATION
  • MsHashMask : MEMORY_CONFIGURATION
  • MsiInterrupt : ISH_CONFIG
  • MultiVcEnable : TSN_CONFIG
  • MultiVcEnabled : CPU_PCIE_ROOT_PORT_CONFIG
  • MultU64x32 : SA_FUNCTION_CALLS
  • MvcEnabled : PCH_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- n -

  • Name : EFI_HOB_GUID_TYPE , EFI_HOB_MEMORY_ALLOCATION_HEADER
  • NewFeatureEnable1 : MEMORY_CONFIGURATION
  • NewFeatureEnable2 : MEMORY_CONFIGURATION
  • NewFom : CPU_PCIE_RP_PREMEM_CONFIG
  • NModeSupport : MEMORY_CONFIGURATION
  • NoFatalErrorReport : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatency : PCIE_DEVICE_OVERRIDE
  • NonSnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • NumberOfBlocks : _CONFIG_BLOCK_TABLE_STRUCT
  • NumberOfEntries : PPM_CUSTOM_RATIO_TABLE
  • NumberOfSsidTableEntry : SI_CONFIG
  • NumOfDevIntConfig : PCH_INTERRUPT_CONFIG
  • NumRsvdSmbusAddresses : PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- o -

  • OcLock : OVERCLOCKING_PREMEM_CONFIG
  • OcSupport : OVERCLOCKING_PREMEM_CONFIG
  • OemResolutionSettingsRsvd : AMT_DXE_CONFIG
  • OemT12DelayOverride : GRAPHICS_PEI_PREMEM_CONFIG
  • OffToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • OneCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • OpRomScanTempMmioBar : SA_MISC_PEI_PREMEM_CONFIG
  • OpRomScanTempMmioLimit : SA_MISC_PEI_PREMEM_CONFIG
  • OptaneMemory : RST_CONFIG
  • OromUiBanner : RST_CONFIG
  • OromUiDelay : RST_CONFIG
  • OsIdleEnable : PCH_PM_CONFIG
  • OtherSettings : GPIO_CONFIG
  • OutputReportAddress : THC_HID_OVER_SPI
  • OutputState : GPIO_CONFIG
  • OverCurrentEnable : USB_CONFIG
  • OverCurrentPin : USB2_PORT_CONFIG , USB3_PORT_CONFIG
  • OverrideConfig : PCIE_DEVICE_OVERRIDE
  • Owner : EFI_HOB_RESOURCE_DESCRIPTOR
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- p -

  • P0T1M : SATA_THERMAL_THROTTLING
  • P0T2M : SATA_THERMAL_THROTTLING
  • P0T3M : SATA_THERMAL_THROTTLING
  • P0TDisp : SATA_THERMAL_THROTTLING
  • P0TDispFinit : SATA_THERMAL_THROTTLING
  • P0Tinact : SATA_THERMAL_THROTTLING
  • P1T1M : SATA_THERMAL_THROTTLING
  • P1T2M : SATA_THERMAL_THROTTLING
  • P1T3M : SATA_THERMAL_THROTTLING
  • P1TDisp : SATA_THERMAL_THROTTLING
  • P1TDispFinit : SATA_THERMAL_THROTTLING
  • P1Tinact : SATA_THERMAL_THROTTLING
  • PadMode : GPIO_CONFIG
  • PadTermination : ISH_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG
  • PanelPowerEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • Parity : SERIAL_IO_UART_ATTRIBUTES
  • PavpEnable : GRAPHICS_PEI_CONFIG
  • PCETTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PchCrossThrottling : THERMAL_THROTTLE_LEVELS
  • PchDeepSxPol : PCH_PM_CONFIG
  • PchHotEnable : THERMAL_CONFIG
  • PchHotLevel : THERMAL_CONFIG
  • PchPciePort8xhDecodePortIndex : PCH_PCIE_CONFIG
  • PchPwrCycDur : PCH_PM_CONFIG
  • PchSlpAMinAssert : PCH_PM_CONFIG
  • PchSlpS3MinAssert : PCH_PM_CONFIG
  • PchSlpS4MinAssert : PCH_PM_CONFIG
  • PchSlpSusMinAssert : PCH_PM_CONFIG
  • PciData : MEMORY_CONFIGURATION
  • PcieClock : PCH_PCIE_RP_PREMEM_CONFIG
  • PcieCommonConfig : PCH_PCIE_CONFIG
  • PcieDeviceOverrideTablePtr : CPU_PCIE_CONFIG , PCIE_RP_DXE_CONFIG
  • PcieImr : PCIE_PREMEM_CONFIG
  • PcieLinkEqMethod : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieLinkEqMode : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieMultipleSegmentEnabled : TCSS_MISC_PEI_PREMEM_CONFIG
  • PciePllSsc : PCH_PM_CONFIG
  • PciePolicy : TCSS_PEI_CONFIG
  • PcieRpCommonConfig : CPU_PCIE_ROOT_PORT_CONFIG
  • PcieSpeed : CPU_PCIE_RP_PREMEM_CONFIG
  • PcieWakeFromDeepSx : PCH_WAKE_CONFIG
  • PciIndex : MEMORY_CONFIGURATION
  • PDA : MEMORY_CONFIGURATION
  • PdoProgramming : USB_CONFIG
  • PdtUnlock : ISH_CONFIG
  • PeciC10Reset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • PeciSxReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • PegGen3EndPointHint : CPU_PCIE_EQ_LANE_PARAM
  • PegGen3EndPointPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen3ProgramStaticEq : CPU_PCIE_CONFIG
  • PegGen3RootPortPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4EndPointHint : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4EndPointPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4ProgramStaticEq : CPU_PCIE_CONFIG
  • PegGen4RootPortPreset : CPU_PCIE_EQ_LANE_PARAM
  • Pehalfbit : USB2_PHY_PARAMETERS
  • PeiGraphicsPeimInit : GRAPHICS_PEI_CONFIG
  • PeiPolicyInit : _PEI_SI_DEFAULT_POLICY_INIT_PPI
  • PeiPreMemPolicyInit : _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  • PerAtomClusterVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerBankRefresh : MEMORY_CONFIGURATION
  • PerCoreHtDisable : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreRatioOverride : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerformanceLimitation : THC_PORT
  • PeriodicDcc : MEMORY_CONFIGURATION
  • Petxiset : USB2_PHY_PARAMETERS
  • Ph1DownstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph1UpstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph2LocalTransmitterOverridePreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3CoefficientsList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3NumberOfPresetsOrCoefficients : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3PresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PhysicalSize : EFI_MMRAM_DESCRIPTOR
  • PhysicalStart : EFI_HOB_RESOURCE_DESCRIPTOR , EFI_MMRAM_DESCRIPTOR
  • PinMux : CNVI_CONFIG , HDA_LINK_DMIC , ISH_GPIO_CONFIG , SERIAL_IO_I2C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG
  • PinSelection : TS_GPIO_PIN_SETTING
  • PkgCStateDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateLimit : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateUnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PlatformConfig : GRAPHICS_DXE_CONFIG
  • PlatformDebugConsent : SI_PREMEM_CONFIG
  • PlatformMemorySize : MEMORY_CONFIG_NO_CRC
  • PllMaxBandingRatio : OVERCLOCKING_PREMEM_CONFIG
  • PmcDbgMsgEn : PCH_PM_CONFIG
  • PmcInterface : TCSS_IOM_PEI_CONFIG
  • PmcPdEnable : PMC_INTERFACE_CONFIG
  • Pme : HDAUDIO_CONFIG
  • PmeB0S5Dis : PCH_WAKE_CONFIG
  • PmgCstCfgCtrlLock : CPU_POWER_MGMT_TEST_CONFIG
  • PmodeClkEn : PCH_GENERAL_PREMEM_CONFIG
  • PmSupport : GRAPHICS_PEI_CONFIG
  • PmsyncEnable : TS_GPIO_PIN_SETTING
  • Port : USB2_PHY_CONFIG , USB3_HSIO_CONFIG
  • Port80Route : PCH_GENERAL_PREMEM_CONFIG
  • PortResetMessageEnable : USB2_PORT_CONFIG
  • PortSettings : SATA_CONFIG
  • PortUsb20 : USB_CONFIG
  • PortUsb30 : USB_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerDownMode : MEMORY_CONFIGURATION
  • PowerGating : SERIAL_IO_UART_CONFIG
  • PowerGatingSupported : HDAUDIO_PREMEM_CONFIG
  • PowerLimit1 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit1Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2Power : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3DutyCycle : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PpinSupport : CPU_CONFIG
  • PpmIrmSetting : CPU_POWER_MGMT_TEST_CONFIG
  • PprEnable : MEMORY_CONFIGURATION
  • PreBootDmaMask : VTD_CONFIG
  • Predeemp : USB2_PHY_PARAMETERS
  • PreWake : CPU_POWER_MGMT_VR_CONFIG
  • PrimaryDisplay : GRAPHICS_PEI_PREMEM_CONFIG
  • PrmrrSize : CPU_SECURITY_PREMEM_CONFIG
  • ProbelessTrace : MEMORY_CONFIGURATION
  • ProcessorTraceEnable : CPU_TEST_CONFIG
  • ProcessorTraceMemSize : CPU_TEST_CONFIG
  • ProcessorTraceOutputScheme : CPU_TEST_CONFIG
  • ProcHotLock : CPU_POWER_MGMT_TEST_CONFIG
  • ProcHotResponse : CPU_POWER_MGMT_TEST_CONFIG
  • ProgramGtChickenBits : GRAPHICS_PEI_CONFIG
  • PS1toPS0CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0MCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1MCoef : CPU_POWER_MGMT_VR_CONFIG
  • Psi1Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi2Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Enable : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi4Enable : CPU_POWER_MGMT_VR_CONFIG
  • PsmiRegionSize : GRAPHICS_PEI_PREMEM_CONFIG
  • PsOnEnable : PCH_PM_CONFIG
  • PsysOffset : CPU_POWER_MGMT_VR_CONFIG
  • PsysOffset1 : CPU_POWER_MGMT_VR_CONFIG
  • PsysPmax : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Time : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysSlope : CPU_POWER_MGMT_VR_CONFIG
  • PtmEnabled : TCSS_PCIE_PORT_POLICY
  • PvdMode : OVERCLOCKING_PREMEM_CONFIG
  • PvdRatioThreshold : OVERCLOCKING_PREMEM_CONFIG
  • PVTTDNLP : MEMORY_CONFIGURATION
  • PwdwnIdleCounter : MEMORY_CONFIGURATION
  • PwrBtnOverridePeriod : PCH_PM_CONFIG
  • PwrEnable : CPU_PCIE_RTD3_GPIO
  • PwrOptEnable : PCH_DMI_CONFIG , SATA_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- r -

  • RaceToHalt : CPU_POWER_MGMT_TEST_CONFIG
  • Raid0 : RST_CONFIG
  • Raid1 : RST_CONFIG
  • Raid10 : RST_CONFIG
  • Raid5 : RST_CONFIG
  • RaidDeviceId : SATA_CONFIG
  • RampDown : CPU_POWER_MGMT_VR_CONFIG
  • RampUp : CPU_POWER_MGMT_VR_CONFIG
  • Rank : SA_ADDRESS_DECODE
  • RankInterleave : MEMORY_CONFIGURATION
  • Ras : SA_ADDRESS_DECODE
  • Ratio : MEMORY_CONFIGURATION
  • RC1pFreqEnable : GRAPHICS_PEI_CONFIG
  • RcompData : MEMORY_CONFIG_NO_CRC
  • RcompResistor : SA_MEMORY_RCOMP
  • RcompTarget : SA_MEMORY_RCOMP
  • RCVENC1D : MEMORY_CONFIGURATION
  • RCVET : MEMORY_CONFIGURATION
  • RDAPT : MEMORY_CONFIGURATION
  • RDEQT : MEMORY_CONFIGURATION
  • RDMPRT : MEMORY_CONFIGURATION
  • RDODTT : MEMORY_CONFIGURATION
  • RDTC1D : MEMORY_CONFIGURATION
  • RDTC2D : MEMORY_CONFIGURATION
  • RDVC1D : MEMORY_CONFIGURATION
  • RDVC2D : MEMORY_CONFIGURATION
  • RDVREFDC : MEMORY_CONFIGURATION
  • ReadMsr64 : SA_FUNCTION_CALLS
  • ReadOpcode : THC_HID_OVER_SPI
  • RealtimeMemoryFrequency : MEMORY_CONFIGURATION
  • RealtimeMemoryTiming : OVERCLOCKING_PREMEM_CONFIG
  • RefClk : MEMORY_CONFIGURATION
  • Refresh2X : MEMORY_CONFIGURATION
  • RefreshHpWm : MEMORY_CONFIGURATION
  • RefreshPanicWm : MEMORY_CONFIGURATION
  • RefreshWm : MEMORY_CONFIGURATION
  • RegionState : EFI_MMRAM_DESCRIPTOR
  • RemapEnable : MEMORY_CONFIGURATION
  • RemoteAssistance : AMT_PEI_CONFIG
  • RemotePresetCoeffoverride : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • RenderStandby : GRAPHICS_PEI_CONFIG
  • Reserved : _CONFIG_BLOCK_HEADER , _ITBT_GENERIC_CONFIG , _ITBT_ROOTPORT_CONFIG , BIOS_GUARD_CONFIG , CPU_SECURITY_PREMEM_CONFIG , EFI_HOB_CPU , EFI_HOB_GENERIC_HEADER , EFI_HOB_MEMORY_ALLOCATION_HEADER , GRAPHICS_DXE_CONFIG , HDA_LINK_HDA , PMC_LPM_S0IX_SUB_STATE_EN , TCSS_IOM_PEI_CONFIG , THC_PORT , VTD_CONFIG
  • Reserved0 : CPU_CONFIG
  • Reserved1 : SA_MISC_PEI_PREMEM_CONFIG
  • Reserved11 : MEMORY_CONFIG_NO_CRC
  • Reserved274 : MEMORY_CONFIGURATION
  • Reserved3 : SPD_OFFSET_TABLE
  • Reserved336 : MEMORY_CONFIGURATION
  • ReservedBits1 : CPU_POWER_MGMT_BASIC_CONFIG
  • ReservedBits2 : MEMORY_CONFIGURATION
  • ResetAux : CPU_SECURITY_PREMEM_CONFIG
  • ResetPad : THC_HID_OVER_SPI
  • ResetPadTrigger : THC_HID_OVER_SPI
  • ResetWaitTimer : HDAUDIO_PREMEM_CONFIG
  • ResourceAttribute : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceLength : EFI_HOB_RESOURCE_DESCRIPTOR
  • ResourceType : EFI_HOB_RESOURCE_DESCRIPTOR
  • RetrainOnFastFail : MEMORY_CONFIGURATION
  • RetToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RetToLowCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • ReuseAdlSDdr5Board : MEMORY_CONFIGURATION
  • RevId : PCIE_DEVICE_OVERRIDE
  • Revision : _CONFIG_BLOCK_HEADER
  • RevisionId : HDA_VERB_TABLE_HEADER
  • RfiMitigation : CPU_POWER_MGMT_VR_CONFIG
  • RfReset : CNVI_PIN_MUX
  • RhSelect : MEMORY_CONFIGURATION
  • RightShift64 : SA_FUNCTION_CALLS
  • RingDownBin : OVERCLOCKING_PREMEM_CONFIG
  • RingMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointCount : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • RMC : MEMORY_CONFIGURATION
  • RMT : MEMORY_CONFIGURATION
  • RMTBIT : MEMORY_CONFIGURATION
  • RMTLoopCount : MEMORY_CONFIGURATION
  • RmtPerTask : MEMORY_CONFIGURATION
  • RootPort : CPU_PCIE_CONFIG
  • RootPortIndex : HYBRID_GRAPHICS_CONFIG
  • RpDpcExtensionsEnabled : TCSS_PCIE_PORT_POLICY
  • RpEnabledMask : CPU_PCIE_RP_PREMEM_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG
  • RpFunctionSwap : PCIE_COMMON_CONFIG
  • RstPcieStoragePort : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • Rsvd : CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , TCSS_MISC_PEI_CONFIG , TCSS_MISC_PEI_PREMEM_CONFIG , TCSS_USBTC_PEI_PERMEM_CONFIG
  • Rsvd0 : _CONFIG_BLOCK_TABLE_STRUCT , CPU_DMI_EQ_PARAM , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_GPIO_INFO , CPU_PCIE_RTD3_GPIO , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , PCH_DMI_EQ_PARAM , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_EQ_PARAM , PCIE_PEI_PREMEM_CONFIG , PPM_CUSTOM_RATIO_TABLE , THERMAL_THROTTLE_LEVELS , TSN_CONFIG
  • Rsvd1 : GRAPHICS_PEI_CONFIG , PCH_PM_CONFIG
  • Rsvd2 : GRAPHICS_PEI_PREMEM_CONFIG
  • Rsvd5 : CPU_POWER_MGMT_VR_CONFIG
  • RsvdBits : _PPM_CUSTOM_CTDP_TABLE , AMT_DXE_CONFIG , AMT_PEI_CONFIG , CPU_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , GPIO_CONFIG , HDAUDIO_PREMEM_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG
  • Rsvdbits : PCH_DMI_CONFIG
  • RsvdBits : PCH_ESPI_CONFIG
  • Rsvdbits : PCH_P2SB_CONFIG
  • RsvdBits : SI_PREMEM_CONFIG
  • RsvdBits0 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , GBE_CONFIG , GNA_CONFIG , HDAUDIO_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_UART , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_LOCK_DOWN_CONFIG , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_COMMON_CONFIG , PCIE_PEI_PREMEM_CONFIG , PSF_CONFIG , RST_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_THERMAL_THROTTLING , USB2_PORT_CONFIG , USB3_PORT_CONFIG , USB_CONFIG , XDCI_CONFIG
  • RsvdBits1 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , FIVR_EXT_RAIL_CONFIG , PCH_IOAPIC_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • RsvdBits2 : FIVR_EXT_RAIL_CONFIG
  • RsvdByte2 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte3 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte4 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte5 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte6 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdBytes : PCH_PCIE_CLOCK , SI_PREMEM_CONFIG
  • RsvdBytes0 : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG , SI_CONFIG
  • RsvdBytes1 : SI_CONFIG
  • RsvdBytes2 : SI_CONFIG
  • RsvdField0 : ISH_SPI
  • RsvdO64B25to31 : MEMORY_CONFIGURATION
  • RsvdSmbusAddressTable : PCH_SMBUS_PREMEM_CONFIG
  • RTL : MEMORY_CONFIGURATION
  • Rts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • Rx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RxPolarity : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- s -

  • S0i2p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p3En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p4En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0ixAutoDemotion : PCH_PM_CONFIG
  • S3DataPtr : SA_MISC_PEI_PREMEM_CONFIG
  • SaCall : MEMORY_CONFIG_NO_CRC
  • SaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • SaExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • SafeMode : MEMORY_CONFIGURATION
  • SaGv : MEMORY_CONFIGURATION
  • SaGvFreq : MEMORY_CONFIGURATION
  • SaGvGear : MEMORY_CONFIGURATION
  • SagvHeuristicsDownControl : MEMORY_CONFIGURATION
  • SagvHeuristicsUpControl : MEMORY_CONFIGURATION
  • SagvSwitchFactorGT : MEMORY_CONFIGURATION
  • SagvSwitchFactorIA : MEMORY_CONFIGURATION
  • SagvSwitchFactorIO : MEMORY_CONFIGURATION
  • SagvSwitchFactorStall : MEMORY_CONFIGURATION
  • SalpSupport : SATA_CONFIG
  • SaPllFreqOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SataMode : SATA_CONFIG
  • SataPmPtm : PCH_SATA_PORT_CONFIG
  • SataRstInterrupt : SATA_CONFIG
  • SaVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaXdci : TCSS_MISC_PEI_CONFIG
  • SbAccessUnlock : PCH_P2SB_CONFIG
  • ScanExtGfxForLegacyOpRom : SA_MISC_PEI_PREMEM_CONFIG
  • SciIrqSelect : PCH_INTERRUPT_CONFIG
  • Scl : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • ScramblerSupport : MEMORY_CONFIGURATION
  • Sda : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • SdiEnable : HDA_LINK_HDA
  • SdiNum : HDA_VERB_TABLE_HEADER
  • SendDidMsg : ME_PEI_PREMEM_CONFIG
  • SendEcCmd : BIOS_GUARD_CONFIG
  • SendVrMbxCmd : CPU_POWER_MGMT_VR_CONFIG
  • SerialDebugLevel : MEMORY_CONFIG_NO_CRC
  • SetMem : SA_FUNCTION_CALLS
  • SetMemDword : SA_FUNCTION_CALLS
  • SetMemoryPmicVoltage : SA_FUNCTION_CALLS
  • SetMemoryVdd : SA_FUNCTION_CALLS
  • SetMemWord : SA_FUNCTION_CALLS
  • SetSecuredRegisterLock : CPU_PCIE_CONFIG
  • SevenCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • SgpioSupport : SATA_CONFIG
  • SharedZqPin : MEMORY_CONFIGURATION
  • ShiftPiCommandTrain : SA_MEMORY_FUNCTIONS
  • SimicsFlag : MEMORY_CONFIGURATION
  • SinitMemorySize : CPU_TXT_PREMEM_CONFIG
  • SixCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Size : GRAPHICS_DXE_CONFIG , MEMORY_CONFIGURATION
  • SizeOfIoSpace : EFI_HOB_CPU
  • SizeOfMemorySpace : EFI_HOB_CPU
  • SkipBiosDoneWhenFwUpdate : SI_CONFIG
  • SkipCdClockInit : GRAPHICS_PEI_CONFIG
  • SkipCpuReplacementCheck : ME_PEI_PREMEM_CONFIG
  • SkipExtGfxScan : SA_MISC_PEI_PREMEM_CONFIG
  • SkipFspGop : GRAPHICS_PEI_CONFIG
  • SkipMbpHob : ME_PEI_PREMEM_CONFIG
  • SkipMpInit : CPU_CONFIG
  • SkipOverrideBootModeWhenFwUpdate : SI_PREMEM_CONFIG
  • SkipSetBootPState : CPU_POWER_MGMT_BASIC_CONFIG
  • SkipSsidProgramming : SI_CONFIG
  • SkipStopPbet : CPU_SECURITY_PREMEM_CONFIG
  • SlotNumber : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitScale : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitValue : TCSS_PCIE_PORT_POLICY
  • SlotSelection : CPU_PCIE_CONFIG
  • SlowSlewRate : CPU_POWER_MGMT_VR_CONFIG
  • SlpLanLowDc : PCH_PM_CONFIG
  • SlpStrchSusUp : PCH_PM_CONFIG
  • SmartStorage : RST_CONFIG
  • SmbAlertEnable : PCH_SMBUS_PREMEM_CONFIG
  • SmbiosData : FIRMWARE_VERSION_INFO_HOB
  • SmbiosType4MaxSpeedOverride : CPU_CONFIG
  • SmbusBar : SA_MISC_PEI_PREMEM_CONFIG
  • SmbusIoBase : PCH_SMBUS_PREMEM_CONFIG
  • SmbusRead16 : SA_FUNCTION_CALLS
  • SmbusRead8 : SA_FUNCTION_CALLS
  • SmbusWrite16 : SA_FUNCTION_CALLS
  • SmbusWrite8 : SA_FUNCTION_CALLS
  • SmramMask : MEMORY_CONFIGURATION
  • SndwConfig : HDAUDIO_DXE_CONFIG
  • SnoopLatency : PCIE_DEVICE_OVERRIDE
  • SnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • SocBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • SocBclkPllOn : BCLK_CONFIG
  • SocDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SocDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SolidStateDrive : PCH_SATA_PORT_CONFIG
  • SOT : MEMORY_CONFIGURATION
  • SpdAddressTable : SA_MISC_PEI_PREMEM_CONFIG
  • SpdData : MEMORY_CONFIG_NO_CRC , SPD_DATA_BUFFER
  • SpdProfileSelected : MEMORY_CONFIGURATION
  • SpdWriteDisable : PCH_SMBUS_PREMEM_CONFIG
  • SpeedLimit : SATA_CONFIG
  • SpiDeviceConfig : SERIAL_IO_CONFIG
  • SpiEiss : PCH_LOCK_DOWN_CONFIG
  • SpinUp : PCH_SATA_PORT_CONFIG
  • SrefCfgEna : MEMORY_CONFIGURATION
  • SrefCfgIdleTmr : MEMORY_CONFIGURATION
  • SsidTablePtr : SI_CONFIG
  • Start : SPD_OFFSET_TABLE
  • StateRatio : PPM_CUSTOM_RATIO_TABLE
  • StateRatioMax16 : PPM_CUSTOM_RATIO_TABLE
  • Status : FSP_ERROR_INFO_HOB
  • StopBits : SERIAL_IO_UART_ATTRIBUTES
  • SubClassCode : PCIE_DEVICE_OVERRIDE
  • SubSystemIds : HDAUDIO_PREMEM_CONFIG
  • SuggestedSetting : DMI_HW_WIDTH_CONTROL , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS
  • SupportedVoltageStates : FIVR_EXT_RAIL_CONFIG
  • SystemErrorEnable : PCH_PCIE_ROOT_PORT_CONFIG
  • SystemErrorOnCorrectableError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnFatalError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnNonFatalError : TCSS_PCIE_PORT_POLICY
  • SystemMemoryLength : SA_MISC_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- t -

  • T0Level : THERMAL_THROTTLE_LEVELS
  • T1Level : THERMAL_THROTTLE_LEVELS
  • T2Level : THERMAL_THROTTLE_LEVELS
  • TableHeader : _SI_POLICY_STRUCT , _SI_PREMEM_POLICY_STRUCT
  • TAT : MEMORY_CONFIGURATION
  • TccActivationOffset : CPU_POWER_MGMT_BASIC_CONFIG
  • tCCD_L : MEMORY_CONFIGURATION
  • TccEnable : PSF_CONFIG
  • TccOffsetClamp : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetTimeWindowForRatl : CPU_POWER_MGMT_BASIC_CONFIG
  • tCL : MEMORY_CONFIGURATION
  • TcoIrqEnable : PCH_INTERRUPT_CONFIG
  • TcoIrqSelect : PCH_INTERRUPT_CONFIG
  • TcssDevEn : TCSS_DEVEN_PEI_PREMEM_CONFIG
  • TcStateLimit : TCSS_IOM_PEI_CONFIG
  • tCWL : MEMORY_CONFIGURATION
  • TdcCurrentLimit : CPU_POWER_MGMT_VR_CONFIG
  • TdcEnable : CPU_POWER_MGMT_VR_CONFIG
  • TdcLock : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow1 : CPU_POWER_MGMT_VR_CONFIG
  • TestMode : SATA_CONFIG
  • tFAW : MEMORY_CONFIGURATION
  • TgaSize : CPU_TXT_PREMEM_CONFIG
  • ThcPort : THC_CONFIG
  • ThermalMonitor : CPU_POWER_MGMT_TEST_CONFIG
  • ThermalThrottling : SATA_CONFIG
  • ThermTimerDelay : PCH_PM_CONFIG
  • ThreeCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • ThreeStrikeCounterDisable : CPU_TEST_CONFIG
  • ThrtCkeMinDefeat : MEMORY_CONFIGURATION
  • ThrtCkeMinDefeatLpddr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmrLpddr : MEMORY_CONFIGURATION
  • TimedMwait : CPU_POWER_MGMT_TEST_CONFIG
  • TjMaxOffset : OVERCLOCKING_PREMEM_CONFIG
  • TmeEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • TraceHub : CPU_TRACE_HUB_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG
  • TrainTrace : MEMORY_CONFIGURATION
  • tRAS : MEMORY_CONFIGURATION
  • tRCDtRP : MEMORY_CONFIGURATION
  • tREFI : MEMORY_CONFIGURATION
  • tRFC : MEMORY_CONFIGURATION
  • tRFC2 : MEMORY_CONFIGURATION
  • tRFC4 : MEMORY_CONFIGURATION
  • tRFCpb : MEMORY_CONFIGURATION
  • tRRD : MEMORY_CONFIGURATION
  • tRRD_L : MEMORY_CONFIGURATION
  • tRRD_S : MEMORY_CONFIGURATION
  • tRTP : MEMORY_CONFIGURATION
  • TS0TW : DMI_HW_WIDTH_CONTROL
  • TS1TW : DMI_HW_WIDTH_CONTROL
  • TS2TW : DMI_HW_WIDTH_CONTROL
  • TS3TW : DMI_HW_WIDTH_CONTROL
  • TscDisableHwFixup : OVERCLOCKING_PREMEM_CONFIG
  • TsegSize : SA_MISC_PEI_PREMEM_CONFIG
  • TsGpioPinSetting : PCH_MEMORY_THROTTLING
  • TsLockTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • TsnLinkSpeed : TSN_CONFIG
  • TsnMacAddressHigh : TSN_CONFIG
  • TsnMacAddressLow : TSN_CONFIG
  • TStates : CPU_POWER_MGMT_TEST_CONFIG
  • TTEnable : THERMAL_THROTTLE_LEVELS
  • TTLevels : THERMAL_CONFIG
  • TTLock : THERMAL_THROTTLE_LEVELS
  • TTState13Enable : THERMAL_THROTTLE_LEVELS
  • TurboMode : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboPowerLimitLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • TvbDownBinsTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbDownBinsTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbRatioClipping : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbVoltageOptimization : OVERCLOCKING_PREMEM_CONFIG
  • TwoCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • tWR : MEMORY_CONFIGURATION
  • tWTR : MEMORY_CONFIGURATION
  • tWTR_L : MEMORY_CONFIGURATION
  • tWTR_S : MEMORY_CONFIGURATION
  • Tx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • TXDQSDCC : MEMORY_CONFIGURATION
  • Txiset : USB2_PHY_PARAMETERS
  • Txt : CPU_SECURITY_PREMEM_CONFIG
  • TxtAcheckRequest : CPU_SECURITY_PREMEM_CONFIG
  • TXTCO : MEMORY_CONFIGURATION
  • TXTCODQS : MEMORY_CONFIGURATION
  • TxtDprMemoryBase : CPU_TXT_PREMEM_CONFIG
  • TxtDprMemorySize : CPU_TXT_PREMEM_CONFIG
  • TxtEnable : CPU_CONFIG
  • TxtHeapMemorySize : CPU_TXT_PREMEM_CONFIG
  • TxtImplemented : SA_MISC_PEI_PREMEM_CONFIG
  • TxtLcpPdBase : CPU_TXT_PREMEM_CONFIG
  • TxtLcpPdSize : CPU_TXT_PREMEM_CONFIG
  • Type : FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- u -

  • UaolEnable : USB_CONFIG
  • UartDeviceConfig : SERIAL_IO_CONFIG
  • UnConfigureMe : AMT_DXE_CONFIG
  • UnlimitedIccMax : OVERCLOCKING_PREMEM_CONFIG
  • UnlockGpioPads : PCH_LOCK_DOWN_CONFIG
  • UnsupportedRequestReport : TCSS_PCIE_PORT_POLICY
  • Usage : PCH_PCIE_CLOCK
  • Usb2PhySusPgEnable : PCH_PM_CONFIG
  • Usb4CmMode : _ITBT_GENERIC_CONFIG
  • UsbConfig : TCSS_PEI_CONFIG
  • UsbOverride : IOM_INTERFACE_CONFIG
  • UsbProvision : AMT_DXE_CONFIG
  • UsbTcConfig : TCSS_PEI_PREMEM_CONFIG
  • UsbTcPortEn : TCSS_USBTC_PEI_PERMEM_CONFIG
  • UserBd : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • UserBudgetEnable : MEMORY_CONFIGURATION
  • UserThresholdEnable : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- v -

  • V1p05IsExtFetControlEn : PCH_PM_CONFIG
  • V1p05PhyExtFetControlEn : PCH_PM_CONFIG
  • Value : FSP_ERROR_INFO_HOB
  • VbtAddress : GRAPHICS_DXE_CONFIG
  • Vc1ReadMeter : MEMORY_CONFIGURATION
  • VCCDLLBP : MEMORY_CONFIGURATION
  • VccinAux : PCH_FIVR_CONFIG
  • VccInAuxImonIccImax : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionCapacitanceInUf : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionEnable : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionQuiescentPowerInMw : CPU_POWER_MGMT_VR_CONFIG
  • VccSt : IOM_INTERFACE_CONFIG
  • VcType : HDAUDIO_PREMEM_CONFIG
  • VDDQT : MEMORY_CONFIGURATION
  • VddqVoltage : MEMORY_CONFIGURATION
  • VddSettleWaitTime : MEMORY_CONFIGURATION
  • VddVoltage : MEMORY_CONFIGURATION
  • VendorId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • VerbTableEntryNum : HDAUDIO_CONFIG
  • VerbTablePtr : HDAUDIO_CONFIG
  • Version : EFI_HOB_HANDOFF_INFO_TABLE , FIRMWARE_VERSION_INFO
  • VersionStringIndex : FIRMWARE_VERSION_INFO
  • VerticalResolution : GRAPHICS_PEI_CONFIG
  • VmdCfgBarAttr : VMD_PEI_CONFIG
  • VmdCfgBarBase : VMD_PEI_CONFIG
  • VmdCfgBarSize : VMD_PEI_CONFIG
  • VmdEnable : VMD_PEI_CONFIG
  • VmdGlobalMapping : VMD_PEI_CONFIG
  • VmdMemBar1Attr : VMD_PEI_CONFIG
  • VmdMemBar1Base : VMD_PEI_CONFIG
  • VmdMemBar2Attr : VMD_PEI_CONFIG
  • VmdMemBar2Base : VMD_PEI_CONFIG
  • VmdMemBarSize1 : VMD_PEI_CONFIG
  • VmdMemBarSize2 : VMD_PEI_CONFIG
  • VmdPortBEnable : VMD_PEI_CONFIG
  • VmdPortCEnable : VMD_PEI_CONFIG
  • VmdPortDEnable : VMD_PEI_CONFIG
  • VmdPortEnable : VMD_PEI_CONFIG
  • VmxEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Voltage : FIVR_EXT_RAIL_CONFIG
  • VppAddress : PCH_PCIE_ROOT_PORT_CONFIG
  • VppPort : PCH_PCIE_ROOT_PORT_CONFIG
  • VppVoltage : MEMORY_CONFIGURATION
  • VrConfigEnable : CPU_POWER_MGMT_VR_CONFIG
  • VrPowerDeliveryDesign : CPU_POWER_MGMT_VR_CONFIG
  • VrVoltageLimit : CPU_POWER_MGMT_VR_CONFIG
  • VsysAssertionDeglitchMantissa : CPU_POWER_MGMT_VR_CONFIG
  • VsysFullScale : CPU_POWER_MGMT_VR_CONFIG
  • VtdDisable : VTD_CONFIG
  • VtdIgdEnable : VTD_CONFIG
  • VtdIopEnable : VTD_CONFIG
  • VtdIpuEnable : VTD_CONFIG
  • VttCompForVsshi : MEMORY_CONFIGURATION
  • VttTermination : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- w -

  • WakeConfig : PCH_PM_CONFIG
  • WakeGpioNo : CPU_PCIE_RTD3_GPIO
  • WakeOnTouch : THC_PORT
  • WatchDogEnabled : AMT_PEI_CONFIG
  • WatchDogTimerBios : AMT_PEI_CONFIG
  • WatchDogTimerOs : AMT_PEI_CONFIG
  • WeaklockEn : MEMORY_CONFIGURATION
  • WifiCore : CNVI_CONFIG
  • WolEnableOverride : PCH_WAKE_CONFIG
  • WolOvrWkSts : PCH_PM_CONFIG
  • WoWlanDeepSxEnable : PCH_WAKE_CONFIG
  • WoWlanEnable : PCH_WAKE_CONFIG
  • WrcFeatureEnable : SA_MISC_PEI_PREMEM_CONFIG
  • WRDS : MEMORY_CONFIGURATION
  • WRDSEQT : MEMORY_CONFIGURATION
  • WRDSUDT : MEMORY_CONFIGURATION
  • Write0 : MEMORY_CONFIGURATION
  • WriteMsr64 : SA_FUNCTION_CALLS
  • WriteOpcode : THC_HID_OVER_SPI
  • WriteThreshold : MEMORY_CONFIGURATION
  • WRSRT : MEMORY_CONFIGURATION
  • WRTC1D : MEMORY_CONFIGURATION
  • WRTC2D : MEMORY_CONFIGURATION
  • WRVC1D : MEMORY_CONFIGURATION
  • WRVC2D : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- x -

  • X2ApicOptOut : VTD_CONFIG
  • X2ApicSupport : CPU_CONFIG
  • XdciConfig : USB_CONFIG
  • XhciOcLock : USB_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Class Members - Variables

- z -

  • ZpOdd : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File List

File List
Here is a list of all documented files with brief descriptions:
AdrConfig.h | ADR policy
AmtConfig.h | AMT Config Block for PEI/DXE phase
Base.h | Root include file for Mde Package Base type modules
BiosGuardConfig.h | CPU BIOS Guard Config Block
CnviConfig.h | CNVi policy
ConfigBlock.h | Header file for Config Block Lib implementation
ConfigBlockLib.h | Header file for Config Block Lib implementation
CpuConfig.h | CPU Config Block
CpuConfigLibPreMemConfig.h | CPU Security PreMemory Config Block
CpuDmiPreMemConfig.h | DMI policy
CpuPcieConfig.h | Pcie root port policy
CpuPowerMgmtBasicConfig.h | CPU Power Management Basic Config Block
CpuPowerMgmtCustomConfig.h | CPU Power Managment Custom Config Block
CpuPowerMgmtPsysConfig.h | CPU Power Management Psys(Platform) Config Block
CpuPowerMgmtTestConfig.h | CPU Power Management Test Config Block
CpuPowerMgmtVrConfig.h | CPU Power Management VR Config Block
CpuSecurityPreMemConfig.h | CPU Security PreMemory Config Block
CpuTestConfig.h | CPU Test Config Block
CpuTxtConfig.h | CPU TXT PreMemory Config Block
DciConfig.h | Dci policy
EspiConfig.h | Espi policy
FirmwareVersionInfoHob.h | Header file for Firmware Version Information
FivrConfig.h | PCH FIVR policy
FspErrorInfo.h | FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios
FspFixedPcds.h | This file lists all FixedAtBuild PCDs referenced in FSP integration guide
FspInfoHob.h | Header file for FSP Information HOB
FspmArchConfigPpi.h | Header file for FSP-M Arch Config PPI
GbeConfig.h | Gigabit Ethernet policy
GnaConfig.h | Policy definition for GNA Config Block
GpioConfig.h | Header file for GpioConfig structure used by GPIO library
GpioSampleDef.h | Copyright (c) 2015 - 2021, Intel Corporation
GraphicsConfig.h | Policy definition for Internal Graphics Config Block
HdAudioConfig.h | HDAUDIO policy
HybridGraphicsConfig.h | Hybrid Graphics policy definitions
HybridStorageConfig.h | Hybrid Storage policy
IehConfig.h | Integrated Error Handler policy
InterruptConfig.h | Interrupt policy
IoApicConfig.h | IoApic policy
IpuPreMemConfig.h | IPU policy definitions
IshConfig.h | ISH policy
LockDownConfig.h | Lock down policy
MemoryConfig.h | Policy definition of Memory Config Block
MePeiConfig.h | ME config block for PEI phase
MpServices.h | This file declares UEFI PI Multi-processor PPI
OverclockingConfig.h | Overclocking Config Block
P2sbConfig.h | P2sb policy
PchDmiConfig.h | DMI policy
PchGeneralConfig.h | PCH General policy
PchPcieRpConfig.h | PCH Pcie root port policy
PcieConfig.h | PCIe Config Block
PciePreMemConfig.h | PCIe Config Block PreMem
PeiITbtConfig.h | Header file for TBT PEI Policy
PeiITbtGenericStructure.h | ITBT Policy definition to be referred in both PEI and DXE phase
PeiPreMemSiDefaultPolicy.h | This file defines the function to initialize default silicon policy PPI
PeiSiDefaultPolicy.h | This file defines the function to initialize default silicon policy PPI
PiHob.h | HOB related definitions in PI
PiMultiPhase.h | Include file matches things in PI for multiple module types
PmConfig.h | Power Management policy
PsfConfig.h | Primary Sideband Fabric policy
RstConfig.h | Rst policy
RtcConfig.h | RTC policy
SaMiscPeiConfig.h | Policy details for miscellaneous configuration in System Agent
SaMiscPeiPreMemConfig.h | Policy details for miscellaneous configuration in System Agent
SataConfig.h | Sata policy
SerialIoConfig.h | Serial IO policy
SerialIoDevices.h | Serial IO policy
SiConfig.h | Si Config Block
SiPolicyStruct.h | Intel reference code configuration policies
SiPreMemConfig.h | Si Config Block PreMem
SmbusConfig.h | Smbus policy
TcssPeiConfig.h | TCSS PEI policy
TcssPeiPreMemConfig.h | TCSS PEI PreMem policy
TelemetryPeiConfig.h | Configurations for Telemetry
ThcConfig.h | Touch Host Controller policy
ThermalConfig.h | Thermal policy
TraceHubConfig.h | Configurations for TraceHub
TsnConfig.h | TSN Config policy
UefiBaseType.h | Defines data types and constants introduced in UEFI
Usb2PhyConfig.h | USB2 PHY configuration policy
Usb3HsioConfig.h | USB3 Mod PHY configuration policy
UsbConfig.h | Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI
VmdPeiConfig.h | VMD PEI policy
VtdConfig.h | VT-d policy definitions
WatchDogConfig.h | WatchDog policy
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AdrConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Classes
AdrConfig.h File Reference

ADR policy. More...

#include <ConfigBlock.h>
Include dependency graph for AdrConfig.h:

Go to the source code of this file.

Classes

union | ADR_SOURCE_ENABLE
ADR Source Enable. More...
struct | ADR_CONFIG
ADR Configuration Revision 1: - Initial version. More...

Detailed Description

ADR policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AdrConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AdrConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
AdrConfig.h
Go to the documentation of this file.
1 /** @file
2 ADR policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ADR_CONFIG_H_
36 #define _ADR_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define ADR_CONFIG_REVISION 1
41 extern EFI_GUID gAdrConfigGuid;
42
43 #pragma pack (push,1)
44
45 typedef enum {
46 AdrScale1us,
47 AdrScale10us,
48 AdrScale100us,
49 AdrScale1ms,
50 AdrScale10ms,
51 AdrScale100ms,
52 AdrScale1s,
53 AdrScale10s
54 } ADR_TIMER_SCALE;
55
56 /**
57 ADR Source Enable
58 **/
59 typedef union {
60 struct {
61 UINT32 Reserved1 : 1;
62 UINT32 AdrSrcPbo : 1;
63 UINT32 AdrSrcPmcUncErr : 1;
64 UINT32 AdrSrcPchThrm : 1;
65 UINT32 AdrSrcMePbo : 1;
66 UINT32 AdrSrcCpuThrm : 1;
67 UINT32 AdrSrcMegbl : 1;
68 UINT32 AdrSrcLtReset : 1;
69 UINT32 AdrSrcPmcWdt : 1;
70 UINT32 AdrSrcMeWdt : 1;
71 UINT32 AdrSrcPmcFw : 1;
72 UINT32 AdrSrcPchpwrFlr : 1;
73 UINT32 AdrSrcSyspwrFlr : 1;
74 UINT32 Reserved2 : 1;
75 UINT32 AdrSrcMiaUxsErr : 1;
76 UINT32 AdrSrcMiaUxErr : 1;
77 UINT32 AdrSrcCpuThrmWdt : 1;
78 UINT32 AdrSrcMeUncErr : 1;
79 UINT32 AdrSrcAdrGpio : 1;
80 UINT32 AdrSrcOcwdtNoicc : 1;
81 UINT32 AdrSrcOcwdtIcc : 1;
82 UINT32 AdrSrcCseHecUncErr : 1;
83 UINT32 AdrSrcPmcSramUncErr : 1;
84 UINT32 AdrSrcPmcIromParity : 1;
85 UINT32 AdrSrcPmcRfFusaErr : 1;
86 UINT32 Reserved3 : 4;
87 UINT32 AdrSrcPpbrParityErr : 1;
88 UINT32 Reserved4 : 2;
89 } Field;
90 UINT32 Value;
91 } ADR_SOURCE_ENABLE;
92
93 /**
94 ADR Configuration
95 <b>Revision 1</b>: - Initial version.
96 **/
97 typedef struct {
98 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
99 UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
100 UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
101 UINT32 AdrTimer1Val : 8; ///< Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer
102 UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values
103 UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer
104 UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values
105 UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
106 UINT32 AdrSrcOverride : 1; ///< Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten
107 UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
108 UINT32 ReservedBits : 1;
109 ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sources are enabled - 0: Enabled, 1: Disabled
110 } ADR_CONFIG;
111
112 #pragma pack (pop)
113
114 #endif // _ADR_CONFIG_H_
ADR_CONFIG::AdrSrcSel
ADR_SOURCE_ENABLE AdrSrcSel
Determine which ADR sources are enabled - 0: Enabled, 1: Disabled.
Definition: AdrConfig.h:109
ADR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AdrConfig.h:98
ConfigBlock.h
Header file for Config Block Lib implementation.
ADR_CONFIG::AdrSrcOverride
UINT32 AdrSrcOverride
Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten.
Definition: AdrConfig.h:106
ADR_CONFIG::AdrHostPartitionReset
UINT32 AdrHostPartitionReset
Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:105
ADR_CONFIG::AdrTimerEn
UINT32 AdrTimerEn
Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:100
ADR_CONFIG::AdrTimer1Val
UINT32 AdrTimer1Val
Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer.
Definition: AdrConfig.h:101
ADR_CONFIG::AdrMultiplier2Val
UINT32 AdrMultiplier2Val
Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to...
Definition: AdrConfig.h:104
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ADR_CONFIG::AdrPlatAckEn
UINT32 AdrPlatAckEn
Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:107
ADR_CONFIG
ADR Configuration Revision 1: - Initial version.
Definition: AdrConfig.h:97
ADR_CONFIG::AdrMultiplier1Val
UINT32 AdrMultiplier1Val
Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to...
Definition: AdrConfig.h:102
ADR_CONFIG::AdrTimer2Val
UINT32 AdrTimer2Val
Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer.
Definition: AdrConfig.h:103
ADR_CONFIG::AdrEn
UINT32 AdrEn
Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:99
ADR_SOURCE_ENABLE
ADR Source Enable.
Definition: AdrConfig.h:59
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AmtConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
Classes | Typedefs | Enumerations
AmtConfig.h File Reference

AMT Config Block for PEI/DXE phase. More...

#include <Library/ConfigBlockLib.h>
#include <ConfigBlock.h>
Include dependency graph for AmtConfig.h:

Go to the source code of this file.

Classes

struct | AMT_PEI_CONFIG
AMT Pei Configuration Structure. More...
struct | AMT_DXE_CONFIG
AMT Dxe Configuration Structure. More...

Typedefs

typedef VOID(* AMT_REPORT_ERROR) (IN AMT_ERROR_MSG_ID MsgId)
Show AMT Error message. More...

Enumerations

enum AMT_ERROR_MSG_ID
AMT Error Message ID.

Detailed Description

AMT Config Block for PEI/DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmtConfig.h.

Typedef Documentation

◆ AMT_REPORT_ERROR

typedef VOID(* AMT_REPORT_ERROR) (IN AMT_ERROR_MSG_ID MsgId)

Show AMT Error message.

This is to display localized message in the console. This is used to display message strings in local language. To display the message, the routine will check the message ID and ConOut the message strings. For example, the End of Post error displayed in English will be: gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of Post message to ME\n"); It is recommended to clear the screen before displaying the error message and keep the message on the screen for several seconds. A sample is provided, see ShowAmtReportError () to retrieve details.

Parameters
[in] MsgId AMT error message ID for displaying on screen message

Definition at line 75 of file AmtConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AmtConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
AmtConfig.h
Go to the documentation of this file.
1 /** @file
2 AMT Config Block for PEI/DXE phase
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _AMT_CONFIG_H_
36 #define _AMT_CONFIG_H_
37
38 #include <Library/ConfigBlockLib.h>
39 #include <ConfigBlock.h>
40
41 #define AMT_PEI_CONFIG_REVISION 1
42 extern EFI_GUID gAmtPeiConfigGuid;
43
44 #define AMT_DXE_CONFIG_REVISION 1
45 extern EFI_GUID gAmtDxeConfigGuid;
46
47 ///
48 /// AMT Error Message ID
49 ///
50 typedef enum {
51 MSG_ASF_BOOT_DISK_MISSING,
52 MSG_KVM_TIMES_UP,
53 MSG_KVM_REJECTED,
54 MSG_KVM_WAIT,
55 MAX_AMT_ERROR_ENUM
56 } AMT_ERROR_MSG_ID;
57
58 /**
59 Show AMT Error message. This is to display localized message in
60 the console. This is used to display message strings in local
61 language. To display the message, the routine will check the
62 message ID and ConOut the message strings. For example, the
63 End of Post error displayed in English will be:
64 gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of
65 Post message to ME\n"); It is recommended to clear the screen
66 before displaying the error message and keep the message on
67 the screen for several seconds.
68 A sample is provided, see ShowAmtReportError () to retrieve
69 details.
70
71 @param[in] MsgId AMT error message ID for displaying on screen message
72
73 **/
74 typedef
75 VOID
76 (*AMT_REPORT_ERROR) (
77 IN AMT_ERROR_MSG_ID MsgId
78 );
79
80
81 #pragma pack (1)
82
83 /**
84 AMT Pei Configuration Structure.
85
86 <b>Revision 1</b>:
87 - Initial version.
88 **/
89 typedef struct {
90 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
91 /**
92 Enable or Disable Intel Active Management Technology feature.
93 If disabled, all Intel AMT features, including Alert Standard Format features, will not be supported.
94 0: Disable
95 <b>1: Enable.</b>
96 **/
97 UINT32 AmtEnabled : 1;
98 /**
99 ME WatchDog timer feature. If disabled, below WatchDogTimerOs/WatchDogTimerBios will be irrelevant.
100 See WatchDogTimerOs and WatchDogTimerBios description.
101 <b>0: Disable</b>
102 1: Enable ME WDT if corresponding timer value is not zero.
103 **/
104 UINT32 WatchDogEnabled : 1;
105 UINT32 FwProgress : 1; ///< PET Events Progress to receive PET Events. 0: Disable; <b>1: Enable</b>
106 UINT32 ManageabilityMode : 1; ///< @deprecated: Manageability Mode sync with Mebx, 0: Disabled; <b>1: AMT</b>
107 UINT32 AmtSolEnabled : 1; ///< Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, <b>1: Enable</b>
108 UINT32 RemoteAssistance : 1; ///< @deprecated: Remote Assistance is enabled if platform is provisioned. <b>0: Disable</b>, 1: Enable
109 UINT32 AmtKvmEnabled : 1; ///< @deprecated: KVM retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, <b>1: Enable</b>
110 UINT32 ForcMebxSyncUp : 1; ///< <b>0: No</b>; 1: Force MEBX execution
111 UINT32 RsvdBits : 24; ///< Reserved for future use & Config block alignment
112 /**
113 OS WatchDog Timer
114 <b>0: Disable</b> OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1.
115 Non zero value - OS WDT will be started after stopping BIOS WDT if WatchDogEnabled is 1. The timer is set
116 according to the value.
117 **/
118 UINT16 WatchDogTimerOs;
119 /**
120 BIOS WatchDog Timer
121 <b>0: Disable</b> BIOS WDT won't be started even if WatchDogEnabled is 1.
122 Non zero value - The BIOS WDT is set according to the value and started if WatchDogEnabled is 1.
123 **/
124 UINT16 WatchDogTimerBios;
125 } AMT_PEI_CONFIG;
126
127
128 /**
129 AMT Dxe Configuration Structure.
130
131 <b>Revision 1</b>:
132 - Initial version.
133 **/
134 typedef struct {
135 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
136 UINT32 CiraRequest : 1; ///< Trigger CIRA boot. <b>0: No CIRA request</b>; 1: Trigger CIRA request
137 UINT32 UnConfigureMe : 1; ///< OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. <b>0: No</b>; 1: Un-configure ME without password
138 UINT32 MebxDebugMsg : 1; ///< @deprecated: OEMFlag Bit 14: Enable OEM debug menu in MEBx. <b>0: Disable</b>; 1: Enable
139 UINT32 HideUnConfigureMeConfirm : 1; ///< @deprecated: OEMFlag Bit 6: Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration. <b>0: Don't hide</b>; 1: Hide
140 UINT32 UsbProvision : 1; ///< Enable/Disable of AMT USB Provisioning. <b>0: Disable</b>; 1: Enable
141 UINT32 AmtbxHotkeyPressed : 1; ///< @deprecated: OEMFlag Bit 1: Enable automatic MEBx hotkey press. <b>0: Disable</b>; 1: Enable
142 /**
143 OEMFlag Bit 2: Enable MEBx selection screen with 2 options:
144 Press 1 to enter ME Configuration Screens
145 Press 2 to initiate a remote connection
146 - <b>0: Disabled</b>
147 - 1: Enabled
148 **/
149 UINT32 AmtbxSelectionScreen : 1; ///< @deprecated
150 UINT32 RsvdBits : 25; ///< Reserved for future use & Config block alignment
151 UINT32 CiraTimeout : 8; ///< @deprecated
152 /**
153 CPU Replacement Timeout
154 <b>0: 10 seconds</b>
155 1: 30 seconds
156 2~5: Reserved
157 6: No delay
158 7: Unlimited delay
159 **/
160 UINT32 CpuReplacementTimeout : 8; ///< @deprecated
161 UINT32 MebxNonUiTextMode : 4; ///< @deprecated: Resolution for non-UI text mode. <b>0: Auto</b>; 1: 80x25; 2: 100x31
162 UINT32 MebxUiTextMode : 4; ///< @deprecated: Resolution for UI text mode. <b>0: Auto</b>; 1: 80x25; 2: 100x31
163 UINT32 MebxGraphicsMode : 4; ///< @deprecated: Resolution for graphics mode. <b>0: Auto</b>; 1: 640x480; 2: 800x600; 3: 1024x768
164 UINT32 OemResolutionSettingsRsvd : 4; ///< @deprecated: Reserved for future use & Config block alignment
165 /**
166 Function pointer for displaying error message on screen
167 **/
168 AMT_REPORT_ERROR AmtReportError;
169 } AMT_DXE_CONFIG;
170
171 #pragma pack ()
172
173 #endif // _AMT_CONFIG_H_
AMT_PEI_CONFIG::FwProgress
UINT32 FwProgress
PET Events Progress to receive PET Events. 0: Disable; 1: Enable
Definition: AmtConfig.h:105
AMT_DXE_CONFIG::AmtbxHotkeyPressed
UINT32 AmtbxHotkeyPressed
Definition: AmtConfig.h:141
ConfigBlock.h
Header file for Config Block Lib implementation.
AMT_DXE_CONFIG::AmtbxSelectionScreen
UINT32 AmtbxSelectionScreen
OEMFlag Bit 2: Enable MEBx selection screen with 2 options: Press 1 to enter ME Configuration Screens...
Definition: AmtConfig.h:149
AMT_DXE_CONFIG::CiraRequest
UINT32 CiraRequest
Trigger CIRA boot. 0: No CIRA request; 1: Trigger CIRA request.
Definition: AmtConfig.h:136
IN
#define IN
Datum is passed to the function.
Definition: Base.h:288
AMT_PEI_CONFIG
AMT Pei Configuration Structure.
Definition: AmtConfig.h:89
AMT_PEI_CONFIG::AmtSolEnabled
UINT32 AmtSolEnabled
Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable,...
Definition: AmtConfig.h:107
AMT_DXE_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: AmtConfig.h:150
AMT_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AmtConfig.h:90
AMT_PEI_CONFIG::AmtEnabled
UINT32 AmtEnabled
Enable or Disable Intel Active Management Technology feature.
Definition: AmtConfig.h:97
AMT_DXE_CONFIG::OemResolutionSettingsRsvd
UINT32 OemResolutionSettingsRsvd
Definition: AmtConfig.h:164
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
AMT_ERROR_MSG_ID
AMT_ERROR_MSG_ID
AMT Error Message ID.
Definition: AmtConfig.h:50
AMT_PEI_CONFIG::WatchDogTimerOs
UINT16 WatchDogTimerOs
OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled ...
Definition: AmtConfig.h:118
AMT_DXE_CONFIG::HideUnConfigureMeConfirm
UINT32 HideUnConfigureMeConfirm
Definition: AmtConfig.h:139
AMT_DXE_CONFIG::CpuReplacementTimeout
UINT32 CpuReplacementTimeout
CPU Replacement Timeout 0: 10 seconds 1: 30 seconds 2~5: Reserved 6: No delay 7: Unlimited delay.
Definition: AmtConfig.h:160
AMT_REPORT_ERROR
VOID(* AMT_REPORT_ERROR)(IN AMT_ERROR_MSG_ID MsgId)
Show AMT Error message.
Definition: AmtConfig.h:76
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
AMT_PEI_CONFIG::AmtKvmEnabled
UINT32 AmtKvmEnabled
Definition: AmtConfig.h:109
AMT_DXE_CONFIG::MebxGraphicsMode
UINT32 MebxGraphicsMode
Definition: AmtConfig.h:163
AMT_DXE_CONFIG::MebxUiTextMode
UINT32 MebxUiTextMode
Definition: AmtConfig.h:162
AMT_DXE_CONFIG::CiraTimeout
UINT32 CiraTimeout
Definition: AmtConfig.h:151
AMT_PEI_CONFIG::RemoteAssistance
UINT32 RemoteAssistance
Definition: AmtConfig.h:108
AMT_DXE_CONFIG::UsbProvision
UINT32 UsbProvision
Enable/Disable of AMT USB Provisioning. 0: Disable; 1: Enable.
Definition: AmtConfig.h:140
ConfigBlockLib.h
Header file for Config Block Lib implementation.
AMT_DXE_CONFIG::MebxNonUiTextMode
UINT32 MebxNonUiTextMode
Definition: AmtConfig.h:161
AMT_DXE_CONFIG::AmtReportError
AMT_REPORT_ERROR AmtReportError
Function pointer for displaying error message on screen.
Definition: AmtConfig.h:168
AMT_PEI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: AmtConfig.h:111
AMT_DXE_CONFIG::MebxDebugMsg
UINT32 MebxDebugMsg
Definition: AmtConfig.h:138
AMT_DXE_CONFIG::UnConfigureMe
UINT32 UnConfigureMe
OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. 0: No; 1: Un-configure ME wit...
Definition: AmtConfig.h:137
AMT_PEI_CONFIG::WatchDogEnabled
UINT32 WatchDogEnabled
ME WatchDog timer feature.
Definition: AmtConfig.h:104
AMT_PEI_CONFIG::ForcMebxSyncUp
UINT32 ForcMebxSyncUp
0: No; 1: Force MEBX execution
Definition: AmtConfig.h:110
AMT_PEI_CONFIG::WatchDogTimerBios
UINT16 WatchDogTimerBios
BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1.
Definition: AmtConfig.h:124
AMT_DXE_CONFIG
AMT Dxe Configuration Structure.
Definition: AmtConfig.h:134
AMT_PEI_CONFIG::ManageabilityMode
UINT32 ManageabilityMode
Definition: AmtConfig.h:106
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
AMT_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AmtConfig.h:135
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Base.h File Reference

  • Edk2
  • MdePkg
  • Include
Classes | Macros | Typedefs
Base.h File Reference

Root include file for Mde Package Base type modules. More...

#include <ProcessorBind.h>
Include dependency graph for Base.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | GUID
128 bit buffer containing a unique identifier value. More...
struct | IPv4_ADDRESS
4-byte buffer. More...
struct | IPv6_ADDRESS
16-byte buffer. More...
struct | _LIST_ENTRY
_LIST_ENTRY structure definition. More...

Macros

#define | GLOBAL_REMOVE_IF_UNREFERENCED
Remove the global variable from the linked image if there are no references to it after all compiler and linker optimizations have been performed.
#define | UNREACHABLE()
Signal compilers and analyzers that this call is not reachable. More...
#define | NORETURN
Signal compilers and analyzers that the function cannot return. More...
#define | ANALYZER_UNREACHABLE()
Signal the analyzer that this call is not reachable. More...
#define | ANALYZER_NORETURN
Signal the analyzer that the function cannot return. More...
#define | RETURNS_TWICE
Tell the code optimizer that the function will return twice. More...
#define | _CONCATENATE(a, b) __CONCATENATE(a, b)
Private worker functions for ASM_PFX()
#define | ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
The USER_LABEL_PREFIX macro predefined by GNUC represents the prefix on symbols in assembly language.
#define | CONST const
Datum is read-only.
#define | STATIC static
Datum is scoped to the current file or function.
#define | VOID void
Undeclared type.
#define | IN
Datum is passed to the function.
#define | OUT
Datum is returned from the function.
#define | OPTIONAL
Passing the datum to the function is optional, and a NULL is passed if the value is not supplied.
#define | TRUE ((BOOLEAN)(1==1))
Boolean true value. More...
#define | FALSE ((BOOLEAN)(0==1))
Boolean false value. More...
#define | NULL ((VOID *) 0)
NULL pointer (VOID *)
#define | MAX_INT8 ((INT8)0x7F)
Maximum values for common UEFI Data Types.
#define | MIN_INT8 (((INT8) -127) - 1)
Minimum values for the signed UEFI Data Types.
#define | _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
Return the size of argument that has been aligned to sizeof (UINTN). More...
#define | VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))
Retrieves a pointer to the beginning of a variable argument list, based on the name of the parameter that immediately precedes the variable argument list. More...
#define | VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))
Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument. More...
#define | VA_END(Marker) (Marker = (VA_LIST) 0)
Terminates the use of a variable argument list. More...
#define | VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
Initializes a VA_LIST as a copy of an existing VA_LIST. More...
#define | _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))
Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary. More...
#define | BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))
Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument. More...
#define | OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
The macro that returns the byte offset of a field in a data structure. More...
#define | STATIC_ASSERT _Static_assert
Portable definition for compile time assertions. More...
#define | BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))
Macro that returns a pointer to the data structure that contains a specified field of that data structure. More...
#define | ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))
Rounds a value up to the next boundary using a specified alignment. More...
#define | ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))
Adjust a pointer by adding the minimum offset required for it to be aligned on a specified alignment boundary. More...
#define | ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN))
Rounds a value up to the next natural boundary for the current CPU. More...
#define | MAX(a, b) (((a) > (b)) ? (a) : (b))
Return the maximum of two operands. More...
#define | MIN(a, b) (((a) < (b)) ? (a) : (b))
Return the minimum of two operands. More...
#define | ABS(a) (((a) < 0) ? (-(a)) : (a))
Return the absolute value of a signed operand. More...
#define | ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))
Produces a RETURN_STATUS code with the highest bit set. More...
#define | ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))
Produces a RETURN_STATUS code with the highest bit clear. More...
#define | RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
Returns TRUE if a specified RETURN_STATUS code is an error code. More...
#define | RETURN_SUCCESS 0
The operation completed successfully.
#define | RETURN_LOAD_ERROR ENCODE_ERROR (1)
The image failed to load.
#define | RETURN_INVALID_PARAMETER ENCODE_ERROR (2)
The parameter was incorrect.
#define | RETURN_UNSUPPORTED ENCODE_ERROR (3)
The operation is not supported.
#define | RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)
The buffer was not the proper size for the request.
#define | RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)
The buffer was not large enough to hold the requested data. More...
#define | RETURN_NOT_READY ENCODE_ERROR (6)
There is no data pending upon return.
#define | RETURN_DEVICE_ERROR ENCODE_ERROR (7)
The physical device reported an error while attempting the operation.
#define | RETURN_WRITE_PROTECTED ENCODE_ERROR (8)
The device can not be written to.
#define | RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)
The resource has run out.
#define | RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)
An inconsistency was detected on the file system causing the operation to fail.
#define | RETURN_VOLUME_FULL ENCODE_ERROR (11)
There is no more space on the file system.
#define | RETURN_NO_MEDIA ENCODE_ERROR (12)
The device does not contain any medium to perform the operation.
#define | RETURN_MEDIA_CHANGED ENCODE_ERROR (13)
The medium in the device has changed since the last access.
#define | RETURN_NOT_FOUND ENCODE_ERROR (14)
The item was not found.
#define | RETURN_ACCESS_DENIED ENCODE_ERROR (15)
Access was denied.
#define | RETURN_NO_RESPONSE ENCODE_ERROR (16)
The server was not found or did not respond to the request.
#define | RETURN_NO_MAPPING ENCODE_ERROR (17)
A mapping to the device does not exist.
#define | RETURN_TIMEOUT ENCODE_ERROR (18)
A timeout time expired.
#define | RETURN_NOT_STARTED ENCODE_ERROR (19)
The protocol has not been started.
#define | RETURN_ALREADY_STARTED ENCODE_ERROR (20)
The protocol has already been started.
#define | RETURN_ABORTED ENCODE_ERROR (21)
The operation was aborted.
#define | RETURN_ICMP_ERROR ENCODE_ERROR (22)
An ICMP error occurred during the network operation.
#define | RETURN_TFTP_ERROR ENCODE_ERROR (23)
A TFTP error occurred during the network operation.
#define | RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)
A protocol error occurred during the network operation.
#define | RETURN_INCOMPATIBLE_VERSION ENCODE_ERROR (25)
A function encountered an internal version that was incompatible with a version requested by the caller.
#define | RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)
The function was not performed due to a security violation.
#define | RETURN_CRC_ERROR ENCODE_ERROR (27)
A CRC error was detected.
#define | RETURN_END_OF_MEDIA ENCODE_ERROR (28)
The beginning or end of media was reached.
#define | RETURN_END_OF_FILE ENCODE_ERROR (31)
The end of the file was reached.
#define | RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)
The language specified was invalid.
#define | RETURN_COMPROMISED_DATA ENCODE_ERROR (33)
The security status of the data is unknown or compromised and the data must be updated or replaced to restore a valid security status.
#define | RETURN_HTTP_ERROR ENCODE_ERROR (35)
A HTTP error occurred during the network operation.
#define | RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)
The string contained one or more characters that the device could not render and were skipped.
#define | RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)
The handle was closed, but the file was not deleted.
#define | RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)
The handle was closed, but the data to the file was not flushed properly.
#define | RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)
The resulting buffer was too small, and the data was truncated to the buffer size.
#define | RETURN_WARN_STALE_DATA ENCODE_WARNING (5)
The data has not been updated within the timeframe set by local policy for this type of data.
#define | RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)
The resulting buffer contains UEFI-compliant file system.
#define | SIGNATURE_16(A, B) ((A) | (B << 8))
Returns a 16-bit signature built from 2 ASCII characters. More...
#define | SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))
Returns a 32-bit signature built from 4 ASCII characters. More...
#define | SIGNATURE_64(A, B, C, D, E, F, G, H) (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
Returns a 64-bit signature built from 8 ASCII characters. More...
#define | RETURN_ADDRESS(L) ((VOID *) 0)
Get the return address of the calling function. More...
#define | ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))
Return the number of elements in an array. More...

Typedefs

typedef struct _LIST_ENTRY | LIST_ENTRY
LIST_ENTRY structure definition.
typedef CHAR8 * | VA_LIST
Variable used to traverse the list of arguments. More...
typedef UINTN * | BASE_LIST
Pointer to the start of a variable argument list stored in a memory buffer. More...

Detailed Description

Root include file for Mde Package Base type modules.

This is the include file for any module of type base. Base modules only use types defined via this include file and can be ported easily to any environment. There are a set of base libraries in the Mde Package that can be used to implement base modules.

Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file Base.h.

Macro Definition Documentation

◆ _BASE_INT_SIZE_OF

#define _BASE_INT_SIZE_OF ( TYPE ) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))

Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary.

Parameters
TYPE The date type to determine the size of.
Returns
The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary.

Definition at line 751 of file Base.h.

◆ _INT_SIZE_OF

#define _INT_SIZE_OF ( n ) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))

Return the size of argument that has been aligned to sizeof (UINTN).

Parameters
n The parameter size to be aligned.
Returns
The aligned size.

Definition at line 580 of file Base.h.

◆ ABS

#define ABS ( a ) (((a) < 0) ? (-(a)) : (a))

Return the absolute value of a signed operand.

This macro returns the absolute value of the signed operand specified by a.

Parameters
a The signed operand.
Returns
The absolute value of the signed operand.

Definition at line 956 of file Base.h.

◆ ALIGN_POINTER

#define ALIGN_POINTER | ( | Pointer,
 |  | Alignment
 | ) | ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))

Adjust a pointer by adding the minimum offset required for it to be aligned on a specified alignment boundary.

This function rounds the pointer specified by Pointer to the next alignment boundary specified by Alignment. The pointer to the aligned address is returned.

Parameters
Pointer | The pointer to round up.
Alignment | The alignment boundary to use to return an aligned pointer.
Returns
Pointer to the aligned address.

Definition at line 898 of file Base.h.

◆ ALIGN_VALUE

#define ALIGN_VALUE | ( | Value,
 |  | Alignment
 | ) | ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))

Rounds a value up to the next boundary using a specified alignment.

This function rounds Value up to the next boundary using the specified Alignment. This aligned value is returned.

Parameters
Value | The value to round up.
Alignment | The alignment boundary used to return the aligned value.
Returns
A value up to the next boundary.

Definition at line 883 of file Base.h.

◆ ALIGN_VARIABLE

#define ALIGN_VARIABLE ( Value ) ALIGN_VALUE ((Value), sizeof (UINTN))

Rounds a value up to the next natural boundary for the current CPU.

This is 4-bytes for 32-bit CPUs and 8-bytes for 64-bit CPUs.

This function rounds the value specified by Value up to the next natural boundary for the current CPU. This rounded value is returned.

Parameters
Value The value to round up.
Returns
Rounded value specified by Value.

Definition at line 912 of file Base.h.

◆ ANALYZER_NORETURN

#define ANALYZER_NORETURN

Signal the analyzer that the function cannot return.

This excludes compilers.

Definition at line 158 of file Base.h.

◆ ANALYZER_UNREACHABLE

#define ANALYZER_UNREACHABLE ( )

Signal the analyzer that this call is not reachable.

This excludes compilers.

Definition at line 132 of file Base.h.

◆ ARRAY_SIZE

#define ARRAY_SIZE ( Array ) (sizeof (Array) / sizeof ((Array)[0]))

Return the number of elements in an array.

Parameters
Array An object of array type. Array is only used as an argument to the sizeof operator, therefore Array is never evaluated. The caller is responsible for ensuring that Array's type is not incomplete; that is, Array must have known constant size.
Returns
The number of elements in Array. The result has type UINTN.

Definition at line 1313 of file Base.h.

◆ BASE_ARG

#define BASE_ARG | ( | Marker,
 |  | TYPE
 | ) | (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))

Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument.

This function returns an argument of the type specified by TYPE from the beginning of the variable argument list specified by Marker. Marker is then updated to point to the next argument in the variable argument list. The method for computing the pointer to the next argument in the argument list is CPU specific following the EFIAPI ABI.

Parameters
Marker | The pointer to the beginning of a variable argument list.
TYPE | The type of argument to retrieve from the beginning of the variable argument list.
Returns
An argument of the type specified by TYPE.

Definition at line 769 of file Base.h.

◆ BASE_CR

#define BASE_CR | ( | Record,
 |  | TYPE,
 |  | Field
 | ) | ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))

Macro that returns a pointer to the data structure that contains a specified field of that data structure.

This is a lightweight method to hide information by placing a public data structure inside a larger private data structure and using a pointer to the public data structure to retrieve a pointer to the private data structure.

This function computes the offset, in bytes, of field specified by Field from the beginning of the data structure specified by TYPE. This offset is subtracted from Record, and is used to return a pointer to a data structure of the type specified by TYPE. If the data type specified by TYPE does not contain the field specified by Field, then the module will not compile.

Parameters
Record | Pointer to the field specified by Field within a data structure of type TYPE.
TYPE | The name of the data structure type to return. This data structure must contain the field specified by Field.
Field | The name of the field in the data structure specified by TYPE to which Record points.
Returns
A pointer to the structure from one of it's elements.

Definition at line 869 of file Base.h.

◆ ENCODE_ERROR

#define ENCODE_ERROR ( StatusCode ) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))

Produces a RETURN_STATUS code with the highest bit set.

Parameters
StatusCode The status code value to convert into a warning code. StatusCode must be in the range 0x00000000..0x7FFFFFFF.
Returns
The value specified by StatusCode with the highest bit set.

Definition at line 973 of file Base.h.

◆ ENCODE_WARNING

#define ENCODE_WARNING ( StatusCode ) ((RETURN_STATUS)(StatusCode))

Produces a RETURN_STATUS code with the highest bit clear.

Parameters
StatusCode The status code value to convert into a warning code. StatusCode must be in the range 0x00000000..0x7FFFFFFF.
Returns
The value specified by StatusCode with the highest bit clear.

Definition at line 984 of file Base.h.

◆ FALSE

#define FALSE ((BOOLEAN)(0==1))

Boolean false value.

UEFI Specification defines this value to be 0, but this form is more portable.

Definition at line 316 of file Base.h.

◆ MAX

#define MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Return the maximum of two operands.

This macro returns the maximum of two operand specified by a and b. Both a and b must be the same numerical types, signed or unsigned.

Parameters
a | The first operand with any numerical type.
b | The second operand. Can be any numerical type as long as is the same type as a.
Returns
Maximum of two operands.

Definition at line 928 of file Base.h.

◆ MIN

#define MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Return the minimum of two operands.

This macro returns the minimal of two operand specified by a and b. Both a and b must be the same numerical types, signed or unsigned.

Parameters
a | The first operand with any numerical type.
b | The second operand. It should be the same any numerical type with a.
Returns
Minimum of two operands.

Definition at line 943 of file Base.h.

◆ NORETURN

#define NORETURN

Signal compilers and analyzers that the function cannot return.

It is up to the compiler to remove any code past a call to functions flagged with this attribute.

Definition at line 108 of file Base.h.

◆ OFFSET_OF

#define OFFSET_OF | ( | TYPE,
 |  | Field
 | ) | ((UINTN) &(((TYPE *)0)->Field))

The macro that returns the byte offset of a field in a data structure.

This function returns the offset, in bytes, of field specified by Field from the beginning of the data structure specified by TYPE. If TYPE does not contain Field, the module will not compile.

Parameters
TYPE | The name of the data structure that contains the field specified by Field.
Field | The name of the field in the data structure.
Returns
Offset, in bytes, of field.

Definition at line 789 of file Base.h.

◆ RETURN_ADDRESS

#define RETURN_ADDRESS ( L ) ((VOID *) 0)

Get the return address of the calling function.

Parameters
L Return Level.
Returns
0 as compilers don't support this feature.

Definition at line 1299 of file Base.h.

◆ RETURN_BUFFER_TOO_SMALL

#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)

The buffer was not large enough to hold the requested data.

The required buffer size is returned in the appropriate parameter when this error occurs.

Definition at line 1029 of file Base.h.

◆ RETURN_ERROR

#define RETURN_ERROR ( StatusCode ) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)

Returns TRUE if a specified RETURN_STATUS code is an error code.

This function returns TRUE if StatusCode has the high bit set. Otherwise, FALSE is returned.

Parameters
StatusCode The status code value to evaluate.
Return values
TRUE | The high bit of StatusCode is set.
FALSE | The high bit of StatusCode is clear.

Definition at line 997 of file Base.h.

◆ RETURNS_TWICE

#define RETURNS_TWICE

Tell the code optimizer that the function will return twice.

This prevents wrong optimizations which can cause bugs. Tell the code optimizer that the function will return twice. This prevents wrong optimizations which can cause bugs.

Definition at line 178 of file Base.h.

◆ SIGNATURE_16

#define SIGNATURE_16 | ( | A,
 |  | B
 | ) | ((A) | (B << 8))

Returns a 16-bit signature built from 2 ASCII characters.

This macro returns a 16-bit value built from the two ASCII characters specified by A and B.

Parameters
A | The first ASCII character.
B | The second ASCII character.
Returns
A 16-bit value built from the two ASCII characters specified by A and B.

Definition at line 1220 of file Base.h.

◆ SIGNATURE_32

#define SIGNATURE_32 | ( | A,
 |  | B,
 |  | C,
 |  | D
 | ) | (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))

Returns a 32-bit signature built from 4 ASCII characters.

This macro returns a 32-bit value built from the four ASCII characters specified by A, B, C, and D.

Parameters
A | The first ASCII character.
B | The second ASCII character.
C | The third ASCII character.
D | The fourth ASCII character.
Returns
A 32-bit value built from the two ASCII characters specified by A, B, C and D.

Definition at line 1237 of file Base.h.

◆ SIGNATURE_64

#define SIGNATURE_64 | ( | A,
 |  | B,
 |  | C,
 |  | D,
 |  | E,
 |  | F,
 |  | G,
 |  | H
 | ) | (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))

Returns a 64-bit signature built from 8 ASCII characters.

This macro returns a 64-bit value built from the eight ASCII characters specified by A, B, C, D, E, F, G,and H.

Parameters
A | The first ASCII character.
B | The second ASCII character.
C | The third ASCII character.
D | The fourth ASCII character.
E | The fifth ASCII character.
F | The sixth ASCII character.
G | The seventh ASCII character.
H | The eighth ASCII character.
Returns
A 64-bit value built from the two ASCII characters specified by A, B, C, D, E, F, G and H.

Definition at line 1258 of file Base.h.

◆ STATIC_ASSERT

#define STATIC_ASSERT _Static_assert

Portable definition for compile time assertions.

Equivalent to C11 static_assert macro from assert.h.

Parameters
Expression | Boolean expression.
Message | Raised compiler diagnostic message when expression is false.

Definition at line 805 of file Base.h.

◆ TRUE

#define TRUE ((BOOLEAN)(1==1))

Boolean true value.

UEFI Specification defines this value to be 1, but this form is more portable.

Definition at line 310 of file Base.h.

◆ UNREACHABLE

#define UNREACHABLE ( )

Signal compilers and analyzers that this call is not reachable.

It is up to the compiler to remove any code past that point.

Definition at line 78 of file Base.h.

◆ VA_ARG

#define VA_ARG | ( | Marker,
 |  | TYPE
 | ) | (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))

Returns an argument of a specified type from a variable argument list and updates the pointer to the variable argument list to point to the next argument.

This function returns an argument of the type specified by TYPE from the beginning of the variable argument list specified by Marker. Marker is then updated to point to the next argument in the variable argument list. The method for computing the pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI.

Parameters
Marker | VA_LIST used to traverse the list of arguments.
TYPE | The type of argument to retrieve from the beginning of the variable argument list.
Returns
An argument of the type specified by TYPE.

Definition at line 710 of file Base.h.

◆ VA_COPY

#define VA_COPY | ( | Dest,
 |  | Start
 | ) | ((void)((Dest) = (Start)))

Initializes a VA_LIST as a copy of an existing VA_LIST.

This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach the present state of Start.

Parameters
Dest | VA_LIST used to traverse the list of arguments.
Start | VA_LIST used to traverse the list of arguments.

Definition at line 735 of file Base.h.

◆ VA_END

#define VA_END ( Marker ) (Marker = (VA_LIST) 0)

Terminates the use of a variable argument list.

This function initializes Marker so it can no longer be used with VA_ARG(). After this macro is used, the only way to access the variable argument list is by using VA_START() again.

Parameters
Marker VA_LIST used to traverse the list of arguments.

Definition at line 722 of file Base.h.

◆ VA_START

#define VA_START | ( | Marker,
 |  | Parameter
 | ) | (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))

Retrieves a pointer to the beginning of a variable argument list, based on the name of the parameter that immediately precedes the variable argument list.

This function initializes Marker to point to the beginning of the variable argument list that immediately follows Parameter. The method for computing the pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI.

Parameters
Marker | The VA_LIST used to traverse the list of arguments.
Parameter | The name of the parameter that immediately precedes the variable argument list.
Returns
A pointer to the beginning of a variable argument list.

Definition at line 692 of file Base.h.

Typedef Documentation

◆ BASE_LIST

typedef UINTN* BASE_LIST

Pointer to the start of a variable argument list stored in a memory buffer.

Same as UINT8 *.

Definition at line 742 of file Base.h.

◆ VA_LIST

typedef CHAR8* VA_LIST

Variable used to traverse the list of arguments.

This type can vary by implementation and could be an array or structure.

Definition at line 674 of file Base.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Base.h Source File

  • Edk2
  • MdePkg
  • Include
Base.h
Go to the documentation of this file.
1 /** @file
2 Root include file for Mde Package Base type modules
3
4 This is the include file for any module of type base. Base modules only use
5 types defined via this include file and can be ported easily to any
6 environment. There are a set of base libraries in the Mde Package that can
7 be used to implement base modules.
8
9 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
10 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
11 SPDX-License-Identifier: BSD-2-Clause-Patent
12
13 **/
14
15
16 #ifndef __BASE_H__
17 #define __BASE_H__
18
19 //
20 // Include processor specific binding
21 //
22 #include <ProcessorBind.h>
23
24 #if defined(_MSC_EXTENSIONS)
25 //
26 // Disable warning when last field of data structure is a zero sized array.
27 //
28 #pragma warning ( disable : 4200 )
29 #endif
30
31 //
32 // The Microsoft* C compiler can removed references to unreferenced data items
33 // if the /OPT:REF linker option is used. We defined a macro as this is a
34 // a non standard extension
35 //
36 #if defined(_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)
37 ///
38 /// Remove global variable from the linked image if there are no references to
39 /// it after all compiler and linker optimizations have been performed.
40 ///
41 ///
42 #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
43 #else
44 ///
45 /// Remove the global variable from the linked image if there are no references
46 /// to it after all compiler and linker optimizations have been performed.
47 ///
48 ///
49 #define GLOBAL_REMOVE_IF_UNREFERENCED
50 #endif
51
52 //
53 // Should be used in combination with NORETURN to avoid 'noreturn' returns
54 // warnings.
55 //
56 #ifndef UNREACHABLE
57 #ifdef __GNUC__
58 ///
59 /// Signal compilers and analyzers that this call is not reachable. It is
60 /// up to the compiler to remove any code past that point.
61 ///
62 #define UNREACHABLE() __builtin_unreachable ()
63 #elif defined (__has_feature)
64 #if __has_builtin (__builtin_unreachable)
65 ///
66 /// Signal compilers and analyzers that this call is not reachable. It is
67 /// up to the compiler to remove any code past that point.
68 ///
69 #define UNREACHABLE() __builtin_unreachable ()
70 #endif
71 #endif
72
73 #ifndef UNREACHABLE
74 ///
75 /// Signal compilers and analyzers that this call is not reachable. It is
76 /// up to the compiler to remove any code past that point.
77 ///
78 #define UNREACHABLE()
79 #endif
80 #endif
81
82 //
83 // Signaling compilers and analyzers that a certain function cannot return may
84 // remove all following code and thus lead to better optimization and less
85 // false positives.
86 //
87 #ifndef NORETURN
88 #if defined (__GNUC__) || defined (__clang__)
89 ///
90 /// Signal compilers and analyzers that the function cannot return.
91 /// It is up to the compiler to remove any code past a call to functions
92 /// flagged with this attribute.
93 ///
94 #define NORETURN __attribute__((noreturn))
95 #elif defined(_MSC_EXTENSIONS) && !defined(MDE_CPU_EBC)
96 ///
97 /// Signal compilers and analyzers that the function cannot return.
98 /// It is up to the compiler to remove any code past a call to functions
99 /// flagged with this attribute.
100 ///
101 #define NORETURN __declspec(noreturn)
102 #else
103 ///
104 /// Signal compilers and analyzers that the function cannot return.
105 /// It is up to the compiler to remove any code past a call to functions
106 /// flagged with this attribute.
107 ///
108 #define NORETURN
109 #endif
110 #endif
111
112 //
113 // Should be used in combination with ANALYZER_NORETURN to avoid 'noreturn'
114 // returns warnings.
115 //
116 #ifndef ANALYZER_UNREACHABLE
117 #ifdef __clang_analyzer__
118 #if __has_builtin (__builtin_unreachable)
119 ///
120 /// Signal the analyzer that this call is not reachable.
121 /// This excludes compilers.
122 ///
123 #define ANALYZER_UNREACHABLE() __builtin_unreachable ()
124 #endif
125 #endif
126
127 #ifndef ANALYZER_UNREACHABLE
128 ///
129 /// Signal the analyzer that this call is not reachable.
130 /// This excludes compilers.
131 ///
132 #define ANALYZER_UNREACHABLE()
133 #endif
134 #endif
135
136 //
137 // Static Analyzers may issue errors about potential NULL-dereferences when
138 // dereferencing a pointer, that has been checked before, outside of a
139 // NULL-check. This may lead to false positives, such as when using ASSERT()
140 // for verification.
141 //
142 #ifndef ANALYZER_NORETURN
143 #ifdef __has_feature
144 #if __has_feature (attribute_analyzer_noreturn)
145 ///
146 /// Signal analyzers that the function cannot return.
147 /// This excludes compilers.
148 ///
149 #define ANALYZER_NORETURN __attribute__((analyzer_noreturn))
150 #endif
151 #endif
152
153 #ifndef ANALYZER_NORETURN
154 ///
155 /// Signal the analyzer that the function cannot return.
156 /// This excludes compilers.
157 ///
158 #define ANALYZER_NORETURN
159 #endif
160 #endif
161
162 ///
163 /// Tell the code optimizer that the function will return twice.
164 /// This prevents wrong optimizations which can cause bugs.
165 ///
166 #ifndef RETURNS_TWICE
167 #if defined (__GNUC__) || defined (__clang__)
168 ///
169 /// Tell the code optimizer that the function will return twice.
170 /// This prevents wrong optimizations which can cause bugs.
171 ///
172 #define RETURNS_TWICE __attribute__((returns_twice))
173 #else
174 ///
175 /// Tell the code optimizer that the function will return twice.
176 /// This prevents wrong optimizations which can cause bugs.
177 ///
178 #define RETURNS_TWICE
179 #endif
180 #endif
181
182 //
183 // For symbol name in assembly code, an extra "_" is sometimes necessary
184 //
185
186 ///
187 /// Private worker functions for ASM_PFX()
188 ///
189 #define _CONCATENATE(a, b) __CONCATENATE(a, b)
190 #define __CONCATENATE(a, b) a ## b
191
192 ///
193 /// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix
194 /// on symbols in assembly language.
195 ///
196 #define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
197
198 #ifdef __APPLE__
199 //
200 // Apple extension that is used by the linker to optimize code size
201 // with assembly functions. Put at the end of your .S files
202 //
203 #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols
204 #else
205 #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED
206 #endif
207
208 #ifdef __CC_ARM
209 //
210 // Older RVCT ARM compilers don't fully support #pragma pack and require __packed
211 // as a prefix for the structure.
212 //
213 #define PACKED __packed
214 #else
215 #define PACKED
216 #endif
217
218 ///
219 /// 128 bit buffer containing a unique identifier value.
220 /// Unless otherwise specified, aligned on a 64 bit boundary.
221 ///
222 typedef struct {
223 UINT32 Data1;
224 UINT16 Data2;
225 UINT16 Data3;
226 UINT8 Data4[8];
227 } GUID;
228
229 ///
230 /// 4-byte buffer. An IPv4 internet protocol address.
231 ///
232 typedef struct {
233 UINT8 Addr[4];
234 } IPv4_ADDRESS;
235
236 ///
237 /// 16-byte buffer. An IPv6 internet protocol address.
238 ///
239 typedef struct {
240 UINT8 Addr[16];
241 } IPv6_ADDRESS;
242
243 //
244 // 8-bytes unsigned value that represents a physical system address.
245 //
246 typedef UINT64 PHYSICAL_ADDRESS;
247
248 ///
249 /// LIST_ENTRY structure definition.
250 ///
251 typedef struct _LIST_ENTRY LIST_ENTRY;
252
253 ///
254 /// _LIST_ENTRY structure definition.
255 ///
256 struct _LIST_ENTRY {
257 LIST_ENTRY *ForwardLink;
258 LIST_ENTRY *BackLink;
259 };
260
261 //
262 // Modifiers to abstract standard types to aid in debug of problems
263 //
264
265 ///
266 /// Datum is read-only.
267 ///
268 #define CONST const
269
270 ///
271 /// Datum is scoped to the current file or function.
272 ///
273 #define STATIC static
274
275 ///
276 /// Undeclared type.
277 ///
278 #define VOID void
279
280 //
281 // Modifiers for Data Types used to self document code.
282 // This concept is borrowed for UEFI specification.
283 //
284
285 ///
286 /// Datum is passed to the function.
287 ///
288 #define IN
289
290 ///
291 /// Datum is returned from the function.
292 ///
293 #define OUT
294
295 ///
296 /// Passing the datum to the function is optional, and a NULL
297 /// is passed if the value is not supplied.
298 ///
299 #define OPTIONAL
300
301 //
302 // UEFI specification claims 1 and 0. We are concerned about the
303 // compiler portability so we did it this way.
304 //
305
306 ///
307 /// Boolean true value. UEFI Specification defines this value to be 1,
308 /// but this form is more portable.
309 ///
310 #define TRUE ((BOOLEAN)(1==1))
311
312 ///
313 /// Boolean false value. UEFI Specification defines this value to be 0,
314 /// but this form is more portable.
315 ///
316 #define FALSE ((BOOLEAN)(0==1))
317
318 ///
319 /// NULL pointer (VOID *)
320 ///
321 #define NULL ((VOID *) 0)
322
323 //
324 // Null character
325 //
326 #define CHAR_NULL 0x0000
327
328 ///
329 /// Maximum values for common UEFI Data Types
330 ///
331 #define MAX_INT8 ((INT8)0x7F)
332 #define MAX_UINT8 ((UINT8)0xFF)
333 #define MAX_INT16 ((INT16)0x7FFF)
334 #define MAX_UINT16 ((UINT16)0xFFFF)
335 #define MAX_INT32 ((INT32)0x7FFFFFFF)
336 #define MAX_UINT32 ((UINT32)0xFFFFFFFF)
337 #define MAX_INT64 ((INT64)0x7FFFFFFFFFFFFFFFULL)
338 #define MAX_UINT64 ((UINT64)0xFFFFFFFFFFFFFFFFULL)
339
340 ///
341 /// Minimum values for the signed UEFI Data Types
342 ///
343 #define MIN_INT8 (((INT8) -127) - 1)
344 #define MIN_INT16 (((INT16) -32767) - 1)
345 #define MIN_INT32 (((INT32) -2147483647) - 1)
346 #define MIN_INT64 (((INT64) -9223372036854775807LL) - 1)
347
348 #define BIT0 0x00000001
349 #define BIT1 0x00000002
350 #define BIT2 0x00000004
351 #define BIT3 0x00000008
352 #define BIT4 0x00000010
353 #define BIT5 0x00000020
354 #define BIT6 0x00000040
355 #define BIT7 0x00000080
356 #define BIT8 0x00000100
357 #define BIT9 0x00000200
358 #define BIT10 0x00000400
359 #define BIT11 0x00000800
360 #define BIT12 0x00001000
361 #define BIT13 0x00002000
362 #define BIT14 0x00004000
363 #define BIT15 0x00008000
364 #define BIT16 0x00010000
365 #define BIT17 0x00020000
366 #define BIT18 0x00040000
367 #define BIT19 0x00080000
368 #define BIT20 0x00100000
369 #define BIT21 0x00200000
370 #define BIT22 0x00400000
371 #define BIT23 0x00800000
372 #define BIT24 0x01000000
373 #define BIT25 0x02000000
374 #define BIT26 0x04000000
375 #define BIT27 0x08000000
376 #define BIT28 0x10000000
377 #define BIT29 0x20000000
378 #define BIT30 0x40000000
379 #define BIT31 0x80000000
380 #define BIT32 0x0000000100000000ULL
381 #define BIT33 0x0000000200000000ULL
382 #define BIT34 0x0000000400000000ULL
383 #define BIT35 0x0000000800000000ULL
384 #define BIT36 0x0000001000000000ULL
385 #define BIT37 0x0000002000000000ULL
386 #define BIT38 0x0000004000000000ULL
387 #define BIT39 0x0000008000000000ULL
388 #define BIT40 0x0000010000000000ULL
389 #define BIT41 0x0000020000000000ULL
390 #define BIT42 0x0000040000000000ULL
391 #define BIT43 0x0000080000000000ULL
392 #define BIT44 0x0000100000000000ULL
393 #define BIT45 0x0000200000000000ULL
394 #define BIT46 0x0000400000000000ULL
395 #define BIT47 0x0000800000000000ULL
396 #define BIT48 0x0001000000000000ULL
397 #define BIT49 0x0002000000000000ULL
398 #define BIT50 0x0004000000000000ULL
399 #define BIT51 0x0008000000000000ULL
400 #define BIT52 0x0010000000000000ULL
401 #define BIT53 0x0020000000000000ULL
402 #define BIT54 0x0040000000000000ULL
403 #define BIT55 0x0080000000000000ULL
404 #define BIT56 0x0100000000000000ULL
405 #define BIT57 0x0200000000000000ULL
406 #define BIT58 0x0400000000000000ULL
407 #define BIT59 0x0800000000000000ULL
408 #define BIT60 0x1000000000000000ULL
409 #define BIT61 0x2000000000000000ULL
410 #define BIT62 0x4000000000000000ULL
411 #define BIT63 0x8000000000000000ULL
412
413 #define SIZE_1KB 0x00000400
414 #define SIZE_2KB 0x00000800
415 #define SIZE_4KB 0x00001000
416 #define SIZE_8KB 0x00002000
417 #define SIZE_16KB 0x00004000
418 #define SIZE_32KB 0x00008000
419 #define SIZE_64KB 0x00010000
420 #define SIZE_128KB 0x00020000
421 #define SIZE_256KB 0x00040000
422 #define SIZE_512KB 0x00080000
423 #define SIZE_1MB 0x00100000
424 #define SIZE_2MB 0x00200000
425 #define SIZE_4MB 0x00400000
426 #define SIZE_8MB 0x00800000
427 #define SIZE_16MB 0x01000000
428 #define SIZE_32MB 0x02000000
429 #define SIZE_64MB 0x04000000
430 #define SIZE_128MB 0x08000000
431 #define SIZE_256MB 0x10000000
432 #define SIZE_512MB 0x20000000
433 #define SIZE_1GB 0x40000000
434 #define SIZE_2GB 0x80000000
435 #define SIZE_4GB 0x0000000100000000ULL
436 #define SIZE_8GB 0x0000000200000000ULL
437 #define SIZE_16GB 0x0000000400000000ULL
438 #define SIZE_32GB 0x0000000800000000ULL
439 #define SIZE_64GB 0x0000001000000000ULL
440 #define SIZE_128GB 0x0000002000000000ULL
441 #define SIZE_256GB 0x0000004000000000ULL
442 #define SIZE_512GB 0x0000008000000000ULL
443 #define SIZE_1TB 0x0000010000000000ULL
444 #define SIZE_2TB 0x0000020000000000ULL
445 #define SIZE_4TB 0x0000040000000000ULL
446 #define SIZE_8TB 0x0000080000000000ULL
447 #define SIZE_16TB 0x0000100000000000ULL
448 #define SIZE_32TB 0x0000200000000000ULL
449 #define SIZE_64TB 0x0000400000000000ULL
450 #define SIZE_128TB 0x0000800000000000ULL
451 #define SIZE_256TB 0x0001000000000000ULL
452 #define SIZE_512TB 0x0002000000000000ULL
453 #define SIZE_1PB 0x0004000000000000ULL
454 #define SIZE_2PB 0x0008000000000000ULL
455 #define SIZE_4PB 0x0010000000000000ULL
456 #define SIZE_8PB 0x0020000000000000ULL
457 #define SIZE_16PB 0x0040000000000000ULL
458 #define SIZE_32PB 0x0080000000000000ULL
459 #define SIZE_64PB 0x0100000000000000ULL
460 #define SIZE_128PB 0x0200000000000000ULL
461 #define SIZE_256PB 0x0400000000000000ULL
462 #define SIZE_512PB 0x0800000000000000ULL
463 #define SIZE_1EB 0x1000000000000000ULL
464 #define SIZE_2EB 0x2000000000000000ULL
465 #define SIZE_4EB 0x4000000000000000ULL
466 #define SIZE_8EB 0x8000000000000000ULL
467
468 #define BASE_1KB 0x00000400
469 #define BASE_2KB 0x00000800
470 #define BASE_4KB 0x00001000
471 #define BASE_8KB 0x00002000
472 #define BASE_16KB 0x00004000
473 #define BASE_32KB 0x00008000
474 #define BASE_64KB 0x00010000
475 #define BASE_128KB 0x00020000
476 #define BASE_256KB 0x00040000
477 #define BASE_512KB 0x00080000
478 #define BASE_1MB 0x00100000
479 #define BASE_2MB 0x00200000
480 #define BASE_4MB 0x00400000
481 #define BASE_8MB 0x00800000
482 #define BASE_16MB 0x01000000
483 #define BASE_32MB 0x02000000
484 #define BASE_64MB 0x04000000
485 #define BASE_128MB 0x08000000
486 #define BASE_256MB 0x10000000
487 #define BASE_512MB 0x20000000
488 #define BASE_1GB 0x40000000
489 #define BASE_2GB 0x80000000
490 #define BASE_4GB 0x0000000100000000ULL
491 #define BASE_8GB 0x0000000200000000ULL
492 #define BASE_16GB 0x0000000400000000ULL
493 #define BASE_32GB 0x0000000800000000ULL
494 #define BASE_64GB 0x0000001000000000ULL
495 #define BASE_128GB 0x0000002000000000ULL
496 #define BASE_256GB 0x0000004000000000ULL
497 #define BASE_512GB 0x0000008000000000ULL
498 #define BASE_1TB 0x0000010000000000ULL
499 #define BASE_2TB 0x0000020000000000ULL
500 #define BASE_4TB 0x0000040000000000ULL
501 #define BASE_8TB 0x0000080000000000ULL
502 #define BASE_16TB 0x0000100000000000ULL
503 #define BASE_32TB 0x0000200000000000ULL
504 #define BASE_64TB 0x0000400000000000ULL
505 #define BASE_128TB 0x0000800000000000ULL
506 #define BASE_256TB 0x0001000000000000ULL
507 #define BASE_512TB 0x0002000000000000ULL
508 #define BASE_1PB 0x0004000000000000ULL
509 #define BASE_2PB 0x0008000000000000ULL
510 #define BASE_4PB 0x0010000000000000ULL
511 #define BASE_8PB 0x0020000000000000ULL
512 #define BASE_16PB 0x0040000000000000ULL
513 #define BASE_32PB 0x0080000000000000ULL
514 #define BASE_64PB 0x0100000000000000ULL
515 #define BASE_128PB 0x0200000000000000ULL
516 #define BASE_256PB 0x0400000000000000ULL
517 #define BASE_512PB 0x0800000000000000ULL
518 #define BASE_1EB 0x1000000000000000ULL
519 #define BASE_2EB 0x2000000000000000ULL
520 #define BASE_4EB 0x4000000000000000ULL
521 #define BASE_8EB 0x8000000000000000ULL
522
523 //
524 // Support for variable argument lists in freestanding edk2 modules.
525 //
526 // For modules that use the ISO C library interfaces for variable
527 // argument lists, refer to "StdLib/Include/stdarg.h".
528 //
529 // VA_LIST - typedef for argument list.
530 // VA_START (VA_LIST Marker, argument before the ...) - Init Marker for use.
531 // VA_END (VA_LIST Marker) - Clear Marker
532 // VA_ARG (VA_LIST Marker, var arg type) - Use Marker to get an argument from
533 // the ... list. You must know the type and pass it in this macro. Type
534 // must be compatible with the type of the actual next argument (as promoted
535 // according to the default argument promotions.)
536 // VA_COPY (VA_LIST Dest, VA_LIST Start) - Initialize Dest as a copy of Start.
537 //
538 // Example:
539 //
540 // UINTN
541 // EFIAPI
542 // ExampleVarArg (
543 // IN UINTN NumberOfArgs,
544 // ...
545 // )
546 // {
547 // VA_LIST Marker;
548 // UINTN Index;
549 // UINTN Result;
550 //
551 // //
552 // // Initialize the Marker
553 // //
554 // VA_START (Marker, NumberOfArgs);
555 // for (Index = 0, Result = 0; Index < NumberOfArgs; Index++) {
556 // //
557 // // The ... list is a series of UINTN values, so sum them up.
558 // //
559 // Result += VA_ARG (Marker, UINTN);
560 // }
561 //
562 // VA_END (Marker);
563 // return Result;
564 // }
565 //
566 // Notes:
567 // - Functions that call VA_START() / VA_END() must have a variable
568 // argument list and must be declared EFIAPI.
569 // - Functions that call VA_COPY() / VA_END() must be declared EFIAPI.
570 // - Functions that only use VA_LIST and VA_ARG() need not be EFIAPI.
571 //
572
573 /**
574 Return the size of argument that has been aligned to sizeof (UINTN).
575
576 @param n The parameter size to be aligned.
577
578 @return The aligned size.
579 **/
580 #define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))
581
582 #if defined(__CC_ARM)
583 //
584 // RVCT ARM variable argument list support.
585 //
586
587 ///
588 /// Variable used to traverse the list of arguments. This type can vary by
589 /// implementation and could be an array or structure.
590 ///
591 #ifdef __APCS_ADSABI
592 typedef int *va_list[1];
593 #define VA_LIST va_list
594 #else
595 typedef struct __va_list { void *__ap; } va_list;
596 #define VA_LIST va_list
597 #endif
598
599 #define VA_START(Marker, Parameter) __va_start(Marker, Parameter)
600
601 #define VA_ARG(Marker, TYPE) __va_arg(Marker, TYPE)
602
603 #define VA_END(Marker) ((void)0)
604
605 // For some ARM RVCT compilers, __va_copy is not defined
606 #ifndef __va_copy
607 #define __va_copy(dest, src) ((void)((dest) = (src)))
608 #endif
609
610 #define VA_COPY(Dest, Start) __va_copy (Dest, Start)
611
612 #elif defined(_M_ARM) || defined(_M_ARM64)
613 //
614 // MSFT ARM variable argument list support.
615 //
616
617 typedef char* VA_LIST;
618
619 #define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)
620 #define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
621 #define VA_END(Marker) (Marker = (VA_LIST) 0)
622 #define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
623
624 #elif defined(__GNUC__) || defined(__clang__)
625
626 #if defined(MDE_CPU_X64) && !defined(NO_MSABI_VA_FUNCS)
627 //
628 // X64 only. Use MS ABI version of GCC built-in macros for variable argument lists.
629 //
630 ///
631 /// Both GCC and LLVM 3.8 for X64 support new variable argument intrinsics for Microsoft ABI
632 ///
633
634 ///
635 /// Variable used to traverse the list of arguments. This type can vary by
636 /// implementation and could be an array or structure.
637 ///
638 typedef __builtin_ms_va_list VA_LIST;
639
640 #define VA_START(Marker, Parameter) __builtin_ms_va_start (Marker, Parameter)
641
642 #define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
643
644 #define VA_END(Marker) __builtin_ms_va_end (Marker)
645
646 #define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start)
647
648 #else
649 //
650 // Use GCC built-in macros for variable argument lists.
651 //
652
653 ///
654 /// Variable used to traverse the list of arguments. This type can vary by
655 /// implementation and could be an array or structure.
656 ///
657 typedef __builtin_va_list VA_LIST;
658
659 #define VA_START(Marker, Parameter) __builtin_va_start (Marker, Parameter)
660
661 #define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))
662
663 #define VA_END(Marker) __builtin_va_end (Marker)
664
665 #define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start)
666
667 #endif
668
669 #else
670 ///
671 /// Variable used to traverse the list of arguments. This type can vary by
672 /// implementation and could be an array or structure.
673 ///
674 typedef CHAR8 *VA_LIST;
675
676 /**
677 Retrieves a pointer to the beginning of a variable argument list, based on
678 the name of the parameter that immediately precedes the variable argument list.
679
680 This function initializes Marker to point to the beginning of the variable
681 argument list that immediately follows Parameter. The method for computing the
682 pointer to the next argument in the argument list is CPU-specific following the
683 EFIAPI ABI.
684
685 @param Marker The VA_LIST used to traverse the list of arguments.
686 @param Parameter The name of the parameter that immediately precedes
687 the variable argument list.
688
689 @return A pointer to the beginning of a variable argument list.
690
691 **/
692 #define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))
693
694 /**
695 Returns an argument of a specified type from a variable argument list and updates
696 the pointer to the variable argument list to point to the next argument.
697
698 This function returns an argument of the type specified by TYPE from the beginning
699 of the variable argument list specified by Marker. Marker is then updated to point
700 to the next argument in the variable argument list. The method for computing the
701 pointer to the next argument in the argument list is CPU-specific following the EFIAPI ABI.
702
703 @param Marker VA_LIST used to traverse the list of arguments.
704 @param TYPE The type of argument to retrieve from the beginning
705 of the variable argument list.
706
707 @return An argument of the type specified by TYPE.
708
709 **/
710 #define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))
711
712 /**
713 Terminates the use of a variable argument list.
714
715 This function initializes Marker so it can no longer be used with VA_ARG().
716 After this macro is used, the only way to access the variable argument list is
717 by using VA_START() again.
718
719 @param Marker VA_LIST used to traverse the list of arguments.
720
721 **/
722 #define VA_END(Marker) (Marker = (VA_LIST) 0)
723
724 /**
725 Initializes a VA_LIST as a copy of an existing VA_LIST.
726
727 This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest
728 followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach
729 the present state of Start.
730
731 @param Dest VA_LIST used to traverse the list of arguments.
732 @param Start VA_LIST used to traverse the list of arguments.
733
734 **/
735 #define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))
736
737 #endif
738
739 ///
740 /// Pointer to the start of a variable argument list stored in a memory buffer. Same as UINT8 *.
741 ///
742 typedef UINTN *BASE_LIST;
743
744 /**
745 Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary.
746
747 @param TYPE The date type to determine the size of.
748
749 @return The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary.
750 **/
751 #define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))
752
753 /**
754 Returns an argument of a specified type from a variable argument list and updates
755 the pointer to the variable argument list to point to the next argument.
756
757 This function returns an argument of the type specified by TYPE from the beginning
758 of the variable argument list specified by Marker. Marker is then updated to point
759 to the next argument in the variable argument list. The method for computing the
760 pointer to the next argument in the argument list is CPU specific following the EFIAPI ABI.
761
762 @param Marker The pointer to the beginning of a variable argument list.
763 @param TYPE The type of argument to retrieve from the beginning
764 of the variable argument list.
765
766 @return An argument of the type specified by TYPE.
767
768 **/
769 #define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))
770
771 /**
772 The macro that returns the byte offset of a field in a data structure.
773
774 This function returns the offset, in bytes, of field specified by Field from the
775 beginning of the data structure specified by TYPE. If TYPE does not contain Field,
776 the module will not compile.
777
778 @param TYPE The name of the data structure that contains the field specified by Field.
779 @param Field The name of the field in the data structure.
780
781 @return Offset, in bytes, of field.
782
783 **/
784 #if (defined(__GNUC__) && __GNUC__ >= 4) || defined(__clang__)
785 #define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
786 #endif
787
788 #ifndef OFFSET_OF
789 #define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
790 #endif
791
792 /**
793 Portable definition for compile time assertions.
794 Equivalent to C11 static_assert macro from assert.h.
795
796 @param Expression Boolean expression.
797 @param Message Raised compiler diagnostic message when expression is false.
798
799 **/
800 #ifdef MDE_CPU_EBC
801 #define STATIC_ASSERT(Expression, Message)
802 #elif defined(_MSC_EXTENSIONS)
803 #define STATIC_ASSERT static_assert
804 #else
805 #define STATIC_ASSERT _Static_assert
806 #endif
807
808 //
809 // Verify that ProcessorBind.h produced UEFI Data Types that are compliant with
810 // Section 2.3.1 of the UEFI 2.3 Specification.
811 //
812
813 STATIC_ASSERT (sizeof (BOOLEAN) == 1, "sizeof (BOOLEAN) does not meet UEFI Specification Data Type requirements");
814 STATIC_ASSERT (sizeof (INT8) == 1, "sizeof (INT8) does not meet UEFI Specification Data Type requirements");
815 STATIC_ASSERT (sizeof (UINT8) == 1, "sizeof (UINT8) does not meet UEFI Specification Data Type requirements");
816 STATIC_ASSERT (sizeof (INT16) == 2, "sizeof (INT16) does not meet UEFI Specification Data Type requirements");
817 STATIC_ASSERT (sizeof (UINT16) == 2, "sizeof (UINT16) does not meet UEFI Specification Data Type requirements");
818 STATIC_ASSERT (sizeof (INT32) == 4, "sizeof (INT32) does not meet UEFI Specification Data Type requirements");
819 STATIC_ASSERT (sizeof (UINT32) == 4, "sizeof (UINT32) does not meet UEFI Specification Data Type requirements");
820 STATIC_ASSERT (sizeof (INT64) == 8, "sizeof (INT64) does not meet UEFI Specification Data Type requirements");
821 STATIC_ASSERT (sizeof (UINT64) == 8, "sizeof (UINT64) does not meet UEFI Specification Data Type requirements");
822 STATIC_ASSERT (sizeof (CHAR8) == 1, "sizeof (CHAR8) does not meet UEFI Specification Data Type requirements");
823 STATIC_ASSERT (sizeof (CHAR16) == 2, "sizeof (CHAR16) does not meet UEFI Specification Data Type requirements");
824 STATIC_ASSERT (sizeof (L'A') == 2, "sizeof (L'A') does not meet UEFI Specification Data Type requirements");
825 STATIC_ASSERT (sizeof (L"A") == 4, "sizeof (L\"A\") does not meet UEFI Specification Data Type requirements");
826
827 //
828 // The following three enum types are used to verify that the compiler
829 // configuration for enum types is compliant with Section 2.3.1 of the
830 // UEFI 2.3 Specification. These enum types and enum values are not
831 // intended to be used. A prefix of '__' is used avoid conflicts with
832 // other types.
833 //
834 typedef enum {
835 __VerifyUint8EnumValue = 0xff
836 } __VERIFY_UINT8_ENUM_SIZE;
837
838 typedef enum {
839 __VerifyUint16EnumValue = 0xffff
840 } __VERIFY_UINT16_ENUM_SIZE;
841
842 typedef enum {
843 __VerifyUint32EnumValue = 0xffffffff
844 } __VERIFY_UINT32_ENUM_SIZE;
845
846 STATIC_ASSERT (sizeof (__VERIFY_UINT8_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
847 STATIC_ASSERT (sizeof (__VERIFY_UINT16_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
848 STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
849
850 /**
851 Macro that returns a pointer to the data structure that contains a specified field of
852 that data structure. This is a lightweight method to hide information by placing a
853 public data structure inside a larger private data structure and using a pointer to
854 the public data structure to retrieve a pointer to the private data structure.
855
856 This function computes the offset, in bytes, of field specified by Field from the beginning
857 of the data structure specified by TYPE. This offset is subtracted from Record, and is
858 used to return a pointer to a data structure of the type specified by TYPE. If the data type
859 specified by TYPE does not contain the field specified by Field, then the module will not compile.
860
861 @param Record Pointer to the field specified by Field within a data structure of type TYPE.
862 @param TYPE The name of the data structure type to return. This data structure must
863 contain the field specified by Field.
864 @param Field The name of the field in the data structure specified by TYPE to which Record points.
865
866 @return A pointer to the structure from one of it's elements.
867
868 **/
869 #define BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))
870
871 /**
872 Rounds a value up to the next boundary using a specified alignment.
873
874 This function rounds Value up to the next boundary using the specified Alignment.
875 This aligned value is returned.
876
877 @param Value The value to round up.
878 @param Alignment The alignment boundary used to return the aligned value.
879
880 @return A value up to the next boundary.
881
882 **/
883 #define ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))
884
885 /**
886 Adjust a pointer by adding the minimum offset required for it to be aligned on
887 a specified alignment boundary.
888
889 This function rounds the pointer specified by Pointer to the next alignment boundary
890 specified by Alignment. The pointer to the aligned address is returned.
891
892 @param Pointer The pointer to round up.
893 @param Alignment The alignment boundary to use to return an aligned pointer.
894
895 @return Pointer to the aligned address.
896
897 **/
898 #define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))
899
900 /**
901 Rounds a value up to the next natural boundary for the current CPU.
902 This is 4-bytes for 32-bit CPUs and 8-bytes for 64-bit CPUs.
903
904 This function rounds the value specified by Value up to the next natural boundary for the
905 current CPU. This rounded value is returned.
906
907 @param Value The value to round up.
908
909 @return Rounded value specified by Value.
910
911 **/
912 #define ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN))
913
914
915 /**
916 Return the maximum of two operands.
917
918 This macro returns the maximum of two operand specified by a and b.
919 Both a and b must be the same numerical types, signed or unsigned.
920
921 @param a The first operand with any numerical type.
922 @param b The second operand. Can be any numerical type as long as is
923 the same type as a.
924
925 @return Maximum of two operands.
926
927 **/
928 #define MAX(a, b) \
929 (((a) > (b)) ? (a) : (b))
930
931 /**
932 Return the minimum of two operands.
933
934 This macro returns the minimal of two operand specified by a and b.
935 Both a and b must be the same numerical types, signed or unsigned.
936
937 @param a The first operand with any numerical type.
938 @param b The second operand. It should be the same any numerical type with a.
939
940 @return Minimum of two operands.
941
942 **/
943 #define MIN(a, b) \
944 (((a) < (b)) ? (a) : (b))
945
946 /**
947 Return the absolute value of a signed operand.
948
949 This macro returns the absolute value of the signed operand specified by a.
950
951 @param a The signed operand.
952
953 @return The absolute value of the signed operand.
954
955 **/
956 #define ABS(a) \
957 (((a) < 0) ? (-(a)) : (a))
958
959 //
960 // Status codes common to all execution phases
961 //
962 typedef UINTN RETURN_STATUS;
963
964 /**
965 Produces a RETURN_STATUS code with the highest bit set.
966
967 @param StatusCode The status code value to convert into a warning code.
968 StatusCode must be in the range 0x00000000..0x7FFFFFFF.
969
970 @return The value specified by StatusCode with the highest bit set.
971
972 **/
973 #define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))
974
975 /**
976 Produces a RETURN_STATUS code with the highest bit clear.
977
978 @param StatusCode The status code value to convert into a warning code.
979 StatusCode must be in the range 0x00000000..0x7FFFFFFF.
980
981 @return The value specified by StatusCode with the highest bit clear.
982
983 **/
984 #define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))
985
986 /**
987 Returns TRUE if a specified RETURN_STATUS code is an error code.
988
989 This function returns TRUE if StatusCode has the high bit set. Otherwise, FALSE is returned.
990
991 @param StatusCode The status code value to evaluate.
992
993 @retval TRUE The high bit of StatusCode is set.
994 @retval FALSE The high bit of StatusCode is clear.
995
996 **/
997 #define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)
998
999 ///
1000 /// The operation completed successfully.
1001 ///
1002 #define RETURN_SUCCESS 0
1003
1004 ///
1005 /// The image failed to load.
1006 ///
1007 #define RETURN_LOAD_ERROR ENCODE_ERROR (1)
1008
1009 ///
1010 /// The parameter was incorrect.
1011 ///
1012 #define RETURN_INVALID_PARAMETER ENCODE_ERROR (2)
1013
1014 ///
1015 /// The operation is not supported.
1016 ///
1017 #define RETURN_UNSUPPORTED ENCODE_ERROR (3)
1018
1019 ///
1020 /// The buffer was not the proper size for the request.
1021 ///
1022 #define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)
1023
1024 ///
1025 /// The buffer was not large enough to hold the requested data.
1026 /// The required buffer size is returned in the appropriate
1027 /// parameter when this error occurs.
1028 ///
1029 #define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)
1030
1031 ///
1032 /// There is no data pending upon return.
1033 ///
1034 #define RETURN_NOT_READY ENCODE_ERROR (6)
1035
1036 ///
1037 /// The physical device reported an error while attempting the
1038 /// operation.
1039 ///
1040 #define RETURN_DEVICE_ERROR ENCODE_ERROR (7)
1041
1042 ///
1043 /// The device can not be written to.
1044 ///
1045 #define RETURN_WRITE_PROTECTED ENCODE_ERROR (8)
1046
1047 ///
1048 /// The resource has run out.
1049 ///
1050 #define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)
1051
1052 ///
1053 /// An inconsistency was detected on the file system causing the
1054 /// operation to fail.
1055 ///
1056 #define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)
1057
1058 ///
1059 /// There is no more space on the file system.
1060 ///
1061 #define RETURN_VOLUME_FULL ENCODE_ERROR (11)
1062
1063 ///
1064 /// The device does not contain any medium to perform the
1065 /// operation.
1066 ///
1067 #define RETURN_NO_MEDIA ENCODE_ERROR (12)
1068
1069 ///
1070 /// The medium in the device has changed since the last
1071 /// access.
1072 ///
1073 #define RETURN_MEDIA_CHANGED ENCODE_ERROR (13)
1074
1075 ///
1076 /// The item was not found.
1077 ///
1078 #define RETURN_NOT_FOUND ENCODE_ERROR (14)
1079
1080 ///
1081 /// Access was denied.
1082 ///
1083 #define RETURN_ACCESS_DENIED ENCODE_ERROR (15)
1084
1085 ///
1086 /// The server was not found or did not respond to the request.
1087 ///
1088 #define RETURN_NO_RESPONSE ENCODE_ERROR (16)
1089
1090 ///
1091 /// A mapping to the device does not exist.
1092 ///
1093 #define RETURN_NO_MAPPING ENCODE_ERROR (17)
1094
1095 ///
1096 /// A timeout time expired.
1097 ///
1098 #define RETURN_TIMEOUT ENCODE_ERROR (18)
1099
1100 ///
1101 /// The protocol has not been started.
1102 ///
1103 #define RETURN_NOT_STARTED ENCODE_ERROR (19)
1104
1105 ///
1106 /// The protocol has already been started.
1107 ///
1108 #define RETURN_ALREADY_STARTED ENCODE_ERROR (20)
1109
1110 ///
1111 /// The operation was aborted.
1112 ///
1113 #define RETURN_ABORTED ENCODE_ERROR (21)
1114
1115 ///
1116 /// An ICMP error occurred during the network operation.
1117 ///
1118 #define RETURN_ICMP_ERROR ENCODE_ERROR (22)
1119
1120 ///
1121 /// A TFTP error occurred during the network operation.
1122 ///
1123 #define RETURN_TFTP_ERROR ENCODE_ERROR (23)
1124
1125 ///
1126 /// A protocol error occurred during the network operation.
1127 ///
1128 #define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)
1129
1130 ///
1131 /// A function encountered an internal version that was
1132 /// incompatible with a version requested by the caller.
1133 ///
1134 #define RETURN_INCOMPATIBLE_VERSION ENCODE_ERROR (25)
1135
1136 ///
1137 /// The function was not performed due to a security violation.
1138 ///
1139 #define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)
1140
1141 ///
1142 /// A CRC error was detected.
1143 ///
1144 #define RETURN_CRC_ERROR ENCODE_ERROR (27)
1145
1146 ///
1147 /// The beginning or end of media was reached.
1148 ///
1149 #define RETURN_END_OF_MEDIA ENCODE_ERROR (28)
1150
1151 ///
1152 /// The end of the file was reached.
1153 ///
1154 #define RETURN_END_OF_FILE ENCODE_ERROR (31)
1155
1156 ///
1157 /// The language specified was invalid.
1158 ///
1159 #define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)
1160
1161 ///
1162 /// The security status of the data is unknown or compromised
1163 /// and the data must be updated or replaced to restore a valid
1164 /// security status.
1165 ///
1166 #define RETURN_COMPROMISED_DATA ENCODE_ERROR (33)
1167
1168 ///
1169 /// A HTTP error occurred during the network operation.
1170 ///
1171 #define RETURN_HTTP_ERROR ENCODE_ERROR (35)
1172
1173 ///
1174 /// The string contained one or more characters that
1175 /// the device could not render and were skipped.
1176 ///
1177 #define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)
1178
1179 ///
1180 /// The handle was closed, but the file was not deleted.
1181 ///
1182 #define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)
1183
1184 ///
1185 /// The handle was closed, but the data to the file was not
1186 /// flushed properly.
1187 ///
1188 #define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)
1189
1190 ///
1191 /// The resulting buffer was too small, and the data was
1192 /// truncated to the buffer size.
1193 ///
1194 #define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)
1195
1196 ///
1197 /// The data has not been updated within the timeframe set by
1198 /// local policy for this type of data.
1199 ///
1200 #define RETURN_WARN_STALE_DATA ENCODE_WARNING (5)
1201
1202 ///
1203 /// The resulting buffer contains UEFI-compliant file system.
1204 ///
1205 #define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)
1206
1207
1208 /**
1209 Returns a 16-bit signature built from 2 ASCII characters.
1210
1211 This macro returns a 16-bit value built from the two ASCII characters specified
1212 by A and B.
1213
1214 @param A The first ASCII character.
1215 @param B The second ASCII character.
1216
1217 @return A 16-bit value built from the two ASCII characters specified by A and B.
1218
1219 **/
1220 #define SIGNATURE_16(A, B) ((A) | (B << 8))
1221
1222 /**
1223 Returns a 32-bit signature built from 4 ASCII characters.
1224
1225 This macro returns a 32-bit value built from the four ASCII characters specified
1226 by A, B, C, and D.
1227
1228 @param A The first ASCII character.
1229 @param B The second ASCII character.
1230 @param C The third ASCII character.
1231 @param D The fourth ASCII character.
1232
1233 @return A 32-bit value built from the two ASCII characters specified by A, B,
1234 C and D.
1235
1236 **/
1237 #define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16))
1238
1239 /**
1240 Returns a 64-bit signature built from 8 ASCII characters.
1241
1242 This macro returns a 64-bit value built from the eight ASCII characters specified
1243 by A, B, C, D, E, F, G,and H.
1244
1245 @param A The first ASCII character.
1246 @param B The second ASCII character.
1247 @param C The third ASCII character.
1248 @param D The fourth ASCII character.
1249 @param E The fifth ASCII character.
1250 @param F The sixth ASCII character.
1251 @param G The seventh ASCII character.
1252 @param H The eighth ASCII character.
1253
1254 @return A 64-bit value built from the two ASCII characters specified by A, B,
1255 C, D, E, F, G and H.
1256
1257 **/
1258 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \
1259 (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
1260
1261 #if defined(_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)
1262 void * _ReturnAddress(void);
1263 #pragma intrinsic(_ReturnAddress)
1264 /**
1265 Get the return address of the calling function.
1266
1267 Based on intrinsic function _ReturnAddress that provides the address of
1268 the instruction in the calling function that will be executed after
1269 control returns to the caller.
1270
1271 @param L Return Level.
1272
1273 @return The return address of the calling function or 0 if L != 0.
1274
1275 **/
1276 #define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0)
1277 #elif defined (__GNUC__) || defined (__clang__)
1278 /**
1279 Get the return address of the calling function.
1280
1281 Based on built-in Function __builtin_return_address that returns
1282 the return address of the current function, or of one of its callers.
1283
1284 @param L Return Level.
1285
1286 @return The return address of the calling function.
1287
1288 **/
1289 #define RETURN_ADDRESS(L) __builtin_return_address (L)
1290 #else
1291 /**
1292 Get the return address of the calling function.
1293
1294 @param L Return Level.
1295
1296 @return 0 as compilers don't support this feature.
1297
1298 **/
1299 #define RETURN_ADDRESS(L) ((VOID *) 0)
1300 #endif
1301
1302 /**
1303 Return the number of elements in an array.
1304
1305 @param Array An object of array type. Array is only used as an argument to
1306 the sizeof operator, therefore Array is never evaluated. The
1307 caller is responsible for ensuring that Array's type is not
1308 incomplete; that is, Array must have known constant size.
1309
1310 @return The number of elements in Array. The result has type UINTN.
1311
1312 **/
1313 #define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))
1314
1315 #endif
1316
IPv4_ADDRESS
4-byte buffer.
Definition: Base.h:232
BASE_LIST
UINTN * BASE_LIST
Pointer to the start of a variable argument list stored in a memory buffer.
Definition: Base.h:742
IPv6_ADDRESS
16-byte buffer.
Definition: Base.h:239
VA_LIST
CHAR8 * VA_LIST
Variable used to traverse the list of arguments.
Definition: Base.h:674
STATIC_ASSERT
#define STATIC_ASSERT
Portable definition for compile time assertions.
Definition: Base.h:805
_LIST_ENTRY
_LIST_ENTRY structure definition.
Definition: Base.h:256
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: BiosGuardConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • BiosGuard
Classes | Macros | Typedefs | Enumerations | Variables
BiosGuardConfig.h File Reference

CPU BIOS Guard Config Block. More...

#include <BiosGuard.h>
Include dependency graph for BiosGuardConfig.h:

Go to the source code of this file.

Classes

struct BIOS_GUARD_CONFIG
BIOS Guard Configuration Structure. More...

Macros

#define BIOS_GUARD_CONFIG_REVISION 1
BIOS Guard Configuration Revision.

Typedefs

typedef EFI_STATUS(* PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData)
This function is for platform code to provide EC Commands since different BIOS might have different EC. More...

Enumerations

enum EC_COMMAND_TYPE
Enums for EC Command Type.

Variables

EFI_GUID gBiosGuardConfigGuid
BIOS Guard Configuration GUID.

Detailed Description

CPU BIOS Guard Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file BiosGuardConfig.h.

Typedef Documentation

◆ PLATFORM_SEND_EC_COMMAND

typedef EFI_STATUS( * PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData)

This function is for platform code to provide EC Commands since different BIOS might have different EC.

Platform code need to provide a function for CPU code to call to communicate with EC.

Parameters
[in] | EcCmdType | - EC Command Type.
[in] | EcCmd | - EC Command Byte to send.
[in] | SendData | - EC Data Byte to send.
[in] | ReceiveData | - EC Data Byte received.
Return values
EFI_SUCCESS | Command Read/ Write Success.
EFI_DEVICE_ERROR | Command Read/ Write Error.
EFI_OUT_OF_RESOURCES | No enough resources (such as out of memory).

Definition at line 93 of file BiosGuardConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: BiosGuardConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • BiosGuard
BiosGuardConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU BIOS Guard Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _BIOS_GUARD_CONFIG_H_
36 #define _BIOS_GUARD_CONFIG_H_
37
38 #include <BiosGuard.h>
39
40 #define BIOS_GUARD_CONFIG_REVISION 1 ///< BIOS Guard Configuration Revision
41
42 extern EFI_GUID gBiosGuardConfigGuid; ///< BIOS Guard Configuration GUID
43
44 #pragma pack (push,1)
45
46 /**
47 BIOS Guard Configuration Structure.
48 Platform policies for BIOS Guard Configuration for all processor security features configuration.
49 Platform code can pass relevant configuration data through this structure.
50 @note <b>Optional.</b> These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> BiosGuard is disabled, or PeiBiosGuardLibNull is used.
51
52 <b>Revision 1</b>:
53 - Initial version.
54 **/
55 typedef struct {
56 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
57 BIOSGUARD_ATTRIBUTES BiosGuardAttr; ///< BIT1 - EC Present, BIT2 - EC BIOS Guard protection, BIT3 - Descriptor Override policy, BIT4 - Flash wearout protection, BIT5 - FTU enable
58 UINT64 BgpdtHash[4]; ///< Hash of the BGPDT that will be programmed to PLAT_FRMW_PROT_HASH_0/1/2/3 MSR.
59 EFI_PHYSICAL_ADDRESS BiosGuardModulePtr; ///< Pointer to the BIOS Guard Module.
60 EFI_PHYSICAL_ADDRESS SendEcCmd; ///< Platform code can provide interface to communicate with EC through this function.
61 UINT8 EcCmdProvisionEav; ///< EC Command Provision Eav.
62 UINT8 EcCmdLock; ///< EC Command Lock.
63
64 // Since the biggest element is UINT64, this structure should be aligned with 64 bits.
65 UINT8 Reserved[6]; ///< Reserved for future use and config block alignment.
66 } BIOS_GUARD_CONFIG;
67 #pragma pack (pop)
68
69 ///
70 /// Enums for EC Command Type
71 ///
72 typedef enum {
73 SendEcCmds = 1,
74 SendEcValue,
75 ReceiveEcValue,
76 EcCmdMax
77 } EC_COMMAND_TYPE;
78
79 /**
80 This function is for platform code to provide EC Commands since different BIOS might have different EC.
81 Platform code need to provide a function for CPU code to call to communicate with EC.
82
83 @param[in] EcCmdType - EC Command Type.
84 @param[in] EcCmd - EC Command Byte to send.
85 @param[in] SendData - EC Data Byte to send.
86 @param[in] ReceiveData - EC Data Byte received.
87
88 @retval EFI_SUCCESS Command Read/ Write Success.
89 @retval EFI_DEVICE_ERROR Command Read/ Write Error.
90 @retval EFI_OUT_OF_RESOURCES No enough resources (such as out of memory).
91 **/
92 typedef
93 EFI_STATUS
94 (EFIAPI *PLATFORM_SEND_EC_COMMAND) (
95 IN EC_COMMAND_TYPE EcCmdType,
96 IN UINT8 EcCmd,
97 IN UINT8 SendData,
98 IN OUT UINT8 *ReceiveData
99 );
100
101 #endif // _BIOS_GUARD_CONFIG_H_
IN
#define IN
Datum is passed to the function.
Definition: Base.h:288
BIOS_GUARD_CONFIG::BiosGuardModulePtr
EFI_PHYSICAL_ADDRESS BiosGuardModulePtr
Pointer to the BIOS Guard Module.
Definition: BiosGuardConfig.h:59
BIOS_GUARD_CONFIG::EcCmdProvisionEav
UINT8 EcCmdProvisionEav
EC Command Provision Eav.
Definition: BiosGuardConfig.h:61
EC_COMMAND_TYPE
EC_COMMAND_TYPE
Enums for EC Command Type.
Definition: BiosGuardConfig.h:72
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
BIOS_GUARD_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: BiosGuardConfig.h:56
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
OUT
#define OUT
Datum is returned from the function.
Definition: Base.h:293
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
BIOS_GUARD_CONFIG::EcCmdLock
UINT8 EcCmdLock
EC Command Lock.
Definition: BiosGuardConfig.h:62
gBiosGuardConfigGuid
EFI_GUID gBiosGuardConfigGuid
BIOS Guard Configuration GUID.
BIOS_GUARD_CONFIG
BIOS Guard Configuration Structure.
Definition: BiosGuardConfig.h:55
PLATFORM_SEND_EC_COMMAND
EFI_STATUS(* PLATFORM_SEND_EC_COMMAND)(IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData)
This function is for platform code to provide EC Commands since different BIOS might have different E...
Definition: BiosGuardConfig.h:94
BIOS_GUARD_CONFIG::BiosGuardAttr
BIOSGUARD_ATTRIBUTES BiosGuardAttr
BIT1 - EC Present, BIT2 - EC BIOS Guard protection, BIT3 - Descriptor Override policy,...
Definition: BiosGuardConfig.h:57
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
BIOS_GUARD_CONFIG::SendEcCmd
EFI_PHYSICAL_ADDRESS SendEcCmd
Platform code can provide interface to communicate with EC through this function.
Definition: BiosGuardConfig.h:60
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CnviConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
Classes | Enumerations
CnviConfig.h File Reference

CNVi policy. More...

Go to the source code of this file.

Classes

struct | CNVI_PIN_MUX
CNVi signals pin muxing settings. More...
struct | CNVI_CONFIG
The CNVI_CONFIG block describes the expected configuration of the CNVi IP. More...
struct | CNVI_PREMEM_CONFIG
The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP. More...

Enumerations

enum CNVI_MODE
CNVi Mode options.

Detailed Description

CNVi policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CnviConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CnviConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
CnviConfig.h
Go to the documentation of this file.
1 /** @file
2 CNVi policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CNVI_CONFIG_H_
36 #define _CNVI_CONFIG_H_
37
38 #define CNVI_CONFIG_REVISION 4
39 extern EFI_GUID gCnviConfigGuid;
40
41 #define CNVI_PREMEM_CONFIG_REVISION 1
42 extern EFI_GUID gCnviPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 /**
47 CNVi Mode options
48 **/
49 typedef enum {
50 CnviModeDisabled = 0,
51 CnviModeAuto
52 } CNVI_MODE;
53
54
55 /**
56 CNVi signals pin muxing settings. If signal can be enable only on a single pin
57 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in GpioPins*.h
58 for supported settings on a given platform
59 **/
60 typedef struct {
61 UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*
62 UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*
63 } CNVI_PIN_MUX;
64
65 /**
66 The CNVI_CONFIG block describes the expected configuration of the CNVi IP.
67
68 <b>Revision 1</b>: - Initial version.
69 <b>Revision 2</b>: - Add DdrRfim.
70 <b>Revision 3</b>: - Add WifiCore.
71 <b>Revision 4</b>: - Move DdrRfim to Pre-Mem config.
72 **/
73 typedef struct {
74 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
75 /**
76 This option allows for automatic detection of Connectivity Solution.
77 Auto Detection assumes that CNVi will be enabled when available;
78 Disable allows for disabling CNVi.
79 CnviModeDisabled = Disabled,
80 <b>CnviModeAuto = Auto Detection</b>
81 **/
82 UINT32 Mode : 1;
83 UINT32 BtCore : 1; ///< The option to turn ON or OFF the BT Core. 0: Disabled, <b>1: Enabled</b>
84 /**
85 The option to enable or disable BT Audio Offload.
86 <b>0: Disabled</b>, 1: Enabled
87 @note This feature only support with Intel(R) Wireless-AX 22560
88 **/
89 UINT32 BtAudioOffload : 1;
90 UINT32 WifiCore : 1; ///< The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, <b>1: Enabled</b>
91 UINT32 RsvdBits : 28;
92 /**
93 CNVi PinMux Configuration
94 RESET#/CLKREQ to CRF, can have two alternative mappings, depending on board routing requirements.
95 **/
96 CNVI_PIN_MUX PinMux;
97 } CNVI_CONFIG;
98
99
100 /**
101 The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.
102
103 <b>Revision 1</b>: - Initial version.
104 **/
105 typedef struct {
106 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
107 UINT8 DdrRfim; ///< The option to enable or disable DDR RFI Mitigation. 0: Disabled, <b>1: Enabled</b>
108 UINT8 RsvdByte[3];
109 } CNVI_PREMEM_CONFIG;
110
111 #pragma pack (pop)
112
113 #endif // _CNVI_CONFIG_H_
CNVI_CONFIG::PinMux
CNVI_PIN_MUX PinMux
CNVi PinMux Configuration RESET#/CLKREQ to CRF, can have two alternative mappings,...
Definition: CnviConfig.h:96
CNVI_CONFIG::Mode
UINT32 Mode
This option allows for automatic detection of Connectivity Solution.
Definition: CnviConfig.h:82
CNVI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CnviConfig.h:106
CNVI_CONFIG::BtCore
UINT32 BtCore
The option to turn ON or OFF the BT Core. 0: Disabled, 1: Enabled
Definition: CnviConfig.h:83
CNVI_PIN_MUX::Clkreq
UINT32 Clkreq
CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*.
Definition: CnviConfig.h:62
CNVI_CONFIG::WifiCore
UINT32 WifiCore
The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, 1: Enabled
Definition: CnviConfig.h:90
CNVI_PREMEM_CONFIG::DdrRfim
UINT8 DdrRfim
The option to enable or disable DDR RFI Mitigation. 0: Disabled, 1: Enabled
Definition: CnviConfig.h:107
CNVI_CONFIG
The CNVI_CONFIG block describes the expected configuration of the CNVi IP.
Definition: CnviConfig.h:73
CNVI_PIN_MUX
CNVi signals pin muxing settings.
Definition: CnviConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CNVI_PIN_MUX::RfReset
UINT32 RfReset
RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*.
Definition: CnviConfig.h:61
CNVI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CnviConfig.h:74
CNVI_MODE
CNVI_MODE
CNVi Mode options.
Definition: CnviConfig.h:49
CNVI_CONFIG::BtAudioOffload
UINT32 BtAudioOffload
The option to enable or disable BT Audio Offload.
Definition: CnviConfig.h:89
CNVI_PREMEM_CONFIG
The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.
Definition: CnviConfig.h:105
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Typedefs
ConfigBlock.h File Reference

Header file for Config Block Lib implementation. More...

#include <Uefi/UefiBaseType.h>
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
Include dependency graph for ConfigBlock.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _CONFIG_BLOCK_HEADER
Config Block Header. More...
struct | _CONFIG_BLOCK
Config Block. More...
struct | _CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header. More...

Typedefs

typedef struct _CONFIG_BLOCK_HEADER | CONFIG_BLOCK_HEADER
Config Block Header.
typedef struct _CONFIG_BLOCK | CONFIG_BLOCK
Config Block.
typedef struct _CONFIG_BLOCK_TABLE_STRUCT | CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.

Detailed Description

Header file for Config Block Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ConfigBlock.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock.h Source File

  • Intel
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ConfigBlock.h
Go to the documentation of this file.
1 /** @file
2 Header file for Config Block Lib implementation
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _CONFIG_BLOCK_H_
18 #define _CONFIG_BLOCK_H_
19
20 #include <Uefi/UefiBaseType.h>
21 #include <Uefi/UefiMultiPhase.h>
22 #include <Pi/PiBootMode.h>
23 #include <Pi/PiHob.h>
24
25 #pragma pack (push,1)
26
27 ///
28 /// Config Block Header
29 ///
30 typedef struct _CONFIG_BLOCK_HEADER {
31 EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
32 UINT8 Revision; ///< Offset 24 Revision of this config block
33 UINT8 Attributes; ///< Offset 25 The main revision for config block
34 UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
35 } CONFIG_BLOCK_HEADER;
36
37 ///
38 /// Config Block
39 ///
40 typedef struct _CONFIG_BLOCK {
41 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
42 //
43 // Config Block Data
44 //
45 } CONFIG_BLOCK;
46
47 ///
48 /// Config Block Table Header
49 ///
50 typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
51 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
52 UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
53 UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
54 UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
55 ///
56 /// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
57 ///
58 } CONFIG_BLOCK_TABLE_HEADER;
59 #pragma pack (pop)
60
61 #endif // _CONFIG_BLOCK_H_
62
CONFIG_BLOCK_HEADER
struct _CONFIG_BLOCK_HEADER CONFIG_BLOCK_HEADER
Config Block Header.
UefiBaseType.h
Defines data types and constants introduced in UEFI.
CONFIG_BLOCK
struct _CONFIG_BLOCK CONFIG_BLOCK
Config Block.
_CONFIG_BLOCK_HEADER::Reserved
UINT8 Reserved[2]
Offset 26-27 Reserved for future use.
Definition: ConfigBlock.h:34
_CONFIG_BLOCK_TABLE_STRUCT::NumberOfBlocks
UINT16 NumberOfBlocks
Offset 30-31 Number of config blocks (N)
Definition: ConfigBlock.h:53
_CONFIG_BLOCK_HEADER::Revision
UINT8 Revision
Offset 24 Revision of this config block.
Definition: ConfigBlock.h:32
_CONFIG_BLOCK_TABLE_STRUCT::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
Definition: ConfigBlock.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CONFIG_BLOCK_TABLE_HEADER
struct _CONFIG_BLOCK_TABLE_STRUCT CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.
_CONFIG_BLOCK::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Header of config block.
Definition: ConfigBlock.h:41
_CONFIG_BLOCK_HEADER::Attributes
UINT8 Attributes
Offset 25 The main revision for config block.
Definition: ConfigBlock.h:33
_CONFIG_BLOCK
Config Block.
Definition: ConfigBlock.h:40
_CONFIG_BLOCK_TABLE_STRUCT::Rsvd0
UINT8 Rsvd0[2]
Offset 28-29 Reserved for future use.
Definition: ConfigBlock.h:52
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:338
PiHob.h
HOB related definitions in PI.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_CONFIG_BLOCK_TABLE_STRUCT::AvailableSize
UINT32 AvailableSize
Offset 32-35 Current config block table size.
Definition: ConfigBlock.h:54
_CONFIG_BLOCK_HEADER::GuidHob
EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
Definition: ConfigBlock.h:31
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlockLib.h File Reference

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  • ClientOneSiliconPkg
  • Include
  • Library
Functions
ConfigBlockLib.h File Reference

Header file for Config Block Lib implementation. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | CreateConfigBlockTable (IN UINT16 TotalSize, OUT VOID **ConfigBlockTableAddress)
Create config block table. More...
EFI_STATUS | AddConfigBlock (IN VOID *ConfigBlockTableAddress, OUT VOID **ConfigBlockAddress)
Add config block into config block table structure. More...
EFI_STATUS | GetConfigBlock (IN VOID *ConfigBlockTableAddress, IN EFI_GUID *ConfigBlockGuid, OUT VOID **ConfigBlockAddress)
Retrieve a specific Config Block data by GUID. More...

Detailed Description

Header file for Config Block Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ConfigBlockLib.h.

Function Documentation

◆ AddConfigBlock()

EFI_STATUS AddConfigBlock | ( | IN VOID * | ConfigBlockTableAddress,
 |  | OUT VOID ** | ConfigBlockAddress
 | ) |  |

Add config block into config block table structure.

Parameters
[in] | ConfigBlockTableAddress | - A pointer to the beginning of Config Block Table Address
[out] | ConfigBlockAddress | - On return, points to a pointer to the beginning of Config Block Address
Return values
EFI_OUT_OF_RESOURCES | - Config Block Table is full and cannot add new Config Block or Config Block Offset Table is full and cannot add new Config Block.
EFI_SUCCESS | - Successfully added Config Block

◆ CreateConfigBlockTable()

EFI_STATUS CreateConfigBlockTable | ( | IN UINT16 | TotalSize,
 |  | OUT VOID ** | ConfigBlockTableAddress
 | ) |  |

Create config block table.

Parameters
[in] | TotalSize | - Max size to be allocated for the Config Block Table
[out] | ConfigBlockTableAddress | - On return, points to a pointer to the beginning of Config Block Table Address
Return values
EFI_INVALID_PARAMETER | - Invalid Parameter
EFI_OUT_OF_RESOURCES | - Out of resources
EFI_SUCCESS | - Successfully created Config Block Table at ConfigBlockTableAddress

◆ GetConfigBlock()

EFI_STATUS GetConfigBlock | ( | IN VOID * | ConfigBlockTableAddress,
 |  | IN EFI_GUID * | ConfigBlockGuid,
 |  | OUT VOID ** | ConfigBlockAddress
 | ) |  |

Retrieve a specific Config Block data by GUID.

Parameters
[in] | ConfigBlockTableAddress | - A pointer to the beginning of Config Block Table Address
[in] | ConfigBlockGuid | - A pointer to the GUID uses to search specific Config Block
[out] | ConfigBlockAddress | - On return, points to a pointer to the beginning of Config Block Address
Return values
EFI_NOT_FOUND | - Could not find the Config Block
EFI_SUCCESS | - Config Block found and return
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlockLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
ConfigBlockLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Config Block Lib implementation
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _CONFIG_BLOCK_LIB_H_
18 #define _CONFIG_BLOCK_LIB_H_
19
20 /**
21 Create config block table
22
23 @param[in] TotalSize - Max size to be allocated for the Config Block Table
24 @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
25
26 @retval EFI_INVALID_PARAMETER - Invalid Parameter
27 @retval EFI_OUT_OF_RESOURCES - Out of resources
28 @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
29 **/
30 EFI_STATUS
31 EFIAPI
32 CreateConfigBlockTable (
33 IN UINT16 TotalSize,
34 OUT VOID **ConfigBlockTableAddress
35 );
36
37 /**
38 Add config block into config block table structure
39
40 @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
41 @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
42
43 @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
44 Config Block Offset Table is full and cannot add new Config Block.
45 @retval EFI_SUCCESS - Successfully added Config Block
46 **/
47 EFI_STATUS
48 EFIAPI
49 AddConfigBlock (
50 IN VOID *ConfigBlockTableAddress,
51 OUT VOID **ConfigBlockAddress
52 );
53
54 /**
55 Retrieve a specific Config Block data by GUID
56
57 @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
58 @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
59 @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
60
61 @retval EFI_NOT_FOUND - Could not find the Config Block
62 @retval EFI_SUCCESS - Config Block found and return
63 **/
64 EFI_STATUS
65 EFIAPI
66 GetConfigBlock (
67 IN VOID *ConfigBlockTableAddress,
68 IN EFI_GUID *ConfigBlockGuid,
69 OUT VOID **ConfigBlockAddress
70 );
71
72 #endif // _CONFIG_BLOCK_LIB_H_
73
IN
#define IN
Datum is passed to the function.
Definition: Base.h:288
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
OUT
#define OUT
Datum is returned from the function.
Definition: Base.h:293
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
AddConfigBlock
EFI_STATUS AddConfigBlock(IN VOID *ConfigBlockTableAddress, OUT VOID **ConfigBlockAddress)
Add config block into config block table structure.
GetConfigBlock
EFI_STATUS GetConfigBlock(IN VOID *ConfigBlockTableAddress, IN EFI_GUID *ConfigBlockGuid, OUT VOID **ConfigBlockAddress)
Retrieve a specific Config Block data by GUID.
CreateConfigBlockTable
EFI_STATUS CreateConfigBlockTable(IN UINT16 TotalSize, OUT VOID **ConfigBlockTableAddress)
Create config block table.
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuConfig.h File Reference

  • Intel
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  • Cpu
  • Include
  • ConfigBlock
Classes
CpuConfig.h File Reference

CPU Config Block. More...

Go to the source code of this file.

Classes

struct CPU_CONFIG
CPU Configuration Structure. More...

Detailed Description

CPU Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_CONFIG_H_
36 #define _CPU_CONFIG_H_
37
38 #define CPU_CONFIG_REVISION 5
39
40 extern EFI_GUID gCpuConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 <b>Revision 2</b>:
50 - Add SmbiosType4MaxSpeedOverride.
51 <b>Revision 3</b>:
52 - Add AvxDisable & Avx3Disable.
53 <b>Revision 4</b>:
54 - Add X2ApicSupport.
55 <b>Revision 5</b>:
56 - Deprecate Avx3Disable
57 **/
58 typedef struct {
59 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
60 UINT32 MicrocodePatchRegionSize;
61 EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor.
62 /**
63 Enable or Disable Advanced Encryption Standard (AES) feature.
64 For some countries, this should be disabled for legal reasons.
65 - 0: Disable
66 - <b>1: Enable</b>
67 **/
68 UINT32 AesEnable : 1;
69 /**
70 Enable or Disable Trusted Execution Technology (TXT) feature.
71 - 0: Disable
72 - <b>1: Enable</b>
73 **/
74 UINT32 TxtEnable : 1;
75 UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
76 /**
77 Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number.
78 - <b>0: Disable</b>
79 - 1: Enable
80 - 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM is set, it is disabled.
81 **/
82 UINT32 PpinSupport : 2;
83 /**
84 Enable or Disable #AC machine check on split lock.
85 - <b>0: Disable</b>
86 - 1: Enable
87 **/
88 UINT32 AcSplitLock : 1;
89 /**
90 Enable or Disable Avx.
91 - 1: Disable
92 - <b> 0: Enable</b>
93 **/
94 UINT32 AvxDisable : 1;
95 /**
96 @deprecated
97 Enable or Disable Avx3.
98 - <b> 1: Disable</b>
99 - 0: Enable
100 **/
101 UINT32 Avx3Disable : 1;
102 /**
103 Enable or Disable X2APIC Support.
104 - <b>0: Disable</b>
105 - 1: Enable
106 **/
107 UINT32 X2ApicSupport : 1;
108 UINT32 RsvdBits : 23; ///< Reserved for future use
109 /**
110 Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
111 Value 4000 means 4000MHz.
112 If this value is not zero, it dominates the field.
113 If this value is zero, CPU RC will update the field according to the max radio.
114 <b>default is 0.</b>
115 **/
116 UINT16 SmbiosType4MaxSpeedOverride;
117 UINT8 Reserved0[2]; ///< Reserved for future use
118 } CPU_CONFIG;
119
120 #pragma pack (pop)
121
122 #endif // _CPU_CONFIG_H_
CPU_CONFIG::AvxDisable
UINT32 AvxDisable
Enable or Disable Avx.
Definition: CpuConfig.h:94
CPU_CONFIG::PpinSupport
UINT32 PpinSupport
Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number.
Definition: CpuConfig.h:82
CPU_CONFIG::AcSplitLock
UINT32 AcSplitLock
Enable or Disable #AC machine check on split lock.
Definition: CpuConfig.h:88
CPU_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuConfig.h:59
CPU_CONFIG::SkipMpInit
UINT32 SkipMpInit
For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled....
Definition: CpuConfig.h:75
CPU_CONFIG::MicrocodePatchAddress
EFI_PHYSICAL_ADDRESS MicrocodePatchAddress
Pointer to microcode patch that is suitable for this processor.
Definition: CpuConfig.h:61
CPU_CONFIG::TxtEnable
UINT32 TxtEnable
Enable or Disable Trusted Execution Technology (TXT) feature.
Definition: CpuConfig.h:74
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
CPU_CONFIG::X2ApicSupport
UINT32 X2ApicSupport
Enable or Disable X2APIC Support.
Definition: CpuConfig.h:107
CPU_CONFIG::AesEnable
UINT32 AesEnable
Enable or Disable Advanced Encryption Standard (AES) feature.
Definition: CpuConfig.h:68
CPU_CONFIG
CPU Configuration Structure.
Definition: CpuConfig.h:58
CPU_CONFIG::SmbiosType4MaxSpeedOverride
UINT16 SmbiosType4MaxSpeedOverride
Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
Definition: CpuConfig.h:116
CPU_CONFIG::Avx3Disable
UINT32 Avx3Disable
Definition: CpuConfig.h:101
CPU_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuConfig.h:108
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuConfigLibPreMemConfig.h File Reference

  • Intel
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Classes
CpuConfigLibPreMemConfig.h File Reference

CPU Security PreMemory Config Block. More...

Go to the source code of this file.

Classes

struct CPU_CONFIG_LIB_PREMEM_CONFIG
CPU Config Library PreMemory Configuration Structure. More...

Detailed Description

CPU Security PreMemory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2015 - 2021 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.
Specification Reference:

Definition in file CpuConfigLibPreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuConfigLibPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuConfigLibPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Security PreMemory Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2015 - 2021 Intel Corporation. All rights reserved
7 This software and associated documentation (if any) is furnished
8 under a license and may only be used or copied in accordance
9 with the terms of the license. Except as permitted by the
10 license, no part of this software or documentation may be
11 reproduced, stored in a retrieval system, or transmitted in any
12 form or by any means without the express written consent of
13 Intel Corporation.
14 This file contains an 'Intel Peripheral Driver' and is uniquely
15 identified as "Intel Reference Module" and is licensed for Intel
16 CPUs and chipsets under the terms of your license agreement with
17 Intel or your vendor. This file may be modified by the user, subject
18 to additional terms of the license agreement.
19
20 @par Specification Reference:
21 **/
22 #ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
23 #define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
24
25 #define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 11
26
27 extern EFI_GUID gCpuConfigLibPreMemConfigGuid;
28
29 #define BOOT_FREQUENCY_MAX_BATTERY_PERF 0
30 #define BOOT_FREQUENCY_MAX_NON_TURBO_PERF 1
31 #define BOOT_FREQUENCY_TURBO_PERF 2
32
33 #pragma pack (push,1)
34
35 /**
36 CPU Config Library PreMemory Configuration Structure.
37
38 <b>Revision 1</b>:
39 - Initial version.
40 <b>Revision 2</b>:
41 - Expand the supported number of processor cores (ActiveCoreCount1).
42 <b>Revision 3</b>:
43 - Added PECI Sx and C10 Reset.
44 <b>Revision 4</b>:
45 - Added ActiveSmallCoreCount.
46 <b>Revision 5</b>:
47 - Added CrashLogGprs
48 <b>Revision 6</b>:
49 - Added ActiveSocNorthAtomCoreCount
50 <b>Revision 7</b>:
51 - Added ComputeDieSscEnable, SocDieSscEnable, ComputeDieSscValue, and SocDieSscValue
52 <b>Revision 8</b>:
53 - Added BclkSource.
54 <b>Revision 9</b>:
55 - Removed Elixir Springs Patch
56 <b>Revision 10</b>
57 - Add InfDfxPwrEnable
58 <b>Revision 11</b>
59 - Add ConfigTdpLevel, CustomPowerLimit1
60 **/
61 typedef struct {
62 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
63 UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>.
64 /**
65 Sets the boot frequency starting from reset vector.
66 - 0: Maximum battery performance.
67 - 1: Maximum non-turbo performance
68 -<b>2: Turbo performance</b>.
69 @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
70 **/
71 UINT32 BootFrequency : 2;
72 /**
73 Number of processor cores to enable.
74 - <b> 0: All cores</b>
75 - 1: 1 core
76 - 2: 2 cores
77 - 3: 3 cores
78 **/
79 UINT32 ActiveCoreCount : 3; ///< @deprecated due to core active number limitaion.
80 UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. <b>0: False<\b>; 1: True.
81 UINT32 BistOnReset : 1; ///< <b>(Test)</b> Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
82 /**
83 Enable or Disable Virtual Machine Extensions (VMX) feature.
84 - 0: Disable
85 - <b>1: Enable</b>
86 **/
87 UINT32 VmxEnable : 1;
88 /**
89 Processor Early Power On Configuration FCLK setting.
90 - <b>0: 800 MHz (ULT/ULX)</b>.
91 - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
92 - 2: 400 MHz.
93 - 3: Reserved.
94 **/
95 UINT32 FClkFrequency : 2;
96 /**
97 Enable or Disable CrashLog feature
98 - 0: Disable
99 - <b>1: Enable</b>
100 **/
101 UINT32 CrashLogEnable : 1;
102
103 /**
104 Enable or Disable Total Memory Encryption (TME) feature.
105 - 0: Disable
106 - <b>1: Enable</b>
107 **/
108 UINT32 TmeEnable : 1;
109
110 UINT32 DebugInterfaceEnable : 2; ///< Enable or Disable processor debug features; 0: Disable; 1: Enable; <b>2: No Change</b>.
111 UINT32 DebugInterfaceLockEnable : 1; ///< Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
112
113 /**
114 Number of big cores in processor to enable.
115 And support up to 15 cores.
116 - 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 16).
117 - 1: 1 core
118 - 2: 2 cores
119 - 3: 3 cores
120 **/
121 UINT32 ActiveCoreCount1 : 4;
122
123 /**
124 Enables a mailbox command to resolve rare PECI related Sx issues.
125 @note This should only be used on systems that observe PECI Sx issues.
126 - <b>0: Disable</b>
127 - 1: Enable
128 **/
129 UINT32 PeciSxReset : 1;
130
131 /**
132 Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.
133 If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit.
134 The default value <b>0: Disable</b> for CPU's
135 - 0: Disable
136 - 1: Enable
137 **/
138 UINT32 PeciC10Reset : 1; ///< @deprecated no longer used.
139
140 /**
141 Number of small cores in processor to enable.
142 And support up to 63 cores.
143 - 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 64).
144 - 1: 1 core
145 - 2: 2 cores
146 - 3: 3 cores
147 **/
148 UINT32 ActiveSmallCoreCount : 6;
149
150 /**
151 Enable or Disable CrashLog GPRs dump
152 - <b>0: Disable</b>
153 - 1: Gprs Enabled, Smm Gprs Enabled
154 2: Gprs Enabled, Smm Gprs Disabled
155 **/
156 UINT32 CrashLogGprs : 2;
157
158 /**
159 Enable or Disable Compute Die SSC configuration.
160 - <b>0: Disable</b>
161 - 1: Enable
162 **/
163 UINT32 ComputeDieSscEnable : 1;
164
165 /**
166 Enable or Disable Soc Die SSC configuration.
167 - <b>0: Disable</b>
168 - 1: Enable
169 **/
170 UINT32 SocDieSscEnable : 1;
171
172 /**
173 CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio. <b>0: Disabled</b> If disabled, doesn't override max-non turbo ratio.
174 **/
175 UINT8 CpuRatio;
176
177 /**
178 Number of enabled atom cores on SoC.
179 Default is set to supported core number.
180 - 0 - all core disabled
181 - 1 - enable 1 core
182 - 2 - enable 2 cores
183 - others - reserved for future use
184 **/
185 UINT8 ActiveSocNorthAtomCoreCount;
186
187 /**
188 SSC configuration value of Compute Die.
189 SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.
190 - <b>0 : invalid</b>
191 - 1 : 0.01%
192 - 2 : 0.02%
193 - 100 : 1%
194 **/
195 UINT8 ComputeDieSscValue;
196
197 /**
198 SSC configuration value of Soc Die.
199 SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.
200 - <b>0 : invalid</b>
201 - 1 : 0.01%
202 - 2 : 0.02%
203 - 100 : 1%
204 **/
205 UINT8 SocDieSscValue;
206
207 /**
208 Clock source of BCLK OC Frequency
209 - 0: SOC
210 - <b>1: CPU</b>
211 - 2: PCH
212 - 3: Ext. Clock (optional)
213 **/
214 UINT32 BclkSource : 2;
215 UINT32 RsvdBits : 30;
216 /**
217 Determine whether to keep or shutdown INF_DFX power rail. INF_DFX power is up from cold boot.
218 - <b>0 : INF_DFX shutdown</b>
219 - 1 : INF_DFX power up </b>
220 **/
221 UINT8 InfDfxPwrEnable;
222 /**
223 Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up.
224 **/
225 UINT8 ConfigTdpLevel;
226 UINT8 RsvdByte[2];
227 UINT32 CustomPowerLimit1;
228
229 } CPU_CONFIG_LIB_PREMEM_CONFIG;
230
231 #pragma pack (pop)
232
233 #endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
CPU_CONFIG_LIB_PREMEM_CONFIG::DebugInterfaceLockEnable
UINT32 DebugInterfaceLockEnable
Lock or Unlock debug interface features; 0: Disable; 1: Enable.
Definition: CpuConfigLibPreMemConfig.h:111
CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogEnable
UINT32 CrashLogEnable
Enable or Disable CrashLog feature.
Definition: CpuConfigLibPreMemConfig.h:101
CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscEnable
UINT32 ComputeDieSscEnable
Enable or Disable Compute Die SSC configuration.
Definition: CpuConfigLibPreMemConfig.h:163
CPU_CONFIG_LIB_PREMEM_CONFIG::ConfigTdpLevel
UINT8 ConfigTdpLevel
Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up.
Definition: CpuConfigLibPreMemConfig.h:225
CPU_CONFIG_LIB_PREMEM_CONFIG
CPU Config Library PreMemory Configuration Structure.
Definition: CpuConfigLibPreMemConfig.h:61
CPU_CONFIG_LIB_PREMEM_CONFIG::VmxEnable
UINT32 VmxEnable
Enable or Disable Virtual Machine Extensions (VMX) feature.
Definition: CpuConfigLibPreMemConfig.h:87
CPU_CONFIG_LIB_PREMEM_CONFIG::BootFrequency
UINT32 BootFrequency
Sets the boot frequency starting from reset vector.
Definition: CpuConfigLibPreMemConfig.h:71
CPU_CONFIG_LIB_PREMEM_CONFIG::BclkSource
UINT32 BclkSource
Clock source of BCLK OC Frequency.
Definition: CpuConfigLibPreMemConfig.h:214
CPU_CONFIG_LIB_PREMEM_CONFIG::PeciC10Reset
UINT32 PeciC10Reset
Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.
Definition: CpuConfigLibPreMemConfig.h:138
CPU_CONFIG_LIB_PREMEM_CONFIG::BistOnReset
UINT32 BistOnReset
(Test) Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
Definition: CpuConfigLibPreMemConfig.h:81
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount
UINT32 ActiveCoreCount
Number of processor cores to enable.
Definition: CpuConfigLibPreMemConfig.h:79
CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscEnable
UINT32 SocDieSscEnable
Enable or Disable Soc Die SSC configuration.
Definition: CpuConfigLibPreMemConfig.h:170
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_CONFIG_LIB_PREMEM_CONFIG::TmeEnable
UINT32 TmeEnable
Enable or Disable Total Memory Encryption (TME) feature.
Definition: CpuConfigLibPreMemConfig.h:108
CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogGprs
UINT32 CrashLogGprs
Enable or Disable CrashLog GPRs dump.
Definition: CpuConfigLibPreMemConfig.h:156
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSmallCoreCount
UINT32 ActiveSmallCoreCount
Number of small cores in processor to enable.
Definition: CpuConfigLibPreMemConfig.h:148
CPU_CONFIG_LIB_PREMEM_CONFIG::PeciSxReset
UINT32 PeciSxReset
Enables a mailbox command to resolve rare PECI related Sx issues.
Definition: CpuConfigLibPreMemConfig.h:129
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount1
UINT32 ActiveCoreCount1
Number of big cores in processor to enable.
Definition: CpuConfigLibPreMemConfig.h:121
CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscValue
UINT8 ComputeDieSscValue
SSC configuration value of Compute Die.
Definition: CpuConfigLibPreMemConfig.h:195
CPU_CONFIG_LIB_PREMEM_CONFIG::DebugInterfaceEnable
UINT32 DebugInterfaceEnable
Enable or Disable processor debug features; 0: Disable; 1: Enable; 2: No Change.
Definition: CpuConfigLibPreMemConfig.h:110
CPU_CONFIG_LIB_PREMEM_CONFIG::CpuRatio
UINT8 CpuRatio
CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.
Definition: CpuConfigLibPreMemConfig.h:175
CPU_CONFIG_LIB_PREMEM_CONFIG::HyperThreading
UINT32 HyperThreading
Enable or Disable Hyper Threading; 0: Disable; 1: Enable.
Definition: CpuConfigLibPreMemConfig.h:63
CPU_CONFIG_LIB_PREMEM_CONFIG::InfDfxPwrEnable
UINT8 InfDfxPwrEnable
Determine whether to keep or shutdown INF_DFX power rail.
Definition: CpuConfigLibPreMemConfig.h:221
CPU_CONFIG_LIB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuConfigLibPreMemConfig.h:62
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSocNorthAtomCoreCount
UINT8 ActiveSocNorthAtomCoreCount
Number of enabled atom cores on SoC.
Definition: CpuConfigLibPreMemConfig.h:185
CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscValue
UINT8 SocDieSscValue
SSC configuration value of Soc Die.
Definition: CpuConfigLibPreMemConfig.h:205
CPU_CONFIG_LIB_PREMEM_CONFIG::FClkFrequency
UINT32 FClkFrequency
Processor Early Power On Configuration FCLK setting.
Definition: CpuConfigLibPreMemConfig.h:95
CPU_CONFIG_LIB_PREMEM_CONFIG::JtagC10PowerGateDisable
UINT32 JtagC10PowerGateDisable
False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power st...
Definition: CpuConfigLibPreMemConfig.h:80
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuDmiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuDmi
Classes | Enumerations
CpuDmiPreMemConfig.h File Reference

DMI policy. More...

#include <ConfigBlock.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for CpuDmiPreMemConfig.h:

Go to the source code of this file.

Classes

struct | CPU_DMI_EQ_PARAM
Represent lane specific Dmi Gen3 equalization parameters. More...
struct | CPU_DMI_PREMEM_CONFIG
The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI. More...

Enumerations

enum DMI_ASPM
The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature.

Detailed Description

DMI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuDmiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuDmiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuDmi
CpuDmiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 DMI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_DMI_PREMEM_CONFIG_H_
36 #define _CPU_DMI_PREMEM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <Register/SaRegsHostBridge.h>
40
41 #define CPU_DMI_PREMEM_CONFIG_REVISION 4
42
43 #define CPU_DMI_HWEQ_COEFFS_MAX 8
44
45 #pragma pack (push,1)
46 ///
47 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
48 ///
49 typedef enum {
50 DmiAspmDisabled,
51 DmiAspmL0s,
52 DmiAspmL1,
53 DmiAspmL0sL1,
54 DmiAspmAutoConfig,
55 DmiAspmMax
56 } DMI_ASPM;
57
58 /**
59 Represent lane specific Dmi Gen3 equalization parameters.
60 **/
61 typedef struct {
62 UINT8 Cm; ///< Coefficient C-1
63 UINT8 Cp; ///< Coefficient C+1
64 UINT8 Rsvd0[2]; ///< Reserved bytes
65 } CPU_DMI_EQ_PARAM;
66
67 /**
68 The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI.
69 <b>Revision 1</b>:
70 - Initial version.
71 <b>Revision 2</b>:
72 - Added Policies for Dmi Higer Speed Training.
73 <b>Revision 3</b>:
74 - Added DmiCdrRelock Policy.
75 **/
76 typedef struct {
77 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
78
79 /**
80 - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
81 - Gen1 (0x1) : Limit Link to Gen1 Speed
82 - Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig
83 - Gen3 (0x3) : Limit Link to Gen3 Speed
84 **/
85 UINT8 DmiMaxLinkSpeed;
86 /**
87 <b>(Test)</b> DMI Equalization Phase 2 Enable Control
88 - Disabled (0x0) : Disable phase 2
89 - Enabled (0x1) : Enable phase 2
90 - <b>Auto</b> (0x2) : Use the current default method (Default)
91 **/
92 UINT8 DmiGen3EqPh2Enable;
93 /**
94 <b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
95 - <b>Auto</b> (0x0) : Use the current default method (Default)
96 - HwEq (0x1) : Use Adaptive Hardware Equalization
97 - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
98 - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
99 - Disabled (0x4) : Bypass Equalization Phase 3
100 **/
101 UINT8 DmiGen3EqPh3Method;
102 /**
103 <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
104 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
105 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
106 **/
107 UINT8 DmiGen3ProgramStaticEq;
108 UINT8 DmiDeEmphasis; ///< DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
109 UINT8 DmiAspm;
110 UINT8 DmiAspmCtrl; ///< ASPM configuration on the CPU side of the DMI/OPI Link. Default is <b>DmiAspmAutoConfig</b>
111 UINT8 DmiAspmL1ExitLatency; ///< ASPM configuration on the CPU side of the DMI/OPI Link. Default is <b>DmiAspmAutoConfig</b>
112 UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
113 UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
114 UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
115
116 /**
117 DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
118 has to be specified based upon platform design and must follow the guideline. Default is 12.
119 **/
120
121 UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
122 UINT8 DmiGen3DsPortRxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
123 UINT8 DmiGen3DsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
124 UINT8 DmiGen3UsPortRxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
125 UINT8 DmiGen3UsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
126 UINT8 Gen3EqPhase23Bypass;
127 UINT8 Gen3EqPhase3Bypass;
128 UINT8 Gen3LtcoEnable;
129 UINT8 Gen3RtcoRtpoEnable;
130 UINT8 DmiGen3Ltcpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
131 UINT8 DmiGen3Ltcpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
132 UINT8 DmiGen3RtcoCpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
133 UINT8 DmiGen3RtcoCpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
134 CPU_DMI_EQ_PARAM DmiHwEqGen3CoeffList[CPU_DMI_HWEQ_COEFFS_MAX];
135 UINT8 DmiHweq;
136 UINT8 DmiGen3DsPresetEnable;
137 UINT8 DmiGen3UsPresetEnable;
138 UINT8 Rsvd0[1]; ///< Reserved bytes
139 CPU_DMI_EQ_PARAM DmiHwEqGen4CoeffList[CPU_DMI_HWEQ_COEFFS_MAX];
140 UINT8 Gen4EqPhase23Bypass;
141 UINT8 Gen4EqPhase3Bypass;
142 UINT8 DmiGen4DsPresetEnable;
143 UINT8 DmiGen4UsPresetEnable;
144 UINT8 Gen4RtcoRtpoEnable;
145 UINT8 Gen4LtcoEnable;
146 UINT8 DmiGen4Ltcpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
147 UINT8 DmiGen4Ltcpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
148 UINT8 DmiGen4DsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
149 UINT8 DmiGen4UsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
150 UINT8 DmiGen4RtcoCpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
151 UINT8 DmiGen4RtcoCpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
152 UINT8 DmiNewFom; ///< Used for programming DMI New FOM
153 UINT8 DmiCdrRelock; ///< Used for programming DMI CDR Relock
154 } CPU_DMI_PREMEM_CONFIG;
155
156 #pragma pack (pop)
157
158 #endif // _CPU_DMI_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
CPU_DMI_PREMEM_CONFIG::DmiGen3ProgramStaticEq
UINT8 DmiGen3ProgramStaticEq
(Test) Program DMI Gen3 EQ Phase1 Static Presets
Definition: CpuDmiPreMemConfig.h:107
CPU_DMI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuDmiPreMemConfig.h:77
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_DMI_PREMEM_CONFIG
The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI.
Definition: CpuDmiPreMemConfig.h:76
CPU_DMI_PREMEM_CONFIG::DmiAspmCtrl
UINT8 DmiAspmCtrl
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
Definition: CpuDmiPreMemConfig.h:110
CPU_DMI_PREMEM_CONFIG::DmiDeEmphasis
UINT8 DmiDeEmphasis
DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
Definition: CpuDmiPreMemConfig.h:108
DMI_ASPM
DMI_ASPM
The values before AutoConfig match the setting of PCI Express Base Specification 1....
Definition: CpuDmiPreMemConfig.h:49
CPU_DMI_PREMEM_CONFIG::DmiCdrRelock
UINT8 DmiCdrRelock
Used for programming DMI CDR Relock.
Definition: CpuDmiPreMemConfig.h:153
CPU_DMI_PREMEM_CONFIG::DmiAspmL1ExitLatency
UINT8 DmiAspmL1ExitLatency
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
Definition: CpuDmiPreMemConfig.h:111
CPU_DMI_EQ_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: CpuDmiPreMemConfig.h:62
CPU_DMI_EQ_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: CpuDmiPreMemConfig.h:63
CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh2Enable
UINT8 DmiGen3EqPh2Enable
(Test) DMI Equalization Phase 2 Enable Control
Definition: CpuDmiPreMemConfig.h:92
CPU_DMI_PREMEM_CONFIG::DmiNewFom
UINT8 DmiNewFom
Used for programming DMI New FOM.
Definition: CpuDmiPreMemConfig.h:152
CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh3Method
UINT8 DmiGen3EqPh3Method
(Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI
Definition: CpuDmiPreMemConfig.h:101
CPU_DMI_EQ_PARAM
Represent lane specific Dmi Gen3 equalization parameters.
Definition: CpuDmiPreMemConfig.h:61
CPU_DMI_PREMEM_CONFIG::DmiMaxLinkSpeed
UINT8 DmiMaxLinkSpeed
Definition: CpuDmiPreMemConfig.h:85
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPcieConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4
Classes | Macros | Enumerations
CpuPcieConfig.h File Reference

Pcie root port policy. More...

#include <Library/GpioLib.h>
#include <Library/CpuPcieInfoFruLib.h>
#include <PcieConfig.h>
#include <ConfigBlock.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for CpuPcieConfig.h:

Go to the source code of this file.

Classes

struct | PCIE_PEI_PREMEM_CONFIG
PCI Express and DMI controller configuration
. More...
struct | CPU_PCIE_RP_PREMEM_CONFIG
CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version. More...
struct | CPU_PCIE_EQ_LANE_PARAM
Represent lane specific PCIe Gen3 equalization parameters. More...
struct | CPU_PCIE_ROOT_PORT_CONFIG
The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port. More...
struct | CPU_PCIE_CONFIG
The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version. More...

Macros

#define CPU_PCIE_CONFIG_REVISION 10
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...

Enumerations

enum | CPU_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature.
enum | CPU_PCIE_L1SUBSTATES_CONTROL
Refer to SA EDS for the SA implementation values corresponding to below PCI-E spec defined ranges.
enum | CPU_PCIE_EQ_METHOD

Detailed Description

Pcie root port policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPcieConfig.h.

Macro Definition Documentation

◆ CPU_PCIE_CONFIG_REVISION

#define CPU_PCIE_CONFIG_REVISION 10

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Add Gen3TxOverride and Gen4TxOverride Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable Revision 4: - Add FOMS Control Policy Setup Variable Revision 5: - Add Gen3HwEqOverride and Gen4HwEqOverride Revision 6: - Align revision with CPU_PCIE_CONFIG_REVISION value Revision 7:

  • Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection Revision 8 :
    • Move PcieGen3LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
    • Move PcieGen4LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
    • Move PcieGen5LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
    • Move OverrideEqualizationDefaults policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG Revision 10: - Add Port0 Link Disable Setup Variable to CPU_PCIE_ROOT_PORT_CONFIG2

Definition at line 70 of file CpuPcieConfig.h.

Enumeration Type Documentation

◆ CPU_PCIE_EQ_METHOD

enum CPU_PCIE_EQ_METHOD
Enumerator
CpuPcieEqDefault
Deprecated:
since revision 3. Behaves as PchPcieEqHardware.
CpuPcieEqHardware

Hardware equalization.

CpuPcieEqStaticCoeff

Fixed equalization (requires Coefficient settings per lane)

Definition at line 278 of file CpuPcieConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPcieConfig.h Source File

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  • CpuPcieRp
  • Gen4
CpuPcieConfig.h
Go to the documentation of this file.
1 /** @file
2 Pcie root port policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _CPU_PCIE_CONFIG_H_
37 #define _CPU_PCIE_CONFIG_H_
38
39 #include <Library/GpioLib.h>
40 #include <Library/CpuPcieInfoFruLib.h>
41 #include <PcieConfig.h>
42 #include <ConfigBlock.h>
43 #include <Register/SaRegsHostBridge.h>
44
45 #pragma pack(push, 1)
46
47 #define PCIE_PEI_PREMEM_CONFIG_REVISION 1
48 #define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 5
49
50 /**
51 Making any setup structure change after code frozen
52 will need to maintain backward compatibility, bump up
53 structure revision and update below history table\n
54 <b>Revision 1</b>: - Initial version.
55 <b>Revision 2</b>: - Add Gen3TxOverride and Gen4TxOverride
56 <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
57 <b>Revision 4</b>: - Add FOMS Control Policy Setup Variable
58 <b>Revision 5</b>: - Add Gen3HwEqOverride and Gen4HwEqOverride
59 <b>Revision 6</b>: - Align revision with CPU_PCIE_CONFIG_REVISION value
60 <b>Revision 7</b>:
61 - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
62 <b>Revision 8 </b>:
63 - Move PcieGen3LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
64 - Move PcieGen4LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
65 - Move PcieGen5LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
66 - Move OverrideEqualizationDefaults policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
67 <b>Revision 10</b>: - Add Port0 Link Disable Setup Variable to CPU_PCIE_ROOT_PORT_CONFIG2
68 **/
69
70 #define CPU_PCIE_CONFIG_REVISION 10
71
72 #define L0_SET BIT0
73 #define L1_SET BIT1
74
75
76
77
78 /**
79 PCI Express and DMI controller configuration\n
80 @note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
81 <b>Revision 1</b>:
82 - Initial version.
83 **/
84 typedef struct {
85 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
86 /**
87 Offset 28:0 :
88 <b>(Test)</b> DMI Link Speed Control
89 - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
90 - Gen1 (0x1) : Limit Link to Gen1 Speed
91 - Gen2 (0x2) : Limit Link to Gen2 Speed
92 - Gen3 (0x3) : Limit Link to Gen3 Speed
93 **/
94 UINT32 DmiMaxLinkSpeed : 2;
95 /**
96 Offset 28:2 :
97 <b>(Test)</b> DMI Equalization Phase 2 Enable Control
98 - Disabled (0x0) : Disable phase 2
99 - Enabled (0x1) : Enable phase 2
100 - <b>Auto</b> (0x2) : Use the current default method (Default)
101 **/
102 UINT32 DmiGen3EqPh2Enable : 2;
103 /**
104 Offset 28:4 :
105 <b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
106 - <b>Auto</b> (0x0) : Use the current default method (Default)
107 - HwEq (0x1) : Use Adaptive Hardware Equalization
108 - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
109 - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
110 - Disabled (0x4) : Bypass Equalization Phase 3
111 **/
112 UINT32 DmiGen3EqPh3Method : 3;
113 /**
114 Offset 28:7 :
115 <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
116 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
117 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
118 **/
119 UINT32 DmiGen3ProgramStaticEq : 1;
120 UINT32 RsvdBits0 : 24; ///< Offset 28:8 :Reserved for future use
121
122 /**
123 Offset 32:0 :
124 Select when PCIe ASPM programming will happen in relation to the Oprom
125 - <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom. (Default)
126 - After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.
127 **/
128 UINT32 InitPcieAspmAfterOprom : 1;
129 UINT32 RsvdBits1 : 31; ///< Offset 32:1 :Reserved for future use
130
131 UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///< Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
132 UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///< Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
133 UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
134 /**
135 Offset 48/60 :
136 DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
137 has to be specified based upon platform design and must follow the guideline. Default is 12.
138 **/
139
140 UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
141
142 UINT8 DmiDeEmphasis; ///< Offset 64 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
143 UINT8 Rsvd0[3]; ///< Offset 65
144 } PCIE_PEI_PREMEM_CONFIG;
145
146
147 /**
148 CPU PCIe Root Port Pre-Memory Configuration
149 Contains Root Port settings and capabilities
150 <b>Revision 1</b>: - Initial version.
151 <b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
152 <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
153 <b>Revision 4</b>: - Adding New FOM Setup Variable
154 <b>Revision 5</b>: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.
155 **/
156 typedef struct {
157 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
158 /**
159 Root Port enabling mask.
160 Bit0 presents RP1, Bit1 presents RP2, and so on.
161 0: Disable; <b>1: Enable</b>.
162 **/
163 UINT32 RpEnabledMask;
164 /**
165 Assertion on Link Down GPIOs
166 - <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
167 - Enabled (0x1) : Enable assertion on Link Down GPIOs
168 **/
169 UINT8 LinkDownGpios;
170 /**
171 Enable ClockReq Messaging
172 - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
173 - Enabled (0x1) : Enable ClockReq Messaging
174 **/
175 UINT8 ClkReqMsgEnable;
176 /**
177 Dekel Recipe Workaround
178 <b>2</b>
179 1=Minimal, 9=Maximum,
180 **/
181 UINT8 DekelSquelchWa; // Deprecated variable
182 UINT8 Rsvd0[1];
183 /**
184 Determines each PCIE Port speed capability.
185 <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)
186 **/
187 UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
188
189 /**
190 Enable ClockReq Messaging Policy is for all Rootports
191 - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
192 - Enabled (0x1) : Enable ClockReq Messaging
193 **/
194 UINT8 ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS];
195 /**
196 To Enable/Disable New FOM
197 <b>0: Disable</b>; 1: Enable
198 **/
199 UINT8 NewFom[CPU_PCIE_MAX_ROOT_PORTS];
200 /**
201 To Enable/Disable CDR Relock
202 <b>0: Disable</b>; 1: Enable
203 **/
204 UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
205 } CPU_PCIE_RP_PREMEM_CONFIG;
206
207 typedef enum {
208 CpuPcieOverrideDisabled = 0,
209 CpuPcieL1L2Override = 0x01,
210 CpuPcieL1SubstatesOverride = 0x02,
211 CpuPcieL1L2AndL1SubstatesOverride = 0x03,
212 CpuPcieLtrOverride = 0x04
213 } CPU_PCIE_OVERRIDE_CONFIG;
214
215 enum CPU_PCIE_SPEED {
216 CpuPcieAuto,
217 CpuPcieGen1,
218 CpuPcieGen2,
219 CpuPcieGen3,
220 CpuPcieGen4,
221 CpuPcieGen5
222 };
223
224 ///
225 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
226 ///
227 typedef enum {
228 CpuPcieAspmDisabled,
229 CpuPcieAspmL0s,
230 CpuPcieAspmL1,
231 CpuPcieAspmL0sL1,
232 CpuPcieAspmAutoConfig,
233 CpuPcieAspmMax
234 } CPU_PCIE_ASPM_CONTROL;
235
236 /**
237 Refer to SA EDS for the SA implementation values corresponding
238 to below PCI-E spec defined ranges
239 **/
240 typedef enum {
241 CpuPcieL1SubstatesDisabled,
242 CpuPcieL1SubstatesL1_1,
243 CpuPcieL1SubstatesL1_1_2,
244 CpuPcieL1SubstatesMax
245 } CPU_PCIE_L1SUBSTATES_CONTROL;
246
247 enum CPU_PCIE_MAX_PAYLOAD {
248 CpuPcieMaxPayload128 = 0,
249 CpuPcieMaxPayload256,
250 CpuPcieMaxPayload512,
251 CpuPcieMaxPayloadMax
252 };
253
254 enum CPU_PCIE_COMPLETION_TIMEOUT {
255 CpuPcieCompletionTO_Default,
256 CpuPcieCompletionTO_50_100us,
257 CpuPcieCompletionTO_1_10ms,
258 CpuPcieCompletionTO_16_55ms,
259 CpuPcieCompletionTO_65_210ms,
260 CpuPcieCompletionTO_260_900ms,
261 CpuPcieCompletionTO_1_3P5s,
262 CpuPcieCompletionTO_4_13s,
263 CpuPcieCompletionTO_17_64s,
264 CpuPcieCompletionTO_Disabled
265 };
266
267
268 enum CPU_PCIE_GEN3_PRESET_COEFF_SELECTION {
269 CpuPcieGen3PresetSelection,
270 CpuPcieGen3CoefficientSelection
271 };
272
273 enum CPU_PCIE_GEN4_PRESET_COEFF_SELECTION {
274 CpuPcieGen4PresetSelection,
275 CpuPcieGen4CoefficientSelection
276 };
277
278 typedef enum {
279 CpuPcieEqDefault = 0, ///< @deprecated since revision 3. Behaves as PchPcieEqHardware.
280 CpuPcieEqHardware = 1, ///< Hardware equalization
281 CpuPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane)
282 } CPU_PCIE_EQ_METHOD;
283
284
285 /**
286 Represent lane specific PCIe Gen3 equalization parameters.
287 **/
288 typedef struct {
289 UINT8 Cm; ///< Coefficient C-1
290 UINT8 Cp; ///< Coefficient C+1
291 UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
292 UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
293 UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
294 UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
295 UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
296 UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
297 } CPU_PCIE_EQ_LANE_PARAM;
298
299 /**
300 The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
301 **/
302 typedef struct {
303
304 UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
305 UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0: Disable; <b>1: Enable</b>
306 UINT32 RsvdBits0 : 30; ///< Reserved bits
307 /**
308 PCIe Gen4 Equalization Method
309 - HwEq (0x1) : Hardware Equalization (Default)
310 - StaticEq (0x2) : Static Equalization
311 **/
312 UINT8 Gen4EqPh3Method;
313 UINT8 FomsCp; ///< FOM Score Board Control Policy
314 UINT8 RsvdBytes0[2]; ///< Reserved bytes
315
316 //
317 // Gen3 Equalization settings
318 //
319 UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
320 UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
321 //
322 // Gen4 Equalization settings
323 //
324 UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
325 UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
326 //
327 // Gen5 Equalization settings
328 //
329 UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>5</b>.
330 UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
331 UINT32 RsvdBits1 : 8; ///< Reserved Bits
332
333 PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///< <b>(Test)</b> Includes policies which are common to both SA and PCH RootPort
334
335 } CPU_PCIE_ROOT_PORT_CONFIG;
336
337 typedef struct {
338 UINT8 PcieGen3PresetCoeffSelection; ///<Gen3 Preset or Coefficient Selection
339 UINT8 PcieGen4PresetCoeffSelection; ///<Gen4 Preset or Coefficient Selection
340 UINT8 PcieGen5PresetCoeffSelection; ///<Gen5 Preset or Coefficient Selection
341 UINT8 Func0LinkDisable; ///< Disable Func0 Port
342 } CPU_PCIE_ROOT_PORT_CONFIG2;
343
344 /**
345 The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers
346 <b>Revision 1< / b>:
347 -Initial version.
348 <b>Revision 2</b>:
349 - SlotSelection policy added
350 <b>Revision 3</b>
351 - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
352 <b>Revision 4</b>:
353 - Deprecating SetSecuredRegisterLock
354 <b>Revision 5</b>:
355 - Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
356 - Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
357 - Deprecate VcEnabled policy
358 <b>Revision 7</b>:
359 - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
360 <b>Revision 8</b>:
361 - Added Serl policy
362 <b>Revision 9</b>:
363 - Align revision with CPU_PCIE_CONFIG_REVISION value
364 <b>Revision 10</b>:
365 - Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp
366 **/
367 typedef struct {
368 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
369 ///
370 /// These members describe the configuration of each SA PCIe root port.
371 ///
372 CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
373 ///
374 /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
375 /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
376 ///
377 CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; //@ Deprecated Policy
378 ///
379 /// List of coefficients used during equalization (applicable to both software and hardware EQ)
380 ///
381 PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; //@ Deprecated Policy
382
383 PCIE_COMMON_CONFIG PcieCommonConfig; /// < <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
384
385 UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and lock if enable
386 // Deprecated Policy
387 /**
388 <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
389 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
390 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
391 **/
392 UINT32 PegGen3ProgramStaticEq : 1;
393
394 // Deprecated Policy
395 /**
396 <b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
397 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
398 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
399 **/
400 UINT32 PegGen4ProgramStaticEq : 1;
401 /**
402 <b>(Test)</b> Cpu Pcie Secure Register Lock
403 - Disabled (0x0)
404 - <b>Enabled</b> (0x1)
405 **/
406 UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
407 ///
408 /// This member allows to select between the PCI Express M2 or CEMx4 slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
409 ///
410 UINT32 SlotSelection : 1;
411
412 UINT32 Serl : 1;
413
414 UINT32 RsvdBits0 : 26;
415
416 /**
417 PCIe device override table
418 The PCIe device table is being used to override PCIe device ASPM settings.
419 This is a pointer points to a 32bit address. And it's only used in PostMem phase.
420 Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
421 Last entry VendorId must be 0.
422 The prototype of this policy is:
423 PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
424 **/
425 UINT32 PcieDeviceOverrideTablePtr;
426 CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
427 PCIE_COMMON_CONFIG2 PcieCommonConfig2;
428 } CPU_PCIE_CONFIG;
429
430 #pragma pack (pop)
431
432 #endif // _CPU_PCIE_CONFIG_H_
PCIE_PEI_PREMEM_CONFIG::RsvdBits1
UINT32 RsvdBits1
Offset 32:1 :Reserved for future use.
Definition: CpuPcieConfig.h:129
ConfigBlock.h
Header file for Config Block Lib implementation.
CPU_PCIE_ROOT_PORT_CONFIG::Gen3Uptp
UINT32 Gen3Uptp
(Test) Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:319
PCIE_PEI_PREMEM_CONFIG::DmiMaxLinkSpeed
UINT32 DmiMaxLinkSpeed
Offset 28:0 : (Test) DMI Link Speed Control.
Definition: CpuPcieConfig.h:94
CPU_PCIE_EQ_LANE_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: CpuPcieConfig.h:289
CPU_PCIE_EQ_LANE_PARAM
Represent lane specific PCIe Gen3 equalization parameters.
Definition: CpuPcieConfig.h:288
CPU_PCIE_CONFIG::FiaProgramming
UINT32 FiaProgramming
< (Test) Includes policies which are common to both SA and PCH PCIe
Definition: CpuPcieConfig.h:385
CPU_PCIE_CONFIG::PcieDeviceOverrideTablePtr
UINT32 PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.
Definition: CpuPcieConfig.h:425
CPU_PCIE_ROOT_PORT_CONFIG::Gen4Uptp
UINT32 Gen4Uptp
(Test) Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:324
CPU_PCIE_EQ_LANE_PARAM::PegGen4EndPointPreset
UINT8 PegGen4EndPointPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
Definition: CpuPcieConfig.h:295
PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters.
Definition: PcieConfig.h:76
CPU_PCIE_EQ_LANE_PARAM::PegGen3RootPortPreset
UINT8 PegGen3RootPortPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
Definition: CpuPcieConfig.h:291
CPU_PCIE_ROOT_PORT_CONFIG::ExtSync
UINT32 ExtSync
Indicate whether the extended synch is enabled. 0: Disable; 1: Enable.
Definition: CpuPcieConfig.h:304
CPU_PCIE_CONFIG::PegGen4ProgramStaticEq
UINT32 PegGen4ProgramStaticEq
(Test) Program PEG Gen4 EQ Phase1 Static Presets
Definition: CpuPcieConfig.h:400
CPU_PCIE_CONFIG
The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Rev...
Definition: CpuPcieConfig.h:367
PCIE_PEI_PREMEM_CONFIG::InitPcieAspmAfterOprom
UINT32 InitPcieAspmAfterOprom
Offset 32:0 : Select when PCIe ASPM programming will happen in relation to the Oprom.
Definition: CpuPcieConfig.h:128
PCIE_PEI_PREMEM_CONFIG::DmiGen3ProgramStaticEq
UINT32 DmiGen3ProgramStaticEq
Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets.
Definition: CpuPcieConfig.h:119
CPU_PCIE_RP_PREMEM_CONFIG::RpEnabledMask
UINT32 RpEnabledMask
Root Port enabling mask.
Definition: CpuPcieConfig.h:163
CPU_PCIE_EQ_LANE_PARAM::PegGen3EndPointHint
UINT8 PegGen3EndPointHint
(Test) Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
Definition: CpuPcieConfig.h:293
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_PCIE_ROOT_PORT_CONFIG::FomsCp
UINT8 FomsCp
FOM Score Board Control Policy.
Definition: CpuPcieConfig.h:313
CPU_PCIE_RP_PREMEM_CONFIG::ClkReqMsgEnable
UINT8 ClkReqMsgEnable
Enable ClockReq Messaging.
Definition: CpuPcieConfig.h:175
CPU_PCIE_L1SUBSTATES_CONTROL
CPU_PCIE_L1SUBSTATES_CONTROL
Refer to SA EDS for the SA implementation values corresponding to below PCI-E spec defined ranges.
Definition: CpuPcieConfig.h:240
CPU_PCIE_RP_PREMEM_CONFIG
CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: ...
Definition: CpuPcieConfig.h:156
CPU_PCIE_RP_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPcieConfig.h:157
CPU_PCIE_ROOT_PORT_CONFIG::Gen4Dptp
UINT32 Gen4Dptp
(Test) Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:325
CPU_PCIE_EQ_LANE_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: CpuPcieConfig.h:290
CPU_PCIE_ROOT_PORT_CONFIG::Gen5Dptp
UINT32 Gen5Dptp
(Test) Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:330
CpuPcieEqDefault
@ CpuPcieEqDefault
Definition: CpuPcieConfig.h:279
PCIE_PEI_PREMEM_CONFIG
PCI Express and DMI controller configuration .
Definition: CpuPcieConfig.h:84
PCIE_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: CpuPcieConfig.h:85
CPU_PCIE_ROOT_PORT_CONFIG::MultiVcEnabled
UINT32 MultiVcEnabled
Multiple Virtual Channel. 0: Disable; 1: Enable
Definition: CpuPcieConfig.h:305
CPU_PCIE_ROOT_PORT_CONFIG::Gen3Dptp
UINT32 Gen3Dptp
(Test) Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:320
PCIE_PEI_PREMEM_CONFIG::DmiDeEmphasis
UINT8 DmiDeEmphasis
Offset 64 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3....
Definition: CpuPcieConfig.h:142
CPU_PCIE_CONFIG::SetSecuredRegisterLock
UINT32 SetSecuredRegisterLock
(Test) Cpu Pcie Secure Register Lock
Definition: CpuPcieConfig.h:406
PCIE_PEI_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 28:8 :Reserved for future use.
Definition: CpuPcieConfig.h:120
CPU_PCIE_ROOT_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: CpuPcieConfig.h:306
CPU_PCIE_ROOT_PORT_CONFIG::PcieRpCommonConfig
PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig
(Test) Includes policies which are common to both SA and PCH RootPort
Definition: CpuPcieConfig.h:333
PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh3Method
UINT32 DmiGen3EqPh3Method
Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI.
Definition: CpuPcieConfig.h:112
CPU_PCIE_EQ_LANE_PARAM::PegGen4EndPointHint
UINT8 PegGen4EndPointHint
(Test) Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
Definition: CpuPcieConfig.h:296
CPU_PCIE_CONFIG::PegGen3ProgramStaticEq
UINT32 PegGen3ProgramStaticEq
< Skip Fia Configuration and lock if enable
Definition: CpuPcieConfig.h:392
CPU_PCIE_ROOT_PORT_CONFIG::Gen4EqPh3Method
UINT8 Gen4EqPh3Method
PCIe Gen4 Equalization Method.
Definition: CpuPcieConfig.h:312
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:287
PcieConfig.h
PCIe Config Block.
CPU_PCIE_RP_PREMEM_CONFIG::LinkDownGpios
UINT8 LinkDownGpios
Assertion on Link Down GPIOs.
Definition: CpuPcieConfig.h:169
CPU_PCIE_ROOT_PORT_CONFIG
The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
Definition: CpuPcieConfig.h:302
CPU_PCIE_EQ_LANE_PARAM::PegGen4RootPortPreset
UINT8 PegGen4RootPortPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
Definition: CpuPcieConfig.h:294
CPU_PCIE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPcieConfig.h:368
CPU_PCIE_EQ_LANE_PARAM::PegGen3EndPointPreset
UINT8 PegGen3EndPointPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
Definition: CpuPcieConfig.h:292
CPU_PCIE_ROOT_PORT_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved Bits.
Definition: CpuPcieConfig.h:331
CPU_PCIE_ASPM_CONTROL
CPU_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1....
Definition: CpuPcieConfig.h:227
CPU_PCIE_CONFIG::SlotSelection
UINT32 SlotSelection
This member allows to select between the PCI Express M2 or CEMx4 slot 1: PCIe M2; 0: CEMx4 slot.
Definition: CpuPcieConfig.h:410
PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh2Enable
UINT32 DmiGen3EqPh2Enable
Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control.
Definition: CpuPcieConfig.h:102
CPU_PCIE_ROOT_PORT_CONFIG::Gen5Uptp
UINT32 Gen5Uptp
(Test) Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:329
CpuPcieEqHardware
@ CpuPcieEqHardware
Hardware equalization.
Definition: CpuPcieConfig.h:280
CPU_PCIE_RP_PREMEM_CONFIG::DekelSquelchWa
UINT8 DekelSquelchWa
Dekel Recipe Workaround 2 1=Minimal, 9=Maximum,.
Definition: CpuPcieConfig.h:181
CpuPcieEqStaticCoeff
@ CpuPcieEqStaticCoeff
Fixed equalization (requires Coefficient settings per lane)
Definition: CpuPcieConfig.h:281
CPU_PCIE_EQ_METHOD
CPU_PCIE_EQ_METHOD
Definition: CpuPcieConfig.h:278
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtBasicConfig.h File Reference

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CpuPowerMgmtBasicConfig.h File Reference

CPU Power Management Basic Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_BASIC_CONFIG
CPU Power Management Basic Configuration Structure. More...

Detailed Description

CPU Power Management Basic Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtBasicConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtBasicConfig.h Source File

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CpuPowerMgmtBasicConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management Basic Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_
36 #define _CPU_POWER_MGMT_BASIC_CONFIG_H_
37
38 #define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 6
39
40 extern EFI_GUID gCpuPowerMgmtBasicConfigGuid;
41
42 #ifndef TURBO_RATIO_LIMIT_ARRAY_SIZE
43 #define TURBO_RATIO_LIMIT_ARRAY_SIZE 8
44 #endif
45
46 #pragma pack (push,1)
47
48 /**
49 CPU Power Management Basic Configuration Structure.
50
51 <b>Revision 1</b>:
52 - Initial version.
53 <b>Revision 2</b>:
54 - Changed EnableItbm default to be disable
55 - Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS driver
56 <b>Revision 3</b>:
57 - Add ApplyConfigTdp for TDP initialization settings based on non-cTDP or cTDP
58 <b>Revision 4</b>:
59 - Add Hwp Lock support
60 <b>Revision 5</b>:
61 - Add TurboRatioLimitRatio, TurboRatioLimitNumCore, AtomTurboRatioLimitRatio and AtomTurboRatioLimitNumCore
62 <b>Revision 6</b>:
63 - Add DualTauBoost
64 <b>Revision 7</b>:
65 - Changed EnableItbm default to be enable
66 **/
67 typedef struct {
68 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
69 /**
70 Sets the boot frequency starting from reset vector.
71 - 0: Maximum battery performance.
72 - 1: Maximum non-turbo performance.
73 - <b>2: Turbo performance.</b>
74 @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
75 **/
76 UINT32 BootFrequency : 2; //@deprecated
77 UINT32 SkipSetBootPState : 1; ///< Choose whether to skip SetBootPState function for all APs; <b>0: Do not skip</b>; 1: Skip.
78 /**
79 Enable or Disable Intel Speed Shift Technology.
80 Enabling allows for processor control of P-state transitions.
81 0: Disable; <b>1: Enable;</b> Bit 1 is ignored.
82 @note Currently this feature is recommended to be enabled only on win10
83 **/
84 UINT32 Hwp : 2;
85 /**
86 Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
87 HDC enables the processor to autonomously force components to enter into an idle state to lower effective frequency.
88 This allows for increased package level C6 residency.
89 @note Currently this feature is recommended to be enabled only on win10
90 **/
91 UINT32 HdcControl : 2;
92 UINT32 PowerLimit2 : 1; ///< Enable or Disable short duration Power Limit (PL2). 0: Disable; <b>1: Enable</b>
93 UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; <b>0: Disable</b>; 1: Enable (Lock).
94 UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. <b>Default: 0</b>.
95 UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615h lock; <b>0: Disable</b>; 1: Enable (Lock).
96 UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601h lock; <b>0: Disable</b>; 1: Enable (Lock).
97 /**
98 Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.
99 For Y SKU, the recommended default for this policy is <b>1: Enabled</b>, which indicates throttling below P1 is allowed.
100 For all other SKUs the recommended default are <b>0: Disabled</b>.
101 **/
102 UINT32 TccOffsetClamp : 1;
103 UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: Disabled; <b>1: Enabled (Lock)</b>.
104 UINT32 TurboMode : 1; ///< Enable or Disable Turbo Mode. Disable; <b>1: Enable</b>
105 UINT32 HwpInterruptControl : 1; ///< Set HW P-State Interrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; <b>0: Disable</b>; 1: Enable.
106 UINT32 ApplyConfigTdp : 1; ///< Switch TDP applied setting based on non-cTDP or TDP; 0: non-cTDP; <b>1: cTDP</b>.
107 UINT32 HwpLock : 1; ///< HWP Lock in MISC PWR MGMT MSR 1AAh; <b>0: Disable</b>; 1: Enable (Lock).
108 /**
109 Dual Tau Base Performance Boost support. This will improve platform performance for desktop sku.
110 When enabled, it exposes 2 MMIO PL1 and MMIO Tau registers, and also provides the default value.
111 @note: This is only applicable for Desktop 35W/65W/125W sku.
112 @note: When this is enabled, it will override the settings in policys PowerLimit1, PowerLimit1Time, PowerLimit2Power.
113 <b>0: Disable</b>; 1: Enable
114 **/
115 UINT32 DualTauBoost : 1;
116 UINT32 RsvdBits : 6; ///< Reserved for future use.
117
118 /**
119 1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking parts: LFM to Fused 1-Core Ratio Limit + OC Bins.
120 Default value is from hardware register MSR 0x1AD.
121 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
122 - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
123 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
124 **/
125 UINT8 OneCoreRatioLimit;
126 /**
127 2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.
128 Default value is from hardware register MSR 0x1AD.
129 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
130 - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
131 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
132 **/
133 UINT8 TwoCoreRatioLimit;
134 /**
135 3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.
136 Default value is from hardware register MSR 0x1AD.
137 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
138 - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
139 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
140 **/
141 UINT8 ThreeCoreRatioLimit;
142 /**
143 4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.
144 Default value is from hardware register MSR 0x1AD.
145 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
146 - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
147 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
148 **/
149 UINT8 FourCoreRatioLimit;
150 /**
151 5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.
152 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
153 - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
154 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
155 **/
156 UINT8 FiveCoreRatioLimit;
157 /**
158 6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.
159 Default value is from hardware register MSR 0x1AD.
160 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
161 - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
162 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
163 **/
164 UINT8 SixCoreRatioLimit;
165 /**
166 7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.
167 Default value is from hardware register MSR 0x1AD.
168 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
169 - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
170 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
171 **/
172 UINT8 SevenCoreRatioLimit;
173 /**
174 8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.
175 Default value is from hardware register MSR 0x1AD.
176 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
177 - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
178 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
179 **/
180 UINT8 EightCoreRatioLimit;
181 /**
182 TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated.
183 TCC will be activated at (TCC Activation Temperature - TCC Activation Offset), in degrees Celcius.
184 For Y SKU, the recommended default for this policy is <b>10</b>
185 For all other SKUs the recommended default are <b>0</b>, causing TCC to activate at TCC Activation temperature.
186 @note The policy is recommended for validation purpose only.
187 **/
188 UINT8 TccActivationOffset;
189 /**
190 Intel Turbo Boost Max Technology 3.0
191 Enabling it on processors with OS support will allow OS to exploit the diversity in max turbo frequency of the cores.
192 <b>0: Disable</b>; 1: Enable;
193 **/
194 UINT8 EnableItbm : 1;
195 /**
196 @deprecated: Platform doesn't have Intel Turbo Boost Max Technology 3.0 Driver
197 Enabling it will load the driver upon ACPI device with HID = INT3510.
198 <b> 0: Disable;</b> 1: Enable;
199 **/
200 UINT8 EnableItbmDriver : 1;
201 /**
202 Per Core P State OS control mode
203 Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1. When set, the highest core request is used for all other core requests.
204 0: Disable;<b> 1: Enable;</b>
205 **/
206 UINT8 EnablePerCorePState : 1;
207 /**
208 HwP Autonomous Per Core P State
209 Disabling will set Bit 30 = 1, command 0x11. When set, autonomous will request the same value
210 for all cores all the time.
211 0: Disable;<b> 1: Enable;</b>
212 **/
213 UINT8 EnableHwpAutoPerCorePstate : 1;
214 /**
215 HwP Autonomous EPP grouping.
216 Disabling will set Bit 29 = 1, command 0x11. When set, autonomous will not necesarrily request the same value
217 for all cores with same EPP.
218 Enabling will clean Bit 29 = 0, command 0x11. Autonomous will request same values for all cores with same EPP.
219 0: Disable;<b> 1: Enable;</b>
220 **/
221 UINT8 EnableHwpAutoEppGrouping : 1;
222 /**
223 EPB override over PECI
224 Enable by sending pcode command 0x2b , subcommand 0x3 to 1.
225 This will allow OOB EPB PECI override control.
226 <b>0: Disable;</b> 1: Enable;
227 **/
228 UINT8 EnableEpbPeciOverride : 1;
229 /**
230 Support for Fast MSR for IA32_HWP_REQUEST.
231 On systems with HwP enabled, if this feature is available as indicated by MSR 0x65F[0] = 1,
232 set MSR 0x657[0] = 1.
233 0: Disable; <b> 1: Enable;</b>
234 **/
235 UINT8 EnableFastMsrHwpReq : 1;
236 UINT8 ReservedBits1 : 1; ///< Reserved for future use.
237 UINT8 MinRingRatioLimit; ///< Minimum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
238 UINT8 MaxRingRatioLimit; ///< Maximum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
239 /**
240 Package Long duration turbo mode power limit (PL1).
241 Default is the TDP power limit of processor. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
242 **/
243 UINT16 PowerLimit1;
244 /**
245 Package Short duration turbo mode power limit (PL2). Allows for short excursions above TDP power limit.
246 Default = 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
247 **/
248 UINT16 PowerLimit2Power;
249 /**
250 Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit.
251 <b>Default: 0</b>. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
252 **/
253 UINT16 PowerLimit3;
254 /**
255 Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power Limit, it will never be exceeded.
256 Power is premptively lowered before limit is reached. <b>Default: 0</b>. Range 0-65535.
257 Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
258 **/
259 UINT16 PowerLimit4;
260 /**
261 Package Long duration turbo mode power limit (PL1) time window in seconds.
262 Used in calculating the average power over time.
263 Mobile: <b> 28s</b>
264 Desktop: <b> 8s</b>
265 Range: 0 - 128s
266 **/
267 UINT32 PowerLimit1Time;
268 UINT32 PowerLimit3Time; ///< Package PL3 time window. Range from 3ms to 64ms.
269 /**
270 Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).
271 For Y SKU, the recommended default for this policy is <b>5000: 5 seconds</b>, For all other SKUs the recommended default are <b>0: Disabled</b>
272 **/
273 UINT32 TccOffsetTimeWindowForRatl;
274 /**
275 Turbo Ratio Limit Ratio array, TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0]
276 to determine the active core ranges for each frequency point.
277 Default value is from hardware register MSR 0x1AD.
278 Note:
279 - These policies are for platforms support MSR pair 0x1AD and 0x1AE.
280 **/
281 UINT8 TurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE];
282 /**
283 Turbo Ratio Limit Num Core array, TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0]
284 to determine the active core ranges for each frequency point.
285 Default value is from hardware register MSR 0x1AE.
286 Note:
287 - These policies are for platforms support MSR pair 0x1AD and 0x1AE.
288 **/
289 UINT8 TurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE];
290 /**
291 ATOM Turbo Ratio Limit Ratio array, AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0]
292 to determine the active core ranges for each frequency point.
293 Default value is from hardware register MSR 0x650.
294 Note:
295 - These policies are for platforms support ATOM MSR pair 0x650 and 0x651.
296 **/
297 UINT8 AtomTurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE];
298 /**
299 ATOM Turbo Ratio Limit Num Core array, AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0]
300 to determine the active core ranges for each frequency point.
301 Default value is from hardware register MSR 0x651.
302 Note:
303 - These policies are for platforms support ATOM MSR pair 0x650 and 0x651.
304 **/
305 UINT8 AtomTurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE];
306 } CPU_POWER_MGMT_BASIC_CONFIG;
307
308 #pragma pack (pop)
309
310 #endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_
CPU_POWER_MGMT_BASIC_CONFIG::OneCoreRatioLimit
UINT8 OneCoreRatioLimit
1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit.
Definition: CpuPowerMgmtBasicConfig.h:125
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3DutyCycle
UINT32 PowerLimit3DutyCycle
Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0.
Definition: CpuPowerMgmtBasicConfig.h:94
CPU_POWER_MGMT_BASIC_CONFIG::EnableFastMsrHwpReq
UINT8 EnableFastMsrHwpReq
Support for Fast MSR for IA32_HWP_REQUEST.
Definition: CpuPowerMgmtBasicConfig.h:235
CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetLock
UINT32 TccOffsetLock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: ...
Definition: CpuPowerMgmtBasicConfig.h:103
CPU_POWER_MGMT_BASIC_CONFIG
CPU Power Management Basic Configuration Structure.
Definition: CpuPowerMgmtBasicConfig.h:67
CPU_POWER_MGMT_BASIC_CONFIG::MinRingRatioLimit
UINT8 MinRingRatioLimit
Minimum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
Definition: CpuPowerMgmtBasicConfig.h:237
CPU_POWER_MGMT_BASIC_CONFIG::EightCoreRatioLimit
UINT8 EightCoreRatioLimit
8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:180
CPU_POWER_MGMT_BASIC_CONFIG::FiveCoreRatioLimit
UINT8 FiveCoreRatioLimit
5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:156
CPU_POWER_MGMT_BASIC_CONFIG::SkipSetBootPState
UINT32 SkipSetBootPState
Choose whether to skip SetBootPState function for all APs; 0: Do not skip; 1: Skip.
Definition: CpuPowerMgmtBasicConfig.h:77
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3Time
UINT32 PowerLimit3Time
Package PL3 time window. Range from 3ms to 64ms.
Definition: CpuPowerMgmtBasicConfig.h:268
CPU_POWER_MGMT_BASIC_CONFIG::Hwp
UINT32 Hwp
Enable or Disable Intel Speed Shift Technology.
Definition: CpuPowerMgmtBasicConfig.h:84
CPU_POWER_MGMT_BASIC_CONFIG::MaxRingRatioLimit
UINT8 MaxRingRatioLimit
Maximum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
Definition: CpuPowerMgmtBasicConfig.h:238
CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetClamp
UINT32 TccOffsetClamp
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.
Definition: CpuPowerMgmtBasicConfig.h:102
CPU_POWER_MGMT_BASIC_CONFIG::ReservedBits1
UINT8 ReservedBits1
Reserved for future use.
Definition: CpuPowerMgmtBasicConfig.h:236
CPU_POWER_MGMT_BASIC_CONFIG::HwpLock
UINT32 HwpLock
HWP Lock in MISC PWR MGMT MSR 1AAh; 0: Disable; 1: Enable (Lock).
Definition: CpuPowerMgmtBasicConfig.h:107
CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetTimeWindowForRatl
UINT32 TccOffsetTimeWindowForRatl
Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).
Definition: CpuPowerMgmtBasicConfig.h:273
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit2Power
UINT16 PowerLimit2Power
Package Short duration turbo mode power limit (PL2).
Definition: CpuPowerMgmtBasicConfig.h:248
CPU_POWER_MGMT_BASIC_CONFIG::SixCoreRatioLimit
UINT8 SixCoreRatioLimit
6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:164
CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoEppGrouping
UINT8 EnableHwpAutoEppGrouping
HwP Autonomous EPP grouping.
Definition: CpuPowerMgmtBasicConfig.h:221
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit4
UINT16 PowerLimit4
Package PL4 power limit.
Definition: CpuPowerMgmtBasicConfig.h:259
CPU_POWER_MGMT_BASIC_CONFIG::EnableEpbPeciOverride
UINT8 EnableEpbPeciOverride
EPB override over PECI Enable by sending pcode command 0x2b , subcommand 0x3 to 1.
Definition: CpuPowerMgmtBasicConfig.h:228
CPU_POWER_MGMT_BASIC_CONFIG::EnablePerCorePState
UINT8 EnablePerCorePState
Per Core P State OS control mode Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1.
Definition: CpuPowerMgmtBasicConfig.h:206
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1Time
UINT32 PowerLimit1Time
Package Long duration turbo mode power limit (PL1) time window in seconds.
Definition: CpuPowerMgmtBasicConfig.h:267
CPU_POWER_MGMT_BASIC_CONFIG::TurboPowerLimitLock
UINT32 TurboPowerLimitLock
MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; 0: Disable; 1: Enable...
Definition: CpuPowerMgmtBasicConfig.h:93
CPU_POWER_MGMT_BASIC_CONFIG::HdcControl
UINT32 HdcControl
Hardware Duty Cycle Control configuration.
Definition: CpuPowerMgmtBasicConfig.h:91
CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoPerCorePstate
UINT8 EnableHwpAutoPerCorePstate
HwP Autonomous Per Core P State Disabling will set Bit 30 = 1, command 0x11.
Definition: CpuPowerMgmtBasicConfig.h:213
CPU_POWER_MGMT_BASIC_CONFIG::DualTauBoost
UINT32 DualTauBoost
Dual Tau Base Performance Boost support.
Definition: CpuPowerMgmtBasicConfig.h:115
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit4Lock
UINT32 PowerLimit4Lock
Package PL4 MSR 601h lock; 0: Disable; 1: Enable (Lock).
Definition: CpuPowerMgmtBasicConfig.h:96
CPU_POWER_MGMT_BASIC_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtBasicConfig.h:116
CPU_POWER_MGMT_BASIC_CONFIG::HwpInterruptControl
UINT32 HwpInterruptControl
Set HW P-State Interrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtBasicConfig.h:105
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit2
UINT32 PowerLimit2
Enable or Disable short duration Power Limit (PL2). 0: Disable; 1: Enable
Definition: CpuPowerMgmtBasicConfig.h:92
CPU_POWER_MGMT_BASIC_CONFIG::FourCoreRatioLimit
UINT8 FourCoreRatioLimit
4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:149
CPU_POWER_MGMT_BASIC_CONFIG::ApplyConfigTdp
UINT32 ApplyConfigTdp
Switch TDP applied setting based on non-cTDP or TDP; 0: non-cTDP; 1: cTDP.
Definition: CpuPowerMgmtBasicConfig.h:106
CPU_POWER_MGMT_BASIC_CONFIG::BootFrequency
UINT32 BootFrequency
Sets the boot frequency starting from reset vector.
Definition: CpuPowerMgmtBasicConfig.h:76
CPU_POWER_MGMT_BASIC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtBasicConfig.h:68
CPU_POWER_MGMT_BASIC_CONFIG::EnableItbm
UINT8 EnableItbm
Intel Turbo Boost Max Technology 3.0 Enabling it on processors with OS support will allow OS to explo...
Definition: CpuPowerMgmtBasicConfig.h:194
CPU_POWER_MGMT_BASIC_CONFIG::TccActivationOffset
UINT8 TccActivationOffset
TCC Activation Offset.
Definition: CpuPowerMgmtBasicConfig.h:188
CPU_POWER_MGMT_BASIC_CONFIG::TurboMode
UINT32 TurboMode
Enable or Disable Turbo Mode. Disable; 1: Enable
Definition: CpuPowerMgmtBasicConfig.h:104
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3Lock
UINT32 PowerLimit3Lock
Package PL3 MSR 615h lock; 0: Disable; 1: Enable (Lock).
Definition: CpuPowerMgmtBasicConfig.h:95
CPU_POWER_MGMT_BASIC_CONFIG::EnableItbmDriver
UINT8 EnableItbmDriver
Definition: CpuPowerMgmtBasicConfig.h:200
CPU_POWER_MGMT_BASIC_CONFIG::ThreeCoreRatioLimit
UINT8 ThreeCoreRatioLimit
3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:141
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1
UINT16 PowerLimit1
Package Long duration turbo mode power limit (PL1).
Definition: CpuPowerMgmtBasicConfig.h:243
CPU_POWER_MGMT_BASIC_CONFIG::TwoCoreRatioLimit
UINT8 TwoCoreRatioLimit
2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:133
CPU_POWER_MGMT_BASIC_CONFIG::SevenCoreRatioLimit
UINT8 SevenCoreRatioLimit
7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:172
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3
UINT16 PowerLimit3
Package PL3 power limit.
Definition: CpuPowerMgmtBasicConfig.h:253
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtCustomConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes | Macros | Typedefs
CpuPowerMgmtCustomConfig.h File Reference

CPU Power Managment Custom Config Block. More...

Go to the source code of this file.

Classes

struct | PPM_CUSTOM_RATIO_TABLE
This structure is used to describe the custom processor ratio table desired by the platform. More...
struct | _PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings. More...
struct | CPU_POWER_MGMT_CUSTOM_CONFIG
CPU Power Management Custom Configuration Structure. More...

Macros

#define | MAX_CUSTOM_RATIO_TABLE_ENTRIES 40
Defines the maximum number of custom ratio states supported.
#define | MAX_CUSTOM_CTDP_ENTRIES 3
Defines the maximum number of custom ConfigTdp entries supported. More...

Typedefs

typedef struct _PPM_CUSTOM_CTDP_TABLE PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings.

Detailed Description

CPU Power Managment Custom Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtCustomConfig.h.

Macro Definition Documentation

◆ MAX_CUSTOM_CTDP_ENTRIES

#define MAX_CUSTOM_CTDP_ENTRIES 3

Defines the maximum number of custom ConfigTdp entries supported.

Warning
: Changing this define would cause DWORD alignment issues in policy structures.

Definition at line 54 of file CpuPowerMgmtCustomConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtCustomConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuPowerMgmtCustomConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Managment Custom Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
36 #define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
37
38 #define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1
39
40 extern EFI_GUID gCpuPowerMgmtCustomConfigGuid;
41
42 #pragma pack (push,1)
43
44 ///
45 /// Defines the maximum number of custom ratio states supported.
46 ///
47 #define MAX_CUSTOM_RATIO_TABLE_ENTRIES 40
48 #define MAX_16_CUSTOM_RATIO_TABLE_ENTRIES 16
49
50 ///
51 /// Defines the maximum number of custom ConfigTdp entries supported.
52 /// @warning: Changing this define would cause DWORD alignment issues in policy structures.
53 ///
54 #define MAX_CUSTOM_CTDP_ENTRIES 3
55
56 ///
57 /// This structure is used to describe the custom processor ratio table desired by the platform.
58 ///
59 typedef struct {
60 UINT8 MaxRatio; ///< The maximum ratio of the custom ratio table.
61 UINT8 NumberOfEntries; ///< The number of custom ratio state entries, ranges from 2 to 40 for a valid custom ratio table.
62 UINT8 Rsvd0[2]; ///< Reserved for DWORD alignment.
63 UINT32 Cpuid; ///< The CPU ID for which this custom ratio table applies.
64 UINT8 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The processor ratios in the custom ratio table.
65 ///
66 /// If there are more than 16 total entries in the StateRatio table, then use these 16 entries to fill max 16 table.
67 /// @note If NumberOfEntries is 16 or less, or the first entry of this table is 0, then this table is ignored,
68 /// and up to the top 16 values from the StateRatio table is used instead.
69 ///
70 UINT8 StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES];
71 #if ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4)
72 UINT8 Rsvd1[4 - ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4)]; ///< If needed, add padding for dword alignment.
73 #endif
74 } PPM_CUSTOM_RATIO_TABLE;
75
76 ///
77 /// PPM Custom ConfigTdp Settings
78 ///
79 typedef struct _PPM_CUSTOM_CTDP_TABLE {
80 UINT32 CustomPowerLimit1Time : 8; ///< Short term Power Limit time window value for custom cTDP level.
81 UINT32 CustomTurboActivationRatio : 8; ///< Turbo Activation Ratio for custom cTDP level.
82 UINT32 RsvdBits : 16; ///< Bits reserved for DWORD alignment.
83 UINT16 CustomPowerLimit1; ///< Short term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
84 UINT16 CustomPowerLimit2; ///< Long term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
85 } PPM_CUSTOM_CTDP_TABLE;
86
87 /**
88 CPU Power Management Custom Configuration Structure.
89
90 <b>Revision 1</b>:
91 - Initial version.
92 **/
93 typedef struct {
94 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
95 PPM_CUSTOM_RATIO_TABLE CustomRatioTable; ///< Custom Processor Ratio Table Instance
96 PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; ///< Custom ConfigTdp Settings Instance
97 UINT32 ConfigTdpLock : 1; ///< Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable.
98 UINT32 ConfigTdpBios : 1; ///< Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
99 UINT32 RsvdBits : 30; ///< Reserved for future use
100 } CPU_POWER_MGMT_CUSTOM_CONFIG;
101
102 #pragma pack (pop)
103
104 #endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
PPM_CUSTOM_RATIO_TABLE
This structure is used to describe the custom processor ratio table desired by the platform.
Definition: CpuPowerMgmtCustomConfig.h:59
_PPM_CUSTOM_CTDP_TABLE::CustomPowerLimit1Time
UINT32 CustomPowerLimit1Time
Short term Power Limit time window value for custom cTDP level.
Definition: CpuPowerMgmtCustomConfig.h:80
_PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings.
Definition: CpuPowerMgmtCustomConfig.h:79
PPM_CUSTOM_RATIO_TABLE::NumberOfEntries
UINT8 NumberOfEntries
The number of custom ratio state entries, ranges from 2 to 40 for a valid custom ratio table.
Definition: CpuPowerMgmtCustomConfig.h:61
PPM_CUSTOM_CTDP_TABLE
struct _PPM_CUSTOM_CTDP_TABLE PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings.
CPU_POWER_MGMT_CUSTOM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtCustomConfig.h:94
MAX_CUSTOM_RATIO_TABLE_ENTRIES
#define MAX_CUSTOM_RATIO_TABLE_ENTRIES
Defines the maximum number of custom ratio states supported.
Definition: CpuPowerMgmtCustomConfig.h:47
_PPM_CUSTOM_CTDP_TABLE::CustomPowerLimit1
UINT16 CustomPowerLimit1
Short term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG....
Definition: CpuPowerMgmtCustomConfig.h:83
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PPM_CUSTOM_RATIO_TABLE::Cpuid
UINT32 Cpuid
The CPU ID for which this custom ratio table applies.
Definition: CpuPowerMgmtCustomConfig.h:63
CPU_POWER_MGMT_CUSTOM_CONFIG::ConfigTdpBios
UINT32 ConfigTdpBios
Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtCustomConfig.h:98
CPU_POWER_MGMT_CUSTOM_CONFIG::CustomRatioTable
PPM_CUSTOM_RATIO_TABLE CustomRatioTable
Custom Processor Ratio Table Instance.
Definition: CpuPowerMgmtCustomConfig.h:95
CPU_POWER_MGMT_CUSTOM_CONFIG::ConfigTdpLock
UINT32 ConfigTdpLock
Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtCustomConfig.h:97
MAX_CUSTOM_CTDP_ENTRIES
#define MAX_CUSTOM_CTDP_ENTRIES
Defines the maximum number of custom ConfigTdp entries supported.
Definition: CpuPowerMgmtCustomConfig.h:54
_PPM_CUSTOM_CTDP_TABLE::CustomPowerLimit2
UINT16 CustomPowerLimit2
Long term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG....
Definition: CpuPowerMgmtCustomConfig.h:84
_PPM_CUSTOM_CTDP_TABLE::RsvdBits
UINT32 RsvdBits
Bits reserved for DWORD alignment.
Definition: CpuPowerMgmtCustomConfig.h:82
CPU_POWER_MGMT_CUSTOM_CONFIG
CPU Power Management Custom Configuration Structure.
Definition: CpuPowerMgmtCustomConfig.h:93
CPU_POWER_MGMT_CUSTOM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtCustomConfig.h:99
_PPM_CUSTOM_CTDP_TABLE::CustomTurboActivationRatio
UINT32 CustomTurboActivationRatio
Turbo Activation Ratio for custom cTDP level.
Definition: CpuPowerMgmtCustomConfig.h:81
PPM_CUSTOM_RATIO_TABLE::MaxRatio
UINT8 MaxRatio
The maximum ratio of the custom ratio table.
Definition: CpuPowerMgmtCustomConfig.h:60
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtPsysConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuPowerMgmtPsysConfig.h File Reference

CPU Power Management Psys(Platform) Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_PSYS_CONFIG
CPU Power Management Psys(Platform) Configuration Structure. More...

Detailed Description

CPU Power Management Psys(Platform) Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtPsysConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtPsysConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuPowerMgmtPsysConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management Psys(Platform) Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_PSYS_CONFIG_H_
36 #define _CPU_POWER_MGMT_PSYS_CONFIG_H_
37
38 #define CPU_POWER_MGMT_PSYS_CONFIG_REVISION 1
39
40 extern EFI_GUID gCpuPowerMgmtPsysConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Power Management Psys(Platform) Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 **/
50 typedef struct {
51 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
52 UINT32 PsysPowerLimit1 : 1; ///< MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power
53 UINT32 PsysPowerLimit1Time : 8; ///< MSR 0x65C[23:17]: PL1 timewindow in seconds.
54 UINT32 PsysPowerLimit2 : 1; ///< MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power
55 UINT32 RsvdBits : 22; ///< Reserved for future use.
56 UINT16 PsysPowerLimit1Power; ///< MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
57 UINT16 PsysPowerLimit2Power; ///< MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
58 UINT16 PsysPmax; ///< PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. 0-1024 Watts. Value of 800 = 100W.
59 UINT8 Rsvd[2]; ///< Reserved for future use and config block alignment
60 } CPU_POWER_MGMT_PSYS_CONFIG;
61
62 #pragma pack (pop)
63
64 #endif // _CPU_POWER_MGMT_PSYS_CONFIG_H_
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit2Power
UINT16 PsysPowerLimit2Power
MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
Definition: CpuPowerMgmtPsysConfig.h:57
CPU_POWER_MGMT_PSYS_CONFIG::PsysPmax
UINT16 PsysPmax
PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments....
Definition: CpuPowerMgmtPsysConfig.h:58
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit1
UINT32 PsysPowerLimit1
MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power.
Definition: CpuPowerMgmtPsysConfig.h:52
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit1Time
UINT32 PsysPowerLimit1Time
MSR 0x65C[23:17]: PL1 timewindow in seconds.
Definition: CpuPowerMgmtPsysConfig.h:53
CPU_POWER_MGMT_PSYS_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtPsysConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit1Power
UINT16 PsysPowerLimit1Power
MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
Definition: CpuPowerMgmtPsysConfig.h:56
CPU_POWER_MGMT_PSYS_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtPsysConfig.h:51
CPU_POWER_MGMT_PSYS_CONFIG
CPU Power Management Psys(Platform) Configuration Structure.
Definition: CpuPowerMgmtPsysConfig.h:50
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit2
UINT32 PsysPowerLimit2
MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power.
Definition: CpuPowerMgmtPsysConfig.h:54
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtTestConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes | Enumerations
CpuPowerMgmtTestConfig.h File Reference

CPU Power Management Test Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_TEST_CONFIG
CPU Power Management Test Configuration Structure. More...

Enumerations

enum | MAX_PKG_C_STATE
PPM Package C State Limit.
enum | C_STATE_TIME_UNIT
PPM Package C State Time Limit.
enum | CUSTOM_POWER_UNIT
Custom Power Units. More...
enum | PPM_IRM_SETTING
PPM Interrupt Redirection Mode Selection.

Detailed Description

CPU Power Management Test Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtTestConfig.h.

Enumeration Type Documentation

◆ CUSTOM_POWER_UNIT

enum CUSTOM_POWER_UNIT

Custom Power Units.

User can choose to enter in watts or 125 milliwatt increments.

Enumerator
PowerUnitWatts | in Watts.
PowerUnit125MilliWatts | in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.

Definition at line 78 of file CpuPowerMgmtTestConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtTestConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
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CpuPowerMgmtTestConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management Test Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_
36 #define _CPU_POWER_MGMT_TEST_CONFIG_H_
37
38 #define CPU_POWER_MGMT_TEST_CONFIG_REVISION 7
39
40 extern EFI_GUID gCpuPowerMgmtTestConfigGuid;
41
42 #pragma pack (push,1)
43
44 ///
45 /// PPM Package C State Limit
46 ///
47 typedef enum {
48 PkgC0C1 = 0,
49 PkgC2,
50 PkgC3,
51 PkgC6,
52 PkgC7,
53 PkgC7s,
54 PkgC8,
55 PkgC9,
56 PkgC10,
57 PkgCMax,
58 PkgCpuDefault = 254,
59 PkgAuto = 255
60 } MAX_PKG_C_STATE;
61
62 ///
63 /// PPM Package C State Time Limit
64 ///
65 typedef enum {
66 TimeUnit1ns = 0,
67 TimeUnit32ns,
68 TimeUnit1024ns,
69 TimeUnit32768ns,
70 TimeUnit1048576ns,
71 TimeUnit33554432ns,
72 TimeUnitMax
73 } C_STATE_TIME_UNIT;
74
75 ///
76 /// Custom Power Units. User can choose to enter in watts or 125 milliwatt increments.
77 ///
78 typedef enum {
79 PowerUnitWatts = 0, ///< in Watts.
80 PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.
81 PowerUnitMax
82 } CUSTOM_POWER_UNIT;
83
84 ///
85 /// PPM Interrupt Redirection Mode Selection
86 ///
87 typedef enum {
88 PpmIrmFixedPriority = 0,
89 PpmIrmRoundRobin,
90 PpmIrmHashVector,
91 PpmIrmReserved1,
92 PpmIrmReserved2,
93 PpmIrmReserved3,
94 PpmIrmReserved4,
95 PpmIrmNoChange
96 } PPM_IRM_SETTING;
97
98 /**
99 CPU Power Management Test Configuration Structure.
100
101 <b>Revision 1</b>:
102 - Initial version.
103 <b>Revision 2</b>:
104 - Add CstateLatencyControl0TimeUnit for WHL only
105 - Add CstateLatencyControl0Irtl for WHL only
106 <b>Revision 3</b>:
107 - Change C State LatencyContol to Auto as default.
108 <b>Revision 4</b>:
109 - Add CstateLatencyControl0TimeUnit and CstateLatencyControl0Irtl.
110 <b>Revision 5</b>:
111 - Change EnergyEfficientTurbo to Disable as default.
112 <b>Revision 6</b>:
113 - Change ProcHotResponse and ProcHotLock to Enable as default.
114 <b>Revision 7</b>:
115 - Deprecate ConfigTdpLevel. Move to premem.
116 **/
117 typedef struct {
118 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
119 UINT32 Eist : 1; ///< Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
120 UINT32 EnergyEfficientPState : 1; ///< Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; <b>1: Enable</b>
121 UINT32 EnergyEfficientTurbo : 1; ///< Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. <b>0: Disable</b>; 1: Enable.
122 UINT32 TStates : 1; ///< Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
123 UINT32 BiProcHot : 1; ///< Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>.
124 UINT32 DisableProcHotOut : 1; ///< Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
125 UINT32 ProcHotResponse : 1; ///< Enable or Disable PROCHOT# Response; 0: Disable; <b>1: Enable</b>.
126 UINT32 DisableVrThermalAlert : 1; ///< Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
127 UINT32 EnableAllThermalFunctions : 1; ///< Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
128 UINT32 ThermalMonitor : 1; ///< Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>.
129 UINT32 Cx : 1; ///< Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
130 UINT32 PmgCstCfgCtrlLock : 1; ///< If enabled, sets MSR 0xE2[15]; 0: Disable; <b>1: Enable</b>.
131 UINT32 C1e : 1; ///< Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
132 UINT32 C1AutoDemotion : 1; ///< Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; <b>1: C1 Auto demotion</b>
133 UINT32 C1UnDemotion : 1; ///< Enable or Disable C1UnDemotion. 0: Disabled; <b>1: C1 Auto undemotion</b>
134 UINT32 C3AutoDemotion : 1; ///< @deprecated no longer used
135 UINT32 C3UnDemotion : 1; ///< @deprecated no longer used
136 UINT32 PkgCStateDemotion : 1; ///< Enable or Disable Package Cstate Demotion. Disable; <b>1: Enable</b> [WhiskeyLake] <b>Disable</b>; 1: Enable
137 UINT32 PkgCStateUnDemotion : 1; ///< Enable or Disable Package Cstate UnDemotion. Disable; <b>1: Enable</b> [WhiskeyLake] <b>Disable</b>; 1: Enable
138 UINT32 CStatePreWake : 1; ///< Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b>
139 UINT32 TimedMwait : 1; ///< Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
140 UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
141 UINT32 ProcHotLock : 1; ///< If enabled, sets MSR 0x1FC[23]; 0: Disable; <b>1: Enable</b>.
142 UINT32 RaceToHalt : 1; ///< Enable or Disable Race To Halt feature; 0: Disable; <b>1: Enable </b>. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)
143 UINT32 ConfigTdpLevel : 8; ///< @deprecated Move to premem phase.
144 UINT16 CstateLatencyControl1Irtl; ///< Offset 32-33 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].<b>0 is Auto</b>.
145 UINT16 CstateLatencyControl2Irtl; ///< Offset 34-35 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].<b>0 is Auto</b>.
146 UINT16 CstateLatencyControl3Irtl; ///< Offset 36-37 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].<b>0 is Auto</b>.
147 UINT16 CstateLatencyControl4Irtl; ///< Offset 38-39 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].<b>0 is Auto</b>.
148 UINT16 CstateLatencyControl5Irtl; ///< Offset 40-41 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].<b>0 is Auto</b>.
149 UINT16 CstateLatencyControl0Irtl; ///< Offset 42-43 Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].<b>0 is Auto</b>.
150 MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
151 /**
152 @todo: The following enums have to be replaced with policies.
153 **/
154 C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit; ///< Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; <b>2: 1024ns</b>.
155 C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; <b>2: 1024ns</b>.
156 C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; <b>2: 1024ns</b>.
157 C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; <b>2: 1024ns</b>.
158 C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; <b>2: 1024ns</b>.
159 C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; <b>2: 1024ns</b>.
160 /**
161 Offset 51 Default power unit in watts or in 125 milliwatt increments.
162 - 0: PowerUnitWatts.
163 - <b>1: PowerUnit125MilliWatts</b>.
164 **/
165 CUSTOM_POWER_UNIT CustomPowerUnit;
166 /**
167 Offset 52 Interrupt Redirection Mode Select.
168 - 0: Fixed priority. //Default under CNL.
169 - 1: Round robin.
170 - 2: Hash vector.
171 - 4: PAIR with fixed priority. //Default under KBL, not available under CNL.
172 - 5: PAIR with round robin. //Not available under CNL.
173 - 6: PAIR with hash vector. //Not available under CNL.
174 - 7: No change.
175 **/
176 PPM_IRM_SETTING PpmIrmSetting;
177 // Move the padding to previous offset to align the structure at 32-bit address.
178 UINT8 Rsvd[4]; ///< Offset 53-56 Reserved for future use and config block alignment
179 } CPU_POWER_MGMT_TEST_CONFIG;
180
181 #pragma pack (pop)
182
183 #endif // _CPU_POWER_MGMT_TEST_CONFIG_H_
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl2Irtl
UINT16 CstateLatencyControl2Irtl
Offset 34-35 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:145
CPU_POWER_MGMT_TEST_CONFIG::CStatePreWake
UINT32 CStatePreWake
Enable or Disable CState-Pre wake. Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:138
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl4Irtl
UINT16 CstateLatencyControl4Irtl
Offset 38-39 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:147
CPU_POWER_MGMT_TEST_CONFIG::C3AutoDemotion
UINT32 C3AutoDemotion
Definition: CpuPowerMgmtTestConfig.h:134
CPU_POWER_MGMT_TEST_CONFIG::TimedMwait
UINT32 TimedMwait
Enable or Disable TimedMwait Support. Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:139
CPU_POWER_MGMT_TEST_CONFIG::C3UnDemotion
UINT32 C3UnDemotion
Definition: CpuPowerMgmtTestConfig.h:135
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl4TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit
Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:158
PowerUnit125MilliWatts
@ PowerUnit125MilliWatts
in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.
Definition: CpuPowerMgmtTestConfig.h:80
CPU_POWER_MGMT_TEST_CONFIG::PkgCStateDemotion
UINT32 PkgCStateDemotion
Enable or Disable Package Cstate Demotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:136
CPU_POWER_MGMT_TEST_CONFIG::RaceToHalt
UINT32 RaceToHalt
Enable or Disable Race To Halt feature; 0: Disable; 1: Enable . RTH will dynamically increase CPU fre...
Definition: CpuPowerMgmtTestConfig.h:142
CPU_POWER_MGMT_TEST_CONFIG::EnergyEfficientTurbo
UINT32 EnergyEfficientTurbo
Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:121
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl1Irtl
UINT16 CstateLatencyControl1Irtl
Offset 32-33 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:144
PPM_IRM_SETTING
PPM_IRM_SETTING
PPM Interrupt Redirection Mode Selection.
Definition: CpuPowerMgmtTestConfig.h:87
PowerUnitWatts
@ PowerUnitWatts
in Watts.
Definition: CpuPowerMgmtTestConfig.h:79
CPU_POWER_MGMT_TEST_CONFIG::ConfigTdpLevel
UINT32 ConfigTdpLevel
Definition: CpuPowerMgmtTestConfig.h:143
C_STATE_TIME_UNIT
C_STATE_TIME_UNIT
PPM Package C State Time Limit.
Definition: CpuPowerMgmtTestConfig.h:65
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl5TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit
Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:159
CPU_POWER_MGMT_TEST_CONFIG::DisableProcHotOut
UINT32 DisableProcHotOut
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:124
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl2TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit
Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:156
CPU_POWER_MGMT_TEST_CONFIG::BiProcHot
UINT32 BiProcHot
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:123
CPU_POWER_MGMT_TEST_CONFIG::Cx
UINT32 Cx
Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:129
CPU_POWER_MGMT_TEST_CONFIG::CustomPowerUnit
CUSTOM_POWER_UNIT CustomPowerUnit
Offset 51 Default power unit in watts or in 125 milliwatt increments.
Definition: CpuPowerMgmtTestConfig.h:165
CPU_POWER_MGMT_TEST_CONFIG::PkgCStateUnDemotion
UINT32 PkgCStateUnDemotion
Enable or Disable Package Cstate UnDemotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:137
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
MAX_PKG_C_STATE
MAX_PKG_C_STATE
PPM Package C State Limit.
Definition: CpuPowerMgmtTestConfig.h:47
CPU_POWER_MGMT_TEST_CONFIG
CPU Power Management Test Configuration Structure.
Definition: CpuPowerMgmtTestConfig.h:117
CPU_POWER_MGMT_TEST_CONFIG::PpmIrmSetting
PPM_IRM_SETTING PpmIrmSetting
Offset 52 Interrupt Redirection Mode Select.
Definition: CpuPowerMgmtTestConfig.h:176
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit
Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:154
CPU_POWER_MGMT_TEST_CONFIG::PkgCStateLimit
MAX_PKG_C_STATE PkgCStateLimit
Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg ...
Definition: CpuPowerMgmtTestConfig.h:150
CPU_POWER_MGMT_TEST_CONFIG::Eist
UINT32 Eist
Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:119
CPU_POWER_MGMT_TEST_CONFIG::PmgCstCfgCtrlLock
UINT32 PmgCstCfgCtrlLock
If enabled, sets MSR 0xE2[15]; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:130
CPU_POWER_MGMT_TEST_CONFIG::EnableAllThermalFunctions
UINT32 EnableAllThermalFunctions
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:127
CPU_POWER_MGMT_TEST_CONFIG::C1UnDemotion
UINT32 C1UnDemotion
Enable or Disable C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion
Definition: CpuPowerMgmtTestConfig.h:133
CPU_POWER_MGMT_TEST_CONFIG::EnergyEfficientPState
UINT32 EnergyEfficientPState
Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:120
CPU_POWER_MGMT_TEST_CONFIG::ProcHotLock
UINT32 ProcHotLock
If enabled, sets MSR 0x1FC[23]; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:141
CPU_POWER_MGMT_TEST_CONFIG::C1AutoDemotion
UINT32 C1AutoDemotion
Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; 1: C1 Auto demotion
Definition: CpuPowerMgmtTestConfig.h:132
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl5Irtl
UINT16 CstateLatencyControl5Irtl
Offset 40-41 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:148
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl3TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit
Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:157
CUSTOM_POWER_UNIT
CUSTOM_POWER_UNIT
Custom Power Units.
Definition: CpuPowerMgmtTestConfig.h:78
CPU_POWER_MGMT_TEST_CONFIG::ProcHotResponse
UINT32 ProcHotResponse
Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:125
CPU_POWER_MGMT_TEST_CONFIG::C1e
UINT32 C1e
Enable or Disable Enhanced C-states. 0: Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:131
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0Irtl
UINT16 CstateLatencyControl0Irtl
Offset 42-43 Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:149
CPU_POWER_MGMT_TEST_CONFIG::DisableVrThermalAlert
UINT32 DisableVrThermalAlert
Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:126
CPU_POWER_MGMT_TEST_CONFIG::CstCfgCtrIoMwaitRedirection
UINT32 CstCfgCtrIoMwaitRedirection
Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:140
CPU_POWER_MGMT_TEST_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: CpuPowerMgmtTestConfig.h:118
CPU_POWER_MGMT_TEST_CONFIG::ThermalMonitor
UINT32 ThermalMonitor
Enable or Disable Thermal Monitor; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:128
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl1TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit
Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:155
CPU_POWER_MGMT_TEST_CONFIG::TStates
UINT32 TStates
Enable or Disable T states; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:122
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl3Irtl
UINT16 CstateLatencyControl3Irtl
Offset 36-37 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:146
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtVrConfig.h File Reference

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Classes | Macros
CpuPowerMgmtVrConfig.h File Reference

CPU Power Management VR Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_VR_CONFIG
CPU Power Management VR Configuration Structure. More...

Macros

#define MAX_NUM_VRS 5
Defines the maximum number of VR domains supported. More...

Detailed Description

CPU Power Management VR Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtVrConfig.h.

Macro Definition Documentation

◆ MAX_NUM_VRS

#define MAX_NUM_VRS 5

Defines the maximum number of VR domains supported.

Warning
: Changing this define would cause DWORD alignment issues in policy structures.

Definition at line 48 of file CpuPowerMgmtVrConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPowerMgmtVrConfig.h Source File

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CpuPowerMgmtVrConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management VR Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_VR_CONFIG_H_
36 #define _CPU_POWER_MGMT_VR_CONFIG_H_
37
38 #define CPU_POWER_MGMT_VR_CONFIG_REVISION 16
39
40 extern EFI_GUID gCpuPowerMgmtVrConfigGuid;
41
42 #pragma pack (push,1)
43
44 ///
45 /// Defines the maximum number of VR domains supported.
46 /// @warning: Changing this define would cause DWORD alignment issues in policy structures.
47 ///
48 #define MAX_NUM_VRS 5
49
50 /**
51 CPU Power Management VR Configuration Structure.
52
53 <b>Revision 1</b>:
54 - Initial version.
55 <b>Revision 2</b>:
56 - Updated Acoustic Noise Mitigation.
57 <b>Revision 3</b>:
58 - Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction
59 <b>Revision 4</b>:
60 - Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time
61 Added Irms support.
62 <b>Revision 5</b>:
63 - Add RfiMitigation.
64 <b>Revision 6</b>:
65 - Add Dynamic Periodicity Alteration (DPA) tuning feature
66 <b>Revision 7</b>:
67 - Add VccIn Aux Imon feature
68 <b>Revision 8</b>:
69 - Deprecate SendVrMbxCmd
70 <b>Revision 9</b>:
71 - Added an option to Enable/Disable FIVR Spread Spectrum
72 <b>Revision 10</b>:
73 - Add DlvrRfiEnable, DlvrSpreadSpectrumPercentage and DlvrRfiFrequency for RFI control.
74 <b>Revision 11</b>:
75 - Added an option to Enable/Disable PS1 to PS0/PS2 to PS1 dynamic cutoff
76 <b>Revision 12</b>:
77 - Added an option for Vr Power Delivery design
78 <b>Revision 13</b>:
79 - Add VccInDemotionEnable, VccInDemotionQuiescentPowerInMw and VccInDemotionCapacitanceInUf
80 <b>Revision 14</b>:
81 - Add EnableVsysCritical, VsysFullScale,VsysCriticalThreshold, VsysAssertionDeglitchMantissa
82 - VsysAssertionDeglitchExponent, VsysDeassertionDeglitchMantissa, VsysDeassertionDeglitchExponent
83 <b>Revision 15</b>:
84 - Add Voltage Regulator Fast Vmode ICC Limit
85 <b>Revision 16</b>:
86 - Modified IccMax range up to 512A
87 **/
88 typedef struct {
89 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
90 UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
91
92 UINT32 SendVrMbxCmd : 2; ///< Deprecated
93 UINT32 EnableMinVoltageOverride : 1; ///< Enable or disable Minimum Voltage override for minimum voltage runtime and minimum voltage C8. <b>0: Disabled</b> 1: Enabled.
94 UINT32 RfiMitigation : 1; ///< Enable or Disable RFI Mitigation. <b>0: Disable - DCM is the IO_N default</b>; 1: Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
95 UINT32 RsvdBits : 27; ///< Reserved for future use.
96 UINT8 PsysSlope; ///< PCODE MMIO Mailbox: Platform Psys slope correction. <b>0: Auto</b> Specified in 1/100 increment values. Range is 0-200. 125 = 1.25.
97 UINT8 PsysOffset; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0: Auto</b> Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. Deprecated
98 /**
99 PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range.
100 <b>1.5%</b>
101 Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%.
102 Each Range is translated to an encoded value for FIVR register.
103 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
104 **/
105 UINT8 FivrSpreadSpectrum;
106 UINT8 RsvdBytes0;
107 /**
108 PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
109 <b>0: Auto</b>
110 Range varies based on XTAL clock:
111 - 0-1918 (Up to 191.8HMz) for 24MHz clock.
112 - 0-1535 (Up to 153.5MHz) for 19MHz clock.
113 **/
114 UINT16 FivrRfiFrequency;
115 UINT8 RsvdBytes1[2];
116 /** @name VR Settings
117 The VR related settings are sorted in an array where each index maps to the VR domain as defined below:
118 - 0 = System Agent VR
119 - 1 = IA Core VR
120 - 2 = Ring Vr
121 - 3 = GT VR
122 - 4 = FIVR VR
123
124 The VR settings for a given domain must be populated in the appropriate index.
125 **/
126 ///@{
127 UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. <b>0: 0 Amps</b>
128 UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.</b>
129 UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
130 UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
131 UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
132 UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
133 INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
134 UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A. <b>Default: 0 - Auto, no override</b>
135 UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
136 UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>
137 UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
138 UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.
139 UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS configuration of VR; 0: Disable; <b>1: Enable.</b>
140 UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable; </b>1: Enable
141 UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< @deprecated. PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
142 UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.
143 UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
144 UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
145 ///@}
146 UINT16 MinVoltageRuntime; ///< PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 .Range 0 to 1999mV. <b> 0: 0mV </b>
147 UINT16 MinVoltageC8; ///< PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. <b> 0: 0mV </b>
148 UINT16 PsysOffset1; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0: Auto</b> Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348.
149 UINT8 RsvdBytes2[2];
150 UINT32 TdcTimeWindow1[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
151 UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Current root mean square. <b>0: Disable</b>; 1: Enable.
152 UINT8 FivrSpectrumEnable; ///< Enable or Disable FIVR Spread Spectrum 0: Disable; <b> 1: Enable.</b>
153 UINT8 DlvrSpreadSpectrumPercentage; ///< PCODE MMIO Mailbox: Encoded DLVR SSC value. 0x0 = Disabled. u3.2 value from 0% - 7.75%.
154 UINT8 DlvrRfiEnable; ///< PCODE MMIO Mailbox: Enable/Disable RFI frequency hopping. <b>0: Disable.</b> 1:Disable
155 UINT8 PreWake; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max pre-wake randomization time in micro ticks. Range is 0-255.
156 UINT8 RampUp; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp up randomization time in micro ticks. Range is 0-255.
157 UINT8 RampDown; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp down randomization time in micro ticks. Range is 0-255.
158 UINT8 Rsvd2[1];
159 UINT16 VccInAuxImonIccImax; ///< PCODE MMIO Mailbox: VccIn Aux Imon IccMax. <b>0 - Auto</b> Values are in 1/4 Amp increments. Range is 0-128A8.
160 UINT16 VccInAuxImonSlope; ///< PCODE MMIO Mailbox: VccInAuxImon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>
161 INT16 VccInAuxImonOffset; ///< PCODE MMIO Mailbox: VccinAuxImon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
162 UINT16 DlvrRfiFrequency; ///< PCODE MMIO Mailbox: DLVR clock frequency in MHz. Default is 0x55A MHz.
163 UINT8 PS1toPS0DynamicCutoffEnable[MAX_NUM_VRS];///< Enable/Disable PS1 to PS0 Dynamic Cutoff; <b>0: Disable</b>; 1: Enable.
164 UINT8 PS2toPS1DynamicCutoffEnable[MAX_NUM_VRS];///< Enable/Disable:PS2 to PS1 Dynamic Cutoff; <b>0: Disable</b>; 1: Enable.
165 UINT16 PS1toPS0MCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS1 to PS0 M Coef. This number is in M*100 units. <b>Default: 100</b> Range: 0-4096.
166 INT16 PS1toPS0CCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS1 to PS0 C Coef. This number is in C*100 units. <b>Default: 2000</b> Range: 0-4096.
167 UINT16 PS2toPS1MCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS2 to PS1 M Coef. This number is in M*100 units. <b>Default: 100</b> Range: 0-4096.
168 INT16 PS2toPS1CCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS2 to PS1 C Coef. This number is in C*100 units. <b>Default: 500</b> Range: 0-4096.
169 /**
170 This field is required to be non-zero on Desktop platforms.
171
172 Used to communicate the power delivery design capability of the board. This value is an
173 enum of the available power delivery segments that are defined in the Platform Design Guide.
174 This is required due to CPU socket compatibility across different board designs. Without
175 this field populated, the system may experience VR OCP/OVP shutdowns, hangs, thermal and
176 performance loss.
177 <b> 0 - Disable </b>
178 **/
179 UINT8 VrPowerDeliveryDesign;
180 UINT8 Rsvd4[1];
181 /**
182 Enable VCC Demotion.
183 0: Disable;
184 <b>1: Enable with default threshold</b>;
185 2: Enable with user configured threshold.
186 **/
187 UINT8 VccInDemotionEnable[MAX_NUM_VRS];
188 /**
189 User configured platform quiescent threshold in milli-watt
190 when VCC Demotion is enabled with user configured threshold.
191 Range: 0-255.
192 **/
193 UINT8 VccInDemotionQuiescentPowerInMw[MAX_NUM_VRS];
194 UINT8 Rsvd5[2]; ///< Make next field 4-byte aligned.
195 /**
196 User configured VR's quiescent power threshold in micro-farad
197 when VCC Demotion is enabled with user configured threshold.
198 Range: 0-2000.
199 **/
200 UINT32 VccInDemotionCapacitanceInUf[MAX_NUM_VRS];
201
202 UINT8 EnableVsysCritical; ///< PCODE MMIO Mailbox: Enable/Disable Vsys Critical; <b>0: Disable</b>; 1: Enable.
203 /**
204 Set VSYS Critical [0x4A]
205 Write to 0x4A to program Vsys Critical Threshold which is a linear fractional value of the Vsys input full scale voltage
206 where minimun is 0 and maximum is 255. Default 0
207 For example: Vsys_Crit (0x4A) = (Critical Threshold/Full Scale) * 0xFF
208 **/
209 UINT8 VsysFullScale;
210 UINT8 VsysCriticalThreshold;
211 /**
212 Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49]
213 Provide 2 fields in BIOS Menu for Assertion/De-Assertion Deglitch: Mantissa and Exponent.
214 The format for Assertion/De-Assertion Deglitch: 0.002ms * Mantissa * 2^(Exponent).
215 **/
216 UINT8 VsysAssertionDeglitchMantissa;
217 UINT8 VsysAssertionDeglitchExponent;
218 UINT8 VsysDeassertionDeglitchMantissa;
219 UINT8 VsysDeassertionDeglitchExponent;
220 UINT8 Rsvd6[1];
221 /**
222 PCODE VR Mailbox: Voltage Regulator Fast Vmode ICC Limit.
223 This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
224 A value of 0 corresponds to feature disabled (no reactive protection).
225 <b>Default: 0 - Disable, no override</b>
226 **/
227 UINT16 IccLimit[MAX_NUM_VRS];
228 UINT8 RsvdBytes3[2];
229 } CPU_POWER_MGMT_VR_CONFIG;
230
231 #pragma pack (pop)
232
233 #endif // _CPU_POWER_MGMT_VR_CONFIG_H_
CPU_POWER_MGMT_VR_CONFIG::DlvrRfiFrequency
UINT16 DlvrRfiFrequency
PCODE MMIO Mailbox: DLVR clock frequency in MHz. Default is 0x55A MHz.
Definition: CpuPowerMgmtVrConfig.h:162
CPU_POWER_MGMT_VR_CONFIG::RampUp
UINT8 RampUp
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMiti...
Definition: CpuPowerMgmtVrConfig.h:156
CPU_POWER_MGMT_VR_CONFIG::PsysOffset
UINT8 PsysOffset
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/4, Range 0-255....
Definition: CpuPowerMgmtVrConfig.h:97
CPU_POWER_MGMT_VR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtVrConfig.h:89
CPU_POWER_MGMT_VR_CONFIG::VsysFullScale
UINT8 VsysFullScale
Set VSYS Critical [0x4A] Write to 0x4A to program Vsys Critical Threshold which is a linear fractiona...
Definition: CpuPowerMgmtVrConfig.h:209
CPU_POWER_MGMT_VR_CONFIG
CPU Power Management VR Configuration Structure.
Definition: CpuPowerMgmtVrConfig.h:88
CPU_POWER_MGMT_VR_CONFIG::VccInAuxImonIccImax
UINT16 VccInAuxImonIccImax
PCODE MMIO Mailbox: VccIn Aux Imon IccMax. 0 - Auto Values are in 1/4 Amp increments....
Definition: CpuPowerMgmtVrConfig.h:159
CPU_POWER_MGMT_VR_CONFIG::PreWake
UINT8 PreWake
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMiti...
Definition: CpuPowerMgmtVrConfig.h:155
CPU_POWER_MGMT_VR_CONFIG::DlvrSpreadSpectrumPercentage
UINT8 DlvrSpreadSpectrumPercentage
PCODE MMIO Mailbox: Encoded DLVR SSC value. 0x0 = Disabled. u3.2 value from 0% - 7....
Definition: CpuPowerMgmtVrConfig.h:153
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_POWER_MGMT_VR_CONFIG::MinVoltageC8
UINT16 MinVoltageC8
PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1....
Definition: CpuPowerMgmtVrConfig.h:147
CPU_POWER_MGMT_VR_CONFIG::VccInAuxImonOffset
INT16 VccInAuxImonOffset
PCODE MMIO Mailbox: VccinAuxImon offset correction. Value is a 2's complement signed integer....
Definition: CpuPowerMgmtVrConfig.h:161
MAX_NUM_VRS
#define MAX_NUM_VRS
Defines the maximum number of VR domains supported.
Definition: CpuPowerMgmtVrConfig.h:48
CPU_POWER_MGMT_VR_CONFIG::RfiMitigation
UINT32 RfiMitigation
Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1: Enable - Enable IO_N DCM/C...
Definition: CpuPowerMgmtVrConfig.h:94
CPU_POWER_MGMT_VR_CONFIG::EnableVsysCritical
UINT8 EnableVsysCritical
PCODE MMIO Mailbox: Enable/Disable Vsys Critical; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtVrConfig.h:202
CPU_POWER_MGMT_VR_CONFIG::PsysSlope
UINT8 PsysSlope
PCODE MMIO Mailbox: Platform Psys slope correction. 0: Auto Specified in 1/100 increment values....
Definition: CpuPowerMgmtVrConfig.h:96
CPU_POWER_MGMT_VR_CONFIG::FivrRfiFrequency
UINT16 FivrRfiFrequency
PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
Definition: CpuPowerMgmtVrConfig.h:114
CPU_POWER_MGMT_VR_CONFIG::SendVrMbxCmd
UINT32 SendVrMbxCmd
Deprecated.
Definition: CpuPowerMgmtVrConfig.h:92
CPU_POWER_MGMT_VR_CONFIG::PsysOffset1
UINT16 PsysOffset1
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/1000, Range 0-63999....
Definition: CpuPowerMgmtVrConfig.h:148
CPU_POWER_MGMT_VR_CONFIG::EnableMinVoltageOverride
UINT32 EnableMinVoltageOverride
Enable or disable Minimum Voltage override for minimum voltage runtime and minimum voltage C8....
Definition: CpuPowerMgmtVrConfig.h:93
CPU_POWER_MGMT_VR_CONFIG::MinVoltageRuntime
UINT16 MinVoltageRuntime
PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 ....
Definition: CpuPowerMgmtVrConfig.h:146
CPU_POWER_MGMT_VR_CONFIG::DlvrRfiEnable
UINT8 DlvrRfiEnable
PCODE MMIO Mailbox: Enable/Disable RFI frequency hopping. 0: Disable. 1:Disable.
Definition: CpuPowerMgmtVrConfig.h:154
CPU_POWER_MGMT_VR_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtVrConfig.h:95
CPU_POWER_MGMT_VR_CONFIG::FivrSpectrumEnable
UINT8 FivrSpectrumEnable
Enable or Disable FIVR Spread Spectrum 0: Disable; 1: Enable.
Definition: CpuPowerMgmtVrConfig.h:152
CPU_POWER_MGMT_VR_CONFIG::RampDown
UINT8 RampDown
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMiti...
Definition: CpuPowerMgmtVrConfig.h:157
CPU_POWER_MGMT_VR_CONFIG::VccInAuxImonSlope
UINT16 VccInAuxImonSlope
PCODE MMIO Mailbox: VccInAuxImon slope correction. Specified in 1/100 increment values....
Definition: CpuPowerMgmtVrConfig.h:160
CPU_POWER_MGMT_VR_CONFIG::AcousticNoiseMitigation
UINT32 AcousticNoiseMitigation
Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled.
Definition: CpuPowerMgmtVrConfig.h:90
CPU_POWER_MGMT_VR_CONFIG::VrPowerDeliveryDesign
UINT8 VrPowerDeliveryDesign
This field is required to be non-zero on Desktop platforms.
Definition: CpuPowerMgmtVrConfig.h:179
CPU_POWER_MGMT_VR_CONFIG::FivrSpreadSpectrum
UINT8 FivrSpreadSpectrum
PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range.
Definition: CpuPowerMgmtVrConfig.h:105
CPU_POWER_MGMT_VR_CONFIG::VsysAssertionDeglitchMantissa
UINT8 VsysAssertionDeglitchMantissa
Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49] Provide 2 fields in BIOS Menu for Asse...
Definition: CpuPowerMgmtVrConfig.h:216
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuSecurityPreMemConfig.h File Reference

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CpuSecurityPreMemConfig.h File Reference

CPU Security PreMemory Config Block. More...

Go to the source code of this file.

Classes

struct CPU_SECURITY_PREMEM_CONFIG
CPU Security PreMemory Configuration Structure. More...

Detailed Description

CPU Security PreMemory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuSecurityPreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuSecurityPreMemConfig.h Source File

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CpuSecurityPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Security PreMemory Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_SECURITY_PREMEM_CONFIG_H_
36 #define _CPU_SECURITY_PREMEM_CONFIG_H_
37
38 #define CPU_SECURITY_PREMEM_CONFIG_REVISION 2
39
40 extern EFI_GUID gCpuSecurityPreMemConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Security PreMemory Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 <b>Revision 2</b>:
50 - Deprecated SGx
51 **/
52 typedef struct {
53 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
54 UINT32 PrmrrSize; ///< PRMRR Size.<b>Software Control: 0x0</b> 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000, 256 MB: 0x10000000, 512 MB: 0x20000000
55 UINT16 BiosSize; ///< Flash information for BIOS Guard: BIOS Size in KB.
56 UINT8 Reserved[2]; ///< Reserved for future use
57 /**
58 Enable or Disable BIOS Guard; 0: Disable; <b>1: Enable</b>.
59 - This is an optional feature and can be opted out.
60 - If this policy is set to Disabled, the policies in the BIOS_GUARD_CONFIG will be ignored.
61 - If PeiBiosGuardLibNull is used, this policy will have no effect.
62 **/
63 UINT32 BiosGuard : 1;
64 UINT32 BiosGuardToolsInterface : 1; ///< BIOS Guard Tools Interface; <b>0: Disable</b>, 1:Enable
65 /**
66 Enable or Disable Software Guard Extensions; <b>0: Disable</b>; 1: Enable.
67 - This is an optional feature and can be opted out.
68 - If this policy is set to Disabled, the policies in the CPU_SGX_CONFIG will be ignored.
69 - If BaseSoftwareGuardLibNull is used, this policy will have no effect.
70 **/
71 UINT32 EnableSgx : 1; ///< @deprecated due to Non-POR feature.
72 /**
73 Enable or Disable Trusted Execution Technology; <b>0: Disable</b>; 1: Enable.
74 - This is an optional feature and can be opted out.
75 - If this policy is set to Disabled, the policies in the CPU_TXT_PREMEM_CONFIG will be ignored.
76 - If PeiTxtLibNull is used, this policy will have no effect.
77 **/
78 UINT32 Txt : 1;
79 UINT32 SkipStopPbet : 1; ///< <b>(Test)</b> Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable.
80 ///
81 /// <b>(Test)</b> This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.
82 /// - 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.
83 /// - <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
84 ///
85 UINT32 EnableC6Dram : 1;
86 UINT32 ResetAux : 1; ///< <b>(Test)</b> Reset Auxiliary content, <b>0: Disabled</b>, 1: Enabled
87 UINT32 TxtAcheckRequest : 1; ///< <b>(Test)</b> AcheckRequest <b>0: Disabled</b>, 1: Enabled. When Enabled, it will call Acheck regardless of crashcode value
88 UINT32 RsvdBits : 24; ///< Reserved for future use
89 } CPU_SECURITY_PREMEM_CONFIG;
90
91 #pragma pack (pop)
92
93 #endif // _CPU_SECURITY_CONFIG_H_
CPU_SECURITY_PREMEM_CONFIG::SkipStopPbet
UINT32 SkipStopPbet
(Test) Skip Stop PBET Timer; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:79
CPU_SECURITY_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuSecurityPreMemConfig.h:88
CPU_SECURITY_PREMEM_CONFIG::EnableSgx
UINT32 EnableSgx
Enable or Disable Software Guard Extensions; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:71
CPU_SECURITY_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuSecurityPreMemConfig.h:53
CPU_SECURITY_PREMEM_CONFIG::BiosGuardToolsInterface
UINT32 BiosGuardToolsInterface
BIOS Guard Tools Interface; 0: Disable, 1:Enable.
Definition: CpuSecurityPreMemConfig.h:64
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_SECURITY_PREMEM_CONFIG::BiosGuard
UINT32 BiosGuard
Enable or Disable BIOS Guard; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:63
CPU_SECURITY_PREMEM_CONFIG::TxtAcheckRequest
UINT32 TxtAcheckRequest
(Test) AcheckRequest 0: Disabled, 1: Enabled. When Enabled, it will call Acheck regardless of crashco...
Definition: CpuSecurityPreMemConfig.h:87
CPU_SECURITY_PREMEM_CONFIG::ResetAux
UINT32 ResetAux
(Test) Reset Auxiliary content, 0: Disabled, 1: Enabled
Definition: CpuSecurityPreMemConfig.h:86
CPU_SECURITY_PREMEM_CONFIG::Txt
UINT32 Txt
Enable or Disable Trusted Execution Technology; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:78
CPU_SECURITY_PREMEM_CONFIG::EnableC6Dram
UINT32 EnableC6Dram
(Test) This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating...
Definition: CpuSecurityPreMemConfig.h:85
CPU_SECURITY_PREMEM_CONFIG
CPU Security PreMemory Configuration Structure.
Definition: CpuSecurityPreMemConfig.h:52
CPU_SECURITY_PREMEM_CONFIG::BiosSize
UINT16 BiosSize
Flash information for BIOS Guard: BIOS Size in KB.
Definition: CpuSecurityPreMemConfig.h:55
CPU_SECURITY_PREMEM_CONFIG::PrmrrSize
UINT32 PrmrrSize
PRMRR Size.Software Control: 0x0 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000,...
Definition: CpuSecurityPreMemConfig.h:54
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuTestConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuTestConfig.h File Reference

CPU Test Config Block. More...

Go to the source code of this file.

Classes

struct CPU_TEST_CONFIG
CPU Test Configuration Structure. More...

Detailed Description

CPU Test Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuTestConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuTestConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuTestConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Test Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_TEST_CONFIG_H_
36 #define _CPU_TEST_CONFIG_H_
37
38 #define CPU_TEST_CONFIG_REVISION 3
39
40 extern EFI_GUID gCpuTestConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Test Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 <b>Revision 2</b>:
50 - Removed Voltage Optimization feature.
51 <b>Revision 3</b>:
52 - Add PostedInterruptCapability
53 **/
54 typedef struct {
55 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
56 UINT32 MlcStreamerPrefetcher : 1; ///< Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
57 UINT32 MlcSpatialPrefetcher : 1; ///< Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>.
58 UINT32 MonitorMwaitEnable : 1; ///< Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
59 UINT32 MachineCheckEnable : 1; ///< Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
60 UINT32 ProcessorTraceOutputScheme : 1; ///< Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
61 UINT32 ProcessorTraceEnable : 1; ///< Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
62 UINT32 ThreeStrikeCounterDisable : 1; ///< Disable Three strike counter; <b>0: FALSE</b>; 1: TRUE.
63 UINT32 RsvdBits : 25; ///< Reserved for future use
64 /**
65 Memory size per thread for Processor Trace.
66 Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.
67 - <b>0: Disable</b>
68 **/
69 UINT32 ProcessorTraceMemSize;
70 } CPU_TEST_CONFIG;
71
72 #pragma pack (pop)
73
74 #endif // _CPU_TEST_CONFIG_H_
CPU_TEST_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuTestConfig.h:55
CPU_TEST_CONFIG::MonitorMwaitEnable
UINT32 MonitorMwaitEnable
Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:58
CPU_TEST_CONFIG::MlcStreamerPrefetcher
UINT32 MlcStreamerPrefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:56
CPU_TEST_CONFIG::MlcSpatialPrefetcher
UINT32 MlcSpatialPrefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_TEST_CONFIG::ThreeStrikeCounterDisable
UINT32 ThreeStrikeCounterDisable
Disable Three strike counter; 0: FALSE; 1: TRUE.
Definition: CpuTestConfig.h:62
CPU_TEST_CONFIG::MachineCheckEnable
UINT32 MachineCheckEnable
Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:59
CPU_TEST_CONFIG::ProcessorTraceEnable
UINT32 ProcessorTraceEnable
Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:61
CPU_TEST_CONFIG::ProcessorTraceOutputScheme
UINT32 ProcessorTraceOutputScheme
Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.
Definition: CpuTestConfig.h:60
CPU_TEST_CONFIG::ProcessorTraceMemSize
UINT32 ProcessorTraceMemSize
Memory size per thread for Processor Trace.
Definition: CpuTestConfig.h:69
CPU_TEST_CONFIG
CPU Test Configuration Structure.
Definition: CpuTestConfig.h:54
CPU_TEST_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuTestConfig.h:63
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuTxtConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuTxtConfig.h File Reference

CPU TXT PreMemory Config Block. More...

Go to the source code of this file.

Classes

struct CPU_TXT_PREMEM_CONFIG
CPU TXT PreMemory Configuration Structure. More...

Detailed Description

CPU TXT PreMemory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuTxtConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuTxtConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuTxtConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU TXT PreMemory Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_TXT_CONFIG_H_
36 #define _CPU_TXT_CONFIG_H_
37
38 #define CPU_TXT_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gCpuTxtPreMemConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU TXT PreMemory Configuration Structure.
46 @note <b>Optional.</b> These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> Txt is disabled, or PeiTxtLibNull is used.
47
48 <b>Revision 1</b>:
49 - Initial version.
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 UINT32 SinitMemorySize; ///< Size of SINIT module if installed in flash part. Zero otherwise.
54 UINT32 TxtHeapMemorySize; ///< Size of memory reserved for TXT Heap. This memory is used by MLE.
55 UINT32 TxtDprMemorySize; ///< Size of DPR protected memory reserved for Intel TXT component.
56 EFI_PHYSICAL_ADDRESS TxtDprMemoryBase; ///< Base address of DPR protected memory reserved for Intel TXT component.
57 UINT64 TxtLcpPdSize; ///< Size of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
58 EFI_PHYSICAL_ADDRESS TxtLcpPdBase; ///< Base address of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
59 EFI_PHYSICAL_ADDRESS ApStartupBase; ///< Base address of TXT AP Startup code
60 EFI_PHYSICAL_ADDRESS BiosAcmBase; ///< Base address of BIOS ACM in flash part
61 UINT32 BiosAcmSize; ///< Size of ACM Binary.
62 UINT32 TgaSize; ///< Size of Trusted Graphics Aperture if supported by chipset.
63 UINT32 IsTPMPresence;
64 UINT8 Reserved[4];
65 } CPU_TXT_PREMEM_CONFIG;
66
67 #pragma pack (pop)
68
69 #endif // _CPU_TXT_CONFIG_H_
CPU_TXT_PREMEM_CONFIG::BiosAcmSize
UINT32 BiosAcmSize
Size of ACM Binary.
Definition: CpuTxtConfig.h:61
CPU_TXT_PREMEM_CONFIG::TgaSize
UINT32 TgaSize
Size of Trusted Graphics Aperture if supported by chipset.
Definition: CpuTxtConfig.h:62
CPU_TXT_PREMEM_CONFIG::BiosAcmBase
EFI_PHYSICAL_ADDRESS BiosAcmBase
Base address of BIOS ACM in flash part.
Definition: CpuTxtConfig.h:60
CPU_TXT_PREMEM_CONFIG::ApStartupBase
EFI_PHYSICAL_ADDRESS ApStartupBase
Base address of TXT AP Startup code.
Definition: CpuTxtConfig.h:59
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_TXT_PREMEM_CONFIG
CPU TXT PreMemory Configuration Structure.
Definition: CpuTxtConfig.h:51
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
CPU_TXT_PREMEM_CONFIG::TxtDprMemorySize
UINT32 TxtDprMemorySize
Size of DPR protected memory reserved for Intel TXT component.
Definition: CpuTxtConfig.h:55
CPU_TXT_PREMEM_CONFIG::TxtDprMemoryBase
EFI_PHYSICAL_ADDRESS TxtDprMemoryBase
Base address of DPR protected memory reserved for Intel TXT component.
Definition: CpuTxtConfig.h:56
CPU_TXT_PREMEM_CONFIG::TxtHeapMemorySize
UINT32 TxtHeapMemorySize
Size of memory reserved for TXT Heap. This memory is used by MLE.
Definition: CpuTxtConfig.h:54
CPU_TXT_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuTxtConfig.h:52
CPU_TXT_PREMEM_CONFIG::SinitMemorySize
UINT32 SinitMemorySize
Size of SINIT module if installed in flash part. Zero otherwise.
Definition: CpuTxtConfig.h:53
CPU_TXT_PREMEM_CONFIG::TxtLcpPdSize
UINT64 TxtLcpPdSize
Size of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
Definition: CpuTxtConfig.h:57
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
CPU_TXT_PREMEM_CONFIG::TxtLcpPdBase
EFI_PHYSICAL_ADDRESS TxtLcpPdBase
Base address of Platform Default Launch Control Policy data if installed in flash part....
Definition: CpuTxtConfig.h:58
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: DciConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
Classes
DciConfig.h File Reference

Dci policy. More...

Go to the source code of this file.

Classes

struct PCH_DCI_PREMEM_CONFIG
The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI) More...

Detailed Description

Dci policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DciConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: DciConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
DciConfig.h
Go to the documentation of this file.
1 /** @file
2 Dci policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DCI_CONFIG_H_
36 #define _DCI_CONFIG_H_
37
38 #define PCH_DCI_PREMEM_CONFIG_REVISION 3
39 extern EFI_GUID gDciPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 typedef enum {
44 DciDbcDisabled = 0x0,
45 DciDbcUsb2 = 0x1,
46 DciDbcUsb3 = 0x2,
47 DciDbcBoth = 0x3,
48 DciDbcNoChange = 0x4,
49 DciDbcMax
50 } DCI_DBC_MODE;
51
52 typedef enum {
53 Usb3TcDbgDisabled = 0x0,
54 Usb3TcDbgEnabled = 0x1,
55 Usb3TcDbgNoChange = 0x2,
56 Usb3TcDbgMax
57 } DCI_USB3_TYPE_C_DEBUG_MODE;
58
59 /**
60 The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
61
62 <b>Revision 1</b>:
63 - Initial version.
64 <b>Revision 2</b>:
65 - Added DciModphyPg
66 - change to use data in byte unit rather than bit-field
67 <b>Revision 3</b>:
68 - Deprecated DciModphyPg
69 - Added DciClkEnable, KeepEarlyTrace
70 **/
71 typedef struct {
72 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
73 /**
74 DCI enable.
75 Determine if to enable DCI debug from host.
76 <b>0:Disabled</b>; 1:Enabled
77 **/
78 UINT8 DciEn;
79 /**
80 USB DbC enable mode.
81 Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value
82 Refer to definition of DCI_USB_DBC_MODE for supported settings.
83 0:Disabled; 1:USB2; 2:USB3; 3:Both; <b>4:No Change</b>
84 **/
85 UINT8 DciDbcMode;
86 UINT8 DciModphyPg; ///< Deprecated
87 /**
88 USB3 Type-C UFP2DFP kenel / platform debug support. No change will do nothing to UFP2DFP configuration.
89 When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP (downstream-facing port) for first connection.
90 It must be enabled for USB3 kernel(kernel mode debug) and platform debug(DFx, DMA, Trace) over UFP Type-C receptacle.
91 Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported settings.
92 0:Disabled; 1:Enabled; <b>2:No Change</b>
93 **/
94 UINT8 DciUsb3TypecUfpDbg;
95 /**
96 Determine if to enable or disable DCI clock request in lowest power state.
97 0:Disabled; <b>1:Enabled</b>
98 **/
99 UINT8 DciClkEnable;
100 /**
101 Early trace is activated by default.
102 Enable to keep early trace data and keep tracing; disable to stop tracing;
103 When debug probe is connected and granted, force to no change, let host tool to set it.
104 <b>0: Disable</b>; 1: Enable early trace; 2:No Change;
105 **/
106 UINT8 KeepEarlyTrace;
107 UINT8 ReservedBytes[2];
108 } PCH_DCI_PREMEM_CONFIG;
109
110 #pragma pack (pop)
111
112 #endif // _DCI_CONFIG_H_
PCH_DCI_PREMEM_CONFIG::DciEn
UINT8 DciEn
DCI enable.
Definition: DciConfig.h:78
PCH_DCI_PREMEM_CONFIG::KeepEarlyTrace
UINT8 KeepEarlyTrace
Early trace is activated by default.
Definition: DciConfig.h:106
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_DCI_PREMEM_CONFIG::DciDbcMode
UINT8 DciDbcMode
USB DbC enable mode.
Definition: DciConfig.h:85
PCH_DCI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: DciConfig.h:72
PCH_DCI_PREMEM_CONFIG::DciClkEnable
UINT8 DciClkEnable
Determine if to enable or disable DCI clock request in lowest power state.
Definition: DciConfig.h:99
PCH_DCI_PREMEM_CONFIG::DciModphyPg
UINT8 DciModphyPg
Deprecated.
Definition: DciConfig.h:86
PCH_DCI_PREMEM_CONFIG::DciUsb3TypecUfpDbg
UINT8 DciUsb3TypecUfpDbg
USB3 Type-C UFP2DFP kenel / platform debug support.
Definition: DciConfig.h:94
PCH_DCI_PREMEM_CONFIG
The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
Definition: DciConfig.h:71
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EspiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Classes
EspiConfig.h File Reference

Espi policy. More...

Go to the source code of this file.

Classes

struct PCH_ESPI_CONFIG
This structure contains the policies which are related to ESPI. More...

Detailed Description

Espi policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file EspiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: EspiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
EspiConfig.h
Go to the documentation of this file.
1 /** @file
2 Espi policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ESPI_CONFIG_H_
36 #define _ESPI_CONFIG_H_
37
38 #define PCH_ESPI_CONFIG_REVISION 2
39 extern EFI_GUID gEspiConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure contains the policies which are related to ESPI.
45
46 <b>Revision 1</b>:
47 - Initial revision
48 <b>Revision 2</b>:
49 - Added LockLinkConfiguration field to config block
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 /**
54 LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range
55 specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).
56 <b>0: FALSE</b>, 1: TRUE
57 **/
58 UINT32 LgmrEnable : 1;
59 /**
60 eSPI host and device BME settings.
61 When TRUE, then the BME bit enabled in eSPI host and device.
62 0: FALSE, <b>1: TRUE </b>
63 **/
64 UINT32 BmeMasterSlaveEnabled : 1;
65 /**
66 Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE)
67 <b>0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ignored)</b>
68 1b: Enable HOST_C10 reporting to device via eSPI Virtual Wire (upon receiving a HOST_C10 indication from PMC)
69 **/
70 UINT32 HostC10ReportEnable : 1;
71 /**
72 eSPI Link Configuration Lock (SBLCL)
73 If set to TRUE then communication through SET_CONFIG/GET_CONFIG
74 to eSPI device addresses from range 0x0 - 0x7FF
75 <b>1: TRUE</b>, 0: FALSE
76 **/
77 UINT32 LockLinkConfiguration : 1;
78 /**
79 Hardware Autonomous Enable (HAE)
80 If set to TRUE, then the IP may request a PG whenever it is idle
81 **/
82 UINT32 EspiPmHAE : 1;
83 UINT32 RsvdBits : 27; ///< Reserved bits
84 } PCH_ESPI_CONFIG;
85
86 #pragma pack (pop)
87
88 #endif // _ESPI_CONFIG_H_
89
PCH_ESPI_CONFIG::LgmrEnable
UINT32 LgmrEnable
LPC (eSPI) Memory Range Decode Enable.
Definition: EspiConfig.h:58
PCH_ESPI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits.
Definition: EspiConfig.h:83
PCH_ESPI_CONFIG::LockLinkConfiguration
UINT32 LockLinkConfiguration
eSPI Link Configuration Lock (SBLCL) If set to TRUE then communication through SET_CONFIG/GET_CONFIG ...
Definition: EspiConfig.h:77
PCH_ESPI_CONFIG::HostC10ReportEnable
UINT32 HostC10ReportEnable
Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE) 0b: Disable HOST_C10 reporting (HOST_C10 ind...
Definition: EspiConfig.h:70
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_ESPI_CONFIG::EspiPmHAE
UINT32 EspiPmHAE
Hardware Autonomous Enable (HAE) If set to TRUE, then the IP may request a PG whenever it is idle.
Definition: EspiConfig.h:82
PCH_ESPI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: EspiConfig.h:52
PCH_ESPI_CONFIG
This structure contains the policies which are related to ESPI.
Definition: EspiConfig.h:51
PCH_ESPI_CONFIG::BmeMasterSlaveEnabled
UINT32 BmeMasterSlaveEnabled
eSPI host and device BME settings.
Definition: EspiConfig.h:64
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FirmwareVersionInfoHob.h File Reference

  • Intel
  • AlderLakeFspBinPkg
  • Include
Classes
FirmwareVersionInfoHob.h File Reference

Header file for Firmware Version Information. More...

#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
Include dependency graph for FirmwareVersionInfoHob.h:

Go to the source code of this file.

Classes

struct | FIRMWARE_VERSION
Firmware Version Structure. More...
struct | FIRMWARE_VERSION_INFO
Firmware Version Information Structure. More...
struct | SMBIOS_STRUCTURE
The Smbios structure header. More...
struct | FIRMWARE_VERSION_INFO_HOB
Firmware Version Information HOB Structure. More...

Detailed Description

Header file for Firmware Version Information.

Copyright
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file FirmwareVersionInfoHob.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FirmwareVersionInfoHob.h Source File

  • Intel
  • AlderLakeFspBinPkg
  • Include
FirmwareVersionInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for Firmware Version Information
3
4 @copyright
5 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
6
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License which accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _FIRMWARE_VERSION_INFO_HOB_H_
18 #define _FIRMWARE_VERSION_INFO_HOB_H_
19
20 #include <Uefi/UefiMultiPhase.h>
21 #include <Pi/PiBootMode.h>
22 #include <Pi/PiHob.h>
23
24 #pragma pack(1)
25 ///
26 /// Firmware Version Structure
27 ///
28 typedef struct {
29 UINT8 MajorVersion;
30 UINT8 MinorVersion;
31 UINT8 Revision;
32 UINT16 BuildNumber;
33 } FIRMWARE_VERSION;
34
35 ///
36 /// Firmware Version Information Structure
37 ///
38 typedef struct {
39 UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
40 UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
41 FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
42 } FIRMWARE_VERSION_INFO;
43
44 #ifndef __SMBIOS_STANDARD_H__
45 ///
46 /// The Smbios structure header.
47 ///
48 typedef struct {
49 UINT8 Type;
50 UINT8 Length;
51 UINT16 Handle;
52 } SMBIOS_STRUCTURE;
53 #endif
54
55 ///
56 /// Firmware Version Information HOB Structure
57 ///
58 typedef struct {
59 EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
60 SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
61 UINT8 Count; ///< Offset 28 Number of FVI elements included.
62 ///
63 /// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
64 ///
65 } FIRMWARE_VERSION_INFO_HOB;
66 #pragma pack()
67
68 #endif // _FIRMWARE_VERSION_INFO_HOB_H_
SMBIOS_STRUCTURE
The Smbios structure header.
Definition: FirmwareVersionInfoHob.h:48
FIRMWARE_VERSION_INFO_HOB::Count
UINT8 Count
Offset 28 Number of FVI elements included.
Definition: FirmwareVersionInfoHob.h:61
FIRMWARE_VERSION_INFO_HOB::Header
EFI_HOB_GUID_TYPE Header
Offset 0-23 The header of FVI HOB.
Definition: FirmwareVersionInfoHob.h:59
FIRMWARE_VERSION_INFO_HOB
Firmware Version Information HOB Structure.
Definition: FirmwareVersionInfoHob.h:58
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:338
FIRMWARE_VERSION_INFO_HOB::SmbiosData
SMBIOS_STRUCTURE SmbiosData
Offset 24-27 The SMBIOS header of FVI HOB.
Definition: FirmwareVersionInfoHob.h:60
FIRMWARE_VERSION_INFO::ComponentNameIndex
UINT8 ComponentNameIndex
Offset 0 Index of Component Name.
Definition: FirmwareVersionInfoHob.h:39
PiHob.h
HOB related definitions in PI.
FIRMWARE_VERSION
Firmware Version Structure.
Definition: FirmwareVersionInfoHob.h:28
FIRMWARE_VERSION_INFO::Version
FIRMWARE_VERSION Version
Offset 2-6 Firmware version.
Definition: FirmwareVersionInfoHob.h:41
FIRMWARE_VERSION_INFO
Firmware Version Information Structure.
Definition: FirmwareVersionInfoHob.h:38
FIRMWARE_VERSION_INFO::VersionStringIndex
UINT8 VersionStringIndex
Offset 1 Index of Version String.
Definition: FirmwareVersionInfoHob.h:40
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FivrConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
Classes | Macros | Enumerations
FivrConfig.h File Reference

PCH FIVR policy. More...

Go to the source code of this file.

Classes

struct | FIVR_EXT_RAIL_CONFIG
Structure for V1p05/Vnn VR rail configuration. More...
struct | FIVR_VCCIN_AUX_CONFIG
Structure for VCCIN_AUX voltage rail configuration. More...
struct | PCH_FIVR_CONFIG
The PCH_FIVR_CONFIG block describes FIVR settings. More...

Macros

#define PCH_FIVR_CONFIG_REVISION 2
Revision 1: - Initial version. More...

Enumerations

enum FIVR_RAIL_SX_STATE
Rail support in S0ix and Sx Settings other than FivrRailDisabled can be OR'ed.

Detailed Description

PCH FIVR policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FivrConfig.h.

Macro Definition Documentation

◆ PCH_FIVR_CONFIG_REVISION

#define PCH_FIVR_CONFIG_REVISION 2

Revision 1: - Initial version.

Revision 2: - Added BypassFivrConfig

Definition at line 42 of file FivrConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FivrConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
FivrConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH FIVR policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FIVR_CONFIG_H_
36 #define _FIVR_CONFIG_H_
37
38 /**
39 <b>Revision 1</b>: - Initial version.
40 <b>Revision 2</b>: - Added BypassFivrConfig
41 **/
42 #define PCH_FIVR_CONFIG_REVISION 2
43 extern EFI_GUID gFivrConfigGuid;
44
45 #pragma pack (push,1)
46
47 /**
48 Rail support in S0ix and Sx
49 Settings other than FivrRailDisabled can be OR'ed
50 **/
51 typedef enum {
52 FivrRailDisabled = 0,
53 FivrRailInS0i1S0i2 = BIT0,
54 FivrRailInS0i3 = BIT1,
55 FivrRailInS3 = BIT2,
56 FivrRailInS4 = BIT3,
57 FivrRailInS5 = BIT4,
58 FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
59 FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
60 FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
61 } FIVR_RAIL_SX_STATE;
62
63 typedef enum {
64 FivrRetentionActive = BIT0,
65 FivrNormActive = BIT1,
66 FivrMinActive = BIT2,
67 FivrMinRetention = BIT3
68 } FIVR_RAIL_SUPPORTED_VOLTAGE;
69
70 /**
71 Structure for V1p05/Vnn VR rail configuration
72 **/
73 typedef struct {
74 /**
75 Mask to enable the usage of external VR rail in specific S0ix or Sx states
76 Use values from FIVR_RAIL_SX_STATE
77 The default is <b>FivrRailDisabled</b>.
78 **/
79 UINT32 EnabledStates : 6;
80
81 /**
82 VR rail voltage value that will be used in S0i2/S0i3 states.
83 This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
84 The default for Vnn is set to <b>420 - 1050 mV</b>.
85 **/
86 UINT32 Voltage : 11;
87 /**
88 @deprecated
89 THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
90 VR rail Icc Max Value
91 Granularity of this setting is 1mA and maximal possible value is 500mA
92 The default is <b> 0mA </b>.
93 **/
94 UINT32 IccMax : 8;
95 /**
96 UINT32 Alignement
97 **/
98 UINT32 RsvdBits1 : 7;
99 /**
100 This register holds the control hold off values to be used when
101 changing the rail control for external bypass value in us
102 **/
103 UINT32 CtrlRampTmr : 8;
104
105 /**
106 Mask to set the supported configuration in VR rail.
107 Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
108 **/
109 UINT32 SupportedVoltageStates : 4;
110
111 /**
112 VR rail Icc Maximum Value
113 Granularity of this setting is 1mA and maximal possible value is 500mA
114 The default is <b> 0mA </b>.
115 **/
116 UINT32 IccMaximum : 16;
117 /**
118 UINT32 Alignment
119 **/
120 UINT32 RsvdBits2 : 4;
121
122 } FIVR_EXT_RAIL_CONFIG;
123
124
125 /**
126 Structure for VCCIN_AUX voltage rail configuration
127 **/
128 typedef struct {
129 /**
130 Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
131 Voltage transition time required by motherboard voltage regulator when PCH changes
132 the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
133 This field has 1us resolution.
134 When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
135 The default is <b> 0xC </b>.
136 **/
137 UINT8 LowToHighCurModeVolTranTime;
138
139 /**
140 Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
141 Voltage transition time required by motherboard voltage regulator when PCH changes
142 the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
143 This field has 1us resolution.
144 When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
145 The default is <b> 0x36 </b>.
146 **/
147 UINT8 RetToHighCurModeVolTranTime;
148
149 /**
150 Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
151 Voltage transition time required by motherboard voltage regulator when PCH changes
152 the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
153 This field has 1us resolution.
154 When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
155 The default is <b> 0x2B </b>.
156 **/
157 UINT8 RetToLowCurModeVolTranTime;
158 UINT8 RsvdByte1;
159 /**
160 Transition time in microseconds from Off (0V) to High Current Mode Voltage.
161 Voltage transition time required by motherboard voltage regulator when PCH changes
162 the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
163 This field has 1us resolution.
164 0 = Transition to 0V is disabled
165 Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
166 in all S0 & Sx power states after initial start up on G3 exit
167 The default is <b> 0x96 </b>.
168 **/
169 UINT32 OffToHighCurModeVolTranTime : 11;
170 UINT32 RsvdBits1 : 21;
171 } FIVR_VCCIN_AUX_CONFIG;
172
173 /**
174 The PCH_FIVR_CONFIG block describes FIVR settings.
175 **/
176 typedef struct {
177 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
178 /**
179 External V1P05 VR rail configuration.
180 **/
181 FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
182 /**
183 External Vnn VR rail configuration.
184 **/
185 FIVR_EXT_RAIL_CONFIG ExtVnnRail;
186 /**
187 Additional External Vnn VR rail configuration that will get applied
188 in Sx entry SMI callback. Required only if External Vnn VR
189 needs different settings for Sx than those specified in ExtVnnRail.
190 **/
191 FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
192 /**
193 VCCIN_AUX voltage rail configuration.
194 **/
195 FIVR_VCCIN_AUX_CONFIG VccinAux;
196
197 /**
198 Enable/Disable FIVR Dynamic Power Management
199 Default is <b> 1 </b>.
200 **/
201 UINT32 FivrDynPm : 1;
202 /**
203 Enable/Disable Bypass of FIVR configuration
204 Default is <b> 0 </b>.
205 **/
206 UINT32 BypassFivrConfig : 1;
207 UINT32 RsvdBits2 : 30;
208 } PCH_FIVR_CONFIG;
209
210 #pragma pack (pop)
211
212 #endif // _FIVR_CONFIG_H_
PCH_FIVR_CONFIG::BypassFivrConfig
UINT32 BypassFivrConfig
Enable/Disable Bypass of FIVR configuration Default is 0 .
Definition: FivrConfig.h:206
FIVR_EXT_RAIL_CONFIG::IccMaximum
UINT32 IccMaximum
VR rail Icc Maximum Value Granularity of this setting is 1mA and maximal possible value is 500mA The ...
Definition: FivrConfig.h:116
PCH_FIVR_CONFIG
The PCH_FIVR_CONFIG block describes FIVR settings.
Definition: FivrConfig.h:176
FIVR_EXT_RAIL_CONFIG
Structure for V1p05/Vnn VR rail configuration.
Definition: FivrConfig.h:73
FIVR_VCCIN_AUX_CONFIG::OffToHighCurModeVolTranTime
UINT32 OffToHighCurModeVolTranTime
Transition time in microseconds from Off (0V) to High Current Mode Voltage.
Definition: FivrConfig.h:169
PCH_FIVR_CONFIG::ExtV1p05Rail
FIVR_EXT_RAIL_CONFIG ExtV1p05Rail
External V1P05 VR rail configuration.
Definition: FivrConfig.h:181
PCH_FIVR_CONFIG::VccinAux
FIVR_VCCIN_AUX_CONFIG VccinAux
VCCIN_AUX voltage rail configuration.
Definition: FivrConfig.h:195
PCH_FIVR_CONFIG::ExtVnnRail
FIVR_EXT_RAIL_CONFIG ExtVnnRail
External Vnn VR rail configuration.
Definition: FivrConfig.h:185
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
FIVR_VCCIN_AUX_CONFIG::RetToLowCurModeVolTranTime
UINT8 RetToLowCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
Definition: FivrConfig.h:157
FIVR_RAIL_SX_STATE
FIVR_RAIL_SX_STATE
Rail support in S0ix and Sx Settings other than FivrRailDisabled can be OR'ed.
Definition: FivrConfig.h:51
FIVR_EXT_RAIL_CONFIG::Voltage
UINT32 Voltage
VR rail voltage value that will be used in S0i2/S0i3 states.
Definition: FivrConfig.h:86
PCH_FIVR_CONFIG::FivrDynPm
UINT32 FivrDynPm
Enable/Disable FIVR Dynamic Power Management Default is 1 .
Definition: FivrConfig.h:201
FIVR_EXT_RAIL_CONFIG::CtrlRampTmr
UINT32 CtrlRampTmr
This register holds the control hold off values to be used when changing the rail control for externa...
Definition: FivrConfig.h:103
FIVR_EXT_RAIL_CONFIG::SupportedVoltageStates
UINT32 SupportedVoltageStates
Mask to set the supported configuration in VR rail.
Definition: FivrConfig.h:109
PCH_FIVR_CONFIG::ExtVnnRailSx
FIVR_EXT_RAIL_CONFIG ExtVnnRailSx
Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback.
Definition: FivrConfig.h:191
FIVR_EXT_RAIL_CONFIG::EnabledStates
UINT32 EnabledStates
Mask to enable the usage of external VR rail in specific S0ix or Sx states Use values from FIVR_RAIL_...
Definition: FivrConfig.h:79
FIVR_VCCIN_AUX_CONFIG
Structure for VCCIN_AUX voltage rail configuration.
Definition: FivrConfig.h:128
FIVR_VCCIN_AUX_CONFIG::LowToHighCurModeVolTranTime
UINT8 LowToHighCurModeVolTranTime
Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
Definition: FivrConfig.h:137
FIVR_EXT_RAIL_CONFIG::IccMax
UINT32 IccMax
Definition: FivrConfig.h:94
FIVR_VCCIN_AUX_CONFIG::RetToHighCurModeVolTranTime
UINT8 RetToHighCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
Definition: FivrConfig.h:147
PCH_FIVR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: FivrConfig.h:177
FIVR_EXT_RAIL_CONFIG::RsvdBits2
UINT32 RsvdBits2
UINT32 Alignment.
Definition: FivrConfig.h:120
FIVR_EXT_RAIL_CONFIG::RsvdBits1
UINT32 RsvdBits1
UINT32 Alignement.
Definition: FivrConfig.h:98
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspErrorInfo.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
Classes | Macros
FspErrorInfo.h File Reference

FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios. More...

Go to the source code of this file.

Classes

struct FSP_ERROR_INFO_HOB
FSP Error Information Block. More...

Macros

#define FSP_ERROR_INFO_HOB_GUID
GUID value indicating the FSP error information.

Detailed Description

FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FspErrorInfo.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspErrorInfo.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
FspErrorInfo.h
Go to the documentation of this file.
1 /** @file
2 FSP Error Information HOB to describe errors inside FSP that bootloader may
3 take some actions to handle those error scenarios.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2019 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _FSP_ERROR_INFO_H_
38 #define _FSP_ERROR_INFO_H_
39
40 ///
41 /// GUID value indicating the FSP error information.
42 ///
43 #define FSP_ERROR_INFO_HOB_GUID \
44 { \
45 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } \
46 }
47 #define STATUS_CODE_DATA_TYPE_FSP_ERROR_GUID \
48 { \
49 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } \
50 }
51
52 #define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
53 #define FSP_ERROR_INFO_STATUS_CODE_VALUE 0
54 #define FSP_ERROR_INFO_STATUS_CODE_INSTANCE 0
55
56 ///
57 /// FSP Error Information Block.
58 ///
59 #pragma pack(1)
60 typedef struct {
61 ///
62 /// GUID HOB header.
63 ///
64 EFI_HOB_GUID_TYPE GuidHob;
65
66 ///
67 /// ReportStatusCode () type identifier.
68 ///
69 EFI_STATUS_CODE_TYPE Type;
70
71 ///
72 /// ReportStatusCode () value.
73 ///
74 EFI_STATUS_CODE_VALUE Value;
75
76 ///
77 /// ReportStatusCode () Instance number.
78 ///
79 UINT32 Instance;
80
81 ///
82 /// Optional GUID which may be used to identify
83 /// which internal component of the FSP was
84 /// executing at the time of the error.
85 ///
86 EFI_GUID CallerId;
87
88 ///
89 /// GUID identifying the nature of the fatal error.
90 ///
91 EFI_GUID ErrorType;
92
93 ///
94 /// EFI_STATUS code describing the error encountered.
95 ///
96 UINT32 Status;
97 } FSP_ERROR_INFO_HOB;
98
99 typedef struct {
100 ///
101 /// A GUID identifying the nature of the fatal error.
102 /// This GUID is platform speciic.
103 ///
104 EFI_GUID ErrorType;
105
106 ///
107 /// A code describing the error encountered.
108 ///
109 EFI_STATUS Status;
110 } FSP_ERROR_INFO;
111
112 #pragma pack()
113
114 extern GUID gFspErrorInfoHobGuid;
115
116 #endif //_FSP_ERROR_INFO_H_
FSP_ERROR_INFO_HOB::Value
EFI_STATUS_CODE_VALUE Value
ReportStatusCode () value.
Definition: FspErrorInfo.h:74
FSP_ERROR_INFO_HOB::CallerId
EFI_GUID CallerId
Optional GUID which may be used to identify which internal component of the FSP was executing at the ...
Definition: FspErrorInfo.h:86
FSP_ERROR_INFO_HOB::Instance
UINT32 Instance
ReportStatusCode () Instance number.
Definition: FspErrorInfo.h:79
FSP_ERROR_INFO_HOB::Status
UINT32 Status
EFI_STATUS code describing the error encountered.
Definition: FspErrorInfo.h:96
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
FSP_ERROR_INFO_HOB
FSP Error Information Block.
Definition: FspErrorInfo.h:60
FSP_ERROR_INFO_HOB::GuidHob
EFI_HOB_GUID_TYPE GuidHob
GUID HOB header.
Definition: FspErrorInfo.h:64
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:338
FSP_ERROR_INFO_HOB::Type
EFI_STATUS_CODE_TYPE Type
ReportStatusCode () type identifier.
Definition: FspErrorInfo.h:69
FSP_ERROR_INFO_HOB::ErrorType
EFI_GUID ErrorType
GUID identifying the nature of the fatal error.
Definition: FspErrorInfo.h:91
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspFixedPcds.h File Reference

  • Intel
  • AlderLakeFspBinPkg
  • DoxygenInternalOnly
Macros
FspFixedPcds.h File Reference

This file lists all FixedAtBuild PCDs referenced in FSP integration guide. More...

Go to the source code of this file.

Macros

#define | PcdFspAreaBaseAddress 0xFFE00000
FspAreaBaseAddress.
#define | PcdFspImageIdString $ADLFSP$
FspImageIdString.
#define | PcdSiliconInitVersionMajor 0x0C
SiliconInitVersionMajor.
#define | PcdSiliconInitVersionMinor 0x00
SiliconInitVersionMinor.
#define | PcdSiliconInitVersionRevision 0x65
SiliconInitVersionRevision.
#define | PcdSiliconInitVersionBuild 0x70
SiliconInitVersionBuild.
#define | PcdGlobalDataPointerAddress 0xFED00148
GlobalDataPointerAddress.
#define | PcdTemporaryRamBase 0xFEF00000
TemporaryRamBase.
#define | PcdTemporaryRamSize 0x00100000
TemporaryRamSize.
#define | PcdFspReservedBufferSize 0x100
FspReservedBufferSize.

Detailed Description

This file lists all FixedAtBuild PCDs referenced in FSP integration guide.

Those value may vary in different FSP revision to meet different requirements.

Definition in file FspFixedPcds.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspFixedPcds.h Source File

  • Intel
  • AlderLakeFspBinPkg
  • DoxygenInternalOnly
FspFixedPcds.h
Go to the documentation of this file.
1 /** @file
2
3 This file lists all FixedAtBuild PCDs referenced in FSP integration guide.
4 Those value may vary in different FSP revision to meet different requirements.
5
6 **/
7
8 #ifndef __FSPFIXEDPCDS_H__
9 #define __FSPFIXEDPCDS_H__
10
11 #pragma pack(1)
12
13 #define PcdFspAreaBaseAddress 0xFFE00000 ///< FspAreaBaseAddress
14 #define PcdFspImageIdString $ADLFSP$ ///< FspImageIdString
15 #define PcdSiliconInitVersionMajor 0x0C ///< SiliconInitVersionMajor
16 #define PcdSiliconInitVersionMinor 0x00 ///< SiliconInitVersionMinor
17 #define PcdSiliconInitVersionRevision 0x65 ///< SiliconInitVersionRevision
18 #define PcdSiliconInitVersionBuild 0x70 ///< SiliconInitVersionBuild
19 #define PcdGlobalDataPointerAddress 0xFED00148 ///< GlobalDataPointerAddress
20 #define PcdTemporaryRamBase 0xFEF00000 ///< TemporaryRamBase
21 #define PcdTemporaryRamSize 0x00100000 ///< TemporaryRamSize
22 #define PcdFspReservedBufferSize 0x100 ///< FspReservedBufferSize
23 #pragma pack()
24
25 #endif
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspInfoHob.h File Reference

  • Intel
  • AlderLakeFspBinPkg
  • Include
FspInfoHob.h File Reference

Header file for FSP Information HOB. More...

Go to the source code of this file.

Detailed Description

Header file for FSP Information HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FspInfoHob.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspInfoHob.h Source File

  • Intel
  • AlderLakeFspBinPkg
  • Include
FspInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for FSP Information HOB.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _FSP_INFO_HOB_H_
37 #define _FSP_INFO_HOB_H_
38
39 extern EFI_GUID gFspInfoGuid;
40
41 #pragma pack (push, 1)
42
43 typedef struct {
44 UINT8 SiliconInitVersionMajor;
45 UINT8 SiliconInitVersionMinor;
46 UINT8 SiliconInitVersionRevision;
47 UINT8 SiliconInitVersionBuild;
48 UINT8 FspVersionRevision;
49 UINT8 FspVersionBuild;
50 UINT8 TimeStamp [12];
51 UINT8 FspVersionMinor;
52 } FSP_INFO_HOB;
53
54 #pragma pack (pop)
55
56 #endif // _FSP_INFO_HOB_H_
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspmArchConfigPpi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Macros
FspmArchConfigPpi.h File Reference

Header file for FSP-M Arch Config PPI. More...

Go to the source code of this file.

Classes

struct FSPM_ARCH_CONFIG_PPI
This PPI provides FSP-M Arch Config PPI. More...

Macros

#define FSPM_ARCH_CONFIG_GUID
Global ID for the FSPM_ARCH_CONFIG_PPI.

Detailed Description

Header file for FSP-M Arch Config PPI.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file FspmArchConfigPpi.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: FspmArchConfigPpi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
FspmArchConfigPpi.h
Go to the documentation of this file.
1 /** @file
2 Header file for FSP-M Arch Config PPI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
7
8 This program and the accompanying materials are licensed and made available under
9 the terms and conditions of the BSD License which accompanies this distribution.
10 The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #ifndef _FSPM_ARCH_CONFIG_PPI_H_
19 #define _FSPM_ARCH_CONFIG_PPI_H_
20
21 ///
22 /// Global ID for the FSPM_ARCH_CONFIG_PPI.
23 ///
24 #define FSPM_ARCH_CONFIG_GUID \
25 { \
26 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
27 }
28
29 ///
30 /// This PPI provides FSP-M Arch Config PPI.
31 ///
32 typedef struct {
33 UINT8 Revision;
34 UINT8 Reserved[3];
35 VOID *NvsBufferPtr;
36 UINT32 BootLoaderTolumSize;
37 UINT8 Reserved1[4];
38 } FSPM_ARCH_CONFIG_PPI;
39
40 extern EFI_GUID gFspmArchConfigPpiGuid;
41
42 #endif // _FSPM_ARCH_CONFIG_PPI_H_
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
FSPM_ARCH_CONFIG_PPI
This PPI provides FSP-M Arch Config PPI.
Definition: FspmArchConfigPpi.h:32
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GbeConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
Classes
GbeConfig.h File Reference

Gigabit Ethernet policy. More...

Go to the source code of this file.

Classes

struct GBE_CONFIG
PCH intergrated GBE controller configuration settings. More...

Detailed Description

Gigabit Ethernet policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GbeConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GbeConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
GbeConfig.h
Go to the documentation of this file.
1 /** @file
2 Gigabit Ethernet policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GBE_CONFIG_H_
36 #define _GBE_CONFIG_H_
37
38 #define GBE_CONFIG_REVISION 1
39 extern EFI_GUID gGbeConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 PCH intergrated GBE controller configuration settings.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 Determines if enable PCH internal GBE, 0: Disable; <b>1: Enable</b>.
50 When Enable is changed (from disabled to enabled or from enabled to disabled),
51 it needs to set LAN Disable regsiter, which might be locked by FDSWL register.
52 So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.
53 **/
54 UINT32 Enable : 1;
55 UINT32 LtrEnable : 1; ///< <b>0: Disable</b>; 1: Enable LTR capabilty of PCH internal LAN.
56 UINT32 RsvdBits0 : 30; ///< Reserved bits
57 } GBE_CONFIG;
58
59 #pragma pack (pop)
60
61 #endif // _GBE_CONFIG_H_
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GBE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: GbeConfig.h:47
GBE_CONFIG::Enable
UINT32 Enable
Determines if enable PCH internal GBE, 0: Disable; 1: Enable.
Definition: GbeConfig.h:54
GBE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: GbeConfig.h:56
GBE_CONFIG
PCH intergrated GBE controller configuration settings.
Definition: GbeConfig.h:46
GBE_CONFIG::LtrEnable
UINT32 LtrEnable
0: Disable; 1: Enable LTR capabilty of PCH internal LAN.
Definition: GbeConfig.h:55
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GnaConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
Classes
GnaConfig.h File Reference

Policy definition for GNA Config Block. More...

Go to the source code of this file.

Classes

struct GNA_CONFIG
GNA config block for configuring GNA. More...

Detailed Description

Policy definition for GNA Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GnaConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GnaConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
GnaConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition for GNA Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GNA_CONFIG_H_
36 #define _GNA_CONFIG_H_
37 #pragma pack(push, 1)
38
39 #define GNA_CONFIG_REVISION 1
40 /**
41 GNA config block for configuring GNA.\n
42 <b>Revision 1</b>:
43 - Initial version.
44 **/
45 typedef struct {
46 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
47 /**
48 Offset 28:0
49 This policy enables the GNA Device (SA Device 8) if supported.
50 If FALSE, all other policies in this config block will be ignored.
51 <b>1=TRUE</b>;
52 0=FALSE.
53 **/
54 UINT32 GnaEnable : 1;
55 UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved for future use
56 } GNA_CONFIG;
57 #pragma pack(pop)
58
59 #endif // _GNA_CONFIG_H_
GNA_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: GnaConfig.h:46
GNA_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 28:1 :Reserved for future use.
Definition: GnaConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GNA_CONFIG::GnaEnable
UINT32 GnaEnable
Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported.
Definition: GnaConfig.h:54
GNA_CONFIG
GNA config block for configuring GNA.
Definition: GnaConfig.h:45
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GpioConfig.h File Reference

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Classes | Macros | Typedefs | Enumerations
GpioConfig.h File Reference

Header file for GpioConfig structure used by GPIO library. More...

Go to the source code of this file.

Classes

struct GPIO_CONFIG
GPIO configuration structure used for pin programming. More...

Macros

#define | B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F
Mask for GPIO_INT_CONFIG for interrupt source.
#define | B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0
Mask for GPIO_INT_CONFIG for interrupt type.
#define | B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F
Mask for GPIO_ELECTRICAL_CONFIG for termination value.
#define | B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60
Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting.
#define | B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3
Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock.
#define | B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5
Mask for GPIO_LOCK_CONFIG for Pad Output Lock.
#define | B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3
Mask for GPIO_OTHER_CONFIG for RxRaw1 setting.

Typedefs

typedef UINT32 | GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
typedef UINT32 | GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.

Enumerations

enum | GPIO_HARDWARE_DEFAULT
enum | GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad. More...
enum | GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers. More...
enum | GPIO_DIRECTION
GPIO Direction. More...
enum | GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled. More...
enum | GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled. More...
enum | GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings. More...
enum | GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8. More...
enum | GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock. More...
enum | GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings: More...

Detailed Description

Header file for GpioConfig structure used by GPIO library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioConfig.h.

Enumeration Type Documentation

◆ GPIO_DIRECTION

enum GPIO_DIRECTION

GPIO Direction.

Enumerator
GpioDirDefault | Leave pad direction setting unmodified.
GpioDirInOut | Set pad for both output and input.
GpioDirInInvOut | Set pad for both output and input with inversion.
GpioDirIn | Set pad for input only.
GpioDirInInv | Set pad for input with inversion.
GpioDirOut | Set pad for output only.
GpioDirNone | Disable both output and input.

Definition at line 167 of file GpioConfig.h.

◆ GPIO_ELECTRICAL_CONFIG

enum GPIO_ELECTRICAL_CONFIG

GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.

Enumerator
GpioTermDefault | Leave termination setting unmodified.
GpioTermNone | none
GpioTermWpd5K | 5kOhm weak pull-down
GpioTermWpd20K | 20kOhm weak pull-down
GpioTermWpu1K | 1kOhm weak pull-up
GpioTermWpu2K | 2kOhm weak pull-up
GpioTermWpu5K | 5kOhm weak pull-up
GpioTermWpu20K | 20kOhm weak pull-up
GpioTermWpu1K2K | 1kOhm & 2kOhm weak pull-up
GpioTermNative | Native function controls pads termination This setting is applicable only to some native modes. Please check EDS to determine which native functionality can control pads termination
GpioNoTolerance1v8 | Disable 1.8V pad tolerance.
GpioTolerance1v8 | Enable 1.8V pad tolerance.

Definition at line 296 of file GpioConfig.h.

◆ GPIO_HARDWARE_DEFAULT

enum GPIO_HARDWARE_DEFAULT
Enumerator
GpioHardwareDefault

Leave setting unmodified.

Definition at line 118 of file GpioConfig.h.

◆ GPIO_HOSTSW_OWN

enum GPIO_HOSTSW_OWN

Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.

Depending on chosen ownership some GPIO Interrupt status register get updated and other masked. Please refer to EDS for HOSTSW_OWN register description.

Enumerator
GpioHostOwnDefault | Leave ownership value unmodified.
GpioHostOwnAcpi | Set HOST ownership to ACPI. Use this setting if pad is not going to be used by GPIO OS driver. If GPIO is configured to generate SCI/SMI/NMI then this setting must be used for interrupts to work
GpioHostOwnGpio | Set HOST ownership to GPIO Driver mode. Use this setting only if GPIO pad should be controlled by GPIO OS Driver. GPIO OS Driver will be able to control the pad if appropriate entry in ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)

Definition at line 146 of file GpioConfig.h.

◆ GPIO_INT_CONFIG

enum GPIO_INT_CONFIG

GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled.

GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in EDS for details on this settings. Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge to describe an interrupt e.g. GpioIntApic | GpioIntLevel If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. Not all GPIO are capable of generating an SMI or NMI interrupt. When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this interrupt cannot be shared and its IRQn number is not configurable. Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). This type of GPIO Driver interrupt doesn't have any additional routing setting required to be set by BIOS. Interrupt is handled by GPIO OS Driver.

Enumerator
GpioIntDefault | Leave value of interrupt routing unmodified.
GpioIntDis | Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
GpioIntNmi | Enable NMI interrupt only.
GpioIntSmi | Enable SMI interrupt only.
GpioIntSci | Enable SCI interrupt only.
GpioIntApic | Enable IOxAPIC interrupt only.
GpioIntLevel | Set interrupt as level triggered.
GpioIntEdge | Set interrupt as edge triggered (type of edge depends on input inversion)
GpioIntLvlEdgDis | Disable interrupt trigger.
GpioIntBothEdge | Set interrupt as both edge triggered.

Definition at line 207 of file GpioConfig.h.

◆ GPIO_LOCK_CONFIG

enum GPIO_LOCK_CONFIG

GPIO LockConfiguration Set GPIO configuration lock and output state lock.

GpioLockPadConfig and GpioLockOutputState can be OR'ed. Lock settings reset is in Powergood domain. Care must be taken when using this setting as fields it locks may be reset by a different signal and can be controllable by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides functions which allow to unlock a GPIO pad.

Enumerator
GpioLockDefault | Leave lock setting unmodified.
GpioPadConfigLock | Lock Pad Configuration.
GpioOutputStateLock | Lock GPIO pad output value.

Definition at line 329 of file GpioConfig.h.

◆ GPIO_OTHER_CONFIG

enum GPIO_OTHER_CONFIG

Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings:

  • RX raw override to '1' - allows to override input value to '1' This setting is applicable only if in input mode (both in GPIO and native usage). The override takes place at the internal pad state directly from buffer and before the RXINV.
Enumerator
GpioRxRaw1Default | Use default input override value.
GpioRxRaw1Dis | Don't override input.
GpioRxRaw1En | Override input to '1'.

Definition at line 346 of file GpioConfig.h.

◆ GPIO_OUTPUT_STATE

enum GPIO_OUTPUT_STATE

GPIO Output State This field is relevant only if output is enabled.

Enumerator
GpioOutDefault | Leave output value unmodified.
GpioOutLow | Set output to low.
GpioOutHigh | Set output to high.

Definition at line 181 of file GpioConfig.h.

◆ GPIO_PAD_MODE

enum GPIO_PAD_MODE

GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.

If GPIO is set to one of NativeX modes then following settings are not applicable and can be skipped:

  • Interrupt related settings
  • Host Software Ownership
  • Output/Input enabling/disabling
  • Output lock

Definition at line 132 of file GpioConfig.h.

◆ GPIO_RESET_CONFIG

enum GPIO_RESET_CONFIG

GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings.

Refer to EDS for settings that are controllable by PadRstCfg.

Enumerator
GpioResetDefault

Leave value of pad reset unmodified.

GpioResetPwrGood

Deprecated settings.

Maintained only for compatibility. GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")

GpioResetDeep

Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")

GpioResetNormal

GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )

GpioResetResume

GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )

GpioResumeReset

New GPIO reset configuration options.

Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad setting will reset on:

  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
GpioHostDeepReset

Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:

  • Warm/Cold/Global reset
  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
GpioPlatformReset

Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:

  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition
  • G3
GpioDswReset

Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings will reset on:

  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition

Definition at line 229 of file GpioConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GpioConfig.h Source File

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  • Include
GpioConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for GpioConfig structure used by GPIO library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GPIO_CONFIG_H_
36 #define _GPIO_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 ///
41 /// For any GpioPad usage in code use GPIO_PAD type
42 ///
43 typedef UINT32 GPIO_PAD;
44
45
46 ///
47 /// For any GpioGroup usage in code use GPIO_GROUP type
48 ///
49 typedef UINT32 GPIO_GROUP;
50
51 /**
52 GPIO configuration structure used for pin programming.
53 Structure contains fields that can be used to configure pad.
54 **/
55 typedef struct {
56 /**
57 Pad Mode
58 Pad can be set as GPIO or one of its native functions.
59 When in native mode setting Direction (except Inversion), OutputState,
60 InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
61 Refer to definition of GPIO_PAD_MODE.
62 Refer to EDS for each native mode according to the pad.
63 **/
64 UINT32 PadMode : 5;
65 /**
66 Host Software Pad Ownership
67 Set pad to ACPI mode or GPIO Driver Mode.
68 Refer to definition of GPIO_HOSTSW_OWN.
69 **/
70 UINT32 HostSoftPadOwn : 2;
71 /**
72 GPIO Direction
73 Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
74 Refer to definition of GPIO_DIRECTION for supported settings.
75 **/
76 UINT32 Direction : 6;
77 /**
78 Output State
79 Set Pad output value.
80 Refer to definition of GPIO_OUTPUT_STATE for supported settings.
81 This setting takes place when output is enabled.
82 **/
83 UINT32 OutputState : 2;
84 /**
85 GPIO Interrupt Configuration
86 Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
87 This setting is applicable only if GPIO is in GpioMode with input enabled.
88 Refer to definition of GPIO_INT_CONFIG for supported settings.
89 **/
90 UINT32 InterruptConfig : 9;
91 /**
92 GPIO Power Configuration.
93 This setting controls Pad Reset Configuration.
94 Refer to definition of GPIO_RESET_CONFIG for supported settings.
95 **/
96 UINT32 PowerConfig : 8;
97 /**
98 GPIO Electrical Configuration
99 This setting controls pads termination and voltage tolerance.
100 Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
101 **/
102 UINT32 ElectricalConfig : 9;
103 /**
104 GPIO Lock Configuration
105 This setting controls pads lock.
106 Refer to definition of GPIO_LOCK_CONFIG for supported settings.
107 **/
108 UINT32 LockConfig : 4;
109 /**
110 Additional GPIO configuration
111 Refer to definition of GPIO_OTHER_CONFIG for supported settings.
112 **/
113 UINT32 OtherSettings : 2;
114 UINT32 RsvdBits : 17; ///< Reserved bits for future extension
115 } GPIO_CONFIG;
116
117
118 typedef enum {
119 GpioHardwareDefault = 0x0 ///< Leave setting unmodified
120 } GPIO_HARDWARE_DEFAULT;
121
122 /**
123 GPIO Pad Mode
124 Refer to GPIO documentation on native functions available for certain pad.
125 If GPIO is set to one of NativeX modes then following settings are not applicable
126 and can be skipped:
127 - Interrupt related settings
128 - Host Software Ownership
129 - Output/Input enabling/disabling
130 - Output lock
131 **/
132 typedef enum {
133 GpioPadModeGpio = 0x1,
134 GpioPadModeNative1 = 0x3,
135 GpioPadModeNative2 = 0x5,
136 GpioPadModeNative3 = 0x7,
137 GpioPadModeNative4 = 0x9
138 } GPIO_PAD_MODE;
139
140 /**
141 Host Software Pad Ownership modes
142 This setting affects GPIO interrupt status registers. Depending on chosen ownership
143 some GPIO Interrupt status register get updated and other masked.
144 Please refer to EDS for HOSTSW_OWN register description.
145 **/
146 typedef enum {
147 GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
148 /**
149 Set HOST ownership to ACPI.
150 Use this setting if pad is not going to be used by GPIO OS driver.
151 If GPIO is configured to generate SCI/SMI/NMI then this setting must be
152 used for interrupts to work
153 **/
154 GpioHostOwnAcpi = 0x1,
155 /**
156 Set HOST ownership to GPIO Driver mode.
157 Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
158 GPIO OS Driver will be able to control the pad if appropriate entry in
159 ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
160 **/
161 GpioHostOwnGpio = 0x3
162 } GPIO_HOSTSW_OWN;
163
164 ///
165 /// GPIO Direction
166 ///
167 typedef enum {
168 GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
169 GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
170 GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
171 GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
172 GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
173 GpioDirOut = 0x5, ///< Set pad for output only
174 GpioDirNone = 0x7 ///< Disable both output and input
175 } GPIO_DIRECTION;
176
177 /**
178 GPIO Output State
179 This field is relevant only if output is enabled
180 **/
181 typedef enum {
182 GpioOutDefault = 0x0, ///< Leave output value unmodified
183 GpioOutLow = 0x1, ///< Set output to low
184 GpioOutHigh = 0x3 ///< Set output to high
185 } GPIO_OUTPUT_STATE;
186
187 /**
188 GPIO interrupt configuration
189 This setting is applicable only if pad is in GPIO mode and has input enabled.
190 GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
191 and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
192 EDS for details on this settings.
193 Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
194 to describe an interrupt e.g. GpioIntApic | GpioIntLevel
195 If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
196 If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
197 Not all GPIO are capable of generating an SMI or NMI interrupt.
198 When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
199 interrupt cannot be shared and its IRQn number is not configurable.
200 Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
201 If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
202 exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
203 This type of GPIO Driver interrupt doesn't have any additional routing setting
204 required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
205 **/
206
207 typedef enum {
208 GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
209 GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
210 GpioIntNmi = 0x3, ///< Enable NMI interrupt only
211 GpioIntSmi = 0x5, ///< Enable SMI interrupt only
212 GpioIntSci = 0x9, ///< Enable SCI interrupt only
213 GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
214 GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
215 GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
216 GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
217 GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
218 } GPIO_INT_CONFIG;
219
220 #define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
221 #define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
222
223 /**
224 GPIO Power Configuration
225 GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
226 be used to reset certain GPIO settings.
227 Refer to EDS for settings that are controllable by PadRstCfg.
228 **/
229 typedef enum {
230
231
232 GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
233 ///
234 /// Deprecated settings. Maintained only for compatibility.
235 ///
236 GpioResetPwrGood = 0x09, ///< GPP: RSMRST; GPD: DSW_PWROK; (PadRstCfg = 00b = "Powergood")
237 GpioResetDeep = 0x0B, ///< Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
238 GpioResetNormal = 0x0D, ///< GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
239 GpioResetResume = 0x0F, ///< GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
240
241 ///
242 /// New GPIO reset configuration options
243 ///
244 /**
245 Resume Reset (RSMRST)
246 GPP: PadRstCfg = 00b = "Powergood"
247 GPD: PadRstCfg = 11b = "Resume Reset"
248 Pad setting will reset on:
249 - DeepSx transition
250 - G3
251 Pad settings will not reset on:
252 - S3/S4/S5 transition
253 - Warm/Cold/Global reset
254 **/
255 GpioResumeReset = 0x01,
256 /**
257 Host Deep Reset
258 PadRstCfg = 01b = "Deep GPIO Reset"
259 Pad settings will reset on:
260 - Warm/Cold/Global reset
261 - DeepSx transition
262 - G3
263 Pad settings will not reset on:
264 - S3/S4/S5 transition
265 **/
266 GpioHostDeepReset = 0x03,
267 /**
268 Platform Reset (PLTRST)
269 PadRstCfg = 10b = "GPIO Reset"
270 Pad settings will reset on:
271 - S3/S4/S5 transition
272 - Warm/Cold/Global reset
273 - DeepSx transition
274 - G3
275 **/
276 GpioPlatformReset = 0x05,
277 /**
278 Deep Sleep Well Reset (DSW_PWROK)
279 GPP: not applicable
280 GPD: PadRstCfg = 00b = "Powergood"
281 Pad settings will reset on:
282 - G3
283 Pad settings will not reset on:
284 - S3/S4/S5 transition
285 - Warm/Cold/Global reset
286 - DeepSx transition
287 **/
288 GpioDswReset = 0x07
289 } GPIO_RESET_CONFIG;
290
291 /**
292 GPIO Electrical Configuration
293 Set GPIO termination and Pad Tolerance (applicable only for some pads)
294 Field from GpioTermNone to GpioTermNative can be OR'ed with GpioTolerance1v8.
295 **/
296 typedef enum {
297 GpioTermDefault = 0x0, ///< Leave termination setting unmodified
298 GpioTermNone = 0x1, ///< none
299 GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
300 GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
301 GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
302 GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
303 GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
304 GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
305 GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
306 /**
307 Native function controls pads termination
308 This setting is applicable only to some native modes.
309 Please check EDS to determine which native functionality
310 can control pads termination
311 **/
312 GpioTermNative = 0x1F,
313 GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance
314 GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance
315 } GPIO_ELECTRICAL_CONFIG;
316
317 #define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
318 #define B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting
319
320 /**
321 GPIO LockConfiguration
322 Set GPIO configuration lock and output state lock.
323 GpioLockPadConfig and GpioLockOutputState can be OR'ed.
324 Lock settings reset is in Powergood domain. Care must be taken when using this setting
325 as fields it locks may be reset by a different signal and can be controllable
326 by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
327 functions which allow to unlock a GPIO pad.
328 **/
329 typedef enum {
330 GpioLockDefault = 0x0, ///< Leave lock setting unmodified
331 GpioPadConfigLock = 0x3, ///< Lock Pad Configuration
332 GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value
333 } GPIO_LOCK_CONFIG;
334
335 #define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
336 #define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0x5 ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
337
338 /**
339 Other GPIO Configuration
340 GPIO_OTHER_CONFIG is used for less often settings and for future extensions
341 Supported settings:
342 - RX raw override to '1' - allows to override input value to '1'
343 This setting is applicable only if in input mode (both in GPIO and native usage).
344 The override takes place at the internal pad state directly from buffer and before the RXINV.
345 **/
346 typedef enum {
347 GpioRxRaw1Default = 0x0, ///< Use default input override value
348 GpioRxRaw1Dis = 0x1, ///< Don't override input
349 GpioRxRaw1En = 0x3 ///< Override input to '1'
350 } GPIO_OTHER_CONFIG;
351
352 #define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
353
354 #pragma pack(pop)
355
356 #endif //_GPIO_CONFIG_H_
GpioTermWpu5K
@ GpioTermWpu5K
5kOhm weak pull-up
Definition: GpioConfig.h:303
GpioOutDefault
@ GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:182
GPIO_RESET_CONFIG
GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0....
Definition: GpioConfig.h:229
GpioRxRaw1Default
@ GpioRxRaw1Default
Use default input override value.
Definition: GpioConfig.h:347
GpioDirInInv
@ GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:172
GpioOutLow
@ GpioOutLow
Set output to low.
Definition: GpioConfig.h:183
GPIO_CONFIG::Direction
UINT32 Direction
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion...
Definition: GpioConfig.h:76
GpioResetResume
@ GpioResetResume
GPP: Reserved; GPD: RSMRST; (PadRstCfg = 11b = "Resume Reset" )
Definition: GpioConfig.h:239
GPIO_CONFIG::PadMode
UINT32 PadMode
Pad Mode Pad can be set as GPIO or one of its native functions.
Definition: GpioConfig.h:64
GPIO_CONFIG::OutputState
UINT32 OutputState
Output State Set Pad output value.
Definition: GpioConfig.h:83
GpioTermWpu1K
@ GpioTermWpu1K
1kOhm weak pull-up
Definition: GpioConfig.h:301
GPIO_CONFIG::PowerConfig
UINT32 PowerConfig
GPIO Power Configuration.
Definition: GpioConfig.h:96
GpioNoTolerance1v8
@ GpioNoTolerance1v8
Disable 1.8V pad tolerance.
Definition: GpioConfig.h:313
GPIO_CONFIG::LockConfig
UINT32 LockConfig
GPIO Lock Configuration This setting controls pads lock.
Definition: GpioConfig.h:108
GpioDirOut
@ GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:173
GpioIntEdge
@ GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:215
GpioResetPwrGood
@ GpioResetPwrGood
Deprecated settings.
Definition: GpioConfig.h:236
GpioTermWpu2K
@ GpioTermWpu2K
2kOhm weak pull-up
Definition: GpioConfig.h:302
GpioResetNormal
@ GpioResetNormal
GPIO Reset (PadRstCfg = 10b = "GPIO Reset" )
Definition: GpioConfig.h:238
GpioTermNative
@ GpioTermNative
Native function controls pads termination This setting is applicable only to some native modes.
Definition: GpioConfig.h:312
GpioDirDefault
@ GpioDirDefault
Leave pad direction setting unmodified.
Definition: GpioConfig.h:168
GpioTermWpu20K
@ GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:304
GpioTermWpd20K
@ GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:300
GpioDirIn
@ GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:171
GpioRxRaw1En
@ GpioRxRaw1En
Override input to '1'.
Definition: GpioConfig.h:349
GpioRxRaw1Dis
@ GpioRxRaw1Dis
Don't override input.
Definition: GpioConfig.h:348
GpioOutputStateLock
@ GpioOutputStateLock
Lock GPIO pad output value.
Definition: GpioConfig.h:332
GPIO_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits for future extension.
Definition: GpioConfig.h:114
GpioTermNone
@ GpioTermNone
none
Definition: GpioConfig.h:298
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:43
GPIO_OTHER_CONFIG
GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions ...
Definition: GpioConfig.h:346
GPIO_HARDWARE_DEFAULT
GPIO_HARDWARE_DEFAULT
Definition: GpioConfig.h:118
GpioIntApic
@ GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:213
GPIO_DIRECTION
GPIO_DIRECTION
GPIO Direction.
Definition: GpioConfig.h:167
GpioTermWpu1K2K
@ GpioTermWpu1K2K
1kOhm & 2kOhm weak pull-up
Definition: GpioConfig.h:305
GPIO_CONFIG::ElectricalConfig
UINT32 ElectricalConfig
GPIO Electrical Configuration This setting controls pads termination and voltage tolerance.
Definition: GpioConfig.h:102
GpioTermWpd5K
@ GpioTermWpd5K
5kOhm weak pull-down
Definition: GpioConfig.h:299
GpioIntDefault
@ GpioIntDefault
Leave value of interrupt routing unmodified.
Definition: GpioConfig.h:208
GPIO_CONFIG::InterruptConfig
UINT32 InterruptConfig
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
Definition: GpioConfig.h:90
GpioIntLevel
@ GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:214
GpioLockDefault
@ GpioLockDefault
Leave lock setting unmodified.
Definition: GpioConfig.h:330
GpioTermDefault
@ GpioTermDefault
Leave termination setting unmodified.
Definition: GpioConfig.h:297
GpioResumeReset
@ GpioResumeReset
New GPIO reset configuration options.
Definition: GpioConfig.h:255
GpioDswReset
@ GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:288
GpioIntSmi
@ GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:211
GPIO_LOCK_CONFIG
GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock.
Definition: GpioConfig.h:329
GpioIntDis
@ GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:209
GPIO_PAD_MODE
GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.
Definition: GpioConfig.h:132
GpioHostDeepReset
@ GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:266
GPIO_CONFIG::OtherSettings
UINT32 OtherSettings
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
Definition: GpioConfig.h:113
GpioResetDefault
@ GpioResetDefault
Leave value of pad reset unmodified.
Definition: GpioConfig.h:232
GpioIntNmi
@ GpioIntNmi
Enable NMI interrupt only.
Definition: GpioConfig.h:210
GpioIntSci
@ GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:212
GpioHostOwnDefault
@ GpioHostOwnDefault
Leave ownership value unmodified.
Definition: GpioConfig.h:147
GpioDirInOut
@ GpioDirInOut
Set pad for both output and input.
Definition: GpioConfig.h:169
GpioHardwareDefault
@ GpioHardwareDefault
Leave setting unmodified.
Definition: GpioConfig.h:119
GPIO_HOSTSW_OWN
GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.
Definition: GpioConfig.h:146
GPIO_INT_CONFIG
GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input ena...
Definition: GpioConfig.h:207
GpioPlatformReset
@ GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:276
GpioTolerance1v8
@ GpioTolerance1v8
Enable 1.8V pad tolerance.
Definition: GpioConfig.h:314
GPIO_OUTPUT_STATE
GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled.
Definition: GpioConfig.h:181
GpioPadConfigLock
@ GpioPadConfigLock
Lock Pad Configuration.
Definition: GpioConfig.h:331
GPIO_ELECTRICAL_CONFIG
GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Set GPIO termination and Pad Tolerance (applicable only for some pads) ...
Definition: GpioConfig.h:296
GpioOutHigh
@ GpioOutHigh
Set output to high.
Definition: GpioConfig.h:184
GpioIntBothEdge
@ GpioIntBothEdge
Set interrupt as both edge triggered.
Definition: GpioConfig.h:217
GpioHostOwnGpio
@ GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:161
GPIO_GROUP
UINT32 GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.
Definition: GpioConfig.h:49
GPIO_CONFIG::HostSoftPadOwn
UINT32 HostSoftPadOwn
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.
Definition: GpioConfig.h:70
GpioDirInInvOut
@ GpioDirInInvOut
Set pad for both output and input with inversion.
Definition: GpioConfig.h:170
GPIO_CONFIG
GPIO configuration structure used for pin programming.
Definition: GpioConfig.h:55
GpioDirNone
@ GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:174
GpioHostOwnAcpi
@ GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:154
GpioIntLvlEdgDis
@ GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:216
GpioResetDeep
@ GpioResetDeep
Deep GPIO Reset (PadRstCfg = 01b = "Deep GPIO Reset")
Definition: GpioConfig.h:237
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GpioSampleDef.h File Reference

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  • Include
GpioSampleDef.h File Reference

Copyright (c) 2015 - 2021, Intel Corporation. More...

#include <FsptUpd.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
Include dependency graph for GpioSampleDef.h:

Go to the source code of this file.

Detailed Description

Copyright (c) 2015 - 2021, Intel Corporation.

All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

This file is automatically generated. Please do NOT modify !!!

Definition in file GpioSampleDef.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GpioSampleDef.h Source File

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  • AlderLakeFspBinPkg
  • Include
GpioSampleDef.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
4
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31 **/
32
33 #ifndef __GPIOCONFIG_H__
34 #define __GPIOCONFIG_H__
35 #include <FsptUpd.h>
36 #include <FspmUpd.h>
37 #include <FspsUpd.h>
38
39 /*
40 SKL LP GPIO pins
41 Use below for functions from PCH GPIO Lib which
42 require GpioPad as argument. Encoding used here
43 has all information required by library functions
44 */
45 #define GPIO_SKL_LP_GPP_A0 0x02000000
46 #define GPIO_SKL_LP_GPP_A1 0x02000001
47 #define GPIO_SKL_LP_GPP_A2 0x02000002
48 #define GPIO_SKL_LP_GPP_A3 0x02000003
49 #define GPIO_SKL_LP_GPP_A4 0x02000004
50 #define GPIO_SKL_LP_GPP_A5 0x02000005
51 #define GPIO_SKL_LP_GPP_A6 0x02000006
52 #define GPIO_SKL_LP_GPP_A7 0x02000007
53 #define GPIO_SKL_LP_GPP_A8 0x02000008
54 #define GPIO_SKL_LP_GPP_A9 0x02000009
55 #define GPIO_SKL_LP_GPP_A10 0x0200000A
56 #define GPIO_SKL_LP_GPP_A11 0x0200000B
57 #define GPIO_SKL_LP_GPP_A12 0x0200000C
58 #define GPIO_SKL_LP_GPP_A13 0x0200000D
59 #define GPIO_SKL_LP_GPP_A14 0x0200000E
60 #define GPIO_SKL_LP_GPP_A15 0x0200000F
61 #define GPIO_SKL_LP_GPP_A16 0x02000010
62 #define GPIO_SKL_LP_GPP_A17 0x02000011
63 #define GPIO_SKL_LP_GPP_A18 0x02000012
64 #define GPIO_SKL_LP_GPP_A19 0x02000013
65 #define GPIO_SKL_LP_GPP_A20 0x02000014
66 #define GPIO_SKL_LP_GPP_A21 0x02000015
67 #define GPIO_SKL_LP_GPP_A22 0x02000016
68 #define GPIO_SKL_LP_GPP_A23 0x02000017
69 #define GPIO_SKL_LP_GPP_B0 0x02010000
70 #define GPIO_SKL_LP_GPP_B1 0x02010001
71 #define GPIO_SKL_LP_GPP_B2 0x02010002
72 #define GPIO_SKL_LP_GPP_B3 0x02010003
73 #define GPIO_SKL_LP_GPP_B4 0x02010004
74 #define GPIO_SKL_LP_GPP_B5 0x02010005
75 #define GPIO_SKL_LP_GPP_B6 0x02010006
76 #define GPIO_SKL_LP_GPP_B7 0x02010007
77 #define GPIO_SKL_LP_GPP_B8 0x02010008
78 #define GPIO_SKL_LP_GPP_B9 0x02010009
79 #define GPIO_SKL_LP_GPP_B10 0x0201000A
80 #define GPIO_SKL_LP_GPP_B11 0x0201000B
81 #define GPIO_SKL_LP_GPP_B12 0x0201000C
82 #define GPIO_SKL_LP_GPP_B13 0x0201000D
83 #define GPIO_SKL_LP_GPP_B14 0x0201000E
84 #define GPIO_SKL_LP_GPP_B15 0x0201000F
85 #define GPIO_SKL_LP_GPP_B16 0x02010010
86 #define GPIO_SKL_LP_GPP_B17 0x02010011
87 #define GPIO_SKL_LP_GPP_B18 0x02010012
88 #define GPIO_SKL_LP_GPP_B19 0x02010013
89 #define GPIO_SKL_LP_GPP_B20 0x02010014
90 #define GPIO_SKL_LP_GPP_B21 0x02010015
91 #define GPIO_SKL_LP_GPP_B22 0x02010016
92 #define GPIO_SKL_LP_GPP_B23 0x02010017
93 #define GPIO_SKL_LP_GPP_C0 0x02020000
94 #define GPIO_SKL_LP_GPP_C1 0x02020001
95 #define GPIO_SKL_LP_GPP_C2 0x02020002
96 #define GPIO_SKL_LP_GPP_C3 0x02020003
97 #define GPIO_SKL_LP_GPP_C4 0x02020004
98 #define GPIO_SKL_LP_GPP_C5 0x02020005
99 #define GPIO_SKL_LP_GPP_C6 0x02020006
100 #define GPIO_SKL_LP_GPP_C7 0x02020007
101 #define GPIO_SKL_LP_GPP_C8 0x02020008
102 #define GPIO_SKL_LP_GPP_C9 0x02020009
103 #define GPIO_SKL_LP_GPP_C10 0x0202000A
104 #define GPIO_SKL_LP_GPP_C11 0x0202000B
105 #define GPIO_SKL_LP_GPP_C12 0x0202000C
106 #define GPIO_SKL_LP_GPP_C13 0x0202000D
107 #define GPIO_SKL_LP_GPP_C14 0x0202000E
108 #define GPIO_SKL_LP_GPP_C15 0x0202000F
109 #define GPIO_SKL_LP_GPP_C16 0x02020010
110 #define GPIO_SKL_LP_GPP_C17 0x02020011
111 #define GPIO_SKL_LP_GPP_C18 0x02020012
112 #define GPIO_SKL_LP_GPP_C19 0x02020013
113 #define GPIO_SKL_LP_GPP_C20 0x02020014
114 #define GPIO_SKL_LP_GPP_C21 0x02020015
115 #define GPIO_SKL_LP_GPP_C22 0x02020016
116 #define GPIO_SKL_LP_GPP_C23 0x02020017
117 #define GPIO_SKL_LP_GPP_D0 0x02030000
118 #define GPIO_SKL_LP_GPP_D1 0x02030001
119 #define GPIO_SKL_LP_GPP_D2 0x02030002
120 #define GPIO_SKL_LP_GPP_D3 0x02030003
121 #define GPIO_SKL_LP_GPP_D4 0x02030004
122 #define GPIO_SKL_LP_GPP_D5 0x02030005
123 #define GPIO_SKL_LP_GPP_D6 0x02030006
124 #define GPIO_SKL_LP_GPP_D7 0x02030007
125 #define GPIO_SKL_LP_GPP_D8 0x02030008
126 #define GPIO_SKL_LP_GPP_D9 0x02030009
127 #define GPIO_SKL_LP_GPP_D10 0x0203000A
128 #define GPIO_SKL_LP_GPP_D11 0x0203000B
129 #define GPIO_SKL_LP_GPP_D12 0x0203000C
130 #define GPIO_SKL_LP_GPP_D13 0x0203000D
131 #define GPIO_SKL_LP_GPP_D14 0x0203000E
132 #define GPIO_SKL_LP_GPP_D15 0x0203000F
133 #define GPIO_SKL_LP_GPP_D16 0x02030010
134 #define GPIO_SKL_LP_GPP_D17 0x02030011
135 #define GPIO_SKL_LP_GPP_D18 0x02030012
136 #define GPIO_SKL_LP_GPP_D19 0x02030013
137 #define GPIO_SKL_LP_GPP_D20 0x02030014
138 #define GPIO_SKL_LP_GPP_D21 0x02030015
139 #define GPIO_SKL_LP_GPP_D22 0x02030016
140 #define GPIO_SKL_LP_GPP_D23 0x02030017
141 #define GPIO_SKL_LP_GPP_E0 0x02040000
142 #define GPIO_SKL_LP_GPP_E1 0x02040001
143 #define GPIO_SKL_LP_GPP_E2 0x02040002
144 #define GPIO_SKL_LP_GPP_E3 0x02040003
145 #define GPIO_SKL_LP_GPP_E4 0x02040004
146 #define GPIO_SKL_LP_GPP_E5 0x02040005
147 #define GPIO_SKL_LP_GPP_E6 0x02040006
148 #define GPIO_SKL_LP_GPP_E7 0x02040007
149 #define GPIO_SKL_LP_GPP_E8 0x02040008
150 #define GPIO_SKL_LP_GPP_E9 0x02040009
151 #define GPIO_SKL_LP_GPP_E10 0x0204000A
152 #define GPIO_SKL_LP_GPP_E11 0x0204000B
153 #define GPIO_SKL_LP_GPP_E12 0x0204000C
154 #define GPIO_SKL_LP_GPP_E13 0x0204000D
155 #define GPIO_SKL_LP_GPP_E14 0x0204000E
156 #define GPIO_SKL_LP_GPP_E15 0x0204000F
157 #define GPIO_SKL_LP_GPP_E16 0x02040010
158 #define GPIO_SKL_LP_GPP_E17 0x02040011
159 #define GPIO_SKL_LP_GPP_E18 0x02040012
160 #define GPIO_SKL_LP_GPP_E19 0x02040013
161 #define GPIO_SKL_LP_GPP_E20 0x02040014
162 #define GPIO_SKL_LP_GPP_E21 0x02040015
163 #define GPIO_SKL_LP_GPP_E22 0x02040016
164 #define GPIO_SKL_LP_GPP_E23 0x02040017
165 #define GPIO_SKL_LP_GPP_F0 0x02050000
166 #define GPIO_SKL_LP_GPP_F1 0x02050001
167 #define GPIO_SKL_LP_GPP_F2 0x02050002
168 #define GPIO_SKL_LP_GPP_F3 0x02050003
169 #define GPIO_SKL_LP_GPP_F4 0x02050004
170 #define GPIO_SKL_LP_GPP_F5 0x02050005
171 #define GPIO_SKL_LP_GPP_F6 0x02050006
172 #define GPIO_SKL_LP_GPP_F7 0x02050007
173 #define GPIO_SKL_LP_GPP_F8 0x02050008
174 #define GPIO_SKL_LP_GPP_F9 0x02050009
175 #define GPIO_SKL_LP_GPP_F10 0x0205000A
176 #define GPIO_SKL_LP_GPP_F11 0x0205000B
177 #define GPIO_SKL_LP_GPP_F12 0x0205000C
178 #define GPIO_SKL_LP_GPP_F13 0x0205000D
179 #define GPIO_SKL_LP_GPP_F14 0x0205000E
180 #define GPIO_SKL_LP_GPP_F15 0x0205000F
181 #define GPIO_SKL_LP_GPP_F16 0x02050010
182 #define GPIO_SKL_LP_GPP_F17 0x02050011
183 #define GPIO_SKL_LP_GPP_F18 0x02050012
184 #define GPIO_SKL_LP_GPP_F19 0x02050013
185 #define GPIO_SKL_LP_GPP_F20 0x02050014
186 #define GPIO_SKL_LP_GPP_F21 0x02050015
187 #define GPIO_SKL_LP_GPP_F22 0x02050016
188 #define GPIO_SKL_LP_GPP_F23 0x02050017
189 #define GPIO_SKL_LP_GPP_G0 0x02060000
190 #define GPIO_SKL_LP_GPP_G1 0x02060001
191 #define GPIO_SKL_LP_GPP_G2 0x02060002
192 #define GPIO_SKL_LP_GPP_G3 0x02060003
193 #define GPIO_SKL_LP_GPP_G4 0x02060004
194 #define GPIO_SKL_LP_GPP_G5 0x02060005
195 #define GPIO_SKL_LP_GPP_G6 0x02060006
196 #define GPIO_SKL_LP_GPP_G7 0x02060007
197 #define GPIO_SKL_LP_GPD0 0x02070000
198 #define GPIO_SKL_LP_GPD1 0x02070001
199 #define GPIO_SKL_LP_GPD2 0x02070002
200 #define GPIO_SKL_LP_GPD3 0x02070003
201 #define GPIO_SKL_LP_GPD4 0x02070004
202 #define GPIO_SKL_LP_GPD5 0x02070005
203 #define GPIO_SKL_LP_GPD6 0x02070006
204 #define GPIO_SKL_LP_GPD7 0x02070007
205 #define GPIO_SKL_LP_GPD8 0x02070008
206 #define GPIO_SKL_LP_GPD9 0x02070009
207 #define GPIO_SKL_LP_GPD10 0x0207000A
208 #define GPIO_SKL_LP_GPD11 0x0207000B
209
210 #define END_OF_GPIO_TABLE 0xFFFFFFFF
211
212 //
213 //AlderLake S GPIO PCIe SLOT RTD3 and PEG reset pins.
214 //
215 #define GPIO_VER4_S_GPP_E2 0x080E0002
216 #define GPIO_VER4_S_GPP_E3 0x080E0003
217 #define GPIO_VER4_S_GPP_F11 0x0810000B
218 #define GPIO_VER4_S_GPP_F12 0x0810000C
219 #define GPIO_VER4_S_GPP_F13 0x0810000D
220
221 //Sample GPIO Table
222
223 //
224 //AlderLake S Gpio table for assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase.
225 //
226 static GPIO_INIT_CONFIG mAdlSPcieRstPinGpioTable[] =
227 {
228 { GPIO_VER4_S_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PEG_1 RTD3 Reset
229 { GPIO_VER4_S_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PEG_2 RTD3 Reset Sinai DR0 (Rework)
230 { GPIO_VER4_S_GPP_F11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PCIe SLOT_1 RTD3 Reset MIPI60 (Rework)
231 { GPIO_VER4_S_GPP_F12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PCIe SLOT_2 RTD3 Reset MIPI60 (Rework)
232 { GPIO_VER4_S_GPP_F13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }},// PCIe SLOT_3 RTD3 Reset MIPI60 (Rework)
233 { 0x0 } // terminator
234 };
235
236 static GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =
237 {
238 //skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//H_RCIN_N
239 //skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD0_ESPI_IO0
240 //skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD1_ESPI_IO1
241 //skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD2_ESPI_IO2
242 //skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_AD3_ESPI_IO3
243 //skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//LPC_FRAME_ESPI_CS_N
244 //skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//INT_SERIRQ
245 //skip for eSPI function {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S0ix_R_N
246 {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_CLKRUN_N
247 //skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//LPC_CLK_ESPI_CLK
248 {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//PCH_CLK_PCI_TPM
249 {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//EC_HID_INTR
250 {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//M.2_WWAN_GNSS_UART_RST_N
251 {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SUS_PWR_ACK_R
252 //skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N
253 {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SUSACK_R_N
254 {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_SEL
255 {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_EN_N
256 {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0_SENSOR
257 {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1_SENSOR
258 {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2_SENSOR
259 {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHUB_IRQ
260 {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_N
261 {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//FPS_DRDY
262 {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID0
263 {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_VID1
264 {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALERTB
265 {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone}},//TCH_PAD_INTR_R_N
266 {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KILL_N
267 {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_BT_UART_WAKE_N
268 // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT1_N
269 // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_SLOT2_LAN_N
270 // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_SSD_SLOT3_N
271 // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WIGIG_N
272 // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_REQ_M.2_WLAN_N
273 {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT_PWR_GATEB
274 {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_S0_N
275 {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_N
276 {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_PWREN
277 {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_DFU
278 {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//M.2_WLAN_WIFI_WAKE_N
279 {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpd20K}},//TBT_CIO_PLUG_EVENT_N
280 {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWpu20K}},//PCH_SLOT1_WAKE_N
281 {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSPI1_CS_R1_N
282 {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_CLK_R1
283 {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MISO_R1
284 {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GSPI1_MOSI_R1
285 {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRETE_GNSS_RESET_N
286 {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK
287 {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DATA
288 {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_THRM_SNSR_ALERT_N
289 {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK
290 {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DATA
291 {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpd20K}},//M.2_WIGIG_WAKE_N
292 {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK
293 {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_DATA
294 {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RXD
295 {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_TXD
296 {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_RTS_N
297 {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART0_CTS_N
298 {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RXD
299 {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_TXD
300 {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_RTS_N
301 {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART1_ISH_UART1_CTS_N
302 {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SDA
303 {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C0_SCL
304 {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SDA
305 {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_I2C1_SCL
306 {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
307 {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
308 {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RTS_N
309 {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_CTS_N
310 {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CS_N
311 {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_CLK
312 {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MISO
313 {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_MOSI
314 {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLASH_STROBE
315 {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SDA
316 {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0_SCL
317 {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SDA
318 {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1_SCL
319 {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//HOME_BTN
320 {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SCREEN_LOCK_PCH
321 {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_UP_PCH
322 {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//VOL_DOWN_PCH
323 {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RXD_SML0B_DATA
324 {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_TXD_SML0B_CLK
325 {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_RTS_N
326 {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART0_CTS_SML0B_ALERT_N
327 {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_1
328 {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_1
329 {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK_0
330 {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_DATA_0
331 {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO2
332 {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCHPNL_IO3
333 {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK
334 {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//SPI_TPM_HDR_IRQ_N
335 {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD_PRSNT_N
336 {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//M.2_SSD_SATA2_PCIE3_DET_N
337 {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_DFU_N
338 {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_RESET
339 {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PHYSLP1_DIRECT_R
340 {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2_PHYSLP2_M.2SSD_R
341 {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA_LED_N
342 {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0_WP1_OTG_N
343 {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1_WP4_N
344 {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2_WP2_WP3_WP5_R_N
345 {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_IRQ
346 {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD_Q
347 {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD_Q
348 {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNone}},//SMC_EXTSMI_R_N
349 {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNone}},//SMC_RUNTIME_SCI_R_N
350 {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD
351 {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTRL_CLK
352 {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_CTRL_DATA
353 {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTRL_CLK
354 {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_CTRL_DATA
355 {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_CODEC_IRQ
356 {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PNL_RST_N
357 {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCLK
358 {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFRM
359 {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD
360 {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD
361 {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SDA
362 {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C2_SCL
363 {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SDA
364 {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C3_SCL
365 {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SDA
366 {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C4_SCL
367 {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SDA
368 {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTermNone}},//SERIALIO_I2C5_ISH_12C2_SCL
369 {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
370 {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
371 {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
372 {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
373 {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
374 {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
375 {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
376 {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
377 {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
378 {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
379 {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
380 {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone}},//PCH_M.2_WWAN_UIM_SIM_DET
381 {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD
382 {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0
383 {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1
384 {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2
385 {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3
386 {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB
387 {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK
388 {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP
389 {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N
390 {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R
391 {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},//LANWAKE_SMC_WAKE_SCI_N
392 {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_N
393 {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N
394 {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N
395 {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N
396 {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_INTRUDET_N
397 {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK
398 {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N
399 {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N
400 {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENABLE
401 {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of Table
402 };
403
404 #endif //_GPIO_CONFIG_H_
GpioOutDefault
@ GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:182
GpioDirInInv
@ GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:172
GpioOutLow
@ GpioOutLow
Set output to low.
Definition: GpioConfig.h:183
GpioDirOut
@ GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:173
GpioIntEdge
@ GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:215
GpioTermWpu20K
@ GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:304
GpioTermWpd20K
@ GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:300
GpioDirIn
@ GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:171
GpioTermNone
@ GpioTermNone
none
Definition: GpioConfig.h:298
GpioIntApic
@ GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:213
GpioIntDefault
@ GpioIntDefault
Leave value of interrupt routing unmodified.
Definition: GpioConfig.h:208
GpioIntLevel
@ GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:214
GpioResumeReset
@ GpioResumeReset
New GPIO reset configuration options.
Definition: GpioConfig.h:255
GpioDswReset
@ GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:288
GpioIntSmi
@ GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:211
GpioIntDis
@ GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:209
GpioHostDeepReset
@ GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:266
GpioIntSci
@ GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:212
GpioPlatformReset
@ GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:276
GpioTolerance1v8
@ GpioTolerance1v8
Enable 1.8V pad tolerance.
Definition: GpioConfig.h:314
GpioOutHigh
@ GpioOutHigh
Set output to high.
Definition: GpioConfig.h:184
GpioHostOwnGpio
@ GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:161
GpioDirNone
@ GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:174
GpioHostOwnAcpi
@ GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:154
GpioIntLvlEdgDis
@ GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:216
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GraphicsConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
  • Gen12
Classes
GraphicsConfig.h File Reference

Policy definition for Internal Graphics Config Block. More...

Go to the source code of this file.

Classes

struct | DDI_CONFIGURATION
This structure configures the Native GPIOs for DDI port per VBT settings. More...
struct | GRAPHICS_PEI_PREMEM_CONFIG
This Configuration block is to configure GT related PreMem data/variables. More...
struct | GRAPHICS_PEI_CONFIG
This configuration block is to configure IGD related variables used in PostMem PEI. More...
struct | GRAPHICS_DXE_CONFIG
This configuration block is to configure IGD related variables used in DXE. More...

Detailed Description

Policy definition for Internal Graphics Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GraphicsConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: GraphicsConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
  • Gen12
GraphicsConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition for Internal Graphics Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GRAPHICS_CONFIG_H_
36 #define _GRAPHICS_CONFIG_H_
37 #pragma pack(push, 1)
38
39 #define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 7
40 #define GRAPHICS_PEI_CONFIG_REVISION 8
41 #define GRAPHICS_DXE_CONFIG_REVISION 2
42
43 #define DDI_DEVICE_NUMBER 4
44 #define MAX_BCLM_ENTRIES 20
45
46
47 //
48 // DDI defines
49 //
50 typedef enum {
51 DdiDisable = 0x00,
52 DdiDdcEnable = 0x01,
53 } DDI_DDC_TBT_VAL;
54
55 typedef enum {
56 DdiHpdDisable = 0x00,
57 DdiHpdEnable = 0x01,
58 } DDI_HPD_VAL;
59
60 typedef enum {
61 DdiPortDisabled = 0x00,
62 DdiPortEdp = 0x01,
63 DdiPortMipiDsi = 0x02,
64 } DDI_PORT_SETTINGS;
65
66 /**
67 This structure configures the Native GPIOs for DDI port per VBT settings.
68 **/
69 typedef struct {
70 UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, <b>DdiPortEdp - Set DdiPortA to eDP</b>, DdiPortMipiDsi - Set DdiPortA to MIPI DSI
71 UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, <b>DdiPortEdp - Set DdiPortB to eDP</b>, DdiPortMipiDsi - Set DdiPortB to MIPI DSI
72 UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
73 UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, <b>DdiHpdEnable - Enable HPD</b>
74 UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
75 UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
76 UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
77 UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
78 UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
79 UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
80 UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, <b>DdiDdcEnable - Enable DDC </b>
81 UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
82 UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
83 UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
84 UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
85 UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
86 } DDI_CONFIGURATION;
87
88 /**
89 This Configuration block is to configure GT related PreMem data/variables.\n
90 <b>Revision 1</b>:
91 - Initial version.
92 <b>Revision 2</b>:
93 - Added DfdRestoreEnable.
94 <b>Revision 3</b>:
95 - Added DdiConfiguration.
96 <b>Revision 4</b>:
97 - Added GmAdr64 and made GmAdr obselete
98 <b>Revision 5</b>:
99 - Added DeltaT12PowerCycleDelay
100 <b>Revision 6</b>:
101 - Added DisplayAudioLink
102 <b>Revision 7</b>:
103 - Added OemT12DelayOverride
104 **/
105 typedef struct {
106 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
107 /**
108 Offset 28
109 Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
110 When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX
111 **/
112 UINT8 PrimaryDisplay;
113 /**
114 Offset 29
115 Intel Gfx Support. It controls enabling/disabling iGfx device.
116 When AUTO mode selected, iGFX will be turned off when external graphics detected.
117 If FALSE, all other polices can be ignored.
118 <b>2 = AUTO</b>;
119 0 = FALSE;
120 1 = TRUE.
121 **/
122 UINT8 InternalGraphics;
123 /**
124 Offset 30
125 Pre-allocated memory for iGFX\n
126 0 = 0MB,1 or 247 = 32MB,\n
127 2 = 64MB,\n
128 240 = 4MB, 241 = 8MB,\n
129 242 = 12MB, 243 = 16MB,\n
130 244 = 20MB, 245 = 24MB,\n
131 246 = 28MB, 248 = 36MB,\n
132 249 = 40MB, 250 = 44MB,\n
133 251 = 48MB, 252 = 52MB,\n
134 253 = 56MB,<b> 254 = 60MB</b>,\n
135 <b>Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation</b>
136 **/
137 UINT16 IgdDvmt50PreAlloc;
138 UINT8 PanelPowerEnable; ///< Offset 32 :<b>(Test)</b> Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, <b>1=TRUE</b>
139 UINT8 ApertureSize; ///< Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
140 UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support On/Off: <b>0=FALSE</b>, 1=TRUE
141 UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region size: <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
142 UINT8 DismSize; ///< Offset 36 :DiSM Size for 2LM Sku: <b>0=0GB</b>, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB
143 UINT8 DfdRestoreEnable; ///< Offset 37 :(Deprecated) Display memory map programming for DFD Restore <b>0- Disable</b>, 1- Enable
144 UINT16 GttSize; ///< Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
145 /**
146 Offset 40
147 Temp Address of System Agent GTTMMADR: Default is <b>0xAF000000</b>
148 **/
149 UINT32 GttMmAdr;
150 UINT32 GmAdr; ///< Offset 44 Obsolete not to be used, use GmAdr64
151 DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configuration, need to match with VBT settings.
152
153 UINT8 GtClosEnable; ///< Offset 50 Gt ClOS
154 UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 bytes of alignment
155 /**
156 Offset 58
157 Temp Address of System Agent GMADR: Default is <b>0xB0000000</b>
158 **/
159 UINT64 GmAdr64;
160 UINT16 DeltaT12PowerCycleDelay; ///< Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, <b>0xFFFF - Auto calculate to max 500 ms<\b>
161 UINT8 DisplayAudioLink; ///< Offset 68 Enable/Disable Display Audio Links in Pre-OS.<b>0- Disable</b>, 1- Enable
162 UINT8 OemT12DelayOverride; ///< Offset 69 :Oem T12 Delay Override <b> Disable<\b>,Enable-Enable T12 Time.
163 UINT8 Rsvd2[4]; ///< Offset 70 Reserved for 4 bytes of alignment
164 } GRAPHICS_PEI_PREMEM_CONFIG;
165
166 /**
167 This configuration block is to configure IGD related variables used in PostMem PEI.
168 If Intel Gfx Device is not supported, all policies can be ignored.
169 <b>Revision 1</b>:
170 - Initial version.
171 <b>Revision 2</b>:
172 - Removed DfdRestoreEnable.
173 <b>Revision 3</b>:
174 - Removed DdiConfiguration.
175 <b>Revision 4</b>:
176 - Added new CdClock frequency
177 <b>Revision 5</b>:
178 - Added GT Chicket bits
179 <b>Revision 6</b>:
180 - Added LogoPixelHeight and LogoPixelWidth
181 <b>Revision 7</b>:
182 - Added SkipFspGop
183 <b>Revision 8</b>:
184 - Added VerticalResolution and HorizontalResolution
185
186 **/
187 typedef struct {
188 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
189 UINT8 RenderStandby; ///< Offset 28 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
190 UINT8 PmSupport; ///< Offset 29 :<b>(Test)</b> Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
191 /**
192 Offset 30
193 CdClock Frequency select\n
194 <b>0xFF = Auto. Max CdClock freq based on Reference Clk</b> \n
195 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
196
197 **/
198 UINT16 CdClock;
199 UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
200 UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
201 UINT16 GtFreqMax; ///< Offset 34 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
202 UINT8 DisableTurboGt; ///< Offset 36 : This policy is used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
203 UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD clock initialization. <b>0- Disable</b>, 1- Enable
204 UINT8 RC1pFreqEnable; ///< Offset 38 : This policy is used to enable/disable RC1p Frequency. <b>0- Disable</b>, 1- Enable
205 UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
206 VOID* LogoPtr; ///< Offset 40 Address of Intel Gfx PEIM Logo to be displayed
207 UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM Logo Size
208 VOID* GraphicsConfigPtr; ///< Offset 48 Address of the Graphics Configuration Table
209 VOID* BltBufferAddress; ///< Offset 52 Address of Blt buffer for PEIM Logo use
210 UINT32 BltBufferSize; ///< Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
211 UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
212 UINT8 SkipFspGop; ///< Offset 61 This policy is used to skip PEIM GOP in FSP.<b>0- Use FSP provided GOP driver</b>, 1- Skip FSP provided GOP driver
213 UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4 bytes alignment
214 UINT32 LogoPixelHeight; ///< Offset 64 Address of LogoPixelHeight for PEIM Logo use
215 UINT32 LogoPixelWidth; ///< Offset 68 Address of LogoPixelWidth for PEIM Logo use
216 UINT32 VerticalResolution; ///< Offset 72 Address of VerticalResolution for PEIM Logo use
217 UINT32 HorizontalResolution; ///< Offset 76 Address of HorizontalResolution for PEIM Logo use
218 } GRAPHICS_PEI_CONFIG;
219
220 /**
221 This configuration block is to configure IGD related variables used in DXE.
222 If Intel Gfx Device is not supported or disabled, all policies will be ignored.
223 The data elements should be initialized by a Platform Module.\n
224 <b>Revision 1</b>:
225 - Initial version.
226 <b>Revision 2</b>:
227 - Removed IgdDvmtMemSize.
228 **/
229 typedef struct {
230 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
231 UINT32 Size; ///< Offset 28 - 31: This field gives the size of the GOP VBT Data buffer
232 EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field points to the GOP VBT data buffer
233 UINT8 PlatformConfig; ///< Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable for All SKUs)
234 UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor Enable: <b>0=Disable</b>, 2=Enable
235 UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
236 UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2
237 UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
238 CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code
239 /**
240 Offset 80: IGD Panel Type CMOS option\n
241 <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1\n
242 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
243 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS
244 **/
245 UINT8 IgdPanelType;
246 UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling: <b>0=AUTO</b>, 1=OFF, 6=Force scaling
247 UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
248 UINT8 IgdDvmtMemSize; ///< Offset 83: @deprecated IGD DVMT Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
249 UINT8 GfxTurboIMON; ///< Offset 84: IMON Current Value: 14=Minimal, <b>31=Maximum</b>
250 UINT8 Reserved[3]; ///< Offset 85: Reserved for DWORD alignment.
251 UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.
252 } GRAPHICS_DXE_CONFIG;
253 #pragma pack(pop)
254
255 #endif // _GRAPHICS_CONFIG_H_
GRAPHICS_PEI_CONFIG::DisableTurboGt
UINT8 DisableTurboGt
Offset 36 : This policy is used to enable/disable DisableTurboGt 0- Disable, 1- Enable.
Definition: GraphicsConfig.h:202
DDI_CONFIGURATION::DdiPortCHpd
UINT8 DdiPortCHpd
The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:74
GRAPHICS_DXE_CONFIG::BacklightControlSupport
UINT8 BacklightControlSupport
Offset 42: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
Definition: GraphicsConfig.h:235
DDI_CONFIGURATION::DdiPort2Hpd
UINT8 DdiPort2Hpd
The HPD setting of DDI Port 1, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:76
GRAPHICS_PEI_PREMEM_CONFIG
This Configuration block is to configure GT related PreMem data/variables.
Definition: GraphicsConfig.h:105
GRAPHICS_PEI_PREMEM_CONFIG::GttSize
UINT16 GttSize
Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, 3=8MB
Definition: GraphicsConfig.h:144
GRAPHICS_PEI_CONFIG::BltBufferSize
UINT32 BltBufferSize
Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI...
Definition: GraphicsConfig.h:210
GRAPHICS_PEI_CONFIG::PavpEnable
UINT8 PavpEnable
Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, 1=TRUE
Definition: GraphicsConfig.h:205
GRAPHICS_DXE_CONFIG::VbtAddress
EFI_PHYSICAL_ADDRESS VbtAddress
Offset 32 - 39: This field points to the GOP VBT data buffer.
Definition: GraphicsConfig.h:232
DDI_CONFIGURATION::DdiPort1Ddc
UINT8 DdiPort1Ddc
The DDC setting of DDI Port C, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:82
GRAPHICS_PEI_PREMEM_CONFIG::DisplayAudioLink
UINT8 DisplayAudioLink
Offset 68 Enable/Disable Display Audio Links in Pre-OS.0- Disable, 1- Enable.
Definition: GraphicsConfig.h:161
DDI_CONFIGURATION::DdiPort3Hpd
UINT8 DdiPort3Hpd
The HPD setting of DDI Port 2, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:77
GRAPHICS_DXE_CONFIG::IgdBootType
UINT8 IgdBootType
Offset 43: IGD Boot Type CMOS option: 0=Default, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3,...
Definition: GraphicsConfig.h:236
GRAPHICS_PEI_CONFIG::LogoPtr
VOID * LogoPtr
Offset 40 Address of Intel Gfx PEIM Logo to be displayed.
Definition: GraphicsConfig.h:206
GRAPHICS_DXE_CONFIG::IgdPanelScaling
UINT8 IgdPanelScaling
Offset 81: IGD Panel Scaling: 0=AUTO, 1=OFF, 6=Force scaling.
Definition: GraphicsConfig.h:246
GRAPHICS_PEI_PREMEM_CONFIG::GtClosEnable
UINT8 GtClosEnable
Offset 50 Gt ClOS.
Definition: GraphicsConfig.h:153
GRAPHICS_PEI_PREMEM_CONFIG::PsmiRegionSize
UINT8 PsmiRegionSize
Offset 35 :Psmi region size: 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1056MB.
Definition: GraphicsConfig.h:141
GRAPHICS_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27: Config Block Header.
Definition: GraphicsConfig.h:230
GRAPHICS_PEI_CONFIG::PmSupport
UINT8 PmSupport
Offset 29 :(Test) Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, 1=TRUE
Definition: GraphicsConfig.h:190
GRAPHICS_DXE_CONFIG::IgdBlcConfig
UINT8 IgdBlcConfig
Offset 82: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
Definition: GraphicsConfig.h:247
GRAPHICS_PEI_PREMEM_CONFIG::DeltaT12PowerCycleDelay
UINT16 DeltaT12PowerCycleDelay
Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, 0xFFFF - Auto calculate t...
Definition: GraphicsConfig.h:160
GRAPHICS_PEI_CONFIG::ProgramGtChickenBits
UINT8 ProgramGtChickenBits
Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
Definition: GraphicsConfig.h:211
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
GRAPHICS_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: GraphicsConfig.h:106
GRAPHICS_PEI_PREMEM_CONFIG::PrimaryDisplay
UINT8 PrimaryDisplay
Offset 28 Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH,...
Definition: GraphicsConfig.h:112
GRAPHICS_DXE_CONFIG
This configuration block is to configure IGD related variables used in DXE.
Definition: GraphicsConfig.h:229
GRAPHICS_PEI_PREMEM_CONFIG::DismSize
UINT8 DismSize
Offset 36 :DiSM Size for 2LM Sku: 0=0GB, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB,...
Definition: GraphicsConfig.h:142
GRAPHICS_PEI_CONFIG::CdynmaxClampEnable
UINT8 CdynmaxClampEnable
Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable,...
Definition: GraphicsConfig.h:200
GRAPHICS_DXE_CONFIG::IgdPanelType
UINT8 IgdPanelType
Offset 80: IGD Panel Type CMOS option 0=Default, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS,...
Definition: GraphicsConfig.h:245
GRAPHICS_PEI_PREMEM_CONFIG::IgdDvmt50PreAlloc
UINT16 IgdDvmt50PreAlloc
Offset 30 Pre-allocated memory for iGFX 0 = 0MB,1 or 247 = 32MB, 2 = 64MB, 240 = 4MB,...
Definition: GraphicsConfig.h:137
DDI_CONFIGURATION::DdiPortAHpd
UINT8 DdiPortAHpd
The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is...
Definition: GraphicsConfig.h:72
GRAPHICS_DXE_CONFIG::GfxTurboIMON
UINT8 GfxTurboIMON
Offset 84: IMON Current Value: 14=Minimal, 31=Maximum
Definition: GraphicsConfig.h:249
GRAPHICS_PEI_PREMEM_CONFIG::GmAdr
UINT32 GmAdr
Offset 44 Obsolete not to be used, use GmAdr64.
Definition: GraphicsConfig.h:150
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GRAPHICS_DXE_CONFIG::AlsEnable
UINT8 AlsEnable
Offset 41: Ambient Light Sensor Enable: 0=Disable, 2=Enable.
Definition: GraphicsConfig.h:234
GRAPHICS_PEI_PREMEM_CONFIG::DdiConfiguration
DDI_CONFIGURATION DdiConfiguration
Offset 48 DDI configuration, need to match with VBT settings.
Definition: GraphicsConfig.h:151
DDI_CONFIGURATION::DdiPortBConfig
UINT8 DdiPortBConfig
The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is...
Definition: GraphicsConfig.h:71
GRAPHICS_PEI_PREMEM_CONFIG::GmAdr64
UINT64 GmAdr64
Offset 58 Temp Address of System Agent GMADR: Default is 0xB0000000
Definition: GraphicsConfig.h:159
GRAPHICS_PEI_CONFIG::RenderStandby
UINT8 RenderStandby
Offset 28 :(Test) This field is used to enable or disable RC6 (Render Standby): 0=FALSE,...
Definition: GraphicsConfig.h:189
DDI_CONFIGURATION::DdiPort3Ddc
UINT8 DdiPort3Ddc
The DDC setting of DDI Port 2, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:84
GRAPHICS_DXE_CONFIG::IgdDvmtMemSize
UINT8 IgdDvmtMemSize
Offset 83:
Definition: GraphicsConfig.h:248
DDI_CONFIGURATION::DdiPortADdc
UINT8 DdiPortADdc
The HPD setting of DDI Port 4, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:79
DDI_CONFIGURATION::DdiPortCDdc
UINT8 DdiPortCDdc
The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:81
DDI_CONFIGURATION
This structure configures the Native GPIOs for DDI port per VBT settings.
Definition: GraphicsConfig.h:69
GRAPHICS_PEI_CONFIG
This configuration block is to configure IGD related variables used in PostMem PEI.
Definition: GraphicsConfig.h:187
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
GRAPHICS_PEI_CONFIG::RC1pFreqEnable
UINT8 RC1pFreqEnable
Offset 38 : This policy is used to enable/disable RC1p Frequency. 0- Disable, 1- Enable.
Definition: GraphicsConfig.h:204
GRAPHICS_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: GraphicsConfig.h:188
DDI_CONFIGURATION::DdiPort1Hpd
UINT8 DdiPort1Hpd
The HPD setting of DDI Port C, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:75
GRAPHICS_PEI_CONFIG::LogoPixelWidth
UINT32 LogoPixelWidth
Offset 68 Address of LogoPixelWidth for PEIM Logo use.
Definition: GraphicsConfig.h:215
GRAPHICS_PEI_CONFIG::CdClock
UINT16 CdClock
Offset 30 CdClock Frequency select 0xFF = Auto.
Definition: GraphicsConfig.h:198
GRAPHICS_PEI_PREMEM_CONFIG::GttMmAdr
UINT32 GttMmAdr
Offset 40 Temp Address of System Agent GTTMMADR: Default is 0xAF000000
Definition: GraphicsConfig.h:149
GRAPHICS_PEI_PREMEM_CONFIG::OemT12DelayOverride
UINT8 OemT12DelayOverride
Offset 69 :Oem T12 Delay Override Disable< >,Enable-Enable T12 Time.
Definition: GraphicsConfig.h:162
GRAPHICS_PEI_PREMEM_CONFIG::InternalGraphics
UINT8 InternalGraphics
Offset 29 Intel Gfx Support.
Definition: GraphicsConfig.h:122
GRAPHICS_DXE_CONFIG::Size
UINT32 Size
Offset 28 - 31: This field gives the size of the GOP VBT Data buffer.
Definition: GraphicsConfig.h:231
GRAPHICS_PEI_PREMEM_CONFIG::GtPsmiSupport
UINT8 GtPsmiSupport
Offset 34 :PSMI support On/Off: 0=FALSE, 1=TRUE.
Definition: GraphicsConfig.h:140
GRAPHICS_DXE_CONFIG::PlatformConfig
UINT8 PlatformConfig
Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for UL...
Definition: GraphicsConfig.h:233
GRAPHICS_PEI_CONFIG::GtFreqMax
UINT16 GtFreqMax
Offset 34 : (Test) Max GT frequency limited by user in multiples of 50MHz: Default value which indica...
Definition: GraphicsConfig.h:201
DDI_CONFIGURATION::DdiPortBHpd
UINT8 DdiPortBHpd
The HPD setting of DDI Port A, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:73
DDI_CONFIGURATION::DdiPort4Hpd
UINT8 DdiPort4Hpd
The HPD setting of DDI Port 3, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:78
GRAPHICS_PEI_CONFIG::SkipCdClockInit
UINT8 SkipCdClockInit
Offset 37 : SKip full CD clock initialization. 0- Disable, 1- Enable.
Definition: GraphicsConfig.h:203
GRAPHICS_PEI_PREMEM_CONFIG::PanelPowerEnable
UINT8 PanelPowerEnable
Offset 32 :(Test) Control for enabling/disabling VDD force bit (Required only for early enabling of e...
Definition: GraphicsConfig.h:138
GRAPHICS_PEI_CONFIG::HorizontalResolution
UINT32 HorizontalResolution
Offset 76 Address of HorizontalResolution for PEIM Logo use.
Definition: GraphicsConfig.h:217
DDI_CONFIGURATION::DdiPort4Ddc
UINT8 DdiPort4Ddc
The DDC setting of DDI Port 3, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:85
GRAPHICS_PEI_CONFIG::LogoPixelHeight
UINT32 LogoPixelHeight
Offset 64 Address of LogoPixelHeight for PEIM Logo use.
Definition: GraphicsConfig.h:214
GRAPHICS_PEI_CONFIG::GraphicsConfigPtr
VOID * GraphicsConfigPtr
Offset 48 Address of the Graphics Configuration Table.
Definition: GraphicsConfig.h:208
GRAPHICS_PEI_CONFIG::SkipFspGop
UINT8 SkipFspGop
Offset 61 This policy is used to skip PEIM GOP in FSP.0- Use FSP provided GOP driver,...
Definition: GraphicsConfig.h:212
GRAPHICS_PEI_PREMEM_CONFIG::ApertureSize
UINT8 ApertureSize
Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB,...
Definition: GraphicsConfig.h:139
GRAPHICS_PEI_PREMEM_CONFIG::DfdRestoreEnable
UINT8 DfdRestoreEnable
Offset 37 :(Deprecated) Display memory map programming for DFD Restore 0- Disable,...
Definition: GraphicsConfig.h:143
GRAPHICS_PEI_CONFIG::BltBufferAddress
VOID * BltBufferAddress
Offset 52 Address of Blt buffer for PEIM Logo use.
Definition: GraphicsConfig.h:209
GRAPHICS_PEI_CONFIG::LogoSize
UINT32 LogoSize
Offset 44 Intel Gfx PEIM Logo Size.
Definition: GraphicsConfig.h:207
GRAPHICS_DXE_CONFIG::IuerStatusVal
UINT32 IuerStatusVal
Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (...
Definition: GraphicsConfig.h:237
GRAPHICS_PEI_CONFIG::VerticalResolution
UINT32 VerticalResolution
Offset 72 Address of VerticalResolution for PEIM Logo use.
Definition: GraphicsConfig.h:216
GRAPHICS_PEI_CONFIG::PeiGraphicsPeimInit
UINT8 PeiGraphicsPeimInit
Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable.
Definition: GraphicsConfig.h:199
DDI_CONFIGURATION::DdiPortBDdc
UINT8 DdiPortBDdc
The DDC setting of DDI Port A, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:80
DDI_CONFIGURATION::DdiPort2Ddc
UINT8 DdiPort2Ddc
The DDC setting of DDI Port 1, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:83
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HdAudioConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
Classes | Macros
HdAudioConfig.h File Reference

HDAUDIO policy. More...

#include <ConfigBlock.h>
#include <PchLimits.h>
Include dependency graph for HdAudioConfig.h:

Go to the source code of this file.

Classes

struct | HDA_VERB_TABLE_HEADER
Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands. More...
struct | HDA_LINK_HDA
HD Audio Link Policies. More...
struct | HDA_LINK_DMIC
HD Audio DMIC Interface Policies. More...
struct | HDA_LINK_SSP
HD Audio SSP Interface Policies. More...
struct | HDA_LINK_SNDW
HD Audio SNDW Interface Policies. More...
struct | HDAUDIO_CONFIG
This structure contains the policies which are related to HD Audio device (cAVS). More...
struct | HDAUDIO_PREMEM_CONFIG
This structure contains the premem policies which are related to HD Audio device (cAVS). More...
struct | HDAUDIO_DXE_CONFIG
This structure contains the DXE policies which are related to HD Audio device (cAVS). More...

Macros

#define | HDAUDIO_VERB_TABLE_VIDDID(Vid, Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
#define | HDAUDIO_VERB_TABLE_INIT(Vid, Did, Rid, Sdi, ...)
Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically.

Detailed Description

HDAUDIO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HdAudioConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HdAudioConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
HdAudioConfig.h
Go to the documentation of this file.
1 /** @file
2 HDAUDIO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HDAUDIO_CONFIG_H_
36 #define _HDAUDIO_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <PchLimits.h>
40
41 #define HDAUDIO_PREMEM_CONFIG_REVISION 4
42 #define HDAUDIO_CONFIG_REVISION 1
43 #define HDAUDIO_DXE_CONFIG_REVISION 2
44
45 extern EFI_GUID gHdAudioPreMemConfigGuid;
46 extern EFI_GUID gHdAudioConfigGuid;
47 extern EFI_GUID gHdAudioDxeConfigGuid;
48
49 #pragma pack (push,1)
50
51 ///
52 /// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
53 ///
54
55 #define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
56 #define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))
57 #define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))
58
59 ///
60 /// Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically
61 ///
62 #define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \
63 { \
64 { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \
65 { __VA_ARGS__ } \
66 }
67
68 /**
69 Azalia verb table header
70 Every verb table should contain this defined header and followed by azalia verb commands.
71 **/
72 typedef struct {
73 UINT16 VendorId; ///< Codec Vendor ID
74 UINT16 DeviceId; ///< Codec Device ID
75 UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
76 UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
77 UINT16 DataDwords; ///< Number of data DWORDs following the header.
78 } HDA_VERB_TABLE_HEADER;
79
80 #ifdef _MSC_VER
81 //
82 // Disable "zero-sized array in struct/union" extension warning.
83 // Used for neater verb table definitions.
84 //
85 #pragma warning (push)
86 #pragma warning (disable: 4200)
87 #endif
88 typedef struct {
89 HDA_VERB_TABLE_HEADER Header;
90 UINT32 Data[];
91 } HDAUDIO_VERB_TABLE;
92 #ifdef _MSC_VER
93 #pragma warning (pop)
94 #endif
95
96 typedef struct {
97 UINT32 ClkA; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKA_*
98 UINT32 ClkB; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKB_*
99 UINT32 Data; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_DATA_*
100 } HDA_DMIC_PIN_MUX;
101
102 /**
103 HD Audio Link Policies
104 **/
105 typedef struct {
106 UINT32 Enable : 1; ///< HDA interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
107 UINT32 RsvdBits0 : 31;
108 UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable. When enabled related SDI pins will be switched to appropriate native mode: <b>0: Disable</b>; 1: Enable
109 UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for SDI enable table.
110 } HDA_LINK_HDA;
111
112 /**
113 HD Audio DMIC Interface Policies
114 **/
115 typedef struct {
116 UINT32 Enable : 1; ///< HDA DMIC interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
117 UINT32 DmicClockSelect : 2; ///< DMIC link clock select: <b>0: Both</b>, 1: ClkA, 2: ClkB; default is "Both"
118 UINT32 RsvdBits0 : 29;
119 HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration.
120 } HDA_LINK_DMIC;
121
122 /**
123 HD Audio SSP Interface Policies
124 **/
125 typedef struct {
126 UINT32 Enable : 1; ///< HDA SSP interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
127 UINT32 RsvdBits0 : 31;
128 } HDA_LINK_SSP;
129
130 /**
131 HD Audio SNDW Interface Policies
132 **/
133 typedef struct {
134 UINT32 Enable : 1; ///< HDA SNDW interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
135 UINT32 RsvdBits0 : 31;
136 } HDA_LINK_SNDW;
137
138
139 /**
140 This structure contains the policies which are related to HD Audio device (cAVS).
141
142 <b>Revision 1:</b>
143 - Inital version.
144
145 **/
146 typedef struct {
147 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
148 UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
149 UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake initiated by a codec in Sx (eg by modem codec), <b>0: Disable</b>; 1: Enable
150 UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz
151 UINT32 RsvdBits0 : 26; ///< Reserved bits 0
152 /**
153 Number of the verb table entry defined in VerbTablePtr.
154 Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
155 **/
156 UINT8 VerbTableEntryNum;
157 UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
158 /**
159 Pointer to a verb table array.
160 This pointer points to 32bits address, and is only eligible and consumed in post mem phase.
161 Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
162 The prototype of this is:
163 HDAUDIO_VERB_TABLE **VerbTablePtr;
164 **/
165 UINT32 VerbTablePtr;
166 } HDAUDIO_CONFIG;
167
168 /**
169 This structure contains the premem policies which are related to HD Audio device (cAVS).
170
171 <b>Revision 1:</b>
172 - Inital version.
173 <b>Revision 2:</b>
174 - Add DmicClockSelect
175 <b>Revision 3:</b>
176 - Add AudioFpgaSocVer
177 <b>Revision 4:</b>
178 - Remove AudioFpgaSocVer
179 **/
180 typedef struct {
181 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
182 UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enablement: 0: Disable, <b>1: Enable</b>
183 UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
184 UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1
185 /**
186 Universal Audio Architecture compliance for DSP enabled system:
187 <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
188 1: UAA Compliant (HDA Inbox driver or SST driver supported)
189 **/
190 UINT32 DspUaaCompliance : 1;
191 UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
192 UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, <b>3: 8T</b>, 4: 16T
193 UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI, not enumerable
194 UINT32 PowerGatingSupported : 1; ///< Power Gating supported: <b>0: Not supported</b>, 1: Supported
195 UINT32 RsvdBits : 19; ///< Reserved bits 0
196
197 /**
198 Audio Link Mode configuration bitmask.
199 Allows to configure enablement of the following interfaces: HDA-Link, DMIC, SSP, SoundWire.
200 **/
201
202 HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0: Disable; <b>1: Enable</b>.
203 /**
204 DMIC link enablement: 0: Disable; <b>1: Enable</b>.
205 DMIC0 LKF: Muxed with SNDW2/SNDW4.
206 **/
207 HDA_LINK_DMIC AudioLinkDmic [PCH_MAX_HDA_DMIC_LINK_NUM];
208 /**
209 I2S/SSP link enablement: <b>0: Disable</b>; 1: Enable.
210 SSP0/1 LKF: Muxed with HDA.
211 @note Since the I2S/SSP2 pin set contains pads which are also used for CNVi purpose, enabling AudioLinkSsp2
212 is exclusive with CNVi is present.
213 **/
214 HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM];
215 /**
216 SoundWire link enablement: <b>0: Disable</b>; 1: Enable.
217 SNDW2 LKF: Muxed with DMIC0/DMIC1.
218 SNDW3 LKF: Muxed with DMIC1.
219 SNDW4 LKF: Muxed with DMIC0.
220 **/
221 HDA_LINK_SNDW AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM];
222
223 UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>600</b>.
224 UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4
225 UINT32 SubSystemIds; ///< Value for SID and SVID. If its set to 0 then default value is used.
226 } HDAUDIO_PREMEM_CONFIG;
227
228 typedef struct {
229 UINT32 AutonomousClockStop : 1; ///< SoundWire1 link autonomous clock stop capability: <b>0: Disable</b>; 1: Enable
230 UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data on active interval select 0: 6 clock periods; <b>1: 7 clock periods</b>; 2: 8 clock periods; 3: 11 clock periods
231 UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data on delay select 0: 2 clock periods; <b>1: 3 clock periods</b>
232 UINT32 RsvdBits1 : 28; ///< Reserved bits 1
233 } HDAUDIO_SNDW_CONFIG;
234
235 /**
236 This structure contains the DXE policies which are related to HD Audio device (cAVS).
237 <b>Revision 1:</b>
238 - Inital version.
239 <b>Revision 2:</b>
240 - Add IoControlEnabled
241 <b>Revision 3:</b>
242 - Remove IoControlEnabled
243 **/
244 typedef struct {
245 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
246 /**
247 SNDW configuration for exposed via SNDW ACPI tables:
248 **/
249 HDAUDIO_SNDW_CONFIG SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM];
250 /**
251 Bitmask of supported DSP features:
252 [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP
253 [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation
254 Default is <b>zero</b>.
255 **/
256 UINT32 DspFeatureMask;
257 } HDAUDIO_DXE_CONFIG;
258
259 #pragma pack (pop)
260
261 #endif // _HDAUDIO_CONFIG_H_
HDA_VERB_TABLE_HEADER::SdiNum
UINT8 SdiNum
SDI number, 0xFF matches any SDI.
Definition: HdAudioConfig.h:76
HDA_LINK_SSP
HD Audio SSP Interface Policies.
Definition: HdAudioConfig.h:125
ConfigBlock.h
Header file for Config Block Lib implementation.
HDAUDIO_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits 0.
Definition: HdAudioConfig.h:195
HDA_LINK_SNDW::Enable
UINT32 Enable
HDA SNDW interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: ...
Definition: HdAudioConfig.h:134
HDA_LINK_DMIC::PinMux
HDA_DMIC_PIN_MUX PinMux
Pin mux configuration.
Definition: HdAudioConfig.h:119
HDAUDIO_CONFIG::VerbTableEntryNum
UINT8 VerbTableEntryNum
Number of the verb table entry defined in VerbTablePtr.
Definition: HdAudioConfig.h:156
HDA_LINK_HDA
HD Audio Link Policies.
Definition: HdAudioConfig.h:105
HDAUDIO_DXE_CONFIG
This structure contains the DXE policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:244
HDA_VERB_TABLE_HEADER::VendorId
UINT16 VendorId
Codec Vendor ID.
Definition: HdAudioConfig.h:73
HDAUDIO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:147
HDAUDIO_PREMEM_CONFIG::DspUaaCompliance
UINT32 DspUaaCompliance
Universal Audio Architecture compliance for DSP enabled system: 0: Not-UAA Compliant (Intel SST drive...
Definition: HdAudioConfig.h:190
HDA_LINK_DMIC::Enable
UINT32 Enable
HDA DMIC interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: ...
Definition: HdAudioConfig.h:116
HDAUDIO_PREMEM_CONFIG::Enable
UINT32 Enable
Intel HD Audio (Azalia) enablement: 0: Disable, 1: Enable
Definition: HdAudioConfig.h:182
HDA_VERB_TABLE_HEADER::RevisionId
UINT8 RevisionId
Revision ID of the codec. 0xFF matches any revision.
Definition: HdAudioConfig.h:75
HDAUDIO_CONFIG::HdAudioLinkFrequency
UINT32 HdAudioLinkFrequency
HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz.
Definition: HdAudioConfig.h:150
HDAUDIO_PREMEM_CONFIG::SubSystemIds
UINT32 SubSystemIds
Value for SID and SVID. If its set to 0 then default value is used.
Definition: HdAudioConfig.h:225
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HDAUDIO_PREMEM_CONFIG::AudioLinkHda
HDA_LINK_HDA AudioLinkHda
Audio Link Mode configuration bitmask.
Definition: HdAudioConfig.h:202
HDAUDIO_PREMEM_CONFIG::IDispLinkFrequency
UINT32 IDispLinkFrequency
iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz
Definition: HdAudioConfig.h:191
HDA_LINK_DMIC
HD Audio DMIC Interface Policies.
Definition: HdAudioConfig.h:115
HDAUDIO_PREMEM_CONFIG::DspEnable
UINT32 DspEnable
DSP enablement: 0: Disable; 1: Enable
Definition: HdAudioConfig.h:183
HDAUDIO_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits 0.
Definition: HdAudioConfig.h:151
HDAUDIO_PREMEM_CONFIG::PowerGatingSupported
UINT32 PowerGatingSupported
Power Gating supported: 0: Not supported, 1: Supported.
Definition: HdAudioConfig.h:194
HDA_LINK_DMIC::DmicClockSelect
UINT32 DmicClockSelect
DMIC link clock select: 0: Both, 1: ClkA, 2: ClkB; default is "Both".
Definition: HdAudioConfig.h:117
HDAUDIO_PREMEM_CONFIG::VcType
UINT32 VcType
Virtual Channel Type Select: 0: VC0, 1: VC1.
Definition: HdAudioConfig.h:184
HDAUDIO_CONFIG::VerbTablePtr
UINT32 VerbTablePtr
Pointer to a verb table array.
Definition: HdAudioConfig.h:165
HDA_VERB_TABLE_HEADER::DeviceId
UINT16 DeviceId
Codec Device ID.
Definition: HdAudioConfig.h:74
HDAUDIO_CONFIG::Pme
UINT32 Pme
Azalia wake-on-ring, 0: Disable; 1: Enable.
Definition: HdAudioConfig.h:148
HDAUDIO_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:181
HDAUDIO_CONFIG::CodecSxWakeCapability
UINT32 CodecSxWakeCapability
Capability to detect wake initiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Enable.
Definition: HdAudioConfig.h:149
HDAUDIO_PREMEM_CONFIG::ResetWaitTimer
UINT16 ResetWaitTimer
(Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
Definition: HdAudioConfig.h:223
HDA_LINK_SSP::Enable
UINT32 Enable
HDA SSP interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: E...
Definition: HdAudioConfig.h:126
HDAUDIO_DXE_CONFIG::DspFeatureMask
UINT32 DspFeatureMask
Bitmask of supported DSP features: [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - B...
Definition: HdAudioConfig.h:256
HDAUDIO_PREMEM_CONFIG::IDispCodecDisconnect
UINT32 IDispCodecDisconnect
iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI,...
Definition: HdAudioConfig.h:193
HDA_VERB_TABLE_HEADER::DataDwords
UINT16 DataDwords
Number of data DWORDs following the header.
Definition: HdAudioConfig.h:77
HDAUDIO_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:245
HDA_LINK_HDA::Enable
UINT32 Enable
HDA interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enabl...
Definition: HdAudioConfig.h:106
HDAUDIO_CONFIG
This structure contains the policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:146
HDAUDIO_PREMEM_CONFIG
This structure contains the premem policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:180
HDA_LINK_SNDW
HD Audio SNDW Interface Policies.
Definition: HdAudioConfig.h:133
HDAUDIO_PREMEM_CONFIG::IDispLinkTmode
UINT32 IDispLinkTmode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T
Definition: HdAudioConfig.h:192
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
HDA_VERB_TABLE_HEADER
Azalia verb table header Every verb table should contain this defined header and followed by azalia v...
Definition: HdAudioConfig.h:72
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HybridGraphicsConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
Classes | Enumerations
HybridGraphicsConfig.h File Reference

Hybrid Graphics policy definitions. More...

Go to the source code of this file.

Classes

struct | CPU_PCIE_GPIO_INFO
CPU PCIe GPIO Data Structure. More...
struct | CPU_PCIE_RTD3_GPIO
CPU PCIE RTD3 GPIO Data Structure. More...
struct | HYBRID_GRAPHICS_CONFIG
This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port. More...

Enumerations

enum GPIO_SUPPORT
GPIO Support.

Detailed Description

Hybrid Graphics policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HybridGraphicsConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HybridGraphicsConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
HybridGraphicsConfig.h
Go to the documentation of this file.
1 /** @file
2 Hybrid Graphics policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HYBRID_GRAPHICS_CONFIG_H_
36 #define _HYBRID_GRAPHICS_CONFIG_H_
37
38 #define HYBRID_GRAPHICS_CONFIG_REVISION 4
39
40 #pragma pack(push, 1)
41 ///
42 /// GPIO Support
43 ///
44 typedef enum {
45 NotSupported = 0,
46 PchGpio,
47 I2CGpio,
48 } GPIO_SUPPORT;
49
50 ///
51 /// CPU PCIe GPIO Data Structure
52 ///
53 typedef struct {
54 UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO
55 BOOLEAN Active; ///< Offset 1 0=Active Low; 1=Active High
56 UINT8 Rsvd0[2]; ///< Offset 2 Reserved
57 UINT32 GpioNo; ///< Offset 4 GPIO pad
58 } CPU_PCIE_GPIO_INFO;
59
60 /**
61 CPU PCIE RTD3 GPIO Data Structure
62 **/
63 typedef struct {
64 CPU_PCIE_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD RESET GPIO value and level information
65 CPU_PCIE_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe PWR Enable GPIO value and level information
66 UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number
67 UINT8 GpioSupport; ///< Offset 20 Depends on board design the GPIO configuration may be different: <b>0=Not Supported</b>, 1=PCH Based, 2=I2C based
68 UINT8 Rsvd0[3]; ///< Offset 21
69 } CPU_PCIE_RTD3_GPIO;
70
71 /**
72 This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port.
73 Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3.
74 <b>Revision 1</b>:
75 - Initial version.
76 <b>Revision 2</b>:
77 - Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics
78 <b>Revision 3</b>:
79 - Removed HgSlot Policy: As there is no selection between PEG or PCH Slot for Hybrid Graphics
80 <b>Revision 4</b>:
81 - Added HgSupport Policy: To support HG support on other PEG ports
82 **/
83 typedef struct {
84 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
85 CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio; ///< Offset 28 RTD3 GPIOs used for PCIe
86 UINT8 RootPortIndex; ///< Offset 52 Root Port Index number used for HG
87 UINT8 HgMode; ///< Offset 53 HgMode: <b>0=Disabled</b>, 1=HG Muxed, 2=HG Muxless, 3=PEG
88 UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graphics Subsystem ID: <b>2212</b>
89 UINT16 HgDelayAfterPwrEn; ///< Offset 56 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum, <b>300=300 microseconds</b>
90 UINT16 HgDelayAfterHoldReset; ///< Offset 58 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum, <b>100=100 microseconds</b>
91 CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio; ///< Offset 60 RTD3 GPIOs used for PCIe
92 CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio; ///< Offset 84 RTD3 GPIOs used for PCIe
93 CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio; ///< Offset 108 RTD3 GPIOs used for PCIe
94 UINT8 HgSupport; ///< Offset 132 HgSupport on specific port
95 UINT8 Rsvd0[3]; ///< Offset 133 Reserved bytes for future use
96 } HYBRID_GRAPHICS_CONFIG;
97 #pragma pack(pop)
98 #endif // _HYBRID_GRAPHICS_CONFIG_H_
HYBRID_GRAPHICS_CONFIG::CpuPcie1Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio
Offset 60 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:91
HYBRID_GRAPHICS_CONFIG
This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port.
Definition: HybridGraphicsConfig.h:83
HYBRID_GRAPHICS_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: HybridGraphicsConfig.h:84
HYBRID_GRAPHICS_CONFIG::HgSubSystemId
UINT16 HgSubSystemId
Offset 54 Hybrid Graphics Subsystem ID: 2212
Definition: HybridGraphicsConfig.h:88
HYBRID_GRAPHICS_CONFIG::HgDelayAfterHoldReset
UINT16 HgDelayAfterHoldReset
Offset 58 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum,...
Definition: HybridGraphicsConfig.h:90
HYBRID_GRAPHICS_CONFIG::HgMode
UINT8 HgMode
Offset 53 HgMode: 0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=PEG.
Definition: HybridGraphicsConfig.h:87
HYBRID_GRAPHICS_CONFIG::CpuPcie2Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio
Offset 84 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:92
CPU_PCIE_RTD3_GPIO::HoldRst
CPU_PCIE_GPIO_INFO HoldRst
Offset 0 This field contain PCIe HLD RESET GPIO value and level information.
Definition: HybridGraphicsConfig.h:64
CPU_PCIE_GPIO_INFO::Active
BOOLEAN Active
Offset 1 0=Active Low; 1=Active High.
Definition: HybridGraphicsConfig.h:55
CPU_PCIE_GPIO_INFO::ExpanderNo
UINT8 ExpanderNo
Offset 0 Expander No For I2C based GPIO.
Definition: HybridGraphicsConfig.h:54
CPU_PCIE_RTD3_GPIO::GpioSupport
UINT8 GpioSupport
Offset 20 Depends on board design the GPIO configuration may be different: 0=Not Supported,...
Definition: HybridGraphicsConfig.h:67
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HYBRID_GRAPHICS_CONFIG::HgSupport
UINT8 HgSupport
Offset 132 HgSupport on specific port.
Definition: HybridGraphicsConfig.h:94
CPU_PCIE_RTD3_GPIO::PwrEnable
CPU_PCIE_GPIO_INFO PwrEnable
Offset 8 This field contain PCIe PWR Enable GPIO value and level information.
Definition: HybridGraphicsConfig.h:65
HYBRID_GRAPHICS_CONFIG::CpuPcie0Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio
Offset 28 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:85
HYBRID_GRAPHICS_CONFIG::RootPortIndex
UINT8 RootPortIndex
Offset 52 Root Port Index number used for HG.
Definition: HybridGraphicsConfig.h:86
CPU_PCIE_GPIO_INFO
CPU PCIe GPIO Data Structure.
Definition: HybridGraphicsConfig.h:53
GPIO_SUPPORT
GPIO_SUPPORT
GPIO Support.
Definition: HybridGraphicsConfig.h:44
HYBRID_GRAPHICS_CONFIG::CpuPcie3Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio
Offset 108 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:93
CPU_PCIE_RTD3_GPIO
CPU PCIE RTD3 GPIO Data Structure.
Definition: HybridGraphicsConfig.h:63
CPU_PCIE_RTD3_GPIO::WakeGpioNo
UINT32 WakeGpioNo
Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number.
Definition: HybridGraphicsConfig.h:66
HYBRID_GRAPHICS_CONFIG::HgDelayAfterPwrEn
UINT16 HgDelayAfterPwrEn
Offset 56 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum,...
Definition: HybridGraphicsConfig.h:89
CPU_PCIE_GPIO_INFO::GpioNo
UINT32 GpioNo
Offset 4 GPIO pad.
Definition: HybridGraphicsConfig.h:57
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HybridStorageConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridStorage
Classes
HybridStorageConfig.h File Reference

Hybrid Storage policy. More...

#include <ConfigBlock.h>
Include dependency graph for HybridStorageConfig.h:

Go to the source code of this file.

Classes

struct HYBRID_STORAGE_CONFIG
The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device. More...

Detailed Description

Hybrid Storage policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HybridStorageConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HybridStorageConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridStorage
HybridStorageConfig.h
Go to the documentation of this file.
1 /** @file
2 Hybrid Storage policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HYBRID_STORAGE_CONFIG_H_
36 #define _HYBRID_STORAGE_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define HYBRID_STORAGE_CONFIG_REVISION 2
41
42 extern EFI_GUID gHybridStorageConfigGuid;
43
44 #pragma pack (push,1)
45
46 /**
47 The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device
48
49 <b>Revision 1</b>:
50 - Init version
51 <b>Revision 2</b>:
52 - Added support for cpu attached hybrid storage
53 **/
54 typedef struct {
55 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
56 /**
57 Hybrid Storage Mode
58 <b>0: Disable</b>, 1: Enable Dynamic Configuration
59 **/
60 UINT8 HybridStorageMode;
61 UINT8 CpuRootportUsedForHybridStorage;
62 UINT8 PchRootportUsedForCpuAttach;
63 UINT8 RsvdBytes[1];
64 } HYBRID_STORAGE_CONFIG;
65
66 #pragma pack (pop)
67
68 #endif // _HYBRID_STORAGE_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
HYBRID_STORAGE_CONFIG
The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device.
Definition: HybridStorageConfig.h:54
HYBRID_STORAGE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HybridStorageConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HYBRID_STORAGE_CONFIG::HybridStorageMode
UINT8 HybridStorageMode
Hybrid Storage Mode 0: Disable, 1: Enable Dynamic Configuration.
Definition: HybridStorageConfig.h:60
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IehConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
Classes
IehConfig.h File Reference

Integrated Error Handler policy. More...

#include <ConfigBlock.h>
Include dependency graph for IehConfig.h:

Go to the source code of this file.

Classes

struct IEH_CONFIG
The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler. More...

Detailed Description

Integrated Error Handler policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IehConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IehConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
IehConfig.h
Go to the documentation of this file.
1 /** @file
2 Integrated Error Handler policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _IEH_CONFIG_H_
37 #define _IEH_CONFIG_H_
38
39 #include <ConfigBlock.h>
40
41 #define IEH_MODE_BYPASS 0
42 #define IEH_MODE_ENABLE 1
43
44 #define IEH_CONFIG_REVISION 1
45 extern EFI_GUID gIehConfigGuid;
46
47 #pragma pack (push,1)
48
49 /**
50 The IEH_CONFIG block describes the expected configuration of the PCH
51 Integrated Error Handler.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
55 /**
56 IEH mode <b>0: Bypass Mode</b>; 1: Enable
57 **/
58 UINT32 Mode : 1;
59 UINT32 RsvdBits0 : 31; ///< Reserved bits
60 } IEH_CONFIG;
61
62 #pragma pack (pop)
63
64 #endif // _IEH_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
IEH_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: IehConfig.h:59
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
IEH_CONFIG
The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler.
Definition: IehConfig.h:53
IEH_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IehConfig.h:54
IEH_CONFIG::Mode
UINT32 Mode
IEH mode 0: Bypass Mode; 1: Enable.
Definition: IehConfig.h:58
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: InterruptConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Classes | Macros | Enumerations
InterruptConfig.h File Reference

Interrupt policy. More...

Go to the source code of this file.

Classes

struct | PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...
struct | PCH_INTERRUPT_CONFIG
The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. More...

Macros

#define | PCH_MAX_DEVICE_INTERRUPT_CONFIG 128
Number of all PCH devices.
#define | PCH_MAX_PXRC_CONFIG 8
Number of PXRC registers in ITSS.
#define | PCH_MAX_ITSS_IPC_REGS 4
Number of IPC registers in ITSS.
#define | PCH_MAX_ITSS_IRQ_NUM 120
Maximum number of IRQs.

Enumerations

enum PCH_INT_PIN

Detailed Description

Interrupt policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file InterruptConfig.h.

Enumeration Type Documentation

◆ PCH_INT_PIN

enum PCH_INT_PIN
Enumerator
PchNoInt

No Interrupt Pin.

Definition at line 46 of file InterruptConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: InterruptConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
InterruptConfig.h
Go to the documentation of this file.
1 /** @file
2 Interrupt policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _INTERRUPT_CONFIG_H_
36 #define _INTERRUPT_CONFIG_H_
37
38 #define PCH_INTERRUPT_CONFIG_REVISION 1
39 extern EFI_GUID gInterruptConfigGuid;
40
41 #pragma pack (push,1)
42
43 //
44 // --------------------- Interrupts Config ------------------------------
45 //
46 typedef enum {
47 PchNoInt, ///< No Interrupt Pin
48 PchIntA,
49 PchIntB,
50 PchIntC,
51 PchIntD
52 } PCH_INT_PIN;
53
54 ///
55 /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
56 ///
57 typedef struct {
58 UINT8 Device; ///< Device number
59 UINT8 Function; ///< Device function
60 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
61 UINT8 Irq; ///< IRQ to be set for device.
62 } PCH_DEVICE_INTERRUPT_CONFIG;
63
64 #define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all PCH devices
65 #define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
66 #define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC registers in ITSS
67 #define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of IRQs
68
69
70 ///
71 /// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
72 ///
73 typedef struct {
74 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
75 UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
76 UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
77 PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
78 UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
79 UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>.
80 UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>.
81 UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
82 } PCH_INTERRUPT_CONFIG;
83
84 #pragma pack (pop)
85
86 #endif // _INTERRUPT_CONFIG_H_
PCH_DEVICE_INTERRUPT_CONFIG::Function
UINT8 Function
Device function.
Definition: InterruptConfig.h:59
PCH_INTERRUPT_CONFIG::TcoIrqEnable
UINT8 TcoIrqEnable
Enable IRQ generation for TCO. 0: Disable; 1: Enable.
Definition: InterruptConfig.h:81
PCH_DEVICE_INTERRUPT_CONFIG::IntX
UINT8 IntX
Interrupt pin: INTA-INTD (see PCH_INT_PIN)
Definition: InterruptConfig.h:60
PCH_INTERRUPT_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: InterruptConfig.h:74
PCH_DEVICE_INTERRUPT_CONFIG::Irq
UINT8 Irq
IRQ to be set for device.
Definition: InterruptConfig.h:61
PCH_DEVICE_INTERRUPT_CONFIG::Device
UINT8 Device
Device number.
Definition: InterruptConfig.h:58
PCH_MAX_DEVICE_INTERRUPT_CONFIG
#define PCH_MAX_DEVICE_INTERRUPT_CONFIG
Number of all PCH devices.
Definition: InterruptConfig.h:64
PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
Definition: InterruptConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_INTERRUPT_CONFIG::NumOfDevIntConfig
UINT8 NumOfDevIntConfig
Number of entries in DevIntConfig table.
Definition: InterruptConfig.h:75
PCH_INT_PIN
PCH_INT_PIN
Definition: InterruptConfig.h:46
PCH_INTERRUPT_CONFIG::TcoIrqSelect
UINT8 TcoIrqSelect
Interrupt select for TCO. Default is 9.
Definition: InterruptConfig.h:80
PCH_INTERRUPT_CONFIG::GpioIrqRoute
UINT8 GpioIrqRoute
Interrupt routing for GPIO. Default is 14.
Definition: InterruptConfig.h:78
PchNoInt
@ PchNoInt
No Interrupt Pin.
Definition: InterruptConfig.h:47
PCH_INTERRUPT_CONFIG::SciIrqSelect
UINT8 SciIrqSelect
Interrupt select for SCI. Default is 9.
Definition: InterruptConfig.h:79
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
PCH_INTERRUPT_CONFIG
The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
Definition: InterruptConfig.h:73
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IoApicConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Classes
IoApicConfig.h File Reference

IoApic policy. More...

Go to the source code of this file.

Classes

struct PCH_IOAPIC_CONFIG
The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE. More...

Detailed Description

IoApic policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IoApicConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IoApicConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
IoApicConfig.h
Go to the documentation of this file.
1 /** @file
2 IoApic policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IOAPIC_CONFIG_H_
36 #define _IOAPIC_CONFIG_H_
37
38 #define PCH_IOAPIC_CONFIG_REVISION 1
39 extern EFI_GUID gIoApicConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH
45 IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
46 not TRUE. Bus:device:function fields will be programmed to the register
47 P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
48 As the Requester ID when initiating Interrupt Messages to the processor.
49 As the Completer ID when responding to the reads targeting the IOxAPI's
50 Memory-Mapped I/O registers.
51 This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
52 program this field to provide a unique Bus:Device:Function number for the
53 internal IOxAPIC.
54 The address resource range of IOAPIC must be reserved in E820 and ACPI as
55 system resource.
56 **/
57 typedef struct {
58 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
59 UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119
60 /**
61 Enable 8254 Static Clock Gating during early POST time. 0: Disable, <b>1: Enable</b>
62 Setting 8254CGE is required to support SLP_S0.
63 Enable this if 8254 timer is not used.
64 However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer.
65 Make sure it is disabled to support legacy OS using 8254 timer.
66 @note:
67 For some OS environment that it needs to set 8254CGE in late state it should
68 set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in SMM later.
69 This is also required during S3 resume.
70 To avoid SMI requirement in S3 reusme path, it can enable the Enable8254ClockGatingOnS3
71 and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_SAI.
72 **/
73 UINT32 Enable8254ClockGating : 1;
74 /**
75 Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, <b>1: Enable</b>
76 This is only applicable when Enable8254ClockGating is disabled.
77 If Enable8254ClockGating is enabled, RC will do the 8254 CGE programming on
78 S3 resume path as well.
79 **/
80 UINT32 Enable8254ClockGatingOnS3 : 1;
81 UINT32 RsvdBits1 : 29; ///< Reserved bits
82 UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is <b>0x02</b>.
83 UINT8 Rsvd0[3]; ///< Reserved bytes
84 } PCH_IOAPIC_CONFIG;
85
86 #pragma pack (pop)
87
88 #endif // _IOAPIC_CONFIG_H_
PCH_IOAPIC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IoApicConfig.h:58
PCH_IOAPIC_CONFIG::IoApicId
UINT8 IoApicId
This member determines IOAPIC ID. Default is 0x02.
Definition: IoApicConfig.h:82
PCH_IOAPIC_CONFIG::IoApicEntry24_119
UINT32 IoApicEntry24_119
0: Disable; 1: Enable IOAPIC Entry 24-119
Definition: IoApicConfig.h:59
PCH_IOAPIC_CONFIG::Enable8254ClockGating
UINT32 Enable8254ClockGating
Enable 8254 Static Clock Gating during early POST time.
Definition: IoApicConfig.h:73
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_IOAPIC_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: IoApicConfig.h:81
PCH_IOAPIC_CONFIG::Enable8254ClockGatingOnS3
UINT32 Enable8254ClockGatingOnS3
Enable 8254 Static Clock Gating on S3 resume path.
Definition: IoApicConfig.h:80
PCH_IOAPIC_CONFIG
The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC,...
Definition: IoApicConfig.h:57
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IpuPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
Classes
IpuPreMemConfig.h File Reference

IPU policy definitions. More...

#include <ConfigBlock.h>
Include dependency graph for IpuPreMemConfig.h:

Go to the source code of this file.

Classes

struct IPU_PREMEM_CONFIG
IPU PreMem configuration
Revision 1: More...

Detailed Description

IPU policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IpuPreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IpuPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
IpuPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 IPU policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IPU_CONFIG_PREMEM_H_
36 #define _IPU_CONFIG_PREMEM_H_
37
38 #pragma pack(push, 1)
39 #include <ConfigBlock.h>
40
41 #define IPU_PREMEM_CONFIG_REVISION 4
42
43 //
44 // GPIO native features pins data
45 //
46 #define GPIO_IMGUCLK_NUMBER_OF_PINS 6
47
48 //
49 // Maximum CSI (Camera Serial Interface) Port
50 //
51 #define MAX_CSI_PORT 8
52
53 // @todo file name will be changed to IpuConfig.h.
54
55 extern EFI_GUID gIpuPreMemConfigGuid;
56
57 /**
58 IPU PreMem configuration\n
59 <b>Revision 1</b>:
60 - Initial version.
61 <b>Revision 2</b>:
62 - Change Bit-wise to Byte-wise.
63 <b>Revision 3</b>:
64 - Add LaneUsed and Speed of each Port configuration for Mcd10 support.
65 <b>Revision 4</b>:
66 - Change GPIO_IMGUCLK_NUMBER_OF_PINS to 6
67 <b>Revision 5</b>:
68 - Deprecate IpuImrConfiguration.
69 **/
70 typedef struct {
71 CONFIG_BLOCK_HEADER Header; /// Config Block Header
72 /**
73 <b>(Test)</b> It enables the SA IPU Device if supported and not fused off.
74 If FALSE, all other policies in this config block will be ignored.
75 <b>1=TRUE</b>;
76 0=FALSE.
77 **/
78 UINT8 IpuEnable;
79 /**
80 Deprecate
81 **/
82 UINT8 IpuImrConfiguration;
83 /**
84 It enable the IMGU CLKOUT.
85 <b>TRUE</b>
86 FALSE
87 **/
88 UINT8 ImguClkOutEn[GPIO_IMGUCLK_NUMBER_OF_PINS];
89 UINT8 LaneUsed[MAX_CSI_PORT]; ///< Indicate laneUsed of each CSI port <b>0: Not configured</b>; 1: x1; 2:x2; 3:x3; 4:x4
90 UINT8 CsiSpeed[MAX_CSI_PORT]; ///< Indicate speed of each CSI port <b>0: Sensor default</b>; 1: <416Mbps; 2:<1.5Gbps; 3:<2Gbps; 4:<2.5Gbps; 5:<4Gbps; 6>4Gbps
91 } IPU_PREMEM_CONFIG;
92 #pragma pack(pop)
93
94 #endif // _IPU_PREMEM_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
IPU_PREMEM_CONFIG
IPU PreMem configuration Revision 1:
Definition: IpuPreMemConfig.h:70
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
IPU_PREMEM_CONFIG::IpuEnable
UINT8 IpuEnable
Config Block Header.
Definition: IpuPreMemConfig.h:78
IPU_PREMEM_CONFIG::IpuImrConfiguration
UINT8 IpuImrConfiguration
Deprecate.
Definition: IpuPreMemConfig.h:82
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IshConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
Classes
IshConfig.h File Reference

ISH policy. More...

Go to the source code of this file.

Classes

struct | ISH_GPIO_CONFIG
ISH GPIO settings. More...
struct | ISH_SPI_PIN_CONFIG
SPI signals settings. More...
struct | ISH_UART_PIN_CONFIG
UART signals settings. More...
struct | ISH_I2C_PIN_CONFIG
I2C signals settings. More...
struct | ISH_SPI
Struct contains GPIO pins assigned and signal settings of SPI. More...
struct | ISH_UART
Struct contains GPIO pins assigned and signal settings of UART. More...
struct | ISH_I2C
Struct contains GPIO pins assigned and signal settings of I2C. More...
struct | ISH_GP
Struct contains GPIO pins assigned and signal settings of GP. More...
struct | ISH_CONFIG
The ISH_CONFIG block describes Integrated Sensor Hub device. More...
struct | ISH_I3C_CONFIG
The ISH_I3C_CONFIG block describes I3C in ISH device. More...
struct | ISH_PREMEM_CONFIG
Premem Policy for Integrated Sensor Hub device. More...

Detailed Description

ISH policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IshConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: IshConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
IshConfig.h
Go to the documentation of this file.
1 /** @file
2 ISH policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ISH_CONFIG_H_
36 #define _ISH_CONFIG_H_
37
38 #define ISH_PREMEM_CONFIG_REVISION 1
39 #define ISH_CONFIG_REVISION 2
40 #define ISH_I3C_CONFIG_REVISION 1
41 extern EFI_GUID gIshPreMemConfigGuid;
42 extern EFI_GUID gIshConfigGuid;
43 extern EFI_GUID gIshI3cConfigGuid;
44
45 #pragma pack (push,1)
46
47 /**
48 ISH GPIO settings
49 **/
50 typedef struct {
51 /**
52 GPIO signals pin muxing settings. If signal can be enable only on a single pin
53 then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_* in GpioPins*.h
54 for supported settings on a given platform
55 **/
56 UINT32 PinMux; ///< GPIO Pin mux configuration. Refer to GPIO_*_MUXING_ISH_*x_MOSI_*
57 /**
58 GPIO Pads Internal Termination.
59 For more information please see Platform Design Guide.
60 Check GPIO_ELECTRICAL_CONFIG for reference
61 **/
62 UINT32 PadTermination;
63 } ISH_GPIO_CONFIG;
64
65 /**
66 SPI signals settings.
67 **/
68 typedef struct {
69 ISH_GPIO_CONFIG Mosi; ///< MOSI Pin configuration.
70 ISH_GPIO_CONFIG Miso; ///< MISO Pin configuration.
71 ISH_GPIO_CONFIG Clk; ///< CLK Pin configuration.
72 ISH_GPIO_CONFIG Cs[PCH_MAX_ISH_SPI_CS_PINS]; ///< CS Pin configuration.
73 } ISH_SPI_PIN_CONFIG;
74
75
76 /**
77 UART signals settings.
78 **/
79 typedef struct {
80 ISH_GPIO_CONFIG Rx; ///< RXD Pin configuration.
81 ISH_GPIO_CONFIG Tx; ///< TXD Pin configuration.
82 ISH_GPIO_CONFIG Rts; ///< RTS Pin configuration.
83 ISH_GPIO_CONFIG Cts; ///< CTS Pin configuration.
84 } ISH_UART_PIN_CONFIG;
85
86
87 /**
88 I2C signals settings.
89 **/
90 typedef struct {
91 ISH_GPIO_CONFIG Sda; ///< SDA Pin configuration.
92 ISH_GPIO_CONFIG Scl; ///< SCL Pin configuration.
93 } ISH_I2C_PIN_CONFIG;
94
95
96 /**
97 Struct contains GPIO pins assigned and signal settings of SPI
98 **/
99 typedef struct {
100 UINT8 Enable; ///< ISH SPI GPIO pins assigned: <b>0: False</b> 1: True
101 UINT8 CsEnable[PCH_MAX_ISH_SPI_CS_PINS]; ///< ISH SPI CS pins assigned: <b>0: False</b> 1: True
102 UINT16 RsvdField0; ///< Reserved field
103 ISH_SPI_PIN_CONFIG PinConfig;
104 } ISH_SPI;
105
106
107 /**
108 Struct contains GPIO pins assigned and signal settings of UART
109 **/
110 typedef struct {
111 UINT32 Enable : 1; ///< ISH UART GPIO pins assigned: <b>0: False</b> 1: True
112 UINT32 RsvdBits0 : 31; ///< Reserved Bits
113 ISH_UART_PIN_CONFIG PinConfig;
114 } ISH_UART;
115
116 /**
117 Struct contains GPIO pins assigned and signal settings of I2C
118 **/
119 typedef struct {
120 UINT32 Enable : 1; ///< ISH I2C GPIO pins assigned: <b>0: False</b> 1: True
121 UINT32 RsvdBits0 : 31; ///< Reserved Bits
122 ISH_I2C_PIN_CONFIG PinConfig;
123 } ISH_I2C;
124
125 /**
126 Struct contains GPIO pins assigned and signal settings of GP
127 **/
128 typedef struct {
129 UINT32 Enable : 1; ///< ISH GP GPIO pins assigned: <b>0: False</b> 1: True
130 UINT32 RsvdBits0 : 31; ///< Reserved Bits
131 ISH_GPIO_CONFIG PinConfig;
132 } ISH_GP;
133
134 ///
135 /// The ISH_CONFIG block describes Integrated Sensor Hub device.
136 ///
137 typedef struct {
138 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
139 ISH_SPI Spi[PCH_MAX_ISH_SPI_CONTROLLERS];
140 ISH_UART Uart[PCH_MAX_ISH_UART_CONTROLLERS];
141 ISH_I2C I2c[PCH_MAX_ISH_I2C_CONTROLLERS];
142 ISH_GP Gp[PCH_MAX_ISH_GP_PINS];
143
144 UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: <b>0: False</b> 1: True
145 UINT32 MsiInterrupt : 1; ///< ISH MSI Interrupts: <b>0: False</b> 1: True
146 UINT32 RsvdBits0 : 30; ///< Reserved Bits
147
148 } ISH_CONFIG;
149
150 typedef ISH_I2C ISH_I3C;
151 ///
152 /// The ISH_I3C_CONFIG block describes I3C in ISH device.
153 ///
154 typedef struct {
155 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
156
157 ISH_I3C Controller; ///< ISH I3C Controller
158 } ISH_I3C_CONFIG;
159
160 ///
161 /// Premem Policy for Integrated Sensor Hub device.
162 ///
163 typedef struct {
164 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
165 /**
166 ISH Controler 0: Disable; <b>1: Enable</b>.
167 For Desktop sku, the ISH POR should be disabled. <b> 0:Disable </b>.
168 **/
169 UINT32 Enable : 1;
170 UINT32 RsvdBits0 : 31; ///< Reserved Bits
171 } ISH_PREMEM_CONFIG;
172
173 #pragma pack (pop)
174
175 #endif // _ISH_CONFIG_H_
ISH_PREMEM_CONFIG
Premem Policy for Integrated Sensor Hub device.
Definition: IshConfig.h:163
ISH_I3C_CONFIG
The ISH_I3C_CONFIG block describes I3C in ISH device.
Definition: IshConfig.h:154
ISH_SPI::Enable
UINT8 Enable
ISH SPI GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:100
ISH_UART::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:112
ISH_I2C_PIN_CONFIG::Sda
ISH_GPIO_CONFIG Sda
SDA Pin configuration.
Definition: IshConfig.h:91
ISH_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:146
ISH_I2C
Struct contains GPIO pins assigned and signal settings of I2C.
Definition: IshConfig.h:119
ISH_UART_PIN_CONFIG::Cts
ISH_GPIO_CONFIG Cts
CTS Pin configuration.
Definition: IshConfig.h:83
ISH_GPIO_CONFIG::PadTermination
UINT32 PadTermination
GPIO Pads Internal Termination.
Definition: IshConfig.h:62
ISH_UART_PIN_CONFIG::Rx
ISH_GPIO_CONFIG Rx
RXD Pin configuration.
Definition: IshConfig.h:80
ISH_GP
Struct contains GPIO pins assigned and signal settings of GP.
Definition: IshConfig.h:128
ISH_I2C::Enable
UINT32 Enable
ISH I2C GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:120
ISH_UART_PIN_CONFIG
UART signals settings.
Definition: IshConfig.h:79
ISH_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:138
ISH_GPIO_CONFIG::PinMux
UINT32 PinMux
GPIO signals pin muxing settings.
Definition: IshConfig.h:56
ISH_GP::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:130
ISH_UART::Enable
UINT32 Enable
ISH UART GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:111
ISH_GP::Enable
UINT32 Enable
ISH GP GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:129
ISH_I2C::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:121
ISH_SPI::RsvdField0
UINT16 RsvdField0
Reserved field.
Definition: IshConfig.h:102
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ISH_SPI
Struct contains GPIO pins assigned and signal settings of SPI.
Definition: IshConfig.h:99
ISH_SPI_PIN_CONFIG::Clk
ISH_GPIO_CONFIG Clk
CLK Pin configuration.
Definition: IshConfig.h:71
ISH_UART
Struct contains GPIO pins assigned and signal settings of UART.
Definition: IshConfig.h:110
ISH_UART_PIN_CONFIG::Tx
ISH_GPIO_CONFIG Tx
TXD Pin configuration.
Definition: IshConfig.h:81
ISH_I2C_PIN_CONFIG
I2C signals settings.
Definition: IshConfig.h:90
ISH_I3C_CONFIG::Controller
ISH_I3C Controller
ISH I3C Controller.
Definition: IshConfig.h:157
ISH_PREMEM_CONFIG::Enable
UINT32 Enable
ISH Controler 0: Disable; 1: Enable.
Definition: IshConfig.h:169
ISH_SPI_PIN_CONFIG
SPI signals settings.
Definition: IshConfig.h:68
ISH_GPIO_CONFIG
ISH GPIO settings.
Definition: IshConfig.h:50
ISH_I2C_PIN_CONFIG::Scl
ISH_GPIO_CONFIG Scl
SCL Pin configuration.
Definition: IshConfig.h:92
ISH_I3C_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:155
ISH_CONFIG
The ISH_CONFIG block describes Integrated Sensor Hub device.
Definition: IshConfig.h:137
ISH_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:170
ISH_CONFIG::PdtUnlock
UINT32 PdtUnlock
ISH PDT Unlock Msg: 0: False 1: True.
Definition: IshConfig.h:144
ISH_UART_PIN_CONFIG::Rts
ISH_GPIO_CONFIG Rts
RTS Pin configuration.
Definition: IshConfig.h:82
ISH_CONFIG::MsiInterrupt
UINT32 MsiInterrupt
ISH MSI Interrupts: 0: False 1: True.
Definition: IshConfig.h:145
ISH_SPI_PIN_CONFIG::Miso
ISH_GPIO_CONFIG Miso
MISO Pin configuration.
Definition: IshConfig.h:70
ISH_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:164
ISH_SPI_PIN_CONFIG::Mosi
ISH_GPIO_CONFIG Mosi
MOSI Pin configuration.
Definition: IshConfig.h:69
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: LockDownConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
Classes
LockDownConfig.h File Reference

Lock down policy. More...

Go to the source code of this file.

Classes

struct PCH_LOCK_DOWN_CONFIG
The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement. More...

Detailed Description

Lock down policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file LockDownConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: LockDownConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
LockDownConfig.h
Go to the documentation of this file.
1 /** @file
2 Lock down policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _LOCK_DOWN_CONFIG_H_
36 #define _LOCK_DOWN_CONFIG_H_
37
38 #define PCH_LOCK_DOWN_CONFIG_REVISION 1
39 extern EFI_GUID gLockDownConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
45 for security requirement.
46 **/
47 typedef struct {
48 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
49 /**
50 <b>(Test)</b> Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; <b>1: Enable</b>.
51 **/
52 UINT32 GlobalSmi : 1;
53 /**
54 <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
55 Top Swap bit and the General Control and Status Registers Boot BIOS Straps.
56 Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit
57 will mitigate malicious software attempts to replace the system BIOS with its own code.
58 0: Disable; <b>1: Enable</b>.
59 **/
60 UINT32 BiosInterface : 1;
61 /**
62 Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
63 for the BIOS region protection. When it is enabled, the BIOS Region can only be
64 modified from SMM.
65 If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
66 in order to write to BIOS regions of SPI Flash. If this EISS bit is clear,
67 then the InSMM.STS is a don't care.
68 The BIOS must set the EISS bit while BIOS Guard support is enabled.
69 In recovery path, platform can temporary disable EISS for SPI programming in
70 PEI phase or early DXE phase.
71 When PcdSmmVariableEnable is FALSE, to support BIOS regions update outside of SMM,
72 the BiosLock must be set to Disabled by platform.
73 0: Disable; <b>1: Enable.</b>
74 **/
75 UINT32 BiosLock : 1;
76 UINT32 SpiEiss : 1; ///< Separate EISS policy to be handled separately from BiosLock
77 /**
78 <b>(Test)</b> This test option when set will force all GPIO pads to be unlocked
79 before BIOS transitions to POSTBOOT_SAI. This option should not be enabled in production
80 configuration and used only for debug purpose when free runtime reconfiguration of
81 GPIO pads is needed.
82 <b>0: Disable</b>; 1: Enable.
83 **/
84 UINT32 UnlockGpioPads : 1;
85 UINT32 RsvdBits0 : 27; ///< Reserved bits
86 } PCH_LOCK_DOWN_CONFIG;
87
88 #pragma pack (pop)
89
90 #endif // _LOCK_DOWN_CONFIG_H_
PCH_LOCK_DOWN_CONFIG::SpiEiss
UINT32 SpiEiss
Separate EISS policy to be handled separately from BiosLock.
Definition: LockDownConfig.h:76
PCH_LOCK_DOWN_CONFIG::BiosLock
UINT32 BiosLock
Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region pro...
Definition: LockDownConfig.h:75
PCH_LOCK_DOWN_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: LockDownConfig.h:48
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_LOCK_DOWN_CONFIG
The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requireme...
Definition: LockDownConfig.h:47
PCH_LOCK_DOWN_CONFIG::BiosInterface
UINT32 BiosInterface
(Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register Top Swap ...
Definition: LockDownConfig.h:60
PCH_LOCK_DOWN_CONFIG::GlobalSmi
UINT32 GlobalSmi
(Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
Definition: LockDownConfig.h:52
PCH_LOCK_DOWN_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: LockDownConfig.h:85
PCH_LOCK_DOWN_CONFIG::UnlockGpioPads
UINT32 UnlockGpioPads
(Test) This test option when set will force all GPIO pads to be unlocked before BIOS transitions to P...
Definition: LockDownConfig.h:84
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MemoryConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
  • Ver2
Classes | Macros | Typedefs | Enumerations
MemoryConfig.h File Reference

Policy definition of Memory Config Block. More...

Go to the source code of this file.

Classes

struct | SPD_DATA_BUFFER
SPD Data Buffer. More...
struct | SA_MEMORY_DQDQS_MAPPING
DqDqs Mapping. More...
struct | SA_MEMORY_RCOMP
Rcomp Policies. More...
struct | SPD_OFFSET_TABLE
SPD Offset Table. More...
struct | SA_ADDRESS_DECODE
SA memory address decode. More...
struct | SA_FUNCTION_CALLS
Function calls into the SA. More...
struct | SA_MEMORY_FUNCTIONS
Function calls into the MRC. More...
struct | MEMORY_CONFIGURATION
Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection. More...
struct | MEMORY_CONFIG_NO_CRC
Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection. More...

Macros

#define | MRC_MAX_RCOMP_TARGETS 5
MEMORY_CONFIGURATION interface definitions.
#define | MEM_CFG_MAX_CONTROLLERS 2
Memory SubSystem Definitions.
#define | PEI_MR_SMRAM_ABSEG_MASK 0x01
SMRAM Memory Range.

Typedefs

typedef UINT8(* | SA_IO_READ_8) (UINTN IoAddress)
CPU I/O port 8-bit read.
typedef UINT16(* | SA_IO_READ_16) (UINTN IoAddress)
CPU I/O port 16-bit read.
typedef UINT32(* | SA_IO_READ_32) (UINTN IoAddress)
CPU I/O port 32-bit read.
typedef UINT8(* | SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value)
CPU I/O port 8-bit write.
typedef UINT16(* | SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value)
CPU I/O port 16-bit write.
typedef UINT32(* | SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value)
CPU I/O port 32-bit write.
typedef UINT8(* | SA_MMIO_READ_8) (UINTN Address)
Memory Mapped I/O port 8-bit read.
typedef UINT16(* | SA_MMIO_READ_16) (UINTN Address)
Memory Mapped I/O port 16-bit read.
typedef UINT32(* | SA_MMIO_READ_32) (UINTN Address)
Memory Mapped I/O port 32-bit read.
typedef UINT64(* | SA_MMIO_READ_64) (UINTN Address)
Memory Mapped I/O port 64-bit read.
typedef UINT8(* | SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value)
Memory Mapped I/O port 8-bit write.
typedef UINT16(* | SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value)
Memory Mapped I/O port 16-bit write.
typedef UINT32(* | SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value)
Memory Mapped I/O port 32-bit write.
typedef UINT64(* | SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value)
Memory Mapped I/O port 64-bit write.
typedef UINT8(* | SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status)
Smbus 8-bit read.
typedef UINT16(* | SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status)
Smbus 16-bit read.
typedef UINT8(* | SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status)
Smbus 8-bit write.
typedef UINT16(* | SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status)
Smbus 16-bit write.
typedef UINT32(* | SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI device address.
typedef UINT32(* | SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI express device address.
typedef VOID(* | SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year)
Get the current time value.
typedef UINT64(* | SA_GET_CPU_TIME) (VOID)
The current CPU time in milliseconds.
typedef VOID *(* | SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes)
Perform byte copy operation.
typedef VOID *(* | SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value)
Perform byte initialization operation.
typedef VOID *(* | SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value)
Perform word initialization operation.
typedef VOID *(* | SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value)
Perform dword initialization operation.
typedef UINT64(* | SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits)
Left shift the 64-bit data value by specified number of bits.
typedef UINT64(* | SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits)
Right shift the 64-bit data value by specified number of bits.
typedef UINT64(* | SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier)
Multiply a 64-bit data value by a 32-bit data value.
typedef UINT64(* | SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder)
Divide a 64-bit data value by a 64-bit data value.
typedef BOOLEAN(* | SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize)
Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
typedef BOOLEAN(* | SA_GET_RANDOM_NUMBER) (UINT32 *Rand)
Get the next random 32-bit number.
typedef EFI_STATUS(* | SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status)
Perform a CPU mailbox read.
typedef EFI_STATUS(* | SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status)
Perform a CPU mailbox write.
typedef UINT32(* | SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd)
Get the current memory voltage (VDD).
typedef UINT32(* | SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value)
Set the memory voltage (VDD) to the given value.
typedef UINT32(* | SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp)
Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
typedef UINT32(* | SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch)
Check point that is called at various points in the MRC.
typedef VOID(* | SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber)
Typically used to display to the I/O port 80h.
typedef UINT8(* | SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel)
Returns whether Channel is or is not present.
typedef INT32(* | SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format,...)
Print to output stream/device.
typedef VOID(* | SA_DEBUG_PRINT) (VOID *String)
Output a string to the debug stream/device.
typedef UINT32(* | SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam)
Change the margin.
typedef UINT8(* | SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb)
Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
typedef VOID(* | SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost)
Move CMD/CTL/CLK/CKE PIs during training.
typedef VOID(* | SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait)
Update the Vref value and wait until it is stable.
typedef UINT8(* | SA_GET_RTC_CMOS) (UINT8 Location)
Get the current value of the specified RTC CMOS location.
typedef UINT64(* | SA_MSR_READ_64) (UINT32 Location)
Get the current value of the specified MSR location.
typedef UINT64(* | SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data)
Set the current value of the specified MSR location.
typedef VOID(* | SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus)
Hook function after returning from MrcStartMemoryConfiguration()
typedef VOID(* | SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue)
Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
typedef VOID(* | SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs)
Delay (stall) for the given amount of nanoseconds.

Enumerations

enum | SA_SPD
SA SPD profile selections. More...
enum | SPD_BOOT_MODE
Define the boot modes used by the SPD read function. More...

Detailed Description

Policy definition of Memory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MemoryConfig.h.

Enumeration Type Documentation

◆ SA_SPD

enum SA_SPD

SA SPD profile selections.

Enumerator
DEFAULT_SPD | Standard DIMM profile select.
CUSTOM_PROFILE | XMP enthusiast settings: User specifies various override values.
XMP_PROFILE_1 | XMP enthusiast settings: XMP profile #1.
XMP_PROFILE_2 | XMP enthusiast settings: XMP profile #2.
XMP_PROFILE_3 | XMP enthusiast settings: XMP profile #3.
XMP_USER_PROFILE_4 | XMP enthusiast settings: XMP user profile #4.
XMP_USER_PROFILE_5 | XMP enthusiast settings: XMP user profile #5.
SPDProfileMax | Ensures SA_SPD is UINT8.

Definition at line 107 of file MemoryConfig.h.

◆ SPD_BOOT_MODE

enum SPD_BOOT_MODE

Define the boot modes used by the SPD read function.

Enumerator
SpdCold | Cold boot.
SpdWarm | Warm boot.
SpdS3 | S3 resume.
SpdFast | Fast boot.
SpdBootModeMax | Delimiter.

Definition at line 121 of file MemoryConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MemoryConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
  • Ver2
MemoryConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition of Memory Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEMORY_CONFIG_H_
36 #define _MEMORY_CONFIG_H_
37
38
39 #pragma pack(push, 1)
40
41 // MEMORY_CONFIGURATION_REVISION:
42 // 3 - Adds DDR5 PDA Enumeration training
43 // 4 - Adds LPDDR4 Command Mirroring
44 // 5 - Adds PprEnableType
45 // 6 - Removed IbeccParity
46 // 7 - Adds MarginLimitCheck training within MEMORY_CONFIGURATION
47 // 8 - Adds LpddrRttCa, LpddrRttWr
48 // 9 - Adds VddqVoltage, VppVoltage
49 // 10 - Changes PprEnableType to PprEnable
50 // 11 - Changes DisableDimmChannel to DisableChannel
51 // 12 - Added DIMMDFE
52 // 13 - Added ExtendedBankHashing
53 // 14 - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount
54 // 15 - Added DynamicMemoryBoost
55 // 16 - Added ReuseAdlDdr5Board
56 // 17 - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm
57 // 18 - Added DebugValue
58 // 19 - Added McRefreshRate; Deprecated McRefresh2X
59 // 20 - Added RealtimeMemoryFrequency
60 // 21 - Added PeriodicDcc and LpMode
61 // 22 - Added Tx Dqs Dcc Training
62 // 23 - Added tRFCpb, tRFC2, tRFC4, tRRD_L, tRRD_S, tWTR_L, tCCD_L, tWTR_S
63 // 24 - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount
64 // 25 - Added FreqLimitMixedConfig, FirstDimmBitMask, UserBd
65 // 26 - Added SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsDownControl, SagvHeuristicsUpControl
66 // 27 - Added DRAMDCA
67 // 28 - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R
68 // 29 - Added LctCmdEyeWidth
69 // 30 - Added FirstDimmBitMaskEcc
70 // 31 - Added Lp5BankMode
71 // 32 - Added WRDS
72 #define MEMORY_CONFIGURATION_REVISION 32
73
74 // MEMORY_CONFIG_NO_CRC_REVISION:
75 // 3 - adds DDR5 SetMemoryPmicVoltage in SA_FUNCTION_CALLS
76 #define MEMORY_CONFIG_NO_CRC_REVISION 3
77
78 ///
79 /// MEMORY_CONFIGURATION interface definitions
80 ///
81 #define MRC_MAX_RCOMP_TARGETS 5
82 ///
83 /// Memory SubSystem Definitions
84 ///
85 #define MEM_CFG_MAX_CONTROLLERS 2
86 #define MEM_CFG_MAX_CHANNELS 4
87 #define MEM_CFG_MAX_CHANNEL_SHARE_REGS 2
88 #define MEM_CFG_MAX_DIMMS 2
89 #define MEM_CFG_MAX_RANKS_PER_DIMM 2
90 #define MEM_CFG_NUM_BYTES_MAPPED 2
91 #define MEM_CFG_MAX_SPD_SIZE 1024
92 #define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_MAX_DIMMS)
93 #define MEM_CFG_MAX_ROWS (MEM_CFG_MAX_RANKS_PER_DIMM * MEM_CFG_MAX_SOCKETS)
94 #ifndef MEM_MAX_SAGV_POINTS
95 #define MEM_MAX_SAGV_POINTS 4
96 #endif
97 #define MEM_MAX_IBECC_REGIONS 8
98 ///
99 /// SMRAM Memory Range
100 ///
101 #define PEI_MR_SMRAM_ABSEG_MASK 0x01
102 #define PEI_MR_SMRAM_HSEG_MASK 0x02
103
104 ///
105 /// SA SPD profile selections.
106 ///
107 typedef enum {
108 DEFAULT_SPD, ///< Standard DIMM profile select.
109 CUSTOM_PROFILE, ///< XMP enthusiast settings: User specifies various override values
110 XMP_PROFILE_1, ///< XMP enthusiast settings: XMP profile #1
111 XMP_PROFILE_2, ///< XMP enthusiast settings: XMP profile #2
112 XMP_PROFILE_3, ///< XMP enthusiast settings: XMP profile #3
113 XMP_USER_PROFILE_4, ///< XMP enthusiast settings: XMP user profile #4
114 XMP_USER_PROFILE_5, ///< XMP enthusiast settings: XMP user profile #5
115 SPDProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
116 } SA_SPD;
117
118 ///
119 /// Define the boot modes used by the SPD read function.
120 ///
121 typedef enum {
122 SpdCold, ///< Cold boot
123 SpdWarm, ///< Warm boot
124 SpdS3, ///< S3 resume
125 SpdFast, ///< Fast boot
126 SpdBootModeMax ///< Delimiter
127 } SPD_BOOT_MODE;
128
129 /**
130 SPD Data Buffer
131 **/
132 typedef struct {
133 UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData
134 //Next Field Offset 2048
135 } SPD_DATA_BUFFER;
136
137 /**
138 DqDqs Mapping
139 **/
140 typedef struct {
141 UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram
142 UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram
143 //Next Field Offset 16
144 } SA_MEMORY_DQDQS_MAPPING;
145
146 /**
147 Rcomp Policies
148 **/
149 typedef struct {
150 UINT16 RcompResistor; ///< Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms
151 UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
152 //Next Field Offset 16
153 } SA_MEMORY_RCOMP;
154
155 /**
156 SPD Offset Table
157 **/
158 typedef struct {
159 UINT16 Start; ///< Offset 0
160 UINT16 End; ///< Offset 2
161 UINT8 BootMode; ///< Offset 4
162 UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
163 } SPD_OFFSET_TABLE;
164
165 ///
166 /// SA memory address decode.
167 ///
168 typedef struct
169 {
170 UINT8 Controller; ///< Offset 0 Zero based Controller number
171 UINT8 Channel; ///< Offset 1 Zero based Channel number
172 UINT8 Dimm; ///< Offset 2 Zero based DIMM number
173 UINT8 Rank; ///< Offset 3 Zero based Rank number
174 UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
175 UINT8 Bank; ///< Offset 5 Zero based Bank number
176 UINT16 Cas; ///< Offset 6 Zero based CAS number
177 UINT32 Ras; ///< Offset 8 Zero based RAS number
178 } SA_ADDRESS_DECODE;
179
180 typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress); ///< CPU I/O port 8-bit read.
181 typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress); ///< CPU I/O port 16-bit read.
182 typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress); ///< CPU I/O port 32-bit read.
183 typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value); ///< CPU I/O port 8-bit write.
184 typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value); ///< CPU I/O port 16-bit write.
185 typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value); ///< CPU I/O port 32-bit write.
186 typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); ///< Memory Mapped I/O port 8-bit read.
187 typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); ///< Memory Mapped I/O port 16-bit read.
188 typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); ///< Memory Mapped I/O port 32-bit read.
189 typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); ///< Memory Mapped I/O port 64-bit read.
190 typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value); ///< Memory Mapped I/O port 8-bit write.
191 typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value); ///< Memory Mapped I/O port 16-bit write.
192 typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value); ///< Memory Mapped I/O port 32-bit write.
193 typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value); ///< Memory Mapped I/O port 64-bit write.
194 typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 8-bit read.
195 typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 16-bit read.
196 typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status); ///< Smbus 8-bit write.
197 typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status); ///< Smbus 16-bit write.
198 typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI device address.
199 typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI express device address.
200 typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); ///< Get the current time value.
201 typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); ///< The current CPU time in milliseconds.
202 typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes); ///< Perform byte copy operation.
203 typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value); ///< Perform byte initialization operation.
204 typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value); ///< Perform word initialization operation.
205 typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value); ///< Perform dword initialization operation.
206 typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Left shift the 64-bit data value by specified number of bits.
207 typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Right shift the 64-bit data value by specified number of bits.
208 typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier); ///< Multiply a 64-bit data value by a 32-bit data value.
209 typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder); ///< Divide a 64-bit data value by a 64-bit data value.
210 typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///< Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
211 typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, SA_ADDRESS_DECODE *DramAddress);
212 typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
213 typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); ///< Get the next random 32-bit number.
214 typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status); ///< Perform a CPU mailbox read.
215 typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status); ///< Perform a CPU mailbox write.
216 typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd); ///< Get the current memory voltage (VDD).
217 typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value); ///< Set the memory voltage (VDD) to the given value.
218 typedef UINT32 (EFIAPI * SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp); ///< Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
219 typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch); ///< Check point that is called at various points in the MRC.
220 typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber); ///< Typically used to display to the I/O port 80h.
221 typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel); ///< Returns whether Channel is or is not present.
222 typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format, ...); ///< Print to output stream/device.
223 typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); ///< Output a string to the debug stream/device.
224 typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the margin.
225 typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb); ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
226 typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost); ///< Move CMD/CTL/CLK/CKE PIs during training.
227 typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); ///< Update the Vref value and wait until it is stable.
228 typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); ///< Get the current value of the specified RTC CMOS location.
229 typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location); ///< Get the current value of the specified MSR location.
230 typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data); ///< Set the current value of the specified MSR location.
231 typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus); ///< Hook function after returning from MrcStartMemoryConfiguration()
232 typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue); ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
233 typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs); ///< Delay (stall) for the given amount of nanoseconds.
234 typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBaseAddress, UINT32 PrmrrSize);
235
236
237 ///
238 /// Function calls into the SA.
239 ///
240 typedef struct {
241 SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit read.
242 SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-bit read.
243 SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-bit read.
244 SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit write.
245 SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-bit write.
246 SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-bit write.
247 SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory Mapped I/O port 8-bit read.
248 SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory Mapped I/O port 16-bit read.
249 SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory Mapped I/O port 32-bit read.
250 SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory Mapped I/O port 64-bit read.
251 SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory Mapped I/O port 8-bit write.
252 SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory Mapped I/O port 16-bit write.
253 SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory Mapped I/O port 32-bit write.
254 SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory Mapped I/O port 64-bit write.
255 SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit read.
256 SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-bit read.
257 SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-bit write.
258 SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus 16-bit write.
259 SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get PCI device address.
260 SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get PCI express device address.
261 SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the current time value.
262 SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current CPU time in milliseconds.
263 SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform byte copy operation.
264 SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform byte initialization operation.
265 SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Perform word initialization operation.
266 SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Perform dword initialization operation.
267 SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the 64-bit data value by specified number of bits.
268 SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the 64-bit data value by specified number of bits.
269 SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
270 SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit data value by a 64-bit data value.
271 SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
272 SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get the next random 32-bit number.
273 SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Perform a CPU mailbox read.
274 SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Perform a CPU mailbox write.
275 SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get the current memory voltage (VDD).
276 SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set the memory voltage (VDD) to the given value.
277 SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point that is called at various points in the MRC.
278 SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically used to display to the I/O port 80h.
279 SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a string to the debug stream/device.
280 SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the current value of the specified RTC CMOS location.
281 SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the current value of the specified MSR location.
282 SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the current value of the specified MSR location.
283 SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
284 SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
285 SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Delay (stall) for the given amount of nanoseconds.
286 SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage; ///< Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
287 } SA_FUNCTION_CALLS;
288
289 ///
290 /// Function calls into the MRC.
291 ///
292 typedef struct {
293 SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns whether Channel is or is not present.
294 SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output stream/device.
295 SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Change the margin.
296 SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
297 SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
298 SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update the Vref value and wait until it is stable.
299 } SA_MEMORY_FUNCTIONS;
300
301 /**
302 Memory Configuration
303 The contents of this structure are CRC'd by the MRC for option change detection.
304 This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure.
305 Revision history is at the top of this file
306 **/
307 typedef struct {
308 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
309 UINT16 Size; ///< Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
310 UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
311
312 UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5
313
314 // The following parameters are used only when SpdProfileSelected is User Defined (CUSTOM_PROFILE)
315 UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
316 UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum
317 UINT16 tRAS; ///< Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
318 UINT16 tWR; ///< Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
319 UINT16 tRFC; ///< Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
320 UINT16 tRRD; ///< Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
321 UINT16 tWTR; ///< Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
322 UINT16 tRTP; ///< Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
323 UINT16 tFAW; ///< Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
324 UINT16 tCWL; ///< Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
325 UINT16 tREFI; ///< Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
326 UINT16 PciIndex; ///< Offset 54 Pci index register address: <b>0xCF8=Default</b>
327 UINT16 PciData; ///< Offset 56 Pci data register address: <b>0xCFC=Default</b>
328 UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
329 UINT16 Idd3n; ///< Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
330 UINT16 Idd3p; ///< Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
331
332 UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
333 UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode: <b>0=Disable</b>, 1=Enable
334 UINT32 RemapEnable:1; ///< Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
335 UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scrambler support: 0=Disable, <b>1=Enable</b>
336 UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
337 UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): <b>0=Disable</b>, 1=Enable
338 UINT32 SimicsFlag:1; ///< Bit 6 - Option to Enable SIMICS: 0=Disable, <b>1=Enable</b>
339 UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
340 UINT32 SharedZqPin:1; ///< Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages <b>0=Not Shared</b>, 1=Shared
341 UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, <b>1=Enable</b>
342 UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin Tool Per Task. <b>0 = Disabled</b>, 1 = Enabled
343 UINT32 TrainTrace:1; ///< Bit 11 - Trained state tracing debug. <b>0 = Disabled</b>, 1 = Enabled
344 UINT32 SafeMode:1; ///< Bit 12 - Define if safe mode is enabled for MC/IO
345 UINT32 MsHashEnable:1; ///< Bit 13 - Controller Hash Enable: 0=Disable, <b>1=Enable</b>
346 UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page Close Idle Timeout: 0=Enable, <b>1=Disable</b>
347 UINT32 Ibecc:1; ///< Bit 15 - In-band ECC: <b>0=Disable</b>, 1=Enable
348 UINT32 IbeccOperationMode:2; ///< Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, <b>2=Makes all requests protected and ignore range checks</b>
349 UINT32 ChHashOverride:1; ///< Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
350 UINT32 EccDftEn:1; ///< Bit 19 - ECC DFT support option
351 UINT32 Write0:1; ///< Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, <b>1=Enable</b>
352 UINT32 ReuseAdlSDdr5Board:1; ///< Bit 21 - Indicate whether adl ddr5 board is reused.
353 UINT32 PeriodicDcc:1; ///< Bit 22 - Periodic DCC: <b>0=Disable</b>, 1=Enable
354 UINT32 LpMode:2; ///< Bit 23:24 - LPMode: <b>0=Auto</b>, 1=Enabled, 2=Disabled, 3=Reserved
355 UINT32 RsvdO64B25to31:7; ///< Bits 25:31 reserved
356 UINT8 DisableChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]; ///< Offset 68-75
357 UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. <b>0 = Auto</b>
358 UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: <b>0=Disabled</b>, <b>1=Enabled</b>
359 /**
360 Channel Hash Enable.\n
361 NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8\n
362 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
363 **/
364 UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)
365 UINT8 SmramMask; ///< Offset 79 Reserved memory ranges for SMRAM
366 UINT32 BClkFrequency; ///< Offset 80 Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
367
368 /// Training Algorithms 1 Offset 84
369 UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
370 UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
371 UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
372 UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
373 UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
374 UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
375 UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
376 UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
377 UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
378 UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
379 UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
380 UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
381 UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
382 UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
383 UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable.</b>
384 UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
385 UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
386 UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
387 UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
388 UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
389 UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
390 UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
391 UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, <b>1=Enable</b>.
392 UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
393 UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
394 UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
395 UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin Tool function: <b>0=Disable</b>, 1=Enable.
396 UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test function: <b>0=Disable</b>, 1=Enable.
397 UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, <b>1=Enable</b>
398 UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
399 UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
400 UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
401 /// Training Algorithms 2 Offset 88
402 UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.
403 UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
404 UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
405 UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
406 UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
407 UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
408 UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
409 UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
410 UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
411 UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
412 UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
413 UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
414 UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
415 UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
416 UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
417 UINT32 DIMMDFE : 1; ///< BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
418 UINT32 TXDQSDCC : 1; ///< BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, <b>1=Enable</b>.
419 UINT32 DRAMDCA : 1; ///< BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, <b>1=Enable</b>.
420 UINT32 WRDS : 1; ///< BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, <b>1=Enable</b>.
421 UINT32 ReservedBits2 :13; ///< Bits 19:31 - Reserved
422
423 UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
424 UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
425 UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: <b>0=Disable</b>, 1=Enable
426 UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
427 UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
428 UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
429 UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
430 UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
431 UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
432 UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
433 UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
434 UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
435 UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
436 UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
437 UINT32 MobilePlatform:1; ///< Bit 14 - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
438 UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
439 UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
440 UINT32 VttTermination:1; ///< Bit 17 - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
441 UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
442 UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
443 UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable knob for new feature set 1 <b>0: Disable </b>; 1: Enable
444 UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable knob for new feature set 2 <b>0: Disable </b>; 1: Enable
445 UINT32 RhSelect:2; ///< Bit 22-23 - RH Select: <b>0=Disable</b>, 1=RFM, 2=pTRR
446 UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
447 UINT32 RefreshHpWm:4; ///< Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
448 UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
449 UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
450 UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
451 UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency limit: <b>0 = Auto</b>, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h
452 UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
453 UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
454 UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
455 BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, <b>TRUE=Enabled</b>
456 UINT8 SaGv; ///< Offset 110 SA GV: <b>0=Disabled</b>, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled
457 UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
458 UINT8 RefClk; ///< Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
459 UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, <b>7=3 CMDs</b>, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs
460 UINT8 Refresh2X; ///< Offset 114 Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
461 UINT8 EpgEnable; ///< Offset 115 Enable Energy Performance Gain.
462 UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
463 UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
464 UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
465 UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
466 UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
467 UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and Rank1 is non-terminating</b>
468 UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
469 UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
470 UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, <b>0=Default</b>
471 UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9
472 UINT8 GearRatio; ///< Offset 130 Gear mode when SAGV is disabled: <b>0=Auto</b>, 1 - Gear1, 2 - Gear2, 4 - Gear4.
473 UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
474 UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No RFI Tuning</b>. Range is 98Mhz-100Mhz.
475 UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: <b>0=Default</b>, 1067, 1333, 1600, 1800, 1867, etc.
476 UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: <b>0=Auto</b>, 1, 2, 4
477 UINT8 IbeccProtectedRangeEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset 160 Enable use of address range for ECC Protection: <b>0=Disabled</b>, 1=Enabled
478 UINT32 IbeccProtectedRangeBase[MEM_MAX_IBECC_REGIONS]; ///< Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF]
479 UINT32 IbeccProtectedRangeMask[MEM_MAX_IBECC_REGIONS]; ///< Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF]
480
481 UINT8 McRefresh2X; ///< Offset 232 Deprecated from revision 19, use McRefreshRate instead
482 UINT8 Lfsr0Mask; ///< Offset 233 RH pTRR LFSR0 Mask
483 UINT8 Lfsr1Mask; ///< Offset 234 RH pTRR LFSR1 Mask
484 UINT8 CmdMirror; ///< Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
485 UINT8 AllowOppRefBelowWriteThrehold; ///< Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
486 UINT8 WriteThreshold; ///< Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
487 UINT8 PprEnable; ///< Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR
488 UINT8 MarginLimitCheck; ///< Offset 239 Margin limit check enable: <b>0=Disable</b>, 1=L1 only, 2=L2 only, 3=Both L1 and L2
489 UINT16 MarginLimitL2; ///< Offset 240 Margin limit check L2 threshold: <b>100=Default</b>
490 UINT8 LpddrRttWr; ///< Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto
491 UINT8 LpddrRttCa; ///< Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto
492 UINT16 VddqVoltage; ///< Offset 244 DRAM voltage (Vddq) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
493 UINT16 VppVoltage; ///< Offset 246 DRAM voltage (Vpp) in millivolts: <b>0=Platform Default (no override)</b>, 1800=1.8V, 2050=2.05V etc.
494 UINT8 ExtendedBankHashing; ///< Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; <b>1 = Enabled</b>
495 UINT8 DynamicMemoryBoost; ///< Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
496 UINT8 IbeccErrInjControl; ///< Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter
497 UINT8 RealtimeMemoryFrequency; ///< Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
498 UINT32 IbeccErrInjCount; ///< Offset 252 Number of transactions between ECC error injection
499 UINT64 IbeccErrInjAddress; ///< Offset 256 Address to match against for ECC error injection
500 UINT64 IbeccErrInjMask; ///< Offset 264 Mask to match against for ECC error injection
501 UINT8 RefreshWm; ///< Offset 272 Refresh Watermarks, 0 = Low, <b>1 = High</b>
502 UINT8 McRefreshRate; ///< Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x
503 UINT8 Reserved274[2]; ///< Offset 274-275 Reserved for natural alignment
504 UINT32 DebugValue; ///< Offset 276 Debug Value for general use
505 UINT16 tRFCpb; ///< Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
506 UINT16 tRFC2; ///< Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
507 UINT16 tRFC4; ///< Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
508 UINT16 tRRD_L; ///< Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
509 UINT16 tRRD_S; ///< Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
510 UINT16 tWTR_L; ///< Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
511 UINT16 tCCD_L; ///< Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
512 UINT16 tWTR_S; ///< Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
513 UINT64 EccErrInjAddress; ///< Offset 296 Address to match against for ECC error injection
514 UINT64 EccErrInjMask; ///< Offset 304 Mask to match against for ECC error injection
515 UINT32 EccErrInjCount; ///< Offset 312 Number of transactions between ECC error injection
516
517
518 UINT16 FreqLimitMixedConfig; ///< Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. <b>0=Auto</b>, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h
519 UINT8 FirstDimmBitMask; ///< Offset 318 Defines which DIMM should be populated first on a 2DPC board.
520 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
521 ///< For each MC, the first DIMM to be populated should be set to '1'.
522 ///< Note: this mask is only for non-ECC DIMM.
523 UINT8 UserBd; ///< Offset 319 MrcBoardType
524 ///< 1 - Desktop 1DPC
525 ///< 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first
526 ///< 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order
527 ///< 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order
528 ///< 5 - ULT Mobile
529 UINT8 SagvSwitchFactorIA; ///< Offset 320 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
530 UINT8 SagvSwitchFactorGT; ///< Offset 321 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
531 UINT8 SagvSwitchFactorIO; ///< Offset 322 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
532 UINT8 SagvSwitchFactorStall; ///< Offset 323 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
533 UINT8 SagvHeuristicsUpControl;///< Offset 324 Sagv duration in ms before heuristics up: <b>1 </b>, 50=Maximum, default 1ms.
534 UINT8 SagvHeuristicsDownControl; ///< Offset 325 Sagv duration in ms before heuristics down: <b>1 </b>, 50=Maximum, default 1ms.
535 UINT16 FreqLimitMixedConfig_1R1R_8GB; ///< Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).
536 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
537 UINT16 FreqLimitMixedConfig_1R1R_16GB; ///< Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).
538 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
539 UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; ///< Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).
540 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
541 UINT16 FreqLimitMixedConfig_2R2R; ///< Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).
542 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
543 UINT16 LctCmdEyeWidth; ///< Offset 334 LCT Command eyewidth
544 UINT8 FirstDimmBitMaskEcc; ///< Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
545 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
546 ///< For each MC, the first DIMM to be populated should be set to '1'.
547 ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
548 ///< be populated firstly.
549 ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
550 UINT8 Lp5BankMode; ///< Offset 337 LP5 Bank Mode
551 UINT8 Reserved336[6]; ///< Offset 338-343 Reserved for natural alignment
552 } MEMORY_CONFIGURATION;
553
554 /// Memory Configuration
555 /// The contents of this structure are not CRC'd by the MRC for option change detection.
556 /// <b>Revision 1</b>: - Initial version.
557 /// <b>Revision 2</b>: - Added MemTestOnWarmBoot
558 typedef struct {
559 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
560 SA_FUNCTION_CALLS SaCall; ///< Offset 28 Function calls into the SA.
561 SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 212 Function calls into the MRC.
562 SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
563 SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
564 SA_MEMORY_RCOMP *RcompData; ///< Offset 244 DDR RCOMP resistors and target values.
565 UINT64 PlatformMemorySize; ///< Offset 248 The minimum platform memory size required to pass control into DXE
566 UINT32 CleanMemory:1; ///< Offset 256 Ask MRC to clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear Memory
567 UINT32 ReservedBits5:31;
568 /**
569 Sets the serial debug message level\n
570 0x00 = Disabled\n
571 0x01 = Errors only\n
572 0x02 = Errors and Warnings\n
573 <b>0x03 = Errors, Warnings, and Info</b>\n
574 0x04 = Errors, Warnings, Info, and Events\n
575 0x05 = Displays Memory Init Execution Time Summary only\n
576 **/
577 UINT8 SerialDebugLevel; ///< Offset 260
578 UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
579 UINT8 Reserved11[2]; ///< Offset 262 - 263 Reserved
580 } MEMORY_CONFIG_NO_CRC;
581 #pragma pack(pop)
582
583 #endif // _MEMORY_CONFIG_H_
MEMORY_CONFIGURATION::IbeccOperationMode
UINT32 IbeccOperationMode
Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address ran...
Definition: MemoryConfig.h:348
MEMORY_CONFIGURATION::Ddr4DdpSharedClock
UINT32 Ddr4DdpSharedClock
Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. 0=Not shared,...
Definition: MemoryConfig.h:339
MEMORY_CONFIGURATION::WRTC1D
UINT32 WRTC1D
Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this ...
Definition: MemoryConfig.h:377
SA_IO_WRITE_16
UINT16(* SA_IO_WRITE_16)(UINTN IoAddress, UINT16 Value)
CPU I/O port 16-bit write.
Definition: MemoryConfig.h:184
MEMORY_CONFIGURATION::DIMMRONT
UINT32 DIMMRONT
Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the...
Definition: MemoryConfig.h:381
MEMORY_CONFIGURATION::tRFC
UINT16 tRFC
Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:319
MEMORY_CONFIGURATION::DRAMDCA
UINT32 DRAMDCA
BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:419
MEMORY_CONFIGURATION::Vc1ReadMeter
UINT32 Vc1ReadMeter
Bit 4 - VC1 Read Metering Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:336
SA_FUNCTION_CALLS::MmioWrite64
SA_MMIO_WRITE_64 MmioWrite64
Offset 52: - Memory Mapped I/O port 64-bit write.
Definition: MemoryConfig.h:254
MEMORY_CONFIGURATION::SrefCfgEna
UINT32 SrefCfgEna
Bit 9 - Enable Self Refresh: 0=Disable, 1=Enable
Definition: MemoryConfig.h:432
MEMORY_CONFIGURATION::SagvSwitchFactorGT
UINT8 SagvSwitchFactorGT
Offset 321 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:530
MEMORY_CONFIGURATION::RmtPerTask
UINT32 RmtPerTask
Bit 10 - Rank Margin Tool Per Task. 0 = Disabled, 1 = Enabled.
Definition: MemoryConfig.h:342
MEMORY_CONFIGURATION::Lp5CccConfig
UINT32 Lp5CccConfig
Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel...
Definition: MemoryConfig.h:469
MEMORY_CONFIGURATION::IbeccErrInjMask
UINT64 IbeccErrInjMask
Offset 264 Mask to match against for ECC error injection.
Definition: MemoryConfig.h:500
MEMORY_CONFIGURATION::ForceSingleRank
UINT32 ForceSingleRank
Bit 16 - TRUE means use Rank0 only (in each DIMM): 0=Disable, 1=Enable.
Definition: MemoryConfig.h:439
SA_FUNCTION_CALLS::DebugPrint
SA_DEBUG_PRINT DebugPrint
Offset 152: - Output a string to the debug stream/device.
Definition: MemoryConfig.h:279
MEMORY_CONFIGURATION::tWTR_S
UINT16 tWTR_S
Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:512
MEMORY_CONFIGURATION::RDTC1D
UINT32 RDTC1D
Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this ...
Definition: MemoryConfig.h:379
MEMORY_CONFIGURATION::EnablePwrDnLpddr
UINT32 EnablePwrDnLpddr
Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, 1=BIOS control
Definition: MemoryConfig.h:431
MEMORY_CONFIGURATION::RMTBIT
UINT32 RMTBIT
Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:415
SA_FUNCTION_CALLS::MmioWrite32
SA_MMIO_WRITE_32 MmioWrite32
Offset 48: - Memory Mapped I/O port 32-bit write.
Definition: MemoryConfig.h:253
MEMORY_CONFIGURATION::SaGv
UINT8 SaGv
Offset 110 SA GV: 0=Disabled, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled.
Definition: MemoryConfig.h:456
MEMORY_CONFIGURATION::ProbelessTrace
UINT8 ProbelessTrace
Offset 77 Probeless Trace: 0=Disabled, 1=Enabled
Definition: MemoryConfig.h:358
MEMORY_CONFIGURATION::WRDSUDT
UINT32 WRDSUDT
Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently.
Definition: MemoryConfig.h:400
MEMORY_CONFIGURATION::tRCDtRP
UINT16 tRCDtRP
Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTO...
Definition: MemoryConfig.h:316
MEMORY_CONFIG_NO_CRC::PlatformMemorySize
UINT64 PlatformMemorySize
Offset 248 The minimum platform memory size required to pass control into DXE.
Definition: MemoryConfig.h:565
MEMORY_CONFIGURATION::TXTCODQS
UINT32 TXTCODQS
Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:409
MEMORY_CONFIGURATION::VttTermination
UINT32 VttTermination
Bit 17 - Vtt Termination for Data ODT: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:440
MEMORY_CONFIGURATION::tRFC4
UINT16 tRFC4
Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0...
Definition: MemoryConfig.h:507
MEMORY_CONFIGURATION::PeriodicDcc
UINT32 PeriodicDcc
Bit 22 - Periodic DCC: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:353
MEMORY_CONFIGURATION::ERDMPRTC2D
UINT32 ERDMPRTC2D
Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this s...
Definition: MemoryConfig.h:371
SA_MEMORY_FUNCTIONS::MrcChannelExist
SA_CHANNEL_EXIST MrcChannelExist
Offset 0: - Returns whether Channel is or is not present.
Definition: MemoryConfig.h:293
MEMORY_CONFIGURATION::RefClk
UINT8 RefClk
Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, 0x00 = 133MHz
Definition: MemoryConfig.h:458
SA_FUNCTION_CALLS::SetMemDword
SA_MEMORY_SET_DWORD SetMemDword
Offset 100: - Perform dword initialization operation.
Definition: MemoryConfig.h:266
MEMORY_CONFIGURATION::DIMMDFE
UINT32 DIMMDFE
BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:417
SA_FUNCTION_CALLS::SmbusRead8
SA_SMBUS_READ_8 SmbusRead8
Offset 56: - Smbus 8-bit read.
Definition: MemoryConfig.h:255
MEMORY_CONFIGURATION::EnCmdRate
UINT8 EnCmdRate
Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, 7=3 CMDs, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs,...
Definition: MemoryConfig.h:459
SA_MEMORY_FUNCTIONS::ShiftPiCommandTrain
SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain
Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
Definition: MemoryConfig.h:297
MEMORY_CONFIGURATION::ExtendedBankHashing
UINT8 ExtendedBankHashing
Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; 1 = Enabled
Definition: MemoryConfig.h:494
MEMORY_CONFIGURATION::FreqLimitMixedConfig
UINT16 FreqLimitMixedConfig
Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config....
Definition: MemoryConfig.h:518
SPD_DATA_BUFFER
SPD Data Buffer.
Definition: MemoryConfig.h:132
MEMORY_CONFIGURATION::RCVENC1D
UINT32 RCVENC1D
Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to...
Definition: MemoryConfig.h:398
SA_MMIO_WRITE_8
UINT8(* SA_MMIO_WRITE_8)(UINTN Address, UINT8 Value)
Memory Mapped I/O port 8-bit write.
Definition: MemoryConfig.h:190
SA_FUNCTION_CALLS::MrcDramReset
SA_MRC_DRAM_RESET MrcDramReset
Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
Definition: MemoryConfig.h:284
SA_ADDRESS_DECODE::Dimm
UINT8 Dimm
Offset 2 Zero based DIMM number.
Definition: MemoryConfig.h:172
MEMORY_CONFIG_NO_CRC::MrcCall
SA_MEMORY_FUNCTIONS MrcCall
Offset 212 Function calls into the MRC.
Definition: MemoryConfig.h:561
MEMORY_CONFIG_NO_CRC::MemTestOnWarmBoot
UINT8 MemTestOnWarmBoot
Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, 1=Enabled
Definition: MemoryConfig.h:578
SA_FUNCTION_CALLS::RightShift64
SA_RIGHT_SHIFT_64 RightShift64
Offset 108: - Right shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:268
SA_CHANGE_MARGIN
UINT32(* SA_CHANGE_MARGIN)(VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam)
Change the margin.
Definition: MemoryConfig.h:224
MEMORY_CONFIGURATION::RDEQT
UINT32 RDEQT
Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting...
Definition: MemoryConfig.h:385
MEMORY_CONFIGURATION::RealtimeMemoryFrequency
UINT8 RealtimeMemoryFrequency
Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an X...
Definition: MemoryConfig.h:497
SPDProfileMax
@ SPDProfileMax
Ensures SA_SPD is UINT8.
Definition: MemoryConfig.h:115
MEMORY_CONFIGURATION::PerBankRefresh
BOOLEAN PerBankRefresh
Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that supp...
Definition: MemoryConfig.h:455
MEMORY_CONFIGURATION::WriteThreshold
UINT8 WriteThreshold
Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asse...
Definition: MemoryConfig.h:486
MEMORY_CONFIGURATION::Ibecc
UINT32 Ibecc
Bit 15 - In-band ECC: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:347
MEMORY_CONFIGURATION::DCC
UINT32 DCC
Training Algorithms 2 Offset 88.
Definition: MemoryConfig.h:402
MEMORY_CONFIGURATION::EnablePwrDn
UINT32 EnablePwrDn
Bit 7 - Enable Power Down control for DDR: 0=PCODE control, 1=BIOS control
Definition: MemoryConfig.h:430
MEMORY_CONFIGURATION::CMDVC
UINT32 CMDVC
Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this se...
Definition: MemoryConfig.h:391
XMP_USER_PROFILE_4
@ XMP_USER_PROFILE_4
XMP enthusiast settings: XMP user profile #4.
Definition: MemoryConfig.h:113
SPD_OFFSET_TABLE::End
UINT16 End
Offset 2.
Definition: MemoryConfig.h:160
MEMORY_CONFIGURATION::MrcTimeMeasure
UINT32 MrcTimeMeasure
Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: 0=Disable,...
Definition: MemoryConfig.h:423
SA_FUNCTION_CALLS::GetCpuTime
SA_GET_CPU_TIME GetCpuTime
Offset 84: - The current CPU time in milliseconds.
Definition: MemoryConfig.h:262
MEMORY_CONFIGURATION::RDTC2D
UINT32 RDTC2D
Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this ...
Definition: MemoryConfig.h:388
MEMORY_CONFIGURATION::DynamicMemoryBoost
UINT8 DynamicMemoryBoost
Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Pr...
Definition: MemoryConfig.h:495
MEMORY_CONFIGURATION::tFAW
UINT16 tFAW
Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:323
SA_FUNCTION_CALLS::DebugHook
SA_DEBUG_HOOK DebugHook
Offset 148: - Typically used to display to the I/O port 80h.
Definition: MemoryConfig.h:278
SA_FUNCTION_CALLS::IoRead16
SA_IO_READ_16 IoRead16
Offset 4: - CPU I/O port 16-bit read.
Definition: MemoryConfig.h:242
MEMORY_CONFIGURATION::RDVC2D
UINT32 RDVC2D
Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this...
Definition: MemoryConfig.h:390
MEMORY_CONFIGURATION::GearRatio
UINT8 GearRatio
Offset 130 Gear mode when SAGV is disabled: 0=Auto, 1 - Gear1, 2 - Gear2, 4 - Gear4.
Definition: MemoryConfig.h:472
MEMORY_CONFIGURATION::PDA
UINT32 PDA
BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting f...
Definition: MemoryConfig.h:416
SA_SET_MEMORY_VDD
UINT32(* SA_SET_MEMORY_VDD)(VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value)
Set the memory voltage (VDD) to the given value.
Definition: MemoryConfig.h:217
SA_SHIFT_PI_COMMAND_TRAIN
VOID(* SA_SHIFT_PI_COMMAND_TRAIN)(VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost)
Move CMD/CTL/CLK/CKE PIs during training.
Definition: MemoryConfig.h:226
MEMORY_CONFIGURATION::DqPinsInterleaved
UINT32 DqPinsInterleaved
Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: 0=Disable,...
Definition: MemoryConfig.h:425
SA_MEMORY_RCOMP::RcompResistor
UINT16 RcompResistor
Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms.
Definition: MemoryConfig.h:150
MEMORY_CONFIG_NO_CRC::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: MemoryConfig.h:559
SA_MEMORY_SET_DWORD
VOID *(* SA_MEMORY_SET_DWORD)(VOID *Buffer, UINTN NumDwords, UINT32 Value)
Perform dword initialization operation.
Definition: MemoryConfig.h:205
MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_16GB
UINT16 FreqLimitMixedConfig_1R1R_16GB
Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one cha...
Definition: MemoryConfig.h:537
SA_IO_WRITE_32
UINT32(* SA_IO_WRITE_32)(UINTN IoAddress, UINT32 Value)
CPU I/O port 32-bit write.
Definition: MemoryConfig.h:185
SA_CHANNEL_EXIST
UINT8(* SA_CHANNEL_EXIST)(VOID *Outputs, UINT8 Channel)
Returns whether Channel is or is not present.
Definition: MemoryConfig.h:221
MEMORY_CONFIGURATION::Ratio
UINT8 Ratio
Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. 0 = Auto
Definition: MemoryConfig.h:357
SA_GET_RANDOM_NUMBER
BOOLEAN(* SA_GET_RANDOM_NUMBER)(UINT32 *Rand)
Get the next random 32-bit number.
Definition: MemoryConfig.h:213
MEMORY_CONFIGURATION::SagvHeuristicsUpControl
UINT8 SagvHeuristicsUpControl
Offset 324 Sagv duration in ms before heuristics up: 1 , 50=Maximum, default 1ms.
Definition: MemoryConfig.h:533
MEMORY_CONFIGURATION::PowerDownMode
UINT8 PowerDownMode
Offset 119 CKE Power Down Mode: 0xFF=AUTO, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode.
Definition: MemoryConfig.h:465
MEMORY_CONFIGURATION::ReservedBits2
UINT32 ReservedBits2
Bits 19:31 - Reserved.
Definition: MemoryConfig.h:421
MEMORY_CONFIGURATION::RhSelect
UINT32 RhSelect
Bit 22-23 - RH Select: 0=Disable, 1=RFM, 2=pTRR.
Definition: MemoryConfig.h:445
MEMORY_CONFIGURATION::tRRD
UINT16 tRRD
Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:320
SA_FUNCTION_CALLS::LeftShift64
SA_LEFT_SHIFT_64 LeftShift64
Offset 104: - Left shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:267
SA_FUNCTION_CALLS::IoWrite8
SA_IO_WRITE_8 IoWrite8
Offset 12: - CPU I/O port 8-bit write.
Definition: MemoryConfig.h:244
MEMORY_CONFIGURATION::ExitOnFailure
UINT32 ExitOnFailure
Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, 1=Enable
Definition: MemoryConfig.h:442
MEMORY_CONFIG_NO_CRC
Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detect...
Definition: MemoryConfig.h:558
MEMORY_CONFIGURATION::ThrtCkeMinTmrLpddr
UINT8 ThrtCkeMinTmrLpddr
Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default
Definition: MemoryConfig.h:454
MEMORY_CONFIGURATION::PwdwnIdleCounter
UINT8 PwdwnIdleCounter
Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, 0x80=0x80 DCLK
Definition: MemoryConfig.h:466
MEMORY_CONFIGURATION::MsHashInterleaveBit
UINT8 MsHashInterleaveBit
Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9.
Definition: MemoryConfig.h:471
MEMORY_CONFIGURATION::tCWL
UINT16 tCWL
Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:324
SA_DELAY_NS
VOID(* SA_DELAY_NS)(VOID *GlobalData, UINT32 DelayNs)
Delay (stall) for the given amount of nanoseconds.
Definition: MemoryConfig.h:233
MEMORY_CONFIGURATION::LCT
UINT32 LCT
Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from...
Definition: MemoryConfig.h:392
SA_FUNCTION_CALLS::IoWrite16
SA_IO_WRITE_16 IoWrite16
Offset 16: - CPU I/O port 16-bit write.
Definition: MemoryConfig.h:245
SA_FUNCTION_CALLS::IoWrite32
SA_IO_WRITE_32 IoWrite32
Offset 20: - CPU I/O port 32-bit write.
Definition: MemoryConfig.h:246
MEMORY_CONFIGURATION::ForceSingleSubchannel
UINT32 ForceSingleSubchannel
Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): 0=Disable, 1=Enable.
Definition: MemoryConfig.h:337
MEMORY_CONFIGURATION::LpDqsOscEn
UINT32 LpDqsOscEn
Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, 1=Enable
Definition: MemoryConfig.h:341
MEMORY_CONFIGURATION::MobilePlatform
UINT32 MobilePlatform
Bit 14 - Memory controller device id indicates: TRUE if mobile, FALSE if not. Note: This will be auto...
Definition: MemoryConfig.h:437
MEMORY_CONFIGURATION::RMC
UINT32 RMC
Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from ...
Definition: MemoryConfig.h:399
SA_FUNCTION_CALLS::IoRead32
SA_IO_READ_32 IoRead32
Offset 8: - CPU I/O port 32-bit read.
Definition: MemoryConfig.h:243
MEMORY_CONFIGURATION::MarginLimitL2
UINT16 MarginLimitL2
Offset 240 Margin limit check L2 threshold: 100=Default
Definition: MemoryConfig.h:489
MEMORY_CONFIGURATION::AutoSelfRefreshSupport
UINT32 AutoSelfRefreshSupport
Bit 12 - FALSE = No auto self refresh support, TRUE = auto self refresh support
Definition: MemoryConfig.h:435
MEMORY_CONFIGURATION::DdrFreqLimit
UINT16 DdrFreqLimit
Offset 104 Memory Frequency limit: 0 = Auto, or memory speed value in MT/s: 1067, 1333,...
Definition: MemoryConfig.h:451
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
MEMORY_CONFIGURATION::ReuseAdlSDdr5Board
UINT32 ReuseAdlSDdr5Board
Bit 21 - Indicate whether adl ddr5 board is reused.
Definition: MemoryConfig.h:352
SA_FUNCTION_CALLS::GetSpdData
SA_GET_SPD_DATA GetSpdData
Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to t...
Definition: MemoryConfig.h:271
SA_MMIO_READ_16
UINT16(* SA_MMIO_READ_16)(UINTN Address)
Memory Mapped I/O port 16-bit read.
Definition: MemoryConfig.h:187
MEMORY_CONFIGURATION::SmramMask
UINT8 SmramMask
Offset 79 Reserved memory ranges for SMRAM.
Definition: MemoryConfig.h:365
MEMORY_CONFIGURATION::tCCD_L
UINT16 tCCD_L
Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:511
SA_DEBUG_PRINT
VOID(* SA_DEBUG_PRINT)(VOID *String)
Output a string to the debug stream/device.
Definition: MemoryConfig.h:223
MEMORY_CONFIGURATION::PVTTDNLP
UINT32 PVTTDNLP
Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:412
SA_GET_SPD_DATA
BOOLEAN(* SA_GET_SPD_DATA)(SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize)
Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data struct...
Definition: MemoryConfig.h:210
SA_FUNCTION_CALLS::GetPciDeviceAddress
SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress
Offset 72: - Get PCI device address.
Definition: MemoryConfig.h:259
SA_SMBUS_READ_8
UINT8(* SA_SMBUS_READ_8)(UINTN Address, RETURN_STATUS *Status)
Smbus 8-bit read.
Definition: MemoryConfig.h:194
SPD_OFFSET_TABLE::Start
UINT16 Start
Offset 0.
Definition: MemoryConfig.h:159
SA_FUNCTION_CALLS::GetRtcCmos
SA_GET_RTC_CMOS GetRtcCmos
Offset 156: - Get the current value of the specified RTC CMOS location.
Definition: MemoryConfig.h:280
MEMORY_CONFIGURATION::LpddrRttCa
UINT8 LpddrRttCa
Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto.
Definition: MemoryConfig.h:491
MEMORY_CONFIGURATION::SafeMode
UINT32 SafeMode
Bit 12 - Define if safe mode is enabled for MC/IO.
Definition: MemoryConfig.h:344
MEMORY_CONFIGURATION::Lp5BankMode
UINT8 Lp5BankMode
Offset 337 LP5 Bank Mode.
Definition: MemoryConfig.h:550
SA_SET_MEMORY_PMIC_VOLTAGE
UINT32(* SA_SET_MEMORY_PMIC_VOLTAGE)(VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp)
Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
Definition: MemoryConfig.h:218
MEMORY_CONFIGURATION::RemapEnable
UINT32 RemapEnable
Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable,...
Definition: MemoryConfig.h:334
SA_MEMORY_FUNCTIONS::MrcUpdateVref
SA_UPDATE_VREF MrcUpdateVref
Offset 20: - Update the Vref value and wait until it is stable.
Definition: MemoryConfig.h:298
MEMORY_CONFIGURATION::EccErrInjCount
UINT32 EccErrInjCount
Offset 312 Number of transactions between ECC error injection.
Definition: MemoryConfig.h:515
SA_DEBUG_HOOK
VOID(* SA_DEBUG_HOOK)(VOID *GlobalData, UINT16 DisplayDebugNumber)
Typically used to display to the I/O port 80h.
Definition: MemoryConfig.h:220
SA_SMBUS_WRITE_16
UINT16(* SA_SMBUS_WRITE_16)(UINTN Address, UINT16 Value, RETURN_STATUS *Status)
Smbus 16-bit write.
Definition: MemoryConfig.h:197
MEMORY_CONFIGURATION::MrcFastBoot
UINT32 MrcFastBoot
Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, 1=Enable
Definition: MemoryConfig.h:424
SA_GET_PCI_DEVICE_ADDRESS
UINT32(* SA_GET_PCI_DEVICE_ADDRESS)(UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI device address.
Definition: MemoryConfig.h:198
MEMORY_CONFIGURATION::ChHashOverride
UINT32 ChHashOverride
Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically t...
Definition: MemoryConfig.h:349
SA_FUNCTION_CALLS::SetMemWord
SA_MEMORY_SET_WORD SetMemWord
Offset 96: - Perform word initialization operation.
Definition: MemoryConfig.h:265
MEMORY_CONFIGURATION::ChHashEnable
UINT32 ChHashEnable
Bit 6 - Channel Hash Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:429
SA_FUNCTION_CALLS::GetMemoryVdd
SA_GET_MEMORY_VDD GetMemoryVdd
Offset 136: - Get the current memory voltage (VDD).
Definition: MemoryConfig.h:275
MEMORY_CONFIGURATION::CmdMirror
UINT8 CmdMirror
Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel...
Definition: MemoryConfig.h:484
MEMORY_CONFIGURATION::Write0
UINT32 Write0
Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, 1=Enable
Definition: MemoryConfig.h:351
MEMORY_CONFIGURATION::tRTP
UINT16 tRTP
Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:322
SA_SMBUS_READ_16
UINT16(* SA_SMBUS_READ_16)(UINTN Address, RETURN_STATUS *Status)
Smbus 16-bit read.
Definition: MemoryConfig.h:195
MEMORY_CONFIGURATION::RetrainOnFastFail
UINT8 RetrainOnFastFail
Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled,...
Definition: MemoryConfig.h:464
SA_ADDRESS_DECODE
SA memory address decode.
Definition: MemoryConfig.h:169
SA_MRC_RETURN_FROM_SMC
VOID(* SA_MRC_RETURN_FROM_SMC)(VOID *GlobalData, UINT32 MrcStatus)
Hook function after returning from MrcStartMemoryConfiguration()
Definition: MemoryConfig.h:231
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
MEMORY_CONFIGURATION::RDVC1D
UINT32 RDVC1D
Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:403
MEMORY_CONFIGURATION::Lfsr0Mask
UINT8 Lfsr0Mask
Offset 233 RH pTRR LFSR0 Mask.
Definition: MemoryConfig.h:482
MEMORY_CONFIGURATION::EpgEnable
UINT8 EpgEnable
Offset 115 Enable Energy Performance Gain.
Definition: MemoryConfig.h:461
MEMORY_CONFIGURATION::LpddrRttWr
UINT8 LpddrRttWr
Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto.
Definition: MemoryConfig.h:490
SA_FUNCTION_CALLS::MrcReturnFromSmc
SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc
Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
Definition: MemoryConfig.h:283
MEM_CFG_MAX_CONTROLLERS
#define MEM_CFG_MAX_CONTROLLERS
Memory SubSystem Definitions.
Definition: MemoryConfig.h:85
MEMORY_CONFIGURATION::RDMPRT
UINT32 RDMPRT
Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the ...
Definition: MemoryConfig.h:372
MEMORY_CONFIGURATION::CMDSR
UINT32 CMDSR
Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:406
MEMORY_CONFIGURATION::Idd3p
UINT16 Idd3p
Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
Definition: MemoryConfig.h:330
SA_MEMORY_FUNCTIONS::MrcPrintf
SA_PRINTF MrcPrintf
Offset 4: - Print to output stream/device.
Definition: MemoryConfig.h:294
SA_CHECKPOINT
UINT32(* SA_CHECKPOINT)(VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch)
Check point that is called at various points in the MRC.
Definition: MemoryConfig.h:219
MEMORY_CONFIGURATION::RefreshHpWm
UINT32 RefreshHpWm
Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
Definition: MemoryConfig.h:447
SpdBootModeMax
@ SpdBootModeMax
Delimiter.
Definition: MemoryConfig.h:126
MEMORY_CONFIGURATION::FirstDimmBitMask
UINT8 FirstDimmBitMask
Offset 318 Defines which DIMM should be populated first on a 2DPC board.
Definition: MemoryConfig.h:519
MEMORY_CONFIGURATION::MsHashEnable
UINT32 MsHashEnable
Bit 13 - Controller Hash Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:345
MEMORY_CONFIGURATION::tRAS
UINT16 tRAS
Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:317
MEMORY_CONFIGURATION::tRFC2
UINT16 tRFC2
Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0...
Definition: MemoryConfig.h:506
SA_MEMORY_SET_BYTE
VOID *(* SA_MEMORY_SET_BYTE)(VOID *Buffer, UINTN NumBytes, UINT8 Value)
Perform byte initialization operation.
Definition: MemoryConfig.h:203
MEMORY_CONFIGURATION::VppVoltage
UINT16 VppVoltage
Offset 246 DRAM voltage (Vpp) in millivolts: 0=Platform Default (no override), 1800=1....
Definition: MemoryConfig.h:493
MEMORY_CONFIGURATION::TAT
UINT32 TAT
Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting ...
Definition: MemoryConfig.h:394
MEMORY_CONFIGURATION::tWTR_L
UINT16 tWTR_L
Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:510
SA_MEMORY_FUNCTIONS::MrcSignExtend
SA_SIGN_EXTEND MrcSignExtend
Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
Definition: MemoryConfig.h:296
MEMORY_CONFIGURATION::SOT
UINT32 SOT
Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting f...
Definition: MemoryConfig.h:370
MEMORY_CONFIG_NO_CRC::RcompData
SA_MEMORY_RCOMP * RcompData
Offset 244 DDR RCOMP resistors and target values.
Definition: MemoryConfig.h:564
XMP_USER_PROFILE_5
@ XMP_USER_PROFILE_5
XMP enthusiast settings: XMP user profile #5.
Definition: MemoryConfig.h:114
CUSTOM_PROFILE
@ CUSTOM_PROFILE
XMP enthusiast settings: User specifies various override values.
Definition: MemoryConfig.h:109
MEMORY_CONFIGURATION::SimicsFlag
UINT32 SimicsFlag
Bit 6 - Option to Enable SIMICS: 0=Disable, 1=Enable
Definition: MemoryConfig.h:338
MEMORY_CONFIGURATION::VddVoltage
UINT16 VddVoltage
Offset 58 DRAM voltage (Vdd) in millivolts: 0=Platform Default (no override), 1200=1....
Definition: MemoryConfig.h:328
MEMORY_CONFIGURATION::PprEnable
UINT8 PprEnable
Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR.
Definition: MemoryConfig.h:487
MEMORY_CONFIG_NO_CRC::SaCall
SA_FUNCTION_CALLS SaCall
Offset 28 Function calls into the SA.
Definition: MemoryConfig.h:560
SA_FUNCTION_CALLS
Function calls into the SA.
Definition: MemoryConfig.h:240
SA_ADDRESS_DECODE::Controller
UINT8 Controller
Offset 0 Zero based Controller number.
Definition: MemoryConfig.h:170
MEMORY_CONFIGURATION::ChHashMask
UINT16 ChHashMask
Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum),...
Definition: MemoryConfig.h:450
MEMORY_CONFIGURATION::DebugValue
UINT32 DebugValue
Offset 276 Debug Value for general use.
Definition: MemoryConfig.h:504
SA_PRINTF
INT32(* SA_PRINTF)(VOID *Debug, UINT32 Level, char *Format,...)
Print to output stream/device.
Definition: MemoryConfig.h:222
MEMORY_CONFIGURATION::WRDS
UINT32 WRDS
BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:420
MEMORY_CONFIGURATION::TrainTrace
UINT32 TrainTrace
Bit 11 - Trained state tracing debug. 0 = Disabled, 1 = Enabled.
Definition: MemoryConfig.h:343
MEMORY_CONFIGURATION::RDODTT
UINT32 RDODTT
Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the...
Definition: MemoryConfig.h:384
MEMORY_CONFIGURATION::ALIASCHK
UINT32 ALIASCHK
Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, 1=Enable
Definition: MemoryConfig.h:397
MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB
UINT16 FreqLimitMixedConfig_1R1R_8GB
Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channe...
Definition: MemoryConfig.h:535
MEMORY_CONFIGURATION::ThrtCkeMinTmr
UINT8 ThrtCkeMinTmr
Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, 0x00=Default
Definition: MemoryConfig.h:453
MEMORY_CONFIGURATION::Lfsr1Mask
UINT8 Lfsr1Mask
Offset 234 RH pTRR LFSR1 Mask.
Definition: MemoryConfig.h:483
MEMORY_CONFIGURATION
Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection.
Definition: MemoryConfig.h:307
SA_MSR_READ_64
UINT64(* SA_MSR_READ_64)(UINT32 Location)
Get the current value of the specified MSR location.
Definition: MemoryConfig.h:229
SA_RIGHT_SHIFT_64
UINT64(* SA_RIGHT_SHIFT_64)(UINT64 Data, UINTN NumBits)
Right shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:207
MEMORY_CONFIGURATION::IbeccErrInjControl
UINT8 IbeccErrInjControl
Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Add...
Definition: MemoryConfig.h:496
MEMORY_CONFIGURATION::EnhancedInterleave
UINT32 EnhancedInterleave
Bit 4 - Enhanced Interleave Mode: 0=Disable, 1=Enable
Definition: MemoryConfig.h:427
SA_FUNCTION_CALLS::GetRandomNumber
SA_GET_RANDOM_NUMBER GetRandomNumber
Offset 124: - Get the next random 32-bit number.
Definition: MemoryConfig.h:272
MEMORY_CONFIGURATION::BClkFrequency
UINT32 BClkFrequency
Offset 80 Base reference clock value, in Hertz: 100000000 = 100Hz, 125000000=125Hz,...
Definition: MemoryConfig.h:366
MEMORY_CONFIGURATION::DIMMODTT
UINT32 DIMMODTT
Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the...
Definition: MemoryConfig.h:380
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
MEMORY_CONFIGURATION::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: MemoryConfig.h:308
MEMORY_CONFIGURATION::DIMMODTCA
UINT32 DIMMODTCA
Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:408
MEMORY_CONFIGURATION::FreqLimitMixedConfig_2R2R
UINT16 FreqLimitMixedConfig_2R2R
Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel...
Definition: MemoryConfig.h:541
MEMORY_CONFIG_NO_CRC::CleanMemory
UINT32 CleanMemory
Offset 256 Ask MRC to clear memory content: FALSE=Do not Clear Memory; TRUE=Clear Memory.
Definition: MemoryConfig.h:566
SA_IO_WRITE_8
UINT8(* SA_IO_WRITE_8)(UINTN IoAddress, UINT8 Value)
CPU I/O port 8-bit write.
Definition: MemoryConfig.h:183
SA_GET_MEMORY_VDD
UINT32(* SA_GET_MEMORY_VDD)(VOID *GlobalData, UINT32 DefaultVdd)
Get the current memory voltage (VDD).
Definition: MemoryConfig.h:216
MEMORY_CONFIG_NO_CRC::DqDqsMap
SA_MEMORY_DQDQS_MAPPING * DqDqsMap
Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
Definition: MemoryConfig.h:563
SPD_BOOT_MODE
SPD_BOOT_MODE
Define the boot modes used by the SPD read function.
Definition: MemoryConfig.h:121
MEMORY_CONFIGURATION::LctCmdEyeWidth
UINT16 LctCmdEyeWidth
Offset 334 LCT Command eyewidth.
Definition: MemoryConfig.h:543
MEMORY_CONFIGURATION::SpdProfileSelected
UINT8 SpdProfileSelected
Offset 31 SPD XMP profile selection - for XMP supported DIMM: 0=Default DIMM profile,...
Definition: MemoryConfig.h:312
SA_MMIO_READ_64
UINT64(* SA_MMIO_READ_64)(UINTN Address)
Memory Mapped I/O port 64-bit read.
Definition: MemoryConfig.h:189
MEMORY_CONFIGURATION::WRVC2D
UINT32 WRVC2D
Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change thi...
Definition: MemoryConfig.h:389
SA_FUNCTION_CALLS::GetRtcTime
SA_GET_RTC_TIME GetRtcTime
Offset 80: - Get the current time value.
Definition: MemoryConfig.h:261
MEMORY_CONFIGURATION::McRefreshRate
UINT8 McRefreshRate
Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4...
Definition: MemoryConfig.h:502
SA_FUNCTION_CALLS::GetPcieDeviceAddress
SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress
Offset 76: - Get PCI express device address.
Definition: MemoryConfig.h:260
SA_MMIO_READ_8
UINT8(* SA_MMIO_READ_8)(UINTN Address)
Memory Mapped I/O port 8-bit read.
Definition: MemoryConfig.h:186
SA_DIV_U64_U64
UINT64(* SA_DIV_U64_U64)(UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder)
Divide a 64-bit data value by a 64-bit data value.
Definition: MemoryConfig.h:209
SA_FUNCTION_CALLS::MultU64x32
SA_MULT_U64_U32 MultU64x32
Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
Definition: MemoryConfig.h:269
XMP_PROFILE_2
@ XMP_PROFILE_2
XMP enthusiast settings: XMP profile #2.
Definition: MemoryConfig.h:111
MEMORY_CONFIGURATION::JWRL
UINT32 JWRL
Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setti...
Definition: MemoryConfig.h:374
SA_FUNCTION_CALLS::SetMemoryPmicVoltage
SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage
Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
Definition: MemoryConfig.h:286
MEMORY_CONFIGURATION::ScramblerSupport
UINT32 ScramblerSupport
Bit 3 - Memory scrambler support: 0=Disable, 1=Enable
Definition: MemoryConfig.h:335
SA_FUNCTION_CALLS::CpuMailboxWrite
SA_CPU_MAILBOX_WRITE CpuMailboxWrite
Offset 132: - Perform a CPU mailbox write.
Definition: MemoryConfig.h:274
SA_MMIO_WRITE_64
UINT64(* SA_MMIO_WRITE_64)(UINTN Address, UINT64 Value)
Memory Mapped I/O port 64-bit write.
Definition: MemoryConfig.h:193
MEMORY_CONFIGURATION::EccSupport
UINT32 EccSupport
Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, 1=Enable
Definition: MemoryConfig.h:332
SA_IO_READ_32
UINT32(* SA_IO_READ_32)(UINTN IoAddress)
CPU I/O port 32-bit read.
Definition: MemoryConfig.h:182
MEMORY_CONFIGURATION::tREFI
UINT16 tREFI
Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=...
Definition: MemoryConfig.h:325
SA_ADDRESS_DECODE::BankGroup
UINT8 BankGroup
Offset 4 Zero based Bank Group number.
Definition: MemoryConfig.h:174
MEMORY_CONFIGURATION::Size
UINT16 Size
Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
Definition: MemoryConfig.h:309
MEMORY_CONFIGURATION::WRDSEQT
UINT32 WRDSEQT
Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended t...
Definition: MemoryConfig.h:382
SA_SPD
SA_SPD
SA SPD profile selections.
Definition: MemoryConfig.h:107
MEMORY_CONFIGURATION::MarginLimitCheck
UINT8 MarginLimitCheck
Offset 239 Margin limit check enable: 0=Disable, 1=L1 only, 2=L2 only, 3=Both L1 and L2.
Definition: MemoryConfig.h:488
SA_FUNCTION_CALLS::CpuMailboxRead
SA_CPU_MAILBOX_READ CpuMailboxRead
Offset 128: - Perform a CPU mailbox read.
Definition: MemoryConfig.h:273
MEMORY_CONFIGURATION::SrefCfgIdleTmr
UINT16 SrefCfgIdleTmr
Offset 100 Self Refresh idle timer: 512=Minimal, 65535=Maximum.
Definition: MemoryConfig.h:449
MEMORY_CONFIGURATION::UserBudgetEnable
UINT8 UserBudgetEnable
Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable,...
Definition: MemoryConfig.h:463
SA_SIGN_EXTEND
UINT8(* SA_SIGN_EXTEND)(UINT8 Value, UINT8 OldMsb, UINT8 NewMsb)
Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
Definition: MemoryConfig.h:225
MEMORY_CONFIGURATION::EccDftEn
UINT32 EccDftEn
Bit 19 - ECC DFT support option.
Definition: MemoryConfig.h:350
MEMORY_CONFIGURATION::WeaklockEn
UINT32 WeaklockEn
Bit 5 - Weak Lock Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:428
MEMORY_CONFIGURATION::MaxRttWr
UINT8 MaxRttWr
Offset 106 Maximum DIMM RTT_WR to use in power training: 0=ODT Off, 1 = 120 ohms.
Definition: MemoryConfig.h:452
MEMORY_CONFIGURATION::NewFeatureEnable2
UINT32 NewFeatureEnable2
Bit 21 - Generic enable knob for new feature set 2 0: Disable ; 1: Enable.
Definition: MemoryConfig.h:444
MEMORY_CONFIGURATION::SagvSwitchFactorIA
UINT8 SagvSwitchFactorIA
Offset 320 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:529
SA_IO_READ_16
UINT16(* SA_IO_READ_16)(UINTN IoAddress)
CPU I/O port 16-bit read.
Definition: MemoryConfig.h:181
MEMORY_CONFIGURATION::PciData
UINT16 PciData
Offset 56 Pci data register address: 0xCFC=Default
Definition: MemoryConfig.h:327
MEMORY_CONFIGURATION::ExtTemperatureSupport
UINT32 ExtTemperatureSupport
Bit 13 - FALSE = No extended temperature support, TRUE = extended temperature support
Definition: MemoryConfig.h:436
MEMORY_CONFIG_NO_CRC::SpdData
SPD_DATA_BUFFER * SpdData
Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
Definition: MemoryConfig.h:562
SA_ADDRESS_DECODE::Cas
UINT16 Cas
Offset 6 Zero based CAS number.
Definition: MemoryConfig.h:176
XMP_PROFILE_1
@ XMP_PROFILE_1
XMP enthusiast settings: XMP profile #1.
Definition: MemoryConfig.h:110
SA_MSR_WRITE_64
UINT64(* SA_MSR_WRITE_64)(UINT32 Location, UINT64 Data)
Set the current value of the specified MSR location.
Definition: MemoryConfig.h:230
SA_FUNCTION_CALLS::MmioRead8
SA_MMIO_READ_8 MmioRead8
Offset 24: - Memory Mapped I/O port 8-bit read.
Definition: MemoryConfig.h:247
MEMORY_CONFIGURATION::RMT
UINT32 RMT
Bit 26 - Enable/Disable Rank Margin Tool function: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:395
MEMORY_CONFIGURATION::UserBd
UINT8 UserBd
Offset 319 MrcBoardType 1 - Desktop 1DPC 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated ...
Definition: MemoryConfig.h:523
SA_MEMORY_FUNCTIONS
Function calls into the MRC.
Definition: MemoryConfig.h:292
SA_FUNCTION_CALLS::MrcDelayNs
SA_DELAY_NS MrcDelayNs
Offset 176 - Delay (stall) for the given amount of nanoseconds.
Definition: MemoryConfig.h:285
SA_ADDRESS_DECODE::Ras
UINT32 Ras
Offset 8 Zero based RAS number.
Definition: MemoryConfig.h:177
MEMORY_CONFIGURATION::Idd3n
UINT16 Idd3n
Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
Definition: MemoryConfig.h:329
MEMORY_CONFIGURATION::McRefresh2X
UINT8 McRefresh2X
Offset 232 Deprecated from revision 19, use McRefreshRate instead.
Definition: MemoryConfig.h:481
SA_MEMORY_SET_WORD
VOID *(* SA_MEMORY_SET_WORD)(VOID *Buffer, UINTN NumWords, UINT16 Value)
Perform word initialization operation.
Definition: MemoryConfig.h:204
MEMORY_CONFIGURATION::ERDTC2D
UINT32 ERDTC2D
Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change th...
Definition: MemoryConfig.h:376
SA_CPU_MAILBOX_WRITE
EFI_STATUS(* SA_CPU_MAILBOX_WRITE)(UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status)
Perform a CPU mailbox write.
Definition: MemoryConfig.h:215
SA_MRC_DRAM_RESET
VOID(* SA_MRC_DRAM_RESET)(UINT32 PciEBaseAddress, UINT32 ResetValue)
Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
Definition: MemoryConfig.h:232
MEMORY_CONFIGURATION::tCL
UINT16 tCL
Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AU...
Definition: MemoryConfig.h:315
SA_MULT_U64_U32
UINT64(* SA_MULT_U64_U32)(UINT64 Multiplicand, UINT32 Multiplier)
Multiply a 64-bit data value by a 32-bit data value.
Definition: MemoryConfig.h:208
MEMORY_CONFIGURATION::FirstDimmBitMaskEcc
UINT8 FirstDimmBitMaskEcc
Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
Definition: MemoryConfig.h:544
SA_GET_RTC_CMOS
UINT8(* SA_GET_RTC_CMOS)(UINT8 Location)
Get the current value of the specified RTC CMOS location.
Definition: MemoryConfig.h:228
MEMORY_CONFIGURATION::ChHashInterleaveBit
UINT8 ChHashInterleaveBit
Channel Hash Enable.
Definition: MemoryConfig.h:364
MEMORY_CONFIGURATION::ThrtCkeMinDefeat
UINT32 ThrtCkeMinDefeat
Bit 11 - Throttler CKE min defeature: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:434
CONST
#define CONST
Datum is read-only.
Definition: Base.h:268
MEMORY_CONFIGURATION::CMDDSEQ
UINT32 CMDDSEQ
Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:407
MEMORY_CONFIGURATION::VddqVoltage
UINT16 VddqVoltage
Offset 244 DRAM voltage (Vddq) in millivolts: 0=Platform Default (no override), 1200=1....
Definition: MemoryConfig.h:492
MEMORY_CONFIGURATION::RDVREFDC
UINT32 RDVREFDC
Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:413
MEMORY_CONFIGURATION::PciIndex
UINT16 PciIndex
Offset 54 Pci index register address: 0xCF8=Default
Definition: MemoryConfig.h:326
MEMORY_CONFIG_NO_CRC::SerialDebugLevel
UINT8 SerialDebugLevel
Sets the serial debug message level 0x00 = Disabled 0x01 = Errors only 0x02 = Errors and Warnings ...
Definition: MemoryConfig.h:577
MEMORY_CONFIGURATION::EccErrInjAddress
UINT64 EccErrInjAddress
Offset 296 Address to match against for ECC error injection.
Definition: MemoryConfig.h:513
SpdS3
@ SpdS3
S3 resume.
Definition: MemoryConfig.h:124
MEMORY_CONFIGURATION::WRTC2D
UINT32 WRTC2D
Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this...
Definition: MemoryConfig.h:387
SPD_OFFSET_TABLE::BootMode
UINT8 BootMode
Offset 4.
Definition: MemoryConfig.h:161
MEMORY_CONFIGURATION::RefreshPanicWm
UINT32 RefreshPanicWm
Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
Definition: MemoryConfig.h:446
MEMORY_CONFIGURATION::tRRD_S
UINT16 tRRD_S
Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:509
SA_ADDRESS_DECODE::Rank
UINT8 Rank
Offset 3 Zero based Rank number.
Definition: MemoryConfig.h:173
MEMORY_CONFIGURATION::UserThresholdEnable
UINT8 UserThresholdEnable
Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable,...
Definition: MemoryConfig.h:462
MEMORY_CONFIGURATION::MrcSafeConfig
UINT32 MrcSafeConfig
Bit 1 - MRC Safe Mode: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:333
SA_GET_PCIE_DEVICE_ADDRESS
UINT32(* SA_GET_PCIE_DEVICE_ADDRESS)(UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI express device address.
Definition: MemoryConfig.h:199
MEMORY_CONFIGURATION::Force1Dpc
UINT32 Force1Dpc
Bit 15 - TRUE means force one DIMM per channel, FALSE means no limit
Definition: MemoryConfig.h:438
MEMORY_CONFIGURATION::SagvHeuristicsDownControl
UINT8 SagvHeuristicsDownControl
Offset 325 Sagv duration in ms before heuristics down: 1 , 50=Maximum, default 1ms.
Definition: MemoryConfig.h:534
SA_FUNCTION_CALLS::MmioWrite16
SA_MMIO_WRITE_16 MmioWrite16
Offset 44: - Memory Mapped I/O port 16-bit write.
Definition: MemoryConfig.h:252
MEMORY_CONFIGURATION::MEMTST
UINT32 MEMTST
Bit 27 - Enable/Disable Memory Test function: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:396
MEMORY_CONFIGURATION::VddSettleWaitTime
UINT32 VddSettleWaitTime
Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC ...
Definition: MemoryConfig.h:448
SA_MEMORY_DQDQS_MAPPING
DqDqs Mapping.
Definition: MemoryConfig.h:140
SpdFast
@ SpdFast
Fast boot.
Definition: MemoryConfig.h:125
SpdWarm
@ SpdWarm
Warm boot.
Definition: MemoryConfig.h:123
MEMORY_CONFIGURATION::VttCompForVsshi
UINT32 VttCompForVsshi
Bit 18 - Enable/Disable Vtt Comparator For Vsshi: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:441
MEMORY_CONFIGURATION::IbeccErrInjCount
UINT32 IbeccErrInjCount
Offset 252 Number of transactions between ECC error injection.
Definition: MemoryConfig.h:498
MEMORY_CONFIGURATION::tRFCpb
UINT16 tRFCpb
Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:505
MEMORY_CONFIGURATION::NModeSupport
UINT8 NModeSupport
Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: 0=AUTO, 1=1N,...
Definition: MemoryConfig.h:457
SA_MEMORY_FUNCTIONS::MrcChangeMargin
SA_CHANGE_MARGIN MrcChangeMargin
Offset 8: - Change the margin.
Definition: MemoryConfig.h:295
SA_FUNCTION_CALLS::SmbusWrite16
SA_SMBUS_WRITE_16 SmbusWrite16
Offset 68: - Smbus 16-bit write.
Definition: MemoryConfig.h:258
SA_ADDRESS_DECODE::Channel
UINT8 Channel
Offset 1 Zero based Channel number.
Definition: MemoryConfig.h:171
SA_MEMORY_COPY
VOID *(* SA_MEMORY_COPY)(VOID *Destination, CONST VOID *Source, UINTN NumBytes)
Perform byte copy operation.
Definition: MemoryConfig.h:202
MEMORY_CONFIGURATION::RDAPT
UINT32 RDAPT
Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this sett...
Definition: MemoryConfig.h:386
SA_MMIO_WRITE_16
UINT16(* SA_MMIO_WRITE_16)(UINTN Address, UINT16 Value)
Memory Mapped I/O port 16-bit write.
Definition: MemoryConfig.h:191
SA_FUNCTION_CALLS::MmioRead32
SA_MMIO_READ_32 MmioRead32
Offset 32: - Memory Mapped I/O port 32-bit read.
Definition: MemoryConfig.h:249
SA_FUNCTION_CALLS::DivU64x64
SA_DIV_U64_U64 DivU64x64
Offset 116: - Divide a 64-bit data value by a 64-bit data value.
Definition: MemoryConfig.h:270
MEMORY_CONFIGURATION::ECT
UINT32 ECT
Training Algorithms 1 Offset 84.
Definition: MemoryConfig.h:369
MEMORY_CONFIGURATION::SharedZqPin
UINT32 SharedZqPin
Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=Not Shared,...
Definition: MemoryConfig.h:340
MEMORY_CONFIGURATION::LpMode
UINT32 LpMode
Bit 23:24 - LPMode: 0=Auto, 1=Enabled, 2=Disabled, 3=Reserved.
Definition: MemoryConfig.h:354
MEMORY_CONFIGURATION::AllowOppRefBelowWriteThrehold
UINT8 AllowOppRefBelowWriteThrehold
Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
Definition: MemoryConfig.h:485
MEMORY_CONFIGURATION::EccErrInjMask
UINT64 EccErrInjMask
Offset 304 Mask to match against for ECC error injection.
Definition: MemoryConfig.h:514
DEFAULT_SPD
@ DEFAULT_SPD
Standard DIMM profile select.
Definition: MemoryConfig.h:108
MEMORY_CONFIGURATION::SagvSwitchFactorIO
UINT8 SagvSwitchFactorIO
Offset 322 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:531
MEMORY_CONFIGURATION::Refresh2X
UINT8 Refresh2X
Offset 114 Refresh 2x: 0=Disable, 1=Enable for WARM or HOT, 2=Enable for HOT only.
Definition: MemoryConfig.h:460
MEMORY_CONFIGURATION::RsvdO64B25to31
UINT32 RsvdO64B25to31
Bits 25:31 reserved.
Definition: MemoryConfig.h:355
MEMORY_CONFIGURATION::TXTCO
UINT32 TXTCO
Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:404
SA_FUNCTION_CALLS::MmioWrite8
SA_MMIO_WRITE_8 MmioWrite8
Offset 40: - Memory Mapped I/O port 8-bit write.
Definition: MemoryConfig.h:251
MEMORY_CONFIGURATION::tWR
UINT16 tWR
Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AU...
Definition: MemoryConfig.h:318
SA_FUNCTION_CALLS::CopyMem
SA_MEMORY_COPY CopyMem
Offset 88: - Perform byte copy operation.
Definition: MemoryConfig.h:263
MEMORY_CONFIGURATION::tRRD_L
UINT16 tRRD_L
Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:508
MEMORY_CONFIGURATION::CMDDRUD
UINT32 CMDDRUD
Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:410
SA_MMIO_WRITE_32
UINT32(* SA_MMIO_WRITE_32)(UINTN Address, UINT32 Value)
Memory Mapped I/O port 32-bit write.
Definition: MemoryConfig.h:192
SA_FUNCTION_CALLS::WriteMsr64
SA_MSR_WRITE_64 WriteMsr64
Offset 164 - Set the current value of the specified MSR location.
Definition: MemoryConfig.h:282
SA_FUNCTION_CALLS::SmbusRead16
SA_SMBUS_READ_16 SmbusRead16
Offset 60: - Smbus 16-bit read.
Definition: MemoryConfig.h:256
MEMORY_CONFIGURATION::SagvSwitchFactorStall
UINT8 SagvSwitchFactorStall
Offset 323 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:532
SpdCold
@ SpdCold
Cold boot.
Definition: MemoryConfig.h:122
MEMORY_CONFIGURATION::RMTLoopCount
UINT8 RMTLoopCount
Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal,...
Definition: MemoryConfig.h:470
SA_FUNCTION_CALLS::IoRead8
SA_IO_READ_8 IoRead8
Offset 0: - CPU I/O port 8-bit read.
Definition: MemoryConfig.h:241
MEMORY_CONFIGURATION::DisPgCloseIdleTimeout
UINT32 DisPgCloseIdleTimeout
Bit 14 - Disable Page Close Idle Timeout: 0=Enable, 1=Disable
Definition: MemoryConfig.h:346
SA_IO_READ_8
UINT8(* SA_IO_READ_8)(UINTN IoAddress)
CPU I/O port 8-bit read.
Definition: MemoryConfig.h:180
MEMORY_CONFIGURATION::WRSRT
UINT32 WRSRT
Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting fr...
Definition: MemoryConfig.h:383
SA_GET_CPU_TIME
UINT64(* SA_GET_CPU_TIME)(VOID)
The current CPU time in milliseconds.
Definition: MemoryConfig.h:201
MEMORY_CONFIGURATION::EWRTC2D
UINT32 EWRTC2D
Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change t...
Definition: MemoryConfig.h:375
MEMORY_CONFIGURATION::RTL
UINT32 RTL
Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this settin...
Definition: MemoryConfig.h:393
SA_FUNCTION_CALLS::SmbusWrite8
SA_SMBUS_WRITE_8 SmbusWrite8
Offset 64: - Smbus 8-bit write.
Definition: MemoryConfig.h:257
MEMORY_CONFIGURATION::RCVET
UINT32 RCVET
Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting fro...
Definition: MemoryConfig.h:373
SPD_OFFSET_TABLE
SPD Offset Table.
Definition: MemoryConfig.h:158
MRC_MAX_RCOMP_TARGETS
#define MRC_MAX_RCOMP_TARGETS
MEMORY_CONFIGURATION interface definitions.
Definition: MemoryConfig.h:81
MEMORY_CONFIGURATION::IbeccErrInjAddress
UINT64 IbeccErrInjAddress
Offset 256 Address to match against for ECC error injection.
Definition: MemoryConfig.h:499
SA_FUNCTION_CALLS::CheckPoint
SA_CHECKPOINT CheckPoint
Offset 144: - Check point that is called at various points in the MRC.
Definition: MemoryConfig.h:277
SA_ADDRESS_DECODE::Bank
UINT8 Bank
Offset 5 Zero based Bank number.
Definition: MemoryConfig.h:175
XMP_PROFILE_3
@ XMP_PROFILE_3
XMP enthusiast settings: XMP profile #3.
Definition: MemoryConfig.h:112
SA_UPDATE_VREF
VOID(* SA_UPDATE_VREF)(VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait)
Update the Vref value and wait until it is stable.
Definition: MemoryConfig.h:227
SA_FUNCTION_CALLS::MmioRead16
SA_MMIO_READ_16 MmioRead16
Offset 28: - Memory Mapped I/O port 16-bit read.
Definition: MemoryConfig.h:248
SA_FUNCTION_CALLS::ReadMsr64
SA_MSR_READ_64 ReadMsr64
Offset 160: - Get the current value of the specified MSR location.
Definition: MemoryConfig.h:281
MEMORY_CONFIGURATION::ThrtCkeMinDefeatLpddr
UINT32 ThrtCkeMinDefeatLpddr
Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, 1=Enable
Definition: MemoryConfig.h:433
SA_LEFT_SHIFT_64
UINT64(* SA_LEFT_SHIFT_64)(UINT64 Data, UINTN NumBits)
Left shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:206
MEMORY_CONFIGURATION::tWTR
UINT16 tWTR
Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:321
SA_MMIO_READ_32
UINT32(* SA_MMIO_READ_32)(UINTN Address)
Memory Mapped I/O port 32-bit read.
Definition: MemoryConfig.h:188
MEMORY_CONFIGURATION::RankInterleave
UINT32 RankInterleave
Bit 3 - Rank Interleave Mode: 0=Disable, 1=Enable
Definition: MemoryConfig.h:426
SA_SMBUS_WRITE_8
UINT8(* SA_SMBUS_WRITE_8)(UINTN Address, UINT8 Value, RETURN_STATUS *Status)
Smbus 8-bit write.
Definition: MemoryConfig.h:196
MEMORY_CONFIGURATION::TXDQSDCC
UINT32 TXDQSDCC
BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:418
MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB_16GB
UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB
Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one ...
Definition: MemoryConfig.h:539
SA_GET_RTC_TIME
VOID(* SA_GET_RTC_TIME)(UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year)
Get the current time value.
Definition: MemoryConfig.h:200
MEMORY_CONFIGURATION::VDDQT
UINT32 VDDQT
Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:414
MEMORY_CONFIGURATION::MsHashMask
UINT16 MsHashMask
Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum),...
Definition: MemoryConfig.h:468
MEMORY_CONFIGURATION::RefreshWm
UINT8 RefreshWm
Offset 272 Refresh Watermarks, 0 = Low, 1 = High
Definition: MemoryConfig.h:501
MEMORY_CONFIGURATION::HobBufferSize
UINT8 HobBufferSize
Offset 30 Size of HOB buffer for MRC.
Definition: MemoryConfig.h:310
MEMORY_CONFIGURATION::WRVC1D
UINT32 WRVC1D
Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this...
Definition: MemoryConfig.h:378
SA_CPU_MAILBOX_READ
EFI_STATUS(* SA_CPU_MAILBOX_READ)(UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status)
Perform a CPU mailbox read.
Definition: MemoryConfig.h:214
SA_MEMORY_RCOMP
Rcomp Policies.
Definition: MemoryConfig.h:149
MEMORY_CONFIGURATION::CLKTCO
UINT32 CLKTCO
Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:405
MEMORY_CONFIGURATION::VCCDLLBP
UINT32 VCCDLLBP
Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:411
SA_FUNCTION_CALLS::MmioRead64
SA_MMIO_READ_64 MmioRead64
Offset 36: - Memory Mapped I/O port 64-bit read.
Definition: MemoryConfig.h:250
MEMORY_CONFIGURATION::CmdRanksTerminated
UINT8 CmdRanksTerminated
Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating an...
Definition: MemoryConfig.h:467
SA_FUNCTION_CALLS::SetMem
SA_MEMORY_SET_BYTE SetMem
Offset 92: - Perform byte initialization operation.
Definition: MemoryConfig.h:264
MEMORY_CONFIGURATION::Ddr4OneDpc
UINT8 Ddr4OneDpc
Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only,...
Definition: MemoryConfig.h:473
MEMORY_CONFIGURATION::NewFeatureEnable1
UINT32 NewFeatureEnable1
Bit 20 - Generic enable knob for new feature set 1 0: Disable ; 1: Enable.
Definition: MemoryConfig.h:443
SA_FUNCTION_CALLS::SetMemoryVdd
SA_SET_MEMORY_VDD SetMemoryVdd
Offset 140: - Set the memory voltage (VDD) to the given value.
Definition: MemoryConfig.h:276
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MePeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
Classes
MePeiConfig.h File Reference

ME config block for PEI phase. More...

Go to the source code of this file.

Classes

struct | ME_PEI_PREMEM_CONFIG
ME Pei Pre-Memory Configuration Structure. More...
struct | ME_PEI_CONFIG
ME Pei Post-Memory Configuration Structure. More...

Detailed Description

ME config block for PEI phase.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MePeiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MePeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
MePeiConfig.h
Go to the documentation of this file.
1 /** @file
2 ME config block for PEI phase
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_PEI_CONFIG_H_
36 #define _ME_PEI_CONFIG_H_
37
38 #define ME_PEI_PREMEM_CONFIG_REVISION 4
39 extern EFI_GUID gMePeiPreMemConfigGuid;
40
41 #ifndef PLATFORM_POR
42 #define PLATFORM_POR 0
43 #endif
44 #ifndef FORCE_ENABLE
45 #define FORCE_ENABLE 1
46 #endif
47 #ifndef FORCE_DISABLE
48 #define FORCE_DISABLE 2
49 #endif
50
51 #pragma pack (push,1)
52
53 /**
54 ME Pei Pre-Memory Configuration Structure.
55
56 <b>Revision 1:</b>
57 - Initial version.
58 <b>Revision 2:</b>
59 - Add SkipCpuReplacementCheck Option.
60 <b>Revision 3:</b>
61 - Deprecate SendDidMsg.
62 <b>Revision 4:</b>
63 - Add HeciFullTrace Option.
64 **/
65 typedef struct {
66 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
67 UINT32 HeciTimeouts : 1; ///< 0: Disable; <b>1: Enable</b> - HECI Send/Receive Timeouts.
68 /**
69 <b>(Test)</b>
70 <b>0: Disabled</b>
71 1: ME DID init stat 0 - Success
72 2: ME DID init stat 1 - No Memory in Channels
73 3: ME DID init stat 2 - Memory Init Error
74 **/
75 UINT32 DidInitStat : 2;
76 /**
77 <b>(Test)</b>
78 <b>0: Set to 0 to enable polling for CPU replacement</b>
79 1: Set to 1 will disable polling for CPU replacement
80 **/
81 UINT32 DisableCpuReplacedPolling : 1;
82 UINT32 SendDidMsg : 1; ///< <b>(Deprecated)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable to send DID message.
83 /**
84 <b>(Test)</b>
85 <b>0: ME BIOS will check each messages before sending</b>
86 1: ME BIOS always sends messages without checking
87 **/
88 UINT32 DisableMessageCheck : 1;
89 /**
90 <b>(Test)</b>
91 The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot
92 in a MBP message. If set to 1, BIOS will send the MBP message with SkipMbp flag
93 set causing CSME to respond with MKHI header only and no MBP data
94 <b>0: ME BIOS will keep MBP and create HOB for MBP data</b>
95 1: ME BIOS will skip MBP data
96 **/
97 UINT32 SkipMbpHob : 1;
98 UINT32 HeciCommunication2 : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable HECI2.
99 UINT32 KtDeviceEnable : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable Kt Device.
100 UINT32 SkipCpuReplacementCheck : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable to skip CPU replacement check.
101 UINT32 HeciFullTrace : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable Full HECI communication information logged to serial
102 UINT32 RsvdBits : 21; ///< Reserved for future use & Config block alignment
103 UINT32 Heci1BarAddress; ///< HECI1 BAR address.
104 UINT32 Heci2BarAddress; ///< HECI2 BAR address.
105 UINT32 Heci3BarAddress; ///< HECI3 BAR address.
106 } ME_PEI_PREMEM_CONFIG;
107 #pragma pack (pop)
108
109
110 #define ME_PEI_CONFIG_REVISION 4
111 extern EFI_GUID gMePeiConfigGuid;
112
113 #pragma pack (push,1)
114
115 /**
116 ME Pei Post-Memory Configuration Structure.
117
118 <b>Revision 1:</b>
119 - Initial version.
120 <b>Revision 2</b>:
121 - Deprecated Heci3Enabled.
122 <b>Revision 3</b>
123 - Added EnforceEDebugMode.
124 <b>Revision 4</b>
125 - Added CseDataResilience.
126 **/
127
128 typedef struct {
129 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
130
131 UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send in PEI; <b>2: Send in DXE</b> - Send EOP at specific phase.
132 UINT32 Heci3Enabled : 1; ///< @deprecated
133 UINT32 DisableD0I3SettingForHeci : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable D0i3 for HECI.
134 /**
135 Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0.
136 It will cause ME to unconfig if RTC is cleared.
137 - 0: Disable
138 - <b>1: Enable</b>
139 - 2: Cmos is clear, status unkonwn
140 - 3: Reserved
141 **/
142 UINT32 MeUnconfigOnRtcClear : 2;
143 UINT32 MctpBroadcastCycle : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Program registers for MCTP Cycle.
144 UINT32 EnforceEDebugMode : 1; ///< <b>0: Disable</b>; 1: Enable - Enforces ME to enter Enhanced Debug Mode
145 UINT32 CseDataResilience : 1; ///< 0: Disable; <b>1: Enable</b> - CSE data resilience support
146 UINT32 RsvdBits : 23; ///< Reserved for future use & Config block alignment
147 } ME_PEI_CONFIG;
148
149 #pragma pack (pop)
150
151 #endif // _ME_PEI_CONFIG_H_
ME_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: MePeiConfig.h:66
ME_PEI_PREMEM_CONFIG::KtDeviceEnable
UINT32 KtDeviceEnable
(Test) 0: Disable; 1: Enable - Enable/Disable Kt Device.
Definition: MePeiConfig.h:99
ME_PEI_CONFIG
ME Pei Post-Memory Configuration Structure.
Definition: MePeiConfig.h:128
ME_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: MePeiConfig.h:129
ME_PEI_CONFIG::MctpBroadcastCycle
UINT32 MctpBroadcastCycle
(Test) 0: Disable; 1: Enable - Program registers for MCTP Cycle.
Definition: MePeiConfig.h:143
ME_PEI_PREMEM_CONFIG::Heci3BarAddress
UINT32 Heci3BarAddress
HECI3 BAR address.
Definition: MePeiConfig.h:105
ME_PEI_PREMEM_CONFIG::HeciCommunication2
UINT32 HeciCommunication2
(Test) 0: Disable; 1: Enable - Enable/Disable HECI2.
Definition: MePeiConfig.h:98
ME_PEI_CONFIG::MeUnconfigOnRtcClear
UINT32 MeUnconfigOnRtcClear
Enable/Disable Me Unconfig On Rtc Clear.
Definition: MePeiConfig.h:142
ME_PEI_PREMEM_CONFIG::SkipMbpHob
UINT32 SkipMbpHob
(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot in...
Definition: MePeiConfig.h:97
ME_PEI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: MePeiConfig.h:146
ME_PEI_PREMEM_CONFIG::DisableCpuReplacedPolling
UINT32 DisableCpuReplacedPolling
(Test) 0: Set to 0 to enable polling for CPU replacement 1: Set to 1 will disable polling for CPU rep...
Definition: MePeiConfig.h:81
ME_PEI_PREMEM_CONFIG
ME Pei Pre-Memory Configuration Structure.
Definition: MePeiConfig.h:65
ME_PEI_PREMEM_CONFIG::HeciTimeouts
UINT32 HeciTimeouts
0: Disable; 1: Enable - HECI Send/Receive Timeouts.
Definition: MePeiConfig.h:67
ME_PEI_CONFIG::Heci3Enabled
UINT32 Heci3Enabled
Definition: MePeiConfig.h:132
ME_PEI_CONFIG::CseDataResilience
UINT32 CseDataResilience
0: Disable; 1: Enable - CSE data resilience support
Definition: MePeiConfig.h:145
ME_PEI_PREMEM_CONFIG::SkipCpuReplacementCheck
UINT32 SkipCpuReplacementCheck
(Test) 0: Disable; 1: Enable - Enable/Disable to skip CPU replacement check.
Definition: MePeiConfig.h:100
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ME_PEI_PREMEM_CONFIG::HeciFullTrace
UINT32 HeciFullTrace
(Test) 0: Disable; 1: Enable - Enable/Disable Full HECI communication information logged to serial
Definition: MePeiConfig.h:101
ME_PEI_CONFIG::EndOfPostMessage
UINT32 EndOfPostMessage
0: Disabled; 1: Send in PEI; 2: Send in DXE - Send EOP at specific phase.
Definition: MePeiConfig.h:131
ME_PEI_CONFIG::EnforceEDebugMode
UINT32 EnforceEDebugMode
0: Disable; 1: Enable - Enforces ME to enter Enhanced Debug Mode
Definition: MePeiConfig.h:144
ME_PEI_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: MePeiConfig.h:102
ME_PEI_PREMEM_CONFIG::DisableMessageCheck
UINT32 DisableMessageCheck
(Test) 0: ME BIOS will check each messages before sending 1: ME BIOS always sends messages without ch...
Definition: MePeiConfig.h:88
ME_PEI_CONFIG::DisableD0I3SettingForHeci
UINT32 DisableD0I3SettingForHeci
(Test) 0: Disable; 1: Enable - Enable/Disable D0i3 for HECI.
Definition: MePeiConfig.h:133
ME_PEI_PREMEM_CONFIG::Heci2BarAddress
UINT32 Heci2BarAddress
HECI2 BAR address.
Definition: MePeiConfig.h:104
ME_PEI_PREMEM_CONFIG::SendDidMsg
UINT32 SendDidMsg
(Deprecated) 0: Disable; 1: Enable - Enable/Disable to send DID message.
Definition: MePeiConfig.h:82
ME_PEI_PREMEM_CONFIG::Heci1BarAddress
UINT32 Heci1BarAddress
HECI1 BAR address.
Definition: MePeiConfig.h:103
ME_PEI_PREMEM_CONFIG::DidInitStat
UINT32 DidInitStat
(Test) 0: Disabled 1: ME DID init stat 0 - Success 2: ME DID init stat 1 - No Memory in Channels 3: M...
Definition: MePeiConfig.h:75
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MpServices.h File Reference

  • Edk2
  • MdePkg
  • Include
  • Ppi
Classes | Typedefs
MpServices.h File Reference

This file declares UEFI PI Multi-processor PPI. More...

#include <Protocol/MpService.h>
Include dependency graph for MpServices.h:

Go to the source code of this file.

Classes

struct _EFI_PEI_MP_SERVICES_PPI
This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support. More...

Typedefs

typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
Get the number of CPU's. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Get information on a specific CPU. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_STARTUP_ALL_APS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)
Activate all of the application processors. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_STARTUP_THIS_AP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)
Activate a specific application processor. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_SWITCH_BSP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
Switch the boot strap processor. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_ENABLEDISABLEAP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
Enable or disable an application processor. More...
typedef EFI_STATUS(* | EFI_PEI_MP_SERVICES_WHOAMI) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)
Identify the currently executing processor. More...

Detailed Description

This file declares UEFI PI Multi-processor PPI.

This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support.

Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Revision Reference:
This PPI is introduced in PI Version 1.4.

Definition in file MpServices.h.

Typedef Documentation

◆ EFI_PEI_MP_SERVICES_ENABLEDISABLEAP

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_ENABLEDISABLEAP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)

Enable or disable an application processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.

Definition at line 229 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)

Get the number of CPU's.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL. NumberOfEnabledProcessors is NULL.

Definition at line 44 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)

Get information on a specific CPU.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[in] | ProcessorNumber | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | ProcessorInfoBuffer | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.

Definition at line 69 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_STARTUP_ALL_APS

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_STARTUP_ALL_APS) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)

Activate all of the application processors.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | TimeoutInMicroSeconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.

Definition at line 112 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_STARTUP_THIS_AP

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_STARTUP_THIS_AP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)

Activate a specific application processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | TimeoutInMicroSeconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.

Definition at line 157 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_SWITCH_BSP

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_SWITCH_BSP) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)

Switch the boot strap processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.

Definition at line 192 of file MpServices.h.

◆ EFI_PEI_MP_SERVICES_WHOAMI

typedef EFI_STATUS( * EFI_PEI_MP_SERVICES_WHOAMI) (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)

Identify the currently executing processor.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[out] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.

Definition at line 254 of file MpServices.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MpServices.h Source File

  • Edk2
  • MdePkg
  • Include
  • Ppi
MpServices.h
Go to the documentation of this file.
1 /** @file
2 This file declares UEFI PI Multi-processor PPI.
3 This PPI is installed by some platform or chipset-specific PEIM that abstracts
4 handling multiprocessor support.
5
6 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
8
9 @par Revision Reference:
10 This PPI is introduced in PI Version 1.4.
11
12 **/
13
14 #ifndef __PEI_MP_SERVICES_PPI_H__
15 #define __PEI_MP_SERVICES_PPI_H__
16
17 #include <Protocol/MpService.h>
18
19 #define EFI_PEI_MP_SERVICES_PPI_GUID \
20 { \
21 0xee16160a, 0xe8be, 0x47a6, { 0x82, 0xa, 0xc6, 0x90, 0xd, 0xb0, 0x25, 0xa } \
22 }
23
24 typedef struct _EFI_PEI_MP_SERVICES_PPI EFI_PEI_MP_SERVICES_PPI ;
25
26 /**
27 Get the number of CPU's.
28
29 @param[in] PeiServices An indirect pointer to the PEI Services Table
30 published by the PEI Foundation.
31 @param[in] This Pointer to this instance of the PPI.
32 @param[out] NumberOfProcessors Pointer to the total number of logical processors in
33 the system, including the BSP and disabled APs.
34 @param[out] NumberOfEnabledProcessors
35 Number of processors in the system that are enabled.
36
37 @retval EFI_SUCCESS The number of logical processors and enabled
38 logical processors was retrieved.
39 @retval EFI_DEVICE_ERROR The calling processor is an AP.
40 @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL.
41 NumberOfEnabledProcessors is NULL.
42 **/
43 typedef
44 EFI_STATUS
45 (EFIAPI *EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (
46 IN CONST EFI_PEI_SERVICES **PeiServices,
47 IN EFI_PEI_MP_SERVICES_PPI *This,
48 OUT UINTN *NumberOfProcessors,
49 OUT UINTN *NumberOfEnabledProcessors
50 );
51
52 /**
53 Get information on a specific CPU.
54
55 @param[in] PeiServices An indirect pointer to the PEI Services Table
56 published by the PEI Foundation.
57 @param[in] This Pointer to this instance of the PPI.
58 @param[in] ProcessorNumber Pointer to the total number of logical processors in
59 the system, including the BSP and disabled APs.
60 @param[out] ProcessorInfoBuffer Number of processors in the system that are enabled.
61
62 @retval EFI_SUCCESS Processor information was returned.
63 @retval EFI_DEVICE_ERROR The calling processor is an AP.
64 @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
65 @retval EFI_NOT_FOUND The processor with the handle specified by
66 ProcessorNumber does not exist in the platform.
67 **/
68 typedef
69 EFI_STATUS
70 (EFIAPI *EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO) (
71 IN CONST EFI_PEI_SERVICES **PeiServices,
72 IN EFI_PEI_MP_SERVICES_PPI *This,
73 IN UINTN ProcessorNumber,
74 OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
75 );
76
77 /**
78 Activate all of the application processors.
79
80 @param[in] PeiServices An indirect pointer to the PEI Services Table
81 published by the PEI Foundation.
82 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
83 @param[in] Procedure A pointer to the function to be run on enabled APs of
84 the system.
85 @param[in] SingleThread If TRUE, then all the enabled APs execute the function
86 specified by Procedure one by one, in ascending order
87 of processor handle number. If FALSE, then all the
88 enabled APs execute the function specified by Procedure
89 simultaneously.
90 @param[in] TimeoutInMicroSeconds
91 Indicates the time limit in microseconds for APs to
92 return from Procedure, for blocking mode only. Zero
93 means infinity. If the timeout expires before all APs
94 return from Procedure, then Procedure on the failed APs
95 is terminated. All enabled APs are available for next
96 function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs()
97 or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the
98 timeout expires in blocking mode, BSP returns
99 EFI_TIMEOUT.
100 @param[in] ProcedureArgument The parameter passed into Procedure for all APs.
101
102 @retval EFI_SUCCESS In blocking mode, all APs have finished before the
103 timeout expired.
104 @retval EFI_DEVICE_ERROR Caller processor is AP.
105 @retval EFI_NOT_STARTED No enabled APs exist in the system.
106 @retval EFI_NOT_READY Any enabled APs are busy.
107 @retval EFI_TIMEOUT In blocking mode, the timeout expired before all
108 enabled APs have finished.
109 @retval EFI_INVALID_PARAMETER Procedure is NULL.
110 **/
111 typedef
112 EFI_STATUS
113 (EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_ALL_APS) (
114 IN CONST EFI_PEI_SERVICES **PeiServices,
115 IN EFI_PEI_MP_SERVICES_PPI *This,
116 IN EFI_AP_PROCEDURE Procedure,
117 IN BOOLEAN SingleThread,
118 IN UINTN TimeoutInMicroSeconds,
119 IN VOID *ProcedureArgument OPTIONAL
120 );
121
122 /**
123 Activate a specific application processor.
124
125 @param[in] PeiServices An indirect pointer to the PEI Services Table
126 published by the PEI Foundation.
127 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
128 @param[in] Procedure A pointer to the function to be run on enabled APs of
129 the system.
130 @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
131 total number of logical processors minus 1. The total
132 number of logical processors can be retrieved by
133 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
134 @param[in] TimeoutInMicroSeconds
135 Indicates the time limit in microseconds for APs to
136 return from Procedure, for blocking mode only. Zero
137 means infinity. If the timeout expires before all APs
138 return from Procedure, then Procedure on the failed APs
139 is terminated. All enabled APs are available for next
140 function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs()
141 or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the
142 timeout expires in blocking mode, BSP returns
143 EFI_TIMEOUT.
144 @param[in] ProcedureArgument The parameter passed into Procedure for all APs.
145
146 @retval EFI_SUCCESS In blocking mode, specified AP finished before the
147 timeout expires.
148 @retval EFI_DEVICE_ERROR The calling processor is an AP.
149 @retval EFI_TIMEOUT In blocking mode, the timeout expired before the
150 specified AP has finished.
151 @retval EFI_NOT_FOUND The processor with the handle specified by
152 ProcessorNumber does not exist.
153 @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP or disabled AP.
154 @retval EFI_INVALID_PARAMETER Procedure is NULL.
155 **/
156 typedef
157 EFI_STATUS
158 (EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_THIS_AP) (
159 IN CONST EFI_PEI_SERVICES **PeiServices,
160 IN EFI_PEI_MP_SERVICES_PPI *This,
161 IN EFI_AP_PROCEDURE Procedure,
162 IN UINTN ProcessorNumber,
163 IN UINTN TimeoutInMicroseconds,
164 IN VOID *ProcedureArgument OPTIONAL
165 );
166
167 /**
168 Switch the boot strap processor.
169
170 @param[in] PeiServices An indirect pointer to the PEI Services Table
171 published by the PEI Foundation.
172 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
173 @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
174 total number of logical processors minus 1. The total
175 number of logical processors can be retrieved by
176 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
177 @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an enabled
178 AP. Otherwise, it will be disabled.
179
180 @retval EFI_SUCCESS BSP successfully switched.
181 @retval EFI_UNSUPPORTED Switching the BSP cannot be completed prior to this
182 service returning.
183 @retval EFI_UNSUPPORTED Switching the BSP is not supported.
184 @retval EFI_DEVICE_ERROR The calling processor is an AP.
185 @retval EFI_NOT_FOUND The processor with the handle specified by
186 ProcessorNumber does not exist.
187 @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the current BSP or a disabled
188 AP.
189 @retval EFI_NOT_READY The specified AP is busy.
190 **/
191 typedef
192 EFI_STATUS
193 (EFIAPI *EFI_PEI_MP_SERVICES_SWITCH_BSP) (
194 IN CONST EFI_PEI_SERVICES **PeiServices,
195 IN EFI_PEI_MP_SERVICES_PPI *This,
196 IN UINTN ProcessorNumber,
197 IN BOOLEAN EnableOldBSP
198 );
199
200 /**
201 Enable or disable an application processor.
202
203 @param[in] PeiServices An indirect pointer to the PEI Services Table
204 published by the PEI Foundation.
205 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
206 @param[in] ProcessorNumber The handle number of the AP. The range is from 0 to the
207 total number of logical processors minus 1. The total
208 number of logical processors can be retrieved by
209 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
210 @param[in] EnableAP Specifies the new state for the processor for enabled,
211 FALSE for disabled.
212 @param[in] HealthFlag If not NULL, a pointer to a value that specifies the
213 new health status of the AP. This flag corresponds to
214 StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo().
215 Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other
216 bits are ignored. If it is NULL, this parameter is
217 ignored.
218
219 @retval EFI_SUCCESS The specified AP was enabled or disabled successfully.
220 @retval EFI_UNSUPPORTED Enabling or disabling an AP cannot be completed prior
221 to this service returning.
222 @retval EFI_UNSUPPORTED Enabling or disabling an AP is not supported.
223 @retval EFI_DEVICE_ERROR The calling processor is an AP.
224 @retval EFI_NOT_FOUND Processor with the handle specified by ProcessorNumber
225 does not exist.
226 @retval EFI_INVALID_PARAMETER ProcessorNumber specifies the BSP.
227 **/
228 typedef
229 EFI_STATUS
230 (EFIAPI *EFI_PEI_MP_SERVICES_ENABLEDISABLEAP) (
231 IN CONST EFI_PEI_SERVICES **PeiServices,
232 IN EFI_PEI_MP_SERVICES_PPI *This,
233 IN UINTN ProcessorNumber,
234 IN BOOLEAN EnableAP,
235 IN UINT32 *HealthFlag OPTIONAL
236 );
237
238 /**
239 Identify the currently executing processor.
240
241 @param[in] PeiServices An indirect pointer to the PEI Services Table
242 published by the PEI Foundation.
243 @param[in] This A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
244 @param[out] ProcessorNumber The handle number of the AP. The range is from 0 to the
245 total number of logical processors minus 1. The total
246 number of logical processors can be retrieved by
247 EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
248
249 @retval EFI_SUCCESS The current processor handle number was returned in
250 ProcessorNumber.
251 @retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
252 **/
253 typedef
254 EFI_STATUS
255 (EFIAPI *EFI_PEI_MP_SERVICES_WHOAMI) (
256 IN CONST EFI_PEI_SERVICES **PeiServices,
257 IN EFI_PEI_MP_SERVICES_PPI *This,
258 OUT UINTN *ProcessorNumber
259 );
260
261 ///
262 /// This PPI is installed by some platform or chipset-specific PEIM that abstracts
263 /// handling multiprocessor support.
264 ///
265 struct _EFI_PEI_MP_SERVICES_PPI {
266 EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
267 EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;
268 EFI_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;
269 EFI_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;
270 EFI_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;
271 EFI_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;
272 EFI_PEI_MP_SERVICES_WHOAMI WhoAmI;
273 };
274
275 extern EFI_GUID gEfiPeiMpServicesPpiGuid;
276
277 #endif
EFI_PEI_MP_SERVICES_ENABLEDISABLEAP
EFI_STATUS(* EFI_PEI_MP_SERVICES_ENABLEDISABLEAP)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
Enable or disable an application processor.
Definition: MpServices.h:230
IN
#define IN
Datum is passed to the function.
Definition: Base.h:288
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
EFI_AP_PROCEDURE
VOID(* EFI_AP_PROCEDURE)(IN OUT VOID *Buffer)
The function prototype for invoking a function on an Application Processor.
Definition: PiMultiPhase.h:191
EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS
EFI_STATUS(* EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
Get the number of CPU's.
Definition: MpServices.h:45
OUT
#define OUT
Datum is returned from the function.
Definition: Base.h:293
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
EFI_PEI_MP_SERVICES_WHOAMI
EFI_STATUS(* EFI_PEI_MP_SERVICES_WHOAMI)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)
Identify the currently executing processor.
Definition: MpServices.h:255
OPTIONAL
#define OPTIONAL
Passing the datum to the function is optional, and a NULL is passed if the value is not supplied.
Definition: Base.h:299
EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO
EFI_STATUS(* EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Get information on a specific CPU.
Definition: MpServices.h:70
CONST
#define CONST
Datum is read-only.
Definition: Base.h:268
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS
EFI_STATUS(* EFI_PEI_MP_SERVICES_STARTUP_ALL_APS)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)
Activate all of the application processors.
Definition: MpServices.h:113
EFI_PEI_MP_SERVICES_STARTUP_THIS_AP
EFI_STATUS(* EFI_PEI_MP_SERVICES_STARTUP_THIS_AP)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)
Activate a specific application processor.
Definition: MpServices.h:158
_EFI_PEI_MP_SERVICES_PPI
This PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocesso...
Definition: MpServices.h:265
EFI_PEI_MP_SERVICES_SWITCH_BSP
EFI_STATUS(* EFI_PEI_MP_SERVICES_SWITCH_BSP)(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
Switch the boot strap processor.
Definition: MpServices.h:193
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: OverclockingConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking
Classes
OverclockingConfig.h File Reference

Overclocking Config Block. More...

#include <CpuLimits.h>
Include dependency graph for OverclockingConfig.h:

Go to the source code of this file.

Classes

struct OVERCLOCKING_PREMEM_CONFIG
Overclocking Configuration Structure. More...

Detailed Description

Overclocking Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file OverclockingConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: OverclockingConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking
OverclockingConfig.h
Go to the documentation of this file.
1 /** @file
2 Overclocking Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _OVERCLOCKING_PREMEM_CONFIG_H_
36 #define _OVERCLOCKING_PREMEM_CONFIG_H_
37
38 #include <CpuLimits.h>
39
40 #define OVERCLOCKING_PREMEM_CONFIG_REVISION 37
41
42 extern EFI_GUID gOverclockingPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 //
47 // Max number of VF point offset
48 //
49 #ifndef CPU_OC_MAX_VF_POINTS
50 #define CPU_OC_MAX_VF_POINTS 0xF
51 #endif
52
53 /**
54 Overclocking Configuration Structure.
55
56 <b>Revision 1</b>:
57 - Initial version.
58 <b>Revision 2</b>
59 - Add PerCoreHtDisable
60 <b>Revision 3</b>
61 - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor
62 <b>Revision 4</b>
63 - Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & CoreVfPointCount
64 <b>Revision 5</b>
65 - Change OcLock default to 'Enabled'
66 <b>Revision 6</b>
67 - Add CoreVfScope & PerCoreVoltageOffset
68 <b>Revision 7</b>
69 - Add AtomMaxOcRatio
70 <b>Revision 8</b>
71 - Add PerCoreRatioOverride and PerCoreRatio for Per Core PState overclocking.
72 <b>Revision 9</b>
73 Add UnlimitedIccMax
74 <b>Revision 10</b>
75 Add Atom Voltage configurations
76 <b>Revision 11</b>
77 Add SA Voltage adaptive and override configurations
78 <b>Revision 12</b>
79 Add RingVfPointOffsetMode & RingVfPointOffset & RingVfPointRatio & RingVfPointCount
80 <b>Revision 13</b>
81 Add CpuBclkOcFrequency
82 <b>Revision 14</b>:
83 - Add DisablePerCoreMask & DisablePerAtomMask.
84 <b>Revision 15</b>
85 Add CoreRatioExtensionMode
86 <b>Revision 16</b>
87 Add PvdRatioThreshold
88 <b>Revision 17</b>
89 Add IaCepEnable & GtCepEnable & SaCepEnable & IaSirpEnable
90 <b>Revision 18</b>
91 Add Per Atom Cluster VF support
92 Corrected the policy name of AtomMaxOcRatio to be AtomL2MaxOcRatio
93 <b>Revision 19</b>
94 Modify PllVoltageOffset of each Domain Range in 0 - 15 instead of 0 - 63
95 <b>Revision 20</b>
96 Add ItdThrottleEnable
97 <b>Revision 21</b>
98 Add AtomClusterRatio & Correct max big core number to be 8
99 <b>Revision 22</b>
100 Add SocBclkOcFrequency
101 <b>Revision 23</b>
102 Add AtomPllVoltageOffset
103 <b>Revision 24</b>
104 Deprecated FivrFaults, FivrEfficiency.
105 <b>Revision 25</b>
106 Add DlvrBypassModeEnable.
107 <b>Revision 26</b>
108 Add PvdMode and FllOverclockMode
109 <b>Revision 27</b>
110 Deprecated AtomL2MaxOcRatio
111 <b>Revision 28</b>
112 Deprecated Avx512VoltageScaleFactor and Avx3RatioOffset
113 <b>Revision 29</b>
114 Add SaPllFreqOverride
115 <b>Revision 30</b>
116 Add PllMaxBandingRatio
117 <b>Revision 31</b>
118 Add TscDisableHwFixup
119 <b>Revision 32</b>
120 Add IaIccUnlimitedMode & IaIccMax & GtIccUnlimitedMode & GtIccMax and deprecated UnlimitedIccMax
121 <b>Revision 33</b>
122 Add TvbDownBinsTempThreshold0, TvbDownBinsTempThreshold1, TvbTempThreshold0, TvbTempThreshold1
123 <b>Revision 34</b>
124 Deprecated PllMaxBandingRatio
125 <b>Revision 35</b>
126 Add FllOcModeEn
127 <b>Revision 36</b>
128 Deprecated DisablePerAtomMask (DisablePerCoreMask is used for both the cores)
129 <b>Revision 37</b>
130 Add Etvb
131 **/
132 typedef struct {
133 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
134 /**
135 Overclocking support. This controls whether OC mailbox transactions are sent.
136 If disabled, all policies in this config block besides OcSupport and OcLock will be ignored.
137 <b>0: Disable</b>;
138 1: Enable.
139 @note If PcdOverclockEnable is disabled, this should also be disabled.
140 **/
141 UINT32 OcSupport : 1;
142 UINT32 OcLock : 1; ///< If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; 0: Disable; <b>1: Enable (Lock)</b>.
143 /**
144 Core voltage mode, specifies which voltage mode the processor will be operating.
145 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
146 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
147 **/
148 UINT32 CoreVoltageMode : 1;
149 UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
150 UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
151 UINT32 Avx3RatioOffset : 5; ///< deprecated from version 28
152 UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Voltage enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
153 /**
154 Ring Downbin enable/disable.
155 When enabled, the CPU will force the ring ratio to be lower than the core ratio.
156 Disabling will allow the ring and core ratios to run at the same frequency.
157 Uses OC Mailbox command 0x19.
158 0: Disables Ring Downbin feature. <b>1: Enables Ring downbin feature.</b>
159 **/
160 UINT32 RingDownBin : 1;
161 /**
162 Ring voltage mode, specifies which voltage mode the processor will be operating.
163 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
164 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
165 **/
166 UINT32 RingVoltageMode : 1;
167 UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage is operating in Adaptive or Override mode: <b>0=Adaptive</b>, 1=Override
168 UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE. <b>0=Disable</b>, 1=Enable
169 UINT32 FivrFaults : 1; /// Deprecated < Fivr Faults. Enable or Disable FIVR Faults. 0: Disabled, <b>1: Enabled.</b>
170 UINT32 FivrEfficiency : 1; /// Deprecated < Fivr Efficiency Management. 0: Disabled, <b>1: Enabled.</b>
171 /**
172 Selects Core Voltage & Frequency Offset between Legacy and Selection modes.
173 Need Reset System after enabling OverClocking Feature to Initialize the default value.
174 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
175 1: In Selection Mode, setting a selected VF point.
176 **/
177 UINT32 CoreVfPointOffsetMode : 1;
178 /**
179 Core VF Configuration Scope.
180 Alows both all-core VF curve or per-core VF curve configuration.
181 <b>0: All-core Scope, setting the VF curve for all cores.</b>
182 1: Per-core Scope, setting the VF curve per-core.
183 **/
184 UINT32 CoreVfConfigScope : 1;
185 UINT32 PerCoreRatioOverride : 1; ///< Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. <b>0: Disable</b>, 1: enable
186 UINT32 UnlimitedIccMax : 1; ///< deprecated from version 32
187 /**
188 SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.
189 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
190 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
191 **/
192 UINT32 SaVoltageMode : 1;
193 UINT32 CoreRatioExtensionMode : 1; ///< Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. <b>0: Disable</b>, 1: enable
194
195 /**
196 Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
197 <b>0. no override/HW defaults.</b>. Range non-turbo max - 120 (Previously max turbo is 83).
198 **/
199 UINT8 CoreMaxOcRatio;
200 UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, <b>0=AUTO</b>
201 /**
202 Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.
203 <b>0. no override/HW defaults.</b>. Range non-turbo max - 85.
204 **/
205 UINT8 RingMaxOcRatio;
206 /**
207 Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
208 <b>0. no override/HW defaults.</b>. non-turbo max - 120.
209 **/
210 UINT8 AtomL2MaxOcRatio; ///<deprecated from version 27
211 /**
212 The core voltage override which is applied to the entire range of cpu core frequencies.
213 Used when CoreVoltageMode = Override.
214 <b>0. no override</b>. Range 0-2000 mV.
215 **/
216 UINT16 CoreVoltageOverride;
217 /**
218 Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.
219 Used when CoreVoltageMode = Adaptive.
220 <b>0. no override</b>. Range 0-2000mV.
221 **/
222 UINT16 CoreVoltageAdaptive;
223 /**
224 The core voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
225 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
226 **/
227 INT16 CoreVoltageOffset;
228 /**
229 The ring voltage override which is applied to the entire range of cpu ring frequencies.
230 Used when RingVoltageMode = Override.
231 <b>0. no override</b>. Range 0-2000 mV.
232 **/
233 UINT16 RingVoltageOverride;
234 /**
235 Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range.
236 Used when RingVoltageMode = Adaptive.
237 <b>0. no override</b>. Range 0-2000mV.
238 **/
239 UINT16 RingVoltageAdaptive;
240 /**
241 The ring voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
242 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
243 **/
244 INT16 RingVoltageOffset;
245
246 INT16 GtVoltageOffset; ///< The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: <b>0=Minimal</b>, 1000=Maximum
247 UINT16 GtVoltageOverride; ///< The GT voltage override which is applied to the entire range of GT frequencies <b>0=Default</b>
248 UINT16 GtExtraTurboVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: <b>0=Minimal</b>, 2000=Maximum
249 INT16 SaVoltageOffset; ///< The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: <b>0=Default</b>
250 UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
251 UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
252 UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
253 UINT32 McPllVoltageOffset : 6; ///< Memory Controller PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
254 UINT32 IaCepEnable : 1; ///< Enable IA Current Excursion Protection. <b>1: Enable</b>. 0: Disable.
255 UINT32 GtCepEnable : 1; ///< Enable GT Current Excursion Protection. <b>1: Enable</b>. 0: Disable.
256 UINT32 SaCepEnable : 1; ///< Enable SA Current Excursion Protection. <b>1: Enable</b>. 0: Disable.
257 UINT32 IaSirpEnable : 1; ///< Enable IA SoC Iccmax Reactive Protector. <b>1: Enable</b>. 0: Disable.
258 UINT32 ItdThrottleEnable : 1; ///< Enable Inverse Temperature Dependency Throttle Support. <b>1: Enable</b>. 0: Disable.
259 UINT32 DlvrBypassModeEnable : 1; ///< Enable CPU DLVR bypass mode support, <b>0: Disable</b>. 0: Enable.
260 UINT32 SaPllFreqOverride : 1; ///< Sa PLL Frequecy Override. <b>0: 3200MHz</b>. 1: 1600MHz.
261 UINT32 TscDisableHwFixup : 1; ///< Core HW Fixup disable during TSC copy from PMA to APIC, <b>0: Enable</b>. 1: Disable.
262
263 /**
264 TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius.
265 <b> Default: 0 Hardware Defaults </b> Range 10 to 63. 0 = No offset / Keep HW default.
266 **/
267 UINT8 TjMaxOffset;
268 UINT8 RsvdByte2[3]; ///< Reserved for dword alignment
269 /**
270 This service controls Core frequency reduction caused by high package temperatures for processors that
271 implement the Intel Thermal Velocity Boost (TVB) feature. It is required to be disabled for supporting
272 overclocking at frequencies higher than the default max turbo frequency.
273 <b>0: Disables TVB ratio clipping. </b>1: Enables TVB ratio clipping.
274 **/
275 UINT32 TvbRatioClipping : 1;
276 /**
277 This service controls thermal based voltage optimizations for processors that implement the Intel
278 Thermal Velocity Boost (TVB) feature.
279 0: Disables TVB voltage optimization. <b>1: Enables TVB voltage optimization.</b>
280 **/
281 UINT32 TvbVoltageOptimization : 1;
282 UINT32 IaIccUnlimitedMode : 1; ///< Support IA Unlimited ICCMAX up to maximum value 512A., <b>0: Disable</b>. 1: Enable.
283 UINT32 GtIccUnlimitedMode : 1; ///< Support GT Unlimited ICCMAX up to maximum value 512A., <b>0: Disable</b>. 1: Enable.
284 UINT32 FllOcModeEn : 1; ///< Enable FLL Mode override with the value in FllOcMode. <b>0: Disable</b>. 1: Enable.
285 UINT32 Etvb : 1; ///< Enhanced Thermal Turbo Mode (eTVB). <b>0:eTVB is disabled on supporting products</b> 1:eTVB is enabled on supporting products.
286 UINT32 RsvdBits2 : 26;
287 /**
288 Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.
289 Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0.
290 <b>Default is 0</b>, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.
291 **/
292 UINT16 PerCoreHtDisable;
293 /**
294 Avx2 Voltage Guardband Scale Factor
295 This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads.
296 Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
297 A value of 0 means no scale factor applied (no change to voltage on AVX commands)
298 A value of 100 applies the default voltage guardband values (1.0 factor).
299 A value > 100 will increase the voltage guardband on AVX2 workloads.
300 A value < 100 will decrease the voltage guardband on AVX2 workloads.
301
302 <b>0. No scale factor applied</b>
303 **/
304 UINT8 Avx2VoltageScaleFactor;
305 /**
306 Avx512 Voltage Guardband Scale Factor
307 This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads.
308 Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
309 A value of 0 means no scale factor applied (no change to voltage on AVX commands)
310 A value of 100 applies the default voltage guardband values (1.0 factor).
311 A value > 100 will increase the voltage guardband on AVX512 workloads.
312 A value < 100 will decrease the voltage guardband on AVX512 workloads.
313
314 <b>0. No scale factor applied</b>
315 **/
316 UINT8 Avx512VoltageScaleFactor; ///<deprecated from version 28
317 /**
318 Array used to specifies the Core Voltage Offset applied to the each selected VF Point.
319 This voltage is specified in millivolts.
320 **/
321 INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS];
322 UINT8 RsvdByte3[2]; ///< Reserved for dword alignment
323 /**
324 Array for the each selected VF Point to display the Core Ration.
325 **/
326 UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS];
327 /**
328 Number of supported Core Voltage & Frequency Point.
329 **/
330 UINT8 CoreVfPointCount;
331 /**
332 Array used to specifies the selected Core Offset Voltage.
333 This voltage is specified in millivolts.
334 **/
335 INT16 PerCoreVoltageOffset[CPU_MAX_BIG_CORES];
336 INT16 PerCoreVoltageOffset1[CPU_MAX_BIG_CORES];
337 UINT8 PerCoreRatio[CPU_MAX_BIG_CORES];
338 /**
339 The Atom cluster max ratio overrides.
340 <b>Default: 0</b> Range: 0 to 120.
341 **/
342 UINT8 AtomClusterRatio[CPU_MAX_ATOM_CLUSTERS];
343 /**
344 Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating.
345 <b>0: Adaptive Mode</b> allows the atom processor to interpolate a voltage curve when beyond fused P0 range;
346 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
347 **/
348 UINT8 AtomL2VoltageMode;
349 UINT8 RsvdByte4; ///< Reserved for dword alignment
350 /**
351 The atom L2 voltage override which is applied to the entire range of atom core frequencies.
352 Used when AtomL2VoltageMode = Override.
353 <b>0. no override</b>. Range 0-2000 mV.
354 **/
355 UINT16 AtomL2VoltageOverride;
356 /**
357 Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operating in turbo mode range.
358 Used when AtomL2VoltageMode = Adaptive.
359 <b>0. no override</b>. Range 0-2000mV.
360 **/
361 UINT16 AtomL2VoltageAdaptive;
362 /**
363 The atom L2 voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
364 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
365 **/
366 INT16 AtomL2VoltageOffset;
367 /**
368 The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.
369 Used when SaVoltageMode = Override.
370 <b>0. no override</b>. Range 0-2000 mV.
371 **/
372 UINT16 SaVoltageOverride;
373 /**
374 Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is operating in turbo mode range.
375 Used when SaVoltageMode = Adaptive.
376 <b>0. no override</b>. Range 0-2000mV.
377 **/
378 UINT16 SaExtraTurboVoltage;
379 /**
380 Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.
381 Need Reset System after enabling OverClocking Feature to Initialize the default value.
382 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
383 1: In Selection modes, setting a selected VF point.
384 **/
385 UINT8 RingVfPointOffsetMode;
386 /**
387 Number of supported Ring Voltage & Frequency Point.
388 **/
389 UINT8 RingVfPointCount;
390 UINT8 RsvdByte5[2]; ///< Reserved for dword alignment
391 /**
392 Array used to specifies the Ring Voltage Offset applied to the each selected VF Point.
393 This voltage is specified in millivolts.
394 **/
395 INT16 RingVfPointOffset[CPU_OC_MAX_VF_POINTS];
396 UINT8 RsvdByte6[2]; ///< Reserved for dword alignment
397 /**
398 Array for the each selected VF Point to display the Ring Ration.
399 **/
400 UINT8 RingVfPointRatio[CPU_OC_MAX_VF_POINTS];
401 UINT8 AtomPllVoltageOffset; ///< Atom PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
402 UINT32 CpuBclkOcFrequency; ///< CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 - Auto</b>. Range is 8000-50000 (10KHz)
403 /**
404 Core disable mask is a bitwise indication of which core should be disabled.
405 Each bit represents physical core id for both P-core and E-core:
406 1 - Disable
407 0 - Ignored
408 Default is 0, means no Core disable mask setting.
409 **/
410 UINT32 DisablePerCoreMask;
411 /**
412 Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCoreCount is to set the number of active atoms.
413 Each bit represents logical core id:
414 1 - Disable
415 0 - Ignored
416 Defalut is 0, means no Small Core disable mask setting.
417 **/
418 UINT32 DisablePerAtomMask; //Deprecated from version 36
419 /**
420 The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier
421 so that the output is within the DCO frequency range. This threshold is applied to all the domains
422 (Cores, Ring, SA, Memory and GT).
423 <b>0. Default/No Override</b>. Range 1-63.
424 **/
425 UINT8 PvdRatioThreshold;
426 /**
427 PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0).
428 0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock)
429 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)
430 **/
431 UINT8 PvdMode;
432 /**
433 FLL_OVERCLOCK_MODE: 0x0 = no overclocking,
434 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency,
435 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency,
436 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63.
437 **/
438 UINT8 FllOverclockMode;
439 /**
440 The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains.
441 <b>0. Hardware Default/No Override</b>. Minimum must be greater than P0 and maximum is 120.
442 **/
443 UINT8 PllMaxBandingRatio; /// Deprecated from revision 34
444 INT16 PerAtomClusterVoltageOffset[CPU_MAX_ATOM_CLUSTERS];
445 UINT32 SocBclkOcFrequency; ///< SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 - Auto</b>. Range is 4000-100000 (10KHz)
446 /**
447 Voltage Regulator Current Limit (Icc Max) for IA and GT. This value represents the Maximum instantaneous current allowed at any given time.
448 The value is represented in 1/4 A increments. A value of 400 = 100A. <b>4</b>. Range is 4-2047.
449 **/
450 UINT16 IaIccMax;
451 UINT16 GtIccMax;
452 /**
453 Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold 0,
454 the ratio will be clipped by MAX_RATIO[n]-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
455 <b>1 </b>. Range 0-10.
456 **/
457 UINT8 TvbDownBinsTempThreshold0;
458 /**
459 TVB Temp (degrees C) - Temperature Threshold 0. Running ABOVE this temperature will clip delta
460 Down Bins for Threshold 0 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
461 <b>70 </b>. Range 0-100.
462 **/
463 UINT8 TvbTempThreshold0;
464 /**
465 TVB Temp (degrees C) - Temperature Threshold 1. Running ABOVE this temperature, clip delta
466 Down Bins for Threshold 1 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
467 <b>100 </b>. Range 0-100.
468 **/
469 UINT8 TvbTempThreshold1;
470 /**
471 Down Bins (delta) for Temperature Threshold 1. When running above Temperature Threshold 1,
472 the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 0-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
473 <b>2 </b>. Range 0-10.
474 **/
475 UINT8 TvbDownBinsTempThreshold1;
476 } OVERCLOCKING_PREMEM_CONFIG;
477
478 #pragma pack (pop)
479
480 #endif // _CPU_OVERCLOCKING_CONFIG_H_
OVERCLOCKING_PREMEM_CONFIG::RingVoltageAdaptive
UINT16 RingVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operati...
Definition: OverclockingConfig.h:239
OVERCLOCKING_PREMEM_CONFIG::RingVoltageOffset
INT16 RingVoltageOffset
The ring voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:244
OVERCLOCKING_PREMEM_CONFIG::GtVoltageOverride
UINT16 GtVoltageOverride
The GT voltage override which is applied to the entire range of GT frequencies 0=Default
Definition: OverclockingConfig.h:247
OVERCLOCKING_PREMEM_CONFIG::Avx512VoltageScaleFactor
UINT8 Avx512VoltageScaleFactor
Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied...
Definition: OverclockingConfig.h:316
OVERCLOCKING_PREMEM_CONFIG::GtVoltageOffset
INT16 GtVoltageOffset
The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: 0=Minimal,...
Definition: OverclockingConfig.h:246
OVERCLOCKING_PREMEM_CONFIG::SaCepEnable
UINT32 SaCepEnable
Enable SA Current Excursion Protection. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:256
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageAdaptive
UINT16 CoreVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operatin...
Definition: OverclockingConfig.h:222
OVERCLOCKING_PREMEM_CONFIG::FllOverclockMode
UINT8 FllOverclockMode
FLL_OVERCLOCK_MODE: 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0....
Definition: OverclockingConfig.h:438
OVERCLOCKING_PREMEM_CONFIG::IaIccMax
UINT16 IaIccMax
Voltage Regulator Current Limit (Icc Max) for IA and GT.
Definition: OverclockingConfig.h:450
OVERCLOCKING_PREMEM_CONFIG::ItdThrottleEnable
UINT32 ItdThrottleEnable
Enable Inverse Temperature Dependency Throttle Support. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:258
OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffsetMode
UINT32 CoreVfPointOffsetMode
Deprecated < Fivr Efficiency Management. 0: Disabled, 1: Enabled.
Definition: OverclockingConfig.h:177
OVERCLOCKING_PREMEM_CONFIG::RealtimeMemoryTiming
UINT32 RealtimeMemoryTiming
Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE....
Definition: OverclockingConfig.h:168
OVERCLOCKING_PREMEM_CONFIG::SocBclkOcFrequency
UINT32 SocBclkOcFrequency
SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto....
Definition: OverclockingConfig.h:445
OVERCLOCKING_PREMEM_CONFIG::Avx2VoltageScaleFactor
UINT8 Avx2VoltageScaleFactor
Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to ...
Definition: OverclockingConfig.h:304
OVERCLOCKING_PREMEM_CONFIG::DisablePerAtomMask
UINT32 DisablePerAtomMask
Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCo...
Definition: OverclockingConfig.h:418
OVERCLOCKING_PREMEM_CONFIG::RingDownBin
UINT32 RingDownBin
Ring Downbin enable/disable.
Definition: OverclockingConfig.h:160
OVERCLOCKING_PREMEM_CONFIG::UnlimitedIccMax
UINT32 UnlimitedIccMax
deprecated from version 32
Definition: OverclockingConfig.h:186
OVERCLOCKING_PREMEM_CONFIG::Avx2RatioOffset
UINT32 Avx2RatioOffset
AVX2 Ratio Offset. 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize possible rati...
Definition: OverclockingConfig.h:150
OVERCLOCKING_PREMEM_CONFIG::FllOcModeEn
UINT32 FllOcModeEn
Enable FLL Mode override with the value in FllOcMode. 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:284
OVERCLOCKING_PREMEM_CONFIG::CoreVfPointCount
UINT8 CoreVfPointCount
Number of supported Core Voltage & Frequency Point.
Definition: OverclockingConfig.h:330
OVERCLOCKING_PREMEM_CONFIG::PerCoreHtDisable
UINT16 PerCoreHtDisable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.
Definition: OverclockingConfig.h:292
OVERCLOCKING_PREMEM_CONFIG::SaPllFreqOverride
UINT32 SaPllFreqOverride
Sa PLL Frequecy Override. 0: 3200MHz. 1: 1600MHz.
Definition: OverclockingConfig.h:260
OVERCLOCKING_PREMEM_CONFIG::RingVfPointCount
UINT8 RingVfPointCount
Number of supported Ring Voltage & Frequency Point.
Definition: OverclockingConfig.h:389
OVERCLOCKING_PREMEM_CONFIG::GtCepEnable
UINT32 GtCepEnable
Enable GT Current Excursion Protection. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:255
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOverride
UINT16 AtomL2VoltageOverride
The atom L2 voltage override which is applied to the entire range of atom core frequencies.
Definition: OverclockingConfig.h:355
OVERCLOCKING_PREMEM_CONFIG
Overclocking Configuration Structure.
Definition: OverclockingConfig.h:132
OVERCLOCKING_PREMEM_CONFIG::IaSirpEnable
UINT32 IaSirpEnable
Enable IA SoC Iccmax Reactive Protector. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:257
OVERCLOCKING_PREMEM_CONFIG::GtMaxOcRatio
UINT8 GtMaxOcRatio
Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, 0=AUTO
Definition: OverclockingConfig.h:200
OVERCLOCKING_PREMEM_CONFIG::RingVoltageOverride
UINT16 RingVoltageOverride
The ring voltage override which is applied to the entire range of cpu ring frequencies.
Definition: OverclockingConfig.h:233
OVERCLOCKING_PREMEM_CONFIG::OcSupport
UINT32 OcSupport
Overclocking support.
Definition: OverclockingConfig.h:141
OVERCLOCKING_PREMEM_CONFIG::Etvb
UINT32 Etvb
Enhanced Thermal Turbo Mode (eTVB). 0:eTVB is disabled on supporting products 1:eTVB is enabled on su...
Definition: OverclockingConfig.h:285
OVERCLOCKING_PREMEM_CONFIG::RsvdByte4
UINT8 RsvdByte4
Reserved for dword alignment.
Definition: OverclockingConfig.h:349
OVERCLOCKING_PREMEM_CONFIG::IaIccUnlimitedMode
UINT32 IaIccUnlimitedMode
Support IA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:282
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
OVERCLOCKING_PREMEM_CONFIG::FivrEfficiency
UINT32 FivrEfficiency
Deprecated < Fivr Faults. Enable or Disable FIVR Faults. 0: Disabled, 1: Enabled.
Definition: OverclockingConfig.h:170
OVERCLOCKING_PREMEM_CONFIG::CoreRatioExtensionMode
UINT32 CoreRatioExtensionMode
Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MUL...
Definition: OverclockingConfig.h:193
OVERCLOCKING_PREMEM_CONFIG::AtomL2MaxOcRatio
UINT8 AtomL2MaxOcRatio
Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo...
Definition: OverclockingConfig.h:210
OVERCLOCKING_PREMEM_CONFIG::IaCepEnable
UINT32 IaCepEnable
Enable IA Current Excursion Protection. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:254
OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold1
UINT8 TvbTempThreshold1
TVB Temp (degrees C) - Temperature Threshold 1.
Definition: OverclockingConfig.h:469
OVERCLOCKING_PREMEM_CONFIG::SaVoltageMode
UINT32 SaVoltageMode
SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:192
OVERCLOCKING_PREMEM_CONFIG::DisablePerCoreMask
UINT32 DisablePerCoreMask
Core disable mask is a bitwise indication of which core should be disabled.
Definition: OverclockingConfig.h:410
OVERCLOCKING_PREMEM_CONFIG::GtPllVoltageOffset
UINT32 GtPllVoltageOffset
GT PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:250
OVERCLOCKING_PREMEM_CONFIG::DlvrBypassModeEnable
UINT32 DlvrBypassModeEnable
Enable CPU DLVR bypass mode support, 0: Disable. 0: Enable.
Definition: OverclockingConfig.h:259
OVERCLOCKING_PREMEM_CONFIG::CpuBclkOcFrequency
UINT32 CpuBclkOcFrequency
CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto....
Definition: OverclockingConfig.h:402
OVERCLOCKING_PREMEM_CONFIG::RingMaxOcRatio
UINT8 RingMaxOcRatio
Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio lim...
Definition: OverclockingConfig.h:205
OVERCLOCKING_PREMEM_CONFIG::Avx3RatioOffset
UINT32 Avx3RatioOffset
deprecated from version 28
Definition: OverclockingConfig.h:151
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOffset
INT16 AtomL2VoltageOffset
The atom L2 voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:366
OVERCLOCKING_PREMEM_CONFIG::SaVoltageOverride
UINT16 SaVoltageOverride
The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.
Definition: OverclockingConfig.h:372
OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold1
UINT8 TvbDownBinsTempThreshold1
Down Bins (delta) for Temperature Threshold 1.
Definition: OverclockingConfig.h:475
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOverride
UINT16 CoreVoltageOverride
The core voltage override which is applied to the entire range of cpu core frequencies.
Definition: OverclockingConfig.h:216
OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold0
UINT8 TvbTempThreshold0
TVB Temp (degrees C) - Temperature Threshold 0.
Definition: OverclockingConfig.h:463
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageMode
UINT32 CoreVoltageMode
Core voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:148
OVERCLOCKING_PREMEM_CONFIG::CoreVfConfigScope
UINT32 CoreVfConfigScope
Core VF Configuration Scope.
Definition: OverclockingConfig.h:184
OVERCLOCKING_PREMEM_CONFIG::PvdMode
UINT8 PvdMode
PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0).
Definition: OverclockingConfig.h:431
OVERCLOCKING_PREMEM_CONFIG::BclkAdaptiveVoltage
UINT32 BclkAdaptiveVoltage
Bclk Adaptive Voltage enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/F curves are a...
Definition: OverclockingConfig.h:152
OVERCLOCKING_PREMEM_CONFIG::McPllVoltageOffset
UINT32 McPllVoltageOffset
Memory Controller PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:253
OVERCLOCKING_PREMEM_CONFIG::PvdRatioThreshold
UINT8 PvdRatioThreshold
The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier so...
Definition: OverclockingConfig.h:425
OVERCLOCKING_PREMEM_CONFIG::PllMaxBandingRatio
UINT8 PllMaxBandingRatio
The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains.
Definition: OverclockingConfig.h:443
OVERCLOCKING_PREMEM_CONFIG::TvbVoltageOptimization
UINT32 TvbVoltageOptimization
This service controls thermal based voltage optimizations for processors that implement the Intel The...
Definition: OverclockingConfig.h:281
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageAdaptive
UINT16 AtomL2VoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operati...
Definition: OverclockingConfig.h:361
OVERCLOCKING_PREMEM_CONFIG::SaExtraTurboVoltage
UINT16 SaExtraTurboVoltage
Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is op...
Definition: OverclockingConfig.h:378
OVERCLOCKING_PREMEM_CONFIG::SaVoltageOffset
INT16 SaVoltageOffset
The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: 0=Default
Definition: OverclockingConfig.h:249
OVERCLOCKING_PREMEM_CONFIG::GtVoltageMode
UINT32 GtVoltageMode
Specifies whether GT voltage is operating in Adaptive or Override mode: 0=Adaptive,...
Definition: OverclockingConfig.h:167
OVERCLOCKING_PREMEM_CONFIG::OcLock
UINT32 OcLock
If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration sett...
Definition: OverclockingConfig.h:142
OVERCLOCKING_PREMEM_CONFIG::AtomPllVoltageOffset
UINT8 AtomPllVoltageOffset
Atom PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:401
OVERCLOCKING_PREMEM_CONFIG::CorePllVoltageOffset
UINT32 CorePllVoltageOffset
Core PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:149
OVERCLOCKING_PREMEM_CONFIG::TscDisableHwFixup
UINT32 TscDisableHwFixup
Core HW Fixup disable during TSC copy from PMA to APIC, 0: Enable. 1: Disable.
Definition: OverclockingConfig.h:261
OVERCLOCKING_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: OverclockingConfig.h:133
OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffsetMode
UINT8 RingVfPointOffsetMode
Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.
Definition: OverclockingConfig.h:385
OVERCLOCKING_PREMEM_CONFIG::SaPllVoltageOffset
UINT32 SaPllVoltageOffset
System Agent PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:252
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOffset
INT16 CoreVoltageOffset
The core voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:227
OVERCLOCKING_PREMEM_CONFIG::PerCoreRatioOverride
UINT32 PerCoreRatioOverride
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio...
Definition: OverclockingConfig.h:185
OVERCLOCKING_PREMEM_CONFIG::RingVoltageMode
UINT32 RingVoltageMode
Ring voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:166
OVERCLOCKING_PREMEM_CONFIG::RingPllVoltageOffset
UINT32 RingPllVoltageOffset
Ring PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:251
OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold0
UINT8 TvbDownBinsTempThreshold0
Down Bins (delta) for Temperature Threshold 0.
Definition: OverclockingConfig.h:457
OVERCLOCKING_PREMEM_CONFIG::GtExtraTurboVoltage
UINT16 GtExtraTurboVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal,...
Definition: OverclockingConfig.h:248
OVERCLOCKING_PREMEM_CONFIG::GtIccUnlimitedMode
UINT32 GtIccUnlimitedMode
Support GT Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:283
OVERCLOCKING_PREMEM_CONFIG::CoreMaxOcRatio
UINT8 CoreMaxOcRatio
Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ra...
Definition: OverclockingConfig.h:199
OVERCLOCKING_PREMEM_CONFIG::TvbRatioClipping
UINT32 TvbRatioClipping
This service controls Core frequency reduction caused by high package temperatures for processors tha...
Definition: OverclockingConfig.h:275
OVERCLOCKING_PREMEM_CONFIG::TjMaxOffset
UINT8 TjMaxOffset
TjMax Offset.
Definition: OverclockingConfig.h:267
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageMode
UINT8 AtomL2VoltageMode
Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating.
Definition: OverclockingConfig.h:348
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: P2sbConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
Classes
P2sbConfig.h File Reference

P2sb policy. More...

Go to the source code of this file.

Classes

struct PCH_P2SB_CONFIG
This structure contains the policies which are related to P2SB device. More...

Detailed Description

P2sb policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file P2sbConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: P2sbConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
P2sbConfig.h
Go to the documentation of this file.
1 /** @file
2 P2sb policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _P2SB_CONFIG_H_
36 #define _P2SB_CONFIG_H_
37
38 #define PCH_P2SB_CONFIG_REVISION 1
39 extern EFI_GUID gP2sbConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure contains the policies which are related to P2SB device.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 <b>(Test)</b>
50 The sideband MMIO register access to specific ports will be locked
51 before 3rd party code execution. Currently it disables PSFx access.
52 This policy unlocks the sideband MMIO space for those IPs.
53 <b>0: Lock sideband access </b>; 1: Unlock sideband access.
54 NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.
55 **/
56 UINT32 SbAccessUnlock : 1;
57 UINT32 Rsvdbits : 31; ///< Reserved bits
58 } PCH_P2SB_CONFIG;
59
60 #pragma pack (pop)
61
62 #endif // _P2SB_CONFIG_H_
PCH_P2SB_CONFIG
This structure contains the policies which are related to P2SB device.
Definition: P2sbConfig.h:46
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_P2SB_CONFIG::Rsvdbits
UINT32 Rsvdbits
Reserved bits.
Definition: P2sbConfig.h:57
PCH_P2SB_CONFIG::SbAccessUnlock
UINT32 SbAccessUnlock
(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execu...
Definition: P2sbConfig.h:56
PCH_P2SB_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: P2sbConfig.h:47
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchDmiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
Classes
PchDmiConfig.h File Reference

DMI policy. More...

Go to the source code of this file.

Classes

struct | PCH_DMI_EQ_PARAM
Lane specific Dmi Gen3, Gen4 equalization parameters. More...
struct | PCH_DMI_CONFIG
The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. More...

Detailed Description

DMI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchDmiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
PchDmiConfig.h
Go to the documentation of this file.
1 /** @file
2 DMI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_DMI_CONFIG_H_
36 #define _PCH_DMI_CONFIG_H_
37
38 #define PCH_DMI_CONFIG_REVISION 1
39 extern EFI_GUID gPchDmiConfigGuid;
40
41 /*
42 <b>Revision 1</b>: - Initial version.
43 <b>Revision 2</b>: - Added Policies to support FOM
44 */
45 #define PCH_DMI_PREMEM_CONFIG_REVISION 2
46 extern EFI_GUID gPchDmiPreMemConfigGuid;
47
48 #pragma pack (push,1)
49
50 #define PCH_DMI_HWEQ_COEFFS_MAX 8
51 /**
52 Lane specific Dmi Gen3, Gen4 equalization parameters.
53 **/
54 typedef struct {
55 UINT8 Cm; ///< Coefficient C-1
56 UINT8 Cp; ///< Coefficient C+1
57 UINT8 Rsvd0[2]; ///< Reserved bytes
58 } PCH_DMI_EQ_PARAM;
59
60 typedef struct {
61 CONFIG_BLOCK_HEADER Header; ///< Config Block
62 PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX];
63 UINT8 DmiHweq;
64 UINT8 Reserved[3];
65 } PCH_DMI_PREMEM_CONFIG;
66
67
68 /**
69 The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
70 <b>Revision 1</b>:
71 - Initial version.
72 **/
73 typedef struct {
74 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
75
76 UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
77 UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
78 UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
79 UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
80 /**
81 When set to TRUE turns on:
82 - L1 State Controller Power Gating
83 - L1 State PHY Data Lane Power Gating
84 - PHY Common Lane Power Gating
85 - Hardware Autonomous Enable
86 - PMC Request Enable and Sleep Enable
87 **/
88 UINT32 DmiPowerReduction : 1;
89 UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
90 UINT32 Rsvdbits : 19; ///< Reserved bits
91 } PCH_DMI_CONFIG;
92
93 #pragma pack (pop)
94
95 #endif // _PCH_DMI_CONFIG_H_
PCH_DMI_CONFIG::PwrOptEnable
UINT32 PwrOptEnable
0: Disable; 1: Enable DMI Power Optimizer on PCH side.
Definition: PchDmiConfig.h:76
PCH_DMI_CONFIG::DmiAspmCtrl
UINT32 DmiAspmCtrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
Definition: PchDmiConfig.h:77
PCH_DMI_CONFIG
The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
Definition: PchDmiConfig.h:73
PCH_DMI_CONFIG::Rsvdbits
UINT32 Rsvdbits
Reserved bits.
Definition: PchDmiConfig.h:90
PCH_DMI_CONFIG::DmiPowerReduction
UINT32 DmiPowerReduction
When set to TRUE turns on:
Definition: PchDmiConfig.h:88
PCH_DMI_CONFIG::CwbEnable
UINT32 CwbEnable
0: Disable; 1: Enable Central Write Buffer feature configurable and enabled by default
Definition: PchDmiConfig.h:78
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_DMI_EQ_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: PchDmiConfig.h:56
PCH_DMI_CONFIG::ClockGating
UINT32 ClockGating
0: Disable; 1: Enable clock gating.
Definition: PchDmiConfig.h:89
PCH_DMI_CONFIG::L1RpCtl
UINT32 L1RpCtl
0: Disable; 1: Enable Allow DMI enter L1 when all root ports are in L1, L0s or link down....
Definition: PchDmiConfig.h:79
PCH_DMI_EQ_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: PchDmiConfig.h:55
PCH_DMI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchDmiConfig.h:74
PCH_DMI_EQ_PARAM
Lane specific Dmi Gen3, Gen4 equalization parameters.
Definition: PchDmiConfig.h:54
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchGeneralConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
Classes | Enumerations
PchGeneralConfig.h File Reference

PCH General policy. More...

Go to the source code of this file.

Classes

struct | PCH_GENERAL_CONFIG
PCH General Configuration Revision 1: - Initial version. More...
struct | PCH_GENERAL_PREMEM_CONFIG
PCH General Pre-Memory Configuration Revision 1: - Initial version. More...

Enumerations

enum PCH_RESERVED_PAGE_ROUTE

Detailed Description

PCH General policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchGeneralConfig.h.

Enumeration Type Documentation

◆ PCH_RESERVED_PAGE_ROUTE

enum PCH_RESERVED_PAGE_ROUTE
Enumerator
PchReservedPageToLpc | Port 80h cycles are sent to LPC.
PchReservedPageToPcie | Port 80h cycles are sent to PCIe.

Definition at line 46 of file PchGeneralConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchGeneralConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
PchGeneralConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH General policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_GENERAL_CONFIG_H_
36 #define _PCH_GENERAL_CONFIG_H_
37
38 #define PCH_GENERAL_CONFIG_REVISION 2
39 #define PCH_GENERAL_PREMEM_CONFIG_REVISION 3
40
41 extern EFI_GUID gPchGeneralConfigGuid;
42 extern EFI_GUID gPchGeneralPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 enum PCH_RESERVED_PAGE_ROUTE {
47 PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
48 PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
49 };
50
51 /**
52 PCH General Configuration
53 <b>Revision 1</b>: - Initial version.
54 <b>Revision 2</b>: - Added AcpiL6dPmeHandling
55 **/
56 typedef struct {
57 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
58 /**
59 This member describes whether or not the Compatibility Revision ID (CRID) feature
60 of PCH should be enabled. <b>0: Disable</b>; 1: Enable
61 **/
62 UINT32 Crid : 1;
63 /**
64 Set to enable low latency of legacy IO.
65 Some systems require lower IO latency irrespective of power.
66 This is a tradeoff between power and IO latency.
67 @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
68 and ITSS Clock Gating are forced to disabled.
69 <b>0: Disable</b>, 1: Enable
70 **/
71 UINT32 LegacyIoLowLatency : 1;
72 /**
73 Enables _L6D ACPI handler.
74 PME GPE is shared by multiple devices So BIOS must verify the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit
75 <b>0: Disable</b>, 1: Enable
76 **/
77 UINT32 AcpiL6dPmeHandling : 1;
78 UINT32 RsvdBits0 : 29; ///< Reserved bits
79 } PCH_GENERAL_CONFIG;
80
81 /**
82 PCH General Pre-Memory Configuration
83 <b>Revision 1</b>: - Initial version.
84 <b>Revision 2</b>: - Added GpioOverride.
85 <b>Revision 3</b>: - Added IoeDebugEn, PmodeClkEn
86 **/
87 typedef struct {
88 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
89 /**
90 Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
91 **/
92 UINT32 Port80Route : 1;
93 UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SSC for A0 PO
94 /**
95 Gpio override Level
96 -- <b>0: Disable</b>;
97 - 1: Override Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase
98 - 2: Override Level 2 - Reserved for future use
99 **/
100 UINT32 GpioOverride : 3;
101 /**
102 Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link and clock will keep up for debug
103 <b>0: Disable</b>; 1: Enable
104 **/
105 UINT32 IoeDebugEn : 1;
106 /**
107 Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use
108 <b>0: Disable</b>; 1: Enable
109 **/
110 UINT32 PmodeClkEn : 1;
111 UINT32 RsvdBits0 : 25; ///< Reserved bits
112 } PCH_GENERAL_PREMEM_CONFIG;
113
114 #pragma pack (pop)
115
116 #endif // _PCH_GENERAL_CONFIG_H_
PCH_GENERAL_PREMEM_CONFIG::IotgPllSscEn
UINT32 IotgPllSscEn
Need to disable CPU Side SSC for A0 PO.
Definition: PchGeneralConfig.h:93
PCH_RESERVED_PAGE_ROUTE
PCH_RESERVED_PAGE_ROUTE
Definition: PchGeneralConfig.h:46
PCH_GENERAL_PREMEM_CONFIG::Port80Route
UINT32 Port80Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
Definition: PchGeneralConfig.h:92
PCH_GENERAL_CONFIG::LegacyIoLowLatency
UINT32 LegacyIoLowLatency
Set to enable low latency of legacy IO.
Definition: PchGeneralConfig.h:71
PCH_GENERAL_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchGeneralConfig.h:57
PCH_GENERAL_PREMEM_CONFIG::GpioOverride
UINT32 GpioOverride
Gpio override Level – 0: Disable;.
Definition: PchGeneralConfig.h:100
PCH_GENERAL_CONFIG::Crid
UINT32 Crid
This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be en...
Definition: PchGeneralConfig.h:62
PCH_GENERAL_CONFIG::AcpiL6dPmeHandling
UINT32 AcpiL6dPmeHandling
Enables _L6D ACPI handler.
Definition: PchGeneralConfig.h:77
PCH_GENERAL_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchGeneralConfig.h:88
PCH_GENERAL_PREMEM_CONFIG::IoeDebugEn
UINT32 IoeDebugEn
Enable/Disable IOE Debug.
Definition: PchGeneralConfig.h:105
PchReservedPageToPcie
@ PchReservedPageToPcie
Port 80h cycles are sent to PCIe.
Definition: PchGeneralConfig.h:48
PCH_GENERAL_PREMEM_CONFIG::PmodeClkEn
UINT32 PmodeClkEn
Enable/Disable PMODE clock.
Definition: PchGeneralConfig.h:110
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PchReservedPageToLpc
@ PchReservedPageToLpc
Port 80h cycles are sent to LPC.
Definition: PchGeneralConfig.h:47
PCH_GENERAL_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PchGeneralConfig.h:111
PCH_GENERAL_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PchGeneralConfig.h:78
PCH_GENERAL_PREMEM_CONFIG
PCH General Pre-Memory Configuration Revision 1: - Initial version.
Definition: PchGeneralConfig.h:87
PCH_GENERAL_CONFIG
PCH General Configuration Revision 1: - Initial version.
Definition: PchGeneralConfig.h:56
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchPcieRpConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
Classes | Enumerations
PchPcieRpConfig.h File Reference

PCH Pcie root port policy. More...

#include <PchLimits.h>
#include <PcieConfig.h>
#include <ConfigBlock.h>
Include dependency graph for PchPcieRpConfig.h:

Go to the source code of this file.

Classes

struct | PCH_PCIE_CLOCK
PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. More...
struct | PCH_PCIE_ROOT_PORT_CONFIG
The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. More...
struct | PCH_PCIE_CONFIG
The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1: More...
struct | PCH_PCIE_RP_PREMEM_CONFIG
The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1: More...
struct | PCIE_RP_DXE_CONFIG
The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase. More...

Enumerations

enum | PCH_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature.
enum | PCH_PCIE_L1SUBSTATES_CONTROL
Refer to PCH EDS for the PCH implementation values corresponding to below PCI-E spec defined ranges.
enum | PCH_PCIE_CLOCK_USAGE

Detailed Description

PCH Pcie root port policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcieRpConfig.h.

Enumeration Type Documentation

◆ PCH_PCIE_CLOCK_USAGE

enum PCH_PCIE_CLOCK_USAGE
Enumerator
PchClockUsageCpuPcie0

Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silicon generations and series.

Do not assume that PCH port 0 will be always encoded by 0. Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortIndex) style to be forward-compatible

PchClockUsageUnspecified

In use for a purpose not listed above.

Definition at line 134 of file PchPcieRpConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchPcieRpConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
PchPcieRpConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH Pcie root port policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PCIERP_CONFIG_H_
36 #define _PCH_PCIERP_CONFIG_H_
37
38 #include <PchLimits.h>
39 #include <PcieConfig.h>
40 #include <ConfigBlock.h>
41
42 /*
43 Making any setup structure change after code frozen
44 will need to maintain backward compatibility, bump up
45 structure revision and update below history table\n
46
47 <b>Revision 1</b>: - Initial version.
48 <b>Revision 2</b>:
49 FomsCp - Deprecated
50 <b>Revision 3</b>:
51 Added PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
52 Added PCIE_EQ_PARAM HwEqGen4CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
53 Added PCIE_EQ_PARAM HwEqGen5CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
54 <b>Revision 4</b>:
55 AllowL0sWithGen3 - Deprecated
56 Moved EnablePeerMemoryWrite policy from PCIE_COMMON_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
57 Moved ClockGating policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
58 Moved PowerGating policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
59 Moved EnablePort8xhDecode policy form PCH_PCIE_CONFIG to PCIE_COMMON_CONFIG
60 Added LinkDownGpios policy to PCIE_ROOT_PORT_COMMON_CONFIG
61 <b>Revision 5</b>:
62 Deprecated PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
63 <b>Revision 6</b>:
64 Move PcieGen3LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
65 Move PcieGen4LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
66 Move PcieGen5LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
67 Move OverrideEqualizationDefaults policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
68 */
69 #define PCH_PCIE_CONFIG_REVISION 6
70
71 /*
72 Making any setup structure change after code frozen
73 will need to maintain backward compatibility, bump up
74 structure revision and update below history table\n
75
76 <b>Revision 1</b>: - Initial version.
77 */
78 #define PCH_PCIE_RP_PREMEM_CONFIG_REVISION 2
79
80 /*
81 Making any setup structure change after code frozen
82 will need to maintain backward compatibility, bump up
83 structure revision and update below history table\n
84
85 <b>Revision 1</b>: - Initial version.
86 */
87 #define PCIE_RP_DXE_CONFIG_REVISION 1
88
89 extern EFI_GUID gPchPcieConfigGuid;
90 extern EFI_GUID gPcieRpPreMemConfigGuid;
91
92 #pragma pack (push,1)
93
94 typedef enum {
95 PchPcieOverrideDisabled = 0,
96 PchPcieL1L2Override = 0x01,
97 PchPcieL1SubstatesOverride = 0x02,
98 PchPcieL1L2AndL1SubstatesOverride = 0x03,
99 PchPcieLtrOverride = 0x04
100 } PCH_PCIE_OVERRIDE_CONFIG;
101
102 ///
103 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
104 ///
105 typedef enum {
106 PchPcieAspmDisabled,
107 PchPcieAspmL0s,
108 PchPcieAspmL1,
109 PchPcieAspmL0sL1,
110 PchPcieAspmAutoConfig,
111 PchPcieAspmMax
112 } PCH_PCIE_ASPM_CONTROL;
113
114 /**
115 Refer to PCH EDS for the PCH implementation values corresponding
116 to below PCI-E spec defined ranges
117 **/
118 typedef enum {
119 PchPcieL1SubstatesDisabled,
120 PchPcieL1SubstatesL1_1,
121 PchPcieL1SubstatesL1_1_2,
122 PchPcieL1SubstatesMax
123 } PCH_PCIE_L1SUBSTATES_CONTROL;
124
125 enum PCH_PCIE_MAX_PAYLOAD {
126 PchPcieMaxPayload128 = 0,
127 PchPcieMaxPayload256,
128 PchPcieMaxPayloadMax
129 };
130
131 #define PCH_PCIE_NO_SUCH_CLOCK 0xFF
132 #define PCH_PCIE_NO_GPIO_MUXING 0x00
133
134 typedef enum {
135 PchClockUsagePchPcie0 = 0,
136 PchClockUsagePchPcie1 = 1,
137 PchClockUsagePchPcie2 = 2,
138 PchClockUsagePchPcie3 = 3,
139 PchClockUsagePchPcie4 = 4,
140 PchClockUsagePchPcie5 = 5,
141 PchClockUsagePchPcie6 = 6,
142 PchClockUsagePchPcie7 = 7,
143 PchClockUsagePchPcie8 = 8,
144 PchClockUsagePchPcie9 = 9,
145 PchClockUsagePchPcie10 = 10,
146 PchClockUsagePchPcie11 = 11,
147 PchClockUsagePchPcie12 = 12,
148 PchClockUsagePchPcie13 = 13,
149 PchClockUsagePchPcie14 = 14,
150 PchClockUsagePchPcie15 = 15,
151 PchClockUsagePchPcie16 = 16,
152 PchClockUsagePchPcie17 = 17,
153 PchClockUsagePchPcie18 = 18,
154 PchClockUsagePchPcie19 = 19,
155 PchClockUsagePchPcie20 = 20,
156 PchClockUsagePchPcie21 = 21,
157 PchClockUsagePchPcie22 = 22,
158 PchClockUsagePchPcie23 = 23,
159 /**
160 Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between
161 silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0.
162 Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortIndex) style to be forward-compatible
163 **/
164 PchClockUsageCpuPcie0 = 0x40,
165 PchClockUsageCpuPcie1 = 0x41,
166 PchClockUsageCpuPcie2 = 0x42,
167 PchClockUsageCpuPcie3 = 0x43,
168
169 PchClockUsageLan = 0x70,
170 PchClockUsageUnspecified = 0x80, ///< In use for a purpose not listed above
171 PchClockUsageNotUsed = 0xFF
172 } PCH_PCIE_CLOCK_USAGE;
173
174 /**
175 PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
176 **/
177 typedef struct {
178 UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
179 UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
180 UINT8 RsvdBytes[2]; ///< Reserved byte
181 UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SRC_CLKREQ_x*
182 } PCH_PCIE_CLOCK;
183
184
185 /**
186 The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
187 **/
188 typedef struct {
189 PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
190 UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
191 //
192 // Error handlings
193 //
194 UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
195 /**
196 The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
197 Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
198 DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
199 RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
200 disabled.
201 <b>0: Disable</b>; 1: Enable
202 **/
203 UINT8 MvcEnabled;
204 /**
205 Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
206 when GPIO pins expansion is needed. It is server specific feature.
207 <b>0x00: Default</b>; 0xFF: Disabled
208 **/
209 UINT8 VppPort;
210 UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
211 UINT8 RsvdBytes0[3]; ///< Reserved bytes
212 } PCH_PCIE_ROOT_PORT_CONFIG;
213
214 /**
215 The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
216 <b>Revision 1</b>:
217 - Initial version.
218 <b>Revision 2</b>:
219 - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
220 **/
221 typedef struct {
222 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
223 ///
224 /// These members describe the configuration of each PCH PCIe root port.
225 ///
226 PCIE_COMMON_CONFIG PcieCommonConfig;
227 PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
228 PCH_PCIE_ROOT_PORT_CONFIG DmiPort;
229
230 ///
231 /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
232 ///
233 UINT8 PchPciePort8xhDecodePortIndex;
234 UINT8 DmiPowerReduction;
235 UINT8 RsvdBytes0[2];
236 } PCH_PCIE_CONFIG;
237
238 /**
239 The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
240 <b>Revision 1</b>:
241 - Initial version.
242 **/
243 typedef struct {
244 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
245 /**
246 Root Port enabling mask.
247 Bit0 presents RP1, Bit1 presents RP2, and so on.
248 0: Disable; <b>1: Enable</b>.
249 **/
250 UINT32 RpEnabledMask;
251 /// Configuration of PCIe source clocks
252 ///
253 PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
254
255 /**
256 Per Controller Bifurcation Configuration
257 <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
258 **/
259 UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
260 UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
261 } PCH_PCIE_RP_PREMEM_CONFIG;
262
263 /**
264 The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
265
266 <b>Revision 1</b>:
267 - Init version
268 **/
269 typedef struct {
270 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
271
272 /**
273 PCIe device override table
274 The PCIe device table is being used to override PCIe device ASPM settings.
275 And it's only used in DXE phase.
276 Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
277 Last entry VendorId must be 0.
278 **/
279 PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
280 } PCIE_RP_DXE_CONFIG;
281
282 #pragma pack (pop)
283
284 #endif // _PCH_PCIERP_CONFIG_H_
PCH_PCIE_CLOCK::ClkReq
UINT8 ClkReq
ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers.
Definition: PchPcieRpConfig.h:179
PCH_PCIE_CLOCK::Usage
UINT8 Usage
Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF.
Definition: PchPcieRpConfig.h:178
PCIE_RP_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:270
PCH_PCIE_CONFIG::PchPciePort8xhDecodePortIndex
UINT8 PchPciePort8xhDecodePortIndex
(Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
Definition: PchPcieRpConfig.h:233
ConfigBlock.h
Header file for Config Block Lib implementation.
PCH_PCIE_CONFIG::PcieCommonConfig
PCIE_COMMON_CONFIG PcieCommonConfig
These members describe the configuration of each PCH PCIe root port.
Definition: PchPcieRpConfig.h:226
PCH_PCIE_ROOT_PORT_CONFIG::ExtSync
UINT8 ExtSync
an instance of Pcie Common Config
Definition: PchPcieRpConfig.h:190
PCH_PCIE_CLOCK
PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
Definition: PchPcieRpConfig.h:177
PCH_PCIE_L1SUBSTATES_CONTROL
PCH_PCIE_L1SUBSTATES_CONTROL
Refer to PCH EDS for the PCH implementation values corresponding to below PCI-E spec defined ranges.
Definition: PchPcieRpConfig.h:118
PCH_PCIE_ASPM_CONTROL
PCH_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1....
Definition: PchPcieRpConfig.h:105
PchClockUsageUnspecified
@ PchClockUsageUnspecified
In use for a purpose not listed above.
Definition: PchPcieRpConfig.h:170
PCH_PCIE_ROOT_PORT_CONFIG::VppAddress
UINT8 VppAddress
PCIe Hot Plug VPP SMBus Address. Default is zero.
Definition: PchPcieRpConfig.h:210
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PchClockUsageCpuPcie0
@ PchClockUsageCpuPcie0
Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silico...
Definition: PchPcieRpConfig.h:164
PCH_PCIE_ROOT_PORT_CONFIG::SystemErrorEnable
UINT8 SystemErrorEnable
Indicate whether the System Error is enabled. 0: Disable; 1: Enable.
Definition: PchPcieRpConfig.h:194
PCH_PCIE_CONFIG
The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Rev...
Definition: PchPcieRpConfig.h:221
PCIE_RP_DXE_CONFIG
The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers ...
Definition: PchPcieRpConfig.h:269
PCH_PCIE_ROOT_PORT_CONFIG
The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
Definition: PchPcieRpConfig.h:188
PCH_PCIE_RP_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:244
PCH_PCIE_ROOT_PORT_CONFIG::VppPort
UINT8 VppPort
Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins e...
Definition: PchPcieRpConfig.h:209
PCH_PCIE_ROOT_PORT_CONFIG::MvcEnabled
UINT8 MvcEnabled
The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
Definition: PchPcieRpConfig.h:203
PCH_PCIE_CLOCK_USAGE
PCH_PCIE_CLOCK_USAGE
Definition: PchPcieRpConfig.h:134
PCH_PCIE_RP_PREMEM_CONFIG
The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers ...
Definition: PchPcieRpConfig.h:243
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:287
PcieConfig.h
PCIe Config Block.
PCH_PCIE_RP_PREMEM_CONFIG::RpEnabledMask
UINT32 RpEnabledMask
Root Port enabling mask.
Definition: PchPcieRpConfig.h:250
PCIE_RP_DXE_CONFIG::PcieDeviceOverrideTablePtr
PCIE_DEVICE_OVERRIDE * PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.
Definition: PchPcieRpConfig.h:279
PCH_PCIE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:222
PCIE_DEVICE_OVERRIDE
PCIe device table entry entry.
Definition: PcieConfig.h:337
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PcieConfig.h File Reference

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Classes | Enumerations
PcieConfig.h File Reference

PCIe Config Block. More...

#include <CpuPcieInfo.h>
Include dependency graph for PcieConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters. More...
struct | PCIE_LINK_EQ_PLATFORM_SETTINGS
PCIe Link EQ Platform Settings. More...
struct | PCIE_COMMON_CONFIG
PCIe Common Config. More...
struct | PCIE_DEVICE_OVERRIDE
PCIe device table entry entry. More...

Enumerations

enum | PCIE_FORM_FACTOR
Specifies the form factor that the slot implements. More...
enum | PCIE_LINK_EQ_METHOD
enum | PCIE_LINK_EQ_MODE

Detailed Description

PCIe Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PcieConfig.h.

Enumeration Type Documentation

◆ PCIE_FORM_FACTOR

enum PCIE_FORM_FACTOR

Specifies the form factor that the slot implements.

For custom form factors that do not require any special handling please set PcieFormFactorOther.

Definition at line 103 of file PcieConfig.h.

◆ PCIE_LINK_EQ_METHOD

enum PCIE_LINK_EQ_METHOD
Enumerator
PcieLinkHardwareEq | Hardware is responsible for performing coefficient/preset search.
PcieLinkFixedEq | No coefficient/preset search is performed. Fixed values are used.

Definition at line 114 of file PcieConfig.h.

◆ PCIE_LINK_EQ_MODE

enum PCIE_LINK_EQ_MODE
Enumerator
PcieLinkEqPresetMode | Use presets during PCIe link equalization.
PcieLinkEqCoefficientMode | Use coefficients during PCIe link equalization.

Definition at line 119 of file PcieConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PcieConfig.h Source File

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  • PcieRp
PcieConfig.h
Go to the documentation of this file.
1 /** @file
2 PCIe Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_CONFIG_H_
36 #define _PCIE_CONFIG_H_
37 #include <CpuPcieInfo.h>
38
39 #define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
40 #define PCIE_LINK_EQ_PRESETS_MAX 11
41 extern EFI_GUID gPcieConfigGuid;
42
43 #pragma pack (push,1)
44
45 enum PCIE_COMPLETION_TIMEOUT {
46 PcieCompletionTO_Default,
47 PcieCompletionTO_50_100us,
48 PcieCompletionTO_1_10ms,
49 PcieCompletionTO_16_55ms,
50 PcieCompletionTO_65_210ms,
51 PcieCompletionTO_260_900ms,
52 PcieCompletionTO_1_3P5s,
53 PcieCompletionTO_4_13s,
54 PcieCompletionTO_17_64s,
55 PcieCompletionTO_Disabled
56 };
57
58 typedef enum {
59 PcieAuto,
60 PcieGen1,
61 PcieGen2,
62 PcieGen3,
63 PcieGen4,
64 PcieGen5
65 } PCIE_SPEED;
66
67 typedef enum {
68 PcieDisabled,
69 PcieL1SUB_1,
70 PcieL1SUB_1_2
71 }L1_SUBSTATES;
72
73 /**
74 Represent lane specific PCIe Gen3 equalization parameters.
75 **/
76 typedef struct {
77 UINT8 Cm; ///< Coefficient C-1
78 UINT8 Cp; ///< Coefficient C+1
79 UINT8 Rsvd0[2]; ///< Reserved bytes
80 } PCIE_EQ_PARAM;
81
82 typedef struct {
83 UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
84 UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
85 UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
86 UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
87 UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
88 UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
89 UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
90 UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
91 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
92 UINT8 ForceLtrOverride;
93 UINT16 RsvdByte1;
94 } PCIE_LTR_CONFIG;
95
96
97 /**
98 Specifies the form factor that the slot
99 implements. For custom form factors that
100 do not require any special handling please
101 set PcieFormFactorOther.
102 **/
103 typedef enum {
104 PcieFormFactorOther = 0,
105 PcieFormFactorCem,
106 PcieFormFactorMiniPci,
107 PcieFormFactorM2,
108 PcieFormFactorOcuLink,
109 PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
110 PcieFormFactorExpressCard,
111 PcieFormFactorU2 // Also known as SF-8639
112 } PCIE_FORM_FACTOR;
113
114 typedef enum {
115 PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
116 PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
117 } PCIE_LINK_EQ_METHOD;
118
119 typedef enum {
120 PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
121 PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
122 } PCIE_LINK_EQ_MODE;
123
124 typedef struct {
125 UINT32 PreCursor; ///< Pre-cursor coefficient
126 UINT32 PostCursor; ///< Post-cursor coefficient
127 } PCIE_LINK_EQ_COEFFICIENTS;
128
129 /**
130 PCIe Link EQ Platform Settings
131 **/
132 typedef struct {
133 UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
134 UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
135 /**
136 Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
137 If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
138 <b>0: Disabled</b>; 1: Enabled
139 **/
140 UINT8 LocalTransmitterOverrideEnable;
141 /**
142 Tells BIOS how many presets/coefficients should be used during link EQ.
143 Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
144 **/
145 UINT8 Ph3NumberOfPresetsOrCoefficients;
146
147 PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
148 UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
149 UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
150 UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
151 /**
152 Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
153 Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port.
154 Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
155 **/
156 UINT32 Ph2LocalTransmitterOverridePreset;
157 UINT32 PCETTimer; ///< PCET Timer value for single PCIe speed.
158 UINT8 RemotePresetCoeffoverride; ///< Remote Transmitter Preset Coefficient Override for single PCIe speed.
159 /**
160 PCIe Equalization Phase 3 Enable Control
161 - <b>Disabled</b> (0x0) : Disable phase 3 (Default)
162 - Enabled (0x1) : Enable phase 3
163 **/
164 UINT8 EqPh3Bypass;
165 /**
166 PCIe Equalization Phase 2-3 Enable Control
167 - <b>Disabled</b> (0x0) : Disable Phase 2 - Phase 3 (Default)
168 - Enabled (0x1) : Enable Phase 2 - Phase 3
169 **/
170 UINT8 EqPh23Bypass;
171 UINT8 TsLockTimer; ///< 8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
172 } PCIE_LINK_EQ_PLATFORM_SETTINGS;
173
174 //Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
175 typedef struct {
176 UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
177 UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
178 UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
179 UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
180 //
181 // Error handlings
182 //
183 UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
184 UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
185 UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
186 UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
187 UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
188 UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
189 UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
190 UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
191 /**
192 Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
193 Changes Max Payload Size Supported field in Device Capabilities of the root port.
194 **/
195 UINT32 MaxPayload : 2;
196 UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
197 UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
198 /**
199 Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
200 Built-in is incompatible with hotplug-capable ports.
201 **/
202 UINT32 SlotImplemented : 1;
203 UINT32 PtmEnabled : 1; ///< Enables PTM capability
204 UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
205 UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
206 /**
207 Probe CLKREQ# signal before enabling CLKREQ# based power management.
208 Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
209 to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
210 In particular this helps to avoid issues with open-ended PCIe slots.
211 This is only applicable to non hot-plug ports.
212 <b>0: Disable</b>; 1: Enable.
213 **/
214 UINT32 ClkReqDetect : 1;
215 /**
216 Set if the slot supports manually operated retention latch.
217 **/
218 UINT32 MrlSensorPresent : 1;
219 UINT32 RelaxedOrder : 1;
220 UINT32 NoSnoop : 1;
221 ///
222 /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
223 ///
224 UINT32 EnablePeerMemoryWrite : 1;
225 ///
226 /// This member describes whether the PCI Express Clock Gating for each root port
227 /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
228 ///
229 UINT32 ClockGating : 1;
230 ///
231 /// This member describes whether the PCI Express Power Gating for each root port
232 /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
233 ///
234 UINT32 PowerGating : 1;
235 UINT32 RsvdBits0 : 25; ///< Reserved bits.
236 /**
237 PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
238 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
239 **/
240 UINT8 Gen3EqPh3Method;
241 UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
242 UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
243 //
244 // Power Management
245 //
246 UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
247 UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
248 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
249 UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
250 UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
251 /**
252 <b>(Test)</b>
253 Forces LTR override to be permanent
254 The default way LTR override works is:
255 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
256 This settings allows force override of LTR mechanism. If it's enabled, then:
257 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
258 **/
259 PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
260 /**
261 The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
262 before assuming there is no device and potentially disabling the port.
263 It's assumed that the link will exit detect state before root port initialization (sufficient time
264 elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
265 if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
266 In case of non-common clock enabled the default timout is 15ms.
267 <b>Default: 0</b>
268 **/
269 UINT16 DetectTimeoutMs;
270 UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
271 UINT8 L1Low; ///< L1.LOW enable/disable. <b>0: Disable</b>; 1: Enable.
272 UINT8 LinkDownGpios;
273 ///
274 /// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
275 ///
276 UINT8 OverrideEqualizationDefaults;
277 UINT8 Reserved[2];
278 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ for every port.
279 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ for every port.
280 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ for every port.
281 } PCIE_ROOT_PORT_COMMON_CONFIG;
282
283 /**
284 PCIe Common Config
285 @note This structure will be expanded to hold all common PCIe policies between SA and PCH
286 **/
287 typedef struct {
288 /**
289 RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
290 A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
291 BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
292 - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
293 This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
294 - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
295 That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
296 NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
297 In other words, it only affects ports that would become hidden because they have no device connected.
298 NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
299 be used when each one of root ports 1, 9, 17:
300 - is configured as PCIe and has correctly configured ClkReq signal, or
301 - does not own any mPhy lanes (they are configured as SATA or USB)
302 **/
303 UINT32 RpFunctionSwap : 1;
304 /**
305 Compliance Test Mode shall be enabled when using Compliance Load Board.
306 <b>0: Disable</b>, 1: Enable
307 **/
308 UINT32 ComplianceTestMode : 1;
309 UINT32 RsvdBits0 : 30; ///< Reserved bits
310 ///
311 /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
312 ///
313 UINT8 EnablePort8xhDecode;
314 UINT8 RsvdBytes0[3];
315 ///
316 /// List of coefficients used during equalization (applicable to both software and hardware EQ)
317 /// Deprecated Policy
318 ///
319 PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
320 } PCIE_COMMON_CONFIG;
321
322 typedef struct {
323 PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
324 PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
325 PCIE_EQ_PARAM HwEqGen5CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
326 } PCIE_COMMON_CONFIG2;
327
328
329 /**
330 PCIe device table entry entry
331
332 The PCIe device table is being used to override PCIe device ASPM settings.
333 To take effect table consisting of such entries must be instelled as PPI
334 on gPchPcieDeviceTablePpiGuid.
335 Last entry VendorId must be 0.
336 **/
337 typedef struct {
338 UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
339 UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
340 UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
341 UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
342 UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
343 UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
344 ///< Bit 1 must be set in OverrideConfig for this field to take effect
345 UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
346 /**
347 The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
348 This field can be zero if only the L1 Substate value is going to be override.
349 **/
350 UINT16 L1SubstatesCapOffset;
351 /**
352 L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
353 Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
354 Only bit [3:0] are applicable. Other bits are ignored.
355 **/
356 UINT8 L1SubstatesCapMask;
357 /**
358 L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
359 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
360 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
361 and only L1SubstatesCapOffset is override.
362 **/
363 UINT8 L1sCommonModeRestoreTime;
364 /**
365 L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
366 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
367 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
368 and only L1SubstatesCapOffset is override.
369 **/
370 UINT8 L1sTpowerOnScale;
371 /**
372 L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
373 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
374 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
375 and only L1SubstatesCapOffset is override.
376 **/
377 UINT8 L1sTpowerOnValue;
378
379 /**
380 SnoopLatency bit definition
381 Note: All Reserved bits must be set to 0
382
383 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
384 When clear values in bits 9:0 will be ignored
385 BITS[14:13] - Reserved
386 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
387 000b - 1 ns
388 001b - 32 ns
389 010b - 1024 ns
390 011b - 32,768 ns
391 100b - 1,048,576 ns
392 101b - 33,554,432 ns
393 110b - Reserved
394 111b - Reserved
395 BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
396 the scale in bits 12:10
397
398 This field takes effect only if bit 3 is set in OverrideConfig.
399 **/
400 UINT16 SnoopLatency;
401 /**
402 NonSnoopLatency bit definition
403 Note: All Reserved bits must be set to 0
404
405 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
406 When clear values in bits 9:0 will be ignored
407 BITS[14:13] - Reserved
408 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
409 000b - 1 ns
410 001b - 32 ns
411 010b - 1024 ns
412 011b - 32,768 ns
413 100b - 1,048,576 ns
414 101b - 33,554,432 ns
415 110b - Reserved
416 111b - Reserved
417 BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
418 the scale in bits 12:10
419
420 This field takes effect only if bit 3 is set in OverrideConfig.
421 **/
422 UINT16 NonSnoopLatency;
423
424 /**
425 Forces LTR override to be permanent
426 The default way LTR override works is:
427 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
428 This settings allows force override of LTR mechanism. If it's enabled, then:
429 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
430 **/
431 UINT8 ForceLtrOverride;
432 UINT8 Reserved[3];
433 } PCIE_DEVICE_OVERRIDE;
434
435 #pragma pack (pop)
436 #endif // _PCIE_CONFIG_H_
PCIE_DEVICE_OVERRIDE::BaseClassCode
UINT8 BaseClassCode
The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class.
Definition: PcieConfig.h:341
PCIE_LINK_EQ_MODE
PCIE_LINK_EQ_MODE
Definition: PcieConfig.h:119
PCIE_LINK_EQ_PLATFORM_SETTINGS::RemotePresetCoeffoverride
UINT8 RemotePresetCoeffoverride
Remote Transmitter Preset Coefficient Override for single PCIe speed.
Definition: PcieConfig.h:158
PcieLinkFixedEq
@ PcieLinkFixedEq
No coefficient/preset search is performed. Fixed values are used.
Definition: PcieConfig.h:116
PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh3Bypass
UINT8 EqPh3Bypass
PCIe Equalization Phase 3 Enable Control.
Definition: PcieConfig.h:164
PCIE_COMMON_CONFIG::ComplianceTestMode
UINT32 ComplianceTestMode
Compliance Test Mode shall be enabled when using Compliance Load Board.
Definition: PcieConfig.h:308
PCIE_DEVICE_OVERRIDE::SnoopLatency
UINT16 SnoopLatency
SnoopLatency bit definition Note: All Reserved bits must be set to 0.
Definition: PcieConfig.h:400
PCIE_DEVICE_OVERRIDE::DeviceId
UINT16 DeviceId
The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID.
Definition: PcieConfig.h:339
PCIE_DEVICE_OVERRIDE::L1sTpowerOnValue
UINT8 L1sTpowerOnValue
L1 Substate Port Tpower_on Value Override.
Definition: PcieConfig.h:377
PCIE_DEVICE_OVERRIDE::L1SubstatesCapOffset
UINT16 L1SubstatesCapOffset
The L1Substates Capability Offset Override.
Definition: PcieConfig.h:350
PCIE_LINK_EQ_PLATFORM_SETTINGS::PcieLinkEqMode
UINT8 PcieLinkEqMode
Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details ...
Definition: PcieConfig.h:134
PCIE_DEVICE_OVERRIDE::L1SubstatesCapMask
UINT8 L1SubstatesCapMask
L1 Substate Capability Mask.
Definition: PcieConfig.h:356
PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters.
Definition: PcieConfig.h:76
PcieLinkEqPresetMode
@ PcieLinkEqPresetMode
Use presets during PCIe link equalization.
Definition: PcieConfig.h:120
PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh23Bypass
UINT8 EqPh23Bypass
PCIe Equalization Phase 2-3 Enable Control.
Definition: PcieConfig.h:170
PCIE_COMMON_CONFIG::RpFunctionSwap
UINT32 RpFunctionSwap
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is ...
Definition: PcieConfig.h:303
PCIE_DEVICE_OVERRIDE::ForceLtrOverride
UINT8 ForceLtrOverride
Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override...
Definition: PcieConfig.h:431
PCIE_COMMON_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PcieConfig.h:309
PCIE_EQ_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: PcieConfig.h:78
PCIE_LINK_EQ_PLATFORM_SETTINGS::PCETTimer
UINT32 PCETTimer
PCET Timer value for single PCIe speed.
Definition: PcieConfig.h:157
PCIE_DEVICE_OVERRIDE::SubClassCode
UINT8 SubClassCode
The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class.
Definition: PcieConfig.h:342
PCIE_LINK_EQ_PLATFORM_SETTINGS::PcieLinkEqMethod
UINT8 PcieLinkEqMethod
Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for...
Definition: PcieConfig.h:133
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph2LocalTransmitterOverridePreset
UINT32 Ph2LocalTransmitterOverridePreset
Specifies the preset that should be used during local transmitter override during phase 2 of EQ proce...
Definition: PcieConfig.h:156
PCIE_DEVICE_OVERRIDE::OverrideConfig
UINT16 OverrideConfig
The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
Definition: PcieConfig.h:345
PcieLinkHardwareEq
@ PcieLinkHardwareEq
Hardware is responsible for performing coefficient/preset search.
Definition: PcieConfig.h:115
PcieLinkEqCoefficientMode
@ PcieLinkEqCoefficientMode
Use coefficients during PCIe link equalization.
Definition: PcieConfig.h:121
PCIE_DEVICE_OVERRIDE::RevId
UINT8 RevId
The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings.
Definition: PcieConfig.h:340
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph1DownstreamPortTransmitterPreset
UINT32 Ph1DownstreamPortTransmitterPreset
Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equali...
Definition: PcieConfig.h:149
PCIE_DEVICE_OVERRIDE::VendorId
UINT16 VendorId
The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID.
Definition: PcieConfig.h:338
PCIE_DEVICE_OVERRIDE::NonSnoopLatency
UINT16 NonSnoopLatency
NonSnoopLatency bit definition Note: All Reserved bits must be set to 0.
Definition: PcieConfig.h:422
PCIE_LINK_EQ_PLATFORM_SETTINGS::TsLockTimer
UINT8 TsLockTimer
8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
Definition: PcieConfig.h:171
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:287
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph1UpstreamPortTransmitterPreset
UINT32 Ph1UpstreamPortTransmitterPreset
Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equaliza...
Definition: PcieConfig.h:150
PCIE_LINK_EQ_METHOD
PCIE_LINK_EQ_METHOD
Definition: PcieConfig.h:114
PCIE_DEVICE_OVERRIDE::L1sTpowerOnScale
UINT8 L1sTpowerOnScale
L1 Substate Port Tpower_on Scale Override.
Definition: PcieConfig.h:370
PCIE_LINK_EQ_PLATFORM_SETTINGS
PCIe Link EQ Platform Settings.
Definition: PcieConfig.h:132
PCIE_LINK_EQ_PLATFORM_SETTINGS::LocalTransmitterOverrideEnable
UINT8 LocalTransmitterOverrideEnable
Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
Definition: PcieConfig.h:140
PCIE_DEVICE_OVERRIDE::L1sCommonModeRestoreTime
UINT8 L1sCommonModeRestoreTime
L1 Substate Port Common Mode Restore Time Override.
Definition: PcieConfig.h:363
PCIE_COMMON_CONFIG::EnablePort8xhDecode
UINT8 EnablePort8xhDecode
(Test) This member describes whether PCIE root port Port 8xh Decode is enabled.
Definition: PcieConfig.h:313
PCIE_DEVICE_OVERRIDE
PCIe device table entry entry.
Definition: PcieConfig.h:337
PCIE_EQ_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: PcieConfig.h:77
PCIE_DEVICE_OVERRIDE::EndPointAspm
UINT8 EndPointAspm
Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) Bit 1 must be set in OverrideConfig for this field ...
Definition: PcieConfig.h:343
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph3NumberOfPresetsOrCoefficients
UINT8 Ph3NumberOfPresetsOrCoefficients
Tells BIOS how many presets/coefficients should be used during link EQ.
Definition: PcieConfig.h:145
PCIE_FORM_FACTOR
PCIE_FORM_FACTOR
Specifies the form factor that the slot implements.
Definition: PcieConfig.h:103
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PciePreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
Classes
PciePreMemConfig.h File Reference

PCIe Config Block PreMem. More...

Go to the source code of this file.

Classes

struct | PCIE_IMR_CONFIG
PCIe IMR Config. More...
struct | PCIE_PREMEM_CONFIG
PCIe Pre-Memory Configuration Revision 1: - Initial version. More...

Detailed Description

PCIe Config Block PreMem.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PciePreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PciePreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
PciePreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 PCIe Config Block PreMem
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_PREMEM_CONFIG_H_
36 #define _PCIE_PREMEM_CONFIG_H_
37
38 #define PCIE_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gPciePreMemConfigGuid;
41
42 typedef enum {
43 ImrRpLocationPch,
44 ImrRpLocationSa,
45 ImrRpLocationMax
46 } PCIE_IMR_ROOT_PORT_LOCATION;
47
48 #pragma pack (push,1)
49
50 /**
51 PCIe IMR Config
52 **/
53 typedef struct {
54 UINT8 ImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
55 UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
56 UINT16 ImrSize; ///< PCIe IMR size in megabytes
57 UINT8 ImrRpSelection; ///< Index of root port that is selected for PCIe IMR (0 based)
58 UINT8 Rsvd0[3];
59 } PCIE_IMR_CONFIG;
60
61 /**
62 PCIe Pre-Memory Configuration
63 <b>Revision 1</b>: - Initial version.
64 **/
65 typedef struct {
66 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
67 PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration
68 } PCIE_PREMEM_CONFIG;
69
70 #pragma pack (pop)
71 #endif // _PCIE_PREMEM_CONFIG_H_
PCIE_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: PciePreMemConfig.h:66
PCIE_IMR_CONFIG::ImrRpLocation
UINT8 ImrRpLocation
0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port locati...
Definition: PciePreMemConfig.h:55
PCIE_IMR_CONFIG
PCIe IMR Config.
Definition: PciePreMemConfig.h:53
PCIE_PREMEM_CONFIG
PCIe Pre-Memory Configuration Revision 1: - Initial version.
Definition: PciePreMemConfig.h:65
PCIE_IMR_CONFIG::ImrSize
UINT16 ImrSize
PCIe IMR size in megabytes.
Definition: PciePreMemConfig.h:56
PCIE_PREMEM_CONFIG::PcieImr
PCIE_IMR_CONFIG PcieImr
IMR Configuration.
Definition: PciePreMemConfig.h:67
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCIE_IMR_CONFIG::ImrRpSelection
UINT8 ImrRpSelection
Index of root port that is selected for PCIe IMR (0 based)
Definition: PciePreMemConfig.h:57
PCIE_IMR_CONFIG::ImrEnabled
UINT8 ImrEnabled
PCIe IMR. 0: Disable; 1: Enable.
Definition: PciePreMemConfig.h:54
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
Classes | Typedefs
PeiITbtConfig.h File Reference

Header file for TBT PEI Policy. More...

#include <ConfigBlock.h>
#include <TcssInfo.h>
#include <PeiITbtGenericStructure.h>
Include dependency graph for PeiITbtConfig.h:

Go to the source code of this file.

Classes

struct _PEI_ITBT_CONFIG
ITBT PEI configuration
Revision 1: More...

Typedefs

typedef struct _PEI_ITBT_CONFIG PEI_ITBT_CONFIG
ITBT PEI configuration
Revision 1: More...

Detailed Description

Header file for TBT PEI Policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiITbtConfig.h.

Typedef Documentation

◆ PEI_ITBT_CONFIG

typedef struct _PEI_ITBT_CONFIG PEI_ITBT_CONFIG

ITBT PEI configuration
Revision 1:

  • Initial version. Revision 2:
  • Add ITbtPcieTunnelingForUsb4, deprecated ITbtSecurityLevel.
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
PeiITbtConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for TBT PEI Policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_ITBT_CONFIG_H_
37 #define _PEI_ITBT_CONFIG_H_
38
39 #include <ConfigBlock.h>
40 #include <TcssInfo.h>
41 #include <PeiITbtGenericStructure.h>
42
43 #pragma pack(push, 1)
44 #define PEI_ITBT_CONFIG_REVISION 2
45
46 /**
47 ITBT PEI configuration\n
48 <b>Revision 1</b>:
49 - Initial version.
50 <b>Revision 2</b>:
51 - Add ITbtPcieTunnelingForUsb4, deprecated ITbtSecurityLevel.
52 **/
53 typedef struct _PEI_ITBT_CONFIG {
54 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
55 ITBT_GENERIC_CONFIG ITbtGenericConfig; ///< ITbt Common Configuration
56 ITBT_ROOTPORT_CONFIG ITbtRootPortConfig [MAX_ITBT_PCIE_PORT]; ///< iTbt Root Port Configuration
57 UINT16 ITbtDmaLtr [MAX_HOST_ITBT_DMA_NUMBER]; ///< iTbt Host controller DMA LTR value
58 } PEI_ITBT_CONFIG;
59 #pragma pack(pop)
60
61 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
_PEI_ITBT_CONFIG::ITbtGenericConfig
ITBT_GENERIC_CONFIG ITbtGenericConfig
ITbt Common Configuration.
Definition: PeiITbtConfig.h:55
_ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
Definition: PeiITbtGenericStructure.h:44
_PEI_ITBT_CONFIG
ITBT PEI configuration Revision 1:
Definition: PeiITbtConfig.h:53
_PEI_ITBT_CONFIG::ITbtDmaLtr
UINT16 ITbtDmaLtr[MAX_HOST_ITBT_DMA_NUMBER]
iTbt Host controller DMA LTR value
Definition: PeiITbtConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PeiITbtGenericStructure.h
ITBT Policy definition to be referred in both PEI and DXE phase.
_PEI_ITBT_CONFIG::ITbtRootPortConfig
ITBT_ROOTPORT_CONFIG ITbtRootPortConfig[MAX_ITBT_PCIE_PORT]
iTbt Root Port Configuration
Definition: PeiITbtConfig.h:56
PEI_ITBT_CONFIG
struct _PEI_ITBT_CONFIG PEI_ITBT_CONFIG
ITBT PEI configuration Revision 1:
_ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
Definition: PeiITbtGenericStructure.h:52
_PEI_ITBT_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: PeiITbtConfig.h:54
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtGenericStructure.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Typedefs
PeiITbtGenericStructure.h File Reference

ITBT Policy definition to be referred in both PEI and DXE phase. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure More...
struct | _ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB. More...

Typedefs

typedef struct _ITBT_ROOTPORT_CONFIG | ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
typedef struct _ITBT_GENERIC_CONFIG | ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB.

Detailed Description

ITBT Policy definition to be referred in both PEI and DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiITbtGenericStructure.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiITbtGenericStructure.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
PeiITbtGenericStructure.h
Go to the documentation of this file.
1 /** @file
2 ITBT Policy definition to be referred in both PEI and DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ITBT_POLICY_GENERIC_H_
37 #define _ITBT_POLICY_GENERIC_H_
38
39 #pragma pack(push, 1)
40
41 ///
42 /// iTBT RootPort Data Structure
43 ///
44 typedef struct _ITBT_ROOTPORT_CONFIG{
45 UINT8 ITbtPcieRootPortEn; ///< Disable/Enable iTBT PCIe Root Port
46 UINT8 Reserved[3]; ///< Reserved for DWORD alignment
47 } ITBT_ROOTPORT_CONFIG;
48
49 ///
50 /// ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB
51 ///
52 typedef struct _ITBT_GENERIC_CONFIG{
53 /**
54 Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following
55 mailbox communication.
56 After applying Force Power Thunderbolt BIOS shall poll for iTBT readiness for mailbox communication
57 If TBT cable is disconnected, iTBT microcontrollers are in lower power state.
58 To ensure successful mailbox execution, independently on presence of TBT cable, TBT BIOS shall bring iTBT
59 microcontrollers up by applying Force Power. iTBT microcontrollers will wake up either due to TBT cable presence or
60 Force Power event.
61 <b>(Test)</b>
62 <b> default is 500 ms </b>
63 **/
64 UINT16 ITbtForcePowerOnTimeoutInMs;
65 /**
66 Timeout value while sending connect topology mailbox command in order to bring all connected TBT devices are available
67 on PCIe before BIOS will enumerate them in BDS
68 <b>(Test)</b>
69 <b> default is 5000 ms </b>
70 **/
71 UINT16 ITbtConnectTopologyTimeoutInMs;
72 UINT8 ITbtSecurityLevel; ///< iTbt Security Level <b>Deprecated</b>
73 UINT8 ITbtPcieTunnelingForUsb4; ///< Disable/Enable PCIe tunneling for USB4. <b>default is enable</b>
74 UINT8 Usb4CmMode; ///< USB4 CM mode
75 UINT8 Reserved[1]; ///< Reserved for DWORD alignment
76 } ITBT_GENERIC_CONFIG;
77
78 #pragma pack(pop)
79
80 #endif
_ITBT_GENERIC_CONFIG::ITbtForcePowerOnTimeoutInMs
UINT16 ITbtForcePowerOnTimeoutInMs
Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for ex...
Definition: PeiITbtGenericStructure.h:64
_ITBT_ROOTPORT_CONFIG::ITbtPcieRootPortEn
UINT8 ITbtPcieRootPortEn
Disable/Enable iTBT PCIe Root Port.
Definition: PeiITbtGenericStructure.h:45
_ITBT_ROOTPORT_CONFIG::Reserved
UINT8 Reserved[3]
Reserved for DWORD alignment.
Definition: PeiITbtGenericStructure.h:46
_ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
Definition: PeiITbtGenericStructure.h:44
_ITBT_GENERIC_CONFIG::Usb4CmMode
UINT8 Usb4CmMode
USB4 CM mode.
Definition: PeiITbtGenericStructure.h:74
_ITBT_GENERIC_CONFIG::ITbtConnectTopologyTimeoutInMs
UINT16 ITbtConnectTopologyTimeoutInMs
Timeout value while sending connect topology mailbox command in order to bring all connected TBT devi...
Definition: PeiITbtGenericStructure.h:71
_ITBT_GENERIC_CONFIG::ITbtSecurityLevel
UINT8 ITbtSecurityLevel
iTbt Security Level Deprecated
Definition: PeiITbtGenericStructure.h:72
ITBT_GENERIC_CONFIG
struct _ITBT_GENERIC_CONFIG ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
_ITBT_GENERIC_CONFIG::ITbtPcieTunnelingForUsb4
UINT8 ITbtPcieTunnelingForUsb4
Disable/Enable PCIe tunneling for USB4. default is enable
Definition: PeiITbtGenericStructure.h:73
_ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
Definition: PeiITbtGenericStructure.h:52
ITBT_ROOTPORT_CONFIG
struct _ITBT_ROOTPORT_CONFIG ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
_ITBT_GENERIC_CONFIG::Reserved
UINT8 Reserved[1]
Reserved for DWORD alignment.
Definition: PeiITbtGenericStructure.h:75
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiPreMemSiDefaultPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Typedefs
PeiPreMemSiDefaultPolicy.h File Reference

This file defines the function to initialize default silicon policy PPI. More...

Go to the source code of this file.

Classes

struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy. More...

Typedefs

typedef EFI_STATUS(* PEI_PREMEM_POLICY_INIT) (VOID)
Initialize and install default silicon policy PPI.

Detailed Description

This file defines the function to initialize default silicon policy PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiPreMemSiDefaultPolicy.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiPreMemSiDefaultPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiPreMemSiDefaultPolicy.h
Go to the documentation of this file.
1 /** @file
2 This file defines the function to initialize default silicon policy PPI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
36 #define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
37
38 //
39 // Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
40 //
41 typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
42
43 /**
44 Initialize and install default silicon policy PPI
45 **/
46 typedef
47 EFI_STATUS
48 (EFIAPI *PEI_PREMEM_POLICY_INIT) (
49 VOID
50 );
51
52 ///
53 /// This PPI provides function to install default silicon policy
54 ///
55 struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
56 PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
57 };
58
59 extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
60
61 #endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy.
Definition: PeiPreMemSiDefaultPolicy.h:55
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI::PeiPreMemPolicyInit
PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit
PeiPreMemPolicyInit()
Definition: PeiPreMemSiDefaultPolicy.h:56
PEI_PREMEM_POLICY_INIT
EFI_STATUS(* PEI_PREMEM_POLICY_INIT)(VOID)
Initialize and install default silicon policy PPI.
Definition: PeiPreMemSiDefaultPolicy.h:48
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiSiDefaultPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Typedefs
PeiSiDefaultPolicy.h File Reference

This file defines the function to initialize default silicon policy PPI. More...

Go to the source code of this file.

Classes

struct _PEI_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy. More...

Typedefs

typedef EFI_STATUS(* PEI_POLICY_INIT) (VOID)
Initialize and install default silicon policy PPI.

Detailed Description

This file defines the function to initialize default silicon policy PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiSiDefaultPolicy.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PeiSiDefaultPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiSiDefaultPolicy.h
Go to the documentation of this file.
1 /** @file
2 This file defines the function to initialize default silicon policy PPI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
36 #define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
37
38 //
39 // Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
40 //
41 typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
42
43 /**
44 Initialize and install default silicon policy PPI
45 **/
46 typedef
47 EFI_STATUS
48 (EFIAPI *PEI_POLICY_INIT) (
49 VOID
50 );
51
52 ///
53 /// This PPI provides function to install default silicon policy
54 ///
55 struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
56 PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
57 };
58
59 extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
60
61 #endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
_PEI_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy.
Definition: PeiSiDefaultPolicy.h:55
_PEI_SI_DEFAULT_POLICY_INIT_PPI::PeiPolicyInit
PEI_POLICY_INIT PeiPolicyInit
PeiPolicyInit()
Definition: PeiSiDefaultPolicy.h:56
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
PEI_POLICY_INIT
EFI_STATUS(* PEI_POLICY_INIT)(VOID)
Initialize and install default silicon policy PPI.
Definition: PeiSiDefaultPolicy.h:48
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PiHob.h File Reference

  • Edk2
  • MdePkg
  • Include
  • Pi
Classes | Macros | Typedefs
PiHob.h File Reference

HOB related definitions in PI. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | EFI_HOB_GENERIC_HEADER
Describes the format and size of the data inside the HOB. More...
struct | EFI_HOB_HANDOFF_INFO_TABLE
Contains general state information used by the HOB producer phase. More...
struct | EFI_HOB_MEMORY_ALLOCATION_HEADER
EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation. More...
struct | EFI_HOB_MEMORY_ALLOCATION
Describes all memory ranges used during the HOB producer phase that exist outside the HOB list. More...
struct | EFI_HOB_MEMORY_ALLOCATION_STACK
Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-installed executable content in the HOB producer phase is executing. More...
struct | EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store"). More...
struct | EFI_HOB_MEMORY_ALLOCATION_MODULE
Defines the location and entry point of the HOB consumer phase. More...
struct | EFI_HOB_RESOURCE_DESCRIPTOR
Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor host bus during the HOB producer phase. More...
struct | EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with specific GUID. More...
struct | EFI_HOB_FIRMWARE_VOLUME
Details the location of firmware volumes that contain firmware files. More...
struct | EFI_HOB_FIRMWARE_VOLUME2
Details the location of a firmware volume that was extracted from a file within another firmware volume. More...
struct | EFI_HOB_FIRMWARE_VOLUME3
Details the location of a firmware volume that was extracted from a file within another firmware volume. More...
struct | EFI_HOB_CPU
Describes processor information, such as address space and I/O space capabilities. More...
struct | EFI_HOB_MEMORY_POOL
Describes pool memory allocations. More...
struct | EFI_HOB_UEFI_CAPSULE
Each UEFI capsule HOB details the location of a UEFI capsule. More...
union | EFI_PEI_HOB_POINTERS
Union of all the possible HOB Types. More...

Macros

#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
Value of version in EFI_HOB_HANDOFF_INFO_TABLE.

Typedefs

typedef UINT32 | EFI_RESOURCE_TYPE
The resource type.
typedef UINT32 | EFI_RESOURCE_ATTRIBUTE_TYPE
A type of recount attribute type.

Detailed Description

HOB related definitions in PI.

Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Revision Reference:
PI Version 1.6

Definition in file PiHob.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PiHob.h Source File

  • Edk2
  • MdePkg
  • Include
  • Pi
PiHob.h
Go to the documentation of this file.
1 /** @file
2 HOB related definitions in PI.
3
4 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 @par Revision Reference:
8 PI Version 1.6
9
10 **/
11
12 #ifndef __PI_HOB_H__
13 #define __PI_HOB_H__
14
15 //
16 // HobType of EFI_HOB_GENERIC_HEADER.
17 //
18 #define EFI_HOB_TYPE_HANDOFF 0x0001
19 #define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
20 #define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
21 #define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
22 #define EFI_HOB_TYPE_FV 0x0005
23 #define EFI_HOB_TYPE_CPU 0x0006
24 #define EFI_HOB_TYPE_MEMORY_POOL 0x0007
25 #define EFI_HOB_TYPE_FV2 0x0009
26 #define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
27 #define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B
28 #define EFI_HOB_TYPE_FV3 0x000C
29 #define EFI_HOB_TYPE_UNUSED 0xFFFE
30 #define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
31
32 ///
33 /// Describes the format and size of the data inside the HOB.
34 /// All HOBs must contain this generic HOB header.
35 ///
36 typedef struct {
37 ///
38 /// Identifies the HOB data structure type.
39 ///
40 UINT16 HobType;
41 ///
42 /// The length in bytes of the HOB.
43 ///
44 UINT16 HobLength;
45 ///
46 /// This field must always be set to zero.
47 ///
48 UINT32 Reserved;
49 } EFI_HOB_GENERIC_HEADER;
50
51
52 ///
53 /// Value of version in EFI_HOB_HANDOFF_INFO_TABLE.
54 ///
55 #define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009
56
57 ///
58 /// Contains general state information used by the HOB producer phase.
59 /// This HOB must be the first one in the HOB list.
60 ///
61 typedef struct {
62 ///
63 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_HANDOFF.
64 ///
65 EFI_HOB_GENERIC_HEADER Header;
66 ///
67 /// The version number pertaining to the PHIT HOB definition.
68 /// This value is four bytes in length to provide an 8-byte aligned entry
69 /// when it is combined with the 4-byte BootMode.
70 ///
71 UINT32 Version;
72 ///
73 /// The system boot mode as determined during the HOB producer phase.
74 ///
75 EFI_BOOT_MODE BootMode;
76 ///
77 /// The highest address location of memory that is allocated for use by the HOB producer
78 /// phase. This address must be 4-KB aligned to meet page restrictions of UEFI.
79 ///
80 EFI_PHYSICAL_ADDRESS EfiMemoryTop;
81 ///
82 /// The lowest address location of memory that is allocated for use by the HOB producer phase.
83 ///
84 EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
85 ///
86 /// The highest address location of free memory that is currently available
87 /// for use by the HOB producer phase.
88 ///
89 EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
90 ///
91 /// The lowest address location of free memory that is available for use by the HOB producer phase.
92 ///
93 EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
94 ///
95 /// The end of the HOB list.
96 ///
97 EFI_PHYSICAL_ADDRESS EfiEndOfHobList;
98 } EFI_HOB_HANDOFF_INFO_TABLE;
99
100 ///
101 /// EFI_HOB_MEMORY_ALLOCATION_HEADER describes the
102 /// various attributes of the logical memory allocation. The type field will be used for
103 /// subsequent inclusion in the UEFI memory map.
104 ///
105 typedef struct {
106 ///
107 /// A GUID that defines the memory allocation region's type and purpose, as well as
108 /// other fields within the memory allocation HOB. This GUID is used to define the
109 /// additional data within the HOB that may be present for the memory allocation HOB.
110 /// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0
111 /// specification.
112 ///
113 EFI_GUID Name;
114
115 ///
116 /// The base address of memory allocated by this HOB. Type
117 /// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0
118 /// specification.
119 ///
120 EFI_PHYSICAL_ADDRESS MemoryBaseAddress;
121
122 ///
123 /// The length in bytes of memory allocated by this HOB.
124 ///
125 UINT64 MemoryLength;
126
127 ///
128 /// Defines the type of memory allocated by this HOB. The memory type definition
129 /// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined
130 /// in AllocatePages() in the UEFI 2.0 specification.
131 ///
132 EFI_MEMORY_TYPE MemoryType;
133
134 ///
135 /// Padding for Itanium processor family
136 ///
137 UINT8 Reserved[4];
138 } EFI_HOB_MEMORY_ALLOCATION_HEADER;
139
140 ///
141 /// Describes all memory ranges used during the HOB producer
142 /// phase that exist outside the HOB list. This HOB type
143 /// describes how memory is used, not the physical attributes of memory.
144 ///
145 typedef struct {
146 ///
147 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
148 ///
149 EFI_HOB_GENERIC_HEADER Header;
150 ///
151 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
152 /// various attributes of the logical memory allocation.
153 ///
154 EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
155 //
156 // Additional data pertaining to the "Name" Guid memory
157 // may go here.
158 //
159 } EFI_HOB_MEMORY_ALLOCATION;
160
161
162 ///
163 /// Describes the memory stack that is produced by the HOB producer
164 /// phase and upon which all post-memory-installed executable
165 /// content in the HOB producer phase is executing.
166 ///
167 typedef struct {
168 ///
169 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
170 ///
171 EFI_HOB_GENERIC_HEADER Header;
172 ///
173 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
174 /// various attributes of the logical memory allocation.
175 ///
176 EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
177 } EFI_HOB_MEMORY_ALLOCATION_STACK;
178
179 ///
180 /// Defines the location of the boot-strap
181 /// processor (BSP) BSPStore ("Backing Store Pointer Store").
182 /// This HOB is valid for the Itanium processor family only
183 /// register overflow store.
184 ///
185 typedef struct {
186 ///
187 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
188 ///
189 EFI_HOB_GENERIC_HEADER Header;
190 ///
191 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
192 /// various attributes of the logical memory allocation.
193 ///
194 EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;
195 } EFI_HOB_MEMORY_ALLOCATION_BSP_STORE;
196
197 ///
198 /// Defines the location and entry point of the HOB consumer phase.
199 ///
200 typedef struct {
201 ///
202 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.
203 ///
204 EFI_HOB_GENERIC_HEADER Header;
205 ///
206 /// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the
207 /// various attributes of the logical memory allocation.
208 ///
209 EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;
210 ///
211 /// The GUID specifying the values of the firmware file system name
212 /// that contains the HOB consumer phase component.
213 ///
214 EFI_GUID ModuleName;
215 ///
216 /// The address of the memory-mapped firmware volume
217 /// that contains the HOB consumer phase firmware file.
218 ///
219 EFI_PHYSICAL_ADDRESS EntryPoint;
220 } EFI_HOB_MEMORY_ALLOCATION_MODULE;
221
222 ///
223 /// The resource type.
224 ///
225 typedef UINT32 EFI_RESOURCE_TYPE;
226
227 //
228 // Value of ResourceType in EFI_HOB_RESOURCE_DESCRIPTOR.
229 //
230 #define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
231 #define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
232 #define EFI_RESOURCE_IO 0x00000002
233 #define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
234 #define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
235 #define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
236 #define EFI_RESOURCE_IO_RESERVED 0x00000006
237 #define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
238
239 ///
240 /// A type of recount attribute type.
241 ///
242 typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE;
243
244 //
245 // These types can be ORed together as needed.
246 //
247 // The following attributes are used to describe settings
248 //
249 #define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
250 #define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
251 #define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
252 #define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
253 //
254 // This is typically used as memory cacheability attribute today.
255 // NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED
256 // as Physical write protected attribute, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED
257 // means Memory cacheability attribute: The memory supports being programmed with
258 // a writeprotected cacheable attribute.
259 //
260 #define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100
261 #define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200
262 #define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000
263 //
264 // The rest of the attributes are used to describe capabilities
265 //
266 #define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008
267 #define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010
268 #define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020
269 #define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040
270 #define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
271 #define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
272 #define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
273 #define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
274 #define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000
275 #define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000
276 #define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000
277 #define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000
278 #define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000
279 //
280 // This is typically used as memory cacheability attribute today.
281 // NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE
282 // as Memory capability attribute: The memory supports being protected from processor
283 // writes, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTEC TABLE means Memory cacheability attribute:
284 // The memory supports being programmed with a writeprotected cacheable attribute.
285 //
286 #define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000
287 #define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000
288 #define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000
289
290 #define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000
291 #define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000
292
293 //
294 // Physical memory relative reliability attribute. This
295 // memory provides higher reliability relative to other
296 // memory in the system. If all memory has the same
297 // reliability, then this bit is not used.
298 //
299 #define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000
300
301 ///
302 /// Describes the resource properties of all fixed,
303 /// nonrelocatable resource ranges found on the processor
304 /// host bus during the HOB producer phase.
305 ///
306 typedef struct {
307 ///
308 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.
309 ///
310 EFI_HOB_GENERIC_HEADER Header;
311 ///
312 /// A GUID representing the owner of the resource. This GUID is used by HOB
313 /// consumer phase components to correlate device ownership of a resource.
314 ///
315 EFI_GUID Owner;
316 ///
317 /// The resource type enumeration as defined by EFI_RESOURCE_TYPE.
318 ///
319 EFI_RESOURCE_TYPE ResourceType;
320 ///
321 /// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
322 ///
323 EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
324 ///
325 /// The physical start address of the resource region.
326 ///
327 EFI_PHYSICAL_ADDRESS PhysicalStart;
328 ///
329 /// The number of bytes of the resource region.
330 ///
331 UINT64 ResourceLength;
332 } EFI_HOB_RESOURCE_DESCRIPTOR;
333
334 ///
335 /// Allows writers of executable content in the HOB producer phase to
336 /// maintain and manage HOBs with specific GUID.
337 ///
338 typedef struct {
339 ///
340 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.
341 ///
342 EFI_HOB_GENERIC_HEADER Header;
343 ///
344 /// A GUID that defines the contents of this HOB.
345 ///
346 EFI_GUID Name;
347 //
348 // Guid specific data goes here
349 //
350 } EFI_HOB_GUID_TYPE;
351
352 ///
353 /// Details the location of firmware volumes that contain firmware files.
354 ///
355 typedef struct {
356 ///
357 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV.
358 ///
359 EFI_HOB_GENERIC_HEADER Header;
360 ///
361 /// The physical memory-mapped base address of the firmware volume.
362 ///
363 EFI_PHYSICAL_ADDRESS BaseAddress;
364 ///
365 /// The length in bytes of the firmware volume.
366 ///
367 UINT64 Length;
368 } EFI_HOB_FIRMWARE_VOLUME;
369
370 ///
371 /// Details the location of a firmware volume that was extracted
372 /// from a file within another firmware volume.
373 ///
374 typedef struct {
375 ///
376 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV2.
377 ///
378 EFI_HOB_GENERIC_HEADER Header;
379 ///
380 /// The physical memory-mapped base address of the firmware volume.
381 ///
382 EFI_PHYSICAL_ADDRESS BaseAddress;
383 ///
384 /// The length in bytes of the firmware volume.
385 ///
386 UINT64 Length;
387 ///
388 /// The name of the firmware volume.
389 ///
390 EFI_GUID FvName;
391 ///
392 /// The name of the firmware file that contained this firmware volume.
393 ///
394 EFI_GUID FileName;
395 } EFI_HOB_FIRMWARE_VOLUME2;
396
397 ///
398 /// Details the location of a firmware volume that was extracted
399 /// from a file within another firmware volume.
400 ///
401 typedef struct {
402 ///
403 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV3.
404 ///
405 EFI_HOB_GENERIC_HEADER Header;
406 ///
407 /// The physical memory-mapped base address of the firmware volume.
408 ///
409 EFI_PHYSICAL_ADDRESS BaseAddress;
410 ///
411 /// The length in bytes of the firmware volume.
412 ///
413 UINT64 Length;
414 ///
415 /// The authentication status.
416 ///
417 UINT32 AuthenticationStatus;
418 ///
419 /// TRUE if the FV was extracted as a file within another firmware volume.
420 /// FALSE otherwise.
421 ///
422 BOOLEAN ExtractedFv;
423 ///
424 /// The name of the firmware volume.
425 /// Valid only if IsExtractedFv is TRUE.
426 ///
427 EFI_GUID FvName;
428 ///
429 /// The name of the firmware file that contained this firmware volume.
430 /// Valid only if IsExtractedFv is TRUE.
431 ///
432 EFI_GUID FileName;
433 } EFI_HOB_FIRMWARE_VOLUME3;
434
435 ///
436 /// Describes processor information, such as address space and I/O space capabilities.
437 ///
438 typedef struct {
439 ///
440 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_CPU.
441 ///
442 EFI_HOB_GENERIC_HEADER Header;
443 ///
444 /// Identifies the maximum physical memory addressability of the processor.
445 ///
446 UINT8 SizeOfMemorySpace;
447 ///
448 /// Identifies the maximum physical I/O addressability of the processor.
449 ///
450 UINT8 SizeOfIoSpace;
451 ///
452 /// This field will always be set to zero.
453 ///
454 UINT8 Reserved[6];
455 } EFI_HOB_CPU;
456
457
458 ///
459 /// Describes pool memory allocations.
460 ///
461 typedef struct {
462 ///
463 /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_POOL.
464 ///
465 EFI_HOB_GENERIC_HEADER Header;
466 } EFI_HOB_MEMORY_POOL;
467
468 ///
469 /// Each UEFI capsule HOB details the location of a UEFI capsule. It includes a base address and length
470 /// which is based upon memory blocks with a EFI_CAPSULE_HEADER and the associated
471 /// CapsuleImageSize-based payloads. These HOB's shall be created by the PEI PI firmware
472 /// sometime after the UEFI UpdateCapsule service invocation with the
473 /// CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE flag set in the EFI_CAPSULE_HEADER.
474 ///
475 typedef struct {
476 ///
477 /// The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
478 ///
479 EFI_HOB_GENERIC_HEADER Header;
480
481 ///
482 /// The physical memory-mapped base address of an UEFI capsule. This value is set to
483 /// point to the base of the contiguous memory of the UEFI capsule.
484 /// The length of the contiguous memory in bytes.
485 ///
486 EFI_PHYSICAL_ADDRESS BaseAddress;
487 UINT64 Length;
488 } EFI_HOB_UEFI_CAPSULE;
489
490 ///
491 /// Union of all the possible HOB Types.
492 ///
493 typedef union {
494 EFI_HOB_GENERIC_HEADER *Header;
495 EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;
496 EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;
497 EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;
498 EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;
499 EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;
500 EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;
501 EFI_HOB_GUID_TYPE *Guid;
502 EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;
503 EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2;
504 EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3;
505 EFI_HOB_CPU *Cpu;
506 EFI_HOB_MEMORY_POOL *Pool;
507 EFI_HOB_UEFI_CAPSULE *Capsule;
508 UINT8 *Raw;
509 } EFI_PEI_HOB_POINTERS;
510
511
512 #endif
EFI_HOB_MEMORY_ALLOCATION::AllocDescriptor
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:154
EFI_HOB_FIRMWARE_VOLUME3::ExtractedFv
BOOLEAN ExtractedFv
TRUE if the FV was extracted as a file within another firmware volume.
Definition: PiHob.h:422
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:189
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE::AllocDescriptor
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:194
EFI_RESOURCE_TYPE
UINT32 EFI_RESOURCE_TYPE
The resource type.
Definition: PiHob.h:225
EFI_HOB_FIRMWARE_VOLUME3::FvName
EFI_GUID FvName
The name of the firmware volume.
Definition: PiHob.h:427
EFI_HOB_HANDOFF_INFO_TABLE::Version
UINT32 Version
The version number pertaining to the PHIT HOB definition.
Definition: PiHob.h:71
EFI_HOB_CPU::SizeOfIoSpace
UINT8 SizeOfIoSpace
Identifies the maximum physical I/O addressability of the processor.
Definition: PiHob.h:450
EFI_HOB_RESOURCE_DESCRIPTOR::ResourceType
EFI_RESOURCE_TYPE ResourceType
The resource type enumeration as defined by EFI_RESOURCE_TYPE.
Definition: PiHob.h:319
EFI_HOB_UEFI_CAPSULE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.
Definition: PiHob.h:479
EFI_HOB_RESOURCE_DESCRIPTOR::PhysicalStart
EFI_PHYSICAL_ADDRESS PhysicalStart
The physical start address of the resource region.
Definition: PiHob.h:327
EFI_HOB_CPU::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:442
EFI_HOB_MEMORY_ALLOCATION_MODULE
Defines the location and entry point of the HOB consumer phase.
Definition: PiHob.h:200
EFI_HOB_FIRMWARE_VOLUME2::Length
UINT64 Length
The length in bytes of the firmware volume.
Definition: PiHob.h:386
EFI_HOB_FIRMWARE_VOLUME::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:359
EFI_HOB_FIRMWARE_VOLUME3::FileName
EFI_GUID FileName
The name of the firmware file that contained this firmware volume.
Definition: PiHob.h:432
EFI_HOB_FIRMWARE_VOLUME2::FileName
EFI_GUID FileName
The name of the firmware file that contained this firmware volume.
Definition: PiHob.h:394
EFI_HOB_MEMORY_ALLOCATION_STACK
Describes the memory stack that is produced by the HOB producer phase and upon which all post-memory-...
Definition: PiHob.h:167
EFI_HOB_FIRMWARE_VOLUME3::AuthenticationStatus
UINT32 AuthenticationStatus
The authentication status.
Definition: PiHob.h:417
EFI_HOB_HANDOFF_INFO_TABLE
Contains general state information used by the HOB producer phase.
Definition: PiHob.h:61
EFI_HOB_UEFI_CAPSULE
Each UEFI capsule HOB details the location of a UEFI capsule.
Definition: PiHob.h:475
EFI_HOB_FIRMWARE_VOLUME2
Details the location of a firmware volume that was extracted from a file within another firmware volu...
Definition: PiHob.h:374
EFI_HOB_FIRMWARE_VOLUME2::FvName
EFI_GUID FvName
The name of the firmware volume.
Definition: PiHob.h:390
EFI_HOB_MEMORY_ALLOCATION_STACK::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:171
EFI_HOB_MEMORY_POOL::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:465
EFI_HOB_CPU
Describes processor information, such as address space and I/O space capabilities.
Definition: PiHob.h:438
EFI_HOB_RESOURCE_DESCRIPTOR
Describes the resource properties of all fixed, nonrelocatable resource ranges found on the processor...
Definition: PiHob.h:306
EFI_HOB_FIRMWARE_VOLUME2::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
Definition: PiHob.h:382
EFI_HOB_RESOURCE_DESCRIPTOR::Owner
EFI_GUID Owner
A GUID representing the owner of the resource.
Definition: PiHob.h:315
EFI_HOB_MEMORY_ALLOCATION_MODULE::EntryPoint
EFI_PHYSICAL_ADDRESS EntryPoint
The address of the memory-mapped firmware volume that contains the HOB consumer phase firmware file.
Definition: PiHob.h:219
EFI_HOB_FIRMWARE_VOLUME3::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:405
EFI_HOB_MEMORY_ALLOCATION_MODULE::ModuleName
EFI_GUID ModuleName
The GUID specifying the values of the firmware file system name that contains the HOB consumer phase ...
Definition: PiHob.h:214
EFI_HOB_RESOURCE_DESCRIPTOR::ResourceLength
UINT64 ResourceLength
The number of bytes of the resource region.
Definition: PiHob.h:331
EFI_PEI_HOB_POINTERS
Union of all the possible HOB Types.
Definition: PiHob.h:493
EFI_HOB_UEFI_CAPSULE::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of an UEFI capsule.
Definition: PiHob.h:486
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
EFI_HOB_FIRMWARE_VOLUME3
Details the location of a firmware volume that was extracted from a file within another firmware volu...
Definition: PiHob.h:401
EFI_HOB_MEMORY_POOL
Describes pool memory allocations.
Definition: PiHob.h:461
EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryType
EFI_MEMORY_TYPE MemoryType
Defines the type of memory allocated by this HOB.
Definition: PiHob.h:132
EFI_HOB_GENERIC_HEADER::HobType
UINT16 HobType
Identifies the HOB data structure type.
Definition: PiHob.h:40
EFI_HOB_HANDOFF_INFO_TABLE::EfiEndOfHobList
EFI_PHYSICAL_ADDRESS EfiEndOfHobList
The end of the HOB list.
Definition: PiHob.h:97
EFI_HOB_HANDOFF_INFO_TABLE::EfiMemoryBottom
EFI_PHYSICAL_ADDRESS EfiMemoryBottom
The lowest address location of memory that is allocated for use by the HOB producer phase.
Definition: PiHob.h:84
EFI_HOB_FIRMWARE_VOLUME::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
Definition: PiHob.h:363
EFI_HOB_FIRMWARE_VOLUME3::BaseAddress
EFI_PHYSICAL_ADDRESS BaseAddress
The physical memory-mapped base address of the firmware volume.
Definition: PiHob.h:409
EFI_HOB_CPU::SizeOfMemorySpace
UINT8 SizeOfMemorySpace
Identifies the maximum physical memory addressability of the processor.
Definition: PiHob.h:446
EFI_HOB_FIRMWARE_VOLUME::Length
UINT64 Length
The length in bytes of the firmware volume.
Definition: PiHob.h:367
EFI_HOB_GUID_TYPE
Allows writers of executable content in the HOB producer phase to maintain and manage HOBs with speci...
Definition: PiHob.h:338
EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryBaseAddress
EFI_PHYSICAL_ADDRESS MemoryBaseAddress
The base address of memory allocated by this HOB.
Definition: PiHob.h:120
EFI_HOB_FIRMWARE_VOLUME3::Length
UINT64 Length
The length in bytes of the firmware volume.
Definition: PiHob.h:413
EFI_HOB_HANDOFF_INFO_TABLE::EfiFreeMemoryTop
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop
The highest address location of free memory that is currently available for use by the HOB producer p...
Definition: PiHob.h:89
EFI_HOB_MEMORY_ALLOCATION_MODULE::MemoryAllocationHeader
EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:209
EFI_HOB_HANDOFF_INFO_TABLE::BootMode
EFI_BOOT_MODE BootMode
The system boot mode as determined during the HOB producer phase.
Definition: PiHob.h:75
EFI_HOB_MEMORY_ALLOCATION_HEADER::MemoryLength
UINT64 MemoryLength
The length in bytes of memory allocated by this HOB.
Definition: PiHob.h:125
EFI_HOB_RESOURCE_DESCRIPTOR::ResourceAttribute
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute
Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.
Definition: PiHob.h:323
EFI_HOB_GENERIC_HEADER
Describes the format and size of the data inside the HOB.
Definition: PiHob.h:36
EFI_HOB_FIRMWARE_VOLUME2::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:378
EFI_RESOURCE_ATTRIBUTE_TYPE
UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE
A type of recount attribute type.
Definition: PiHob.h:242
EFI_HOB_MEMORY_ALLOCATION_MODULE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:204
EFI_HOB_GUID_TYPE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:342
EFI_HOB_MEMORY_ALLOCATION_HEADER
EFI_HOB_MEMORY_ALLOCATION_HEADER describes the various attributes of the logical memory allocation.
Definition: PiHob.h:105
EFI_HOB_GENERIC_HEADER::HobLength
UINT16 HobLength
The length in bytes of the HOB.
Definition: PiHob.h:44
EFI_HOB_GENERIC_HEADER::Reserved
UINT32 Reserved
This field must always be set to zero.
Definition: PiHob.h:48
EFI_HOB_FIRMWARE_VOLUME
Details the location of firmware volumes that contain firmware files.
Definition: PiHob.h:355
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE
Defines the location of the boot-strap processor (BSP) BSPStore ("Backing Store Pointer Store").
Definition: PiHob.h:185
EFI_HOB_MEMORY_ALLOCATION_HEADER::Name
EFI_GUID Name
A GUID that defines the memory allocation region's type and purpose, as well as other fields within t...
Definition: PiHob.h:113
EFI_HOB_HANDOFF_INFO_TABLE::EfiFreeMemoryBottom
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom
The lowest address location of free memory that is available for use by the HOB producer phase.
Definition: PiHob.h:93
EFI_HOB_MEMORY_ALLOCATION_STACK::AllocDescriptor
EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor
An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the various attributes of the logi...
Definition: PiHob.h:176
EFI_HOB_HANDOFF_INFO_TABLE::EfiMemoryTop
EFI_PHYSICAL_ADDRESS EfiMemoryTop
The highest address location of memory that is allocated for use by the HOB producer phase.
Definition: PiHob.h:80
EFI_HOB_GUID_TYPE::Name
EFI_GUID Name
A GUID that defines the contents of this HOB.
Definition: PiHob.h:346
EFI_HOB_HANDOFF_INFO_TABLE::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:65
EFI_HOB_RESOURCE_DESCRIPTOR::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:310
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
EFI_HOB_MEMORY_ALLOCATION
Describes all memory ranges used during the HOB producer phase that exist outside the HOB list.
Definition: PiHob.h:145
EFI_HOB_MEMORY_ALLOCATION::Header
EFI_HOB_GENERIC_HEADER Header
The HOB generic header.
Definition: PiHob.h:149
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PiMultiPhase.h File Reference

  • Edk2
  • MdePkg
  • Include
  • Pi
Classes | Macros | Typedefs
PiMultiPhase.h File Reference

Include file matches things in PI for multiple module types. More...

#include <Pi/PiFirmwareVolume.h>
#include <Pi/PiFirmwareFile.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#include <Pi/PiDependency.h>
#include <Pi/PiStatusCode.h>
#include <Pi/PiS3BootScript.h>
Include dependency graph for PiMultiPhase.h:

Go to the source code of this file.

Classes

struct | EFI_MMRAM_DESCRIPTOR
Structure describing a MMRAM region and its accessibility attributes. More...
struct | _EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap. More...

Macros

#define | DXE_ERROR(StatusCode) (MAX_BIT | (MAX_BIT >> 2) | StatusCode)
Produces an error code in the range reserved for use by the Platform Initialization Architecture Specification. More...
#define | EFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1)
If this value is returned by an EFI image, then the image should be unloaded.
#define | EFI_NOT_AVAILABLE_YET DXE_ERROR (2)
If this value is returned by an API, it means the capability is not yet installed/available/ready to use.
#define | PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))
Success and warning codes reserved for use by PI. More...
#define | PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))
Error codes reserved for use by PI. More...
#define | EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)
Return status codes defined in SMM CIS.
#define | EFI_MMRAM_OPEN 0x00000001
MMRAM states and capabilities.
#define | EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
Bitmask of values for Authentication Status. More...

Typedefs

typedef struct _EFI_MM_RESERVED_MMRAM_REGION | EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap.
typedef VOID(* | EFI_AP_PROCEDURE) (IN OUT VOID *Buffer)
The function prototype for invoking a function on an Application Processor. More...
typedef EFI_STATUS(* | EFI_AP_PROCEDURE2) (IN VOID *ProcedureArgument)
The function prototype for invoking a function on an Application Processor. More...

Detailed Description

Include file matches things in PI for multiple module types.

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Revision Reference:
These elements are defined in UEFI Platform Initialization Specification 1.2.

Definition in file PiMultiPhase.h.

Macro Definition Documentation

◆ DXE_ERROR

#define DXE_ERROR ( StatusCode ) (MAX_BIT | (MAX_BIT >> 2) | StatusCode)

Produces an error code in the range reserved for use by the Platform Initialization Architecture Specification.

The supported 32-bit range is 0xA0000000-0xBFFFFFFF The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF

Parameters
StatusCode The status code value to convert into a warning code. StatusCode must be in the range 0x00000000..0x1FFFFFFF.
Returns
The value specified by StatusCode in the PI reserved range.

Definition at line 36 of file PiMultiPhase.h.

◆ EFI_AUTH_STATUS_PLATFORM_OVERRIDE

#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01

Bitmask of values for Authentication Status.

Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL and the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI

xx00 Image was not signed. xxx1 Platform security policy override. Assumes the same meaning as 0010 (the image was signed, the signature was tested, and the signature passed authentication test). 0010 Image was signed, the signature was tested, and the signature passed authentication test. 0110 Image was signed and the signature was not tested. 1010 Image was signed, the signature was tested, and the signature failed the authentication test.

Definition at line 84 of file PiMultiPhase.h.

◆ PI_ENCODE_ERROR

#define PI_ENCODE_ERROR ( a ) (MAX_BIT | (MAX_BIT >> 2) | (a))

Error codes reserved for use by PI.

Supported 32-bit range is 0xa0000000-0xbfffffff. Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff.

Definition at line 61 of file PiMultiPhase.h.

◆ PI_ENCODE_WARNING

#define PI_ENCODE_WARNING ( a ) ((MAX_BIT >> 2) | (a))

Success and warning codes reserved for use by PI.

Supported 32-bit range is 0x20000000-0x3fffffff. Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff.

Definition at line 54 of file PiMultiPhase.h.

Typedef Documentation

◆ EFI_AP_PROCEDURE

typedef VOID( * EFI_AP_PROCEDURE) (IN OUT VOID *Buffer)

The function prototype for invoking a function on an Application Processor.

This definition is used by the UEFI MP Serices Protocol, and the PI SMM System Table.

Parameters
[in,out] Buffer The pointer to private data buffer.

Definition at line 190 of file PiMultiPhase.h.

◆ EFI_AP_PROCEDURE2

typedef EFI_STATUS( * EFI_AP_PROCEDURE2) (IN VOID *ProcedureArgument)

The function prototype for invoking a function on an Application Processor.

This definition is used by the UEFI MM MP Serices Protocol.

Parameters
[in] ProcedureArgument The pointer to private data buffer.
Return values
EFI_SUCCESS Excutive the procedure successfully

Definition at line 206 of file PiMultiPhase.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PiMultiPhase.h Source File

  • Edk2
  • MdePkg
  • Include
  • Pi
PiMultiPhase.h
Go to the documentation of this file.
1 /** @file
2 Include file matches things in PI for multiple module types.
3
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 @par Revision Reference:
8 These elements are defined in UEFI Platform Initialization Specification 1.2.
9
10 **/
11
12 #ifndef __PI_MULTIPHASE_H__
13 #define __PI_MULTIPHASE_H__
14
15 #include <Pi/PiFirmwareVolume.h>
16 #include <Pi/PiFirmwareFile.h>
17 #include <Pi/PiBootMode.h>
18 #include <Pi/PiHob.h>
19 #include <Pi/PiDependency.h>
20 #include <Pi/PiStatusCode.h>
21 #include <Pi/PiS3BootScript.h>
22
23 /**
24 Produces an error code in the range reserved for use by the Platform Initialization
25 Architecture Specification.
26
27 The supported 32-bit range is 0xA0000000-0xBFFFFFFF
28 The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF
29
30 @param StatusCode The status code value to convert into a warning code.
31 StatusCode must be in the range 0x00000000..0x1FFFFFFF.
32
33 @return The value specified by StatusCode in the PI reserved range.
34
35 **/
36 #define DXE_ERROR(StatusCode) (MAX_BIT | (MAX_BIT >> 2) | StatusCode)
37
38 ///
39 /// If this value is returned by an EFI image, then the image should be unloaded.
40 ///
41 #define EFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1)
42
43 ///
44 /// If this value is returned by an API, it means the capability is not yet
45 /// installed/available/ready to use.
46 ///
47 #define EFI_NOT_AVAILABLE_YET DXE_ERROR (2)
48
49 ///
50 /// Success and warning codes reserved for use by PI.
51 /// Supported 32-bit range is 0x20000000-0x3fffffff.
52 /// Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff.
53 ///
54 #define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))
55
56 ///
57 /// Error codes reserved for use by PI.
58 /// Supported 32-bit range is 0xa0000000-0xbfffffff.
59 /// Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff.
60 ///
61 #define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))
62
63 ///
64 /// Return status codes defined in SMM CIS.
65 ///
66 #define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)
67
68 #define EFI_WARN_INTERRUPT_SOURCE_PENDING PI_ENCODE_WARNING (0)
69 #define EFI_WARN_INTERRUPT_SOURCE_QUIESCED PI_ENCODE_WARNING (1)
70
71 ///
72 /// Bitmask of values for Authentication Status.
73 /// Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
74 /// and the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
75 ///
76 /// xx00 Image was not signed.
77 /// xxx1 Platform security policy override. Assumes the same meaning as 0010 (the image was signed, the
78 /// signature was tested, and the signature passed authentication test).
79 /// 0010 Image was signed, the signature was tested, and the signature passed authentication test.
80 /// 0110 Image was signed and the signature was not tested.
81 /// 1010 Image was signed, the signature was tested, and the signature failed the authentication test.
82 ///
83 ///@{
84 #define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01
85 #define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02
86 #define EFI_AUTH_STATUS_NOT_TESTED 0x04
87 #define EFI_AUTH_STATUS_TEST_FAILED 0x08
88 #define EFI_AUTH_STATUS_ALL 0x0f
89 ///@}
90
91 ///
92 /// MMRAM states and capabilities
93 ///
94 #define EFI_MMRAM_OPEN 0x00000001
95 #define EFI_MMRAM_CLOSED 0x00000002
96 #define EFI_MMRAM_LOCKED 0x00000004
97 #define EFI_CACHEABLE 0x00000008
98 #define EFI_ALLOCATED 0x00000010
99 #define EFI_NEEDS_TESTING 0x00000020
100 #define EFI_NEEDS_ECC_INITIALIZATION 0x00000040
101
102 #define EFI_SMRAM_OPEN EFI_MMRAM_OPEN
103 #define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED
104 #define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED
105
106 ///
107 /// Structure describing a MMRAM region and its accessibility attributes.
108 ///
109 typedef struct {
110 ///
111 /// Designates the physical address of the MMRAM in memory. This view of memory is
112 /// the same as seen by I/O-based agents, for example, but it may not be the address seen
113 /// by the processors.
114 ///
115 EFI_PHYSICAL_ADDRESS PhysicalStart;
116 ///
117 /// Designates the address of the MMRAM, as seen by software executing on the
118 /// processors. This address may or may not match PhysicalStart.
119 ///
120 EFI_PHYSICAL_ADDRESS CpuStart;
121 ///
122 /// Describes the number of bytes in the MMRAM region.
123 ///
124 UINT64 PhysicalSize;
125 ///
126 /// Describes the accessibility attributes of the MMRAM. These attributes include the
127 /// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical
128 /// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC
129 /// initialization).
130 ///
131 UINT64 RegionState;
132 } EFI_MMRAM_DESCRIPTOR;
133
134 typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR;
135
136 ///
137 /// Structure describing a MMRAM region which cannot be used for the MMRAM heap.
138 ///
139 typedef struct _EFI_MM_RESERVED_MMRAM_REGION {
140 ///
141 /// Starting address of the reserved MMRAM area, as it appears while MMRAM is open.
142 /// Ignored if MmramReservedSize is 0.
143 ///
144 EFI_PHYSICAL_ADDRESS MmramReservedStart;
145 ///
146 /// Number of bytes occupied by the reserved MMRAM area. A size of zero indicates the
147 /// last MMRAM area.
148 ///
149 UINT64 MmramReservedSize;
150 } EFI_MM_RESERVED_MMRAM_REGION;
151
152 typedef enum {
153 EFI_PCD_TYPE_8,
154 EFI_PCD_TYPE_16,
155 EFI_PCD_TYPE_32,
156 EFI_PCD_TYPE_64,
157 EFI_PCD_TYPE_BOOL,
158 EFI_PCD_TYPE_PTR
159 } EFI_PCD_TYPE;
160
161 typedef struct {
162 ///
163 /// The returned information associated with the requested TokenNumber. If
164 /// TokenNumber is 0, then PcdType is set to EFI_PCD_TYPE_8.
165 ///
166 EFI_PCD_TYPE PcdType;
167 ///
168 /// The size of the data in bytes associated with the TokenNumber specified. If
169 /// TokenNumber is 0, then PcdSize is set 0.
170 ///
171 UINTN PcdSize;
172 ///
173 /// The null-terminated ASCII string associated with a given token. If the
174 /// TokenNumber specified was 0, then this field corresponds to the null-terminated
175 /// ASCII string associated with the token's namespace Guid. If NULL, there is no
176 /// name associated with this request.
177 ///
178 CHAR8 *PcdName;
179 } EFI_PCD_INFO;
180
181 /**
182 The function prototype for invoking a function on an Application Processor.
183
184 This definition is used by the UEFI MP Serices Protocol, and the
185 PI SMM System Table.
186
187 @param[in,out] Buffer The pointer to private data buffer.
188 **/
189 typedef
190 VOID
191 (EFIAPI *EFI_AP_PROCEDURE)(
192 IN OUT VOID *Buffer
193 );
194
195 /**
196 The function prototype for invoking a function on an Application Processor.
197
198 This definition is used by the UEFI MM MP Serices Protocol.
199
200 @param[in] ProcedureArgument The pointer to private data buffer.
201
202 @retval EFI_SUCCESS Excutive the procedure successfully
203
204 **/
205 typedef
206 EFI_STATUS
207 (EFIAPI *EFI_AP_PROCEDURE2)(
208 IN VOID *ProcedureArgument
209 );
210
211 #endif
EFI_MMRAM_DESCRIPTOR::RegionState
UINT64 RegionState
Describes the accessibility attributes of the MMRAM.
Definition: PiMultiPhase.h:131
IN
#define IN
Datum is passed to the function.
Definition: Base.h:288
EFI_MMRAM_DESCRIPTOR::PhysicalSize
UINT64 PhysicalSize
Describes the number of bytes in the MMRAM region.
Definition: PiMultiPhase.h:124
_EFI_MM_RESERVED_MMRAM_REGION::MmramReservedStart
EFI_PHYSICAL_ADDRESS MmramReservedStart
Starting address of the reserved MMRAM area, as it appears while MMRAM is open.
Definition: PiMultiPhase.h:144
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
EFI_AP_PROCEDURE
VOID(* EFI_AP_PROCEDURE)(IN OUT VOID *Buffer)
The function prototype for invoking a function on an Application Processor.
Definition: PiMultiPhase.h:191
EFI_MM_RESERVED_MMRAM_REGION
struct _EFI_MM_RESERVED_MMRAM_REGION EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap.
EFI_MMRAM_DESCRIPTOR
Structure describing a MMRAM region and its accessibility attributes.
Definition: PiMultiPhase.h:109
EFI_MMRAM_DESCRIPTOR::PhysicalStart
EFI_PHYSICAL_ADDRESS PhysicalStart
Designates the physical address of the MMRAM in memory.
Definition: PiMultiPhase.h:115
EFI_MMRAM_DESCRIPTOR::CpuStart
EFI_PHYSICAL_ADDRESS CpuStart
Designates the address of the MMRAM, as seen by software executing on the processors.
Definition: PiMultiPhase.h:120
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
OUT
#define OUT
Datum is returned from the function.
Definition: Base.h:293
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
EFI_AP_PROCEDURE2
EFI_STATUS(* EFI_AP_PROCEDURE2)(IN VOID *ProcedureArgument)
The function prototype for invoking a function on an Application Processor.
Definition: PiMultiPhase.h:207
_EFI_MM_RESERVED_MMRAM_REGION
Structure describing a MMRAM region which cannot be used for the MMRAM heap.
Definition: PiMultiPhase.h:139
_EFI_MM_RESERVED_MMRAM_REGION::MmramReservedSize
UINT64 MmramReservedSize
Number of bytes occupied by the reserved MMRAM area.
Definition: PiMultiPhase.h:149
PiHob.h
HOB related definitions in PI.
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PmConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Classes | Enumerations
PmConfig.h File Reference

Power Management policy. More...

#include <ConfigBlock.h>
Include dependency graph for PmConfig.h:

Go to the source code of this file.

Classes

struct | PCH_WAKE_CONFIG
This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. More...
union | PMC_LPM_S0IX_SUB_STATE_EN
Low Power Mode Enable config. More...
union | PMC_GLOBAL_RESET_MASK
Description of Global Reset Trigger/Event Mask register. More...
struct | PCH_PM_CONFIG
The PCH_PM_CONFIG block describes expected miscellaneous power management settings. More...
struct | BCLK_CONFIG
BCLK configuration. More...

Enumerations

enum PCH_SLP_S4_MIN_ASSERT

Detailed Description

Power Management policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PmConfig.h.

Enumeration Type Documentation

◆ PCH_SLP_S4_MIN_ASSERT

enum PCH_SLP_S4_MIN_ASSERT
Enumerator
PchSlpS4PchTime

The time defined in PCH EDS Power Sequencing and Reset Signal Timings table.

Definition at line 83 of file PmConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PmConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
PmConfig.h
Go to the documentation of this file.
1 /** @file
2 Power Management policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PM_CONFIG_H_
36 #define _PM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define PCH_PM_CONFIG_REVISION 5
41 extern EFI_GUID gPmConfigGuid;
42
43 #define BCLK_CONFIG_REVISION 1
44 extern EFI_GUID gBclkConfigGuid;
45
46 #pragma pack (push,1)
47
48 /**
49 This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.
50 **/
51 typedef struct {
52 /**
53 Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
54 When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
55 When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
56 **/
57 UINT32 PmeB0S5Dis : 1;
58 UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>.
59 UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable.
60 UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
61 UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
62 UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>.
63 UINT32 RsvdBits0 : 26;
64 } PCH_WAKE_CONFIG;
65
66 typedef enum {
67 PchDeepSxPolDisable,
68 PchDpS5BatteryEn,
69 PchDpS5AlwaysEn,
70 PchDpS4S5BatteryEn,
71 PchDpS4S5AlwaysEn,
72 PchDpS3S4S5BatteryEn,
73 PchDpS3S4S5AlwaysEn
74 } PCH_DEEP_SX_CONFIG;
75
76 typedef enum {
77 PchSlpS360us = 1,
78 PchSlpS31ms,
79 PchSlpS350ms,
80 PchSlpS32s
81 } PCH_SLP_S3_MIN_ASSERT;
82
83 typedef enum {
84 PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table
85 PchSlpS41s,
86 PchSlpS42s,
87 PchSlpS43s,
88 PchSlpS44s
89 } PCH_SLP_S4_MIN_ASSERT;
90
91 typedef enum {
92 PchSlpSus0ms = 1,
93 PchSlpSus500ms,
94 PchSlpSus1s,
95 PchSlpSus4s,
96 } PCH_SLP_SUS_MIN_ASSERT;
97
98 typedef enum {
99 PchSlpA0ms = 1,
100 PchSlpA4s,
101 PchSlpA98ms,
102 PchSlpA2s,
103 } PCH_SLP_A_MIN_ASSERT;
104
105 typedef enum {
106 S0ixDisQNoChange,
107 S0ixDisQDciOob,
108 S0ixDisQUsb2Dbc,
109 S0ixDisQMax,
110 } S0IX_DISQ_PROBE_TYPE;
111
112 /**
113 Low Power Mode Enable config.
114 Used to configure if respective S0i2/3 sub-states are to be supported
115 by the platform. Each bit corresponds to one LPM state - LPMx->BITx.
116 Some sub-states will require external FETs controlled by EXT_PWR_GATE#/EXT_PWR_GATE2# pins
117 to gate v1p05-PHY or v1p05-IS supplies
118 **/
119 typedef union {
120 struct {
121 UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable
122 UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable
123 /**
124 LPM2 - S0i2.2 Enable.
125 Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
126 Refer to V1p05PhyExtFetControlEn.
127 **/
128 UINT32 S0i2p2En : 1;
129 UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable
130 UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable
131 UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable
132 /**
133 LPM5 - S0i3.3 Enable.
134 Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
135 Refer to V1p05PhyExtFetControlEn.
136 **/
137 UINT32 S0i3p3En : 1;
138 /**
139 LPM7 - S0i3.4 Enable.
140 Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK.
141 Refer to V1p05IsExtFetControlEn.
142 **/
143 UINT32 S0i3p4En : 1;
144 UINT32 Reserved : 24; ///< Reserved
145 } Field;
146 UINT32 Val;
147 } PMC_LPM_S0IX_SUB_STATE_EN;
148
149 /**
150 Description of Global Reset Trigger/Event Mask register
151 **/
152 typedef union {
153 struct {
154 UINT32 Reserved1 : 1;
155 UINT32 Pbo : 1;
156 UINT32 PmcUncErr : 1;
157 UINT32 PchThrm : 1;
158 UINT32 MePbo : 1;
159 UINT32 CpuThrm : 1;
160 UINT32 Megbl : 1;
161 UINT32 LtReset : 1;
162 UINT32 PmcWdt : 1;
163 UINT32 MeWdt : 1;
164 UINT32 PmcFw : 1;
165 UINT32 PchpwrFlr : 1;
166 UINT32 SyspwrFlr : 1;
167 UINT32 Reserved2 : 1;
168 UINT32 MiaUxsErr : 1;
169 UINT32 MiaUxErr : 1;
170 UINT32 CpuThrmWdt : 1;
171 UINT32 MeUncErr : 1;
172 UINT32 AdrGpio : 1;
173 UINT32 OcwdtNoicc : 1;
174 UINT32 OcwdtIcc : 1;
175 UINT32 CseHecUncErr : 1;
176 UINT32 PmcSramUncErr : 1;
177 UINT32 PmcIromParity : 1;
178 UINT32 PmcRfFusaErr : 1;
179 UINT32 Reserved3 : 4;
180 UINT32 PpbrParityErr : 1;
181 UINT32 Reserved4 : 2;
182 } Field;
183 UINT32 Value;
184 } PMC_GLOBAL_RESET_MASK;
185
186 typedef union {
187 struct {
188 UINT32 HostResetTimeout : 1;
189 UINT32 SxEntryTimeout : 1;
190 UINT32 HostRstProm : 1;
191 UINT32 HsmbMsg : 1;
192 UINT32 Pmc3Strike : 1;
193 UINT32 FwGblrstScratch5 : 1;
194 UINT32 PmcDmaTimeout : 1;
195 UINT32 EspiType7 : 1;
196 UINT32 EspiType8 : 1;
197 UINT32 FwGblRstScratch10 : 1;
198 UINT32 FwGblRstScratch11 : 1;
199 UINT32 LpmFwErr : 1;
200 UINT32 BscanMode : 1;
201 UINT32 SlpLvlRspErr : 1;
202 UINT32 FwGblrstScratch15 : 1;
203 UINT32 FwGblrstScratch16 : 1;
204 UINT32 FwGblrstScratch17 : 1;
205 UINT32 FwGblrstScratch18 : 1;
206 UINT32 FwGblrstScratch19 : 1;
207 UINT32 FwGblrstScratch20 : 1;
208 UINT32 FwGblrstScratch21 : 1;
209 UINT32 FwGblrstScratch22 : 1;
210 UINT32 FwGblrstScratch23 : 1;
211 UINT32 Rsvd : 9;
212 } Field;
213 UINT32 Value;
214 } PMC_GLOBAL_RESET_MASK1;
215
216 /**
217 The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
218 The PowerResetStatusClear field would clear the Power/Reset status bits, please
219 set the bits if you want PCH Init driver to clear it, if you want to check the
220 status later then clear the bits.
221
222 <b>Revision 1</b>:
223 - Initial version.
224 <b>Revision 2</b>
225 - Added C10DynamicThresholdAdjustment
226 <b>Revision 3</b>:
227 - Added SkipVccInConfig
228 **/
229 typedef struct {
230 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
231
232 PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
233 UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is <b>PchDeepSxPolDisable</b>.
234 UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is <b>PchSlpS350ms</b>.
235 UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is <b>PchSlpS44s</b>.
236 UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is <b>PchSlpSus4s</b>.
237 UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is <b>PchSlpA2s</b>.
238 UINT32 RsvdBits0 : 12;
239 /**
240 This member describes whether or not the LPC ClockRun feature of PCH should
241 be enabled. <b>0: Disable</b>; 1: Enable
242 **/
243 UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up
244 /**
245 Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
246 Configure On DC PHY Power Diable according to policy SlpLanLowDc.
247 When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
248 This indicates that LAN PHY should be powered off on battery mode.
249 This will override the DC_PP_DIS setting by WolEnableOverride.
250 **/
251 UINT32 SlpLanLowDc : 1;
252 /**
253 PCH power button override period.
254 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
255 <b>Default is 0: 4s</b>
256 **/
257 UINT32 PwrBtnOverridePeriod : 3;
258 /**
259 <b>(Test)</b>
260 Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable.
261 Enery Report is must have feature. Wihtout Energy Report, the performance report
262 by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted
263 in power/performance management algorithm.
264 If for some reason PCH energy report is too high, which forces CPU to try to reduce
265 its power by throttling, then it could try to disable Energy Report to do first debug.
266 This might be due to energy scaling factors are not correct or the LPM settings are not
267 kicking in.
268 **/
269 UINT32 DisableEnergyReport : 1;
270 /**
271 When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
272 When set to Enable, PCH will not pull down AC_PRESENT.
273 This setting is ignored when DeepSx is not supported.
274 Default is <b>0:Disable</b>
275 **/
276 UINT32 DisableDsxAcPresentPulldown : 1;
277 /**
278 Power button native mode disable.
279 While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal.
280 While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted.
281 <b>Default is FALSE.</b>
282 **/
283 UINT32 DisableNativePowerButton : 1;
284 UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
285 UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
286 /*
287 Set true to enable TCO timer.
288 When FALSE, it disables PCH ACPI timer, and stops TCO timer.
289 @note: This will have significant power impact when it's enabled.
290 If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
291 and WDAT table must not be exposed to the OS.
292 <b>0: Disable</b>, 1: Enable
293 */
294 UINT32 EnableTcoTimer : 1;
295 /*
296 When VRAlert# feature pin is enabled and its state is '0',
297 the PMC requests throttling to a T3 Tstate to the PCH throttling unit.
298 <b>0: Disable</b>; 1: Enable.
299 */
300 UINT32 VrAlert : 1;
301 /**
302 Decide if PS_ON is to be enabled. This is available on desktop only.
303 PS_ON is a new C10 state from the CPU on desktop SKUs that enables a
304 lower power target that will be required by the California Energy
305 Commission (CEC). When FALSE, PS_ON is to be disabled.}
306 <b>0: Disable</b>; 1: Enable.
307 **/
308 UINT32 PsOnEnable : 1;
309 /**
310 Enable/Disable platform support for CPU_C10_GATE# pin to control gating
311 of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy needs
312 to be set if board design includes support for CPU_C10_GATE# pin.
313 0: Disable; <b>1: Enable</b>
314 **/
315 UINT32 CpuC10GatePinEnable : 1;
316 /**
317 Control whether to enable PMC debug messages to Trace Hub.
318 When Enabled, PMC HW will send debug messages to trace hub;
319 When Disabled, PMC HW will never send debug meesages to trace hub.
320 @note: When enabled, system may not enter S0ix
321 <b>0: Disable</b>; 1: Enable.
322 **/
323 UINT32 PmcDbgMsgEn : 1;
324 /**
325 Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
326 EXT_PWR_GATE# signal (if supported on platform) can be used to
327 control external FET for power gating ModPHY
328 @note: This setting is not supported and ignored on PCH-H
329 0: Disable; <b>1: Enable</b>.
330 **/
331 UINT32 ModPhySusPgEnable : 1;
332 /**
333 <b>(Test)</b>
334 This policy option enables USB2 PHY SUS Well Power Gating functionality.
335 @note: This setting is not supported and ignored on PCH-H
336 0: disable USB2 PHY SUS Well Power Gating
337 <b>1: enable USB2 PHY SUS Well Power Gating</b>
338 **/
339 UINT32 Usb2PhySusPgEnable : 1;
340 /**
341 Enable Os Idle Mode.
342 0: Disable; <b>1: Enable</b>.
343 **/
344 UINT32 OsIdleEnable : 1;
345 /**
346 Enable control using EXT_PWR_GATE# pin of external FET
347 to power gate v1p05-PHY
348 <b>0: Disable</b>; 1: Enable.
349 **/
350 UINT32 V1p05PhyExtFetControlEn : 1;
351 /**
352 Enable control using EXT_PWR_GATE2# pin of external FET
353 to power gate v1p05-IS supply
354 <b>0: Disable</b>; 1: Enable.
355 **/
356 UINT32 V1p05IsExtFetControlEn : 1;
357 /**
358 Enable/Disable the Low Power Mode Host S0ix Auto-Demotion
359 feature. This feature enables the PMC to autonomously manage
360 the deepest allowed S0ix substate to combat thrashing between
361 power management states.
362 0: Disable; <b>1: Enable</b>.
363 **/
364 UINT32 S0ixAutoDemotion : 1;
365 /**
366 Enable/Disable Latch Events C10 Exit. When this bit is set to 1,
367 SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured
368 on C10 exit (instead of C10 entry which is default)
369 <b>0: Disable</b>; 1: Enable.
370 **/
371 UINT32 LatchEventsC10Exit : 1;
372 UINT32 RsvdBits1 : 10;
373 /*
374 Power button debounce configuration
375 Debounce time can be specified in microseconds. Only certain values according
376 to below formula are supported:
377 DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period).
378 RTC clock with f = 32 KHz is used for glitch filter.
379 DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
380 Supported DebounceTime values are following:
381 DebounceTime = 0 -> Debounce feature disabled
382 DebounceTime > 0 && < 250us -> Not supported
383 DebounceTime = 250us - 1024000us -> Supported range (DebounceTime = 250us * 2^n)
384 For values not supported by HW, they will be rounded down to closest supported one
385 <b>Default is 0</b>
386 */
387 UINT32 PowerButtonDebounce;
388 /**
389 Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS
390 for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where
391 <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
392 And make sure the setting correct, which never less than the following register.
393 - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
394 - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
395 - PWRM_CFG.SLP_A_MIN_ASST_WDTH
396 - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
397 **/
398 UINT8 PchPwrCycDur;
399 /**
400 Specifies the Pcie Pll Spread Spectrum Percentage
401 The value of this policy is in 1/10th percent units.
402 Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
403 A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
404 The default is <b>0xFF: AUTO - No BIOS override</b>.
405 **/
406 UINT8 PciePllSsc;
407 /**
408 Tells BIOS to enable C10 dynamic threshold adjustment mode.
409 BIOS will only attemt to enable it on PCH SKUs which support it.
410 **/
411 UINT8 C10DynamicThresholdAdjustment;
412 UINT8 Rsvd0[1]; ///< Reserved bytes
413 /**
414 <b>(Test)</b>
415 Low Power Mode Enable/Disable config.
416 Configure if respective S0i2/3 sub-states are to be supported
417 by the platform. By default all sub-states are enabled but
418 for test purpose respective states can be disabled.
419 <b>Default is 0xFF</b>
420 **/
421 PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable;
422 /*
423 Set true to enable Timed GPIO 0 timer.
424 <b>0: Disable</b>, 1: Enable
425 */
426 UINT32 EnableTimedGpio0 : 1;
427 /*
428 Set true to enable Timed GPIO 1 timer.
429 <b>0: Disable</b>, 1: Enable
430 */
431 UINT32 EnableTimedGpio1 : 1;
432 /*
433 Set true to enable Demoted (Dirty) Warm reset.
434 <b>0: Disable</b>, 1: Enable
435 */
436 UINT32 DirtyWarmResetEnable : 1;
437 UINT32 Rsvdbits2 : 29;
438
439 /**
440 Set true to enable override of Global Reset Event/Trigger masks.
441 Values from GlobalResetTriggerMask and GlobalResetEventMask will
442 be used as override value.
443 <b>0: Disable</b>, 1: Enable
444 **/
445 UINT8 GlobalResetMasksOverride;
446 UINT8 Rsvd1[3]; ///< Reserved bytes
447 /*
448 Mask for enabling Global Reset Trigger prevention
449 */
450 PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask;
451 /*
452 Mask for enabling Global Reset Event prevention
453 */
454 PMC_GLOBAL_RESET_MASK GlobalResetEventMask;
455 /**
456 PMC Therm Timer Delay Register (THERM_TIMER_DELAY). Unit in us(microseconds).
457 Adding delay time between CPU thermal trip propagating through PCH and PCH generating a Global Reset
458 <b>Default is 500</b>
459 **/
460 UINT32 ThermTimerDelay : 10;
461 UINT32 SkipVccInConfig : 1;
462 UINT32 Rsvdbits3 : 21;
463 } PCH_PM_CONFIG;
464
465 /**
466 BCLK configuration. Only available on projects with SOC and CPU BCLK supported.
467 **/
468 typedef struct {
469 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
470
471 /**
472 Controls enable status of SOC BCLK.
473 <b>0: HW default</b>, 1: Force enable, 2: Force disable
474 **/
475 UINT8 SocBclkPllOn;
476 /**
477 Controls enable status of CPU BCLK.
478 <b>0: HW default</b>, 1: Force enable, 2: Force disable
479 **/
480 UINT8 CpuBclkPllOn;
481 UINT8 Rsvd[2];
482 } BCLK_CONFIG;
483
484 #pragma pack (pop)
485
486 #endif // _PM_CONFIG_H_
PCH_PM_CONFIG::PchPwrCycDur
UINT8 PchPwrCycDur
Reset Power Cycle Duration could be customized in the unit of second.
Definition: PmConfig.h:398
PCH_PM_CONFIG::C10DynamicThresholdAdjustment
UINT8 C10DynamicThresholdAdjustment
Tells BIOS to enable C10 dynamic threshold adjustment mode.
Definition: PmConfig.h:411
PCH_WAKE_CONFIG::LanWakeFromDeepSx
UINT32 LanWakeFromDeepSx
Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable.
Definition: PmConfig.h:62
ConfigBlock.h
Header file for Config Block Lib implementation.
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p1En
UINT32 S0i3p1En
LPM4 - S0i3.1 Enable.
Definition: PmConfig.h:130
PCH_PM_CONFIG::PchDeepSxPol
UINT32 PchDeepSxPol
Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxPolDisable.
Definition: PmConfig.h:233
PCH_WAKE_CONFIG
This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL,...
Definition: PmConfig.h:51
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p4En
UINT32 S0i3p4En
LPM7 - S0i3.4 Enable.
Definition: PmConfig.h:143
PCH_WAKE_CONFIG::PcieWakeFromDeepSx
UINT32 PcieWakeFromDeepSx
Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable.
Definition: PmConfig.h:59
BCLK_CONFIG::CpuBclkPllOn
UINT8 CpuBclkPllOn
Controls enable status of CPU BCLK.
Definition: PmConfig.h:480
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p2En
UINT32 S0i2p2En
LPM2 - S0i2.2 Enable.
Definition: PmConfig.h:128
PCH_PM_CONFIG::OsIdleEnable
UINT32 OsIdleEnable
Enable Os Idle Mode.
Definition: PmConfig.h:344
PCH_PM_CONFIG::PsOnEnable
UINT32 PsOnEnable
Decide if PS_ON is to be enabled.
Definition: PmConfig.h:308
PCH_PM_CONFIG::PchSlpS4MinAssert
UINT32 PchSlpS4MinAssert
SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value....
Definition: PmConfig.h:235
PCH_PM_CONFIG::S0ixAutoDemotion
UINT32 S0ixAutoDemotion
Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature.
Definition: PmConfig.h:364
PCH_PM_CONFIG::DisableNativePowerButton
UINT32 DisableNativePowerButton
Power button native mode disable.
Definition: PmConfig.h:283
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p3En
UINT32 S0i3p3En
LPM5 - S0i3.3 Enable.
Definition: PmConfig.h:137
PCH_PM_CONFIG::SlpStrchSusUp
UINT32 SlpStrchSusUp
This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
Definition: PmConfig.h:243
PMC_GLOBAL_RESET_MASK
Description of Global Reset Trigger/Event Mask register.
Definition: PmConfig.h:152
PCH_PM_CONFIG::LpmS0ixSubStateEnable
PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable
(Test) Low Power Mode Enable/Disable config.
Definition: PmConfig.h:421
PCH_PM_CONFIG::Usb2PhySusPgEnable
UINT32 Usb2PhySusPgEnable
(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality.
Definition: PmConfig.h:339
PCH_PM_CONFIG::PciePllSsc
UINT8 PciePllSsc
Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units...
Definition: PmConfig.h:406
PCH_PM_CONFIG::PchSlpS3MinAssert
UINT32 PchSlpS3MinAssert
SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value....
Definition: PmConfig.h:234
PCH_PM_CONFIG::SlpLanLowDc
UINT32 SlpLanLowDc
Enable/Disable SLP_LAN# Low on DC Power.
Definition: PmConfig.h:251
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_PM_CONFIG::ThermTimerDelay
UINT32 ThermTimerDelay
PMC Therm Timer Delay Register (THERM_TIMER_DELAY).
Definition: PmConfig.h:460
PCH_PM_CONFIG::WakeConfig
PCH_WAKE_CONFIG WakeConfig
Specify Wake Policy.
Definition: PmConfig.h:232
PCH_PM_CONFIG::WolOvrWkSts
UINT32 WolOvrWkSts
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
Definition: PmConfig.h:285
PCH_SLP_S4_MIN_ASSERT
PCH_SLP_S4_MIN_ASSERT
Definition: PmConfig.h:83
BCLK_CONFIG
BCLK configuration.
Definition: PmConfig.h:468
PCH_PM_CONFIG::MeWakeSts
UINT32 MeWakeSts
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
Definition: PmConfig.h:284
PCH_PM_CONFIG::PchSlpAMinAssert
UINT32 PchSlpAMinAssert
SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value....
Definition: PmConfig.h:237
PCH_WAKE_CONFIG::WoWlanDeepSxEnable
UINT32 WoWlanDeepSxEnable
Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register...
Definition: PmConfig.h:61
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p1En
UINT32 S0i2p1En
LPM1 - S0i2.1 Enable.
Definition: PmConfig.h:122
PCH_PM_CONFIG
The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
Definition: PmConfig.h:229
PCH_PM_CONFIG::DisableDsxAcPresentPulldown
UINT32 DisableDsxAcPresentPulldown
When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
Definition: PmConfig.h:276
PCH_PM_CONFIG::GlobalResetMasksOverride
UINT8 GlobalResetMasksOverride
Set true to enable override of Global Reset Event/Trigger masks.
Definition: PmConfig.h:445
PMC_LPM_S0IX_SUB_STATE_EN
Low Power Mode Enable config.
Definition: PmConfig.h:119
PCH_PM_CONFIG::V1p05IsExtFetControlEn
UINT32 V1p05IsExtFetControlEn
Enable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply 0: Disable; 1: ...
Definition: PmConfig.h:356
PMC_LPM_S0IX_SUB_STATE_EN::Reserved
UINT32 Reserved
Reserved.
Definition: PmConfig.h:144
PCH_PM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PmConfig.h:230
PCH_PM_CONFIG::LatchEventsC10Exit
UINT32 LatchEventsC10Exit
Enable/Disable Latch Events C10 Exit.
Definition: PmConfig.h:371
PchSlpS4PchTime
@ PchSlpS4PchTime
The time defined in PCH EDS Power Sequencing and Reset Signal Timings table.
Definition: PmConfig.h:84
PCH_WAKE_CONFIG::WolEnableOverride
UINT32 WolEnableOverride
Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register...
Definition: PmConfig.h:58
PCH_PM_CONFIG::ModPhySusPgEnable
UINT32 ModPhySusPgEnable
Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
Definition: PmConfig.h:331
BCLK_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PmConfig.h:469
PCH_WAKE_CONFIG::WoWlanEnable
UINT32 WoWlanEnable
Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register....
Definition: PmConfig.h:60
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p0En
UINT32 S0i2p0En
LPM0 - S0i2.0 Enable.
Definition: PmConfig.h:121
PCH_WAKE_CONFIG::PmeB0S5Dis
UINT32 PmeB0S5Dis
Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
Definition: PmConfig.h:57
BCLK_CONFIG::SocBclkPllOn
UINT8 SocBclkPllOn
Controls enable status of SOC BCLK.
Definition: PmConfig.h:475
PCH_PM_CONFIG::DisableEnergyReport
UINT32 DisableEnergyReport
(Test) Disable/Enable PCH to CPU enery report feature.
Definition: PmConfig.h:269
PCH_PM_CONFIG::PmcDbgMsgEn
UINT32 PmcDbgMsgEn
Control whether to enable PMC debug messages to Trace Hub.
Definition: PmConfig.h:323
PCH_PM_CONFIG::PwrBtnOverridePeriod
UINT32 PwrBtnOverridePeriod
PCH power button override period.
Definition: PmConfig.h:257
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p2En
UINT32 S0i3p2En
LPM5 - S0i3.2 Enable.
Definition: PmConfig.h:131
PCH_PM_CONFIG::PchSlpSusMinAssert
UINT32 PchSlpSusMinAssert
SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value....
Definition: PmConfig.h:236
PCH_PM_CONFIG::CpuC10GatePinEnable
UINT32 CpuC10GatePinEnable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails...
Definition: PmConfig.h:315
PCH_PM_CONFIG::V1p05PhyExtFetControlEn
UINT32 V1p05PhyExtFetControlEn
Enable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY 0: Disable; 1: Enable.
Definition: PmConfig.h:350
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p0En
UINT32 S0i3p0En
LPM3 - S0i3.0 Enable.
Definition: PmConfig.h:129
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PsfConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Psf
Classes
PsfConfig.h File Reference

Primary Sideband Fabric policy. More...

#include <ConfigBlock.h>
Include dependency graph for PsfConfig.h:

Go to the source code of this file.

Classes

struct PSF_CONFIG
The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric. More...

Detailed Description

Primary Sideband Fabric policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PsfConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PsfConfig.h Source File

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  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Psf
PsfConfig.h
Go to the documentation of this file.
1 /** @file
2 Primary Sideband Fabric policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PSF_CONFIG_H_
37 #define _PSF_CONFIG_H_
38
39 #include <ConfigBlock.h>
40 #define PSF_CONFIG_REVISION 1
41 extern EFI_GUID gPsfConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 The PSF_CONFIG block describes the expected configuration of the Primary
47 Sideband Fabric.
48 **/
49 typedef struct {
50 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
51 /**
52 Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable
53 some psf power management features. <b>0: Disable</b>; 1: Enable.
54 **/
55 UINT32 TccEnable : 1;
56 UINT32 RsvdBits0 : 31; ///< Reserved bits
57 } PSF_CONFIG;
58
59 #pragma pack (pop)
60
61 #endif // _PSF_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
PSF_CONFIG
The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric.
Definition: PsfConfig.h:49
PSF_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PsfConfig.h:50
PSF_CONFIG::TccEnable
UINT32 TccEnable
Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable some psf...
Definition: PsfConfig.h:55
PSF_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PsfConfig.h:56
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: RstConfig.h File Reference

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  • Include
  • ConfigBlock
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Classes
RstConfig.h File Reference

Rst policy. More...

#include <PchLimits.h>
#include <ConfigBlock.h>
Include dependency graph for RstConfig.h:

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Classes

struct | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required. More...
struct | RST_CONFIG
Rapid Storage Technology settings. More...

Detailed Description

Rst policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RstConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: RstConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rst
RstConfig.h
Go to the documentation of this file.
1 /** @file
2 Rst policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RST_CONFIG_H_
36 #define _RST_CONFIG_H_
37 #include <PchLimits.h>
38 #include <ConfigBlock.h>
39
40 #define RST_CONFIG_REVISION 1
41 extern EFI_GUID gRstConfigGuid;
42
43 #pragma pack (push,1)
44
45 typedef enum {
46 SataOromDelay2sec,
47 SataOromDelay4sec,
48 SataOromDelay6sec,
49 SataOromDelay8sec
50 } SATA_OROM_DELAY;
51
52 /**
53 This structure describes the details of Intel RST for PCIe Storage remapping
54 Note: In order to use this feature, Intel RST Driver is required
55 **/
56 typedef struct {
57 /**
58 This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable.
59 Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well
60 Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID
61 **/
62 UINT32 Enable : 1;
63 /**
64 Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>)
65 The supported ports for PCIe Storage remapping is different depend on the platform and cycle router
66 **/
67 UINT32 RstPcieStoragePort : 5;
68 /**
69 PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled
70 before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.
71 Default value is <b>100ms</b>.
72 **/
73 UINT32 DeviceResetDelay : 8;
74 UINT32 RsvdBits0 : 18; ///< Reserved bits
75
76 } RST_HARDWARE_REMAPPED_STORAGE_CONFIG;
77
78 /**
79 Rapid Storage Technology settings.
80
81 <b>Revision 1</b>:
82 - Initial version.
83 **/
84 typedef struct {
85 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
86
87 UINT32 Raid0 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID0
88 UINT32 Raid1 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID1
89 UINT32 Raid10 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID10
90 UINT32 Raid5 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID5
91 UINT32 Irrt : 1; ///< 0 : Disable; <b>1 : Enable</b> Intel Rapid Recovery Technology
92 UINT32 OromUiBanner : 1; ///< 0 : Disable; <b>1 : Enable</b> OROM UI and BANNER
93 UINT32 OromUiDelay : 2; ///< <b>00b : 2 secs</b>; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
94 UINT32 HddUnlock : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the HDD password unlock in the OS is enabled
95 UINT32 LedLocate : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
96 UINT32 IrrtOnly : 1; ///< 0 : Disable; <b>1 : Enable</b>. Allow only IRRT drives to span internal and external ports
97 UINT32 SmartStorage : 1; ///< 0 : Disable; <b>1 : Enable</b> RST Smart Storage caching Bit
98 UINT32 LegacyOrom : 1; ///< <b>0 : Disable</b>; 1 : Enable RST Legacy OROM
99 UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b> RST Optane(TM) Memory
100 UINT32 CpuAttachedStorage : 1; ///< 0: Disable; <b>1: Enable</b> CPU Attached Storage
101 UINT32 RsvdBits0 : 17; ///< Reserved Bits
102 /**
103 This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
104 Note: RST for PCIe Sorage remapping is supported only for first SATA controller if more controllers are available
105 **/
106 RST_HARDWARE_REMAPPED_STORAGE_CONFIG HardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR];
107 } RST_CONFIG;
108
109 #pragma pack (pop)
110 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
RST_CONFIG::OromUiBanner
UINT32 OromUiBanner
0 : Disable; 1 : Enable OROM UI and BANNER
Definition: RstConfig.h:92
RST_CONFIG::LegacyOrom
UINT32 LegacyOrom
0 : Disable; 1 : Enable RST Legacy OROM
Definition: RstConfig.h:98
RST_CONFIG::HddUnlock
UINT32 HddUnlock
0 : Disable; 1 : Enable. Indicates that the HDD password unlock in the OS is enabled
Definition: RstConfig.h:94
RST_CONFIG::SmartStorage
UINT32 SmartStorage
0 : Disable; 1 : Enable RST Smart Storage caching Bit
Definition: RstConfig.h:97
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::DeviceResetDelay
UINT32 DeviceResetDelay
PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled...
Definition: RstConfig.h:73
RST_CONFIG::CpuAttachedStorage
UINT32 CpuAttachedStorage
0: Disable; 1: Enable CPU Attached Storage
Definition: RstConfig.h:100
RST_HARDWARE_REMAPPED_STORAGE_CONFIG
This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use th...
Definition: RstConfig.h:56
RST_CONFIG::Raid10
UINT32 Raid10
0 : Disable; 1 : Enable RAID10
Definition: RstConfig.h:89
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
RST_CONFIG
Rapid Storage Technology settings.
Definition: RstConfig.h:84
RST_CONFIG::Raid0
UINT32 Raid0
0 : Disable; 1 : Enable RAID0
Definition: RstConfig.h:87
RST_CONFIG::LedLocate
UINT32 LedLocate
0 : Disable; 1 : Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature...
Definition: RstConfig.h:95
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::RstPcieStoragePort
UINT32 RstPcieStoragePort
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) The supported po...
Definition: RstConfig.h:67
RST_CONFIG::IrrtOnly
UINT32 IrrtOnly
0 : Disable; 1 : Enable. Allow only IRRT drives to span internal and external ports
Definition: RstConfig.h:96
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::Enable
UINT32 Enable
This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled.
Definition: RstConfig.h:62
RST_CONFIG::OptaneMemory
UINT32 OptaneMemory
0: Disable; 1: Enable RST Optane(TM) Memory
Definition: RstConfig.h:99
RST_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: RstConfig.h:101
RST_CONFIG::Irrt
UINT32 Irrt
0 : Disable; 1 : Enable Intel Rapid Recovery Technology
Definition: RstConfig.h:91
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: RstConfig.h:74
RST_CONFIG::OromUiDelay
UINT32 OromUiDelay
00b : 2 secs; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
Definition: RstConfig.h:93
RST_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: RstConfig.h:85
RST_CONFIG::Raid1
UINT32 Raid1
0 : Disable; 1 : Enable RAID1
Definition: RstConfig.h:88
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
RST_CONFIG::Raid5
UINT32 Raid5
0 : Disable; 1 : Enable RAID5
Definition: RstConfig.h:90
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: RtcConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
Classes
RtcConfig.h File Reference

RTC policy. More...

Go to the source code of this file.

Classes

struct RTC_CONFIG
The RTC_CONFIG block describes the expected configuration of RTC configuration. More...

Detailed Description

RTC policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RtcConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: RtcConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
RtcConfig.h
Go to the documentation of this file.
1 /** @file
2 RTC policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RTC_CONFIG_H_
36 #define _RTC_CONFIG_H_
37
38 #define RTC_CONFIG_REVISION 1
39 extern EFI_GUID gRtcConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The RTC_CONFIG block describes the expected configuration of RTC configuration.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 When set, prevents RTC TS (BUC.TS) from being changed.
50 This BILD bit has different function compared to LPC/eSPI, SPI.
51 0: Disabled; <b>1: Enabled</b>
52 **/
53 UINT32 BiosInterfaceLock : 1;
54 /**
55 When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked
56 and cannot be accessed.
57 Writes will be droipped and reads will not return any guaranteed data.
58 0: Disabled; <b>1: Enabled</b>
59 **/
60 UINT32 MemoryLock : 1;
61 UINT32 RsvdBits0 : 30;
62 } RTC_CONFIG;
63
64 #pragma pack (pop)
65
66 #endif // _RTC_CONFIG_H_
RTC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: RtcConfig.h:47
RTC_CONFIG
The RTC_CONFIG block describes the expected configuration of RTC configuration.
Definition: RtcConfig.h:46
RTC_CONFIG::BiosInterfaceLock
UINT32 BiosInterfaceLock
When set, prevents RTC TS (BUC.TS) from being changed.
Definition: RtcConfig.h:53
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
RTC_CONFIG::MemoryLock
UINT32 MemoryLock
When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed.
Definition: RtcConfig.h:60
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SaMiscPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
Classes
SaMiscPeiConfig.h File Reference

Policy details for miscellaneous configuration in System Agent. More...

Go to the source code of this file.

Classes

struct SA_MISC_PEI_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem. More...

Detailed Description

Policy details for miscellaneous configuration in System Agent.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaMiscPeiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SaMiscPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
SaMiscPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy details for miscellaneous configuration in System Agent
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SA_MISC_PEI_CONFIG_H_
36 #define _SA_MISC_PEI_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 #define SA_MISC_PEI_CONFIG_REVISION 1
41
42 /**
43 This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem.\n
44 <b>Revision 1</b>:
45 - Initial version.
46 **/
47 typedef struct {
48 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
49 } SA_MISC_PEI_CONFIG;
50 #pragma pack(pop)
51
52 #endif // _SA_MISC_PEI_CONFIG_H_
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SA_MISC_PEI_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem.
Definition: SaMiscPeiConfig.h:47
SA_MISC_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: SaMiscPeiConfig.h:48
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SaMiscPeiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
Classes
SaMiscPeiPreMemConfig.h File Reference

Policy details for miscellaneous configuration in System Agent. More...

Go to the source code of this file.

Classes

struct SA_MISC_PEI_PREMEM_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc. More...

Detailed Description

Policy details for miscellaneous configuration in System Agent.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaMiscPeiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SaMiscPeiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
SaMiscPeiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy details for miscellaneous configuration in System Agent
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_
36 #define _SA_MISC_PEI_PREMEM_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 #ifndef MEM_CFG_MAX_SOCKETS
41 #define MEM_CFG_MAX_SOCKETS 16
42 #endif
43
44 #define SA_MISC_PEI_PREMEM_CONFIG_REVISION 5
45
46 /**
47 This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming
48 different System Agent BARs, TsegSize, MmioSize required etc.
49 <b>Revision 1</b>:
50 - Initial version.
51 <b>Revision 2</b>:
52 - Deprecate IedSize.
53 <b>Revision 3</b>:
54 - Adding ResizableBarSupport.
55 **/
56 typedef struct {
57 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
58 /**
59 Offset 28 Memory DIMMs' SPD address for reading SPD data.
60 TGL Mapping
61 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
62 1 - Controller 0 Channel 0 Dimm 1 - DDR4
63 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
64 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC
65 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
66 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
67 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
68 9 - Controller 1 Channel 0 Dimm 1 - DDR4
69 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
70 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC
71 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
72 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
73 **/
74 UINT8 SpdAddressTable[MEM_CFG_MAX_SOCKETS];
75 VOID *S3DataPtr; ///< Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path
76 UINT32 SmbusBar; ///< Offset 48 Address of System Agent SMBUS BAR: <b>0xEFA0</b>
77 /**
78 Offset 52 Size of TSEG in bytes. (Must be power of 2)
79 <b>0x400000</b>: 4MB for Release build (When IED enabled, it will be 8MB)
80 0x1000000 : 16MB for Debug build (Regardless IED enabled or disabled)
81 **/
82 UINT32 TsegSize;
83 /**
84 Offset 56
85 <b>(Test)</b> Size of IED region in bytes.
86 <b>0</b> : IED Disabled (no memory occupied)
87 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG)
88 <b>Note: Enabling IED may also enlarge TsegSize together.</b>
89 @deprecated
90 **/
91 UINT32 IedSize;
92 UINT32 SkipExtGfxScan:1; ///< <b>(Test)</b> OFfset 60:0 :1=Skip External Gfx Device Scan; <b>0=Scan for external graphics devices</b>. Set this policy to skip External Graphics card scanning if the platform uses Internal Graphics only.
93 UINT32 BdatEnable:1; ///< Offset 60:1 :This field enables the generation of the BIOS DATA ACPI Tables: <b>0=FALSE</b>, 1=TRUE.
94 UINT32 TxtImplemented:1; ///< OFfset 60:2 :This field currently is used to tell MRC if it should run after TXT initializatoin completed: <b>0=Run without waiting for TXT</b>, 1=Run after TXT initialization by callback
95 /**
96 Offset 60:3 :
97 <b>(Test)</b> Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs
98
99 When enabled, if the primary graphics device is an external discrete graphics device, Si will scan the
100 graphics device for legacy only VGA OpROMs.
101
102 This is intended to ease the implementation of a BIOS feature to automatically enable CSM if the Primary Gfx device
103 only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM won't result in no video being displayed.
104 This is useful for platforms that implement PCIe slots that allow the end user to install an arbitrary Gfx device.
105
106 This setting will only take effect if SkipExtGfxScan == 0. It is ignored otherwise.
107
108 - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
109 - <b>Enabled</b> (0x1) : Scan External Gfx for Legacy Only VGA OpROM
110 **/
111 UINT32 ScanExtGfxForLegacyOpRom:1;
112 UINT32 RsvdBits0 :28; ///< Offset 60:4 :Reserved for future use
113 UINT8 UserBd; ///< Offset 64 <b>0=Mobile/Mobile Halo</b>, 1=Desktop/DT Halo, 2=Desktop 2DPC DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server
114 UINT8 LockPTMregs; ///< <b>(Test)</b> Offset 65 Lock PCU Thermal Management registers: 0=FALSE, <b>1=TRUE</b>
115 UINT8 BdatTestType; ///< Offset 66 When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: <b>0=RMT</b>, 1=RMT Per Bit, 2=Margin 2D.
116 UINT8 CridEnable; ///< Offset 67 For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibility Revision ID (CRID) feature: <b>0=FALSE</b>, 1=TRUE
117 UINT32 AcpiReservedMemorySize; ///< Offset 68 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
118 UINT32 OpRomScanTempMmioBar; ///< <b>(Test)</b> Offset 72 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!
119 UINT32 OpRomScanTempMmioLimit; ///< <b>(Test)</b> Offset 76 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >= 16MB!
120 UINT64 AcpiReservedMemoryBase; ///< Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
121 UINT64 SystemMemoryLength; ///< Offset 88 Total system memory length from previous boot, this is required for S3 resume. Originally it is retrieved from AcpiVariableCompatibility variable.
122
123 UINT8 WrcFeatureEnable; ///< Offset 96: Enable/Disable WRC (Write Cache) feature of IOP. When enabled, supports IO devices allocating onto the ring and into LLC.
124 UINT8 FirstDimmBitMask; ///< Offset 97: Defines which DIMM should be populated first on a 2DPC board.
125 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
126 ///< For each MC, the first DIMM to be populated should be set to '1'.
127 ///< Note: this mask is only for non-ECC DIMM.
128 UINT8 FirstDimmBitMaskEcc; ///< Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board.
129 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
130 ///< For each MC, the first DIMM to be populated should be set to '1'.
131 ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
132 ///< be populated firstly.
133 ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
134
135 UINT8 Reserved1[1]; ///< Reserved for config block alignment.
136
137
138 // Since the biggest element is UINT64, this structure should be aligned with 64 bits.
139 UINT8 Rsvd[4]; ///< Reserved for config block alignment.
140 UINT8 ResizableBarSupport;
141
142 UINT8 Rsrvd1[7];
143 } SA_MISC_PEI_PREMEM_CONFIG;
144 #pragma pack(pop)
145
146 #endif // _SA_MISC_PEI_PREMEM_CONFIG_H_
SA_MISC_PEI_PREMEM_CONFIG::BdatTestType
UINT8 BdatTestType
Offset 66 When BdatEnable is set to TRUE, this option selects the type of data which will be populate...
Definition: SaMiscPeiPreMemConfig.h:115
SA_MISC_PEI_PREMEM_CONFIG::OpRomScanTempMmioLimit
UINT32 OpRomScanTempMmioLimit
(Test) Offset 76 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature....
Definition: SaMiscPeiPreMemConfig.h:119
SA_MISC_PEI_PREMEM_CONFIG::UserBd
UINT8 UserBd
Offset 64 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC DDR5, 5=ULT/ULX/Mobile Halo Type3,...
Definition: SaMiscPeiPreMemConfig.h:113
SA_MISC_PEI_PREMEM_CONFIG::SystemMemoryLength
UINT64 SystemMemoryLength
Offset 88 Total system memory length from previous boot, this is required for S3 resume....
Definition: SaMiscPeiPreMemConfig.h:121
SA_MISC_PEI_PREMEM_CONFIG::LockPTMregs
UINT8 LockPTMregs
(Test) Offset 65 Lock PCU Thermal Management registers: 0=FALSE, 1=TRUE
Definition: SaMiscPeiPreMemConfig.h:114
SA_MISC_PEI_PREMEM_CONFIG::OpRomScanTempMmioBar
UINT32 OpRomScanTempMmioBar
(Test) Offset 72 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLega...
Definition: SaMiscPeiPreMemConfig.h:118
SA_MISC_PEI_PREMEM_CONFIG::SmbusBar
UINT32 SmbusBar
Offset 48 Address of System Agent SMBUS BAR: 0xEFA0
Definition: SaMiscPeiPreMemConfig.h:76
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
SA_MISC_PEI_PREMEM_CONFIG::S3DataPtr
VOID * S3DataPtr
Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled wit...
Definition: SaMiscPeiPreMemConfig.h:75
SA_MISC_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: SaMiscPeiPreMemConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SA_MISC_PEI_PREMEM_CONFIG::IedSize
UINT32 IedSize
Offset 56 (Test) Size of IED region in bytes.
Definition: SaMiscPeiPreMemConfig.h:91
SA_MISC_PEI_PREMEM_CONFIG::TsegSize
UINT32 TsegSize
Offset 52 Size of TSEG in bytes.
Definition: SaMiscPeiPreMemConfig.h:82
SA_MISC_PEI_PREMEM_CONFIG::BdatEnable
UINT32 BdatEnable
Offset 60:1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE,...
Definition: SaMiscPeiPreMemConfig.h:93
SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMask
UINT8 FirstDimmBitMask
Offset 97: Defines which DIMM should be populated first on a 2DPC board.
Definition: SaMiscPeiPreMemConfig.h:124
SA_MISC_PEI_PREMEM_CONFIG::ScanExtGfxForLegacyOpRom
UINT32 ScanExtGfxForLegacyOpRom
Offset 60:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs.
Definition: SaMiscPeiPreMemConfig.h:111
SA_MISC_PEI_PREMEM_CONFIG::AcpiReservedMemorySize
UINT32 AcpiReservedMemorySize
Offset 68 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used....
Definition: SaMiscPeiPreMemConfig.h:117
SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMaskEcc
UINT8 FirstDimmBitMaskEcc
Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board.
Definition: SaMiscPeiPreMemConfig.h:128
SA_MISC_PEI_PREMEM_CONFIG::WrcFeatureEnable
UINT8 WrcFeatureEnable
Offset 96: Enable/Disable WRC (Write Cache) feature of IOP. When enabled, supports IO devices allocat...
Definition: SaMiscPeiPreMemConfig.h:123
SA_MISC_PEI_PREMEM_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like pro...
Definition: SaMiscPeiPreMemConfig.h:56
SA_MISC_PEI_PREMEM_CONFIG::AcpiReservedMemoryBase
UINT64 AcpiReservedMemoryBase
Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used....
Definition: SaMiscPeiPreMemConfig.h:120
SA_MISC_PEI_PREMEM_CONFIG::TxtImplemented
UINT32 TxtImplemented
OFfset 60:2 :This field currently is used to tell MRC if it should run after TXT initializatoin compl...
Definition: SaMiscPeiPreMemConfig.h:94
SA_MISC_PEI_PREMEM_CONFIG::CridEnable
UINT8 CridEnable
Offset 67 For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibi...
Definition: SaMiscPeiPreMemConfig.h:116
SA_MISC_PEI_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 60:4 :Reserved for future use.
Definition: SaMiscPeiPreMemConfig.h:112
SA_MISC_PEI_PREMEM_CONFIG::SkipExtGfxScan
UINT32 SkipExtGfxScan
(Test) OFfset 60:0 :1=Skip External Gfx Device Scan; 0=Scan for external graphics devices....
Definition: SaMiscPeiPreMemConfig.h:92
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SataConfig.h File Reference

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  • ClientOneSiliconPkg
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  • ConfigBlock
  • Sata
Classes
SataConfig.h File Reference

Sata policy. More...

#include <PchLimits.h>
#include <ConfigBlock.h>
#include <Library/GpioConfig.h>
Include dependency graph for SataConfig.h:

Go to the source code of this file.

Classes

struct | PCH_SATA_PORT_CONFIG
This structure configures the features, property, and capability for each SATA port. More...
struct | SATA_THERMAL_THROTTLING
This structure lists PCH supported SATA thermal throttling register setting for customization. More...
struct | SATA_CONFIG
The SATA_CONFIG block describes the expected configuration of the SATA controllers. More...

Detailed Description

Sata policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SataConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SataConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
SataConfig.h
Go to the documentation of this file.
1 /** @file
2 Sata policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SATA_CONFIG_H_
36 #define _SATA_CONFIG_H_
37
38 #include <PchLimits.h>
39 #include <ConfigBlock.h>
40 #include <Library/GpioConfig.h>
41
42 #define SATA_CONFIG_REVISION 1
43 extern EFI_GUID gSataConfigGuid;
44
45 #pragma pack (push,1)
46
47 typedef enum {
48 SataModeAhci,
49 SataModeRaid,
50 SataModeMax
51 } SATA_MODE;
52
53 typedef enum {
54 SataSpeedDefault,
55 SataSpeedGen1,
56 SataSpeedGen2,
57 SataSpeedGen3
58 } SATA_SPEED;
59
60 typedef enum {
61 SataRstMsix,
62 SataRstMsi,
63 SataRstLegacy
64 } SATA_RST_INTERRUPT;
65
66 typedef enum {
67 SataRaidClient,
68 SataRaidAlternate,
69 SataRaidServer
70 } SATA_RAID_DEV_ID;
71
72 /**
73 This structure configures the features, property, and capability for each SATA port.
74 **/
75 typedef struct {
76 /**
77 Enable SATA port.
78 It is highly recommended to disable unused ports for power savings
79 **/
80 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
81 UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
82 UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
83 UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
84 UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device
85 UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
86 UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port
87 UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
88 UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>.
89 UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>.
90 /**
91 Support zero power ODD <b>0: Disable</b>, 1: Enable.
92 This is also used to disable ModPHY dynamic power gate.
93 **/
94 UINT32 ZpOdd : 1;
95 UINT32 DevSlpResetConfig : 4; ///< 0: Hardware default; <b>0x01: GpioResumeReset</b>; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: GpioDswReset
96 UINT32 SataPmPtm : 1; ///< Deprecated
97 UINT32 RxPolarity : 1; ///< <b>0: Disable</b>; 1: Enable; Rx Polarity
98 UINT32 RsvdBits0 : 3; ///< Reserved fields for future expansion w/o protocol change
99 UINT32 DevSlpGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SATA_DEVSLP_x*
100 } PCH_SATA_PORT_CONFIG;
101
102 /**
103 This structure lists PCH supported SATA thermal throttling register setting for customization.
104 The settings is programmed through SATA Index/Data registers.
105 When the SuggestedSetting is enabled, the customized values are ignored.
106 **/
107 typedef struct {
108 UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
109 UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
110 UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
111 UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
112
113 UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
114 UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
115 UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
116 UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
117
118 UINT32 P0Tinact : 2; ///< Port 0 Tinactive
119 UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
120 UINT32 P1Tinact : 2; ///< Port 1 Tinactive
121 UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
122 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
123 UINT32 RsvdBits0 : 9; ///< Reserved bits
124 } SATA_THERMAL_THROTTLING;
125
126 /**
127 The SATA_CONFIG block describes the expected configuration of the SATA controllers.
128
129 <b>Revision 1</b>:
130 - Initial version.
131 <b>Revision 2</b>:
132 - Added DevSlpGpioPinMux.
133 **/
134 typedef struct {
135 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
136 ///
137 /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
138 ///
139 UINT8 Enable;
140 UINT8 TestMode; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
141 UINT8 SalpSupport; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management
142 UINT8 PwrOptEnable; ///< 0: Disable; <b>1: Enable</b> SATA Power Optimizer on PCH side.
143 /**
144 EsataSpeedLimit
145 When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
146 Please be noted, this setting could be cleared by HBA reset, which might be issued
147 by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST.
148 To support the Speed Limitation when POST, the EFI AHCI driver should preserve the
149 setting before and after initialization. For support it after POST, it's dependent on
150 driver's behavior.
151 <b>0: Disable</b>; 1: Enable
152 **/
153 UINT8 EsataSpeedLimit;
154 UINT8 LedEnable; ///< SATA LED indicates SATA controller activity. 0: Disable; <b>1: Enable</b> SATA LED.
155 /**
156 This option allows to configure SATA controller device ID while in RAID mode.
157 Refer to SATA_RAID_DEV_ID enumeration for supported options.
158 Choosing Client will allow RST driver loading, RSTe driver will not be able to load
159 Choosing Alternate will not allow RST inbox driver loading in Windows
160 Choosing Server will allow RSTe driver loading, RST driver will not load
161 <b>0: Client</b>; 1: Alternate; 2: Server
162 **/
163 UINT8 RaidDeviceId;
164 /**
165 Controlls which interrupts will be linked to SATA controller CAP list
166 This option will take effect only if SATA controller is in RAID mode
167 Default: <b>PchSataMsix</b>
168 **/
169 UINT8 SataRstInterrupt;
170
171 /**
172 Determines the system will be configured to which SATA mode.
173 Refer to SATA_MODE enumeration for supported options. Default is <b>SataModeAhci</b>.
174 **/
175 UINT8 SataMode;
176 /**
177 Indicates the maximum speed the SATA controller can support.
178 Refer to SATA_SPEED enumeration for supported options.
179 <b>0h: SataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)
180 **/
181 UINT8 SpeedLimit;
182 UINT8 EnclosureSupport; ///< Enclosure Management Support. 0: Disable; 1: Enable
183 /**
184 Controlls whenever Serial GPIO support is enabled for controller
185 <b>0: Disable</b>; 1: Enable
186 **/
187 UINT8 SgpioSupport;
188 /**
189 This member configures the features, property, and capability for each SATA port.
190 **/
191 PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
192 /**
193 This field decides the settings of Sata thermal throttling. When the Suggested Setting
194 is enabled, PCH RC will use the suggested representative values.
195 **/
196 SATA_THERMAL_THROTTLING ThermalThrottling;
197 } SATA_CONFIG;
198
199 #pragma pack (pop)
200
201 #endif // _SATA_CONFIG_H_
SATA_THERMAL_THROTTLING::P1Tinact
UINT32 P1Tinact
Port 1 Tinactive.
Definition: SataConfig.h:120
PCH_SATA_PORT_CONFIG::HotPlug
UINT32 HotPlug
0: Disable; 1: Enable
Definition: SataConfig.h:81
SATA_CONFIG::SpeedLimit
UINT8 SpeedLimit
Indicates the maximum speed the SATA controller can support.
Definition: SataConfig.h:181
ConfigBlock.h
Header file for Config Block Lib implementation.
SATA_THERMAL_THROTTLING::P0Tinact
UINT32 P0Tinact
Port 0 Tinactive.
Definition: SataConfig.h:118
SATA_THERMAL_THROTTLING::P0T2M
UINT32 P0T2M
Port 0 T2 Multipler.
Definition: SataConfig.h:109
SATA_CONFIG::SataRstInterrupt
UINT8 SataRstInterrupt
Controlls which interrupts will be linked to SATA controller CAP list This option will take effect on...
Definition: SataConfig.h:169
PCH_SATA_PORT_CONFIG::RxPolarity
UINT32 RxPolarity
0: Disable; 1: Enable; Rx Polarity
Definition: SataConfig.h:97
SATA_CONFIG::PwrOptEnable
UINT8 PwrOptEnable
0: Disable; 1: Enable SATA Power Optimizer on PCH side.
Definition: SataConfig.h:142
SATA_THERMAL_THROTTLING::P0T3M
UINT32 P0T3M
Port 0 T3 Multipler.
Definition: SataConfig.h:110
SATA_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: SataConfig.h:135
PCH_SATA_PORT_CONFIG::External
UINT32 External
0: Disable; 1: Enable
Definition: SataConfig.h:83
SATA_THERMAL_THROTTLING::P1TDisp
UINT32 P1TDisp
Port 1 Tdispatch.
Definition: SataConfig.h:116
SATA_CONFIG::LedEnable
UINT8 LedEnable
SATA LED indicates SATA controller activity. 0: Disable; 1: Enable SATA LED.
Definition: SataConfig.h:154
PCH_SATA_PORT_CONFIG::SataPmPtm
UINT32 SataPmPtm
Deprecated.
Definition: SataConfig.h:96
SATA_CONFIG::SgpioSupport
UINT8 SgpioSupport
Controlls whenever Serial GPIO support is enabled for controller 0: Disable; 1: Enable.
Definition: SataConfig.h:187
SATA_THERMAL_THROTTLING::P0T1M
UINT32 P0T1M
Port 0 T1 Multipler.
Definition: SataConfig.h:108
SATA_THERMAL_THROTTLING::P1T1M
UINT32 P1T1M
Port 1 T1 Multipler.
Definition: SataConfig.h:113
SATA_CONFIG::EnclosureSupport
UINT8 EnclosureSupport
Enclosure Management Support. 0: Disable; 1: Enable.
Definition: SataConfig.h:182
SATA_CONFIG::Enable
UINT8 Enable
This member describes whether or not the SATA controllers should be enabled.
Definition: SataConfig.h:139
SATA_CONFIG
The SATA_CONFIG block describes the expected configuration of the SATA controllers.
Definition: SataConfig.h:134
SATA_THERMAL_THROTTLING::P0TDispFinit
UINT32 P0TDispFinit
Port 0 Alternate Fast Init Tdispatch.
Definition: SataConfig.h:119
PCH_SATA_PORT_CONFIG::InterlockSw
UINT32 InterlockSw
0: Disable; 1: Enable
Definition: SataConfig.h:82
PCH_SATA_PORT_CONFIG::Enable
UINT32 Enable
Enable SATA port.
Definition: SataConfig.h:80
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_SATA_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved fields for future expansion w/o protocol change.
Definition: SataConfig.h:98
PCH_SATA_PORT_CONFIG::ZpOdd
UINT32 ZpOdd
Support zero power ODD 0: Disable, 1: Enable.
Definition: SataConfig.h:94
PCH_SATA_PORT_CONFIG::SolidStateDrive
UINT32 SolidStateDrive
0: HDD; 1: SSD
Definition: SataConfig.h:85
PCH_SATA_PORT_CONFIG::DevSlp
UINT32 DevSlp
0: Disable; 1: Enable DEVSLP on the port
Definition: SataConfig.h:86
SATA_CONFIG::RaidDeviceId
UINT8 RaidDeviceId
This option allows to configure SATA controller device ID while in RAID mode.
Definition: SataConfig.h:163
PCH_SATA_PORT_CONFIG::DmVal
UINT32 DmVal
DITO multiplier. Default is 15.
Definition: SataConfig.h:88
SATA_CONFIG::TestMode
UINT8 TestMode
(Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes
Definition: SataConfig.h:140
PCH_SATA_PORT_CONFIG
This structure configures the features, property, and capability for each SATA port.
Definition: SataConfig.h:75
SATA_CONFIG::EsataSpeedLimit
UINT8 EsataSpeedLimit
EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
Definition: SataConfig.h:153
SATA_THERMAL_THROTTLING::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values
Definition: SataConfig.h:122
SATA_THERMAL_THROTTLING::P1TDispFinit
UINT32 P1TDispFinit
Port 1 Alternate Fast Init Tdispatch.
Definition: SataConfig.h:121
SATA_THERMAL_THROTTLING
This structure lists PCH supported SATA thermal throttling register setting for customization.
Definition: SataConfig.h:107
SATA_CONFIG::SalpSupport
UINT8 SalpSupport
0: Disable; 1: Enable Aggressive Link Power Management
Definition: SataConfig.h:141
PCH_SATA_PORT_CONFIG::DitoVal
UINT32 DitoVal
DEVSLP Idle Timeout (DITO), Default is 625.
Definition: SataConfig.h:89
SATA_THERMAL_THROTTLING::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: SataConfig.h:123
SATA_CONFIG::ThermalThrottling
SATA_THERMAL_THROTTLING ThermalThrottling
This field decides the settings of Sata thermal throttling.
Definition: SataConfig.h:196
SATA_CONFIG::SataMode
UINT8 SataMode
Determines the system will be configured to which SATA mode.
Definition: SataConfig.h:175
SATA_THERMAL_THROTTLING::P1T2M
UINT32 P1T2M
Port 1 T2 Multipler.
Definition: SataConfig.h:114
PCH_SATA_PORT_CONFIG::EnableDitoConfig
UINT32 EnableDitoConfig
0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
Definition: SataConfig.h:87
SATA_THERMAL_THROTTLING::P0TDisp
UINT32 P0TDisp
Port 0 Tdispatch.
Definition: SataConfig.h:111
PCH_SATA_PORT_CONFIG::DevSlpResetConfig
UINT32 DevSlpResetConfig
0: Hardware default; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: G...
Definition: SataConfig.h:95
SATA_THERMAL_THROTTLING::P1T3M
UINT32 P1T3M
Port 1 T3 Multipler.
Definition: SataConfig.h:115
PCH_SATA_PORT_CONFIG::SpinUp
UINT32 SpinUp
0: Disable; 1: Enable the COMRESET initialization Sequence to the device
Definition: SataConfig.h:84
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
Classes
SerialIoConfig.h File Reference

Serial IO policy. More...

#include <SerialIoDevices.h>
Include dependency graph for SerialIoConfig.h:

Go to the source code of this file.

Classes

struct SERIAL_IO_CONFIG
The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers. More...

Detailed Description

Serial IO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
SerialIoConfig.h
Go to the documentation of this file.
1 /** @file
2 Serial IO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SERIAL_IO_CONFIG_H_
36 #define _SERIAL_IO_CONFIG_H_
37
38 #define SERIAL_IO_CONFIG_REVISION 2
39 extern EFI_GUID gSerialIoConfigGuid;
40
41 #include <SerialIoDevices.h>
42
43 #pragma pack (push,1)
44
45 /**
46 The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
47
48 <b>Revision 1:</b>
49 - Inital version.
50 <b>Revision 2:</b>
51 - Modified SPI Config to support pinmux functionality.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
55 SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration
56 SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration
57 SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
58 } SERIAL_IO_CONFIG;
59
60 #pragma pack (pop)
61
62 #endif // _SERIAL_IO_CONFIG_H_
SerialIoDevices.h
Serial IO policy.
SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration.
Definition: SerialIoDevices.h:236
SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.
Definition: SerialIoDevices.h:94
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SERIAL_IO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: SerialIoConfig.h:54
SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration.
Definition: SerialIoDevices.h:174
SERIAL_IO_CONFIG
The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers.
Definition: SerialIoConfig.h:53
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoDevices.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Enumerations
SerialIoDevices.h File Reference

Serial IO policy. More...

#include <Protocol/SerialIo.h>
#include <PchLimits.h>
Include dependency graph for SerialIoDevices.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SPI_PIN_MUX
SPI signals pin muxing settings. More...
struct | SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller. More...
struct | SERIAL_IO_UART_ATTRIBUTES
UART Settings. More...
struct | UART_PIN_MUX
UART signals pin muxing settings. More...
struct | SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration. More...
struct | I2C_PIN_MUX
I2C signals pin muxing settings. More...
struct | SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration. More...

Enumerations

enum | SERIAL_IO_SPI_MODE
Available working modes for SerialIo SPI Host Controller. More...
enum | SERIAL_IO_CS_POLARITY
Used to set Inactive/Idle polarity of Spi Chip Select.
enum | SERIAL_IO_UART_MODE
Available working modes for SerialIo UART Host Controller. More...
enum | SERIAL_IO_UART_PG
enum | SERIAL_IO_I2C_MODE
Available working modes for SerialIo I2C Host Controller. More...

Detailed Description

Serial IO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoDevices.h.

Enumeration Type Documentation

◆ SERIAL_IO_I2C_MODE

enum SERIAL_IO_I2C_MODE

Available working modes for SerialIo I2C Host Controller.

 0: SerialIoI2cDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoI2cPci;

  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled 2: SerialIoI2cHidden;
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
    Note
    If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.

Definition at line 217 of file SerialIoDevices.h.

◆ SERIAL_IO_SPI_MODE

enum SERIAL_IO_SPI_MODE

Available working modes for SerialIo SPI Host Controller.

 0: SerialIoSpiDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoSpiPci;

  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled 2: SerialIoSpiHidden;
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
    Note
    If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.

Definition at line 65 of file SerialIoDevices.h.

◆ SERIAL_IO_UART_MODE

enum SERIAL_IO_UART_MODE

Available working modes for SerialIo UART Host Controller.

 0: SerialIoUartDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoUartPci;

  • Designated for Serial IO UART OS driver usage
  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled 2: SerialIoUartHidden;
  • Designated for BIOS and/or DBG2 OS kernel debug
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
    Note
    If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space. 3: SerialIoUartCom;
  • Designated for 16550/PNP0501 compatible COM device
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC 4: SerialIoUartSkipInit;
  • Gpio configuration is skipped
  • PSF configuration is skipped
  • BAR assignemnt is skipped
  • D-satate setting is skipped

Definition at line 140 of file SerialIoDevices.h.

◆ SERIAL_IO_UART_PG

enum SERIAL_IO_UART_PG
Enumerator
SerialIoUartPgDisabled | No _PS0/_PS3 support, device left in D0, after initialization.
SerialIoUartPgEnabled | In mode: SerialIoUartCom; _PS0/_PS3 that supports getting device out of reset In mode: SerialIoUartPci Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only.
SerialIoUartPgAuto | _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,

Definition at line 183 of file SerialIoDevices.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIoDevices.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SerialIoDevices.h
Go to the documentation of this file.
1 /** @file
2 Serial IO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SERIAL_IO_DEVICES_H_
36 #define _SERIAL_IO_DEVICES_H_
37
38 #include <Protocol/SerialIo.h>
39 #include <PchLimits.h>
40
41 #pragma pack (push,1)
42
43 /**
44 Available working modes for SerialIo SPI Host Controller
45
46 0: SerialIoSpiDisabled;
47 - Device is placed in D3
48 - Gpio configuration is skipped
49 - PSF:
50 !important! If given device is Function 0 and other higher functions on given device
51 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
52 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
53 <b>1: SerialIoSpiPci;</b>
54 - Gpio pin configuration in native mode for each assigned pin
55 - Device will be enabled in PSF
56 - Only BAR0 will be enabled
57 2: SerialIoSpiHidden;
58 - Gpio pin configuration in native mode for each assigned pin
59 - Device disabled in the PSF
60 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
61 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
62 @note
63 If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
64 **/
65 typedef enum {
66 SerialIoSpiDisabled,
67 SerialIoSpiPci,
68 SerialIoSpiHidden
69 } SERIAL_IO_SPI_MODE;
70
71 /**
72 Used to set Inactive/Idle polarity of Spi Chip Select
73 **/
74 typedef enum {
75 SerialIoSpiCsActiveLow = 0,
76 SerialIoSpiCsActiveHigh = 1
77 } SERIAL_IO_CS_POLARITY;
78
79 /**
80 SPI signals pin muxing settings. If signal can be enable only on a single pin
81 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
82 for supported settings on a given platform
83 **/
84 typedef struct {
85 UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
86 UINT32 Clk; ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
87 UINT32 Miso; ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
88 UINT32 Mosi; ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
89 } SPI_PIN_MUX;
90
91 /**
92 The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
93 **/
94 typedef struct {
95 UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
96 UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
97 UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
98 UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
99 UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
100 UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
101 SPI_PIN_MUX PinMux; ///< SPI Pinmux configuration
102 } SERIAL_IO_SPI_CONFIG;
103
104 /**
105 Available working modes for SerialIo UART Host Controller
106
107 0: SerialIoUartDisabled;
108 - Device is placed in D3
109 - Gpio configuration is skipped
110 - PSF:
111 !important! If given device is Function 0 and other higher functions on given device
112 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
113 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
114 <b>1: SerialIoUartPci;</b>
115 - Designated for Serial IO UART OS driver usage
116 - Gpio pin configuration in native mode for each assigned pin
117 - Device will be enabled in PSF
118 - Only BAR0 will be enabled
119 2: SerialIoUartHidden;
120 - Designated for BIOS and/or DBG2 OS kernel debug
121 - Gpio pin configuration in native mode for each assigned pin
122 - Device disabled in the PSF
123 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
124 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
125 @note
126 If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
127 3: SerialIoUartCom;
128 - Designated for 16550/PNP0501 compatible COM device
129 - Gpio pin configuration in native mode for each assigned pin
130 - Device disabled in the PSF
131 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
132 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
133 4: SerialIoUartSkipInit;
134 - Gpio configuration is skipped
135 - PSF configuration is skipped
136 - BAR assignemnt is skipped
137 - D-satate setting is skipped
138
139 **/
140 typedef enum {
141 SerialIoUartDisabled,
142 SerialIoUartPci,
143 SerialIoUartHidden,
144 SerialIoUartCom,
145 SerialIoUartSkipInit
146 } SERIAL_IO_UART_MODE;
147
148 /**
149 UART Settings
150 **/
151 typedef struct {
152 UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
153 UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
154 UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
155 UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
156 UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
157 } SERIAL_IO_UART_ATTRIBUTES;
158
159 /**
160 UART signals pin muxing settings. If signal can be enable only on a single pin
161 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
162 for supported settings on a given platform
163 **/
164 typedef struct {
165 UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
166 UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
167 UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
168 UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
169 } UART_PIN_MUX;
170
171 /**
172 Serial IO UART Controller Configuration
173 **/
174 typedef struct {
175 SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
176 UART_PIN_MUX PinMux; ///< UART pin mux configuration
177 UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
178 UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
179 UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
180 UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
181 } SERIAL_IO_UART_CONFIG;
182
183 typedef enum {
184 SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
185 /**
186 In mode: SerialIoUartCom;
187 _PS0/_PS3 that supports getting device out of reset
188 In mode: SerialIoUartPci
189 Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
190 **/
191 SerialIoUartPgEnabled,
192 SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
193 } SERIAL_IO_UART_PG;
194
195 /**
196 Available working modes for SerialIo I2C Host Controller
197
198 0: SerialIoI2cDisabled;
199 - Device is placed in D3
200 - Gpio configuration is skipped
201 - PSF:
202 !important! If given device is Function 0 and other higher functions on given device
203 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
204 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
205 <b>1: SerialIoI2cPci;</b>
206 - Gpio pin configuration in native mode for each assigned pin
207 - Device will be enabled in PSF
208 - Only BAR0 will be enabled
209 2: SerialIoI2cHidden;
210 - Gpio pin configuration in native mode for each assigned pin
211 - Device disabled in the PSF
212 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
213 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
214 @note
215 If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
216 **/
217 typedef enum {
218 SerialIoI2cDisabled,
219 SerialIoI2cPci,
220 SerialIoI2cHidden
221 } SERIAL_IO_I2C_MODE;
222
223 /**
224 I2C signals pin muxing settings. If signal can be enable only on a single pin
225 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
226 for supported settings on a given platform
227 **/
228 typedef struct {
229 UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
230 UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
231 } I2C_PIN_MUX;
232
233 /**
234 Serial IO I2C Controller Configuration
235 **/
236 typedef struct {
237 UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
238 /**
239 I2C Pads Internal Termination.
240 For more information please see Platform Design Guide.
241 Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
242 <b>GpioTermNone: No termination</b>,
243 GpioTermWpu1K: 1kOhm weak pull-up,
244 GpioTermWpu5K: 5kOhm weak pull-up,
245 GpioTermWpu20K: 20kOhm weak pull-up
246 **/
247 UINT8 PadTermination;
248 UINT8 Reserved[2];
249 I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
250 } SERIAL_IO_I2C_CONFIG;
251
252
253 #pragma pack (pop)
254
255 #endif // _SERIAL_IO_DEVICES_H_
SERIAL_IO_UART_ATTRIBUTES::BaudRate
UINT32 BaudRate
115200 Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
Definition: SerialIoDevices.h:152
SERIAL_IO_UART_CONFIG::Attributes
SERIAL_IO_UART_ATTRIBUTES Attributes
see SERIAL_IO_UART_ATTRIBUTES
Definition: SerialIoDevices.h:175
SERIAL_IO_SPI_CONFIG::DefaultCsOutput
UINT8 DefaultCsOutput
0 = CS0 CS1, CS2, CS3. Default CS used by the SPI HC
Definition: SerialIoDevices.h:96
SERIAL_IO_UART_MODE
SERIAL_IO_UART_MODE
Available working modes for SerialIo UART Host Controller.
Definition: SerialIoDevices.h:140
SPI_PIN_MUX::Mosi
UINT32 Mosi
MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*.
Definition: SerialIoDevices.h:88
SERIAL_IO_SPI_CONFIG::PinMux
SPI_PIN_MUX PinMux
SPI Pinmux configuration.
Definition: SerialIoDevices.h:101
SERIAL_IO_UART_CONFIG::Mode
UINT8 Mode
SerialIoUartPci see SERIAL_IO_UART_MODE
Definition: SerialIoDevices.h:177
SERIAL_IO_UART_ATTRIBUTES
UART Settings.
Definition: SerialIoDevices.h:151
SERIAL_IO_UART_ATTRIBUTES::StopBits
UINT8 StopBits
1 - One Stop Bit see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
Definition: SerialIoDevices.h:155
I2C_PIN_MUX
I2C signals pin muxing settings.
Definition: SerialIoDevices.h:228
SERIAL_IO_UART_CONFIG::PowerGating
UINT8 PowerGating
SerialIoUartPgAuto Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
Definition: SerialIoDevices.h:179
SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration.
Definition: SerialIoDevices.h:236
SERIAL_IO_UART_PG
SERIAL_IO_UART_PG
Definition: SerialIoDevices.h:183
I2C_PIN_MUX::Scl
UINT32 Scl
SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*.
Definition: SerialIoDevices.h:230
SERIAL_IO_UART_CONFIG::PinMux
UART_PIN_MUX PinMux
UART pin mux configuration.
Definition: SerialIoDevices.h:176
UART_PIN_MUX::Rx
UINT32 Rx
RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*.
Definition: SerialIoDevices.h:165
SERIAL_IO_I2C_CONFIG::PadTermination
UINT8 PadTermination
SerialIoI2cPci see SERIAL_IO_I2C_MODE
Definition: SerialIoDevices.h:247
SERIAL_IO_UART_CONFIG::DBG2
UINT8 DBG2
FALSE If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
Definition: SerialIoDevices.h:178
SERIAL_IO_UART_CONFIG::DmaEnable
UINT8 DmaEnable
TRUE Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
Definition: SerialIoDevices.h:180
UART_PIN_MUX::Rts
UINT32 Rts
RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*.
Definition: SerialIoDevices.h:167
SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.
Definition: SerialIoDevices.h:94
I2C_PIN_MUX::Sda
UINT32 Sda
SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*.
Definition: SerialIoDevices.h:229
SPI_PIN_MUX::Clk
UINT32 Clk
CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*.
Definition: SerialIoDevices.h:86
SERIAL_IO_SPI_MODE
SERIAL_IO_SPI_MODE
Available working modes for SerialIo SPI Host Controller.
Definition: SerialIoDevices.h:65
UART_PIN_MUX
UART signals pin muxing settings.
Definition: SerialIoDevices.h:164
SPI_PIN_MUX
SPI signals pin muxing settings.
Definition: SerialIoDevices.h:84
SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration.
Definition: SerialIoDevices.h:174
SERIAL_IO_CS_POLARITY
SERIAL_IO_CS_POLARITY
Used to set Inactive/Idle polarity of Spi Chip Select.
Definition: SerialIoDevices.h:74
SPI_PIN_MUX::Miso
UINT32 Miso
MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*.
Definition: SerialIoDevices.h:87
UART_PIN_MUX::Tx
UINT32 Tx
TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*.
Definition: SerialIoDevices.h:166
SERIAL_IO_UART_ATTRIBUTES::DataBits
UINT8 DataBits
8 MdePkg.dec PcdUartDefaultDataBits
Definition: SerialIoDevices.h:154
SERIAL_IO_UART_ATTRIBUTES::Parity
UINT8 Parity
1 - No Parity see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
Definition: SerialIoDevices.h:153
SERIAL_IO_I2C_MODE
SERIAL_IO_I2C_MODE
Available working modes for SerialIo I2C Host Controller.
Definition: SerialIoDevices.h:217
UART_PIN_MUX::Cts
UINT32 Cts
CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*.
Definition: SerialIoDevices.h:168
SERIAL_IO_SPI_CONFIG::CsMode
UINT8 CsMode
0 = HW Control 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
Definition: SerialIoDevices.h:99
SerialIoUartPgEnabled
@ SerialIoUartPgEnabled
In mode: SerialIoUartCom; _PS0/_PS3 that supports getting device out of reset In mode: SerialIoUartPc...
Definition: SerialIoDevices.h:191
SerialIoUartPgAuto
@ SerialIoUartPgAuto
_PS0 and _PS3, detection through ACPI if device was initialized prior to first PG....
Definition: SerialIoDevices.h:192
SerialIoUartPgDisabled
@ SerialIoUartPgDisabled
No _PS0/_PS3 support, device left in D0, after initialization.
Definition: SerialIoDevices.h:184
SERIAL_IO_UART_ATTRIBUTES::AutoFlow
UINT8 AutoFlow
FALSE IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
Definition: SerialIoDevices.h:156
SERIAL_IO_SPI_CONFIG::Mode
UINT8 Mode
SerialIoSpiPci see SERIAL_IO_SPI_MODE
Definition: SerialIoDevices.h:95
SERIAL_IO_SPI_CONFIG::CsState
UINT8 CsState
0 = CS is set to low 1 = CS is set to high
Definition: SerialIoDevices.h:100
SERIAL_IO_I2C_CONFIG::PinMux
I2C_PIN_MUX PinMux
I2C pin mux configuration.
Definition: SerialIoDevices.h:249
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
Classes
SiConfig.h File Reference

Si Config Block. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SI_CONFIG
The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...
struct | SVID_SID_VALUE
Subsystem Vendor ID / Subsystem ID. More...

Detailed Description

Si Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
SiConfig.h
Go to the documentation of this file.
1 /** @file
2 Si Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_CONFIG_H_
36 #define _SI_CONFIG_H_
37
38 #define SI_CONFIG_REVISION 2
39
40 extern EFI_GUID gSiConfigGuid;
41
42
43 #pragma pack (push,1)
44
45 /**
46 The Silicon Policy allows the platform code to publish a set of configuration
47 information that the RC drivers will use to configure the silicon hardware.
48
49 <b>Revision 1</b>: - Initial version.
50 <b>Revision 2</b>: - Deprecate CsmFlag
51 **/
52 typedef struct {
53 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
54 //
55 // Platform specific common policies that used by several silicon components.
56 //
57 UINT8 CsmFlag; ///< offset 28 CSM status flag.@deprecated.
58 /**
59 This is used to skip the SSID programming in silicon code.
60 When set to TRUE, silicon code will not do any SSID programming and platform code
61 needs to handle that by itself properly.
62 <b>0: FALSE</b>, 1: TRUE
63 **/
64 UINT8 SkipSsidProgramming; ///< offset 29
65 UINT8 RsvdBytes0[2]; ///< offset 30 - 31
66 /**
67 When SkipSsidProgramming is FALSE, silicon code will use this as default value
68 to program the SVID for all internal devices.
69 <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized SVID.
70 **/
71 UINT16 CustomizedSvid; ///< offset 32 - 33
72 /**
73 When SkipSsidProgramming is FALSE, silicon code will use this as default value
74 to program the Sid for all internal devices.
75 <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized SSID.
76 **/
77 UINT16 CustomizedSsid; ///< offset 34 - 35
78 /**
79 SsidTablePtr contains the SVID_SID_INIT_ENTRY table.
80 This is valid when SkipSsidProgramming is FALSE;
81 It doesn't need to contain entries for all Intel internal devices.
82 It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Func# which needs
83 to be overridden.
84 In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId are required.
85 <b>Default is NULL.</b>
86
87 E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0:31:3 to CCCC:DDDD,
88 it can be done in platform like this:
89 STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] = {0};
90
91 VOID SiPolicyUpdate () {
92 UINT32 EntryCount = 0;
93 SiPolicy->SkipSsidProgramming = FALSE;
94 SiPolicy->SsidTablePtr = mSsidTablePtr;
95
96 mSsidTablePtr[EntryCount].Address.Bits.Device = SpiDeviceNumber ();
97 mSsidTablePtr[EntryCount].Address.Bits.Function = SpiFunctionNumber ();
98 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xAAAA;
99 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xBBBB;
100 EntryCount ++;
101 mSsidTablePtr[EntryCount].Address.Bits.Device = HdaDevNumber ();
102 mSsidTablePtr[EntryCount].Address.Bits.Function = HdaFuncNumber ();
103 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xCCCC;
104 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xDDDD;
105 EntryCount ++;
106 ASSERT (EntryCount < SI_MAX_DEVICE_COUNT);
107 SiPolicy->NumberOfSsidTableEntry = EntryCount;
108 }
109 **/
110 UINT32 *SsidTablePtr; ///< offset 36 - 39
111 /**
112 Number of valid enties in SsidTablePtr.
113 This is valid when SkipSsidProgramming is FALSE;
114 <b>Default is 0.</b>
115 **/
116 UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41
117 UINT8 RsvdBytes1[2]; ///< offset 42 - 43
118 /**
119 This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
120 When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
121 skip setting BIOS_DONE MSR at EndofPei.
122 <b>0: FALSE</b>, 1: TRUE
123 **/
124 UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44
125 UINT8 RsvdBytes2[3]; ///< Offset 45 - 47
126 } SI_CONFIG;
127
128 #pragma pack (pop)
129
130 #define DEFAULT_SSVID 0x8086
131 #define DEFAULT_SSDID 0x7270
132 #define SI_MAX_DEVICE_COUNT 70
133
134 ///
135 /// Subsystem Vendor ID / Subsystem ID
136 ///
137 typedef struct {
138 UINT16 SubSystemVendorId;
139 UINT16 SubSystemId;
140 } SVID_SID_VALUE;
141
142 //
143 // Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
144 //
145 typedef struct {
146 union {
147 struct {
148 UINT32 Register:12;
149 UINT32 Function:3;
150 UINT32 Device:5;
151 UINT32 Bus:8;
152 UINT32 Reserved1:4;
153 UINT32 Segment:16;
154 UINT32 Reserved2:16;
155 } Bits;
156 UINT64 SegBusDevFuncRegister;
157 } Address;
158 SVID_SID_VALUE SvidSidValue;
159 UINT32 Reserved;
160 } SVID_SID_INIT_ENTRY;
161
162
163 typedef struct {
164 UINT32 SkipBus;
165 UINT32 SkipDevice;
166 UINT32 SkipFunction;
167 } SVID_SID_SKIP_TABLE;
168
169 #endif // _SI_CONFIG_H_
SI_CONFIG::SkipBiosDoneWhenFwUpdate
UINT8 SkipBiosDoneWhenFwUpdate
This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
Definition: SiConfig.h:124
SI_CONFIG::SsidTablePtr
UINT32 * SsidTablePtr
SsidTablePtr contains the SVID_SID_INIT_ENTRY table.
Definition: SiConfig.h:110
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SI_CONFIG::CustomizedSsid
UINT16 CustomizedSsid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for...
Definition: SiConfig.h:77
SI_CONFIG::CsmFlag
UINT8 CsmFlag
offset 28 CSM status flag.
Definition: SiConfig.h:57
SI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: SiConfig.h:53
SI_CONFIG
The Silicon Policy allows the platform code to publish a set of configuration information that the RC...
Definition: SiConfig.h:52
SVID_SID_VALUE
Subsystem Vendor ID / Subsystem ID.
Definition: SiConfig.h:137
SI_CONFIG::CustomizedSvid
UINT16 CustomizedSvid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID fo...
Definition: SiConfig.h:71
SI_CONFIG::NumberOfSsidTableEntry
UINT16 NumberOfSsidTableEntry
Number of valid enties in SsidTablePtr.
Definition: SiConfig.h:116
SI_CONFIG::SkipSsidProgramming
UINT8 SkipSsidProgramming
This is used to skip the SSID programming in silicon code.
Definition: SiConfig.h:64
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SiPolicyStruct.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros
SiPolicyStruct.h File Reference

Intel reference code configuration policies. More...

#include <ConfigBlock.h>
#include <ConfigBlock/SiPreMemConfig.h>
#include <ConfigBlock/SiConfig.h>
Include dependency graph for SiPolicyStruct.h:

Go to the source code of this file.

Classes

struct | _SI_PREMEM_POLICY_STRUCT
SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

. More...
struct | _SI_POLICY_STRUCT
SI Policy PPI
All SI config block change history will be listed here

. More...

Macros

#define | SI_POLICY_REVISION 1
Silicon Policy revision number Any change to this structure will result in an update in the revision number. More...
#define | SI_PREMEM_POLICY_REVISION 1
Silicon pre-memory Policy revision number Any change to this structure will result in an update in the revision number. More...

Detailed Description

Intel reference code configuration policies.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPolicyStruct.h.

Macro Definition Documentation

◆ SI_POLICY_REVISION

#define SI_POLICY_REVISION 1

Silicon Policy revision number Any change to this structure will result in an update in the revision number.

This member specifies the revision of the Silicon Policy. This field is used to indicate change to the policy structure.

Revision 1:

  • Initial version.

Definition at line 52 of file SiPolicyStruct.h.

◆ SI_PREMEM_POLICY_REVISION

#define SI_PREMEM_POLICY_REVISION 1

Silicon pre-memory Policy revision number Any change to this structure will result in an update in the revision number.

Revision 1:

  • Initial version.

Definition at line 61 of file SiPolicyStruct.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SiPolicyStruct.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SiPolicyStruct.h
Go to the documentation of this file.
1 /** @file
2 Intel reference code configuration policies.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_POLICY_STRUCT_H_
36 #define _SI_POLICY_STRUCT_H_
37
38 #include <ConfigBlock.h>
39 #include <ConfigBlock/SiPreMemConfig.h>
40 #include <ConfigBlock/SiConfig.h>
41
42 /**
43 Silicon Policy revision number
44 Any change to this structure will result in an update in the revision number
45
46 This member specifies the revision of the Silicon Policy. This field is used to indicate change
47 to the policy structure.
48
49 <b>Revision 1</b>:
50 - Initial version.
51 **/
52 #define SI_POLICY_REVISION 1
53
54 /**
55 Silicon pre-memory Policy revision number
56 Any change to this structure will result in an update in the revision number
57
58 <b>Revision 1</b>:
59 - Initial version.
60 **/
61 #define SI_PREMEM_POLICY_REVISION 1
62
63
64 /**
65 SI Policy PPI in Pre-Mem\n
66 All SI config block change history will be listed here\n\n
67
68 - <b>Revision 1</b>:
69 - Initial version.\n
70 **/
71 struct _SI_PREMEM_POLICY_STRUCT {
72 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
73 /*
74 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
75 */
76 };
77
78 /**
79 SI Policy PPI\n
80 All SI config block change history will be listed here\n\n
81
82 - <b>Revision 1</b>:
83 - Initial version.\n
84 **/
85 struct _SI_POLICY_STRUCT {
86 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
87 /*
88 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
89 */
90 };
91
92 #endif
_SI_PREMEM_POLICY_STRUCT::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.
Definition: SiPolicyStruct.h:72
ConfigBlock.h
Header file for Config Block Lib implementation.
SiPreMemConfig.h
Si Config Block PreMem.
_SI_PREMEM_POLICY_STRUCT
SI Policy PPI in Pre-Mem All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:71
_SI_POLICY_STRUCT
SI Policy PPI All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:85
SiConfig.h
Si Config Block.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_SI_POLICY_STRUCT::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.
Definition: SiPolicyStruct.h:86
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
Classes
SiPreMemConfig.h File Reference

Si Config Block PreMem. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct SI_PREMEM_CONFIG
The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

Detailed Description

Si Config Block PreMem.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
SiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 Si Config Block PreMem
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_PREMEM_CONFIG_H_
36 #define _SI_PREMEM_CONFIG_H_
37
38 #define SI_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gSiPreMemConfigGuid;
41
42 typedef enum {
43 ProbeTypeDisabled = 0x00,
44 ProbeTypeDciOob = 0x02,
45 ProbeType2WireDciOob = 0x06,
46 ProbeTypeManual = 0x07,
47 ProbeTypeMax
48 } PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
49
50 #pragma pack (push,1)
51 /**
52 The Silicon PreMem Policy allows the platform code to publish a set of configuration
53 information that the RC drivers will use to configure the silicon hardware.
54
55 <b>Revision 1</b>:
56 - Initial version.
57 **/
58 typedef struct {
59 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
60 /**
61 Platform Debug Consent
62 As a main switch to enable platform debug capability and relevant settings with specified probe type.
63 Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.
64
65 PDC-dependent policies are listed:
66 DciPreMemConfig->DciEn
67 CpuTraceHubConfig->EnableMode
68 CpuTraceHubConfig->CpuTraceHubMemReg0Size
69 CpuTraceHubConfig->CpuTraceHubMemReg1Size
70 PchTraceHubPreMemConfig->EnableMode
71 PchTraceHubPreMemConfig->MemReg0Size
72 PchTraceHubPreMemConfig->MemReg1Size
73
74 Note: DCI OOB (aka BSSB) uses CCA probe.
75 Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
76 <b>0:Disabled</b>; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual
77 **/
78 UINT32 PlatformDebugConsent : 4; /// offset 28 - 31
79 UINT32 RsvdBits : 28;
80 /**
81 This is used to skip override boot mode during firmware update boot mode.
82 When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
83 skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
84 <b>0: FALSE</b>, 1: TRUE
85 **/
86 UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32
87 UINT8 RsvdBytes[3]; /// offset 33 - 35
88 } SI_PREMEM_CONFIG;
89
90 #pragma pack (pop)
91 #endif // _SI_PREMEM_CONFIG_H_
SI_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
offset 28 - 31
Definition: SiPreMemConfig.h:79
SI_PREMEM_CONFIG
The Silicon PreMem Policy allows the platform code to publish a set of configuration information that...
Definition: SiPreMemConfig.h:58
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SI_PREMEM_CONFIG::PlatformDebugConsent
UINT32 PlatformDebugConsent
Platform Debug Consent As a main switch to enable platform debug capability and relevant settings wit...
Definition: SiPreMemConfig.h:78
SI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: SiPreMemConfig.h:59
SI_PREMEM_CONFIG::SkipOverrideBootModeWhenFwUpdate
UINT8 SkipOverrideBootModeWhenFwUpdate
This is used to skip override boot mode during firmware update boot mode.
Definition: SiPreMemConfig.h:86
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SmbusConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
Classes
SmbusConfig.h File Reference

Smbus policy. More...

Go to the source code of this file.

Classes

struct PCH_SMBUS_PREMEM_CONFIG
The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. More...

Detailed Description

Smbus policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SmbusConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SmbusConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
SmbusConfig.h
Go to the documentation of this file.
1 /** @file
2 Smbus policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SMBUS_CONFIG_H_
36 #define _SMBUS_CONFIG_H_
37
38 #define PCH_SMBUS_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gSmbusPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 #define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
44
45 ///
46 /// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
47 ///
48 typedef struct {
49 /**
50 Revision 1: Init version
51 **/
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 /**
54 This member describes whether or not the SMBus controller of PCH should be enabled.
55 0: Disable; <b>1: Enable</b>.
56 **/
57 UINT32 Enable : 1;
58 UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
59 UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
60 ///
61 /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
62 /// For security recommendations, SPD write disable bit must be set.
63 ///
64 UINT32 SpdWriteDisable : 1;
65 UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
66 UINT32 RsvdBits0 : 27; ///< Reserved bits
67 UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
68 UINT8 Rsvd0; ///< Reserved bytes
69 UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
70 /**
71 Array of addresses reserved for non-ARP-capable SMBus devices.
72 **/
73 UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
74 } PCH_SMBUS_PREMEM_CONFIG;
75
76 #pragma pack (pop)
77
78 #endif // _SMBUS_CONFIG_H_
PCH_SMBUS_PREMEM_CONFIG::SmbusIoBase
UINT16 SmbusIoBase
SMBUS Base Address (IO space). Default is 0xEFA0.
Definition: SmbusConfig.h:67
PCH_SMBUS_PREMEM_CONFIG
The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
Definition: SmbusConfig.h:48
PCH_SMBUS_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Revision 1: Init version.
Definition: SmbusConfig.h:52
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_SMBUS_PREMEM_CONFIG::SpdWriteDisable
UINT32 SpdWriteDisable
(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit.
Definition: SmbusConfig.h:64
PCH_SMBUS_PREMEM_CONFIG::Rsvd0
UINT8 Rsvd0
Reserved bytes.
Definition: SmbusConfig.h:68
PCH_SMBUS_PREMEM_CONFIG::DynamicPowerGating
UINT32 DynamicPowerGating
(Test) Disable or Enable Smbus dynamic power gating.
Definition: SmbusConfig.h:59
PCH_SMBUS_PREMEM_CONFIG::SmbAlertEnable
UINT32 SmbAlertEnable
Enable SMBus Alert pin (SMBALERT#). 0: Disabled, 1: Enabled.
Definition: SmbusConfig.h:65
PCH_SMBUS_PREMEM_CONFIG::NumRsvdSmbusAddresses
UINT8 NumRsvdSmbusAddresses
The number of elements in the RsvdSmbusAddressTable.
Definition: SmbusConfig.h:69
PCH_SMBUS_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: SmbusConfig.h:66
PCH_SMBUS_PREMEM_CONFIG::Enable
UINT32 Enable
This member describes whether or not the SMBus controller of PCH should be enabled.
Definition: SmbusConfig.h:57
PCH_SMBUS_PREMEM_CONFIG::ArpEnable
UINT32 ArpEnable
Enable SMBus ARP support, 0: Disable; 1: Enable.
Definition: SmbusConfig.h:58
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Classes
TcssPeiConfig.h File Reference

TCSS PEI policy. More...

#include <ConfigBlock.h>
#include <UsbConfig.h>
#include <TcssInfo.h>
Include dependency graph for TcssPeiConfig.h:

Go to the source code of this file.

Classes

struct | IOM_AUX_ORI_PAD_CONFIG
The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. More...
struct | IOM_INTERFACE_CONFIG
The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC. More...
struct | PMC_INTERFACE_CONFIG
The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC. More...
struct | SA_XDCI_IRQ_INT_CONFIG
The SA XDCI INT Pin and IRQ number. More...
struct | TCSS_PCIE_PORT_POLICY
The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. More...
struct | TCSS_PCIE_PEI_POLICY
TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. More...
struct | TCSS_IOM_ORI_OVERRIDE
The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS. More...
struct | TCSS_IOM_PEI_CONFIG
The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. More...
struct | TCSS_MISC_PEI_CONFIG
The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. More...
struct | TCSS_PEI_CONFIG
The TCSS_PEI_CONFIG block describes TCSS settings for SA. More...

Detailed Description

TCSS PEI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssPeiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
TcssPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 TCSS PEI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCSS_PEI_CONFIG_H_
36 #define _TCSS_PEI_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <UsbConfig.h>
40 #include <TcssInfo.h>
41
42 #define TCSS_PEI_CONFIG_REVISION 4
43 extern EFI_GUID gTcssPeiConfigGuid;
44
45 #pragma pack (push,1)
46
47
48 #define MAX_IOM_AUX_BIAS_COUNT 4
49
50 ///
51 /// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
52 /// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
53 /// IOM needs know Pull-Up and Pull-Down pin for Bias control
54 ///
55 typedef struct {
56 UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
57 UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
58 } IOM_AUX_ORI_PAD_CONFIG;
59
60 ///
61 /// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
62 ///
63
64 typedef struct {
65 UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
66 UINT32 UsbOverride; ///< IOM to override USB connection.
67 UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
68 UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
69 } IOM_INTERFACE_CONFIG;
70
71 ///
72 /// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
73 ///
74 typedef struct {
75 UINT8 PmcPdEnable; ///< PMC PD Solution Enable
76 UINT8 Rsvd[3];
77 } PMC_INTERFACE_CONFIG;
78
79 ///
80 /// The SA XDCI INT Pin and IRQ number
81 ///
82 typedef struct {
83 UINT8 IntPing; ///< Int Pin Number
84 UINT8 Irq; ///< Irq Number
85 UINT16 Rsvd;
86 } SA_XDCI_IRQ_INT_CONFIG;
87
88 ///
89 /// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
90 ///
91 typedef struct {
92 UINT8 AcsEnabled; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
93 UINT8 DpcEnabled; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
94 UINT8 RpDpcExtensionsEnabled; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
95 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
96 UINT8 PtmEnabled; ///< Enables PTM capability
97
98 UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>
99 UINT8 SlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
100 UINT8 SlotPowerLimitScale; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
101 UINT16 SlotPowerLimitValue; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
102
103 UINT8 AdvancedErrorReporting; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
104 UINT8 UnsupportedRequestReport; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
105 UINT8 FatalErrorReport; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
106 UINT8 NoFatalErrorReport; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
107 UINT8 CorrectableErrorReport; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
108 UINT8 SystemErrorOnFatalError; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
109 UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
110 UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
111
112 UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting, Max Snoop Latency.
113 UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting, Max Non-Snoop Latency.
114 UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Snoop Latency Override Mode.
115 UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Snoop Latency Override Multiplier.
116 UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Snoop Latency Override Value.
117 UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
118 UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
119 UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Value.
120 UINT8 ForceLtrOverride; ///< <b>0: Disable</b>; 1: Enable.
121 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
122 } TCSS_PCIE_PORT_POLICY;
123
124 ///
125 /// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
126 ///
127 typedef struct {
128 TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT];
129 } TCSS_PCIE_PEI_POLICY;
130
131 ///
132 /// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
133 ///
134 typedef struct {
135 UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
136 UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
137 } TCSS_IOM_ORI_OVERRIDE;
138
139 ///
140 /// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
141 ///
142 typedef struct {
143 IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
144 TCSS_IOM_ORI_OVERRIDE IomOverrides;
145 IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
146 PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
147 UINT8 TcStateLimit; ///< Tcss C-State deep stage
148 UINT8 Reserved[3]; ///< Reserved bytes for future use
149 } TCSS_IOM_PEI_CONFIG;
150
151 ///
152 /// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
153 ///
154 typedef struct {
155 SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and Irq setting
156 UINT8 EnableTcssCovTypeA[MAX_TCSS_USB3_PORTS]; ///< Enable / Disable Type C Port X Convert to TypeA
157 UINT8 MappingPchXhciUsbA[MAX_TCSS_USB3_PORTS]; ///< PCH xhci port number for Type C Port x mapping
158 UINT8 IomStayInTCColdSeconds; ///< Set IOM stay in TC cold seconds.
159 UINT8 IomBeforeEnteringTCColdSeconds; ///< Set IOM before entering TC cold seconds.
160 UINT8 Rsvd[2]; ///< Reserved bytes for future use.
161 } TCSS_MISC_PEI_CONFIG;
162
163 ///
164 /// The TCSS_PEI_CONFIG block describes TCSS settings for SA.
165 ///
166 typedef struct {
167 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
168 TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config
169 USB_CONFIG UsbConfig; ///< USB config is shared between PCH and SA.
170 TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config
171 TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config
172 } TCSS_PEI_CONFIG;
173
174 #pragma pack (pop)
175
176 #endif /* _TCSS_PEI_CONFIG_H_ */
IOM_AUX_ORI_PAD_CONFIG
The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
Definition: TcssPeiConfig.h:55
TCSS_IOM_PEI_CONFIG::IomInterface
IOM_INTERFACE_CONFIG IomInterface
Config settings are BIOS <-> IOM interface.
Definition: TcssPeiConfig.h:145
ConfigBlock.h
Header file for Config Block Lib implementation.
TCSS_PCIE_PORT_POLICY::DpcEnabled
UINT8 DpcEnabled
Downstream Port Containment. 0: Disable; 1: Enable
Definition: TcssPeiConfig.h:93
TCSS_PCIE_PORT_POLICY::RpDpcExtensionsEnabled
UINT8 RpDpcExtensionsEnabled
RP Extensions for Downstream Port Containment. 0: Disable; 1: Enable
Definition: TcssPeiConfig.h:94
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideValue
UINT16 NonSnoopLatencyOverrideValue
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
Definition: TcssPeiConfig.h:119
USB_CONFIG
This member describes the expected configuration of the USB controller, Platform modules may need to ...
Definition: UsbConfig.h:106
TCSS_IOM_PEI_CONFIG::PmcInterface
PMC_INTERFACE_CONFIG PmcInterface
Config settings for BIOS <-> PMC interface.
Definition: TcssPeiConfig.h:146
TCSS_PCIE_PORT_POLICY::SystemErrorOnNonFatalError
UINT8 SystemErrorOnNonFatalError
Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:109
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideMultiplier
UINT8 SnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
Definition: TcssPeiConfig.h:115
IOM_INTERFACE_CONFIG::D3ColdEnable
UINT32 D3ColdEnable
Enable/disable D3 Cold support in TCSS.
Definition: TcssPeiConfig.h:67
PMC_INTERFACE_CONFIG::PmcPdEnable
UINT8 PmcPdEnable
PMC PD Solution Enable.
Definition: TcssPeiConfig.h:75
TCSS_PCIE_PORT_POLICY::SlotPowerLimitValue
UINT16 SlotPowerLimitValue
(Test) Specifies upper limit on power supplies by slot. Leave as 0 to set to default....
Definition: TcssPeiConfig.h:101
TCSS_IOM_PEI_CONFIG
The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
Definition: TcssPeiConfig.h:142
TCSS_PCIE_PORT_POLICY::LtrEnable
UINT8 LtrEnable
Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:95
IOM_INTERFACE_CONFIG
The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
Definition: TcssPeiConfig.h:64
TCSS_PCIE_PORT_POLICY::AcsEnabled
UINT8 AcsEnabled
Indicate whether the ACS is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:92
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideValue
UINT16 SnoopLatencyOverrideValue
Latency Tolerance Reporting, Snoop Latency Override Value.
Definition: TcssPeiConfig.h:116
TCSS_PCIE_PORT_POLICY::NoFatalErrorReport
UINT8 NoFatalErrorReport
Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:106
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
TCSS_PCIE_PORT_POLICY::UnsupportedRequestReport
UINT8 UnsupportedRequestReport
Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:104
TCSS_PCIE_PORT_POLICY::SystemErrorOnFatalError
UINT8 SystemErrorOnFatalError
Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:108
PMC_INTERFACE_CONFIG
The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC.
Definition: TcssPeiConfig.h:74
TCSS_PCIE_PORT_POLICY::FatalErrorReport
UINT8 FatalErrorReport
Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:105
TCSS_PEI_CONFIG::UsbConfig
USB_CONFIG UsbConfig
USB config is shared between PCH and SA.
Definition: TcssPeiConfig.h:169
TCSS_PCIE_PEI_POLICY
TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
Definition: TcssPeiConfig.h:127
TCSS_PCIE_PORT_POLICY::ForceLtrOverride
UINT8 ForceLtrOverride
0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:120
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideMode
UINT8 SnoopLatencyOverrideMode
Latency Tolerance Reporting, Snoop Latency Override Mode.
Definition: TcssPeiConfig.h:114
TCSS_IOM_ORI_OVERRIDE::AuxOri
UINT16 AuxOri
Bits defining value for IOM Aux Orientation Register.
Definition: TcssPeiConfig.h:135
TCSS_PCIE_PORT_POLICY::SlotNumber
UINT8 SlotNumber
Indicates the slot number for the root port. Default is the value as root port index.
Definition: TcssPeiConfig.h:99
TCSS_PCIE_PORT_POLICY::SlotPowerLimitScale
UINT8 SlotPowerLimitScale
(Test) Specifies scale used for slot power limit value. Leave as 0 to set to default....
Definition: TcssPeiConfig.h:100
TCSS_PCIE_PORT_POLICY::SystemErrorOnCorrectableError
UINT8 SystemErrorOnCorrectableError
Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:110
IOM_AUX_ORI_PAD_CONFIG::GpioPullN
UINT32 GpioPullN
GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
Definition: TcssPeiConfig.h:56
SA_XDCI_IRQ_INT_CONFIG
The SA XDCI INT Pin and IRQ number.
Definition: TcssPeiConfig.h:82
SA_XDCI_IRQ_INT_CONFIG::IntPing
UINT8 IntPing
Int Pin Number.
Definition: TcssPeiConfig.h:83
TCSS_PCIE_PORT_POLICY
The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
Definition: TcssPeiConfig.h:91
TCSS_PEI_CONFIG::PciePolicy
TCSS_PCIE_PEI_POLICY PciePolicy
The PCIe Config.
Definition: TcssPeiConfig.h:168
SA_XDCI_IRQ_INT_CONFIG::Irq
UINT8 Irq
Irq Number.
Definition: TcssPeiConfig.h:84
TCSS_MISC_PEI_CONFIG::IomBeforeEnteringTCColdSeconds
UINT8 IomBeforeEnteringTCColdSeconds
Set IOM before entering TC cold seconds.
Definition: TcssPeiConfig.h:159
TCSS_PCIE_PORT_POLICY::LtrConfigLock
UINT8 LtrConfigLock
0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:121
IOM_INTERFACE_CONFIG::VccSt
UINT32 VccSt
IOM VCCST request. (Not equal to actual VCCST value)
Definition: TcssPeiConfig.h:65
TCSS_PEI_CONFIG::IomConfig
TCSS_IOM_PEI_CONFIG IomConfig
The Iom Config.
Definition: TcssPeiConfig.h:170
TCSS_PEI_CONFIG::MiscConfig
TCSS_MISC_PEI_CONFIG MiscConfig
The MISC Config.
Definition: TcssPeiConfig.h:171
TCSS_MISC_PEI_CONFIG::IomStayInTCColdSeconds
UINT8 IomStayInTCColdSeconds
Set IOM stay in TC cold seconds.
Definition: TcssPeiConfig.h:158
TCSS_PCIE_PORT_POLICY::CorrectableErrorReport
UINT8 CorrectableErrorReport
Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:107
TCSS_PEI_CONFIG
The TCSS_PEI_CONFIG block describes TCSS settings for SA.
Definition: TcssPeiConfig.h:166
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideMultiplier
UINT8 NonSnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
Definition: TcssPeiConfig.h:118
TCSS_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: TcssPeiConfig.h:167
TCSS_PCIE_PORT_POLICY::PtmEnabled
UINT8 PtmEnabled
Enables PTM capability.
Definition: TcssPeiConfig.h:96
IOM_INTERFACE_CONFIG::UsbOverride
UINT32 UsbOverride
IOM to override USB connection.
Definition: TcssPeiConfig.h:66
TCSS_PCIE_PORT_POLICY::Aspm
UINT8 Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
Definition: TcssPeiConfig.h:98
TCSS_PCIE_PORT_POLICY::LtrMaxNoSnoopLatency
UINT16 LtrMaxNoSnoopLatency
Latency Tolerance Reporting, Max Non-Snoop Latency.
Definition: TcssPeiConfig.h:113
TCSS_MISC_PEI_CONFIG::SaXdci
SA_XDCI_IRQ_INT_CONFIG SaXdci
System Agent Xdci Int Pin and Irq setting.
Definition: TcssPeiConfig.h:155
TCSS_IOM_ORI_OVERRIDE
The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
Definition: TcssPeiConfig.h:134
TCSS_MISC_PEI_CONFIG
The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
Definition: TcssPeiConfig.h:154
IOM_INTERFACE_CONFIG::D3HotEnable
UINT32 D3HotEnable
Enable/disable D3 Hot support in TCSS.
Definition: TcssPeiConfig.h:68
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideMode
UINT8 NonSnoopLatencyOverrideMode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
Definition: TcssPeiConfig.h:117
TCSS_PCIE_PORT_POLICY::LtrMaxSnoopLatency
UINT16 LtrMaxSnoopLatency
Latency Tolerance Reporting, Max Snoop Latency.
Definition: TcssPeiConfig.h:112
TCSS_PCIE_PORT_POLICY::AdvancedErrorReporting
UINT8 AdvancedErrorReporting
Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:103
IOM_AUX_ORI_PAD_CONFIG::GpioPullP
UINT32 GpioPullP
GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
Definition: TcssPeiConfig.h:57
TCSS_IOM_ORI_OVERRIDE::HslOri
UINT16 HslOri
Bits defining value for IOM HSL Orientation Register.
Definition: TcssPeiConfig.h:136
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
TCSS_IOM_PEI_CONFIG::TcStateLimit
UINT8 TcStateLimit
Tcss C-State deep stage.
Definition: TcssPeiConfig.h:147
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Classes
TcssPeiPreMemConfig.h File Reference

TCSS PEI PreMem policy. More...

#include <ConfigBlock.h>
Include dependency graph for TcssPeiPreMemConfig.h:

Go to the source code of this file.

Classes

union | TCSS_DEVEN_PEI_PREMEM_CONFIG
The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS. More...
struct | TCSS_USBTC_PEI_PERMEM_CONFIG
The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS. More...
struct | TCSS_MISC_PEI_PREMEM_CONFIG
The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS. More...
struct | TCSS_PEI_PREMEM_CONFIG
This configuration block describes TCSS settings. More...

Detailed Description

TCSS PEI PreMem policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssPeiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TcssPeiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
TcssPeiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 TCSS PEI PreMem policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCSS_PEI_PREMEM_CONFIG_H_
36 #define _TCSS_PEI_PREMEM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define TCSS_PEI_PREMEM_CONFIG_REVISION 2
41 extern EFI_GUID gTcssPeiPreMemConfigGuid;
42
43 #pragma pack (push,1)
44
45 ///
46 /// The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.
47 ///
48 typedef union {
49 UINT32 TcssDevEn; ///< Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH
50 struct{
51 UINT32 TcssItbtPcie0En:1;
52 UINT32 TcssItbtPcie1En:1;
53 UINT32 TcssItbtPcie2En:1;
54 UINT32 TcssItbtPcie3En:1;
55 UINT32 :4;
56 UINT32 TcssXhciEn:1;
57 UINT32 TcssXdciEn:1;
58 UINT32 TcssDma0En:1;
59 UINT32 TcssDma1En:1;
60 UINT32 :20;
61 } TcssDevEnBit;
62 } TCSS_DEVEN_PEI_PREMEM_CONFIG;
63
64 ///
65 /// The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.
66 ///
67 typedef struct {
68 UINT32 UsbTcPortEn : 4; ///< bitmap for USB Type C enabled ports
69 UINT32 Rsvd : 28; ///< Reserved bytes for future use
70 } TCSS_USBTC_PEI_PERMEM_CONFIG;
71
72 /**
73 The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS.\n
74 <b>Revision 1</b>: - Initial version.
75 **/
76 typedef struct {
77 /**
78 This is policy to control Multiple Segment setting.
79 When Disabled all the iTBT PCIe RP are located at Segment0
80 When Enabled all the iTBT PCIe RP are located at Segment1,
81 FSP Wrapper need to update PCIEXBAR and PcdPciExpressRegionLength to 512MB
82 prior to FspmWrapperPeim.
83 <b>0: Disable</b>, 1: Enable
84 **/
85 UINT8 PcieMultipleSegmentEnabled; /// Deprecate
86 UINT8 Rsvd[3]; ///< Reserved bytes for future use, align to multiple 4
87 } TCSS_MISC_PEI_PREMEM_CONFIG;
88
89 /**
90 This configuration block describes TCSS settings.\n
91 <b>Revision 1</b>:
92 - Initial version.
93 <b>Revision 2</b>:
94 - Deprecate PcieMultipleSegmentEnabled
95 **/
96 typedef struct {
97 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
98 TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig;///< TCSS DEVEN
99 TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig;///< USB Type C Port Configuration
100 TCSS_MISC_PEI_PREMEM_CONFIG MiscConfig; ///< The MISC PreMem Config
101 } TCSS_PEI_PREMEM_CONFIG;
102
103 #pragma pack (pop)
104
105 #endif /* _TCSS_PEI_PREMEM_CONFIG_H_ */
ConfigBlock.h
Header file for Config Block Lib implementation.
TCSS_USBTC_PEI_PERMEM_CONFIG::UsbTcPortEn
UINT32 UsbTcPortEn
bitmap for USB Type C enabled ports
Definition: TcssPeiPreMemConfig.h:68
TCSS_DEVEN_PEI_PREMEM_CONFIG::TcssDevEn
UINT32 TcssDevEn
Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH.
Definition: TcssPeiPreMemConfig.h:49
TCSS_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: TcssPeiPreMemConfig.h:97
TCSS_DEVEN_PEI_PREMEM_CONFIG
The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.
Definition: TcssPeiPreMemConfig.h:48
TCSS_MISC_PEI_PREMEM_CONFIG
The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS.
Definition: TcssPeiPreMemConfig.h:76
TCSS_PEI_PREMEM_CONFIG
This configuration block describes TCSS settings.
Definition: TcssPeiPreMemConfig.h:96
TCSS_USBTC_PEI_PERMEM_CONFIG::Rsvd
UINT32 Rsvd
Reserved bytes for future use.
Definition: TcssPeiPreMemConfig.h:69
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TCSS_PEI_PREMEM_CONFIG::DevEnConfig
TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig
TCSS DEVEN.
Definition: TcssPeiPreMemConfig.h:98
TCSS_PEI_PREMEM_CONFIG::UsbTcConfig
TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig
USB Type C Port Configuration.
Definition: TcssPeiPreMemConfig.h:99
TCSS_PEI_PREMEM_CONFIG::MiscConfig
TCSS_MISC_PEI_PREMEM_CONFIG MiscConfig
The MISC PreMem Config.
Definition: TcssPeiPreMemConfig.h:100
TCSS_USBTC_PEI_PERMEM_CONFIG
The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.
Definition: TcssPeiPreMemConfig.h:67
TCSS_MISC_PEI_PREMEM_CONFIG::PcieMultipleSegmentEnabled
UINT8 PcieMultipleSegmentEnabled
This is policy to control Multiple Segment setting.
Definition: TcssPeiPreMemConfig.h:85
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TelemetryPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
Classes
TelemetryPeiConfig.h File Reference

Configurations for Telemetry. More...

#include <ConfigBlock.h>
Include dependency graph for TelemetryPeiConfig.h:

Go to the source code of this file.

Classes

struct | TELEMETRY_PEI_PREMEM_CONFIG
This configuration block describes Telemetry settings in PreMem. More...
struct | TELEMETRY_PEI_CONFIG
This configuration block describes Telemetry settings in PostMem. More...

Detailed Description

Configurations for Telemetry.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TelemetryPeiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TelemetryPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
TelemetryPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for Telemetry
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TELEMETRY_CONFIG_H_
36 #define _TELEMETRY_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #pragma pack (push,1)
41
42 #define TELEMETRY_PEI_CONFIG_REVISION 1
43 #define TELEMETRY_PEI_PREMEM_CONFIG_REVISION 1
44
45 extern EFI_GUID gTelemetryPeiConfigGuid;
46 extern EFI_GUID gTelemetryPeiPreMemConfigGuid;
47
48 /**
49 This configuration block describes Telemetry settings in PreMem.\n
50 <b>Revision 1</b>:
51 - Initial version.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; /// Config Block Header
55 UINT32 CpuCrashLogDevice; /// Enable or Disable CrashLog/Telemetry Device 0- Disable, <b>1- Enable</b>
56 } TELEMETRY_PEI_PREMEM_CONFIG;
57
58 /**
59 This configuration block describes Telemetry settings in PostMem.\n
60 <b>Revision 1</b>:
61 - Initial version.
62 **/
63 typedef struct {
64 CONFIG_BLOCK_HEADER Header; /// Config Block Header
65 UINT32 CpuCrashLogEnable; /// Enable or Disable CrashLog feature 0- Disable, <b>1- Enable</b>
66 } TELEMETRY_PEI_CONFIG;
67
68 #pragma pack (pop)
69
70 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
TELEMETRY_PEI_PREMEM_CONFIG
This configuration block describes Telemetry settings in PreMem.
Definition: TelemetryPeiConfig.h:53
TELEMETRY_PEI_PREMEM_CONFIG::CpuCrashLogDevice
UINT32 CpuCrashLogDevice
Config Block Header.
Definition: TelemetryPeiConfig.h:55
TELEMETRY_PEI_CONFIG
This configuration block describes Telemetry settings in PostMem.
Definition: TelemetryPeiConfig.h:63
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TELEMETRY_PEI_CONFIG::CpuCrashLogEnable
UINT32 CpuCrashLogEnable
Config Block Header.
Definition: TelemetryPeiConfig.h:65
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ThcConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
Classes | Enumerations
ThcConfig.h File Reference

Touch Host Controller policy. More...

Go to the source code of this file.

Classes

struct | THC_HID_OVER_SPI
THC Hid Over SPI mode related settings. More...
struct | THC_PORT
Port Configuration structure required for each Port that THC might use. More...
struct | THC_CONFIG
THC_CONFIG block provides the configurations forTouch Host Controllers. More...

Enumerations

enum | THC_PORT_ASSIGNMENT
Available Port Assignments. More...
enum | THC_MODE
Available modes. More...

Detailed Description

Touch Host Controller policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThcConfig.h.

Enumeration Type Documentation

◆ THC_MODE

enum THC_MODE

Available modes.

Enumerator
Thc | Intel THC protocol.
HidOverSpi | Hid Over SPI protocol.

Definition at line 57 of file ThcConfig.h.

◆ THC_PORT_ASSIGNMENT

enum THC_PORT_ASSIGNMENT

Available Port Assignments.

Enumerator
ThcAssignmentNone | None of the avaialbe controllers assigned.
ThcAssignmentThc0 | Port assigned to THC0.
ThcAssignmentThc1 | Port assigned to THC1.

Definition at line 48 of file ThcConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ThcConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
ThcConfig.h
Go to the documentation of this file.
1 /** @file
2 Touch Host Controller policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _THC_CONFIG_H_
37 #define _THC_CONFIG_H_
38
39 #define THC_CONFIG_REVISION 3
40 extern EFI_GUID gThcConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 Available Port Assignments
46
47 **/
48 typedef enum {
49 ThcAssignmentNone, ///< None of the avaialbe controllers assigned
50 ThcAssignmentThc0, ///< Port assigned to THC0
51 ThcAssignmentThc1 ///< Port assigned to THC1
52 } THC_PORT_ASSIGNMENT;
53
54 /**
55 Available modes
56 **/
57 typedef enum {
58 Thc, ///< Intel THC protocol
59 HidOverSpi ///< Hid Over SPI protocol
60 } THC_MODE;
61
62
63 /**
64 THC Hid Over SPI mode related settings. Only applicable when HidOverSpi is enbled.
65 **/
66 typedef struct {
67 UINT32 ResetPad; ///< Reset Pad - <b>0x0 = THC HW default</b> BIOS will pass Pad infromation to ACPI, this Pad is used in _RST function or by the BIOS Quick SPI driver
68 UINT32 ResetPadTrigger; ///< Reset Pad Trigger
69 UINT32 Frequency; ///< Connection Speed - SPI Frequency in Hz
70 UINT32 InputReportHeaderAddress; ///< Input Report Header Address
71 UINT32 InputReportBodyAddress; ///< Input Report Body Address
72 UINT32 OutputReportAddress; ///< Output Report Address
73 UINT32 ReadOpcode; ///< Read Opcode
74 UINT32 WriteOpcode; ///< Write Opcode
75 UINT32 Flags; ///< Flags
76 } THC_HID_OVER_SPI;
77
78 /**
79 Port Configuration structure required for each Port that THC might use.
80
81 **/
82 typedef struct {
83 UINT32 Assignment; ///< Sets THCx assignment see THC_PORT_ASSIGNMENT
84 UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*
85 UINT8 WakeOnTouch; ///< 1 = Enable <b>0 = Disable</b>. Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI
86 UINT8 Mode; ///< 1 = Hid over SPI <b>0 = THC</b>. Switch between Intel THC protcol and Industry standard HID Over SPI protocol.
87 UINT8 Reserved[2]; ///< Reserved
88 THC_HID_OVER_SPI HidOverSpi; ///< Hid Over Spi mode settings
89 UINT32 ActiveLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Active Ltr
90 UINT32 IdleLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Idle Ltr
91 UINT32 LimitPacketSize; ///< Limit Packet Size
92 UINT32 PerformanceLimitation; ///< Performance Limitation
93 } THC_PORT;
94
95 /**
96 THC_CONFIG block provides the configurations forTouch Host Controllers
97
98 Assignment field in each THC port controlls the THC behavior.
99
100 Available scenarios:
101 1: Single Port 0 used by THC0
102 - THC0 Enabled
103 - Port0 assigned to THC0
104 - Port1 unassigned
105 - THC1 will be automatically Disabled.
106 2: Both ports used by THC0
107 - THC0 Enabled
108 - Port0 assigned to THC0
109 - Port1 assigned to THC0
110 - THC1 will be automatically Disabled.
111 3: Port 0 used by THC0 and Port 1 used by THC1
112 - THC0 Enabled
113 - Port0 assigned to THC0
114 - THC1 Enabled
115 - Port1 assigned to THC1.
116 <b>4: Both Ports unassigned.</b>
117 Both THC Controllers will be disabled in that case.
118
119 @note
120 Invalid scenario that will cause ASSERT.
121 1. Same port Number assigned to THC0 or THC1.
122 2. Two Ports assigned to THC1.
123
124 **/
125 typedef struct {
126 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
127 THC_PORT ThcPort[2]; ///< Port Configuration
128 } THC_CONFIG;
129
130 #pragma pack (pop)
131
132 #endif // _THC_CONFIG_H_
THC_HID_OVER_SPI::Frequency
UINT32 Frequency
Connection Speed - SPI Frequency in Hz.
Definition: ThcConfig.h:69
THC_HID_OVER_SPI::ReadOpcode
UINT32 ReadOpcode
Read Opcode.
Definition: ThcConfig.h:73
THC_MODE
THC_MODE
Available modes.
Definition: ThcConfig.h:57
THC_HID_OVER_SPI::Flags
UINT32 Flags
Flags.
Definition: ThcConfig.h:75
ThcAssignmentNone
@ ThcAssignmentNone
None of the avaialbe controllers assigned.
Definition: ThcConfig.h:49
HidOverSpi
@ HidOverSpi
Hid Over SPI protocol.
Definition: ThcConfig.h:59
THC_HID_OVER_SPI::ResetPad
UINT32 ResetPad
Reset Pad - 0x0 = THC HW default BIOS will pass Pad infromation to ACPI, this Pad is used in _RST fun...
Definition: ThcConfig.h:67
ThcAssignmentThc1
@ ThcAssignmentThc1
Port assigned to THC1.
Definition: ThcConfig.h:51
THC_PORT::InterruptPinMuxing
UINT32 InterruptPinMuxing
Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*.
Definition: ThcConfig.h:84
THC_PORT
Port Configuration structure required for each Port that THC might use.
Definition: ThcConfig.h:82
THC_PORT::Assignment
UINT32 Assignment
Sets THCx assignment see THC_PORT_ASSIGNMENT.
Definition: ThcConfig.h:83
Thc
@ Thc
Intel THC protocol.
Definition: ThcConfig.h:58
THC_PORT::IdleLtr
UINT32 IdleLtr
0xFFFFFFFF = Driver Default Idle Ltr
Definition: ThcConfig.h:90
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
THC_PORT::HidOverSpi
THC_HID_OVER_SPI HidOverSpi
Hid Over Spi mode settings.
Definition: ThcConfig.h:88
THC_PORT::LimitPacketSize
UINT32 LimitPacketSize
Limit Packet Size.
Definition: ThcConfig.h:91
THC_HID_OVER_SPI
THC Hid Over SPI mode related settings.
Definition: ThcConfig.h:66
THC_PORT::WakeOnTouch
UINT8 WakeOnTouch
1 = Enable 0 = Disable. Based on this setting vGPIO for given THC will be in native mode,...
Definition: ThcConfig.h:85
THC_HID_OVER_SPI::InputReportBodyAddress
UINT32 InputReportBodyAddress
Input Report Body Address.
Definition: ThcConfig.h:71
THC_PORT::PerformanceLimitation
UINT32 PerformanceLimitation
Performance Limitation.
Definition: ThcConfig.h:92
THC_HID_OVER_SPI::OutputReportAddress
UINT32 OutputReportAddress
Output Report Address.
Definition: ThcConfig.h:72
THC_HID_OVER_SPI::InputReportHeaderAddress
UINT32 InputReportHeaderAddress
Input Report Header Address.
Definition: ThcConfig.h:70
THC_PORT::ActiveLtr
UINT32 ActiveLtr
0xFFFFFFFF = Driver Default Active Ltr
Definition: ThcConfig.h:89
THC_PORT_ASSIGNMENT
THC_PORT_ASSIGNMENT
Available Port Assignments.
Definition: ThcConfig.h:48
THC_HID_OVER_SPI::ResetPadTrigger
UINT32 ResetPadTrigger
Reset Pad Trigger.
Definition: ThcConfig.h:68
THC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: ThcConfig.h:126
ThcAssignmentThc0
@ ThcAssignmentThc0
Port assigned to THC0.
Definition: ThcConfig.h:50
THC_PORT::Mode
UINT8 Mode
1 = Hid over SPI 0 = THC. Switch between Intel THC protcol and Industry standard HID Over SPI protoco...
Definition: ThcConfig.h:86
THC_CONFIG
THC_CONFIG block provides the configurations forTouch Host Controllers.
Definition: ThcConfig.h:125
THC_HID_OVER_SPI::WriteOpcode
UINT32 WriteOpcode
Write Opcode.
Definition: ThcConfig.h:74
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ThermalConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
Classes
ThermalConfig.h File Reference

Thermal policy. More...

Go to the source code of this file.

Classes

struct | THERMAL_THROTTLE_LEVELS
This structure lists PCH supported throttling register setting for custimization. More...
struct | DMI_HW_WIDTH_CONTROL
This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. More...
struct | TS_GPIO_PIN_SETTING
This structure configures PCH memory throttling thermal sensor GPIO PIN settings. More...
struct | PCH_MEMORY_THROTTLING
This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board). More...
struct | THERMAL_CONFIG
The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block. More...

Detailed Description

Thermal policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThermalConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ThermalConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
ThermalConfig.h
Go to the documentation of this file.
1 /** @file
2 Thermal policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _THERMAL_CONFIG_H_
36 #define _THERMAL_CONFIG_H_
37
38 #define THERMAL_CONFIG_REVISION 1
39 extern EFI_GUID gThermalConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure lists PCH supported throttling register setting for custimization.
45 When the SuggestedSetting is enabled, the customized values are ignored.
46 **/
47 typedef struct {
48 UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
49 UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
50 UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
51 UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
52 /**
53 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
54 If SuggestedSetting is used, this setting is ignored.
55 **/
56 UINT32 TTState13Enable : 1;
57 /**
58 When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
59 If SuggestedSetting is used, this setting is ignored.
60 **/
61 UINT32 TTLock : 1;
62 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values.
63 /**
64 ULT processors support thermal management and cross thermal throttling between the processor package
65 and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH
66 thermal status to the processor which is factored into the processor throttling.
67 Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
68 **/
69 UINT32 PchCrossThrottling : 1;
70 UINT32 Rsvd0; ///< Reserved bytes
71 } THERMAL_THROTTLE_LEVELS;
72
73 //
74 // Supported Thermal Sensor Target Width
75 //
76 typedef enum {
77 DmiThermSensWidthX1 = 0,
78 DmiThermSensWidthX2 = 1,
79 DmiThermSensWidthX4 = 2,
80 DmiThermSensWidthX8 = 3,
81 DmiThermSensWidthX16 = 4
82 } DMI_THERMAL_SENSOR_TARGET_WIDTH;
83
84 /**
85 This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.
86 When the SuggestedSetting is enabled, the customized values are ignored.
87 Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values
88 **/
89 typedef struct {
90 UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable
91 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
92 UINT32 RsvdBits0 : 6; ///< Reserved bits
93 UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width (<b>DmiThermSensWidthx8</b>)
94 UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width (<b>DmiThermSensWidthx4</b>)
95 UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width (<b>DmiThermSensWidthx2</b>)
96 UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width (<b>DmiThermSensWidthx1</b>)
97 UINT32 RsvdBits1 : 12; ///< Reserved bits
98 } DMI_HW_WIDTH_CONTROL;
99
100 /**
101 This structure configures PCH memory throttling thermal sensor GPIO PIN settings
102 **/
103 typedef struct {
104 /**
105 GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
106 When enabled, RC will overrides the selected GPIO native mode.
107 For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
108 For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
109 For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.
110 **/
111 UINT32 PmsyncEnable : 1;
112 UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:<b>Enabled</b>
113 UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0: default</b>, 1: secondary
114 UINT32 RsvdBits0 : 29;
115 } TS_GPIO_PIN_SETTING;
116
117 enum PCH_PMSYNC_GPIO_X_SELECTION {
118 TsGpioC,
119 TsGpioD,
120 MaxTsGpioPin
121 };
122
123 /**
124 This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
125 **/
126 typedef struct {
127 /**
128 This will enable PCH memory throttling.
129 While this policy is enabled, must also enable EnableExtts in SA policy.
130 <b>0: Disable</b>; 1: Enable
131 **/
132 UINT32 Enable : 1;
133 UINT32 RsvdBits0 : 31;
134 /**
135 GPIO_C and GPIO_D selection for memory throttling.
136 It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature,
137 and route EXTTS# accordingly.
138 **/
139 TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
140 } PCH_MEMORY_THROTTLING;
141
142 /**
143 The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.
144 **/
145 typedef struct {
146 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
147 UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: <b>Disabled<b>, 1: Enabled.
148 UINT32 RsvdBits0 : 31;
149 /**
150 This field decides the settings of Thermal throttling. When the Suggested Setting
151 is enabled, PCH RC will use the suggested representative values.
152 **/
153 THERMAL_THROTTLE_LEVELS TTLevels;
154 /**
155 This field decides the settings of DMI throttling. When the Suggested Setting
156 is enabled, PCH RC will use the suggested representative values.
157 **/
158 DMI_HW_WIDTH_CONTROL DmiHaAWC;
159 /**
160 Memory Thermal Management settings
161 **/
162 PCH_MEMORY_THROTTLING MemoryThrottling;
163 /**
164 The recommendation is the same as Cat Trip point.
165 This field decides the temperature, default is <b>120</b>.
166 Temperature value used for PCHHOT# pin assertion based on 2s complement format
167 - 0x001 positive 1'C
168 - 0x000 0'C
169 - 0x1FF negative 1'C
170 - 0x1D8 negative 40'C
171 - and so on
172 **/
173 UINT16 PchHotLevel;
174 UINT8 Rsvd0[6];
175
176
177 } THERMAL_CONFIG;
178
179 #pragma pack (pop)
180
181 #endif // _THERMAL_CONFIG_H_
DMI_HW_WIDTH_CONTROL::DmiTsawEn
UINT32 DmiTsawEn
DMI Thermal Sensor Autonomous Width Enable.
Definition: ThermalConfig.h:90
THERMAL_THROTTLE_LEVELS::T0Level
UINT32 T0Level
Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:48
TS_GPIO_PIN_SETTING::PmsyncEnable
UINT32 PmsyncEnable
GPIO PM_SYNC enable, 0:Diabled, 1:Enabled When enabled, RC will overrides the selected GPIO native mo...
Definition: ThermalConfig.h:111
TS_GPIO_PIN_SETTING
This structure configures PCH memory throttling thermal sensor GPIO PIN settings.
Definition: ThermalConfig.h:103
THERMAL_THROTTLE_LEVELS::TTEnable
UINT32 TTEnable
Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
Definition: ThermalConfig.h:51
THERMAL_THROTTLE_LEVELS::TTLock
UINT32 TTLock
When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
Definition: ThermalConfig.h:61
DMI_HW_WIDTH_CONTROL::TS0TW
UINT32 TS0TW
Thermal Sensor 0 Target Width (DmiThermSensWidthx8)
Definition: ThermalConfig.h:93
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
DMI_HW_WIDTH_CONTROL::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: ThermalConfig.h:92
THERMAL_CONFIG::MemoryThrottling
PCH_MEMORY_THROTTLING MemoryThrottling
Memory Thermal Management settings.
Definition: ThermalConfig.h:162
THERMAL_THROTTLE_LEVELS
This structure lists PCH supported throttling register setting for custimization.
Definition: ThermalConfig.h:47
DMI_HW_WIDTH_CONTROL::TS2TW
UINT32 TS2TW
Thermal Sensor 2 Target Width (DmiThermSensWidthx2)
Definition: ThermalConfig.h:95
THERMAL_THROTTLE_LEVELS::Rsvd0
UINT32 Rsvd0
Reserved bytes.
Definition: ThermalConfig.h:70
THERMAL_CONFIG::TTLevels
THERMAL_THROTTLE_LEVELS TTLevels
This field decides the settings of Thermal throttling.
Definition: ThermalConfig.h:153
DMI_HW_WIDTH_CONTROL::TS1TW
UINT32 TS1TW
Thermal Sensor 1 Target Width (DmiThermSensWidthx4)
Definition: ThermalConfig.h:94
PCH_MEMORY_THROTTLING
This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
Definition: ThermalConfig.h:126
THERMAL_THROTTLE_LEVELS::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values.
Definition: ThermalConfig.h:62
THERMAL_CONFIG::PchHotEnable
UINT32 PchHotEnable
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: Disabled,...
Definition: ThermalConfig.h:147
THERMAL_CONFIG::DmiHaAWC
DMI_HW_WIDTH_CONTROL DmiHaAWC
This field decides the settings of DMI throttling.
Definition: ThermalConfig.h:158
THERMAL_THROTTLE_LEVELS::TTState13Enable
UINT32 TTState13Enable
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
Definition: ThermalConfig.h:56
THERMAL_CONFIG
The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.
Definition: ThermalConfig.h:145
DMI_HW_WIDTH_CONTROL::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values
Definition: ThermalConfig.h:91
THERMAL_CONFIG::PchHotLevel
UINT16 PchHotLevel
The recommendation is the same as Cat Trip point.
Definition: ThermalConfig.h:173
TS_GPIO_PIN_SETTING::C0TransmitEnable
UINT32 C0TransmitEnable
GPIO Transmit enable in C0 state, 0:Disabled, 1:Enabled
Definition: ThermalConfig.h:112
DMI_HW_WIDTH_CONTROL::TS3TW
UINT32 TS3TW
Thermal Sensor 3 Target Width (DmiThermSensWidthx1)
Definition: ThermalConfig.h:96
TS_GPIO_PIN_SETTING::PinSelection
UINT32 PinSelection
GPIO Pin assignment selection, 0: default, 1: secondary.
Definition: ThermalConfig.h:113
PCH_MEMORY_THROTTLING::Enable
UINT32 Enable
This will enable PCH memory throttling.
Definition: ThermalConfig.h:132
DMI_HW_WIDTH_CONTROL::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: ThermalConfig.h:97
THERMAL_THROTTLE_LEVELS::T1Level
UINT32 T1Level
Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:49
THERMAL_THROTTLE_LEVELS::PchCrossThrottling
UINT32 PchCrossThrottling
ULT processors support thermal management and cross thermal throttling between the processor package ...
Definition: ThermalConfig.h:69
DMI_HW_WIDTH_CONTROL
This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec de...
Definition: ThermalConfig.h:89
THERMAL_THROTTLE_LEVELS::T2Level
UINT32 T2Level
Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:50
THERMAL_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: ThermalConfig.h:146
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TraceHubConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
Classes | Enumerations
TraceHubConfig.h File Reference

Configurations for TraceHub. More...

#include <ConfigBlock.h>
Include dependency graph for TraceHubConfig.h:

Go to the source code of this file.

Classes

struct | TRACE_HUB_CONFIG
TRACE_HUB_CONFIG block describes TraceHub settings. More...
struct | CPU_TRACE_HUB_PREMEM_CONFIG
CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version. More...
struct | PCH_TRACE_HUB_PREMEM_CONFIG
PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version. More...

Enumerations

enum | TRACE_HUB_ENABLE_MODE
The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation.
enum | TRACE_BUFFER_SIZE
The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size.

Detailed Description

Configurations for TraceHub.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TraceHubConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TraceHubConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
TraceHubConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for TraceHub
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TRACE_HUB_CONFIG_H_
36 #define _TRACE_HUB_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define CPU_TRACE_HUB_PREMEM_CONFIG_REVISION 1
41 #define PCH_TRACE_HUB_PREMEM_CONFIG_REVISION 1
42
43 extern EFI_GUID gPchTraceHubPreMemConfigGuid;
44 extern EFI_GUID gCpuTraceHubPreMemConfigGuid;
45
46 typedef enum {
47 CpuTraceHub,
48 PchTraceHub
49 } TRACE_HUB_DEVICE;
50 ///
51 /// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation
52 ///
53 typedef enum {
54 TraceHubModeDisabled = 0,
55 TraceHubModeTargetDebugger = 1,
56 TraceHubModeHostDebugger = 2,
57 TraceHubModeMax
58 } TRACE_HUB_ENABLE_MODE;
59
60 ///
61 /// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size
62 ///
63 typedef enum {
64 TraceBufferNone,
65 TraceBuffer1M,
66 TraceBuffer8M,
67 TraceBuffer64M,
68 TraceBuffer128M,
69 TraceBuffer256M,
70 TraceBuffer512M,
71 TraceBufferMax
72 } TRACE_BUFFER_SIZE;
73
74 #pragma pack (push,1)
75 ///
76 /// TRACE_HUB_CONFIG block describes TraceHub settings
77 ///
78 typedef struct {
79 /**
80 Trace hub mode. Default is disabled.
81 Target Debugger mode refers to debug tool running on target device itself and it works as a conventional PCI device;
82 Host Debugger mode refers to SUT debugged via probe on host, configured as ACPI device with PCI configuration sapce hidden.
83 <b>0 = Disable</b>; 1 = Target Debugger mode; 2 = Host Debugger mode
84 Refer to TRACE_HUB_ENABLE_MODE
85 **/
86 UINT8 EnableMode;
87 /**
88 Trace hub memory buffer region size policy.
89 The avaliable memory size options are: 0:0MB (none), 1:1MB, <b>2:8MB</b>, 3:64MB, 4:128MB, 5:256MB, 6:512MB.
90 Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is enabled, the total size limits to 256 MB.
91 Refer to TRACE_BUFFER_SIZE
92 **/
93 UINT8 MemReg0Size;
94 UINT8 MemReg1Size;
95 /**
96 AET Trace. AET base address can be set to FW Base either from CPU trace hub or PCH one.
97 AetEnabled must be exclusive, if AetEnabled = 1 for CPU trace hub, must AetEnabled = 0 for PCH one.
98 The default is set to PCH.
99 CPU Trace Hub
100 <b>0 = Disabled</b>; 1 = Enabled
101 PCH Trace Hub
102 0 = Disabled; <b>1 = Enabled</b>
103 **/
104 UINT8 AetEnabled;
105 } TRACE_HUB_CONFIG;
106
107 /**
108 CPU Trace Hub PreMem Configuration
109 Contains Trace Hub settings for CPU side tracing
110 <b>Revision 1</b>: - Initial version.
111 **/
112 typedef struct {
113 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
114 TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config
115 } CPU_TRACE_HUB_PREMEM_CONFIG;
116
117 /**
118 PCH Trace Hub PreMem Configuration
119 Contains Trace Hub settings for PCH side tracing
120 <b>Revision 1</b>: - Initial version.
121 **/
122 typedef struct {
123 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
124 TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config
125 } PCH_TRACE_HUB_PREMEM_CONFIG;
126
127 #pragma pack (pop)
128
129 #endif
TRACE_HUB_CONFIG::AetEnabled
UINT8 AetEnabled
AET Trace.
Definition: TraceHubConfig.h:104
CPU_TRACE_HUB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TraceHubConfig.h:113
ConfigBlock.h
Header file for Config Block Lib implementation.
TRACE_HUB_CONFIG
TRACE_HUB_CONFIG block describes TraceHub settings.
Definition: TraceHubConfig.h:78
TRACE_BUFFER_SIZE
TRACE_BUFFER_SIZE
The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size.
Definition: TraceHubConfig.h:63
TRACE_HUB_CONFIG::EnableMode
UINT8 EnableMode
Trace hub mode.
Definition: TraceHubConfig.h:86
PCH_TRACE_HUB_PREMEM_CONFIG
PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Ini...
Definition: TraceHubConfig.h:122
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TRACE_HUB_ENABLE_MODE
TRACE_HUB_ENABLE_MODE
The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation.
Definition: TraceHubConfig.h:53
CPU_TRACE_HUB_PREMEM_CONFIG::TraceHub
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.
Definition: TraceHubConfig.h:114
PCH_TRACE_HUB_PREMEM_CONFIG::TraceHub
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.
Definition: TraceHubConfig.h:124
TRACE_HUB_CONFIG::MemReg0Size
UINT8 MemReg0Size
Trace hub memory buffer region size policy.
Definition: TraceHubConfig.h:93
CPU_TRACE_HUB_PREMEM_CONFIG
CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Ini...
Definition: TraceHubConfig.h:112
PCH_TRACE_HUB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TraceHubConfig.h:123
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TsnConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
Classes
TsnConfig.h File Reference

TSN Config policy. More...

Go to the source code of this file.

Classes

struct TSN_CONFIG
The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN) More...

Detailed Description

TSN Config policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TsnConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TsnConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
TsnConfig.h
Go to the documentation of this file.
1 /** @file
2 TSN Config policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _TSN_CONFIG_H_
37 #define _TSN_CONFIG_H_
38
39 #define TSN_CONFIG_REVISION 2
40 extern EFI_GUID gTsnConfigGuid;
41
42 #pragma pack (push,1)
43 /**
44 The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)
45
46 <b>Revision 1</b>:
47 - Initial version.
48 <b>Revision 2</b>:
49 - Added MultiVcEnable
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 /**
54 Determines if enable PCH internal TSN, 0: Disable; <b>1: Enable</b>.
55 **/
56 UINT8 Enable;
57 UINT8 TsnLinkSpeed; ///< Refer to "TSN_LINK_SPEED_OPTIONS". Default is <b> TSN_LINK_SPEED_2_5G_34MHZ</b>
58 UINT8 MultiVcEnable; ///< Enable Multi-Vc via Tc to DMA mapping. Deafult is </b> 0:disable</b>
59 UINT8 Rsvd0; ///< Reserved bytes, align to multiple 4.
60 UINT32 TsnMacAddressHigh; ///< MAC Address High bits. Only two lower bytes are used.
61 UINT32 TsnMacAddressLow; ///< MAC Address Low bits
62 } TSN_CONFIG;
63
64 #pragma pack (pop)
65
66 typedef enum {
67 TSN_LINK_SPEED_2_5G_24MHZ = 0,
68 TSN_LINK_SPEED_1G_24MHZ,
69 TSN_LINK_SPEED_2_5G_34MHZ,
70 TSN_LINK_SPEED_1G_34MHZ
71 } TSN_LINK_SPEED_OPTIONS;
72
73 #endif
TSN_CONFIG::TsnMacAddressLow
UINT32 TsnMacAddressLow
MAC Address Low bits.
Definition: TsnConfig.h:61
TSN_CONFIG::TsnMacAddressHigh
UINT32 TsnMacAddressHigh
MAC Address High bits. Only two lower bytes are used.
Definition: TsnConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TSN_CONFIG::Rsvd0
UINT8 Rsvd0
Reserved bytes, align to multiple 4.
Definition: TsnConfig.h:59
TSN_CONFIG::TsnLinkSpeed
UINT8 TsnLinkSpeed
Refer to "TSN_LINK_SPEED_OPTIONS". Default is TSN_LINK_SPEED_2_5G_34MHZ
Definition: TsnConfig.h:57
TSN_CONFIG::MultiVcEnable
UINT8 MultiVcEnable
Enable Multi-Vc via Tc to DMA mapping. Deafult is 0:disable
Definition: TsnConfig.h:58
TSN_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TsnConfig.h:52
TSN_CONFIG::Enable
UINT8 Enable
Determines if enable PCH internal TSN, 0: Disable; 1: Enable.
Definition: TsnConfig.h:56
TSN_CONFIG
The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)
Definition: TsnConfig.h:51
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: UefiBaseType.h File Reference

  • Edk2
  • MdePkg
  • Include
  • Uefi
Classes | Macros | Typedefs
UefiBaseType.h File Reference

Defines data types and constants introduced in UEFI. More...

#include <Base.h>
Include dependency graph for UefiBaseType.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | EFI_TIME
EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second: 0 - 59 Nanosecond: 0 - 999,999,999 TimeZone: -1440 to 1440 or 2047. More...
struct | EFI_MAC_ADDRESS
32-byte buffer containing a network Media Access Control address. More...
union | EFI_IP_ADDRESS
16-byte buffer aligned on a 4-byte boundary. More...

Macros

#define | EFIERR(_a) ENCODE_ERROR(_a)
Define macro to encode the status code.
#define | EFI_SIZE_TO_PAGES(Size) (((Size) >> EFI_PAGE_SHIFT) + (((Size) & EFI_PAGE_MASK) ? 1 : 0))
Macro that converts a size, in bytes, to a number of EFI_PAGESs. More...
#define | EFI_PAGES_TO_SIZE(Pages) ((Pages) << EFI_PAGE_SHIFT)
Macro that converts a number of EFI_PAGEs to a size in bytes. More...
#define | EFI_IMAGE_MACHINE_IA32 0x014C
PE32+ Machine type for IA32 UEFI images.
#define | EFI_IMAGE_MACHINE_IA64 0x0200
PE32+ Machine type for IA64 UEFI images.
#define | EFI_IMAGE_MACHINE_EBC 0x0EBC
PE32+ Machine type for EBC UEFI images.
#define | EFI_IMAGE_MACHINE_X64 0x8664
PE32+ Machine type for X64 UEFI images.
#define | EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images.
#define | EFI_IMAGE_MACHINE_AARCH64 0xAA64
PE32+ Machine type for AARCH64 A64 images.
#define | EFI_IMAGE_MACHINE_RISCV32 0x5032
PE32+ Machine type for RISC-V 32/64/128.
#define | EFI_SUCCESS RETURN_SUCCESS
Enumeration of EFI_STATUS.
#define | EFI_NETWORK_UNREACHABLE EFIERR(100)
ICMP error definitions.
#define | EFI_CONNECTION_FIN EFIERR(104)
Tcp connection status definitions.

Typedefs

typedef GUID | EFI_GUID
128-bit buffer containing a unique identifier value.
typedef RETURN_STATUS | EFI_STATUS
Function return status for EFI API.
typedef VOID * | EFI_HANDLE
A collection of related interfaces.
typedef VOID * | EFI_EVENT
Handle to an event structure.
typedef UINTN | EFI_TPL
Task priority level.
typedef UINT64 | EFI_LBA
Logical block address.
typedef UINT64 | EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
typedef UINT64 | EFI_VIRTUAL_ADDRESS
64-bit virtual memory address.
typedef IPv4_ADDRESS | EFI_IPv4_ADDRESS
4-byte buffer. More...
typedef IPv6_ADDRESS | EFI_IPv6_ADDRESS
16-byte buffer. More...

Detailed Description

Defines data types and constants introduced in UEFI.

Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file UefiBaseType.h.

Macro Definition Documentation

◆ EFI_PAGES_TO_SIZE

#define EFI_PAGES_TO_SIZE ( Pages ) ((Pages) << EFI_PAGE_SHIFT)

Macro that converts a number of EFI_PAGEs to a size in bytes.

Parameters
Pages The number of EFI_PAGES. This parameter is assumed to be type UINTN. Passing in a parameter that is larger than UINTN may produce unexpected results.
Returns
The number of bytes associated with the number of EFI_PAGEs specified by Pages.

Definition at line 212 of file UefiBaseType.h.

◆ EFI_SIZE_TO_PAGES

#define EFI_SIZE_TO_PAGES ( Size ) (((Size) >> EFI_PAGE_SHIFT) + (((Size) & EFI_PAGE_MASK) ? 1 : 0))

Macro that converts a size, in bytes, to a number of EFI_PAGESs.

Parameters
Size A size in bytes. This parameter is assumed to be type UINTN. Passing in a parameter that is larger than UINTN may produce unexpected results.
Returns
The number of EFI_PAGESs associated with the number of bytes specified by Size.

Definition at line 199 of file UefiBaseType.h.

Typedef Documentation

◆ EFI_IPv4_ADDRESS

typedef IPv4_ADDRESS EFI_IPv4_ADDRESS

4-byte buffer.

An IPv4 internet protocol address.

Definition at line 85 of file UefiBaseType.h.

◆ EFI_IPv6_ADDRESS

typedef IPv6_ADDRESS EFI_IPv6_ADDRESS

16-byte buffer.

An IPv6 internet protocol address.

Definition at line 90 of file UefiBaseType.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: UefiBaseType.h Source File

  • Edk2
  • MdePkg
  • Include
  • Uefi
UefiBaseType.h
Go to the documentation of this file.
1 /** @file
2 Defines data types and constants introduced in UEFI.
3
4 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
5 Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
6 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
7
8 SPDX-License-Identifier: BSD-2-Clause-Patent
9
10 **/
11
12 #ifndef __UEFI_BASETYPE_H__
13 #define __UEFI_BASETYPE_H__
14
15 #include <Base.h>
16
17 //
18 // Basic data type definitions introduced in UEFI.
19 //
20
21 ///
22 /// 128-bit buffer containing a unique identifier value.
23 ///
24 typedef GUID EFI_GUID;
25 ///
26 /// Function return status for EFI API.
27 ///
28 typedef RETURN_STATUS EFI_STATUS;
29 ///
30 /// A collection of related interfaces.
31 ///
32 typedef VOID *EFI_HANDLE;
33 ///
34 /// Handle to an event structure.
35 ///
36 typedef VOID *EFI_EVENT;
37 ///
38 /// Task priority level.
39 ///
40 typedef UINTN EFI_TPL;
41 ///
42 /// Logical block address.
43 ///
44 typedef UINT64 EFI_LBA;
45
46 ///
47 /// 64-bit physical memory address.
48 ///
49 typedef UINT64 EFI_PHYSICAL_ADDRESS;
50
51 ///
52 /// 64-bit virtual memory address.
53 ///
54 typedef UINT64 EFI_VIRTUAL_ADDRESS;
55
56 ///
57 /// EFI Time Abstraction:
58 /// Year: 1900 - 9999
59 /// Month: 1 - 12
60 /// Day: 1 - 31
61 /// Hour: 0 - 23
62 /// Minute: 0 - 59
63 /// Second: 0 - 59
64 /// Nanosecond: 0 - 999,999,999
65 /// TimeZone: -1440 to 1440 or 2047
66 ///
67 typedef struct {
68 UINT16 Year;
69 UINT8 Month;
70 UINT8 Day;
71 UINT8 Hour;
72 UINT8 Minute;
73 UINT8 Second;
74 UINT8 Pad1;
75 UINT32 Nanosecond;
76 INT16 TimeZone;
77 UINT8 Daylight;
78 UINT8 Pad2;
79 } EFI_TIME;
80
81
82 ///
83 /// 4-byte buffer. An IPv4 internet protocol address.
84 ///
85 typedef IPv4_ADDRESS EFI_IPv4_ADDRESS;
86
87 ///
88 /// 16-byte buffer. An IPv6 internet protocol address.
89 ///
90 typedef IPv6_ADDRESS EFI_IPv6_ADDRESS;
91
92 ///
93 /// 32-byte buffer containing a network Media Access Control address.
94 ///
95 typedef struct {
96 UINT8 Addr[32];
97 } EFI_MAC_ADDRESS;
98
99 ///
100 /// 16-byte buffer aligned on a 4-byte boundary.
101 /// An IPv4 or IPv6 internet protocol address.
102 ///
103 typedef union {
104 UINT32 Addr[4];
105 EFI_IPv4_ADDRESS v4;
106 EFI_IPv6_ADDRESS v6;
107 } EFI_IP_ADDRESS;
108
109
110 ///
111 /// Enumeration of EFI_STATUS.
112 ///@{
113 #define EFI_SUCCESS RETURN_SUCCESS
114 #define EFI_LOAD_ERROR RETURN_LOAD_ERROR
115 #define EFI_INVALID_PARAMETER RETURN_INVALID_PARAMETER
116 #define EFI_UNSUPPORTED RETURN_UNSUPPORTED
117 #define EFI_BAD_BUFFER_SIZE RETURN_BAD_BUFFER_SIZE
118 #define EFI_BUFFER_TOO_SMALL RETURN_BUFFER_TOO_SMALL
119 #define EFI_NOT_READY RETURN_NOT_READY
120 #define EFI_DEVICE_ERROR RETURN_DEVICE_ERROR
121 #define EFI_WRITE_PROTECTED RETURN_WRITE_PROTECTED
122 #define EFI_OUT_OF_RESOURCES RETURN_OUT_OF_RESOURCES
123 #define EFI_VOLUME_CORRUPTED RETURN_VOLUME_CORRUPTED
124 #define EFI_VOLUME_FULL RETURN_VOLUME_FULL
125 #define EFI_NO_MEDIA RETURN_NO_MEDIA
126 #define EFI_MEDIA_CHANGED RETURN_MEDIA_CHANGED
127 #define EFI_NOT_FOUND RETURN_NOT_FOUND
128 #define EFI_ACCESS_DENIED RETURN_ACCESS_DENIED
129 #define EFI_NO_RESPONSE RETURN_NO_RESPONSE
130 #define EFI_NO_MAPPING RETURN_NO_MAPPING
131 #define EFI_TIMEOUT RETURN_TIMEOUT
132 #define EFI_NOT_STARTED RETURN_NOT_STARTED
133 #define EFI_ALREADY_STARTED RETURN_ALREADY_STARTED
134 #define EFI_ABORTED RETURN_ABORTED
135 #define EFI_ICMP_ERROR RETURN_ICMP_ERROR
136 #define EFI_TFTP_ERROR RETURN_TFTP_ERROR
137 #define EFI_PROTOCOL_ERROR RETURN_PROTOCOL_ERROR
138 #define EFI_INCOMPATIBLE_VERSION RETURN_INCOMPATIBLE_VERSION
139 #define EFI_SECURITY_VIOLATION RETURN_SECURITY_VIOLATION
140 #define EFI_CRC_ERROR RETURN_CRC_ERROR
141 #define EFI_END_OF_MEDIA RETURN_END_OF_MEDIA
142 #define EFI_END_OF_FILE RETURN_END_OF_FILE
143 #define EFI_INVALID_LANGUAGE RETURN_INVALID_LANGUAGE
144 #define EFI_COMPROMISED_DATA RETURN_COMPROMISED_DATA
145 #define EFI_HTTP_ERROR RETURN_HTTP_ERROR
146
147 #define EFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH
148 #define EFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE
149 #define EFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE
150 #define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL
151 #define EFI_WARN_STALE_DATA RETURN_WARN_STALE_DATA
152 #define EFI_WARN_FILE_SYSTEM RETURN_WARN_FILE_SYSTEM
153 ///@}
154
155 ///
156 /// Define macro to encode the status code.
157 ///
158 #define EFIERR(_a) ENCODE_ERROR(_a)
159
160 #define EFI_ERROR(A) RETURN_ERROR(A)
161
162 ///
163 /// ICMP error definitions
164 ///@{
165 #define EFI_NETWORK_UNREACHABLE EFIERR(100)
166 #define EFI_HOST_UNREACHABLE EFIERR(101)
167 #define EFI_PROTOCOL_UNREACHABLE EFIERR(102)
168 #define EFI_PORT_UNREACHABLE EFIERR(103)
169 ///@}
170
171 ///
172 /// Tcp connection status definitions
173 ///@{
174 #define EFI_CONNECTION_FIN EFIERR(104)
175 #define EFI_CONNECTION_RESET EFIERR(105)
176 #define EFI_CONNECTION_REFUSED EFIERR(106)
177 ///@}
178
179 //
180 // The EFI memory allocation functions work in units of EFI_PAGEs that are
181 // 4KB. This should in no way be confused with the page size of the processor.
182 // An EFI_PAGE is just the quanta of memory in EFI.
183 //
184 #define EFI_PAGE_SIZE SIZE_4KB
185 #define EFI_PAGE_MASK 0xFFF
186 #define EFI_PAGE_SHIFT 12
187
188 /**
189 Macro that converts a size, in bytes, to a number of EFI_PAGESs.
190
191 @param Size A size in bytes. This parameter is assumed to be type UINTN.
192 Passing in a parameter that is larger than UINTN may produce
193 unexpected results.
194
195 @return The number of EFI_PAGESs associated with the number of bytes specified
196 by Size.
197
198 **/
199 #define EFI_SIZE_TO_PAGES(Size) (((Size) >> EFI_PAGE_SHIFT) + (((Size) & EFI_PAGE_MASK) ? 1 : 0))
200
201 /**
202 Macro that converts a number of EFI_PAGEs to a size in bytes.
203
204 @param Pages The number of EFI_PAGES. This parameter is assumed to be
205 type UINTN. Passing in a parameter that is larger than
206 UINTN may produce unexpected results.
207
208 @return The number of bytes associated with the number of EFI_PAGEs specified
209 by Pages.
210
211 **/
212 #define EFI_PAGES_TO_SIZE(Pages) ((Pages) << EFI_PAGE_SHIFT)
213
214 ///
215 /// PE32+ Machine type for IA32 UEFI images.
216 ///
217 #define EFI_IMAGE_MACHINE_IA32 0x014C
218
219 ///
220 /// PE32+ Machine type for IA64 UEFI images.
221 ///
222 #define EFI_IMAGE_MACHINE_IA64 0x0200
223
224 ///
225 /// PE32+ Machine type for EBC UEFI images.
226 ///
227 #define EFI_IMAGE_MACHINE_EBC 0x0EBC
228
229 ///
230 /// PE32+ Machine type for X64 UEFI images.
231 ///
232 #define EFI_IMAGE_MACHINE_X64 0x8664
233
234 ///
235 /// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images.
236 ///
237 #define EFI_IMAGE_MACHINE_ARMTHUMB_MIXED 0x01C2
238
239 ///
240 /// PE32+ Machine type for AARCH64 A64 images.
241 ///
242 #define EFI_IMAGE_MACHINE_AARCH64 0xAA64
243
244 ///
245 /// PE32+ Machine type for RISC-V 32/64/128
246 ///
247 #define EFI_IMAGE_MACHINE_RISCV32 0x5032
248 #define EFI_IMAGE_MACHINE_RISCV64 0x5064
249 #define EFI_IMAGE_MACHINE_RISCV128 0x5128
250
251 #if !defined(EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined(EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
252 #if defined (MDE_CPU_IA32)
253
254 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
255 ((Machine) == EFI_IMAGE_MACHINE_IA32)
256
257 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
258
259 #elif defined (MDE_CPU_X64)
260
261 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
262 ((Machine) == EFI_IMAGE_MACHINE_X64)
263
264 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
265
266 #elif defined (MDE_CPU_ARM)
267
268 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
269
270 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
271
272 #elif defined (MDE_CPU_AARCH64)
273
274 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
275 ((Machine) == EFI_IMAGE_MACHINE_AARCH64)
276
277 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
278
279 #elif defined (MDE_CPU_RISCV64)
280 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
281 ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
282
283 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
284
285 #elif defined (MDE_CPU_EBC)
286
287 ///
288 /// This is just to make sure you can cross compile with the EBC compiler.
289 /// It does not make sense to have a PE loader coded in EBC.
290 ///
291 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)
292
293 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
294
295 #else
296 #error Unknown Processor Type
297 #endif
298 #else
299 #if defined (EFI_IMAGE_MACHINE_TYPE_VALUE)
300 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_TYPE_VALUE)
301 #else
302 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) (FALSE)
303 #endif
304 #if defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
305 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
306 #else
307 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
308 #endif
309 #endif
310
311 #endif
EFI_IPv4_ADDRESS
IPv4_ADDRESS EFI_IPv4_ADDRESS
4-byte buffer.
Definition: UefiBaseType.h:85
EFI_VIRTUAL_ADDRESS
UINT64 EFI_VIRTUAL_ADDRESS
64-bit virtual memory address.
Definition: UefiBaseType.h:54
IPv4_ADDRESS
4-byte buffer.
Definition: Base.h:232
EFI_TPL
UINTN EFI_TPL
Task priority level.
Definition: UefiBaseType.h:40
EFI_IPv6_ADDRESS
IPv6_ADDRESS EFI_IPv6_ADDRESS
16-byte buffer.
Definition: UefiBaseType.h:90
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
IPv6_ADDRESS
16-byte buffer.
Definition: Base.h:239
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
Base.h
Root include file for Mde Package Base type modules.
EFI_HANDLE
VOID * EFI_HANDLE
A collection of related interfaces.
Definition: UefiBaseType.h:32
EFI_LBA
UINT64 EFI_LBA
Logical block address.
Definition: UefiBaseType.h:44
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
EFI_IP_ADDRESS
16-byte buffer aligned on a 4-byte boundary.
Definition: UefiBaseType.h:103
EFI_GUID
GUID EFI_GUID
128-bit buffer containing a unique identifier value.
Definition: UefiBaseType.h:24
EFI_EVENT
VOID * EFI_EVENT
Handle to an event structure.
Definition: UefiBaseType.h:36
EFI_MAC_ADDRESS
32-byte buffer containing a network Media Access Control address.
Definition: UefiBaseType.h:95
EFI_TIME
EFI Time Abstraction: Year: 1900 - 9999 Month: 1 - 12 Day: 1 - 31 Hour: 0 - 23 Minute: 0 - 59 Second:...
Definition: UefiBaseType.h:67
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Usb2PhyConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes
Usb2PhyConfig.h File Reference

USB2 PHY configuration policy. More...

#include <UsbConfig.h>
Include dependency graph for Usb2PhyConfig.h:

Go to the source code of this file.

Classes

struct | USB2_PHY_PARAMETERS
This structure configures per USB2 AFE settings. More...
struct | USB2_PHY_CONFIG
This structure holds info on how to tune electrical parameters of USB2 ports based on board layout. More...

Detailed Description

USB2 PHY configuration policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Usb2PhyConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Usb2PhyConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb2PhyConfig.h
Go to the documentation of this file.
1 /** @file
2 USB2 PHY configuration policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _USB2_PHY_CONFIG_H_
36 #define _USB2_PHY_CONFIG_H_
37
38 #include <UsbConfig.h>
39
40 #define USB2_PHY_CONFIG_REVISION 1
41 extern EFI_GUID gUsb2PhyConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 This structure configures per USB2 AFE settings.
47 It allows to setup the port electrical parameters.
48 **/
49 typedef struct {
50 /** Per Port HS Preemphasis Bias (PERPORTPETXISET)
51 000b - 0mV
52 001b - 11.25mV
53 010b - 16.9mV
54 011b - 28.15mV
55 100b - 28.15mV
56 101b - 39.35mV
57 110b - 45mV
58 111b - 56.3mV
59 **/
60 UINT8 Petxiset;
61 /** Per Port HS Transmitter Bias (PERPORTTXISET)
62 000b - 0mV
63 001b - 11.25mV
64 010b - 16.9mV
65 011b - 28.15mV
66 100b - 28.15mV
67 101b - 39.35mV
68 110b - 45mV
69 111b - 56.3mV
70 **/
71 UINT8 Txiset;
72 /**
73 Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
74 00b - Emphasis OFF
75 01b - De-emphasis ON
76 10b - Pre-emphasis ON
77 11b - Pre-emphasis & De-emphasis ON
78 **/
79 UINT8 Predeemp;
80 /**
81 Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
82 1b - half-bit pre-emphasis
83 0b - full-bit pre-emphasis
84 **/
85 UINT8 Pehalfbit;
86 } USB2_PHY_PARAMETERS;
87
88 /**
89 This structure holds info on how to tune electrical parameters of USB2 ports based on board layout
90
91 <b>Revision 1</b>:
92 - Initial version.
93
94 **/
95 typedef struct {
96 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
97 /**
98 This structure configures per USB2 port physical settings.
99 It allows to setup the port location and port length, and configures the port strength accordingly.
100 Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating
101 through Usb2PhySusPgEnable on PCH-LP
102 **/
103 USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS];
104 } USB2_PHY_CONFIG;
105
106 #pragma pack (pop)
107
108 #endif // _USB2_PHY_CONFIG_H_
109
USB2_PHY_PARAMETERS::Pehalfbit
UINT8 Pehalfbit
Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) 1b - half-bit pre-emphasis 0b - full-bit pre-emphasi...
Definition: Usb2PhyConfig.h:85
USB2_PHY_PARAMETERS::Predeemp
UINT8 Predeemp
Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) 00b - Emphasis OFF 01b - De-emphasis ON 10b - Pre...
Definition: Usb2PhyConfig.h:79
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
USB2_PHY_PARAMETERS::Petxiset
UINT8 Petxiset
Per Port HS Preemphasis Bias (PERPORTPETXISET) 000b - 0mV 001b - 11.25mV 010b - 16....
Definition: Usb2PhyConfig.h:60
USB2_PHY_PARAMETERS::Txiset
UINT8 Txiset
Per Port HS Transmitter Bias (PERPORTTXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28....
Definition: Usb2PhyConfig.h:71
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
USB2_PHY_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: Usb2PhyConfig.h:96
USB2_PHY_PARAMETERS
This structure configures per USB2 AFE settings.
Definition: Usb2PhyConfig.h:49
USB2_PHY_CONFIG
This structure holds info on how to tune electrical parameters of USB2 ports based on board layout.
Definition: Usb2PhyConfig.h:95
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Usb3HsioConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes
Usb3HsioConfig.h File Reference

USB3 Mod PHY configuration policy. More...

#include <UsbConfig.h>
Include dependency graph for Usb3HsioConfig.h:

Go to the source code of this file.

Classes

struct | HSIO_PARAMETERS
This structure describes USB3 Port N configuration parameters. More...
struct | USB3_HSIO_CONFIG
Structure for holding USB3 tuning parameters. More...

Detailed Description

USB3 Mod PHY configuration policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Usb3HsioConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Usb3HsioConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb3HsioConfig.h
Go to the documentation of this file.
1 /** @file
2 USB3 Mod PHY configuration policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _USB3_HSIO_CONFIG_H_
37 #define _USB3_HSIO_CONFIG_H_
38
39 #include <UsbConfig.h>
40
41 #define USB3_HSIO_CONFIG_REVISION 2
42 extern EFI_GUID gUsb3HsioConfigGuid;
43
44 #pragma pack (push,1)
45
46 /**
47 This structure describes USB3 Port N configuration parameters
48 **/
49 typedef struct {
50 /**
51 USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
52 HSIO_TX_DWORD8[21:16]
53 <b>Default = 00h</b>
54 **/
55 UINT8 HsioTxDownscaleAmp;
56 /**
57 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
58 HSIO_TX_DWORD5[21:16]
59 <b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
60 **/
61 UINT8 HsioTxDeEmph;
62 /**
63 Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_4_0)
64 HSIO_RX_DWORD25 [20:16]
65 Ex: -1 -- 1_0001. +1: 0_0001
66 <b>Default = 0h</b>
67 **/
68 UINT8 HsioCtrlAdaptOffsetCfg;
69 /**
70 LFPS filter select for n (filter_sel_n_2_0)
71 HSIO_RX_DWORD51 [29:27]
72 0h:1.6ns
73 1h:2.4ns
74 2h:3.2ns
75 3h:4.0ns
76 4h:4.8ns
77 5h:5.6ns
78 6h:6.4ns
79 <b>Default = 0h</b>
80 **/
81 UINT8 HsioFilterSelN;
82 /**
83 LFPS filter select for p (filter_sel_p_2_0)
84 HSIO_RX_DWORD51 [26:24]
85 0h:1.6ns
86 1h:2.4ns
87 2h:3.2ns
88 3h:4.0ns
89 4h:4.8ns
90 5h:5.6ns
91 6h:6.4ns
92 <b>Default = 0h</b>
93 **/
94 UINT8 HsioFilterSelP;
95 /**
96 Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)
97 HSIO_RX_DWORD51 [2:0]
98 000 Prohibited
99 001 45K
100 010 Prohibited
101 011 31K
102 100 36K
103 101 36K
104 110 36K
105 111 36K
106 <b>Default = 3h</b>
107 **/
108 UINT8 HsioOlfpsCfgPullUpDwnRes;
109
110 UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
111 UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
112 UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed Magnatude number added to the CTLE code, <b>0: Disable</b>; 1: Enable.
113 UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS filter select for n, <b>0: Disable</b>; 1: Enable.
114 UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS filter select for p, <b>0: Disable</b>; 1: Enable.
115 UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to olfpscfgpullupdwnres, <b>0: Disable</b>; 1: Enable.
116 /**
117 USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale)
118 HSIO_TX_DWORD9[6:0]
119 <b>Default = 4Ch</b>
120 **/
121 UINT8 HsioTxRate3UniqTran;
122 /**
123 USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale)
124 HSIO_TX_DWORD9[14:8]
125 <b>Default = 4Ch</b>
126 **/
127 UINT8 HsioTxRate2UniqTran;
128 /**
129 USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale)
130 HSIO_TX_DWORD9[22:16]
131 <b>Default = 4Ch</b>
132 **/
133 UINT8 HsioTxRate1UniqTran;
134 /**
135 USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale)
136 HSIO_TX_DWORD9[30:24]
137 <b>Default = 4Ch</b>
138 **/
139 UINT8 HsioTxRate0UniqTran;
140
141 UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, <b>0: Disable</b>; 1: Enable.
142 UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, <b>0: Disable</b>; 1: Enable.
143 UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, <b>0: Disable</b>; 1: Enable.
144 UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, <b>0: Disable</b>; 1: Enable.
145 } HSIO_PARAMETERS;
146
147 /**
148 Structure for holding USB3 tuning parameters
149
150 <b>Revision 1</b>:
151 - Initial version.
152 <b>Revision 2</b>:
153 - USB 3.0 TX Output Unique Transition Bit Scale policies added
154 **/
155 typedef struct {
156 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
157 /**
158 These members describe whether the USB3 Port N of PCH is enabled by platform modules.
159 **/
160 HSIO_PARAMETERS Port[MAX_USB3_PORTS];
161 } USB3_HSIO_CONFIG;
162
163 #pragma pack (pop)
164
165 #endif // _USB3_HSIO_CONFIG_H_
166
HSIO_PARAMETERS::HsioTxRate0UniqTranEnable
UINT8 HsioTxRate0UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:144
USB3_HSIO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: Usb3HsioConfig.h:156
HSIO_PARAMETERS::HsioTxDownscaleAmp
UINT8 HsioTxDownscaleAmp
USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) HSIO_TX_DWORD8[21:16] Default = 00h
Definition: Usb3HsioConfig.h:55
HSIO_PARAMETERS::HsioTxRate3UniqTran
UINT8 HsioTxRate3UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale) HSIO_TX_DWORD9[6:0] D...
Definition: Usb3HsioConfig.h:121
HSIO_PARAMETERS::HsioTxRate2UniqTranEnable
UINT8 HsioTxRate2UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:142
HSIO_PARAMETERS::HsioTxDeEmphEnable
UINT8 HsioTxDeEmphEnable
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:110
HSIO_PARAMETERS::HsioFilterSelNEnable
UINT8 HsioFilterSelNEnable
Enable the write to LFPS filter select for n, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:113
HSIO_PARAMETERS::HsioFilterSelPEnable
UINT8 HsioFilterSelPEnable
Enable the write to LFPS filter select for p, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:114
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
USB3_HSIO_CONFIG
Structure for holding USB3 tuning parameters.
Definition: Usb3HsioConfig.h:155
HSIO_PARAMETERS::HsioTxRate3UniqTranEnable
UINT8 HsioTxRate3UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:141
HSIO_PARAMETERS::HsioTxRate1UniqTran
UINT8 HsioTxRate1UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale) HSIO_TX_DWORD9[22:16]...
Definition: Usb3HsioConfig.h:133
HSIO_PARAMETERS::HsioFilterSelN
UINT8 HsioFilterSelN
LFPS filter select for n (filter_sel_n_2_0) HSIO_RX_DWORD51 [29:27] 0h:1.6ns 1h:2....
Definition: Usb3HsioConfig.h:81
HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfgEnable
UINT8 HsioCtrlAdaptOffsetCfgEnable
Enable the write to Signed Magnatude number added to the CTLE code, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:112
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HSIO_PARAMETERS
This structure describes USB3 Port N configuration parameters.
Definition: Usb3HsioConfig.h:49
HSIO_PARAMETERS::HsioTxRate0UniqTran
UINT8 HsioTxRate0UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale) HSIO_TX_DWORD9[30:24]...
Definition: Usb3HsioConfig.h:139
HSIO_PARAMETERS::HsioOlfpsCfgPullUpDwnRes
UINT8 HsioOlfpsCfgPullUpDwnRes
Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) HSIO_RX_DWORD51 [2:0] 000 Prohibited 001...
Definition: Usb3HsioConfig.h:108
HSIO_PARAMETERS::HsioTxRate1UniqTranEnable
UINT8 HsioTxRate1UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:143
HSIO_PARAMETERS::HsioFilterSelP
UINT8 HsioFilterSelP
LFPS filter select for p (filter_sel_p_2_0) HSIO_RX_DWORD51 [26:24] 0h:1.6ns 1h:2....
Definition: Usb3HsioConfig.h:94
HSIO_PARAMETERS::HsioOlfpsCfgPullUpDwnResEnable
UINT8 HsioOlfpsCfgPullUpDwnResEnable
Enable the write to olfpscfgpullupdwnres, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:115
HSIO_PARAMETERS::HsioTxDownscaleAmpEnable
UINT8 HsioTxDownscaleAmpEnable
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:111
HSIO_PARAMETERS::HsioTxRate2UniqTran
UINT8 HsioTxRate2UniqTran
USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale) HSIO_TX_DWORD9[14:8] D...
Definition: Usb3HsioConfig.h:127
HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfg
UINT8 HsioCtrlAdaptOffsetCfg
Signed Magnatude number added to the CTLE code.
Definition: Usb3HsioConfig.h:68
HSIO_PARAMETERS::HsioTxDeEmph
UINT8 HsioTxDeEmph
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) HSIO_TX_DWORD5[21:16] D...
Definition: Usb3HsioConfig.h:61
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: UsbConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes | Macros
UsbConfig.h File Reference

Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | USB2_PORT_CONFIG
This structure configures per USB2.0 port settings like enabling and overcurrent protection. More...
struct | USB3_PORT_CONFIG
This structure configures per USB3.x port settings like enabling and overcurrent protection. More...
struct | XDCI_CONFIG
The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller. More...
struct | USB_CONFIG
This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field. More...

Macros

#define USB_OC_MAX_PINS 16
Total OC pins number (both physical and virtual)

Detailed Description

Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file UsbConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: UsbConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
UsbConfig.h
Go to the documentation of this file.
1 /** @file
2 Common USB policy shared between PCH and CPU
3 Contains general features settings for xHCI and xDCI
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2017 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _USB_CONFIG_H_
37 #define _USB_CONFIG_H_
38
39 #define USB_CONFIG_REVISION 3
40 extern EFI_GUID gUsbConfigGuid;
41
42 #define MAX_USB2_PORTS 16
43 #define MAX_USB3_PORTS 10
44
45 #pragma pack (push,1)
46
47 typedef UINT8 USB_OVERCURRENT_PIN;
48 #define USB_OC_SKIP 0xFF
49 #define USB_OC_MAX_PINS 16 ///< Total OC pins number (both physical and virtual)
50
51 /**
52 This structure configures per USB2.0 port settings like enabling and overcurrent protection
53 **/
54 typedef struct {
55 /**
56 These members describe the specific over current pin number of USB 2.0 Port N.
57 It is SW's responsibility to ensure that a given port's bit map is set only for
58 one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
59 **/
60 UINT32 OverCurrentPin : 8;
61 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
62 UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
63 UINT32 RsvdBits0 : 22; ///< Reserved bits
64 } USB2_PORT_CONFIG;
65
66 /**
67 This structure configures per USB3.x port settings like enabling and overcurrent protection
68 **/
69 typedef struct {
70 /**
71 These members describe the specific over current pin number of USB 3.x Port N.
72 It is SW's responsibility to ensure that a given port's bit map is set only for
73 one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
74 **/
75 UINT32 OverCurrentPin : 8;
76 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
77 UINT32 RsvdBits0 : 23; ///< Reserved bits
78 } USB3_PORT_CONFIG;
79
80 /**
81 The XDCI_CONFIG block describes the configurations
82 of the xDCI Usb Device controller.
83 **/
84 typedef struct {
85 /**
86 This member describes whether or not the xDCI controller should be enabled.
87 0: Disable; <b>1: Enable</b>.
88 **/
89 UINT32 Enable : 1;
90 UINT32 RsvdBits0 : 31; ///< Reserved bits
91 } XDCI_CONFIG;
92
93
94 /**
95 This member describes the expected configuration of the USB controller,
96 Platform modules may need to refer Setup options, schematic, BIOS specification to update this field.
97 The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring the schematic.
98
99 <b>Revision 1</b>:
100 - Initial version.
101 <b>Revision 2</b>:
102 - Added UaolEnable to control USB Audio Offload Capability.
103 <b>Revision 3</b>:
104 - Add HsiiEnable enable option to control HSII feature
105 **/
106 typedef struct {
107 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
108 /**
109 This policy option when set will make BIOS program Port Disable Override register during PEI phase.
110 When disabled BIOS will not program the PDO during PEI phase and leave PDO register unlocked for later programming.
111 If this is disabled, platform code MUST set it before booting into OS.
112 <b>1: Enable</b>
113 0: Disable
114 **/
115 UINT32 PdoProgramming : 1;
116 /**
117 This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.
118 Disabling this feature will disable overcurrent detection functionality.
119 Overcurrent Pin mapping data is contained in respective port structures (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.
120 By default this Overcurrent functionality should be enabled and disabled only for OBS debug usage.
121 <b>1: Will program USB OC pin mapping in respective xHCI controller registers</b>
122 0: Will clear OC pin mapping allow for OBS usage of OC pins
123 **/
124 UINT32 OverCurrentEnable : 1;
125 /**
126 <b>(Test)</b>
127 If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be
128 consumed by xHCI and OC mapping registers will be locked. OverCurrent mapping data is taken from respective port data
129 structure from OverCurrentPin field.
130 If EnableOverCurrent policy is enabled this also should be enabled, otherwise xHCI won't consume OC mapping data.
131 <b>1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping data</b>
132 0: Do not program OCCFDONE bit making it possible to use OBS debug on OC pins.
133 **/
134 UINT32 XhciOcLock : 1;
135 /**
136 Enabling this feature will allow for overriding LTR values for xHCI controller.
137 Values used for programming will be taken from this config block and BIOS will disregard recommended ones.
138 <b>0: disable - do not override recommended LTR values</b>
139 1: enable - override recommended LTR values
140 **/
141 UINT32 LtrOverrideEnable : 1;
142 /**
143 Enable/disable option for USB Audio Offload feture. Disabling this will disable UAOL capability
144 in xHCI and UAOL ACPI definitions will be hidden.
145 0: disable UAOL
146 <b>1: enable UAOL</b>
147 **/
148 UINT32 UaolEnable : 1;
149 /**
150 Enable HS Interrupt IN Alarm
151 0: disable - Disable HSII
152 <b>1: enable - Enable HSII</b>
153 **/
154 UINT32 HsiiEnable : 1;
155 UINT32 RsvdBits0 : 26; ///< Reserved bits
156 /**
157 High Idle Time Control override value
158 This setting is used only if LtrOverrideEnable is enabled
159 **/
160 UINT32 LtrHighIdleTimeOverride;
161 /**
162 Medium Idle Time Control override value
163 This setting is used only if LtrOverrideEnable is enabled
164 **/
165 UINT32 LtrMediumIdleTimeOverride;
166 /**
167 Low Idle Time Control override value
168 This setting is used only if LtrOverrideEnable is enabled
169 **/
170 UINT32 LtrLowIdleTimeOverride;
171 /**
172 These members describe whether the USB2 Port N of PCH is enabled by platform modules.
173 **/
174 USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];
175 /**
176 These members describe whether the USB3 Port N of PCH is enabled by platform modules.
177 **/
178 USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];
179 /**
180 This member describes whether or not the xDCI controller should be enabled.
181 **/
182 XDCI_CONFIG XdciConfig;
183
184 } USB_CONFIG;
185
186 #pragma pack (pop)
187
188 #endif // _USB_CONFIG_H_
USB3_PORT_CONFIG::Enable
UINT32 Enable
0: Disable; 1: Enable.
Definition: UsbConfig.h:76
USB_CONFIG
This member describes the expected configuration of the USB controller, Platform modules may need to ...
Definition: UsbConfig.h:106
USB2_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:63
USB_CONFIG::XhciOcLock
UINT32 XhciOcLock
(Test) If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC m...
Definition: UsbConfig.h:134
USB_CONFIG::UaolEnable
UINT32 UaolEnable
Enable/disable option for USB Audio Offload feture.
Definition: UsbConfig.h:148
USB2_PORT_CONFIG::Enable
UINT32 Enable
0: Disable; 1: Enable.
Definition: UsbConfig.h:61
USB_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:155
XDCI_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:90
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
USB3_PORT_CONFIG
This structure configures per USB3.x port settings like enabling and overcurrent protection.
Definition: UsbConfig.h:69
USB_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: UsbConfig.h:107
USB_CONFIG::XdciConfig
XDCI_CONFIG XdciConfig
This member describes whether or not the xDCI controller should be enabled.
Definition: UsbConfig.h:182
USB_CONFIG::LtrHighIdleTimeOverride
UINT32 LtrHighIdleTimeOverride
High Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
Definition: UsbConfig.h:160
USB_CONFIG::LtrMediumIdleTimeOverride
UINT32 LtrMediumIdleTimeOverride
Medium Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
Definition: UsbConfig.h:165
XDCI_CONFIG::Enable
UINT32 Enable
This member describes whether or not the xDCI controller should be enabled.
Definition: UsbConfig.h:89
USB_CONFIG::LtrOverrideEnable
UINT32 LtrOverrideEnable
Enabling this feature will allow for overriding LTR values for xHCI controller.
Definition: UsbConfig.h:141
USB_CONFIG::LtrLowIdleTimeOverride
UINT32 LtrLowIdleTimeOverride
Low Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
Definition: UsbConfig.h:170
XDCI_CONFIG
The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller.
Definition: UsbConfig.h:84
USB2_PORT_CONFIG::PortResetMessageEnable
UINT32 PortResetMessageEnable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
Definition: UsbConfig.h:62
USB_CONFIG::OverCurrentEnable
UINT32 OverCurrentEnable
This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.
Definition: UsbConfig.h:124
USB2_PORT_CONFIG::OverCurrentPin
UINT32 OverCurrentPin
These members describe the specific over current pin number of USB 2.0 Port N.
Definition: UsbConfig.h:60
USB_CONFIG::PdoProgramming
UINT32 PdoProgramming
This policy option when set will make BIOS program Port Disable Override register during PEI phase.
Definition: UsbConfig.h:115
USB3_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:77
USB3_PORT_CONFIG::OverCurrentPin
UINT32 OverCurrentPin
These members describe the specific over current pin number of USB 3.x Port N.
Definition: UsbConfig.h:75
USB_CONFIG::HsiiEnable
UINT32 HsiiEnable
Enable HS Interrupt IN Alarm 0: disable - Disable HSII 1: enable - Enable HSII
Definition: UsbConfig.h:154
USB2_PORT_CONFIG
This structure configures per USB2.0 port settings like enabling and overcurrent protection.
Definition: UsbConfig.h:54
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VmdPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
Classes
VmdPeiConfig.h File Reference

VMD PEI policy. More...

#include <ConfigBlock.h>
#include <Library/VmdInfoLib.h>
Include dependency graph for VmdPeiConfig.h:

Go to the source code of this file.

Classes

struct VMD_PEI_CONFIG
This configuration block is to configure VMD related variables used in PostMem PEI. More...

Detailed Description

VMD PEI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VmdPeiConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VmdPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
VmdPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 VMD PEI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _VMD_PEI_CONFIG_H_
36 #define _VMD_PEI_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <Library/VmdInfoLib.h>
40
41 #define VMD_PEI_CONFIG_REVISION 4
42
43 #pragma pack (push,1)
44
45
46 typedef struct {
47 UINT8 RpBus;
48 UINT8 RpDevice;
49 UINT8 RpFunction;
50 UINT8 RpEnable;
51 } RP_BDF_DATA;
52
53 /**
54 This configuration block is to configure VMD related variables used in PostMem PEI.
55 If VMD Device is not supported, all policies can be ignored.
56 <b>Revision 1</b>:
57 - Initial version.
58 <b>Revision 2</b>:
59 - Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
60 - Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details.
61 (Added B/D/F fields along with Port Enable for up to max 31 devices).
62 <b>Revision 3</b>:
63 Added policy to get the Bar values from platform PCD.
64 <b>Revision 4</b>: Added VmdGlobalMapping to map all the storage devices under VMD
65 **/
66
67 typedef struct {
68 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
69 UINT8 VmdEnable; ///< Offset 28 This field used to enable VMD controller 1=Enable <b>0=Disable(default)</b>
70 UINT8 VmdPortAEnable; /// Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
71 UINT8 VmdPortBEnable; /// Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
72 UINT8 VmdPortCEnable; /// Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
73 UINT8 VmdPortDEnable; /// Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
74 UINT8 VmdCfgBarSize; ///< Offset 33 This is used to set the VMD Config Bar Size. <b>25(32MB)</b>
75 UINT8 VmdCfgBarAttr; ///< Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, <b>2: VMD_64BIT_NONPREFETCH(Default)</b>
76 UINT8 VmdMemBarSize1; ///< Offset 35 This is used to set the VMD Mem Bar1 size. <b>25 (32MB)</b>.
77 UINT8 VmdMemBar1Attr; ///< Offset 36 This is used to set VMD Mem Bar1 Attributes <b>0: VMD_32BIT_NONPREFETCH(Default) </b> 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
78 UINT8 VmdMemBarSize2; ///< Offset 37 This is used to set the VMD Mem Bar2 size. <b>20(1MB)</b>.
79 UINT8 VmdMemBar2Attr; ///< Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH <b>1: VMD_64BIT_NONPREFETCH(Default)</b>, 2: VMD_64BIT_PREFETCH
80 UINT8 VmdGlobalMapping; ///< Offset 39 This field used to enable Global Mapping 1=Enable <b>0=Disable(default)</b>
81 RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable <b>0=Disable (default)</b>
82 VOID *VmdVariablePtr; /// This config block will be updated as per the EFI variable.
83 UINT32 VmdCfgBarBase; /// Temp Address VMD CFG BAR Default is <b>0xA0000000</b>
84 UINT32 VmdMemBar1Base; /// Temp Address VMD CFG BAR Default is <b>0xA2000000</b>
85 UINT32 VmdMemBar2Base; /// Temp Address VMD CFG BAR Default is <b>0xA4000000</b>
86 } VMD_PEI_CONFIG;
87
88 #pragma pack (pop)
89
90 #endif /* _VMD_PEI_PREMEM_CONFIG_H_ */
VMD_PEI_CONFIG::VmdMemBar1Base
UINT32 VmdMemBar1Base
Temp Address VMD CFG BAR Default is 0xA0000000
Definition: VmdPeiConfig.h:84
VMD_PEI_CONFIG::VmdMemBarSize2
UINT8 VmdMemBarSize2
Offset 37 This is used to set the VMD Mem Bar2 size. 20(1MB).
Definition: VmdPeiConfig.h:78
ConfigBlock.h
Header file for Config Block Lib implementation.
VMD_PEI_CONFIG::VmdPortCEnable
UINT8 VmdPortCEnable
Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:72
VMD_PEI_CONFIG::VmdCfgBarAttr
UINT8 VmdCfgBarAttr
Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFET...
Definition: VmdPeiConfig.h:75
VMD_PEI_CONFIG::VmdMemBar1Attr
UINT8 VmdMemBar1Attr
Offset 36 This is used to set VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default) 1: VMD_64BIT...
Definition: VmdPeiConfig.h:77
VMD_PEI_CONFIG::VmdPortDEnable
UINT8 VmdPortDEnable
Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:73
VOID
#define VOID
Undeclared type.
Definition: Base.h:278
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
VMD_PEI_CONFIG::VmdEnable
UINT8 VmdEnable
Offset 28 This field used to enable VMD controller 1=Enable 0=Disable(default)
Definition: VmdPeiConfig.h:69
VMD_PEI_CONFIG::VmdGlobalMapping
UINT8 VmdGlobalMapping
Offset 39 This field used to enable Global Mapping 1=Enable 0=Disable(default)
Definition: VmdPeiConfig.h:80
VMD_PEI_CONFIG::VmdCfgBarBase
UINT32 VmdCfgBarBase
This config block will be updated as per the EFI variable.
Definition: VmdPeiConfig.h:83
VMD_PEI_CONFIG::VmdPortBEnable
UINT8 VmdPortBEnable
Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:71
VMD_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: VmdPeiConfig.h:68
VMD_PEI_CONFIG
This configuration block is to configure VMD related variables used in PostMem PEI.
Definition: VmdPeiConfig.h:67
VMD_PEI_CONFIG::VmdMemBarSize1
UINT8 VmdMemBarSize1
Offset 35 This is used to set the VMD Mem Bar1 size. 25 (32MB).
Definition: VmdPeiConfig.h:76
VMD_PEI_CONFIG::VmdMemBar2Attr
UINT8 VmdMemBar2Attr
Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH 1: VMD_64BIT_NONPREFET...
Definition: VmdPeiConfig.h:79
VMD_PEI_CONFIG::VmdMemBar2Base
UINT32 VmdMemBar2Base
Temp Address VMD CFG BAR Default is 0xA2000000
Definition: VmdPeiConfig.h:85
VMD_PEI_CONFIG::VmdCfgBarSize
UINT8 VmdCfgBarSize
Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:74
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VtdConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
Classes | Typedefs
VtdConfig.h File Reference

VT-d policy definitions. More...

#include <Library/VtdInfoLib.h>
Include dependency graph for VtdConfig.h:

Go to the source code of this file.

Classes

struct | VTD_CONFIG
The data elements should be initialized by a Platform Module. More...
struct | VTD_DXE_CONFIG
The data structure is for VT-d driver initialization in DXE
Revision 1: More...

Typedefs

typedef EFI_STATUS(* VTD_ENABLE_DMA_BUFFER) (IN VTD_ENGINE_INDEX VtdEngineIndex)
Enable DMA buffer in VTd. More...

Detailed Description

VT-d policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VtdConfig.h.

Typedef Documentation

◆ VTD_ENABLE_DMA_BUFFER

typedef EFI_STATUS( * VTD_ENABLE_DMA_BUFFER) (IN VTD_ENGINE_INDEX VtdEngineIndex)

Enable DMA buffer in VTd.

Parameters
[in] VtdEngineIndex VTd engine index.
Return values
EFI_SUCCESS | Enable successfully.
EFI_INVALID_PARAMETER | Input parameters are invalid.
EFI_UNSUPPORTED | VTd base is zero.
EFI_OUT_OF_RESOURCES | There is no additional space in the PPI database.

Definition at line 59 of file VtdConfig.h.

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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VtdConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
VtdConfig.h
Go to the documentation of this file.
1 /** @file
2 VT-d policy definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _VTD_CONFIG_H_
36 #define _VTD_CONFIG_H_
37
38 #include <Library/VtdInfoLib.h>
39 #pragma pack(push, 1)
40
41 #define VTD_CONFIG_REVISION 2
42 #define VTD_DXE_CONFIG_REVISION 3
43
44 //
45 // Forward declaration for the VTd Enable DMA Buffer PPI.
46 //
47
48 /**
49 Enable DMA buffer in VTd
50
51 @param[in] VtdEngineIndex VTd engine index.
52
53 @retval EFI_SUCCESS Enable successfully.
54 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
55 @retval EFI_UNSUPPORTED VTd base is zero.
56 @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
57 **/
58 typedef
59 EFI_STATUS
60 (EFIAPI *VTD_ENABLE_DMA_BUFFER) (
61 IN VTD_ENGINE_INDEX VtdEngineIndex
62 );
63
64 /**
65 The data elements should be initialized by a Platform Module.
66 The data structure is for VT-d driver initialization\n
67 <b>Revision 1</b>:
68 - Initial version.
69 <b>Revision 2</b>:
70 - Added field EnableDmaBuffer.
71 **/
72 typedef struct {
73 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
74 /**
75 Offset 28:
76 VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.
77 This policy is for debug purpose only.
78 If VT-D is not supported, all other policies in this config block will be ignored.
79 <b>0 = To use Vt-d</b>;
80 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.
81 **/
82 UINT8 VtdDisable;
83 UINT8 X2ApicOptOut; ///< Offset 29: This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and <b>0=Disable/Clear</b>
84 UINT8 DmaControlGuarantee; ///< Offset 30: This field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1=Enable/Set and <b>0=Disable/Clear</b>
85 UINT8 VtdIgdEnable; ///< Offset 31: This field is used to enable the VtdIgdEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
86 UINT8 VtdIpuEnable; ///< Offset 32: This field is used to enable the VtdIpuEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
87 UINT8 VtdIopEnable; ///< Offset 33: This field is used to enable the VtdIopEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
88 UINT8 VtdItbtEnable; /// Deprecate
89 UINT8 PreBootDmaMask; ///< Offset 35: Convey PcdVTdPolicyPropertyMask value from EDK2 IntelSiliconPkg
90 UINT32 BaseAddress[VTD_ENGINE_NUMBER]; ///< Offset 36: This field is used to describe the base addresses for VT-d function
91 UINT32 DmaBufferSize; ///< Offset 48: Protect Memory Region (PMR) DMA buffer size
92 UINT32 Reserved; ///< Offset 52: Reserved
93 EFI_PHYSICAL_ADDRESS EnableDmaBuffer; ///< Offset 56: Pointer to EnableDmaBuffer function. Platform code provides an interface to enable DMA buffer.
94 ///< VTD_ENABLE_DMA_BUFFER is a prototype for that interface.
95 } VTD_CONFIG;
96
97 /**
98 The data structure is for VT-d driver initialization in DXE\n
99 <b>Revision 1</b>:
100 - Initial version.
101 <b>Revision 2</b>:
102 - Added TE Disable for Igd.
103 <b>Revision 3</b>:
104 - Removed TE Disable for Igd.
105 **/
106 typedef struct {
107 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
108 UINT8 Rsvd[4];
109 } VTD_DXE_CONFIG;
110 #pragma pack(pop)
111
112 #endif // _VTD_CONFIG_H_
VTD_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: VtdConfig.h:73
VTD_DXE_CONFIG
The data structure is for VT-d driver initialization in DXE Revision 1:
Definition: VtdConfig.h:106
IN
#define IN
Datum is passed to the function.
Definition: Base.h:288
VTD_CONFIG::DmaBufferSize
UINT32 DmaBufferSize
Offset 48: Protect Memory Region (PMR) DMA buffer size.
Definition: VtdConfig.h:91
VTD_CONFIG::Reserved
UINT32 Reserved
Offset 52: Reserved.
Definition: VtdConfig.h:92
VTD_CONFIG::VtdDisable
UINT8 VtdDisable
Offset 28: VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.
Definition: VtdConfig.h:82
VTD_ENABLE_DMA_BUFFER
EFI_STATUS(* VTD_ENABLE_DMA_BUFFER)(IN VTD_ENGINE_INDEX VtdEngineIndex)
Enable DMA buffer in VTd.
Definition: VtdConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
VTD_CONFIG
The data elements should be initialized by a Platform Module.
Definition: VtdConfig.h:72
VTD_CONFIG::DmaControlGuarantee
UINT8 DmaControlGuarantee
Offset 30: This field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table....
Definition: VtdConfig.h:84
EFI_PHYSICAL_ADDRESS
UINT64 EFI_PHYSICAL_ADDRESS
64-bit physical memory address.
Definition: UefiBaseType.h:49
VTD_CONFIG::X2ApicOptOut
UINT8 X2ApicOptOut
Offset 29: This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and 0=...
Definition: VtdConfig.h:83
EFI_STATUS
RETURN_STATUS EFI_STATUS
Function return status for EFI API.
Definition: UefiBaseType.h:28
VTD_CONFIG::VtdIopEnable
UINT8 VtdIopEnable
Offset 33: This field is used to enable the VtdIopEnable Policy. 1=Enable/Set and 0=Disable/Clear
Definition: VtdConfig.h:87
VTD_CONFIG::VtdIgdEnable
UINT8 VtdIgdEnable
Offset 31: This field is used to enable the VtdIgdEnable Policy. 1=Enable/Set and 0=Disable/Clear
Definition: VtdConfig.h:85
VTD_CONFIG::VtdIpuEnable
UINT8 VtdIpuEnable
Offset 32: This field is used to enable the VtdIpuEnable Policy. 1=Enable/Set and 0=Disable/Clear
Definition: VtdConfig.h:86
VTD_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: VtdConfig.h:107
VTD_CONFIG::PreBootDmaMask
UINT8 PreBootDmaMask
Deprecate.
Definition: VtdConfig.h:89
VTD_CONFIG::EnableDmaBuffer
EFI_PHYSICAL_ADDRESS EnableDmaBuffer
Offset 56: Pointer to EnableDmaBuffer function.
Definition: VtdConfig.h:93
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: WatchDogConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
Classes
WatchDogConfig.h File Reference

WatchDog policy. More...

Go to the source code of this file.

Classes

struct PCH_WDT_PREMEM_CONFIG
This policy clears status bits and disable watchdog, then lock the WDT registers. More...

Detailed Description

WatchDog policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file WatchDogConfig.h.

Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: WatchDogConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
WatchDogConfig.h
Go to the documentation of this file.
1 /** @file
2 WatchDog policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _WATCH_DOG_CONFIG_H_
36 #define _WATCH_DOG_CONFIG_H_
37
38 #define PCH_WDT_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gWatchDogPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This policy clears status bits and disable watchdog, then lock the
45 WDT registers.
46 while WDT is designed to be disabled and locked by Policy,
47 bios should not enable WDT by WDT PPI. In such case, bios shows the
48 warning message but not disable and lock WDT register to make sure
49 WDT event trigger correctly.
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
54 UINT32 RsvdBits : 31;
55 } PCH_WDT_PREMEM_CONFIG;
56
57 #pragma pack (pop)
58
59 #endif // _WATCH_DOG_CONFIG_H_
PCH_WDT_PREMEM_CONFIG::DisableAndLock
UINT32 DisableAndLock
(Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable.
Definition: WatchDogConfig.h:53
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_WDT_PREMEM_CONFIG
This policy clears status bits and disable watchdog, then lock the WDT registers.
Definition: WatchDogConfig.h:51
GUID
128 bit buffer containing a unique identifier value.
Definition: Base.h:222
PCH_WDT_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: WatchDogConfig.h:52
Generated on Wed Jan 5 2022 01:25:54 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- _ -

  • _BASE_INT_SIZE_OF : Base.h
  • _CONCATENATE : Base.h
  • _INT_SIZE_OF : Base.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- a -

  • ABS : Base.h
  • AddConfigBlock() : ConfigBlockLib.h
  • ALIGN_POINTER : Base.h
  • ALIGN_VALUE : Base.h
  • ALIGN_VARIABLE : Base.h
  • AMT_ERROR_MSG_ID : AmtConfig.h
  • AMT_REPORT_ERROR : AmtConfig.h
  • ANALYZER_NORETURN : Base.h
  • ANALYZER_UNREACHABLE : Base.h
  • ARRAY_SIZE : Base.h
  • ASM_PFX : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- b -

  • B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK : GpioConfig.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • BASE_ARG : Base.h
  • BASE_CR : Base.h
  • BASE_LIST : Base.h
  • BIOS_GUARD_CONFIG_REVISION : BiosGuardConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- c -

  • C_STATE_TIME_UNIT : CpuPowerMgmtTestConfig.h
  • CNVI_MODE : CnviConfig.h
  • CONFIG_BLOCK : ConfigBlock.h
  • CONFIG_BLOCK_HEADER : ConfigBlock.h
  • CONFIG_BLOCK_TABLE_HEADER : ConfigBlock.h
  • CONST : Base.h
  • CPU_PCIE_ASPM_CONTROL : CpuPcieConfig.h
  • CPU_PCIE_CONFIG_REVISION : CpuPcieConfig.h
  • CPU_PCIE_EQ_METHOD : CpuPcieConfig.h
  • CPU_PCIE_L1SUBSTATES_CONTROL : CpuPcieConfig.h
  • CpuPcieEqDefault : CpuPcieConfig.h
  • CpuPcieEqHardware : CpuPcieConfig.h
  • CpuPcieEqStaticCoeff : CpuPcieConfig.h
  • CreateConfigBlockTable() : ConfigBlockLib.h
  • CUSTOM_POWER_UNIT : CpuPowerMgmtTestConfig.h
  • CUSTOM_PROFILE : MemoryConfig.h
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AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

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- d -

  • DEFAULT_SPD : MemoryConfig.h
  • DMI_ASPM : CpuDmiPreMemConfig.h
  • DXE_ERROR : PiMultiPhase.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- e -

  • EC_COMMAND_TYPE : BiosGuardConfig.h
  • EFI_AP_PROCEDURE : PiMultiPhase.h
  • EFI_AP_PROCEDURE2 : PiMultiPhase.h
  • EFI_AUTH_STATUS_PLATFORM_OVERRIDE : PiMultiPhase.h
  • EFI_CONNECTION_FIN : UefiBaseType.h
  • EFI_EVENT : UefiBaseType.h
  • EFI_GUID : UefiBaseType.h
  • EFI_HANDLE : UefiBaseType.h
  • EFI_HOB_HANDOFF_TABLE_VERSION : PiHob.h
  • EFI_IMAGE_MACHINE_AARCH64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_ARMTHUMB_MIXED : UefiBaseType.h
  • EFI_IMAGE_MACHINE_EBC : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_RISCV32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_X64 : UefiBaseType.h
  • EFI_INTERRUPT_PENDING : PiMultiPhase.h
  • EFI_IPv4_ADDRESS : UefiBaseType.h
  • EFI_IPv6_ADDRESS : UefiBaseType.h
  • EFI_LBA : UefiBaseType.h
  • EFI_MM_RESERVED_MMRAM_REGION : PiMultiPhase.h
  • EFI_MMRAM_OPEN : PiMultiPhase.h
  • EFI_NETWORK_UNREACHABLE : UefiBaseType.h
  • EFI_NOT_AVAILABLE_YET : PiMultiPhase.h
  • EFI_PAGES_TO_SIZE : UefiBaseType.h
  • EFI_PEI_MP_SERVICES_ENABLEDISABLEAP : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_ALL_APS : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_THIS_AP : MpServices.h
  • EFI_PEI_MP_SERVICES_SWITCH_BSP : MpServices.h
  • EFI_PEI_MP_SERVICES_WHOAMI : MpServices.h
  • EFI_PHYSICAL_ADDRESS : UefiBaseType.h
  • EFI_REQUEST_UNLOAD_IMAGE : PiMultiPhase.h
  • EFI_RESOURCE_ATTRIBUTE_TYPE : PiHob.h
  • EFI_RESOURCE_TYPE : PiHob.h
  • EFI_SIZE_TO_PAGES : UefiBaseType.h
  • EFI_STATUS : UefiBaseType.h
  • EFI_SUCCESS : UefiBaseType.h
  • EFI_TPL : UefiBaseType.h
  • EFI_VIRTUAL_ADDRESS : UefiBaseType.h
  • EFIERR : UefiBaseType.h
  • ENCODE_ERROR : Base.h
  • ENCODE_WARNING : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- f -

  • FALSE : Base.h
  • FIVR_RAIL_SX_STATE : FivrConfig.h
  • FSP_ERROR_INFO_HOB_GUID : FspErrorInfo.h
  • FSPM_ARCH_CONFIG_GUID : FspmArchConfigPpi.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- g -

  • gBiosGuardConfigGuid : BiosGuardConfig.h
  • GetConfigBlock() : ConfigBlockLib.h
  • GLOBAL_REMOVE_IF_UNREFERENCED : Base.h
  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_GROUP : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • GPIO_SUPPORT : HybridGraphicsConfig.h
  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioNoTolerance1v8 : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateLock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDeep : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResetNormal : GpioConfig.h
  • GpioResetPwrGood : GpioConfig.h
  • GpioResetResume : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h
  • GpioTolerance1v8 : GpioConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- h -

  • HDAUDIO_VERB_TABLE_INIT : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_VIDDID : HdAudioConfig.h
  • HidOverSpi : ThcConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- i -

  • IN : Base.h
  • ITBT_GENERIC_CONFIG : PeiITbtGenericStructure.h
  • ITBT_ROOTPORT_CONFIG : PeiITbtGenericStructure.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- l -

  • LIST_ENTRY : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- m -

  • MAX : Base.h
  • MAX_CUSTOM_CTDP_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_CUSTOM_RATIO_TABLE_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_INT8 : Base.h
  • MAX_NUM_VRS : CpuPowerMgmtVrConfig.h
  • MAX_PKG_C_STATE : CpuPowerMgmtTestConfig.h
  • MEM_CFG_MAX_CONTROLLERS : MemoryConfig.h
  • MIN : Base.h
  • MIN_INT8 : Base.h
  • MRC_MAX_RCOMP_TARGETS : MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- n -

  • NORETURN : Base.h
  • NULL : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- o -

  • OFFSET_OF : Base.h
  • OPTIONAL : Base.h
  • OUT : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- p -

  • PcdFspAreaBaseAddress : FspFixedPcds.h
  • PcdFspImageIdString : FspFixedPcds.h
  • PcdFspReservedBufferSize : FspFixedPcds.h
  • PcdGlobalDataPointerAddress : FspFixedPcds.h
  • PcdSiliconInitVersionBuild : FspFixedPcds.h
  • PcdSiliconInitVersionMajor : FspFixedPcds.h
  • PcdSiliconInitVersionMinor : FspFixedPcds.h
  • PcdSiliconInitVersionRevision : FspFixedPcds.h
  • PcdTemporaryRamBase : FspFixedPcds.h
  • PcdTemporaryRamSize : FspFixedPcds.h
  • PCH_FIVR_CONFIG_REVISION : FivrConfig.h
  • PCH_INT_PIN : InterruptConfig.h
  • PCH_MAX_DEVICE_INTERRUPT_CONFIG : InterruptConfig.h
  • PCH_MAX_ITSS_IPC_REGS : InterruptConfig.h
  • PCH_MAX_ITSS_IRQ_NUM : InterruptConfig.h
  • PCH_MAX_PXRC_CONFIG : InterruptConfig.h
  • PCH_PCIE_ASPM_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_CLOCK_USAGE : PchPcieRpConfig.h
  • PCH_PCIE_L1SUBSTATES_CONTROL : PchPcieRpConfig.h
  • PCH_RESERVED_PAGE_ROUTE : PchGeneralConfig.h
  • PCH_SLP_S4_MIN_ASSERT : PmConfig.h
  • PchClockUsageCpuPcie0 : PchPcieRpConfig.h
  • PchClockUsageUnspecified : PchPcieRpConfig.h
  • PchNoInt : InterruptConfig.h
  • PchReservedPageToLpc : PchGeneralConfig.h
  • PchReservedPageToPcie : PchGeneralConfig.h
  • PchSlpS4PchTime : PmConfig.h
  • PCIE_FORM_FACTOR : PcieConfig.h
  • PCIE_LINK_EQ_METHOD : PcieConfig.h
  • PCIE_LINK_EQ_MODE : PcieConfig.h
  • PcieLinkEqCoefficientMode : PcieConfig.h
  • PcieLinkEqPresetMode : PcieConfig.h
  • PcieLinkFixedEq : PcieConfig.h
  • PcieLinkHardwareEq : PcieConfig.h
  • PEI_ITBT_CONFIG : PeiITbtConfig.h
  • PEI_MR_SMRAM_ABSEG_MASK : MemoryConfig.h
  • PEI_POLICY_INIT : PeiSiDefaultPolicy.h
  • PEI_PREMEM_POLICY_INIT : PeiPreMemSiDefaultPolicy.h
  • PI_ENCODE_ERROR : PiMultiPhase.h
  • PI_ENCODE_WARNING : PiMultiPhase.h
  • PLATFORM_SEND_EC_COMMAND : BiosGuardConfig.h
  • PowerUnit125MilliWatts : CpuPowerMgmtTestConfig.h
  • PowerUnitWatts : CpuPowerMgmtTestConfig.h
  • PPM_CUSTOM_CTDP_TABLE : CpuPowerMgmtCustomConfig.h
  • PPM_IRM_SETTING : CpuPowerMgmtTestConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- r -

  • RETURN_ABORTED : Base.h
  • RETURN_ACCESS_DENIED : Base.h
  • RETURN_ADDRESS : Base.h
  • RETURN_ALREADY_STARTED : Base.h
  • RETURN_BAD_BUFFER_SIZE : Base.h
  • RETURN_BUFFER_TOO_SMALL : Base.h
  • RETURN_COMPROMISED_DATA : Base.h
  • RETURN_CRC_ERROR : Base.h
  • RETURN_DEVICE_ERROR : Base.h
  • RETURN_END_OF_FILE : Base.h
  • RETURN_END_OF_MEDIA : Base.h
  • RETURN_ERROR : Base.h
  • RETURN_HTTP_ERROR : Base.h
  • RETURN_ICMP_ERROR : Base.h
  • RETURN_INCOMPATIBLE_VERSION : Base.h
  • RETURN_INVALID_LANGUAGE : Base.h
  • RETURN_INVALID_PARAMETER : Base.h
  • RETURN_LOAD_ERROR : Base.h
  • RETURN_MEDIA_CHANGED : Base.h
  • RETURN_NO_MAPPING : Base.h
  • RETURN_NO_MEDIA : Base.h
  • RETURN_NO_RESPONSE : Base.h
  • RETURN_NOT_FOUND : Base.h
  • RETURN_NOT_READY : Base.h
  • RETURN_NOT_STARTED : Base.h
  • RETURN_OUT_OF_RESOURCES : Base.h
  • RETURN_PROTOCOL_ERROR : Base.h
  • RETURN_SECURITY_VIOLATION : Base.h
  • RETURN_SUCCESS : Base.h
  • RETURN_TFTP_ERROR : Base.h
  • RETURN_TIMEOUT : Base.h
  • RETURN_UNSUPPORTED : Base.h
  • RETURN_VOLUME_CORRUPTED : Base.h
  • RETURN_VOLUME_FULL : Base.h
  • RETURN_WARN_BUFFER_TOO_SMALL : Base.h
  • RETURN_WARN_DELETE_FAILURE : Base.h
  • RETURN_WARN_FILE_SYSTEM : Base.h
  • RETURN_WARN_STALE_DATA : Base.h
  • RETURN_WARN_UNKNOWN_GLYPH : Base.h
  • RETURN_WARN_WRITE_FAILURE : Base.h
  • RETURN_WRITE_PROTECTED : Base.h
  • RETURNS_TWICE : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- s -

  • SA_CHANGE_MARGIN : MemoryConfig.h
  • SA_CHANNEL_EXIST : MemoryConfig.h
  • SA_CHECKPOINT : MemoryConfig.h
  • SA_CPU_MAILBOX_READ : MemoryConfig.h
  • SA_CPU_MAILBOX_WRITE : MemoryConfig.h
  • SA_DEBUG_HOOK : MemoryConfig.h
  • SA_DEBUG_PRINT : MemoryConfig.h
  • SA_DELAY_NS : MemoryConfig.h
  • SA_DIV_U64_U64 : MemoryConfig.h
  • SA_GET_CPU_TIME : MemoryConfig.h
  • SA_GET_MEMORY_VDD : MemoryConfig.h
  • SA_GET_PCI_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_PCIE_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_RANDOM_NUMBER : MemoryConfig.h
  • SA_GET_RTC_CMOS : MemoryConfig.h
  • SA_GET_RTC_TIME : MemoryConfig.h
  • SA_GET_SPD_DATA : MemoryConfig.h
  • SA_IO_READ_16 : MemoryConfig.h
  • SA_IO_READ_32 : MemoryConfig.h
  • SA_IO_READ_8 : MemoryConfig.h
  • SA_IO_WRITE_16 : MemoryConfig.h
  • SA_IO_WRITE_32 : MemoryConfig.h
  • SA_IO_WRITE_8 : MemoryConfig.h
  • SA_LEFT_SHIFT_64 : MemoryConfig.h
  • SA_MEMORY_COPY : MemoryConfig.h
  • SA_MEMORY_SET_BYTE : MemoryConfig.h
  • SA_MEMORY_SET_DWORD : MemoryConfig.h
  • SA_MEMORY_SET_WORD : MemoryConfig.h
  • SA_MMIO_READ_16 : MemoryConfig.h
  • SA_MMIO_READ_32 : MemoryConfig.h
  • SA_MMIO_READ_64 : MemoryConfig.h
  • SA_MMIO_READ_8 : MemoryConfig.h
  • SA_MMIO_WRITE_16 : MemoryConfig.h
  • SA_MMIO_WRITE_32 : MemoryConfig.h
  • SA_MMIO_WRITE_64 : MemoryConfig.h
  • SA_MMIO_WRITE_8 : MemoryConfig.h
  • SA_MRC_DRAM_RESET : MemoryConfig.h
  • SA_MRC_RETURN_FROM_SMC : MemoryConfig.h
  • SA_MSR_READ_64 : MemoryConfig.h
  • SA_MSR_WRITE_64 : MemoryConfig.h
  • SA_MULT_U64_U32 : MemoryConfig.h
  • SA_PRINTF : MemoryConfig.h
  • SA_RIGHT_SHIFT_64 : MemoryConfig.h
  • SA_SET_MEMORY_PMIC_VOLTAGE : MemoryConfig.h
  • SA_SET_MEMORY_VDD : MemoryConfig.h
  • SA_SHIFT_PI_COMMAND_TRAIN : MemoryConfig.h
  • SA_SIGN_EXTEND : MemoryConfig.h
  • SA_SMBUS_READ_16 : MemoryConfig.h
  • SA_SMBUS_READ_8 : MemoryConfig.h
  • SA_SMBUS_WRITE_16 : MemoryConfig.h
  • SA_SMBUS_WRITE_8 : MemoryConfig.h
  • SA_SPD : MemoryConfig.h
  • SA_UPDATE_VREF : MemoryConfig.h
  • SERIAL_IO_CS_POLARITY : SerialIoDevices.h
  • SERIAL_IO_I2C_MODE : SerialIoDevices.h
  • SERIAL_IO_SPI_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_PG : SerialIoDevices.h
  • SerialIoUartPgAuto : SerialIoDevices.h
  • SerialIoUartPgDisabled : SerialIoDevices.h
  • SerialIoUartPgEnabled : SerialIoDevices.h
  • SI_POLICY_REVISION : SiPolicyStruct.h
  • SI_PREMEM_POLICY_REVISION : SiPolicyStruct.h
  • SIGNATURE_16 : Base.h
  • SIGNATURE_32 : Base.h
  • SIGNATURE_64 : Base.h
  • SPD_BOOT_MODE : MemoryConfig.h
  • SpdBootModeMax : MemoryConfig.h
  • SpdCold : MemoryConfig.h
  • SpdFast : MemoryConfig.h
  • SPDProfileMax : MemoryConfig.h
  • SpdS3 : MemoryConfig.h
  • SpdWarm : MemoryConfig.h
  • STATIC : Base.h
  • STATIC_ASSERT : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- t -

  • Thc : ThcConfig.h
  • THC_MODE : ThcConfig.h
  • THC_PORT_ASSIGNMENT : ThcConfig.h
  • ThcAssignmentNone : ThcConfig.h
  • ThcAssignmentThc0 : ThcConfig.h
  • ThcAssignmentThc1 : ThcConfig.h
  • TRACE_BUFFER_SIZE : TraceHubConfig.h
  • TRACE_HUB_ENABLE_MODE : TraceHubConfig.h
  • TRUE : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- u -

  • UNREACHABLE : Base.h
  • USB_OC_MAX_PINS : UsbConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- v -

  • VA_ARG : Base.h
  • VA_COPY : Base.h
  • VA_END : Base.h
  • VA_LIST : Base.h
  • VA_START : Base.h
  • VOID : Base.h
  • VTD_ENABLE_DMA_BUFFER : VtdConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

Here is a list of all documented file members with links to the documentation:

- x -

  • XMP_PROFILE_1 : MemoryConfig.h
  • XMP_PROFILE_2 : MemoryConfig.h
  • XMP_PROFILE_3 : MemoryConfig.h
  • XMP_USER_PROFILE_4 : MemoryConfig.h
  • XMP_USER_PROFILE_5 : MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

  • AddConfigBlock() : ConfigBlockLib.h
  • CreateConfigBlockTable() : ConfigBlockLib.h
  • GetConfigBlock() : ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

  • gBiosGuardConfigGuid : BiosGuardConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

- a -

  • AMT_REPORT_ERROR : AmtConfig.h

- b -

  • BASE_LIST : Base.h

- c -

  • CONFIG_BLOCK : ConfigBlock.h
  • CONFIG_BLOCK_HEADER : ConfigBlock.h
  • CONFIG_BLOCK_TABLE_HEADER : ConfigBlock.h

- e -

  • EFI_AP_PROCEDURE : PiMultiPhase.h
  • EFI_AP_PROCEDURE2 : PiMultiPhase.h
  • EFI_EVENT : UefiBaseType.h
  • EFI_GUID : UefiBaseType.h
  • EFI_HANDLE : UefiBaseType.h
  • EFI_IPv4_ADDRESS : UefiBaseType.h
  • EFI_IPv6_ADDRESS : UefiBaseType.h
  • EFI_LBA : UefiBaseType.h
  • EFI_MM_RESERVED_MMRAM_REGION : PiMultiPhase.h
  • EFI_PEI_MP_SERVICES_ENABLEDISABLEAP : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS : MpServices.h
  • EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_ALL_APS : MpServices.h
  • EFI_PEI_MP_SERVICES_STARTUP_THIS_AP : MpServices.h
  • EFI_PEI_MP_SERVICES_SWITCH_BSP : MpServices.h
  • EFI_PEI_MP_SERVICES_WHOAMI : MpServices.h
  • EFI_PHYSICAL_ADDRESS : UefiBaseType.h
  • EFI_RESOURCE_ATTRIBUTE_TYPE : PiHob.h
  • EFI_RESOURCE_TYPE : PiHob.h
  • EFI_STATUS : UefiBaseType.h
  • EFI_TPL : UefiBaseType.h
  • EFI_VIRTUAL_ADDRESS : UefiBaseType.h

- g -

  • GPIO_GROUP : GpioConfig.h
  • GPIO_PAD : GpioConfig.h

- i -

  • ITBT_GENERIC_CONFIG : PeiITbtGenericStructure.h
  • ITBT_ROOTPORT_CONFIG : PeiITbtGenericStructure.h

- l -

  • LIST_ENTRY : Base.h

- p -

  • PEI_ITBT_CONFIG : PeiITbtConfig.h
  • PEI_POLICY_INIT : PeiSiDefaultPolicy.h
  • PEI_PREMEM_POLICY_INIT : PeiPreMemSiDefaultPolicy.h
  • PLATFORM_SEND_EC_COMMAND : BiosGuardConfig.h
  • PPM_CUSTOM_CTDP_TABLE : CpuPowerMgmtCustomConfig.h

- s -

  • SA_CHANGE_MARGIN : MemoryConfig.h
  • SA_CHANNEL_EXIST : MemoryConfig.h
  • SA_CHECKPOINT : MemoryConfig.h
  • SA_CPU_MAILBOX_READ : MemoryConfig.h
  • SA_CPU_MAILBOX_WRITE : MemoryConfig.h
  • SA_DEBUG_HOOK : MemoryConfig.h
  • SA_DEBUG_PRINT : MemoryConfig.h
  • SA_DELAY_NS : MemoryConfig.h
  • SA_DIV_U64_U64 : MemoryConfig.h
  • SA_GET_CPU_TIME : MemoryConfig.h
  • SA_GET_MEMORY_VDD : MemoryConfig.h
  • SA_GET_PCI_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_PCIE_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_RANDOM_NUMBER : MemoryConfig.h
  • SA_GET_RTC_CMOS : MemoryConfig.h
  • SA_GET_RTC_TIME : MemoryConfig.h
  • SA_GET_SPD_DATA : MemoryConfig.h
  • SA_IO_READ_16 : MemoryConfig.h
  • SA_IO_READ_32 : MemoryConfig.h
  • SA_IO_READ_8 : MemoryConfig.h
  • SA_IO_WRITE_16 : MemoryConfig.h
  • SA_IO_WRITE_32 : MemoryConfig.h
  • SA_IO_WRITE_8 : MemoryConfig.h
  • SA_LEFT_SHIFT_64 : MemoryConfig.h
  • SA_MEMORY_COPY : MemoryConfig.h
  • SA_MEMORY_SET_BYTE : MemoryConfig.h
  • SA_MEMORY_SET_DWORD : MemoryConfig.h
  • SA_MEMORY_SET_WORD : MemoryConfig.h
  • SA_MMIO_READ_16 : MemoryConfig.h
  • SA_MMIO_READ_32 : MemoryConfig.h
  • SA_MMIO_READ_64 : MemoryConfig.h
  • SA_MMIO_READ_8 : MemoryConfig.h
  • SA_MMIO_WRITE_16 : MemoryConfig.h
  • SA_MMIO_WRITE_32 : MemoryConfig.h
  • SA_MMIO_WRITE_64 : MemoryConfig.h
  • SA_MMIO_WRITE_8 : MemoryConfig.h
  • SA_MRC_DRAM_RESET : MemoryConfig.h
  • SA_MRC_RETURN_FROM_SMC : MemoryConfig.h
  • SA_MSR_READ_64 : MemoryConfig.h
  • SA_MSR_WRITE_64 : MemoryConfig.h
  • SA_MULT_U64_U32 : MemoryConfig.h
  • SA_PRINTF : MemoryConfig.h
  • SA_RIGHT_SHIFT_64 : MemoryConfig.h
  • SA_SET_MEMORY_PMIC_VOLTAGE : MemoryConfig.h
  • SA_SET_MEMORY_VDD : MemoryConfig.h
  • SA_SHIFT_PI_COMMAND_TRAIN : MemoryConfig.h
  • SA_SIGN_EXTEND : MemoryConfig.h
  • SA_SMBUS_READ_16 : MemoryConfig.h
  • SA_SMBUS_READ_8 : MemoryConfig.h
  • SA_SMBUS_WRITE_16 : MemoryConfig.h
  • SA_SMBUS_WRITE_8 : MemoryConfig.h
  • SA_UPDATE_VREF : MemoryConfig.h

- v -

  • VA_LIST : Base.h
  • VTD_ENABLE_DMA_BUFFER : VtdConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

- a -

  • AMT_ERROR_MSG_ID : AmtConfig.h

- c -

  • C_STATE_TIME_UNIT : CpuPowerMgmtTestConfig.h
  • CNVI_MODE : CnviConfig.h
  • CPU_PCIE_ASPM_CONTROL : CpuPcieConfig.h
  • CPU_PCIE_EQ_METHOD : CpuPcieConfig.h
  • CPU_PCIE_L1SUBSTATES_CONTROL : CpuPcieConfig.h
  • CUSTOM_POWER_UNIT : CpuPowerMgmtTestConfig.h

- d -

  • DMI_ASPM : CpuDmiPreMemConfig.h

- e -

  • EC_COMMAND_TYPE : BiosGuardConfig.h

- f -

  • FIVR_RAIL_SX_STATE : FivrConfig.h

- g -

  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • GPIO_SUPPORT : HybridGraphicsConfig.h

- m -

  • MAX_PKG_C_STATE : CpuPowerMgmtTestConfig.h

- p -

  • PCH_INT_PIN : InterruptConfig.h
  • PCH_PCIE_ASPM_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_CLOCK_USAGE : PchPcieRpConfig.h
  • PCH_PCIE_L1SUBSTATES_CONTROL : PchPcieRpConfig.h
  • PCH_RESERVED_PAGE_ROUTE : PchGeneralConfig.h
  • PCH_SLP_S4_MIN_ASSERT : PmConfig.h
  • PCIE_FORM_FACTOR : PcieConfig.h
  • PCIE_LINK_EQ_METHOD : PcieConfig.h
  • PCIE_LINK_EQ_MODE : PcieConfig.h
  • PPM_IRM_SETTING : CpuPowerMgmtTestConfig.h

- s -

  • SA_SPD : MemoryConfig.h
  • SERIAL_IO_CS_POLARITY : SerialIoDevices.h
  • SERIAL_IO_I2C_MODE : SerialIoDevices.h
  • SERIAL_IO_SPI_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_PG : SerialIoDevices.h
  • SPD_BOOT_MODE : MemoryConfig.h

- t -

  • THC_MODE : ThcConfig.h
  • THC_PORT_ASSIGNMENT : ThcConfig.h
  • TRACE_BUFFER_SIZE : TraceHubConfig.h
  • TRACE_HUB_ENABLE_MODE : TraceHubConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

- c -

  • CpuPcieEqDefault : CpuPcieConfig.h
  • CpuPcieEqHardware : CpuPcieConfig.h
  • CpuPcieEqStaticCoeff : CpuPcieConfig.h
  • CUSTOM_PROFILE : MemoryConfig.h

- d -

  • DEFAULT_SPD : MemoryConfig.h

- g -

  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioNoTolerance1v8 : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateLock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDeep : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResetNormal : GpioConfig.h
  • GpioResetPwrGood : GpioConfig.h
  • GpioResetResume : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h
  • GpioTolerance1v8 : GpioConfig.h

- h -

  • HidOverSpi : ThcConfig.h

- p -

  • PchClockUsageCpuPcie0 : PchPcieRpConfig.h
  • PchClockUsageUnspecified : PchPcieRpConfig.h
  • PchNoInt : InterruptConfig.h
  • PchReservedPageToLpc : PchGeneralConfig.h
  • PchReservedPageToPcie : PchGeneralConfig.h
  • PchSlpS4PchTime : PmConfig.h
  • PcieLinkEqCoefficientMode : PcieConfig.h
  • PcieLinkEqPresetMode : PcieConfig.h
  • PcieLinkFixedEq : PcieConfig.h
  • PcieLinkHardwareEq : PcieConfig.h
  • PowerUnit125MilliWatts : CpuPowerMgmtTestConfig.h
  • PowerUnitWatts : CpuPowerMgmtTestConfig.h

- s -

  • SerialIoUartPgAuto : SerialIoDevices.h
  • SerialIoUartPgDisabled : SerialIoDevices.h
  • SerialIoUartPgEnabled : SerialIoDevices.h
  • SpdBootModeMax : MemoryConfig.h
  • SpdCold : MemoryConfig.h
  • SpdFast : MemoryConfig.h
  • SPDProfileMax : MemoryConfig.h
  • SpdS3 : MemoryConfig.h
  • SpdWarm : MemoryConfig.h

- t -

  • Thc : ThcConfig.h
  • ThcAssignmentNone : ThcConfig.h
  • ThcAssignmentThc0 : ThcConfig.h
  • ThcAssignmentThc1 : ThcConfig.h

- x -

  • XMP_PROFILE_1 : MemoryConfig.h
  • XMP_PROFILE_2 : MemoryConfig.h
  • XMP_PROFILE_3 : MemoryConfig.h
  • XMP_USER_PROFILE_4 : MemoryConfig.h
  • XMP_USER_PROFILE_5 : MemoryConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: File Members

- _ -

  • _BASE_INT_SIZE_OF : Base.h
  • _CONCATENATE : Base.h
  • _INT_SIZE_OF : Base.h

- a -

  • ABS : Base.h
  • ALIGN_POINTER : Base.h
  • ALIGN_VALUE : Base.h
  • ALIGN_VARIABLE : Base.h
  • ANALYZER_NORETURN : Base.h
  • ANALYZER_UNREACHABLE : Base.h
  • ARRAY_SIZE : Base.h
  • ASM_PFX : Base.h

- b -

  • B_GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK : GpioConfig.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • BASE_ARG : Base.h
  • BASE_CR : Base.h
  • BIOS_GUARD_CONFIG_REVISION : BiosGuardConfig.h

- c -

  • CONST : Base.h
  • CPU_PCIE_CONFIG_REVISION : CpuPcieConfig.h

- d -

  • DXE_ERROR : PiMultiPhase.h

- e -

  • EFI_AUTH_STATUS_PLATFORM_OVERRIDE : PiMultiPhase.h
  • EFI_CONNECTION_FIN : UefiBaseType.h
  • EFI_HOB_HANDOFF_TABLE_VERSION : PiHob.h
  • EFI_IMAGE_MACHINE_AARCH64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_ARMTHUMB_MIXED : UefiBaseType.h
  • EFI_IMAGE_MACHINE_EBC : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_IA64 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_RISCV32 : UefiBaseType.h
  • EFI_IMAGE_MACHINE_X64 : UefiBaseType.h
  • EFI_INTERRUPT_PENDING : PiMultiPhase.h
  • EFI_MMRAM_OPEN : PiMultiPhase.h
  • EFI_NETWORK_UNREACHABLE : UefiBaseType.h
  • EFI_NOT_AVAILABLE_YET : PiMultiPhase.h
  • EFI_PAGES_TO_SIZE : UefiBaseType.h
  • EFI_REQUEST_UNLOAD_IMAGE : PiMultiPhase.h
  • EFI_SIZE_TO_PAGES : UefiBaseType.h
  • EFI_SUCCESS : UefiBaseType.h
  • EFIERR : UefiBaseType.h
  • ENCODE_ERROR : Base.h
  • ENCODE_WARNING : Base.h

- f -

  • FALSE : Base.h
  • FSP_ERROR_INFO_HOB_GUID : FspErrorInfo.h
  • FSPM_ARCH_CONFIG_GUID : FspmArchConfigPpi.h

- g -

  • GLOBAL_REMOVE_IF_UNREFERENCED : Base.h

- h -

  • HDAUDIO_VERB_TABLE_INIT : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_VIDDID : HdAudioConfig.h

- i -

  • IN : Base.h

- m -

  • MAX : Base.h
  • MAX_CUSTOM_CTDP_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_CUSTOM_RATIO_TABLE_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_INT8 : Base.h
  • MAX_NUM_VRS : CpuPowerMgmtVrConfig.h
  • MEM_CFG_MAX_CONTROLLERS : MemoryConfig.h
  • MIN : Base.h
  • MIN_INT8 : Base.h
  • MRC_MAX_RCOMP_TARGETS : MemoryConfig.h

- n -

  • NORETURN : Base.h
  • NULL : Base.h

- o -

  • OFFSET_OF : Base.h
  • OPTIONAL : Base.h
  • OUT : Base.h

- p -

  • PcdFspAreaBaseAddress : FspFixedPcds.h
  • PcdFspImageIdString : FspFixedPcds.h
  • PcdFspReservedBufferSize : FspFixedPcds.h
  • PcdGlobalDataPointerAddress : FspFixedPcds.h
  • PcdSiliconInitVersionBuild : FspFixedPcds.h
  • PcdSiliconInitVersionMajor : FspFixedPcds.h
  • PcdSiliconInitVersionMinor : FspFixedPcds.h
  • PcdSiliconInitVersionRevision : FspFixedPcds.h
  • PcdTemporaryRamBase : FspFixedPcds.h
  • PcdTemporaryRamSize : FspFixedPcds.h
  • PCH_FIVR_CONFIG_REVISION : FivrConfig.h
  • PCH_MAX_DEVICE_INTERRUPT_CONFIG : InterruptConfig.h
  • PCH_MAX_ITSS_IPC_REGS : InterruptConfig.h
  • PCH_MAX_ITSS_IRQ_NUM : InterruptConfig.h
  • PCH_MAX_PXRC_CONFIG : InterruptConfig.h
  • PEI_MR_SMRAM_ABSEG_MASK : MemoryConfig.h
  • PI_ENCODE_ERROR : PiMultiPhase.h
  • PI_ENCODE_WARNING : PiMultiPhase.h

- r -

  • RETURN_ABORTED : Base.h
  • RETURN_ACCESS_DENIED : Base.h
  • RETURN_ADDRESS : Base.h
  • RETURN_ALREADY_STARTED : Base.h
  • RETURN_BAD_BUFFER_SIZE : Base.h
  • RETURN_BUFFER_TOO_SMALL : Base.h
  • RETURN_COMPROMISED_DATA : Base.h
  • RETURN_CRC_ERROR : Base.h
  • RETURN_DEVICE_ERROR : Base.h
  • RETURN_END_OF_FILE : Base.h
  • RETURN_END_OF_MEDIA : Base.h
  • RETURN_ERROR : Base.h
  • RETURN_HTTP_ERROR : Base.h
  • RETURN_ICMP_ERROR : Base.h
  • RETURN_INCOMPATIBLE_VERSION : Base.h
  • RETURN_INVALID_LANGUAGE : Base.h
  • RETURN_INVALID_PARAMETER : Base.h
  • RETURN_LOAD_ERROR : Base.h
  • RETURN_MEDIA_CHANGED : Base.h
  • RETURN_NO_MAPPING : Base.h
  • RETURN_NO_MEDIA : Base.h
  • RETURN_NO_RESPONSE : Base.h
  • RETURN_NOT_FOUND : Base.h
  • RETURN_NOT_READY : Base.h
  • RETURN_NOT_STARTED : Base.h
  • RETURN_OUT_OF_RESOURCES : Base.h
  • RETURN_PROTOCOL_ERROR : Base.h
  • RETURN_SECURITY_VIOLATION : Base.h
  • RETURN_SUCCESS : Base.h
  • RETURN_TFTP_ERROR : Base.h
  • RETURN_TIMEOUT : Base.h
  • RETURN_UNSUPPORTED : Base.h
  • RETURN_VOLUME_CORRUPTED : Base.h
  • RETURN_VOLUME_FULL : Base.h
  • RETURN_WARN_BUFFER_TOO_SMALL : Base.h
  • RETURN_WARN_DELETE_FAILURE : Base.h
  • RETURN_WARN_FILE_SYSTEM : Base.h
  • RETURN_WARN_STALE_DATA : Base.h
  • RETURN_WARN_UNKNOWN_GLYPH : Base.h
  • RETURN_WARN_WRITE_FAILURE : Base.h
  • RETURN_WRITE_PROTECTED : Base.h
  • RETURNS_TWICE : Base.h

- s -

  • SI_POLICY_REVISION : SiPolicyStruct.h
  • SI_PREMEM_POLICY_REVISION : SiPolicyStruct.h
  • SIGNATURE_16 : Base.h
  • SIGNATURE_32 : Base.h
  • SIGNATURE_64 : Base.h
  • STATIC : Base.h
  • STATIC_ASSERT : Base.h

- t -

  • TRUE : Base.h

- u -

  • UNREACHABLE : Base.h
  • USB_OC_MAX_PINS : UsbConfig.h

- v -

  • VA_ARG : Base.h
  • VA_COPY : Base.h
  • VA_END : Base.h
  • VA_START : Base.h
  • VOID : Base.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Gen4 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4
Gen4 Directory Reference
Directory dependency graph for Gen4:

Files

file CpuPcieConfig.h [code]
Pcie root port policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Intel
  • AlderLakeFspBinPkg
  • Include
Include Directory Reference
Directory dependency graph for Include:

Files

file | FirmwareVersionInfoHob.h [code]
Header file for Firmware Version Information.
file | FspInfoHob.h [code]
Header file for FSP Information HOB.
file | GpioConfig.h [code]
Header file for GpioConfig structure used by GPIO library.
file | GpioSampleDef.h [code]
Copyright (c) 2015 - 2021, Intel Corporation.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ClientOneSiliconPkg -> Edk2 Relation

  • Intel
  • ClientOneSiliconPkg

ClientOneSiliconPkg → Edk2 Relation

File in Intel/ClientOneSiliconPkg | Includes file in Edk2
Include / ConfigBlock.h | MdePkg / Include / Uefi / UefiBaseType.h
Include / ConfigBlock.h | MdePkg / Include / Pi / PiHob.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Gbe Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
Gbe Directory Reference

Files

file GbeConfig.h [code]
Gigabit Ethernet policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Rst Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rst
Rst Directory Reference
Directory dependency graph for Rst:

Files

file RstConfig.h [code]
Rst policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include -> Edk2 Relation

  • Intel
  • ClientOneSiliconPkg
  • Include

Include → Edk2 Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Edk2
ConfigBlock.h | MdePkg / Include / Pi / PiHob.h
ConfigBlock.h | MdePkg / Include / Uefi / UefiBaseType.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Library Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Library Directory Reference

Files

file ConfigBlockLib.h [code]
Header file for Config Block Lib implementation.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Cpu Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
Cpu Directory Reference
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock

ConfigBlock → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock | Includes file in Intel/ClientOneSiliconPkg/Include/Library
Amt / AmtConfig.h | ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Hda Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
Hda Directory Reference
Directory dependency graph for Hda:

Files

file HdAudioConfig.h [code]
HDAUDIO policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Fivr Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
Fivr Directory Reference

Files

file FivrConfig.h [code]
PCH FIVR policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchPcieRp Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
PchPcieRp Directory Reference
Directory dependency graph for PchPcieRp:

Files

file PchPcieRpConfig.h [code]
PCH Pcie root port policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SerialIo Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
SerialIo Directory Reference
Directory dependency graph for SerialIo:

Files

file SerialIoConfig.h [code]
Serial IO policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Rtc Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
Rtc Directory Reference

Files

file RtcConfig.h [code]
RTC policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: SystemAgent Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
SystemAgent Directory Reference
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Uefi Directory Reference

  • Edk2
  • MdePkg
  • Include
  • Uefi
Uefi Directory Reference
Directory dependency graph for Uefi:

Files

file UefiBaseType.h [code]
Defines data types and constants introduced in UEFI.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Amt -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt

Amt → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Amt | Includes file in Intel/ClientOneSiliconPkg/Include/Library
AmtConfig.h | ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: DoxygenInternalOnly Directory Reference

  • Intel
  • AlderLakeFspBinPkg
  • DoxygenInternalOnly
DoxygenInternalOnly Directory Reference

Files

file FspFixedPcds.h [code]
This file lists all FixedAtBuild PCDs referenced in FSP integration guide.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Thermal Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
Thermal Directory Reference

Files

file ThermalConfig.h [code]
Thermal policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file | LockDownConfig.h [code]
Lock down policy.
file | PchGeneralConfig.h [code]
PCH General policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Ish Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
Ish Directory Reference

Files

file IshConfig.h [code]
ISH policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file | SaMiscPeiConfig.h [code]
Policy details for miscellaneous configuration in System Agent.
file | SaMiscPeiPreMemConfig.h [code]
Policy details for miscellaneous configuration in System Agent.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Sata Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
Sata Directory Reference
Directory dependency graph for Sata:

Files

file SataConfig.h [code]
Sata policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Gna Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
Gna Directory Reference

Files

file GnaConfig.h [code]
Policy definition for GNA Config Block.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
Include Directory Reference

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Thc Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
Thc Directory Reference

Files

file ThcConfig.h [code]
Touch Host Controller policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Guid Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
Guid Directory Reference

Files

file FspErrorInfo.h [code]
FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Me Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
Me Directory Reference

Files

file MePeiConfig.h [code]
ME config block for PEI phase.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Dci Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
Dci Directory Reference

Files

file DciConfig.h [code]
Dci policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPcieRp -> PcieRp Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp

CpuPcieRp → PcieRp Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/PcieRp
Gen4 / CpuPcieConfig.h | PcieConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Gen4 -> PcieRp Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4

Gen4 → PcieRp Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4 | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/PcieRp
CpuPcieConfig.h | PcieConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AlderLakeFspBinPkg -> Edk2 Relation

  • Intel
  • AlderLakeFspBinPkg

AlderLakeFspBinPkg → Edk2 Relation

File in Intel/AlderLakeFspBinPkg | Includes file in Edk2
Include / FirmwareVersionInfoHob.h | MdePkg / Include / Pi / PiHob.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include -> Edk2 Relation

  • Intel
  • AlderLakeFspBinPkg
  • Include

Include → Edk2 Relation

File in Intel/AlderLakeFspBinPkg/Include | Includes file in Edk2
FirmwareVersionInfoHob.h | MdePkg / Include / Pi / PiHob.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: AlderLakeFspBinPkg Directory Reference

  • Intel
  • AlderLakeFspBinPkg
AlderLakeFspBinPkg Directory Reference
Directory dependency graph for AlderLakeFspBinPkg:

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Edk2 Directory Reference

  • Edk2
Edk2 Directory Reference
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Ppi Directory Reference

  • Edk2
  • MdePkg
  • Include
  • Ppi
Ppi Directory Reference

Files

file MpServices.h [code]
This file declares UEFI PI Multi-processor PPI.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuDmi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuDmi
CpuDmi Directory Reference
Directory dependency graph for CpuDmi:

Files

file CpuDmiPreMemConfig.h [code]
DMI policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Pi Directory Reference

  • Edk2
  • MdePkg
  • Include
  • Pi
Pi Directory Reference

Files

file | PiHob.h [code]
HOB related definitions in PI.
file | PiMultiPhase.h [code]
Include file matches things in PI for multiple module types.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Tbt Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
Tbt Directory Reference
Directory dependency graph for Tbt:

Files

file PeiITbtConfig.h [code]
Header file for TBT PEI Policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Tcss -> Usb Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss

Tcss → Usb Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Tcss | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Usb
TcssPeiConfig.h | UsbConfig.h
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Amt Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
Amt Directory Reference
Directory dependency graph for Amt:

Files

file AmtConfig.h [code]
AMT Config Block for PEI/DXE phase.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Ver2 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
  • Ver2
Ver2 Directory Reference

Files

file MemoryConfig.h [code]
Policy definition of Memory Config Block.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Smbus Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
Smbus Directory Reference

Files

file SmbusConfig.h [code]
Smbus policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Gen12 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
  • Gen12
Gen12 Directory Reference

Files

file GraphicsConfig.h [code]
Policy definition for Internal Graphics Config Block.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ClientOneSiliconPkg Directory Reference

  • Intel
  • ClientOneSiliconPkg
ClientOneSiliconPkg Directory Reference
Directory dependency graph for ClientOneSiliconPkg:

Directories

directory | Cpu
directory | Pch
directory | SystemAgent
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Memory Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
Memory Directory Reference

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Tcss Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Tcss Directory Reference
Directory dependency graph for Tcss:

Files

file | TcssPeiConfig.h [code]
TCSS PEI policy.
file | TcssPeiPreMemConfig.h [code]
TCSS PEI PreMem policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Usb Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb Directory Reference

Files

file | Usb2PhyConfig.h [code]
USB2 PHY configuration policy.
file | Usb3HsioConfig.h [code]
USB3 Mod PHY configuration policy.
file | UsbConfig.h [code]
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Pch Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
Pch Directory Reference
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: BiosGuard Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • BiosGuard
BiosGuard Directory Reference

Files

file BiosGuardConfig.h [code]
CPU BIOS Guard Config Block.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
Include Directory Reference

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Telemetry Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
Telemetry Directory Reference
Directory dependency graph for Telemetry:

Files

file TelemetryPeiConfig.h [code]
Configurations for Telemetry.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HybridStorage Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridStorage
HybridStorage Directory Reference
Directory dependency graph for HybridStorage:

Files

file HybridStorageConfig.h [code]
Hybrid Storage policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Include Directory Reference

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Intel Directory Reference

  • Intel
Intel Directory Reference
Directory dependency graph for Intel:
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PchDmi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
PchDmi Directory Reference

Files

file PchDmiConfig.h [code]
DMI policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Psf Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Psf
Psf Directory Reference
Directory dependency graph for Psf:

Files

file PsfConfig.h [code]
Primary Sideband Fabric policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Ieh Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
Ieh Directory Reference
Directory dependency graph for Ieh:

Files

file IehConfig.h [code]
Integrated Error Handler policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file | ConfigBlock.h [code]
Header file for Config Block Lib implementation.
file | PeiITbtGenericStructure.h [code]
ITBT Policy definition to be referred in both PEI and DXE phase.
file | SerialIoDevices.h [code]
Serial IO policy.
file | SiPolicyStruct.h [code]
Intel reference code configuration policies.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file | CpuConfig.h [code]
CPU Config Block.
file | CpuConfigLibPreMemConfig.h [code]
CPU Security PreMemory Config Block.
file | CpuPowerMgmtBasicConfig.h [code]
CPU Power Management Basic Config Block.
file | CpuPowerMgmtCustomConfig.h [code]
CPU Power Managment Custom Config Block.
file | CpuPowerMgmtPsysConfig.h [code]
CPU Power Management Psys(Platform) Config Block.
file | CpuPowerMgmtTestConfig.h [code]
CPU Power Management Test Config Block.
file | CpuSecurityPreMemConfig.h [code]
CPU Security PreMemory Config Block.
file | CpuTestConfig.h [code]
CPU Test Config Block.
file | CpuTxtConfig.h [code]
CPU TXT PreMemory Config Block.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Ppi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Ppi Directory Reference

Files

file | FspmArchConfigPpi.h [code]
Header file for FSP-M Arch Config PPI.
file | PeiPreMemSiDefaultPolicy.h [code]
This file defines the function to initialize default silicon policy PPI.
file | PeiSiDefaultPolicy.h [code]
This file defines the function to initialize default silicon policy PPI.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: P2sb Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
P2sb Directory Reference

Files

file P2sbConfig.h [code]
P2sb policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: TraceHub Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
TraceHub Directory Reference
Directory dependency graph for TraceHub:

Files

file TraceHubConfig.h [code]
Configurations for TraceHub.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: CpuPcieRp Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
CpuPcieRp Directory Reference
Directory dependency graph for CpuPcieRp:

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Cnvi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
Cnvi Directory Reference

Files

file CnviConfig.h [code]
CNVi policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Vmd Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
Vmd Directory Reference
Directory dependency graph for Vmd:

Files

file VmdPeiConfig.h [code]
VMD PEI policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: VoltageRegulator Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • VoltageRegulator
VoltageRegulator Directory Reference

Files

file CpuPowerMgmtVrConfig.h [code]
CPU Power Management VR Config Block.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Graphics Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
Graphics Directory Reference

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Vtd Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
Vtd Directory Reference

Files

file VtdConfig.h [code]
VT-d policy definitions.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: PcieRp Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
PcieRp Directory Reference
Directory dependency graph for PcieRp:

Directories

Files

file | PcieConfig.h [code]
PCIe Config Block.
file | PciePreMemConfig.h [code]
PCIe Config Block PreMem.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Tsn Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
Tsn Directory Reference

Files

file TsnConfig.h [code]
TSN Config policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: HybridGraphics Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
HybridGraphics Directory Reference

Files

file HybridGraphicsConfig.h [code]
Hybrid Graphics policy definitions.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
ConfigBlock Directory Reference
Directory dependency graph for ConfigBlock:

Directories

directory | CpuPcieRp
directory | Graphics
directory | Memory

Files

file | SiConfig.h [code]
Si Config Block.
file | SiPreMemConfig.h [code]
Si Config Block PreMem.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Pmc Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Pmc Directory Reference
Directory dependency graph for Pmc:

Files

file | AdrConfig.h [code]
ADR policy.
file | PmConfig.h [code]
Power Management policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Overclocking Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking
Overclocking Directory Reference

Files

file OverclockingConfig.h [code]
Overclocking Config Block.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: MdePkg Directory Reference

  • Edk2
  • MdePkg
MdePkg Directory Reference
Directory dependency graph for MdePkg:

Directories

Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Espi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Espi Directory Reference

Files

file EspiConfig.h [code]
Espi policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Itss Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Itss Directory Reference

Files

file | InterruptConfig.h [code]
Interrupt policy.
file | IoApicConfig.h [code]
IoApic policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Include Directory Reference

  • Edk2
  • MdePkg
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file Base.h [code]
Root include file for Mde Package Base type modules.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Ipu Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
Ipu Directory Reference
Directory dependency graph for Ipu:

Files

file IpuPreMemConfig.h [code]
IPU policy definitions.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Wdt Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
Wdt Directory Reference

Files

file WatchDogConfig.h [code]
WatchDog policy.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };
/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };
/* Class not documented with doxygen comments */
class Undocumented { };
/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };
/*! A template class */
template<class T> class Templ { };
/*! Class that is inherited using protected inheritance */
class ProtectedBase { };
/*! Class that is inherited using private inheritance */
class PrivateBase { };
/*! Class that is used by the Inherited class */
class Used { };
/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ<int>
{
private:
Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a gray border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labelled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labelled with the template parameters of the instance.
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Related Pages

Related Pages
Here is a list of all related documentation pages:
[detail level 12]
2 Overview |
3 FSP Integration |
▼ 4 FSP Dispatch Mode |
4.1 Dispatch Mode Policy Init | For the plurality of platform designs, most of the policy options provided by FSP do not need to be modified by the bootloader
4.2 Config Blocks |
4.3 FSP Error Information | In the case of a fatal error occurring during the execution of the FSP, it may not be possible for the FSP to continue
4.4 Dispatch Mode Integration | Dispatch Mode Integration Notes:
▼ 5 FSP API Mode |
5.1 FSP APIs |
5.2 Reset Return Codes | As per FSP External Architecture Specification version 2.0/2.1/2.2, any reset required in the FSP flow will be reported by returning one of the FSP_STATUS_RESET_REQUIRED* return codes
5.3 UPD Porting Guide | Recommended values for UPDs:
6 Porting Recommendations | Here are some notes and recommendations for adapting an existing boot loader to FSP
7 FSP Output | The FSP builds a series of data structures called Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon
8 POST Codes | The FSP outputs 16-bit POST codes to indicate which API and which module is currently executing
Deprecated List |
Todo List |
Generated on Wed Jan 5 2022 01:26:02 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20


AlderLake Intel® Firmware Support Package (FSP) Integration Guide: Member List

EFI_HOB_FIRMWARE_VOLUME Member List

This is the complete list of members for EFI_HOB_FIRMWARE_VOLUME, including all inherited members.

BaseAddress | EFI_HOB_FIRMWARE_VOLUME
Header | EFI_HOB_FIRMWARE_VOLUME
Length | EFI_HOB_FIRMWARE_VOLUME
Generated on Wed Jan 5 2022 01:26:01 for AlderLake Intel® Firmware Support Package (FSP) Integration Guide by doxygen 1.8.20