IceLake Platform Sample Code: 1 - Introduction

IceLake Platform Sample Code
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1 - Introduction
Note
Platform Sample Code specifications are auto generated via doxygen
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: MKHI Specification

  • Modules
  • Classes
  • Files
MKHI Specification

ABSTRACT

Intel platforms provide manageability features that allow IT departments to better manage corporate assets as well as ensure the client systems independence on operating system being present. These features are provided via manageability engine which runs out of band of host system and therefore is able to execute and provide manageability even when host system is down. ME accomplishes this task by participating in all system level activities such as power management transitions, communication with host OS through selected drivers such as HECI driver etc. ME, for the most part, operates independently of host, however in certain cases it does overlaps with host; most notably in its requirement of h/w resources. For example, BIOS initializes memory and informs ME such that it can utilize BIOS settings to initialize memory when needed. Similarly before ME can provide client specific manageability, it needs to be configured. One possible method to configure ME is MEBx, which runs during BIOS POST and communicates with ME over HECI messages. Communication between ME and host is intricate and can be broadly divided in following categories:

MKHI specification is divided into following sub-sections:

  • MKHI messages Group ID
  • MKHI messages Generic Types and Structures
  • BIOS/MRC -ME Kernel Register Based HECI communication
  • BIOS-ME Kernel HECI Communication
  • MEBx-ME Kernel HECI communication messages


IceLake Platform Sample Code: BIOS-ME Kernel HECI Communication

BIOS-ME Kernel HECI Communication

This section covers the HECI messages that are exchanged between BIOS POST and ME firmware.

Note that some of these messages might get used by the BIOS MRC however they are not restricted to MRC like messages. Related HECI messages are described below.

  • 1.1 Resets
  • 1.2 Manufacturing ME reset and Halt
  • 1.3 END OF POST
  • 1.4 Set Debug Memory Address Request


IceLake Platform Sample Code: MEBx-ME Kernel HECI communication messages

MEBx-ME Kernel HECI communication messages

This section covers HECI messages that are exchanged between MEBx and ME firmware (both kernel and application modules).

Note that this section controls the MKHI version in that any changes in this section effectively increase the MKHI version.Upon starting, MEBx checks the MKHI and AMTHI version numbers and if compatible, runs on the platform. If MEBx is not compatible with either of these revisions then it displays an error message. This functionality allows MEBx to run from one platform to another a long as there have been no changes in MKHI or AMTHI version numbers.Related HECI messages are described below.

  • 2.1 Get MKHI Version
  • 2.2 Get FW Version
  • 2.3 ME Unconfigure
  • 2.4 Get and Set ME Rule
  • 2.5 Get and Set ME Password
  • 2.6 Get and set ME FW SKU and Capabilities
  • 2.7 CPU Brand Class Related messages
  • 2.8 FW Update Messages
  • 2.9 ME MDES Messages
  • 2.10 ME BIST Messages
  • 2.12 ME Debug Messages


IceLake Platform Sample Code: MKHI messages Group ID

MKHI messages Group ID

Each MKHI client in firmware is identified by its GROUP ID.

Following GROUPIDs are supported in firmware:

Group ID | Category Details
MKHI_CBM_GROUP_ID=0x00 | Core BIOS Messages targeted for PM driver
MKHI_PM_GROUP_ID=0x01 | PM Config Messages
MKHI_PWD_GROUP_ID=0x02 | Password config messages
MKHI_FWCAPS_GROUP_ID=0x03 | FW Capabilities config messages
MKHI_APP_GROUP_ID=0x04 | Application config data access messages
MKHI_FWUPDATE_GROUP_ID=0x05 | Used to Query and resume FW update process. This is used for manufacturing downgrade.
MKHI_FIRMWARE_UPDATE_GROUP_ID=0x06 | Used for FW upgrade process. Need to check with FWU team..
MKHI_BIST_GROUP_ID=0x07 | Used for perform ME BIST tests.
MKHI_MDES_GROUP_ID=0x08 | Used for ME debug MDES messaging
MKHI_ME_DBG_GROUP_ID=0x09 | Used internally for ME debug.
MKHI_FPF_GROUP_ID=0x10 | Maximum value of MKHI group ID
MKHI_MAX_GROUP_ID=0x11 | Maximum value of MKHI group ID
MKHI_GEN_GROUP_ID =0xff | General messages targeted to MKHI fw client


IceLake Platform Sample Code: 2 - Platform Sample Module

2 - Platform Sample Module

2.1 - ACPI

Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.1 - ACPI

  • 2 - Platform Sample Module
2.1 - ACPI

This document describes the ACPI design for platform sample code and provides detailed descriptions for all the ASL code in the package. It is a useful reference for the implementation of ACPI support for Kabylake based platforms.

  • 2.1.1 - Architectural Overview
  • 2.1.2 - Rationale
  • 2.1.3 - Requirements
  • 2.1.4 - API
  • 2.1.5 - Build Flags
  • 2.1.6 - MiscInfo


IceLake Platform Sample Code: 2.1.1 - Architectural Overview

  • 2 - Platform Sample Module
  • 2.1 - ACPI
2.1.1 - Architectural Overview

ACPI ASL code is generally categorized into one of the modules listed below:

  • System Agent ASL Code This module contains the ASL files for the System Agent Host Bridge and the bridges/devices inside it. All ASL files for System Agent are included in the System Agent Reference Code package. HOST_BUS.ASL: Defines various Kabylake System Agent PCI Configuration Space registers which will be used to dynamically produce all resources in the Host Bus. SA.ASL: Currently defines the device objects for the PCI Express* Graphics bridge and port, and IGD. INTELGFX.ASL: Defines the methods to enable/disable output switching, store display switching and LCD brightness BIOS control and return valid addresses for all display device encoders present in the system, etc. IgdOpRn.ASL: Defines OperationRegions to cover the IGD PCI configuration space as described in the IGD OpRegion specification. IgdOGBDA.ASL: This file contains Get BIOS Data Area function support for the IGD OpRegion/Software SCI mechanism. IgdOMOBF.ASL: This file contains ASL code for handling the events, i.e. hotkeys and other system interrupts. IgdOSBCB.ASL: This file contains the system BIOS call back functionality for the OpRegion/Software SCI mechanism
  • PCH ASL Code This module contains the definitions for the OperationRegions for accesses to the PCH and the methods to use it. All ASL files for the PCH are included in the PCH Reference Code package. PCH.ASL: Defines the OperationRegions for the accesses to the registers inside PCH, and PCH!|s internal devices. PchAudio.ASL: Defines the OperationRegion for the accesses to HDA controller. PchPcie.ASL: Defines the OperationRegion for the accesses to PCI Express Root Bridge registers. PchSmb.ASL: Defines the OperationRegion for the accesses to SMBus PCI Configuration Space and I/O mapped registers, and the methods to execute various SMBus transactions.
  • CPU ASL Code This module contains the tables, methods, P-state, C-state and T-state support. These will be dynamically loaded according to OS CPU driver capabilities. All CPU ASL files are included in the CPU Reference Code package. Cpu0Cst.ASL/ApCst.ASL: Defines _CST method for all processors to publish C-State capability. Cpu0Ist.ASL/ApIst.ASL: Defines _PPC, _PCT, _PSS method for all processors to publish P-State capabilities. Cpu0Tst.ASL/ApTst.ASL: Defines _TPC, _PTC, _TSS, _TSD method for all processors to publish T-State capabilities. CpuPm.ASL: Defines the methods to get the information for properly initializing tables and dynamically loading them.
  • Platform ASL Code This module contains all platform-related ACPI name spaces and methods. All Platform ASL files are in this Platform Sample package, of which most of the Differentiated System Description Table (DSDT) consists. The following sections will introduce all of ASL files in this package top-to-down in hierarchy. !V DSDT.ASL:This file makes up all components into most of the DSDT, which contains information and descriptions for various system features. Additionally, this file also contains power management packages that defines system _S0, _S1, _S3, _S4 and _S5 state mode. The ASL files listed below are included into this file to compose the whole DSDT.
    • Amlupd.asl
    • PlatformNvs.asl
    • PCItree.asl
    • Platform.asl
    • CPU.asl
    • Thermal.asl
    • PCI_DRC.asl
    • Video.asl
    • Gpe.asl
    • PCIEDOCK.asl
    • Pch.asl: Not in this package. Refer to the PCH Reference Code
    • Sa.asl: Not in this package. Refer to the SA Reference Code
      • Note: _S0 and _S5 are mandatory system states.

Globally-Used Data

  • AmlUpd.ASL: Defines the namespaces for the support of system states.
  • PlatformNvs.ASL: Define a Global region of ACPI NVS Region that may be used for any type of implementation. The starting offset and size will be fixed up by the System BIOS during POST.

PciTree.ASL: This conducts the whole system bus (_SB), starting with PCI Host Bridge Bus hierarchy (_PCI0), incorporating all devices resident in bus 0. This may make references to others ASL files located over other reference code packages, e.g. HOST_BUS.ASL in System Agent Reference Code package. Additionally, this also defines the namespaces for the possible resources (_PRS) for LINKA/B/C/D/E/F/G/H and for routing information (_PRT)

  • Cpu.ASL: The definitions of processor methods for all logical processors under _PR
  • Gpe.ASL: This ASL file contains most of General-Purpose Events methods (_Lxx).
  • LpcB.asl: Defines the OperationRegions for PIRQx Routing Control Registers, I/O Decode Ranges Register, RCBA and Keyboard Controller I/O ports; declares PS/2 keyboard and mouse device. In addition, this drags in the ASL files of the devices resident in LPC bus.
  • EC.ASL: Defines an EC device containing an EC Space and Query Event methods (_Qxx) for handling battery, thermal, docking system, LID, ALS and specific hotkeys; also defines an AC device, a lid switch and power button.
  • Thermal.ASL: Defines two thermal zones: TZ00 and TZ01. The former is for active cooling and the later is for passive cooling. It also defines twoPowerResources: FN00 and FN01, for fan control in active cooling.
  • Super I/O Controllers
    • NAT_COM.ASL/NAT_FDC.ASL/NAT_LPT.ASL/NAT_SIO.ASL: Defines the devices and methods for the National Super I/O controller support.
    • SMSC1000_COM.ASL/SMSC1000_LPT.ASL/SMSC1000_SIO.ASL: Defines the devices and methods for the SMSC1000 Super I/O controller support.
    • SMSC1007_COM.ASL/SMSC1007_SIO.ASL: Defines the devices and methods for the SMSC1007 Super I/O controller support.
    • WPCN381U_COM.asl/WPCN381U_LPT.ASL/WPCN381U_FDC.asl /WPCN381U_SIO.asl: Defines the devices and methods for the Winbond* WPCN381 SuperIO support.
  • PCIEDOCK.ASL: Defines a docking station device with the related control methods, e.g. _EJ0 (a control method that ejects a device; _EJ0 means hot-ejection), _DCK (indicates that this device is a docking station and also controls the isolation logic on the docking connector for docking or undocking), _EDL (returns a packaged list of devices that are dependent on a device.
  • Platform.ASL: Defines some standard methods, e.g. _PIC (for OS to inform the ASL code which interrupt controller is being used, 8259 or APIC), _PTS (Prepare to Sleep, is called when the OS is about to enter a sleep state.), _WAK (is called when the OS is about to wake from sleep state), _INI (is used to determine the OS) and some useful methods for other ASL code!|s use, e.g. P8XH (for port-80 display), GETB (creates then returns a smaller buffer), PNOT (performs all OS-needed notifications during a Power Switch.), TRAP (generates a Mutex protected SMI I/O Trap), NHPG (clears the PCI Express hot-plug SCI enable bits), NPME (clear PCI Express PME SCI enable bits), etc.
  • PCI_DRC.ASL: Defines memory regions for RCRB, MCH BAR, DMI BAR, EP BAR, PCIE BAR Thermal BAR, TTT base address (for TxT), VTD Engine Memory Range, Flash Range, Local APIC Range as Motherboard Resources (PNP0C02). The _BAS, _LEN will be dynamically updated (in _CRS method) to match the real configurations.

ACPI FVI Support

  • This module creates the version information of the ACPI Reference Code, referring to the SMBIOS type 0xDD described in Firmware Version Information (FVI) Interface Specification v0.8

SSDT PTID ASL Code

  • PTID (Power and Temperature Instrumentation) is in an SSDT by design, which is able to dynamically loaded by EFI ACPI Table Protocol.
  • Ptid.ASL: This file contains the code for Thermal Monitoring support for the PTIMon (Power and Temperature Instrumentation Monitor Utility) application to report temperature, power and Fan speed.

Dynamic Platform & Thermal Framework (DPTF)

  • The DPTF reference code is a Framework compliant DXE driver that consists of two main components: 1.DPTF device initialization 2.ACPI SSDT tables It does all the DPTF specific initializations and loads the ACPI tables which provide the AML code to control the various thermal components. DPTF is Intel!|s implementation of the ACPI 5.0 Thermal model. Following are the main features supported by the SSDT tables:
    • Support multiple thermal device components within a single Thermal Zone
    • Device components contain embedded temperature sensors and cooling controls (passive and/or active)
    • Device components expose thermal trip points
    • Device thermal interfaces exposed via device!|s driver The Intel DPTF Thermal Zone has various ACPI objects:
    • Participant device objects like CPU, Memory, Fan and on board sensors (called Generic participant devices)
    • Thermal Objects like PATC, PATx, GTSH, _SCP All these objects are described in detail in the IntelU+00AE Dynamic Platform & Thermal Framework 7.0 BIOS Writer!|s Guide Version.

  • DPTF SSDT The DPTF reference code for Kabylake is loaded in one SSDT by the DXE driver in Dptf.c. All ASL files will be included in Dptf.asl, which is the SSDT file.

    Participants (devices) can be exposed or hidden via the ACPI status method (_STA). Each participant is contained in its own ASL file. The file name format is DeviceParticipant.asl.

    Policies (methods and data structures) can be exposed or hidden by conditionally returning the GUID!|s in the IDSP method. Each policy is contained in its own ASL file. The file name format is DeviceNamePolicy.asl

    Additionally, platforms can be customized by simply removing the unwanted include files from Dptf.asl.

    • Dptf.ASL: The main ASL file with IDSP, _OSC and utility methods. All other files are included here. Customer can remove features here.
    • Art.ASL: Active cooling table for customer modification.
    • Ertm.ASL: Participant list for customer modification.
    • Trt.ASL: Thermal relationship table for customer modification.
    • Dppm.ASL: Guids for Active, Passive, Critical and Cooling mode policies.
    • B0D4Participant.ASL: System agent device.
    • B0D4CtdpPolicy.ASL: CTDP policy.
    • B0D4LpmPolicy.ASL: LPM policy.
    • B0D4DppmPolicy.ASL: DPPM policy.
    • TcpuParticipant.ASL: CPU device for ATOM. This will not be used if B0D4 device is used.
    • TcpuDppmPolicy.ASL: DPPM policy.
    • TpchParticipant.ASL: PCH device.
    • TpchDppmPolicy.ASL: DPPM policy.
    • TAmbParticipant.ASL: Ambient sensor device.
    • TAmbDppmPolicy.ASL: DPPM policy.
    • TEfnParticipant.ASL: Exhaust fan device.
    • TEfnDppmPolicy.ASL: DPPM policy.
    • TFN1Participant.ASL: Fan 1 device.
    • TFN2Participant.ASL: Fan 2 device.
    • TMemParticipant.ASL: Memory device.
    • TMemDppmPolicy.ASL: DPPM policy.
    • TSknParticipant.ASL: Skin temperature sensor.
    • TSknDppmPolicy.ASL: DPPM policy.
    • T_VRParticipant.ASL: Voltage regulator temperature sensor.
    • T_VRDppmPolicy.ASL: DPPM policy.

Miscellaneous ASL Code

Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.1.2 - Rationale

  • 2 - Platform Sample Module
  • 2.1 - ACPI
2.1.2 - Rationale

The Platform Sample code was designed with the ease of customization and integration as a primary goal. Organizing code in individual functional directories and consolidating all the chipset code in a chipset module were the approaches adopted to achieve this.


IceLake Platform Sample Code: 2.1.3 - Requirements

  • 2 - Platform Sample Module
  • 2.1 - ACPI
2.1.3 - Requirements
  • Framework compliant
    • ASL code build with iASL.exe vesion 20130927
    • Build with EDKII code base with specific module revision
    • Compliant to the UEFI 2.1 specification (where appropriate)
    • Compliant to the Framework 0.9x specifications
    • Compliant to VS2012 compiler
  • Easily portable to different Framework-compliant code bases utilizing the EDK
  • Easily portable to different platforms
  • Able to support Client platforms (Mobile and Desktop) with the same code


IceLake Platform Sample Code: 2.1.4 - API

  • 2 - Platform Sample Module
  • 2.1 - ACPI
2.1.4 - API
  • 3.1 ACPI Platform Policy Protocol
    _ACPI_PLATFORM_POLICY_PROTOCOL

  • 3.2 ACPI Info Protocol
    _ACPI_INFO_PROTOCOL

    Note
    This is an Output from reference Code
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.1.5 - Build Flags

  • 2 - Platform Sample Module
  • 2.1 - ACPI
2.1.5 - Build Flags
The following build flags are used for enabling or disabling features/Configurations.
  • MDEPKG_NDEBUG TRUE
  • EFI_S3_RESUME TRUE


IceLake Platform Sample Code: 2.1.6 - MiscInfo

  • 2 - Platform Sample Module
  • 2.1 - ACPI
2.1.6 - MiscInfo
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 3 - Royal Park Platform Override (RPPO)

3 - Royal Park Platform Override (RPPO)

Royal Park Platform Override tags (RPPO-XXX-XXXX) document issues that a Platform team has resolved with an override of Royal Park.

The Active RPPO table lists every issue which is currently resolved with an override. It is a catalog of all such existing overrides.

The Retired RPPO table lists issues which previously required such overrides. It is purely historical as these overrides have all been deleted (are no longer needed).

Active RPPO-ICLs
in IceLakePlatSamplePkg/Override
Tag | Client HSD | BP HSD | Status / Planned EOL | Area | Description
RPPO-SKL-0002 | 1205700453 |  |  | PLATFORM | ASSERT if use third-party AHCI whose port number exceed 3.
RPPO-SKL-0003 | 1205953088 |  |  | PLATFORM | AhciMode.c spend 10ms on each un-plugged port.
RPPO-SKL-0004 | 1206090050 |  |  | PLATFORM | Marvell 9182 AHCI controller can't drive up in native UEFI mode.
RPPO-SKL-0015 | 1206352998 |  |  | SECURITY | NEWCENTURY_STS SMI causes hang in SKL Bios
RPPO-SKL-0026 | 1404331317 |  |  | PLATFORM | HSTI optimization platform driver is not present in SKL/KBL causing 600+ ms of extra post time
RPPO-SKL-0033 | 1504083754 |  |  | CORE | Override FCE tools in KBL stream to resolve long delay during build process
RPPO-KBL-0043 | 1206371435 |  |  | CORE | Add GCC Support to Kabylake BIOS
RPPO-CNL-0042 | 1404702096 |  |  | PCH | UFS command timeout is set too high in V26 BIOS
RPPO-KBL-0069 | 1208882263 |  |  | SECURITY | ME HFSTS resgisters change based on power source and causes inconsistent TPM measurements.
RPPO-CNL-0052 | 1209012154 |  |  | PLATFORM | Enable Catalog Build in one tree KBL tip
RPPO-CNL-0053 | 1604228165 |  |  | PCH | [CNL-Z0 RVP UFS] UFS is detecting in the BIOS, unable to boot and install OS
RPPO-CNL-0061 | 1604324896 |  |  | PLATFORM | [CNL U1] Adding support for USB 3.1 Gen2 device detection (superspeedplus). XHCI Spec update is needed to remove this Override.
RPPO-CNL-0062 | 220151832 |  |  | SECURITY | [CFL43e-CNP] - TXT fails to launch on CFL43e/CNP
RPPO-CNL-0065 | 1604351459 |  |  | CORE | SPI DTPM 2.0 not enumerating in TPM management console and Device manager
RPPO-ICL-0002 | 220512590 |  |  | CORE | Preserve descriptors across call to PciGetBusRange

Retired RPPOs
formerly in IcelakePlatSamplePkg/Override
Tag | Client HSD | BP HSD | Status / Planned EOL | Area | Description
RPPO-ICL-xxxx |  |  |  |  |
RPPO-ICL-0001 | 1604288624 |  |  | SHELL | Reporting Incorrect data in Type 0, 2,3 and 10
RPPO-KBL-0038 | 1207163253 |  |  | PLATFORM | System boots to EFI after flashing new SPI image
RPPO-CNL-0063 | 1405865867 |  |  | PCH | UFS Should be checking for UFS_DEVICE_PATH not SCSI_DEVICE_PATH
RPPO-CNL-0064 | 220190201 |  |  | CORE | [CNL]ASSERT in CNL Debug Performance Build with UDK2017 RC3


IceLake Platform Sample Code: 4 - RoyalPark & PlatSamplePkg build Integration Guide

4 - RoyalPark & PlatSamplePkg build Integration Guide

When building SiPkg/SiBinPkg with RoyalPark and PlatSamplePkg please follow below steps:

  1. Restrieve RoyalPark, KabylakePlatSamplePkg and all required binary/tool files (LINK16.EXE, BpmGen, FitGem, VBIOS, Microcode and GOP...). Or you may exclude those binary files in FDF file if not required
    Summary of build switches in PlatformPkgConfig.dsc for optional feature/process and Binary files including/excluding as below:
    #
    # PCDs consumed by DSC and FDF for optional feature
    #

    PCDs consumed by DSC and FDF for Optional Feature (with default setting) | DESCRIPTION
    gPlatformModuleTokenSpaceGuid.PcdUnitoolEnable|TRUE | Execute or not for KabylakePlatSamplePkg\Tools\UniTool\UniTool.bat
    gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE | Enable or not for ACPI feature
    gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE | Enable or not for S3 feature
    gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE | Enable or not for SMBIOS support
    gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE | Enable or not for SATA ATA feature
    gPlatformModuleTokenSpaceGuid.PcdGopConfigBin|TRUE | Include or exclude GopCofigBin which is for external code base to boot IGFX on RVP/CRB platforms only

    #
    # PCDs consumed by DSC or FDF for bin files.
    #

    PCDs consumed by DSC or FDF for BIN files (with default setting) | DESCRIPTION
    gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable|TRUE | #pubkeyhash.bin
    gPlatformModuleTokenSpaceGuid.PcdStartupAcmBinEnable|TRUE | #StartupAcm.bin
    gPlatformModuleTokenSpaceGuid.PcdBiosAcmBinEnable|TRUE | #BiosAc.bin
    gPlatformModuleTokenSpaceGuid.PcdBiosAcProdBinEnable|TRUE | #BiosAcProd.bin
    gPlatformModuleTokenSpaceGuid.PcdReservedFitBinEnable|TRUE | #ReservedFIT.bin
    gPlatformModuleTokenSpaceGuid.PcdCsmLegacy16BinEnable|TRUE | #AmiLegacy16.bin
    gPlatformModuleTokenSpaceGuid.PcdSredirBinEnable|TRUE | #Sredir.bin
    gPlatformModuleTokenSpaceGuid.PcdRsteOromBinEnable|TRUE | #RsteRaidOrom.bin
    gPlatformModuleTokenSpaceGuid.PcdRaidOromBinEnable|TRUE | #RaidOrom.bin
    gPlatformModuleTokenSpaceGuid.PcdAhciOromBinEnable|TRUE | #AHCIOR.BIN
    gPlatformModuleTokenSpaceGuid.PcdPxeUndiOromBinEnable|TRUE | #PxeUndiRom.BIN
    gPlatformModuleTokenSpaceGuid.PcdUi13BinEnable|TRUE | #UI13.bin
    gPlatformModuleTokenSpaceGuid.PcdLegacyVideoRomBinEnable|TRUE | #LegacyVideoRom.bin
    gPlatformModuleTokenSpaceGuid.PcdStmBinEnable|TRUE | #Stm.bin
    gPlatformModuleTokenSpaceGuid.PcdVbtBinEnable|TRUE | #Vbt.bin
    gPlatformModuleTokenSpaceGuid.PcdPsmihandlerBinEnable|TRUE | #PsmiHandler.bin
    gPlatformModuleTokenSpaceGuid.PcdMeBinEnable|TRUE | #Me.bin
    gPlatformModuleTokenSpaceGuid.PcdFcntrlBinEnable|TRUE | #Fcntrl.bin
    gPlatformModuleTokenSpaceGuid.PcdEcBinEnable|TRUE | #ksc.bin
    gPlatformModuleTokenSpaceGuid.PcdEcBgUpBinEnable|TRUE | #KscBGUP.bin
    gPlatformModuleTokenSpaceGuid.PcdBgupCapsuleBinEnable|TRUE | #BGUP_RELEASE_CAPSULE.bin

    #
    # PCDs consumed by DSC or FDF for efi files.
    #

    PCDs consumed by DSC or FDF for EFI files (with default setting) | DESCRIPTION
    gPlatformModuleTokenSpaceGuid.PcdSectionextractiondxeEfiEnable|TRUE | #SectionExtractionDxe.efi
    gPlatformModuleTokenSpaceGuid.PcdFwvoldxeEfiEnable|TRUE | #FwVolDxe.efi
    gPlatformModuleTokenSpaceGuid.PcdFaulttolerantwritedxeEfiEnable|TRUE | #FaultTolerantWriteDxe.efi
    gPlatformModuleTokenSpaceGuid.PcdUpdateDriverDxeEfiEnable|TRUE | #UpdateDriverDxe.efi
    gPlatformModuleTokenSpaceGuid.PcdIccOverClockingBinEnable|TRUE | #IccOverClocking.efi
    gPlatformModuleTokenSpaceGuid.PcdUhcdBinEnable|TRUE | #Uhcd.efi
    gPlatformModuleTokenSpaceGuid.PcdUsbRtBinEnable|TRUE | #UsbRt.efi
    gPlatformModuleTokenSpaceGuid.PcdUsbInt13BinEnable|TRUE | #UsbInt13.efi
    gPlatformModuleTokenSpaceGuid.PcdKbcEmulEfiEnable|TRUE | #KbcEmul.efi & KbcEmulDxe.efi
    gPlatformModuleTokenSpaceGuid.PcdLegacySredirBinEnable|TRUE | #LegacySredir.efi
    gPlatformModuleTokenSpaceGuid.PcdSmmbaseRelocateEfiEnable|TRUE | #SmmBaseRelocate.efi
    gPlatformModuleTokenSpaceGuid.PcdE0001x3EfiEnable|TRUE | #E6023X3.EFI
    gPlatformModuleTokenSpaceGuid.PcdRaidDriverEfiEnable|TRUE | #RaidDriver.efi
    gPlatformModuleTokenSpaceGuid.PcdRsteDriverEfiEnable|TRUE | #SataDriverRste.efi
    gPlatformModuleTokenSpaceGuid.PcdRstNvmeDriverEfiEnable|TRUE | #RstNvmeDriver.efi
    gPlatformModuleTokenSpaceGuid.PcdMebxEfiEnable|TRUE | #Mebx.efi
    gPlatformModuleTokenSpaceGuid.PcdMebxSetupBrowserEnable|TRUE | #MebxSetupBrowser.efi
    gPlatformModuleTokenSpaceGuid.PcdIntelGopDriverEfiEnable|TRUE | #IntelGopDriver.efi
    gPlatformModuleTokenSpaceGuid.PcdUefiShellBuildSource|FALSE | #Shell.efi
    gPlatformModuleTokenSpaceGuid.PcdUsbFnEnable|TRUE | #UsbDeviceDxe.efi

    Summary the paths of all Binary as below, depends on platform design some of them may not be required:

    • BpCommonPkg\Tools\BpmGen\*.*
    • BpCommonPkg\Tools\FitGen\*.*
    • ClientCommonPkg\Tools\LINK16.EXE
    • KabylakePlatSamplePkg\Binaries\Txt\BiosAcm\BiosAc.bin
    • KabylakePlatSamplePkg\Binaries\Txt\BiosAcm\BiosAcProd.bin
    • KabylakePlatSamplePkg\Binaries\BiosGuard\BiosGuardModule.bin
    • KabylakePlatSamplePkg\Binaries\BootGuard\ACM\StartupAcm.bin
    • KabylakePlatSamplePkg\Binaries\Microcode\*.*
    • KabylakePlatSamplePkg\Binaries\LegacyRom\AhciRom\*.*
    • KabylakePlatSamplePkg\Binaries\LegacyRom\RaidRom\*.*
    • KabylakePlatSamplePkg\Binaries\LegacyRom\VideoRom\*.*
    • KabylakePlatSamplePkg\Tools\RomImage\*.*
    • KabylakePlatSamplePkg\Tools\RomImage\Fit\*.*
    • KabylakePlatSamplePkg\Tools\RomImage\KabylakeLP\*.*
    • KabylakePlatSamplePkg\Tools\RomImage\KabylakeH\*.*
    • KabylakePlatSamplePkg\ToolScripts\BpmGen\*.*
    • KabylakePlatSamplePkg\ToolScripts\FitGen\*.*
    • KabylakePlatSamplePkg\ToolScripts\SignFv\*.* (for SignFvPlatform.bat and keys)
    • KabylakePlatSamplePkg\Binaries\UefiDriver\Gop\*.*
    • KabylakePlatSamplePkg\Binaries\UefiDriver\Mebx\*.*
    • KabylakePlatSamplePkg\Binaries\UefiDriver\MebxSetupBrowser\*.*
    • KabylakePlatSamplePkg\Binaries\UefiDriver\Raid\*.*
      Note: If FitGen and BpmGen are not required, please remove the lines in KabylakePlatSamplePkg\postbuild.bat where FitGen and BpmGen called.
  2. Generate Rsa2048Sha256 Private, public PEM key pair and name the file as privkey.pem and pubkey.pem accordingly. Also generate SHA256 hash of public key and include this as RAW file in Firmware volume. Refer pubkeyhash.bin in PlatformPkg.fdf file
  3. Retrieve KabylakeSiliconPkg (for Source code building) and KabylakeSiliconBinPkg (For release built binary)
  4. All KabylakePlatSamplePkg, KabylakeSiliconPkg and KabylakeSiliconBinPkg should be in root of RoyalPark source
  5. For building with SiPkg source code, go to KabylakePlatSamplePkg and type "prep && bld" to compile the whole source code.
  6. For building with SiBinPkg (Release built binary modules), ensure your code tree has KabylakeSiliconBinPkg then go to KabylakePlatSamplePkg folder and execute "BinBuild.bat r" to compile it
    Note: For Binary model, BinBuild.bat actually just renames KabylakeSiliconBinPkg to KabylakeSiliconPkg (original folder will be renamed too) and then set "gPlatformModuleTokenSpaceGuid.PcdSipkgBinaryEnable|FALSE"
    Refer to KabylakePlatSamplePkg\PlatformPkg.fdf for 'gPlatformModuleTokenSpaceGuid.PcdSipkgBinaryEnable' for how to switch between SiPkg source code build and binary build.
  7. The Full BIOS binary (Descriptor/ME FW + BIOS ROM) generated may not boot on the system as the build steps do not cover all of the strap settings.
    Please get working Descriptor/ME FW and combine with BIOS.ROM generated by this build to be a full Binary to boot the system.

Note on BootGuard: BootGuard ACM authenticates IBB which includes FVRecovery, FVRecovery2 and FSP FV (only in FSP wrapper build). With this consideration, it is mandated to Sign FVRecovery3, FVMain and FVMain2. SignedSection driver authenticates all signed FVs before launching it and the chain of trust will be maintained.

Based on the IBB size, BootGuard ACM with release BIOS works on 2MB LLC silicon and BootGuard ACM with both Release/Debug Bioses work on 4MB LLC silicon. This is not a recommendation and 2MB LLC silicon can boot with Debug BIOS too, if the IBB size meets the requirement. Refer to BootGuard BIOS writers guide for more details.


IceLake Platform Sample Code: 5 - MiscInfo

5 - MiscInfo
  1. PlatformInitPreMem module will install some policy functions for MRC to consume and if those functions were not in code cache region MRC will run slowly and impact both boot time and S3 resume time.
    Please ensure this module will be always in code cache coverage (according to cache initialization and adjust this module in flash map)
  2. The Secondary NvRam term can be used to describe CMOS as like in RVP BIOS, but it can be EMMC or some other non-volatile memory other than EFI Variable.


IceLake Platform Sample Code: 6 - Bios Image

6 - Bios Image

0.

Flash Layout

  1. FVMAIN - DXE drivers required to boot platform.
    Driver Name(.inf) | Build Condition
    8259.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    ArpDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    AmtPetAlertDxe.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    AmtSetupDxe.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    AsfTable.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    AmtWrapperDxe.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    AlertStandardFormatDxe.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    ActiveManagement.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    AcpiPlatform.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    AcpiDebug.inf | gPlatformModuleTokenSpaceGuid.PcdAcpiDebugEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    AcpiTables.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    AcpiFvi.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    AcpiTableDxe.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    AtaBusDxe.inf | gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    AtaAtapiPassThru.inf | gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    AmdAcpiTable.inf | gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    AmdAcpiTablePch.inf | gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    AcpiGlobalVariable.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    AcpiS3SaveDxe.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    BootScriptExecutorDxe.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    BootTimeDxe.inf | gPlatformModuleTokenSpaceGuid.PcdBootTimeEnable == TRUE
    BdsDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    BiosExtensionLoader.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    BootManagerMenuApp.inf | gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE
    CapsuleRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    CpuInitDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    CsmPlatformLoader.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    CpuIo2Dxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    CpuAcpiTables.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    ConPlatformDxe.inf | gPlatformModuleTokenSpaceGuid.PcdConSplitterEnable == TRUE
    ConSplitterDxe.inf | gPlatformModuleTokenSpaceGuid.PcdConSplitterEnable == TRUE
    CpuIoDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    DataHubDxe.inf | gPlatformModuleTokenSpaceGuid.PcdDataHubEnable == TRUE
    Dhcp4Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    DpcDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    DatahubStatusCodeHandlerDxe.inf | gPlatformModuleTokenSpaceGuid.PcdDataHubStatusCodeEnable == TRUE
    Dhcp6Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    DptfAcpiTables.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    DptfAcpiTablesSds.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    DisplayEngineDxe.inf | gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE
    Dptf.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    DxeOverClock.inf | gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE
    DriverHealthManagerDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    DiskIoDxe.inf | gPlatformModuleTokenSpaceGuid.PcdFatEnable == TRUE
    EbcDxe.inf | gPlatformModuleTokenSpaceGuid.PcdEbcEnable == TRUE
    EmuVariableRuntimeDxe.inf | gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == FALSE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    E0001X3.EFI | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdE0001x3EfiEnable == TRUE
    EnglishDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUnicodeCollectionEnable == TRUE
    EhciDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE
    EC.inf | gPlatformModuleTokenSpaceGuid.PcdEcEnable == TRUE
    EmuVariableRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == FALSE
    FaultTolerantWriteDummy.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == FALSE
    FaultTolerantWriteSmm.inf | gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE
    FaultTolerantWriteDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    Fat.efi | gPlatformModuleTokenSpaceGuid.PcdFatEnable == TRUE
    GopPolicy.inf | gSiPkgTokenSpaceGuid.PcdIgdEnable == TRUE
    GopConfig.efi | gSiPkgTokenSpaceGuid.PcdIgdEnable == TRUE
    GfxInt15Legacy.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIgdIntHookEnable == TRUE
    GuidForwardHandlerSmm.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    GuidForwardHandlerRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    GraphicsConsoleDxe.inf | gPlatformModuleTokenSpaceGuid.PcdGraphicsConsoleEnable == TRUE
    GenericMemoryTestDxe.inf | gPlatformModuleTokenSpaceGuid.PcdMemoryTestEnable == TRUE
    HddPasswordDxe.inf | gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    HddPasswordSmm.inf | gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    HitachH8s2113.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    HpetTimerDxe.inf | gSiPkgTokenSpaceGuid.PcdUseHpetTimer == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    HiiDatabaseDxe.inf | gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE
    HeciInit.inf | gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    IntegratedTouch.inf | gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable == TRUE && gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    IrqBoardInfoRvpM.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    IrqBoardInfoRvpDt.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    IrqBoardInfoSvM.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    IrqBoardInfoSv.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    I2cDxe.inf | gPlatformModuleTokenSpaceGuid.PcdPiI2cStackEnable == TRUE
    I2cPlatformDxe.inf | gPlatformModuleTokenSpaceGuid.PcdPiI2cStackEnable == TRUE
    I2cMasterDxe.inf | gPlatformModuleTokenSpaceGuid.PcdPiI2cStackEnable == TRUE
    IntelUefiRaidDiskInfo.inf | gPlatformModuleTokenSpaceGuid.PcdIntelRaidEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    IsaIoDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    IsaSerialDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTerminalEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == FALSE
    IntelGopDriver.efi | gPlatformModuleTokenSpaceGuid.PcdIntelGopDriverEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdIgdEnable == TRUE
    IccPlatformDxe.inf | gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    IsvtCheckpointDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    IrqBoardInfo.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    IrqBoardInfoRvp.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    IsaAcpi.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    IsaBusDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    IccOverClocking.efi | gPlatformModuleTokenSpaceGuid.PcdIccOverClockingBinEnable == TRUE && gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    Ip4Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    Ip4ConfigDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    Ip6Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    IpSecDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    IScsiDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIscsiEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    JpegDecoderDxe.inf | gPlatformModuleTokenSpaceGuid.PcdJpgEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE
    JhiDxe.inf | gSiPkgTokenSpaceGuid.PcdJhiEnable == TRUE
    KeyboardDxe.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    LpcSmsc100x.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    MnpDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    Mebx.efi | gPlatformModuleTokenSpaceGuid.PcdMebxEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    MebxSetupBrowser.efi | gPlatformModuleTokenSpaceGuid.PcdMebxSetupBrowserEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    MeSsdt.inf | gSiPkgTokenSpaceGuid.PcdPttEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    Metronome.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    MonotonicCounterRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    MeUlvCheckDxe.inf | gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    Mtftp4Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    Mtftp6Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    MeSmbiosDxe.inf | gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE && gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    MePlatformReset.inf | gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    MeFwDowngrade.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    NvidiaAcpiTable.inf | gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    NvidiaAcpiTablePch.inf | gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    NationalPC8374L.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    NullMemoryTestDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    NullMemoryTestDxe.inf | gPlatformModuleTokenSpaceGuid.PcdMemoryTestEnable == FALSE
    OpalPasswordDxe.inf | gPlatformModuleTokenSpaceGuid.PcdOpalPasswordEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    OpalPasswordSmm.inf | gPlatformModuleTokenSpaceGuid.PcdOpalPasswordEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    OverclockInterfaceACPI.inf | gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE
    OverClockSmiHandler.inf | gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE
    OverclockInterface.inf | gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE
    Pcd.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PlatformInfoDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PchResetRuntime.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PolicyInitDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PlatformInitDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PcatRealTimeClockRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PlatformFixedPciResource.inf | gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PciRootBridgeNoEnumeration.inf | gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PciHostBridge.inf | gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == FALSE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PlatformSetup.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PchInitDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PciPlatform.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PciBusNoEnumeration.inf | gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PciBusDxe.inf | gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == FALSE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    PlatformStatusCodeHandlerSmm.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PlatformPort80HandlerSmm.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PwdCredentialProviderDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE
    PowerMgmtDxe.inf | gSiPkgTokenSpaceGuid.PcdPpmEnable == TRUE
    PowerMgmtSmm.inf | gSiPkgTokenSpaceGuid.PcdPpmEnable == TRUE
    PchSmbusDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PchSmiDispatcher.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PchSpiRuntime.inf | gSiPkgTokenSpaceGuid.PcdSleEnable==FALSE
    PchSpiSmm.inf | gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE
    PchInitSmm.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PciHotPlug.inf | gPlatformModuleTokenSpaceGuid.PcdPciHotplugEnable == TRUE
    PepBccdSmm.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    PartitionDxe.inf | gPlatformModuleTokenSpaceGuid.PcdFatEnable == TRUE
    PlatformPrivateSmm.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PlatformPrivateDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PchSvSbDxeLate.inf | gSiPkgTokenSpaceGuid.PcdSvBuild == TRUE
    PchSvSbSmiLate.inf | gSiPkgTokenSpaceGuid.PcdSvBuild == TRUE
    PciBusNoEnumeration.inf | gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE
    Ps2keyboardDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    PiSmmCommunicationSmm.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    PttHciSmm.inf | gSiPkgTokenSpaceGuid.PcdPttEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    Ps2MouseDxe.inf | gPlatformModuleTokenSpaceGuid.PcdMouseEnable == TRUE
    RaidDriver.efi | gPlatformModuleTokenSpaceGuid.PcdRaidDriverEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    RstNvmeDriver.efi | gPlatformModuleTokenSpaceGuid.PcdNvmeEnable == TRUE
    ReportStatusCodeRouterRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    RuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    SmmControl.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    SiInitDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    SecurityStubDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    SmmAccess.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    SaInitDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    SmmSvDispatcher.efi | gPlatformModuleTokenSpaceGuid.PcdSmmSvDispatcherEfiEnable == TRUE
    SecureBootConfigDxe.inf | gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
    SpcrAcpiDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTerminalEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == FALSE
    SnpDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    SaAcpiTables.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    SmbiosMiscDxe.inf | gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
    SataController.inf | gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    SpiFvbServiceDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    SpiFvbServiceSmm.inf | gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    SerialOverLan.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    SgAcpiTables.inf | gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE
    SgAcpiTablesPch.inf | gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE
    SaveMemoryConfig.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    SavePegConfig.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    Setup.inf | gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE
    SmmPlatform.inf | gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
    SmmProfileSmi.inf | gPlatformModuleTokenSpaceGuid.PcdSmmProfileEnable == TRUE
    SmramSaveInfoHandlerSmm.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    SimpleBootFlag.inf | gPlatformModuleTokenSpaceGuid.PcdSimpleBootFlagEnable == TRUE
    SecureEraseDxe.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    SmiVariable.inf | gPlatformModuleTokenSpaceGuid.PcdSmiVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    SmiVariableInt15.inf | gPlatformModuleTokenSpaceGuid.PcdSmiVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    SmiVariableInstallInt15Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdSmiVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    SataDriverRste.efi | gPlatformModuleTokenSpaceGuid.PcdRsteDriverEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE
    SaSsdt.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    SetupBrowserDxe.inf | gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE
    SmbiosDxe.inf | gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
    ScsiBusDxe.inf | gPlatformModuleTokenSpaceGuid.PcdScsiEnable == TRUE
    ScsiDiskDxe.inf | gPlatformModuleTokenSpaceGuid.PcdScsiEnable == TRUE
    S3SaveStateDxe.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    SmmS3SaveState.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    SmmLockBox.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
    SmmThunk.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdSmmThunkEnable == TRUE
    TcgConfigDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TcgMor.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TrEEDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TrEESmm.inf | gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TrEEConfigDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TrEEPlatformDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TcgDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TcgSmm.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TcgSetupDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TraceHubStatusCodeHandlerSmm.inf | gSiPkgTokenSpaceGuid.PcdTraceHubEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    TcpDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    Tcp4Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == FALSE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    TxtDxe.inf | gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE
    TerminalDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTerminalEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == FALSE
    I2cTouchPanelDxe.inf | gPlatformModuleTokenSpaceGuid.PcdI2cTouchDriverEnable == TRUE
    Tpm2AcpiTables.inf | gSiPkgTokenSpaceGuid.PcdPttEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    TxtSmm.inf | gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdStmEnable == TRUE
    TxtAcpiTables.inf | gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdStmEnable == TRUE
    TbtDxe.inf | gPlatformModuleTokenSpaceGuid.PcdTbtEnable == TRUE
    TbtSmm.inf | gPlatformModuleTokenSpaceGuid.PcdTbtEnable == TRUE
    TraceHubStatusCodeHandlerRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdTraceHubEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    UiApp.inf | gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE
    UserIdentifyManagerDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE
    UserProfileManagerDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE
    UsbCredentialProviderDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE
    Udp6Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    UsbTypeC.inf | gPlatformModuleTokenSpaceGuid.PcdUsbTypeCEnable == TRUE
    UhciDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE
    UsbBusDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE
    UsbKbDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE
    UsbMassStorageDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE
    UsbMouseDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE
    UsbDeviceDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbFnEnable == TRUE
    Udp4Dxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    VariableSmmRuntimeDxe.inf | gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE
    VariableSmm.inf | gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE
    VlanConfigDxe.inf | gPlatformModuleTokenSpaceGuid.PcdNetworkVlanEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE
    VirtualKeyboardDxe.inf | gPlatformModuleTokenSpaceGuid.PcdVirtualKeyboardEnable == TRUE
    WdtAppDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    WinbondWpcn381u.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    WatchdogTimer.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    WdtDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
    XhciDxe.inf | gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE
  2. FVMAIN2 - DXE drivers for optional features (like CSM legacy support, Overclocking etc.. this will be decompressed and dispatched only when these features are enabled to improve responsiveness.)
    Driver Name(.inf) | Build Condition
    AmiLegacyBiosHook.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    AmtInt16.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    AmtInt16Csm.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE
    BlockIoDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    GfxInt15Legacy.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIgdIntHookEnable == TRUE
    IrqTableInfo.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    IntelRaidAtaAtapiPassThru.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIntelRaidEnable == TRUE
    IntelRaidBiosThunk.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIntelRaidEnable == TRUE
    LegacyInterrupt.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    LegacyBiosPlatform.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    LegacyBiosDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE
    LegacyInterruptHook.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    MeUlvCheckDxe.inf | gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE
    MinUefiShell.inf | gPlatformModuleTokenSpaceGuid.PcdUefiMiniShellEnable == TRUE
    Shell.efi | (Build mode:DEBUG)gPlatformModuleTokenSpaceGuid.PcdUefiShellEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdUefiShellBuildSource == TRUE
    TcgLegacy.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TcgLegacyInstallInt1A.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    TcgLegacy16.inf | gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
    VideoDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
    VgaClassDxe.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE
  3. FVRECOVERY - SEC phase (keep this separate so that we can place TxtPei in the top 128K of the Flash)
    Driver Name(.inf) | Build Condition
    FspWrapperReportFv.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    Pcd.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    ReportFvRecoveryPei.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    SecCore.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    SecCoreFsp.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    TxtPeiAp.inf | gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
  4. FVRECOVERY2 - PeiMain/MRC/SiInit/BoardInit/PlatformInit (pre memory modules which is uncompressed)
    Driver Name(.inf) | Build Condition
    AmtStatusCodePei.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    AmtStatusCodePei.inf | gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    BiosInfoChecker.inf | gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    BiosInfo.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    CpuIoPei.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    CapsulePei.inf | gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    CapsuleX64.inf | gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    CodeCoveragePeiBin.inf | gPlatformModuleTokenSpaceGuid.PcdCodeCoverageEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    CmosAccessPei.inf | (Build mode:DEBUG)gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    DxeIpl.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    DebugServicePei.inf | (Build mode:DEBUG)gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    FaultTolerantWritePei.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    FirmwarePerformancePei.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    FpdtPei.inf | gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PlatformStatusCodeHandlerPei.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PlatformPort80HandlerPei.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PcatSingleSegmentPciCfg2Pei.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    Pcd.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PlatformInitPreMem.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PhysicalPresencePei.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PeiOverClock.inf | gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PiSmmCommunicationPei.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    SignedSectionPei.inf | gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    SiInitPreMem.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    S3Resume2Pei.inf | gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    TraceHubStatusCodeHandlerPei.inf | gSiPkgTokenSpaceGuid.PcdTraceHubEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    TrEEConfigPei.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    TrEEPei.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    TcgPei.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    VariablePei.inf | gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
  5. FVRECOVERY3 - PEI drivers which can be compressed (these are post-memory modules not in CAR range)
    Driver Name(.inf) | Build Condition
    CapsulePei.inf | gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    CapsuleX64.inf | gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    DxeIpl.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    FaultTolerantWritePei.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    FspWrapperInit.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    FspWrapperPeim.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    IntelGraphicsPeim.efi | gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PlatformInit.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE
    PlatformInitPreMem.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    PhysicalPresencePei.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    SignedSectionPei.inf | gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    TrEEConfigPei.inf | gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    TrEEPei.inf | gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
    TcgPei.inf | gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
  6. BiosGuardModuleFv - Bios Guard binary module (technical this could be generic binaries FV or part of FV_Recovery2 or 3).
    # TXT ACM and BootGuard ACM will be moved out of FVRecovery2 into BiosGuardModuleFV and rename it to FV_BINARIES.
  7. FvFSP - FSP binary (this can be split into three separate FVs FSP-T, FSP-M and FSP-S as these can be placed in different regions of flash part).
  8. Note -
    # multiple Recovery FV design is to maintain flexibility to manage platforms with different LLC size.
    # BootGuard IBB = FVRecovery + FvFSP + FvRecovery2. To maintain the chain of trust, FvRecovery3, FvMain and FvMain2 firmware volumes need to be signed and authenticated during UEFI Bios boot.


IceLake Platform Sample Code: 7 - Power Button Override

7 - Power Button Override

Both pre-OS & OS via PCH register programming are enabled 10 seconds override feature but It's not easy to observe in pre-OS phase,
because in pre-OS phase Power Button SMI will be triggered first with system shutdown before 10 seconds override timer expiration.

1) Under UEFI Shell : Upon power button press, system goes to shutdown state immediately.
2) Under OS: Upon power button press, OS will perform actions according to OS design (ex: user confirmation with a few seconds of power button pressing);
Until 10 seconds after power button keeping pressed, system goes to shutdown state.


IceLake Platform Sample Code: 8 - Post Code

8 - Post Code
  • Post code format aligns to Silicon definition Actual Post code displayed will be 16 bits(4 Bytes). Upper 4 bits will be added by Base PostCode Library(either by FSP or EDKII).
    Example : Let's assume Post code as 0xWXYZ
  • Update for platform code
    XYZ is added by component
    W indicate the phase BIOS is running. 0: SEC/PEI; 1: DXE

    Post Code
    Post Code | Progress Code | Description
    0x10 | PEI_CORE_STARTED | Stared Core
    0x11 | PEI_CAR_CPU_INIT | Init Car CPU
    0x1D | PEI_MEMORY_SPD_READ | Read SPD Memory
    0x1E | PEI_MEMORY_PRESENCE_DETECT | Detect Memory Presence
    0x1F | PEI_MEMORY_TIMING | Memory Timing
    0x20 | PEI_MEMORY_CONFIGURING | Memory Configuring
    0x21 | PEI_MEMORY_INIT | Init Memory
    0x31 | PEI_MEMORY_INSTALLED | Installed Memory
    0x32 | PEI_CPU_INIT | CPU Init
    0x33 | PEI_CPU_CACHE_INIT | Init CPU Cache
    0x34 | PEI_CPU_BSP_SELECT | Select CPU BSP
    0x35 | PEI_CPU_AP_INIT | Init CPU AP
    0x36 | PEI_CPU_SMM_INIT | Init CPU SMM
    0x37 | PEI_MEM_NB_INIT | Init Memory NB
    0x3B | PEI_MEM_SB_INIT | Init Memory SB
    0x4F | PEI_DXE_IPL_STARTED | Started PEI DXE IPL
    0xF0 | PEI_RECOVERY_AUTO | Auto Recovery
    0xF1 | PEI_RECOVERY_USER | User Recovery
    0xF2 | PEI_RECOVERY_STARTED | Started Recovery
    0xF3 | PEI_RECOVERY_CAPSULE_FOUND | Found Recovery Capsule
    0xF4 | PEI_RECOVERY_CAPSULE_LOADED | Loaded Recovery Capsule
    0xE0 | PEI_S3_STARTED | Start S3
    0xE1 | PEI_S3_BOOT_SCRIPT | S3 Boot Script
    0xE2 | PEI_S3_VIDEO_REPOST | Repost S3 Video
    0xE3 | PEI_S3_OS_WAKE | Wake S3 OS
    0x1060 | DXE_CORE_STARTED | Started Core
    0x1062 | DXE_SBRUN_INIT | Init SBRUN
    0x1068 | DXE_NB_HB_INIT | Init NB HB
    0x1069 | DXE_NB_INIT | Init NB
    0x106A | DXE_NB_SMM_INIT | Init NB SMM
    0x1070 | DXE_SB_INIT | SInit SB
    0x1071 | DXE_SB_SMM_INIT | Init SB SMM
    0x1072 | DXE_SB_DEVICES_INIT | Init SB Device
    0x1090 | DXE_BDS_STARTED | Started BDS
    0x1092 | DXE_PCI_BUS_BEGIN | Begin PCI BUS
    0x1093 | DXE_PCI_BUS_HPC_INIT | Init HPC BUS
    0x1094 | DXE_PCI_BUS_ENUM | Enum PCI BUS
    0x1095 | DXE_PCI_BUS_REQUEST_RESOURCES | Request PCI BUS Resources
    0x1096 | DXE_PCI_BUS_ASSIGN_RESOURCES | Assign PCI BUS Resources
    0x1097 | DXE_CON_OUT_CONNECT | CON OUT Connect
    0x1098 | DXE_CON_IN_CONNECT | CON IN Connect
    0x1099 | DXE_SIO_INIT | Init SIO
    0x109A | DXE_USB_BEGIN | Begin USB
    0x109B | DXE_USB_RESET | Reset USB
    0x109C | DXE_USB_DETECT | Detect USB
    0x109D | DXE_USB_ENABLE | Enable USB
    0x10A1 | DXE_IDE_BEGIN | Begin IDE
    0x10A2 | DXE_IDE_RESET | Reset IDE
    0x10A3 | DXE_IDE_DETECT | Detect IDE
    0x10A4 | DXE_IDE_ENABLE | Enable IDE
    0x10A5 | DXE_SCSI_BEGIN | Begin SCSI
    0x10A6 | DXE_SCSI_RESET | Reset SCSI
    0x10A7 | DXE_SCSI_DETECT | Detect SCSI
    0x10A8 | DXE_SCSI_ENABLE | Enable SCSI
    0x10AB | DXE_SETUP_START | Start Setup
    0x10AC | DXE_SETUP_INPUT_WAIT | Wait Setup Input
    0x10AD | DXE_READY_TO_BOOT | Ready To Boot
    0x10AE | DXE_LEGACY_BOOT | Legacy Boot
    0x10AF | DXE_EXIT_BOOT_SERVICES | Exit Boot Services
    0x10B0 | RT_SET_VIRTUAL_ADDRESS_MAP_BEGIN | Begin Set RT Virtual Address Map
    0x10B1 | RT_SET_VIRTUAL_ADDRESS_MAP_END | End Set RT Virtual Address Map
    0x10B2 | DXE_LEGACY_OPROM_INIT | Init Legacy OPROM
    0x10B3 | DXE_RESET_SYSTEM | Reset System
    0x10B4 | DXE_USB_HOTPLUG | HotPlug USB
    0x10B5 | DXE_PCI_BUS_HOTPLUG | HotPlug PCI BUS
    0x50 | PEI_MEMORY_INVALID_TYPE | Invalid Memory Type
    0x50 | PEI_MEMORY_INVALID_SPEED | Invalid Memory Speed
    0x51 | PEI_MEMORY_SPD_FAIL | SPD Memory Fail
    0x52 | PEI_MEMORY_INVALID_SIZE | Invalid Memory Size
    0x52 | PEI_MEMORY_MISMATCH | Mismatch Memory
    0x53 | PEI_MEMORY_NOT_DETECTED | Not Detected Memory
    0x53 | PEI_MEMORY_NONE_USEFUL | None Useful Memory
    0x54 | PEI_MEMORY_ERROR | Memory Error
    0x55 | PEI_MEMORY_NOT_INSTALLED | Not Installed Memory
    0x56 | PEI_CPU_INVALID_TYPE | Invalid CPU Type
    0x56 | PEI_CPU_INVALID_SPEED | Invalid CPU Speed
    0x57 | PEI_CPU_MISMATCH | Mismatch CPU
    0x58 | PEI_CPU_SELF_TEST_FAILED | Self CPU Tsst Failed
    0x58 | PEI_CPU_CACHE_ERROR | CPU Cache Error
    0x59 | PEI_CPU_MICROCODE_UPDATE_FAILED | CPU Microcode Update Failed
    0x59 | PEI_CPU_NO_MICROCODE | No CPU Microcode
    0x5A | PEI_CPU_INTERNAL_ERROR | Internal CPU Error
    0x5A | PEI_CPU_ERROR | CPU Error
    0x5B | PEI_RESET_NOT_AVAILABLE | Not Available Reset
    0xF8 | PEI_RECOVERY_PPI_NOT_FOUND | Not Found PPI Recovery
    0xF9 | PEI_RECOVERY_NO_CAPSULE | No Capsule Recovery
    0xFA | PEI_RECOVERY_INVALID_CAPSULE | Invalid Capsule Recovery
    0xE8 | PEI_MEMORY_S3_RESUME_FAILED | Memory S3 Resume Failed
    0xE9 | PEI_S3_RESUME_PPI_NOT_FOUND | S3 Resume PPI Not Found
    0xEA | PEI_S3_BOOT_SCRIPT_ERROR | S3 Boot Script Error
    0xEB | PEI_S3_OS_WAKE_ERROR | S3 OS Wake Error
    0x1058 | DXE_CPU_SELF_TEST_FAILED | Self CPU Test Failed
    0x10D1 | DXE_NB_ERROR | NB Error
    0x10D2 | DXE_SB_ERROR | SB Error
    0x10D3 | DXE_ARCH_PROTOCOL_NOT_AVAILABLE | Not Available ARCH Protocol
    0x10D4 | DXE_PCI_BUS_OUT_OF_RESOURCES | Out of PCI BUS Resources
    0x10D5 | DXE_LEGACY_OPROM_NO_SPACE | No Legacy OPROM Space
    0x10D6 | DXE_NO_CON_OUT | NO CON OUT
    0x10D7 | DXE_NO_CON_IN | NO CON IN
    0x10D8 | DXE_INVALID_PASSWORD | Invalid Password
    0x10D9 | DXE_BOOT_OPTION_LOAD_ERROR | Boot Option Laod Error
    0x10DA | DXE_BOOT_OPTION_FAILED | Boot Option Failed
    0x10DB | DXE_FLASH_UPDATE_FAILED | Falsh Update Failed
    0x10DC | DXE_RESET_NOT_AVAILABLE | Not Available Reset


IceLake Platform Sample Code: Todo List

Todo List
File BasePlatformVariableLib.h
ADD DESCRIPTION
File EcCommands.h
ADD DESCRIPTION
File PeiPlatformLib.h
ADD DESCRIPTION
File PeiReadWriteVariableLib.h
ADD DESCRIPTION
globalScope> Member PlatformInitPreMemEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)

this functionality should be moved to Si Pkg.

it should be moved to Si Pkg.

globalScope> Member UsbcSxEntry (IN OUT UINT8 *DataBuffer)
: it should move to BaseEcAcpiLib once BaseEcAcpiLib has been created.


IceLake Platform Sample Code: Modules

Modules
Here is a list of all modules:
[detail level 123]
MKHI messages Generic Types and Structures | BIOS interacts with Intel ME over Intel ME interface.The MEI(aka HCI)message header is the first dword of any MEI message.It is described with the following C prototype:
BIOS/MRC -ME Kernel Register Based HECI communication | Beginning with the Cougar Point chipset, the ME kernel and BIOS MRC will no longer use MKHI messages to communicate the DRAM INIT status.Instead the MRC will use HECI PCI CFG Space offset 0x4C to send the DRAM INIT message.The FW will then use Host HECI PCI CFG Space offset 0x40 to acknowledge the DRAM init message from BIOS as wells as the biosaction that FW requests of BIOS.Additionally, each processor may have its own requirements for placing ME UMA in the system memory map and these requirements may be found in the specific processor's MRC BIOS Specification
1.1 Resets | Reset System In ME enabled system, ME is running in parallel to the host system
1.2 Manufacturing ME reset and Halt |
1.3 END OF POST |
1.4 Set Debug Memory Address Request |
2.1 Get MKHI Version |
2.2 Get FW Version |
2.3 ME Unconfigure |
2.4 Get and Set ME Rule |
2.5 Get and Set ME Password |
2.6 Get and set ME FW SKU and Capabilities |
2.7 CPU Brand Class Related messages |
2.8 FW Update Messages | HMRFPO_ENABLE Data structure:
2.9 ME MDES Messages |
2.10 ME BIST Messages |
2.12 ME Debug Messages |
▼ Create TCG ComPacket Functions | These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification
▼ Create TCG SubPacket Functions | These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Create TCG Atom Functions | These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Create TCG Sequence Token Functions | These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Create TCG Control Token Functions | These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Parse TCG ComPacket Functions | These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification
Common Create TCG Utility Functions | These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification
Parse TCG ComPacket Utility Functions | These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification


IceLake Platform Sample Code: MKHI messages Generic Types and Structures

MKHI messages Generic Types and Structures

BIOS interacts with Intel ME over Intel ME interface.The MEI(aka HCI)message header is the first dword of any MEI message.It is described with the following C prototype: More...

BIOS interacts with Intel ME over Intel ME interface.The MEI(aka HCI)message header is the first dword of any MEI message.It is described with the following C prototype:

The MKHI message header is defined here _MKHI_MESSAGE_HEADER and consists of the following elements.

  • _CBM_HECI_MSG_HEADER.
    typedef union _MKHI_MESSAGE_HEADER
    {
    // brief DWORD of MKHI header
    uint32_t Data;
    struct
    {
    /// @brief GroupId of MKHI command specific to a client which will process the message.
    uint32_t GroupId :8;
    /// @brief command specific to HECI client.
    uint32_t Command :7;
    /// @brief resonnse from client which requires a client to respond.
    uint32_t IsResponse :1;
    /// @brief reserved bit field.
    uint32_t Reserved :8;
    /// @brief result
    uint32_t Result :8;
    }Fields;
    }MKHI_MESSAGE_HEADER;
    GroupId:8
    Kernel Client specific information for dispatching. Refer to Table in MKHI messages Group ID for
    possible values.
    Command:7
    Command code specific to MEI client.
    IsResponse:
    Set to 1 in response message.
    Result:8
    Result of the request message
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: BIOS/MRC -ME Kernel Register Based HECI communication

BIOS/MRC -ME Kernel Register Based HECI communication

Beginning with the Cougar Point chipset, the ME kernel and BIOS MRC will no longer use MKHI messages to communicate the DRAM INIT status.Instead the MRC will use HECI PCI CFG Space offset 0x4C to send the DRAM INIT message.The FW will then use Host HECI PCI CFG Space offset 0x40 to acknowledge the DRAM init message from BIOS as wells as the biosaction that FW requests of BIOS.Additionally, each processor may have its own requirements for placing ME UMA in the system memory map and these requirements may be found in the specific processor's MRC BIOS Specification. More...

Beginning with the Cougar Point chipset, the ME kernel and BIOS MRC will no longer use MKHI messages to communicate the DRAM INIT status.Instead the MRC will use HECI PCI CFG Space offset 0x4C to send the DRAM INIT message.The FW will then use Host HECI PCI CFG Space offset 0x40 to acknowledge the DRAM init message from BIOS as wells as the biosaction that FW requests of BIOS.Additionally, each processor may have its own requirements for placing ME UMA in the system memory map and these requirements may be found in the specific processor's MRC BIOS Specification.

DRAM INIT request and reponse are defined below.

DRAM INIT REQUEST
Bits Action
31:28 0x01 = DRAM Init Done
27:24 0x00 = Success
0x01 = No Memory in Channels
0x02 = Memory Init Error
0x03 = 0x0F = Reserved
23:16 Reserved
15:0 1M aligned ME UMA base address (maximum address bits supported - 36) This value
is to be read from MESEG_BASE[35:20]
NOTE: 1M alignment is a new requirement for Cougar Point. The Intel 5 Series chipset
is 64K alignment for ME UMA.
DRAM INIT RESPONSE
Bits Action
31:28 BIOS MSG ACK
0x01 = DRAM Init Done ACK
27:25 ACK DATA (ME BIOS Action)
0x00 = No DID Ack received
0x01 = Non-power cycle reset
0x02 = Power cycle reset
0x03 = Go to S3
0x04 = Go to S4
0x05 = Go to S5
0x06 = Global reset
0x07 = Continue to boot
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 1.1 Resets

1.1 Resets

Reset System
In ME enabled system, ME is running in parallel to the host system. More...

Reset System
In ME enabled system, ME is running in parallel to the host system.

Any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if host were to cause a global reset without informing ME and allowing ME to handle it first.

Therefore to maintain appropriate synchronization, following rules must be followed by host system:

  1. If BIOS needs to do Global Reset and either of following is true then it must send the reset request HECI message instead of generating the global reset using CF9 based mechanisms:
                     BIOS is in boot block and ME is in M3.
                 BIOS is in POST (has exited the boot block) and ME f/w status code is
                 initializing or initialized (does not reflect ERROR)
                 MEBx binary is requesting the global reset
  2. If BIOS needs to do a host reset before memory initialization is complete then it must request ME firmware to perform the host reset using messages data structures and commands below.
    Reset Request
    This message is sent by the system BIOS, MEBx binary or host, when it needs to do a global reset in ME enabled system. Note that although this message does support requesting a host only reset, currently there are no known use cases where BIOS would be required to use this message to cause host only reset.
               Response Message Required:   In normal case, No. In case or error, yes
           NOTE: If this message is sent after END_OF_POST message, it is denied and an error
           response is sent


IceLake Platform Sample Code: 1.2 Manufacturing ME reset and Halt

1.2 Manufacturing ME reset and Halt
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 1.3 END OF POST

1.3 END OF POST
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 1.4 Set Debug Memory Address Request

1.4 Set Debug Memory Address Request
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.1 Get MKHI Version

2.1 Get MKHI Version
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.2 Get FW Version

2.2 Get FW Version
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.3 ME Unconfigure

2.3 ME Unconfigure
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.4 Get and Set ME Rule

2.4 Get and Set ME Rule
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.5 Get and Set ME Password

2.5 Get and Set ME Password
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.6 Get and set ME FW SKU and Capabilities

2.6 Get and set ME FW SKU and Capabilities


IceLake Platform Sample Code: 2.7 CPU Brand Class Related messages

2.7 CPU Brand Class Related messages
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.8 FW Update Messages

2.8 FW Update Messages

HMRFPO_ENABLE Data structure: More...

HMRFPO_ENABLE Data structure:

HMRFPO_LOCK_CMD_ACK_STATUS codes:

HMRFPO_LOCK Data structure:

HMRFPO_ENABLE_CMD_ACK_STATUS codes:

  • _FWUPDATE_HMRFPO_ENABLE_DATA
  • _FWUPDATE_HMRFPO_ENABLE
  • _FWUPDATE_HMRFPO_ENABLE_ACK_DATA
  • _FWUPDATE_HMRFPO_ENABLE_ACK
#define HMRFPO_ENABLE_SUCCESS 0
#define HMRFPO_LOCKED 1
#define HMRFPO_NVAR_FAILURE 2
#define HMRFPO_TDT_FAILURE 3
#define HMRFPO_EOP_FAILURE 4
#define HMRFPO_ENABLE_UNKNOWNFAIL 5
  • _FWUPDATE_HMRFPO_LOCK
  • _FWUPDATE_HMRFPO_LOCK_ACK_DATA
  • _FWUPDATE_HMRFPO_LOCK_ACK
#define HMRFPO_LOCK_SUCCESS 0
#define HMRFPO_LOCK_MANUF_MODE_FAIL 1
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.9 ME MDES Messages

2.9 ME MDES Messages
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.10 ME BIST Messages

2.10 ME BIST Messages
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: 2.12 ME Debug Messages

2.12 ME Debug Messages
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Create TCG ComPacket Functions

Modules | Classes | Typedefs | Functions
Create TCG ComPacket Functions

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG ComPacket Functions:

Modules

Create TCG SubPacket Functions
These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Classes

struct _TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...

Typedefs

typedef struct _TcgCreateStruct TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...

Functions

TcgResult TCG_CALL | tcgInitTcgCreateStruct (TcgCreateStruct *createStruct, void *buffer, UINT32 bufferSize)
Required to be called before calling any other Tcg functions with the TcgCreateStruct. More...
TcgResult TCG_CALL | tcgStartComPacket (TcgCreateStruct *createStruct, UINT16 comId, UINT16 comIdExtension)
Encodes the ComPacket header to the data structure. More...
TcgResult TCG_CALL | tcgStartPacket (TcgCreateStruct *createStruct, UINT32 tsn, UINT32 hsn, UINT32 seqNumber, UINT16 ackType, UINT32 ack)
Starts a new ComPacket in the data structure. More...
TcgResult TCG_CALL | tcgStartSubPacket (TcgCreateStruct *createStruct, UINT16 kind)
Starts a new SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndSubPacket (TcgCreateStruct *createStruct)
Ends the current SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndPacket (TcgCreateStruct *createStruct)
Ends the current Packet in the data structure. More...
TcgResult TCG_CALL | tcgEndComPacket (TcgCreateStruct *createStruct, UINT32 *size)
Ends the ComPacket in the data structure and ret. More...

Detailed Description

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Typedef Documentation

typedef struct _TcgCreateStruct TcgCreateStruct

Structure that is used to build the Tcg ComPacket.

It contains the start buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket. This structure must be initialized by calling tcgInitTcgCreateStruct before it is used as parameter to any other Tcg function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgCreateStruct

Function Documentation

TcgResult TCG_CALL tcgEndComPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size
 | ) |  |

Ends the ComPacket in the data structure and ret.

Parameters
[in,out] | createStruct | Structure used to end the Tcg ComPacket
[in,out] | size | Describes the size of the entire ComPacket (header and payload). Filled out by function.
TcgResult TCG_CALL tcgEndPacket ( TcgCreateStruct * createStruct )

Ends the current Packet in the data structure.

Parameters
[in,out] createStruct Structure used to end the current Tcg Packet
TcgResult TCG_CALL tcgEndSubPacket ( TcgCreateStruct * createStruct )

Ends the current SubPacket in the data structure.

This function will also perform the 4-byte padding required for Subpackets.

Parameters
[in,out] createStruct Structure used to end the current Tcg SubPacket
TcgResult TCG_CALL tcgInitTcgCreateStruct | ( | TcgCreateStruct * | createStruct,
 |  | void * | buffer,
 |  | UINT32 | bufferSize
 | ) |  |

Required to be called before calling any other Tcg functions with the TcgCreateStruct.

Initializes the packet variables to NULL. Additionally, the buffer will be memset.

Parameters
[in,out] | createStruct | Structure to initialize
[in] | buffer | Buffer allocated by client of library. It will contain the Tcg encoded packet. This cannot be null.
[in] | bufferSize | Size of buffer provided. It cannot be 0.
TcgResult TCG_CALL tcgStartComPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension
 | ) |  |

Encodes the ComPacket header to the data structure.

Parameters
[in,out] | createStruct | Structure used to build Tcg Compacket
[in] | comId | ComID of the Tcg ComPacket.
[in] | comIdExtension | ComID Extension of the Tcg ComPacket.
TcgResult TCG_CALL tcgStartPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 | tsn,
 |  | UINT32 | hsn,
 |  | UINT32 | seqNumber,
 |  | UINT16 | ackType,
 |  | UINT32 | ack
 | ) |  |

Starts a new ComPacket in the data structure.

Parameters
[in,out] | createStruct | Structure used to add Tcg Packet
[in] | tsn | Packet Tper session number
[in] | hsn | Packet Host session number
[in] | seqNumber | Packet Sequence Number
[in] | ackType | Packet Acknowledge Type
[in] | ack | Packet Acknowledge
TcgResult TCG_CALL tcgStartSubPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT16 | kind
 | ) |  |

Starts a new SubPacket in the data structure.

Parameters
[in,out] | createStruct | Structure used to start Tcg SubPacket
[in] | kind | SubPacket kind


IceLake Platform Sample Code: Create TCG SubPacket Functions

Modules
Create TCG SubPacket Functions
Create TCG ComPacket Functions

These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG SubPacket Functions:

Modules

Create TCG Atom Functions
These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.
Create TCG Sequence Token Functions
These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.
Create TCG Control Token Functions
These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Detailed Description

These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.


IceLake Platform Sample Code: Create TCG Atom Functions

Functions
Create TCG Atom Functions
Create TCG ComPacket Functions » Create TCG SubPacket Functions

These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG Atom Functions:

Functions

TcgResult TCG_CALL | tcgAddRawByte (TcgCreateStruct *createStruct, UINT8 byte)
Adds a single raw token byte to the data structure. More...
TcgResult TCG_CALL | tcgAddByteSequence (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN continued)
Adds the data parameter as a byte sequence to the data structure. More...
TcgResult TCG_CALL | tcgAddInteger (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN signedInteger)
Adds an arbitrary-length integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT8 (TcgCreateStruct *createStruct, UINT8 value)
Adds an 8-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT16 (TcgCreateStruct *createStruct, UINT16 value)
Adds a 16-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT32 (TcgCreateStruct *createStruct, UINT32 value)
Adds a 32-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT64 (TcgCreateStruct *createStruct, UINT64 value)
Adds a 64-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddBOOLEAN (TcgCreateStruct *createStruct, BOOLEAN value)
Adds a BOOLEAN to the data structure. More...
TcgResult TCG_CALL | tcgAddTcgUid (TcgCreateStruct *createStruct, TcgUid uid)
Adds a TcgUid to the data structure. More...

Detailed Description

These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Function Documentation

TcgResult TCG_CALL tcgAddBOOLEAN | ( | TcgCreateStruct * | createStruct,
 |  | BOOLEAN | value
 | ) |  |

Adds a BOOLEAN to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the integer
[in] | value | BOOLEAN value to add
TcgResult TCG_CALL tcgAddByteSequence | ( | TcgCreateStruct * | createStruct,
 |  | const void * | data,
 |  | UINT32 | dataSize,
 |  | BOOLEAN | continued
 | ) |  |

Adds the data parameter as a byte sequence to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the byte sequence
[in] | data | Byte sequence that will be encoded and copied into data structure
[in] | dataSize | Length of data provided
[in] | continued | TRUE if byte sequence is continued or FALSE if the data contains the entire byte sequence to be encoded
TcgResult TCG_CALL tcgAddInteger | ( | TcgCreateStruct * | createStruct,
 |  | const void * | data,
 |  | UINT32 | dataSize,
 |  | BOOLEAN | signedInteger
 | ) |  |

Adds an arbitrary-length integer to the data structure.

The integer will be encoded using the shortest possible atom.

Parameters
[in,out] | createStruct | Structure used to add the integer
[in] | data | Integer in host byte order that will be encoded and copied into data structure
[in] | dataSize | Length in bytes of the data provided
[in] | signedInteger | TRUE if the integer is signed or FALSE if the integer is unsigned
TcgResult TCG_CALL tcgAddRawByte | ( | TcgCreateStruct * | createStruct,
 |  | UINT8 | byte
 | ) |  |

Adds a single raw token byte to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the byte
[in] | byte | Byte to add
TcgResult TCG_CALL tcgAddTcgUid | ( | TcgCreateStruct * | createStruct,
 |  | TcgUid | uid
 | ) |  |

Adds a TcgUid to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the TcgUid
[in] | uid | TcgUid value to add
TcgResult TCG_CALL tcgAddUINT16 | ( | TcgCreateStruct * | createStruct,
 |  | UINT16 | value
 | ) |  |

Adds a 16-bit unsigned integer to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the integer
[in] | value | Integer value to add
TcgResult TCG_CALL tcgAddUINT32 | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 | value
 | ) |  |

Adds a 32-bit unsigned integer to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the integer
[in] | value | Integer value to add
TcgResult TCG_CALL tcgAddUINT64 | ( | TcgCreateStruct * | createStruct,
 |  | UINT64 | value
 | ) |  |

Adds a 64-bit unsigned integer to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the integer
[in] | value | Integer value to add
TcgResult TCG_CALL tcgAddUINT8 | ( | TcgCreateStruct * | createStruct,
 |  | UINT8 | value
 | ) |  |

Adds an 8-bit unsigned integer to the data structure.

Parameters
[in,out] | createStruct | Structure used to add the integer
[in] | value | Integer value to add


IceLake Platform Sample Code: Create TCG Sequence Token Functions

Functions
Create TCG Sequence Token Functions
Create TCG ComPacket Functions » Create TCG SubPacket Functions

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG Sequence Token Functions:

Functions

TcgResult TCG_CALL | tcgAddStartList (TcgCreateStruct *createStruct)
Adds a Start List token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndList (TcgCreateStruct *createStruct)
Adds an End List token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartName (TcgCreateStruct *createStruct)
Adds a Start Name token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndName (TcgCreateStruct *createStruct)
Adds an End Name token to the data structure. More...

Detailed Description

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Function Documentation

TcgResult TCG_CALL tcgAddEndList ( TcgCreateStruct * createStruct )

Adds an End List token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token
TcgResult TCG_CALL tcgAddEndName ( TcgCreateStruct * createStruct )

Adds an End Name token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token
TcgResult TCG_CALL tcgAddStartList ( TcgCreateStruct * createStruct )

Adds a Start List token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token
TcgResult TCG_CALL tcgAddStartName ( TcgCreateStruct * createStruct )

Adds a Start Name token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token


IceLake Platform Sample Code: Create TCG Control Token Functions

Functions
Create TCG Control Token Functions
Create TCG ComPacket Functions » Create TCG SubPacket Functions

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG Control Token Functions:

Functions

TcgResult TCG_CALL | tcgAddCall (TcgCreateStruct *createStruct)
Adds a Call token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfData (TcgCreateStruct *createStruct)
Adds an End of Data token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfSession (TcgCreateStruct *createStruct)
Adds an End of Session token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartTransaction (TcgCreateStruct *createStruct)
Adds a Start Transaction token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndTransaction (TcgCreateStruct *createStruct)
Adds an End Transaction token to the data structure. More...

Detailed Description

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Function Documentation

TcgResult TCG_CALL tcgAddCall ( TcgCreateStruct * createStruct )

Adds a Call token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token
TcgResult TCG_CALL tcgAddEndOfData ( TcgCreateStruct * createStruct )

Adds an End of Data token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token
TcgResult TCG_CALL tcgAddEndOfSession ( TcgCreateStruct * createStruct )

Adds an End of Session token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token
TcgResult TCG_CALL tcgAddEndTransaction ( TcgCreateStruct * createStruct )

Adds an End Transaction token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token
TcgResult TCG_CALL tcgAddStartTransaction ( TcgCreateStruct * createStruct )

Adds a Start Transaction token to the data structure.

Parameters
[in,out] createStruct Structure used to add the token


IceLake Platform Sample Code: _TcgCreateStruct Struct Reference

  • Class List
  • Class Index
  • Class Members
Public Attributes | List of all members
_TcgCreateStruct Struct Reference
Create TCG ComPacket Functions

Structure that is used to build the Tcg ComPacket. More...

#include <TcgCore.h>

Public Attributes

void * | buffer
Buffer allocated and freed by the client of the Tcg library. More...
UINT32 | bufferSize
Size of the buffer provided.
TcgComPacket * | comPacket
Pointer to the start of the Tcg ComPacket. More...
TcgPacket * | curPacket
Current Tcg Packet that is being created. More...
TcgSubPacket * | curSubPacket
Current Tcg SubPacket that is being created. More...
BOOLEAN | dryRun
Flag used to indicate if the buffer of the structure should be filled out. More...

Detailed Description

Structure that is used to build the Tcg ComPacket.

It contains the start buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket. This structure must be initialized by calling tcgInitTcgCreateStruct before it is used as parameter to any other Tcg function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgCreateStruct

Definition at line 135 of file TcgCore.h.

Member Data Documentation

void* _TcgCreateStruct::buffer

Buffer allocated and freed by the client of the Tcg library.

This is the buffer that shall contain the final Tcg encoded compacket.

Definition at line 140 of file TcgCore.h.

TcgComPacket* _TcgCreateStruct::comPacket

Pointer to the start of the Tcg ComPacket.

It should point to a location within buffer.

Definition at line 150 of file TcgCore.h.

TcgPacket* _TcgCreateStruct::curPacket

Current Tcg Packet that is being created.

It should point to a location within buffer.

Definition at line 155 of file TcgCore.h.

TcgSubPacket* _TcgCreateStruct::curSubPacket

Current Tcg SubPacket that is being created.

It should point to a location within buffer.

Definition at line 160 of file TcgCore.h.

BOOLEAN _TcgCreateStruct::dryRun

Flag used to indicate if the buffer of the structure should be filled out.

This is intended to be used to support a use-case where the client of library can perform all the desired tcg calls to determine what the actual size of the final compacket will be. Then the client can allocate the required buffer size and re-run the tcg calls. THIS MAY NOT BE IMPLEMENTED... REQUIRES MORE THOUGHT BECAUSE YOU CANNOT SOLVE ISSUE FOR RECEIVE

Definition at line 169 of file TcgCore.h.

The documentation for this struct was generated from the following file:
  • TcgCore.h


IceLake Platform Sample Code: Parse TCG ComPacket Functions

Classes | Typedefs | Functions
Parse TCG ComPacket Functions

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Classes

struct | _TcgParseStruct
Structure that is used to parse the Tcg response received. More...
struct | _TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions. More...

Typedefs

typedef struct _TcgParseStruct | TcgParseStruct
Structure that is used to parse the Tcg response received. More...
typedef struct _TcgToken | TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.

Functions

TcgResult TCG_CALL | tcgInitTcgParseStruct (TcgParseStruct *parseStruct, const void *buffer, UINT32 bufferSize)
Intializes the parsing structure used to parse the Tcg response. More...
TcgResult TCG_CALL | tcgGetNextToken (TcgParseStruct *parseStruct, TcgToken *tcgToken)
Retrieves next Tcg Token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetNextTokenType (TcgParseStruct *parseStruct, TcgTokenType type)
Retrieves the next TCG token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetAtomInfo (const TcgToken *tcgToken, UINT32 *headerLength, UINT32 *dataLength, UINT8 *byteOrInt, UINT8 *signOrCont)
Retrieves information about a simple token containing an atom. More...
const UINT8 *TCG_CALL | tcgGetTokenByteSequence (const TcgToken *tcgToken, UINT32 *length)
Retrieves byte sequence from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetTokenUINT64 (const TcgToken *tcgToken, UINT64 *value)
Retrieves Integer value up to 64-bits in size from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetNextUINT8 (TcgParseStruct *parseStruct, UINT8 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT16 (TcgParseStruct *parseStruct, UINT16 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT32 (TcgParseStruct *parseStruct, UINT32 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT64 (TcgParseStruct *parseStruct, UINT64 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextBOOLEAN (TcgParseStruct *parseStruct, BOOLEAN *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextTcgUid (TcgParseStruct *parseStruct, TcgUid *uid)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextByteSequence (TcgParseStruct *parseStruct, const void **data, UINT32 *length)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextCall (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfData (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfSession (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...

Detailed Description

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Typedef Documentation

typedef struct _TcgParseStruct TcgParseStruct

Structure that is used to parse the Tcg response received.

It contains the response buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket being parsed. This structure must be initialized by calling tcgInitTcgParseStruct before it is used as parameter to any other Tcg parse function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgParseStruct

Function Documentation

TcgResult TCG_CALL tcgGetAtomInfo | ( | const TcgToken * | tcgToken,
 |  | UINT32 * | headerLength,
 |  | UINT32 * | dataLength,
 |  | UINT8 * | byteOrInt,
 |  | UINT8 * | signOrCont
 | ) |  |

Retrieves information about a simple token containing an atom.

Parameters
[in,out] | tcgToken | TCG token containing simple token atom to retrieve
[out] | headerLength | Length of token header.

This is the number of bytes from the start of the token up to the beginning of the data.

Parameters
[out] dataLength Length of data.

This is the size of the byte or integer data following the token header.

Parameters
[out] | byteOrInt | Flag indicating whether the atom is a byte sequence (TCG_ATOM_TYPE_BYTE) or integer (TCG_ATOM_TYPE_INTEGER).
[out] | signOrCont | Flag indicating whether an integer atom is a signed integer or whether a byte sequence atom is continued.
TcgResult TCG_CALL tcgGetNextBOOLEAN | ( | TcgParseStruct * | parseStruct,
 |  | BOOLEAN * | value
 | ) |  |

Retrieves next token in the current payload.

If it not a BOOLEAN then a failure is reported.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in,out] | value | BOOLEAN value retrieved from current payload
TcgResult TCG_CALL tcgGetNextByteSequence | ( | TcgParseStruct * | parseStruct,
 |  | const void ** | data,
 |  | UINT32 * | length
 | ) |  |

Retrieves next token in the current payload.

If it is not a byte sequence, then a failure is reported.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[out] | data | Pointer to the beginning of the byte sequence
[out] | length | Length of the retrieved byte sequence in bytes
TcgResult TCG_CALL tcgGetNextCall ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Call token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextEndList ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End List token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextEndName ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End Name token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextEndOfData ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End of Data token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextEndOfSession ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End of Session token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextEndTransaction ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End Transaction token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextStartList ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Start List token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextStartName ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Start Name token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextStartTransaction ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Start Transaction token, then a failure is reported.

Parameters
[in,out] parseStruct Structure used to parse received TCG response
TcgResult TCG_CALL tcgGetNextTcgUid | ( | TcgParseStruct * | parseStruct,
 |  | TcgUid * | uid
 | ) |  |

Retrieves next token in the current payload.

If it is not a TcgUid then a failure is reported.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[out] | uid | TcgUid value retrieved from current payload
TcgResult TCG_CALL tcgGetNextToken | ( | TcgParseStruct * | parseStruct,
 |  | TcgToken * | tcgToken
 | ) |  |

Retrieves next Tcg Token from the current subpacket payload.

The first time it is called on a parse structure it starts at the first Subpacket of the first Packet.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in,out] | tcgToken | Tcg Token that was found. Buffer was verified to guarantee the entire Token can be accessed by caller.
TcgResult TCG_CALL tcgGetNextTokenType | ( | TcgParseStruct * | parseStruct,
 |  | TcgTokenType | type
 | ) |  |

Retrieves the next TCG token from the current subpacket payload.

If the token is not of the specified type, an error is returned.

This function is intended for use with sequence and control tokens that have no payload, since it does not return the token contents.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in] | type | Expected TCG token type
TcgResult TCG_CALL tcgGetNextUINT16 | ( | TcgParseStruct * | parseStruct,
 |  | UINT16 * | value
 | ) |  |

Retrieves next token in the current payload.

If it is not a UINT16 then a failure is reported.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in,out] | value | UINT16 value retrieved from current payload
TcgResult TCG_CALL tcgGetNextUINT32 | ( | TcgParseStruct * | parseStruct,
 |  | UINT32 * | value
 | ) |  |

Retrieves next token in the current payload.

If it not a UINT32 then a failure is reported.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in,out] | value | UINT32 value retrieved from current payload
TcgResult TCG_CALL tcgGetNextUINT64 | ( | TcgParseStruct * | parseStruct,
 |  | UINT64 * | value
 | ) |  |

Retrieves next token in the current payload.

If it is not a UINT64 then a failure is reported.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in,out] | value | UINT64 value retrieved from current payload
TcgResult TCG_CALL tcgGetNextUINT8 | ( | TcgParseStruct * | parseStruct,
 |  | UINT8 * | value
 | ) |  |

Retrieves next token in the current payload.

If it is not a UINT8 then a failure is reported.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in,out] | value | UINT8 value retrieved from current payload
const UINT8* TCG_CALL tcgGetTokenByteSequence | ( | const TcgToken * | tcgToken,
 |  | UINT32 * | length
 | ) |  |

Retrieves byte sequence from the Tcg Token provided.

Returns
NULL if failure occurs, otherwise pointer to beginning of byte sequence.
Parameters
[in,out] | tcgToken | Tcg Token containing byte sequence value to retrieve
[out] | length | Length of the byte sequence retrieved
TcgResult TCG_CALL tcgGetTokenUINT64 | ( | const TcgToken * | tcgToken,
 |  | UINT64 * | value
 | ) |  |

Retrieves Integer value up to 64-bits in size from the Tcg Token provided.

Parameters
[in,out] | tcgToken | Tcg Token containing integer value to retrieve
[in,out] | value | Integer value retrieved
TcgResult TCG_CALL tcgInitTcgParseStruct | ( | TcgParseStruct * | parseStruct,
 |  | const void * | buffer,
 |  | UINT32 | bufferSize
 | ) |  |

Intializes the parsing structure used to parse the Tcg response.

This must be called before using the parseStruct with any other function.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in] | buffer | Buffer containing TCG response
[in] | bufferSize | Size of buffer containing TCG response


IceLake Platform Sample Code: _TcgParseStruct Struct Reference

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Public Attributes | List of all members
_TcgParseStruct Struct Reference
Parse TCG ComPacket Functions

Structure that is used to parse the Tcg response received. More...

#include <TcgCore.h>

Public Attributes

const void * | buffer
Buffer allocated and freed by the client of the Tcg library. More...
UINT32 | bufferSize
Size of the buffer provided.
const TcgComPacket * | comPacket
Pointer to the start of the Tcg ComPacket. More...
const TcgPacket * | curPacket
Current Tcg Packet that is being created. More...
const TcgSubPacket * | curSubPacket
Current Tcg SubPacket that is being created. More...
const UINT8 * | curPtr
Current pointer within the current subpacket payload.

Detailed Description

Structure that is used to parse the Tcg response received.

It contains the response buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket being parsed. This structure must be initialized by calling tcgInitTcgParseStruct before it is used as parameter to any other Tcg parse function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgParseStruct

Definition at line 671 of file TcgCore.h.

Member Data Documentation

const void* _TcgParseStruct::buffer

Buffer allocated and freed by the client of the Tcg library.

This is the buffer that contains the Tcg response to decode/parse.

Definition at line 676 of file TcgCore.h.

const TcgComPacket* _TcgParseStruct::comPacket

Pointer to the start of the Tcg ComPacket.

It should point to a location within buffer.

Definition at line 686 of file TcgCore.h.

const TcgPacket* _TcgParseStruct::curPacket

Current Tcg Packet that is being created.

It should point to a location within buffer.

Definition at line 691 of file TcgCore.h.

const TcgSubPacket* _TcgParseStruct::curSubPacket

Current Tcg SubPacket that is being created.

It should point to a location within buffer.

Definition at line 696 of file TcgCore.h.

The documentation for this struct was generated from the following file:
  • TcgCore.h


IceLake Platform Sample Code: _TcgToken Struct Reference

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Public Attributes | List of all members
_TcgToken Struct Reference
Parse TCG ComPacket Functions

Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions. More...

#include <TcgCore.h>

Public Attributes

TcgTokenType | type
Describes the type of Tcg token the hdr start points to.
const UINT8 * | hdrStart
Pointer to the beginning of the header of the Tcg token.

Detailed Description

Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.

Definition at line 708 of file TcgCore.h.

The documentation for this struct was generated from the following file:
  • TcgCore.h


IceLake Platform Sample Code: Common Create TCG Utility Functions

Functions
Common Create TCG Utility Functions

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Functions

TcgResult TCG_CALL | tcgStartMethodCall (TcgCreateStruct *createStruct, TcgUid invokingId, TcgUid methodId)
Adds start Method Call to the data structure using invoking id and method Id provided. More...
TcgResult TCG_CALL | tcgStartParameters (TcgCreateStruct *createStruct)
Adds start parameters (STARTLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndParameters (TcgCreateStruct *createStruct)
Adds end parameters (ENDLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndMethodCall (TcgCreateStruct *createStruct)
Adds end method call (ENDDATA) to the data structure in addition to the method status list. More...
TcgResult TCG_CALL | tcgCreateStartSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, TcgUid spId, BOOLEAN write, UINT32 hostChallengeLength, const void *hostChallenge, TcgUid HostSigningAuthority)
Adds Start Session call to the data structure. More...
TcgResult TCG_CALL | tcgCreateSetCPin (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid sidRow, const void *password, UINT32 passwordSize)
Creates ComPacket with a Method call that sets the PIN column for the row specified. More...
TcgResult TCG_CALL | tcgSetAuthorityEnabled (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid authorityUid, BOOLEAN enabled)
Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified. More...
TcgResult TCG_CALL | tcgCreateEndSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSession, UINT32 tpSessionId)
Creates ComPacket with EndSession. More...

Detailed Description

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Function Documentation

TcgResult TCG_CALL tcgCreateEndSession | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | hostSession,
 |  | UINT32 | tpSessionId
 | ) |  |

Creates ComPacket with EndSession.

This assumes a start session has already been opened.

Parameters
[in,out] | createStruct | Structure used to add Endsession
[in,out] | size | Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | hostSession | Host Session ID for the Packet
[in] | tpSessionId | Tper Session ID for the Packet
TcgResult TCG_CALL tcgCreateSetCPin | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | tperSession,
 |  | UINT32 | hostSession,
 |  | TcgUid | sidRow,
 |  | const void * | password,
 |  | UINT32 | passwordSize
 | ) |  |

Creates ComPacket with a Method call that sets the PIN column for the row specified.

This assumes a start session has already been opened with the desired SP.

Parameters
[in,out] | createStruct | Structure used to add method call
[in,out] | size | Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | tperSession | Tper Session ID for the Packet
[in] | hostSession | Host Session ID for the Packet
[in] | sidRow | UID of row of current SP to set PIN column
[in] | password | value of PIN to set
[in] | passwordSize | Size of PIN
TcgResult TCG_CALL tcgCreateStartSession | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | hostSessionId,
 |  | TcgUid | spId,
 |  | BOOLEAN | write,
 |  | UINT32 | hostChallengeLength,
 |  | const void * | hostChallenge,
 |  | TcgUid | HostSigningAuthority
 | ) |  |

Adds Start Session call to the data structure.

This creates the entire ComPacket structure and returns the size of the entire compacket in the size parameter.

Parameters
[in,out] | createStruct | Structure used to add the start session call
[in,out] | size | Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | hostSessionId | Host Session ID
[in] | spId | Security Provider to start session with
[in] | write | Write option for start session. TRUE = start session requests write access
[in] | hostChallengeLength | Length of the host challenge. Length should be 0 if hostChallenge is NULL
[in] | hostChallenge | Host challenge for Host Signing Authority. If NULL, then no Host Challenge shall be sent.
[in] | HostSigningAuthority | Host Signing Authority used for start session. If NULL, then no Host Signing Authority shall be sent.
TcgResult TCG_CALL tcgEndMethodCall ( TcgCreateStruct * createStruct )

Adds end method call (ENDDATA) to the data structure in addition to the method status list.

Parameters
[in,out] createStruct Structure used to add the method call
TcgResult TCG_CALL tcgEndParameters ( TcgCreateStruct * createStruct )

Adds end parameters (ENDLIST) to the data structure.

Parameters
[in,out] createStruct Structure used to add the end parameters
TcgResult TCG_CALL tcgSetAuthorityEnabled | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | tperSession,
 |  | UINT32 | hostSession,
 |  | TcgUid | authorityUid,
 |  | BOOLEAN | enabled
 | ) |  |

Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified.

This assumes a start session has already been opened with the desired SP.

Parameters
[in,out] | createStruct | Structure used to add method call
[in,out] | size | Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | tperSession | Tper Session ID for the Packet
[in] | hostSession | Host Session ID for the Packet
[in] | authorityUid | Authority UID to modify the "Enabled" column for
[in] | enabled | Value to set the "Enabled" column to
TcgResult TCG_CALL tcgStartMethodCall | ( | TcgCreateStruct * | createStruct,
 |  | TcgUid | invokingId,
 |  | TcgUid | methodId
 | ) |  |

Adds start Method Call to the data structure using invoking id and method Id provided.

Parameters
[in,out] | createStruct | Structure used to add the method call
[in] | invokingId | Invoking ID for the method call
[in] | methodId | Method ID for the method call
TcgResult TCG_CALL tcgStartParameters ( TcgCreateStruct * createStruct )

Adds start parameters (STARTLIST) to the data structure.

Parameters
[in,out] createStruct Structure used to add the start parameters


IceLake Platform Sample Code: Parse TCG ComPacket Utility Functions

Functions
Parse TCG ComPacket Utility Functions

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Functions

const char *TCG_CALL | tcgTokenTypeString (TcgTokenType type)
Retrieves human-readable token type name. More...
TcgResult TCG_CALL | tcgGetMethodStatus (const TcgParseStruct *parseStruct, UINT8 *methodStatus)
Returns the method status of the current subpacket. More...
const char *TCG_CALL | tcgMethodStatusString (UINT8 methodStatus)
Returns a human-readable string representing a method status return code. More...
TcgResult TCG_CALL | tcgGetComIds (const TcgParseStruct *parseStruct, UINT16 *comId, UINT16 *comIdExtension)
Retrieves the comID and Extended comID of the ComPacket in the Tcg response. More...
TcgResult TCG_CALL | tcgCheckComIds (const TcgParseStruct *parseStruct, UINT16 expectedComId, UINT16 expectedComIdExtension)
Checks if the ComIDs of the response match the expected values. More...
TcgResult TCG_CALL | tcgParseSyncSession (const TcgParseStruct *parseStruct, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, UINT32 *tperSessionId)
Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID. More...
BOOLEAN TCG_CALL | tcgIsProtocolSupported (const TCG_SUPPORTED_SECURITY_PROTOCOLS *protocolList, UINT16 protocol)
Determines if the protocol provided is part of the provided supported protocol list. More...
BOOLEAN TCG_CALL | tcgIsLocked (const TCG_LEVEL0_DISCOVERY_HEADER *discovery)
Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response. More...

Detailed Description

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Function Documentation

TcgResult TCG_CALL tcgCheckComIds | ( | const TcgParseStruct * | parseStruct,
 |  | UINT16 | expectedComId,
 |  | UINT16 | expectedComIdExtension
 | ) |  |

Checks if the ComIDs of the response match the expected values.

Parameters
[in] | parseStruct | Structure used to parse received TCG response
[in] | expectedComId | Expected comID
[in] | expectedComIdExtension | Expected extended comID
TcgResult TCG_CALL tcgGetComIds | ( | const TcgParseStruct * | parseStruct,
 |  | UINT16 * | comId,
 |  | UINT16 * | comIdExtension
 | ) |  |

Retrieves the comID and Extended comID of the ComPacket in the Tcg response.

It is intended to be used to confirm the received Tcg response is intended for user that received it.

Parameters
[in] | parseStruct | Structure used to parse received TCG response
[in,out] | comId | comID retrieved from received ComPacket
[in,out] | comIdExtension | Extended comID retrieved from received ComPacket
TcgResult TCG_CALL tcgGetMethodStatus | ( | const TcgParseStruct * | parseStruct,
 |  | UINT8 * | methodStatus
 | ) |  |

Returns the method status of the current subpacket.

Does not affect the current position in the ComPacket. In other words, it can be called whenever you have a valid SubPacket.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response
[in,out] | methodStatus | Method status retrieved of the current SubPacket
BOOLEAN TCG_CALL tcgIsLocked ( const TCG_LEVEL0_DISCOVERY_HEADER * discovery )

Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response.

Returns
TRUE = Locked is set, FALSE = Locked is false
Parameters
[in] discovery Level 0 discovery response
BOOLEAN TCG_CALL tcgIsProtocolSupported | ( | const TCG_SUPPORTED_SECURITY_PROTOCOLS * | protocolList,
 |  | UINT16 | protocol
 | ) |  |

Determines if the protocol provided is part of the provided supported protocol list.

Returns
TRUE = protocol is supported, FALSE = protocol is not supported
Parameters
[in] | protocolList | Supported protocol list to investigate
[in] | protocol | Protocol value to determine if supported
const char* TCG_CALL tcgMethodStatusString ( UINT8 methodStatus )

Returns a human-readable string representing a method status return code.

Parameters
[in] methodStatus Method status to translate to a string
TcgResult TCG_CALL tcgParseSyncSession | ( | const TcgParseStruct * | parseStruct,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | hostSessionId,
 |  | UINT32 * | tperSessionId
 | ) |  |

Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID.

If the Sync Session response parameters do not match the comID, extended ComID and host session ID then a failure is returned.

Parameters
[in,out] | parseStruct | Structure used to parse received TCG response, contains Sync Session response.
[in] | comId | Expected ComID that is compared to actual ComID of response
[in] | comIdExtension | Expected Extended ComID that is compared to actual Extended ComID of response
[in] | hostSessionId | Expected Host Session ID that is compared to actual Host Session ID of response
[in,out] | tperSessionId | Tper Session ID retrieved from the Sync Session response.
const char* TCG_CALL tcgTokenTypeString ( TcgTokenType type )

Retrieves human-readable token type name.

Parameters
[in] type Token type to retrieve
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Class List

  • Class List
  • Class Index
  • Class Members
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL | I2C bus configuration management protocol
C _EFI_I2C_MASTER_PROTOCOL | I2C master mode protocol
C _EFI_SMM_CPU_SAVE_STATE_PROTOCOL | Provides a programatic means to access SMM save state
C _EFI_USB_DEVICE_MODE_PROTOCOL | Usb Device Mode Protocol Structure
C _EPC_BIOS_CONFIG | EPC data structure for BIOS Variable
C _FWU_CONFIRM_LIVE_PING_MSG | FWU_CONFIRM_LIVE_PING_MSG - confirm live ping
C _FWU_DATA_MSG | FWU_DATA_MSG - send data during the update process
C _FWU_END_MESSAGE | FWU_END_MSG - end the update process
C _FWU_FLASH_IMAGE_START_MSG_REPLY | FWU_FLASH_IMAGE_START_MSG - start the update process
C _FWU_GET_FEATURE_STATE_MSG_REPLY | FWU_GET_FEATURE_STATE_MSG - get info
C _FWU_GET_FWU_INFO_STATUS_MSG | FWU_GET_FWU_INFO_STATUS_MSG - get info status
C _FWU_GET_INFO_MSG | FWU_GET_INFO_MSG - get info
C _FWU_GET_IPU_PT_ATTRB_MSG | FWU_GET_IPU_PT_ATTRB_MSG - get info status
C _FWU_GET_OEMID_MSG_REPLY | FWU_GET_OEMID_MSG - verify OEMID
C _FWU_GET_PLATFORM_TYPE_MSG_REPLY | FWU_GET_PLATFORM_TYPE_MSG - get plat type
C _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE | FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image
C _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE | FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image
C _FWU_GET_UPDATE_DATA_EXTENSION_MSG | FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability
C _FWU_GET_VERSION_MSG_REPLY | FWU_GET_VERSION_MSG - start the update process
C _FWU_IMAGE_COMPATABILITY_CHECK_MSG | FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability
C _FWU_INVALID_MSG_REPLY | FWU_INVALID_MSG - confirm live ping
C _FWU_START_MSG | FWU_START_MSG - start the update process
C _FWU_VERIFY_OEMID_MSG | FWU_VERIFY_OEMID_MSG - verify OEMID
C _FWU_VERIFY_PWD_MSG | FWU_VERIFY_PWD_MSG - confirm live ping
C _ME_FWU_INFO_MSG | ME_FWU_INFO_MSG - get ME firmware update info message
C _PLATFORM_EMMC_TUNING_DATA | This structure describes the variable to be set with the returned EMMC_TUNING_DATA from EMMC_TUNE protocol
C _TcgCreateStruct | Structure that is used to build the Tcg ComPacket
C _TcgParseStruct | Structure that is used to parse the Tcg response received
C _TcgToken | Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions
C _VERSION | Defines a generic version structure used in the software build process
C AUTHENTICATED_VARIABLE_HEADER | Single Variable Data Header Structure for Auth variable
C EFI_I2C_REQUEST_PACKET | I2C device operation
C EFI_SMM_CPU_STATE | Union of CPU save-state strcutures for IA32 and X64
C EFI_SMM_CPU_STATE32 | CPU save-state strcuture for IA32 and X64
C EFI_SMM_CPU_STATE64 | This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure
C EFI_USB_INTERFACE_INFO | USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec
C EPC_OS_CONFIG | EPC data structure for OS Variable
C FWU_DATA_MESSAGE | FWU_DATA_MESSAGE - data fragment of the image
C FWU_GET_INFO_MESSAGE | FWU_GET_INFO_MESSAGE - get version
C MEMORY_MAP | If the debugger branch trace/data store debug feature is enabled This is an optional debug feature as enabling it will introduce significant changes in performance and system resources
C SOFTWARE_GUARD_STATUS | Data structure for SGX Policy Status The presence of this variable implies that SGX is supported For backward compatibility: Absence of this variable implies that SGX is supported and defaulted to 'Software Controlled'
C VARIABLE_HEADER | Single Variable Data Header Structure
C VARIABLE_STORE_HEADER | Variable Store region header


IceLake Platform Sample Code: _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL Struct Reference

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Public Attributes | List of all members
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL Struct Reference

I2C bus configuration management protocol. More...

#include <I2cBusConfigurationManagement.h>

Collaboration diagram for _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL:
[legend]

Public Attributes

EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration
Enable an I2C bus configuration for use.
UINTN I2cBusConfigurationCount
Number of switch and multiplexer configurations for this I2C bus.

Detailed Description

I2C bus configuration management protocol.

Definition at line 178 of file I2cBusConfigurationManagement.h.

The documentation for this struct was generated from the following file:
  • I2cBusConfigurationManagement.h


IceLake Platform Sample Code: _EFI_I2C_MASTER_PROTOCOL Struct Reference

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_EFI_I2C_MASTER_PROTOCOL Struct Reference

I2C master mode protocol. More...

#include <I2cMaster.h>

Collaboration diagram for _EFI_I2C_MASTER_PROTOCOL:
[legend]

Public Attributes

EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet
Set the clock frequency for the I2C bus.
EFI_I2C_MASTER_RESET Reset
Reset the I2C host controller.
EFI_I2C_MASTER_START_REQUEST StartRequest
Start an I2C transaction in master mode on the host controller.
UINT32 | MaximumReceiveBytes
The maximum number of bytes the I2C host controller is able to receive from the I2C bus.
UINT32 | MaximumTransmitBytes
The maximum number of bytes the I2C host controller is able to send on the I2C bus.
UINT32 | MaximumTotalBytes
The maximum number of bytes in the I2C bus transaction.

Detailed Description

I2C master mode protocol.

This protocol manipulates the I2C host controller to perform transactions as a master on the I2C bus using the current state of any switches or multiplexers in the I2C bus.

Definition at line 511 of file I2cMaster.h.

The documentation for this struct was generated from the following file:
  • I2cMaster.h


IceLake Platform Sample Code: _EFI_SMM_CPU_SAVE_STATE_PROTOCOL Struct Reference

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_EFI_SMM_CPU_SAVE_STATE_PROTOCOL Struct Reference

Provides a programatic means to access SMM save state. More...

#include <SmmCpuSaveState.h>

Collaboration diagram for _EFI_SMM_CPU_SAVE_STATE_PROTOCOL:
[legend]

Public Attributes

EFI_SMM_CPU_STATE ** CpuSaveState
Reference to a list of save states.

Detailed Description

Provides a programatic means to access SMM save state.

Definition at line 185 of file SmmCpuSaveState.h.

The documentation for this struct was generated from the following file:
  • SmmCpuSaveState.h


IceLake Platform Sample Code: _EFI_USB_DEVICE_MODE_PROTOCOL Struct Reference

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_EFI_USB_DEVICE_MODE_PROTOCOL Struct Reference

Usb Device Mode Protocol Structure. More...

#include <UsbDeviceModeProtocol.h>

Collaboration diagram for _EFI_USB_DEVICE_MODE_PROTOCOL:
[legend]

Detailed Description

Usb Device Mode Protocol Structure.

Definition at line 108 of file UsbDeviceModeProtocol.h.

The documentation for this struct was generated from the following file:
  • UsbDeviceModeProtocol.h


IceLake Platform Sample Code: _EPC_BIOS_CONFIG Struct Reference

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_EPC_BIOS_CONFIG Struct Reference

EPC data structure for BIOS Variable. More...

#include <SoftwareGuardSetupData.h>

Public Attributes

UINT32 | SupportedPrmBins
supported EPC bins; Bit 0- Support for 1 MB, 1- Support for 2 MB, 2- Support for 4 MB,
UINT32 | MaxEpcSize
Maximum EPC size supported by platform in MB.
UINT32 | AllocatedEpcSize
Allocated EPC size in MB.
UINT32 | EpcMap [32]
Mapping of PRM size to corresponding EPC size.

Detailed Description

EPC data structure for BIOS Variable.

Definition at line 54 of file SoftwareGuardSetupData.h.

The documentation for this struct was generated from the following file:
  • SoftwareGuardSetupData.h


IceLake Platform Sample Code: _FWU_CONFIRM_LIVE_PING_MSG Struct Reference

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_FWU_CONFIRM_LIVE_PING_MSG Struct Reference

FWU_CONFIRM_LIVE_PING_MSG - confirm live ping. More...

#include <Fwu_Common.h>

Detailed Description

FWU_CONFIRM_LIVE_PING_MSG - confirm live ping.

: FWU_CONFIRM_LIVE_PING_MSG

Definition at line 1029 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_DATA_MSG Struct Reference

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_FWU_DATA_MSG Struct Reference

FWU_DATA_MSG - send data during the update process. More...

#include <Fwu_Common.h>

Detailed Description

FWU_DATA_MSG - send data during the update process.

: FWU_DATA_MSG

Definition at line 748 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_END_MESSAGE Struct Reference

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_FWU_END_MESSAGE Struct Reference

FWU_END_MSG - end the update process. More...

#include <Fwu_Common.h>

Detailed Description

FWU_END_MSG - end the update process.

: FWU_END_MSG

Definition at line 769 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_FLASH_IMAGE_START_MSG_REPLY Struct Reference

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_FWU_FLASH_IMAGE_START_MSG_REPLY Struct Reference

FWU_FLASH_IMAGE_START_MSG - start the update process. More...

#include <Fwu_Common.h>

Detailed Description

FWU_FLASH_IMAGE_START_MSG - start the update process.

: FWU_FLASH_IMAGE_START_MSG

Definition at line 681 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_FEATURE_STATE_MSG_REPLY Struct Reference

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_FWU_GET_FEATURE_STATE_MSG_REPLY Struct Reference

FWU_GET_FEATURE_STATE_MSG - get info. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_FEATURE_STATE_MSG - get info.

: FWU_GET_FEATURE_STATE_MSG

Definition at line 820 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_FWU_INFO_STATUS_MSG Struct Reference

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_FWU_GET_FWU_INFO_STATUS_MSG Struct Reference

FWU_GET_FWU_INFO_STATUS_MSG - get info status. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_FWU_INFO_STATUS_MSG - get info status.

: FWU_GET_FWU_INFO_STATUS_MSG

Definition at line 990 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_INFO_MSG Struct Reference

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_FWU_GET_INFO_MSG Struct Reference

FWU_GET_INFO_MSG - get info. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_INFO_MSG - get info.

: FWU_GET_INFO_MSG

Definition at line 789 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_IPU_PT_ATTRB_MSG Struct Reference

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_FWU_GET_IPU_PT_ATTRB_MSG Struct Reference

FWU_GET_IPU_PT_ATTRB_MSG - get info status. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_IPU_PT_ATTRB_MSG - get info status.

: FWU_GET_IPU_PT_ATTRB_MSG

Definition at line 966 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_OEMID_MSG_REPLY Struct Reference

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_FWU_GET_OEMID_MSG_REPLY Struct Reference

FWU_GET_OEMID_MSG - verify OEMID. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_OEMID_MSG - verify OEMID.

: FWU_GET_OEMID_MSG

Definition at line 864 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_PLATFORM_TYPE_MSG_REPLY Struct Reference

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_FWU_GET_PLATFORM_TYPE_MSG_REPLY Struct Reference

FWU_GET_PLATFORM_TYPE_MSG - get plat type. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_PLATFORM_TYPE_MSG - get plat type.

: FWU_GET_PLATFORM_TYPE_MSG

Definition at line 833 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE Struct Reference

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_FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE Struct Reference

FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.

: FWU_GET_RESTORE_POINT_IMAGE_MESSAGE

Definition at line 946 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE Struct Reference

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_FWU_GET_RESTORE_POINT_IMAGE_MESSAGE Struct Reference

FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.

: FWU_GET_RESTORE_POINT_IMAGE_MESSAGE

Definition at line 927 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_UPDATE_DATA_EXTENSION_MSG Struct Reference

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_FWU_GET_UPDATE_DATA_EXTENSION_MSG Struct Reference

FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability. More...

#include <Fwu_Common.h>

Detailed Description

FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability.

: FWU_GET_UPDATE_DATA_EXTENSION_MSG

Definition at line 907 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_GET_VERSION_MSG_REPLY Struct Reference

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_FWU_GET_VERSION_MSG_REPLY Struct Reference

FWU_GET_VERSION_MSG - start the update process. More...

#include <Fwu_Common.h>

Collaboration diagram for _FWU_GET_VERSION_MSG_REPLY:
[legend]

Detailed Description

FWU_GET_VERSION_MSG - start the update process.

: FWU_GET_VERSION_MSG

Definition at line 694 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_IMAGE_COMPATABILITY_CHECK_MSG Struct Reference

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_FWU_IMAGE_COMPATABILITY_CHECK_MSG Struct Reference

FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability. More...

#include <Fwu_Common.h>

Detailed Description

FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability.

: FWU_IMAGE_COMPATABILITY_CHECK_MSG

Definition at line 877 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_INVALID_MSG_REPLY Struct Reference

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_FWU_INVALID_MSG_REPLY Struct Reference

FWU_INVALID_MSG - confirm live ping. More...

#include <Fwu_Common.h>

Detailed Description

FWU_INVALID_MSG - confirm live ping.

: FWU_INVALID_MSG

Definition at line 1067 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_START_MSG Struct Reference

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_FWU_START_MSG Struct Reference

FWU_START_MSG - start the update process. More...

#include <Fwu_Common.h>

Detailed Description

FWU_START_MSG - start the update process.

: FWU_START_MSG

Definition at line 717 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_VERIFY_OEMID_MSG Struct Reference

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_FWU_VERIFY_OEMID_MSG Struct Reference

FWU_VERIFY_OEMID_MSG - verify OEMID. More...

#include <Fwu_Common.h>

Detailed Description

FWU_VERIFY_OEMID_MSG - verify OEMID.

: FWU_VERIFY_OEMID_MSG

Definition at line 846 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _FWU_VERIFY_PWD_MSG Struct Reference

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_FWU_VERIFY_PWD_MSG Struct Reference

FWU_VERIFY_PWD_MSG - confirm live ping. More...

#include <Fwu_Common.h>

Detailed Description

FWU_VERIFY_PWD_MSG - confirm live ping.

: FWU_VERIFY_PWD_MSG

Definition at line 1048 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _ME_FWU_INFO_MSG Struct Reference

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_ME_FWU_INFO_MSG Struct Reference

ME_FWU_INFO_MSG - get ME firmware update info message. More...

#include <Fwu_Common.h>

Detailed Description

ME_FWU_INFO_MSG - get ME firmware update info message.

: ME_FWU_INFO_MSG

Definition at line 1011 of file Fwu_Common.h.

The documentation for this struct was generated from the following file:
  • Fwu_Common.h


IceLake Platform Sample Code: _PLATFORM_EMMC_TUNING_DATA Struct Reference

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_PLATFORM_EMMC_TUNING_DATA Struct Reference

This structure describes the variable to be set with the returned EMMC_TUNING_DATA from EMMC_TUNE protocol. More...

#include <PlatformEmmcHs400Info.h>

Public Attributes

UINT8 | Hs400DataValid
eMMC HS400 Data Validation Status 0: HS400 Data is invalid, 1: HS400 Data is valid
UINT8 | Hs400RxStrobe1Dll
Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)
UINT8 | Hs400TxDataDll
Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)

Detailed Description

This structure describes the variable to be set with the returned EMMC_TUNING_DATA from EMMC_TUNE protocol.

Definition at line 43 of file PlatformEmmcHs400Info.h.

The documentation for this struct was generated from the following file:
  • PlatformEmmcHs400Info.h


IceLake Platform Sample Code: _VERSION Struct Reference

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_VERSION Struct Reference

Defines a generic version structure used in the software build process. More...

#include <ver.h>

Detailed Description

Defines a generic version structure used in the software build process.

This structure will be used to represent versions of ROM, FW and Recovery modules.

Definition at line 83 of file ver.h.

The documentation for this struct was generated from the following file:
  • ver.h


IceLake Platform Sample Code: AUTHENTICATED_VARIABLE_HEADER Struct Reference

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AUTHENTICATED_VARIABLE_HEADER Struct Reference

Single Variable Data Header Structure for Auth variable. More...

#include <MultiPlatSupport.h>

Public Attributes

UINT16 | StartId
Variable Data Start Flag.
UINT8 | State
Variable State defined above.
UINT32 | Attributes
Attributes of variable defined in UEFI specification.
UINT64 | MonotonicCount
Associated monotonic count value against replay attack.
EFI_TIME | TimeStamp
Associated TimeStamp value against replay attack.
UINT32 | PubKeyIndex
Index of associated public key in database.
UINT32 | NameSize
Size of variable null-terminated Unicode string name.
UINT32 | DataSize
Size of the variable data without this header.
EFI_GUID | VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.

Detailed Description

Single Variable Data Header Structure for Auth variable.

Definition at line 153 of file MultiPlatSupport.h.

The documentation for this struct was generated from the following file:
  • MultiPlatSupport.h


IceLake Platform Sample Code: EFI_I2C_REQUEST_PACKET Struct Reference

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EFI_I2C_REQUEST_PACKET Struct Reference

I2C device operation. More...

#include <I2cMaster.h>

Public Attributes

UINT32 | WriteBytes
Number of bytes to send to the I2C device.
UINT32 | ReadBytes
Number of bytes to read, set to zero for write only operations.
UINT8 * | WriteBuffer
Address of the buffer containing the data to send to the I2C device. More...
UINT8 * | ReadBuffer
Address of the buffer to receive data from the I2C device. More...
UINT32 | Timeout
Timeout for the I2C operation in 100 ns units.

Detailed Description

I2C device operation.

This structure provides the information necessary for an operation on an I2C device

Definition at line 360 of file I2cMaster.h.

Member Data Documentation

UINT8* EFI_I2C_REQUEST_PACKET::ReadBuffer

Address of the buffer to receive data from the I2C device.

Use NULL for write only operations. The ReadBuffer must be at least ReadBytes in length.

Definition at line 382 of file I2cMaster.h.

UINT8* EFI_I2C_REQUEST_PACKET::WriteBuffer

Address of the buffer containing the data to send to the I2C device.

The WriteBuffer must be at least WriteBytes in length.

Definition at line 375 of file I2cMaster.h.

The documentation for this struct was generated from the following file:
  • I2cMaster.h


IceLake Platform Sample Code: EFI_SMM_CPU_STATE Union Reference

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EFI_SMM_CPU_STATE Union Reference

Union of CPU save-state strcutures for IA32 and X64. More...

#include <SmmCpuSaveState.h>

Collaboration diagram for EFI_SMM_CPU_STATE:
[legend]

Detailed Description

Union of CPU save-state strcutures for IA32 and X64.

This union declaration does not exctly match the Framework SMM CIS 0.91 because the union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200] field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for the layout and also maintains source comaptibility for access of all fields in this union.

Definition at line 175 of file SmmCpuSaveState.h.

The documentation for this union was generated from the following file:
  • SmmCpuSaveState.h


IceLake Platform Sample Code: EFI_SMM_CPU_STATE32 Struct Reference

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EFI_SMM_CPU_STATE32 Struct Reference

CPU save-state strcuture for IA32 and X64. More...

#include <SmmCpuSaveState.h>

Detailed Description

CPU save-state strcuture for IA32 and X64.

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200] field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for the layout and also maintains source comaptibility for access of all fields in this union.

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These have been changed to use the base types defined in the UEFI Specification.

Definition at line 66 of file SmmCpuSaveState.h.

The documentation for this struct was generated from the following file:
  • SmmCpuSaveState.h


IceLake Platform Sample Code: EFI_SMM_CPU_STATE64 Struct Reference

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EFI_SMM_CPU_STATE64 Struct Reference

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. More...

#include <SmmCpuSaveState.h>

Detailed Description

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure.

These have been changed to use the base types defined in the UEFI Specification.

Definition at line 106 of file SmmCpuSaveState.h.

The documentation for this struct was generated from the following file:
  • SmmCpuSaveState.h


IceLake Platform Sample Code: EFI_USB_INTERFACE_INFO Struct Reference

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EFI_USB_INTERFACE_INFO Struct Reference

USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec. More...

#include <EfiUsbFnIo.h>

Detailed Description

USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec.

Definition at line 75 of file EfiUsbFnIo.h.

The documentation for this struct was generated from the following file:
  • EfiUsbFnIo.h


IceLake Platform Sample Code: EPC_OS_CONFIG Struct Reference

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EPC_OS_CONFIG Struct Reference

EPC data structure for OS Variable. More...

#include <SoftwareGuardSetupData.h>

Public Attributes

UINT32 RequestedEpcSize
Requested EPC size in MB.

Detailed Description

EPC data structure for OS Variable.

Definition at line 47 of file SoftwareGuardSetupData.h.

The documentation for this struct was generated from the following file:
  • SoftwareGuardSetupData.h


IceLake Platform Sample Code: FWU_DATA_MESSAGE Struct Reference

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FWU_DATA_MESSAGE Struct Reference

FWU_DATA_MESSAGE - data fragment of the image. More...

#include <FWUpdateLib.h>

Detailed Description

FWU_DATA_MESSAGE - data fragment of the image.

: FWU_MESSAGE_TYPE_DATA : The length of the data field, in Little Endian : Reserved, must be 0 : The data of the image fragment

Definition at line 142 of file FWUpdateLib.h.

The documentation for this struct was generated from the following file:
  • FWUpdateLib.h


IceLake Platform Sample Code: FWU_GET_INFO_MESSAGE Struct Reference

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FWU_GET_INFO_MESSAGE Struct Reference

FWU_GET_INFO_MESSAGE - get version. More...

#include <FWUpdateLib.h>

Detailed Description

FWU_GET_INFO_MESSAGE - get version.

: FWU_MESSAGE_TYPE_GET_INFO

Definition at line 130 of file FWUpdateLib.h.

The documentation for this struct was generated from the following file:
  • FWUpdateLib.h


IceLake Platform Sample Code: MEMORY_MAP Struct Reference

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MEMORY_MAP Struct Reference

If the debugger branch trace/data store debug feature is enabled This is an optional debug feature as enabling it will introduce significant changes in performance and system resources. More...

Detailed Description

If the debugger branch trace/data store debug feature is enabled This is an optional debug feature as enabling it will introduce significant changes in performance and system resources.

Definition at line 112 of file PlatformInitPreMem.c.

The documentation for this struct was generated from the following file:
  • PlatformInitPreMem.c


IceLake Platform Sample Code: SOFTWARE_GUARD_STATUS Struct Reference

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SOFTWARE_GUARD_STATUS Struct Reference

Data structure for SGX Policy Status The presence of this variable implies that SGX is supported For backward compatibility: Absence of this variable implies that SGX is supported and defaulted to 'Software Controlled'. More...

#include <SoftwareGuardSetupData.h>

Public Attributes

UINT8 | SgxStatus:2
Bitmap of SGX Policy setting. More...
UINT8 | Reserved:6
Reserved 6 bits.

Detailed Description

Data structure for SGX Policy Status The presence of this variable implies that SGX is supported For backward compatibility: Absence of this variable implies that SGX is supported and defaulted to 'Software Controlled'.

Definition at line 67 of file SoftwareGuardSetupData.h.

Member Data Documentation

UINT8 SOFTWARE_GUARD_STATUS::SgxStatus

Bitmap of SGX Policy setting.

  • BIT[1:0]: SgxStatus
    • 00b = Disabled.
    • 01b = Enabled.
    • 10b = Software Controlled.
    • 11b = Reserved.

Definition at line 76 of file SoftwareGuardSetupData.h.

The documentation for this struct was generated from the following file:
  • SoftwareGuardSetupData.h


IceLake Platform Sample Code: VARIABLE_HEADER Struct Reference

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VARIABLE_HEADER Struct Reference

Single Variable Data Header Structure. More...

#include <MultiPlatSupport.h>

Public Attributes

UINT16 | StartId
Variable Data Start Flag.
UINT8 | State
Variable State defined above.
UINT32 | Attributes
Attributes of variable defined in UEFI specification.
UINT32 | NameSize
Size of variable null-terminated Unicode string name.
UINT32 | DataSize
Size of the variable data without this header.
EFI_GUID | VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.

Detailed Description

Single Variable Data Header Structure.

Definition at line 122 of file MultiPlatSupport.h.

The documentation for this struct was generated from the following file:
  • MultiPlatSupport.h


IceLake Platform Sample Code: VARIABLE_STORE_HEADER Struct Reference

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VARIABLE_STORE_HEADER Struct Reference

Variable Store region header. More...

#include <MultiPlatSupport.h>

Public Attributes

EFI_GUID | Signature
Variable store region signature.
UINT32 | Size
Size of entire variable store, including size of variable store header but not including the size of FvHeader.
UINT8 | Format
Variable region format state.
UINT8 | State
Variable region healthy state.

Detailed Description

Variable Store region header.

Definition at line 84 of file MultiPlatSupport.h.

The documentation for this struct was generated from the following file:
  • MultiPlatSupport.h


IceLake Platform Sample Code: Class Index

  • Class List
  • Class Index
  • Class Members
Class Index
A | E | F | M | S | V | _
A
FWU_GET_INFO_MESSAGE _EFI_I2C_MASTER_PROTOCOL _FWU_GET_OEMID_MSG_REPLY _PLATFORM_EMMC_TUNING_DATA
M
_EFI_SMM_CPU_SAVE_STATE_PROTOCOL _FWU_GET_PLATFORM_TYPE_MSG_REPLY _TcgCreateStruct
AUTHENTICATED_VARIABLE_HEADER _EFI_USB_DEVICE_MODE_PROTOCOL _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE _TcgParseStruct
E
MEMORY_MAP _EPC_BIOS_CONFIG _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE _TcgToken
S
_FWU_CONFIRM_LIVE_PING_MSG _FWU_GET_UPDATE_DATA_EXTENSION_MSG _VERSION
EFI_I2C_REQUEST_PACKET _FWU_DATA_MSG _FWU_GET_VERSION_MSG_REPLY
EFI_SMM_CPU_STATE SOFTWARE_GUARD_STATUS _FWU_END_MESSAGE _FWU_IMAGE_COMPATABILITY_CHECK_MSG
EFI_SMM_CPU_STATE32
V
_FWU_FLASH_IMAGE_START_MSG_REPLY _FWU_INVALID_MSG_REPLY
EFI_SMM_CPU_STATE64 _FWU_GET_FEATURE_STATE_MSG_REPLY _FWU_START_MSG
EFI_USB_INTERFACE_INFO VARIABLE_HEADER _FWU_GET_FWU_INFO_STATUS_MSG _FWU_VERIFY_OEMID_MSG
EPC_OS_CONFIG VARIABLE_STORE_HEADER _FWU_GET_INFO_MSG _FWU_VERIFY_PWD_MSG
F
_
_FWU_GET_IPU_PT_ATTRB_MSG _ME_FWU_INFO_MSG
FWU_DATA_MESSAGE _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
A | E | F | M | S | V | _


IceLake Platform Sample Code: Class Members

  • Class List
  • Class Index
  • Class Members
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • h
  • i
  • m
  • n
  • p
  • r
  • s
  • t
  • v
  • w
Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • AllocatedEpcSize : _EPC_BIOS_CONFIG
  • Attributes : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- b -

  • buffer : _TcgCreateStruct , _TcgParseStruct
  • bufferSize : _TcgCreateStruct , _TcgParseStruct
  • BusFrequencySet : _EFI_I2C_MASTER_PROTOCOL

- c -

  • comPacket : _TcgCreateStruct , _TcgParseStruct
  • CpuSaveState : _EFI_SMM_CPU_SAVE_STATE_PROTOCOL
  • curPacket : _TcgCreateStruct , _TcgParseStruct
  • curPtr : _TcgParseStruct
  • curSubPacket : _TcgCreateStruct , _TcgParseStruct

- d -

  • DataSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • dryRun : _TcgCreateStruct

- e -

  • EnableI2cBusConfiguration : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
  • EpcMap : _EPC_BIOS_CONFIG

- f -

  • Format : VARIABLE_STORE_HEADER

- h -

  • hdrStart : _TcgToken
  • Hs400DataValid : _PLATFORM_EMMC_TUNING_DATA
  • Hs400RxStrobe1Dll : _PLATFORM_EMMC_TUNING_DATA
  • Hs400TxDataDll : _PLATFORM_EMMC_TUNING_DATA

- i -

  • I2cBusConfigurationCount : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

- m -

  • MaxEpcSize : _EPC_BIOS_CONFIG
  • MaximumReceiveBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTotalBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTransmitBytes : _EFI_I2C_MASTER_PROTOCOL
  • MonotonicCount : AUTHENTICATED_VARIABLE_HEADER

- n -

  • NameSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- p -

  • PubKeyIndex : AUTHENTICATED_VARIABLE_HEADER

- r -

  • ReadBuffer : EFI_I2C_REQUEST_PACKET
  • ReadBytes : EFI_I2C_REQUEST_PACKET
  • RequestedEpcSize : EPC_OS_CONFIG
  • Reserved : SOFTWARE_GUARD_STATUS
  • Reset : _EFI_I2C_MASTER_PROTOCOL

- s -

  • SgxStatus : SOFTWARE_GUARD_STATUS
  • Signature : VARIABLE_STORE_HEADER
  • Size : VARIABLE_STORE_HEADER
  • StartId : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • StartRequest : _EFI_I2C_MASTER_PROTOCOL
  • State : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER , VARIABLE_STORE_HEADER
  • SupportedPrmBins : _EPC_BIOS_CONFIG

- t -

  • Timeout : EFI_I2C_REQUEST_PACKET
  • TimeStamp : AUTHENTICATED_VARIABLE_HEADER
  • type : _TcgToken

- v -

  • VendorGuid : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- w -

  • WriteBuffer : EFI_I2C_REQUEST_PACKET
  • WriteBytes : EFI_I2C_REQUEST_PACKET


IceLake Platform Sample Code: Class Members - Variables

  • Class List
  • Class Index
  • Class Members
  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • h
  • i
  • m
  • n
  • p
  • r
  • s
  • t
  • v
  • w

- a -

  • AllocatedEpcSize : _EPC_BIOS_CONFIG
  • Attributes : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- b -

  • buffer : _TcgCreateStruct , _TcgParseStruct
  • bufferSize : _TcgCreateStruct , _TcgParseStruct
  • BusFrequencySet : _EFI_I2C_MASTER_PROTOCOL

- c -

  • comPacket : _TcgCreateStruct , _TcgParseStruct
  • CpuSaveState : _EFI_SMM_CPU_SAVE_STATE_PROTOCOL
  • curPacket : _TcgCreateStruct , _TcgParseStruct
  • curPtr : _TcgParseStruct
  • curSubPacket : _TcgCreateStruct , _TcgParseStruct

- d -

  • DataSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • dryRun : _TcgCreateStruct

- e -

  • EnableI2cBusConfiguration : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
  • EpcMap : _EPC_BIOS_CONFIG

- f -

  • Format : VARIABLE_STORE_HEADER

- h -

  • hdrStart : _TcgToken
  • Hs400DataValid : _PLATFORM_EMMC_TUNING_DATA
  • Hs400RxStrobe1Dll : _PLATFORM_EMMC_TUNING_DATA
  • Hs400TxDataDll : _PLATFORM_EMMC_TUNING_DATA

- i -

  • I2cBusConfigurationCount : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

- m -

  • MaxEpcSize : _EPC_BIOS_CONFIG
  • MaximumReceiveBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTotalBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTransmitBytes : _EFI_I2C_MASTER_PROTOCOL
  • MonotonicCount : AUTHENTICATED_VARIABLE_HEADER

- n -

  • NameSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- p -

  • PubKeyIndex : AUTHENTICATED_VARIABLE_HEADER

- r -

  • ReadBuffer : EFI_I2C_REQUEST_PACKET
  • ReadBytes : EFI_I2C_REQUEST_PACKET
  • RequestedEpcSize : EPC_OS_CONFIG
  • Reserved : SOFTWARE_GUARD_STATUS
  • Reset : _EFI_I2C_MASTER_PROTOCOL

- s -

  • SgxStatus : SOFTWARE_GUARD_STATUS
  • Signature : VARIABLE_STORE_HEADER
  • Size : VARIABLE_STORE_HEADER
  • StartId : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • StartRequest : _EFI_I2C_MASTER_PROTOCOL
  • State : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER , VARIABLE_STORE_HEADER
  • SupportedPrmBins : _EPC_BIOS_CONFIG

- t -

  • Timeout : EFI_I2C_REQUEST_PACKET
  • TimeStamp : AUTHENTICATED_VARIABLE_HEADER
  • type : _TcgToken

- v -

  • VendorGuid : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- w -

  • WriteBuffer : EFI_I2C_REQUEST_PACKET
  • WriteBytes : EFI_I2C_REQUEST_PACKET


IceLake Platform Sample Code: File List

  • File List
  • File Members
File List
Here is a list of all documented files with brief descriptions:
_Default_BusNumberTranslator.h | Copyright (c) 2011, Intel Corporation
_Default_MpTableData.h | Copyright (c) 2011, Intel Corporation
_Default_PirqTableData.h | Copyright (c) 2011, Intel Corporation
_Rvp_BusNumberTranslator.h | Copyright (c) 2011, Intel Corporation
_Rvp_MpTableData.h | Copyright (c) 2011, Intel Corporation
_Rvp_PirqTableData.h | Copyright (c) 2011, Intel Corporation
_RvpDt_BusNumberTranslator.h | Copyright (c) 2011, Intel Corporation
_RvpDt_MpTableData.h | Copyright (c) 2011, Intel Corporation
_RvpDt_PirqTableData.h | Copyright (c) 2011, Intel Corporation
_RvpM_BusNumberTranslator.h | Copyright (c) 2011, Intel Corporation
_RvpM_MpTableData.h | Copyright (c) 2011, Intel Corporation
_RvpM_PirqTableData.h | Copyright (c) 2011, Intel Corporation
_Sds_BusNumberTranslator.h | Copyright (c) 2011, Intel Corporation
_Sds_MpTableData.h | Copyright (c) 2011, Intel Corporation
_Sds_PirqTableData.h | Copyright (c) 2011, Intel Corporation
AcpiCommon.h | Header file for ACPI common Initialization Driver
AcpiPlatform.c | ACPI Platform Driver
AcpiPlatform.h | This is an implementation of the ACPI platform driver
AcpiVariable.h |
AmtPolicyInitDxe.c | This file is SampleCode for Intel AMT DXE Policy initialization
AmtPolicyInitDxe.h | Header file for the AmtPolicyInitDxe Driver
AmtWrapperProtocol.h | The header file includes the definition of EFI_SPI_PROTOCOL
AttemptUsbFirst.h |
BaseCryptLib.h | Defines base cryptographic library APIs
BaseEcFlashLib.h |
BasePlatformVariableLib.h |
BoardConfigLib.h | Function prototype of BoardConfigLib
BootGuardRevocationLib.h | Header file for Boot Guard revocation notification
Build.h |
CeAta.h |
Common.h |
CommonDefinitions.h |
CpuPolicyInitDxe.c | This file is SampleCode for Intel Silicon DXE Platform Policy initialzation
CpuPolicyInitDxe.h | Header file for the SiliconPolicyInitDxe Driver
CpuSmm.h |
cse_basic_def.h |
cse_basic_types.h |
CustomOptionControl.h |
DimmInfo.h | This header file provides Dimm info definitions used by other modules for dimm info presentation
DoxygenAcpi.h | This file contains doxygen commands definitions for creating quality platform documentation
DoxygenPlat.h | This file contains doxygen commands definitions for creating platform sample documentation
DoxygenRpOverride.h | This file contains doxygen commands definitions for creating Platform override documentation
DsAllocation.h |
DsConfig.h |
DxeAcpiGnvsInitLib.h | Acpi Gnvs Init Library header file
DxeAmtPolicyUpdateLib.h |
DxeCpuPolicyUpdateLib.h |
DxeFirmwareVersionInfoLib.h | Private data structures
DxeMePolicyUpdateLib.h |
DxeOpromPatchLib.h |
DxePchPolicyUpdateLib.h |
DxePlatformBootManagerLib.h | Header file for DxePlatformBootManagerLib
DxePolicyBoardConfigLib.h | Header file for the DxePolicyBoardConfig Library
DxePolicyUpdateProtocol.h |
DxeSaPolicyUpdateLib.h |
DxeSmmAcpiCustomLib.h | This header file provides platform specific definitions used by other modules for platform specific initialization
DxeSmmInternalGraphicDeviceLib.h |
DxeTbtPolicyUpdateLib.h |
EcAccess.h |
EcCommands.h |
Ecdt.h | This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT)
EcHwLib.h | EC hardware library functions and definitions
EcLib.h | EC library functions and definitions
EcMiscLib.h | EC miscellaneous library functions
EcPlatformInitDxe.c | Source code file for the Platform Init DXE module
EcTcssLib.h | EC TCSS library functions
Efi.h |
EfiUsbFnIo.h | EFI USB function IO Protocol This protocol supports Usb Function IO API
EmmcCardInfoProtocol.h |
Facs.h | This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS)
Fadt6.1.h | This file describes the contents of the ACPI Fixed ACPI Description Table (FADT)
FirwmareConfigurations.h | This header file provides definitions of firmware configuration
FspPolicyInitLib.h | Function prototype of FspPolicyInitLib
Fwu_Common.h |
FWUpdateLib.h |
GfxInt15Interface.c | This is a driver to produce Int15 hook
GopPolicyInitDxe.c | This file initialises and Installs GopPolicy Protocol
GopPolicyInitDxe.h | Header file for the GopPolicyInitDxe Driver
GpioExpanderLib.h | Support for IO expander TCA6424
HidI2cPlatformSupportLib.h | Support for IO expander TCA6424
Hpet.h | This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET)
HstiIbvFeatureBit.h | This file contains various definitions for IHV HSTI implementation including error string definitions
I2cAccessLib.h | Support for IO expander TCA6424
I2cBusConfigurationManagement.h | I2C bus configuration management interface
I2cMaster.h | I2C Master interface
I2cMmioConfigLib.h | Memory mapped I/O specific configuration declarations
IccOverClocking.h |
IccSetupData.h |
Madt.h | This file describes the contents of the ACPI Multiple APIC Description Table (MADT)
Mcfg.h | This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG)
me_status.h |
MePolicyInitDxe.c | This file is SampleCode for Intel ME DXE Policy initialization
MePolicyInitDxe.h | Header file for the MePolicyInitDxe Driver
mkhi_hdrs.h |
Mmc.h | Header file for Industry MMC 4.2 spec
MofSampleDev.h |
MofTestDev.h |
MultiPlatSupport.h |
MultiPlatSupportLib.h |
OcSetupVariable.h | Variable definition for overclocking support
OemSetup.h | OEM Specific Setup Variables and Structures
OverClockPpi.h |
PcdInitDxe.c | Driver for initializing platform dynamic PCDs
PchPolicyInitDxe.c | This file is SampleCode for PCH DXE Policy initialization
PchPolicyInitDxe.h | Header file for the PchPolicyInitDxe Driver
PdtUpdateLib.h |
PeiBootGuardEventLogLib.h | This file contains functions for creating TPM Event Log
PeiCpuPolicyDebugLib.h | SampleCode header file of the library for Intel CPU PEI Debug Policy initialization
PeiDxeBoardIdsLib.h | Header file for Board Information boot time changes
PeiPchPolicyDebugLib.h | SampleCode header file of the library for Intel PCH PEI Debug Policy initialization
PeiPlatformLib.h |
PeiPlatformRecoveryLib.h | This library provides platform recovery module
PeiPolicyBoardConfigLib.h | Header file for the PeiPolicyBoardConfig Library
PeiPolicyInitLib.h | Header file for the PolicyInitPei Library
PeiReadWriteVariableLib.h |
PeiSaPolicyDebugLib.h | SampleCode header file of the library for Intel SA PEI Debug Policy initialization
PeiSiPolicyDebugLib.h | SampleCode header file of the library for Intel SI PEI Debug Policy initialization
PeiSwbpeLib.h |
PeiWdtAppLib.h | PEI WDT App library definitions
Platform.h | This header file provides platform specific definitions used by other modules for platform specific initialization
PlatformBoardConfig.h | Header file for Platform Boards Configurations
PlatformBoardId.h | Defines Platform BoardIds
PlatformClock.h |
PlatformConfigurationChangeVariable.h | Platform configuration change variable definitions
PlatformEmmcHs400Info.h | GUID used for Platform Emmc Hs400 Tuning Info NVRAM Data
PlatformGlobalVariable.h | GUID for Platform (NVRAM) Variables
PlatformInfo.h | GUID used for Platform Info Data entries in the HOB list
PlatformInit.c | Source code file for Platform Init PEI module
PlatformInitDxe.c | Source code file for the Platform Init DXE module
PlatformInitDxe.h | Platform Info Driver
PlatformInitLib.h | Function prototype of PlatformInitLib
PlatformInitPreMem.c | Source code file for Platform Init Pre-Memory PEI module
PlatformNvRamHookLib.h | Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc
PlatformNvsArea.h | This file defines the Platform NVS Area Protocol
PlatformNvsAreaDef.h | ACPI DSDT table
PlatformOpRomTable.h |
PlatformOptionRomTable_Default.h |
PlatformOptionRomTable_Rvp.h |
PlatformOptionRomTable_RvpDt.h |
PlatformOptionRomTable_RvpM.h |
PlatformOptionRomTable_Sds.h |
PlatformPostCode.h |
PlatformSecureLib.h | Provides a secure platform-specific method to detect physically present user
PlatformSmmIoLib.h | This library provides SMM functions for IO and PCI IO access
PolicyInitDxe.c | This file is a wrapper for Platform Policy driver
PolicyInitDxe.h | Header file for the PolicyInitDxe Driver
PttInstance.h | GUID definition for the PTT device instance
PttPTPInstanceGuid.h | GUID definition for the PTT device instance
S3MemoryVariable.h |
SaPlatformInitDxe.c | Source code file for the Platform Init DXE module
SaPolicyInitDxe.c | This file is SampleCode for SA DXE Policy initialization
SaPolicyInitDxe.h | Header file for the SaPolicyInitDxe Driver
SdCard.h | Header file for Industry SD Card 2.0 spec
SdHostIo.h | Header file for interface definition of EFI_SD_HOST_IO_PROTOCOL
Setup.h |
SetupConfiguration.h | Default platform setup configuration settings
SetupVariable.h |
SiliconPolicyInitDxe.c | This file is SampleCode for Intel Silicon DXE Platform Policy initialzation
SiliconPolicyInitDxe.h | Header file for the SiliconPolicyInitDxe Driver
SioRegs.h |
SmbiosPlatformInfoDefault.h | This file contains Default data for Platform SMBIOS tables
SmbiosPlatformInfoDefinition.h | This file contains definition for Platform SMBIOS Info
SmmCpuSaveState.h | This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors
SmmStmConfTable.h | GUID definition for the Smm Stm Configuraion Table
SmmStmConfTableLib.h | Txt Protocol definition include file
SmmTxtResource.h | This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM
SmmTxtStmService.h | This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM
SoftwareGuardSetupData.h | Software Guard Setup Variables and Structures
SpiFlashCommon.h | The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib
StmDefinition.h | This file contains definitions required to use the TXT STM
Swbpe.h |
SysFwUpdatePlatformProtocol.h | Define the data structure and GUID of SysFwUpdatePlatform Protocol
SystemMonitor.h |
SystemNvDataGuid.h |
TbtPolicyInitDxe.c | This file is SampleCode for TBT DXE Policy initialization
TbtPolicyInitDxe.h | Header file for the TbtPolicyInitDxe Driver
Tcg.h | TCG defined values and structures used by the Tcg Core library
Tcg2ConfigHii.h | GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver
Tcg2ConfigNvData.h | Header file for NV data structure definition
Tcg2PhysicalPresenceLib.h | Ihis library is intended to be used by BDS modules
TcgCore.h | Public API for the Tcg Core library to perform the lowest level TCG data encoding
TcgSetup.h |
TcgUtil.h | Provides TCG high-level API to perform common TCG actions on a TCG data packet
TcoWdtHob.h |
TxtOneTouch.h | This file contains definitions required for One-Touch function
TxtOneTouchOp.h | Txt specific PPI operation definition
typedef.h |
UsbDeviceLib.h | Header file for USBFN library definition
UsbDeviceModeProtocol.h | Header file for definition of USBFN device mode protocol
ver.h | Contains definitions of the MAJOR, MINOR, & HOTFIX versions used throughout the code


IceLake Platform Sample Code: _Default_BusNumberTranslator.h File Reference

  • Include
  • MultiPlatform
_Default_BusNumberTranslator.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Default_BusNumberTranslator.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Default_MpTableData.h File Reference

  • MultiPlatform
_Default_MpTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Default_MpTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Default_PirqTableData.h File Reference

  • MultiPlatform
_Default_PirqTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Default_PirqTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Rvp_BusNumberTranslator.h File Reference

  • MultiPlatform
_Rvp_BusNumberTranslator.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Rvp_BusNumberTranslator.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Rvp_MpTableData.h File Reference

  • MultiPlatform
_Rvp_MpTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Rvp_MpTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Rvp_PirqTableData.h File Reference

  • MultiPlatform
_Rvp_PirqTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

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Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Rvp_PirqTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpDt_BusNumberTranslator.h File Reference

  • MultiPlatform
_RvpDt_BusNumberTranslator.h File Reference

Copyright (c) 2011, Intel Corporation. More...

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Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _RvpDt_BusNumberTranslator.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpDt_MpTableData.h File Reference

  • MultiPlatform
_RvpDt_MpTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

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Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _RvpDt_MpTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpDt_PirqTableData.h File Reference

  • MultiPlatform
_RvpDt_PirqTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

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Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _RvpDt_PirqTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpM_BusNumberTranslator.h File Reference

  • MultiPlatform
_RvpM_BusNumberTranslator.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _RvpM_BusNumberTranslator.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpM_MpTableData.h File Reference

  • MultiPlatform
_RvpM_MpTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _RvpM_MpTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpM_PirqTableData.h File Reference

  • MultiPlatform
_RvpM_PirqTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _RvpM_PirqTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Sds_BusNumberTranslator.h File Reference

  • MultiPlatform
_Sds_BusNumberTranslator.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Sds_BusNumberTranslator.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Sds_MpTableData.h File Reference

  • MultiPlatform
_Sds_MpTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Sds_MpTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Sds_PirqTableData.h File Reference

  • MultiPlatform
_Sds_PirqTableData.h File Reference

Copyright (c) 2011, Intel Corporation. More...

Go to the source code of this file.

Detailed Description

Copyright (c) 2011, Intel Corporation.

All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file _Sds_PirqTableData.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AcpiCommon.h File Reference

  • Acpi
  • AcpiTables
  • Include
AcpiCommon.h File Reference

Header file for ACPI common Initialization Driver. More...

Go to the source code of this file.

Detailed Description

Header file for ACPI common Initialization Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiCommon.h.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AcpiPlatform.c File Reference

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe
Functions
AcpiPlatform.c File Reference

ACPI Platform Driver. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/HobLib.h>
#include <Guid/HobList.h>
#include <Protocol/FirmwareVolume2.h>
#include <PlatformBoardId.h>
#include <IndustryStandard/AcpiAml.h>
#include <IndustryStandard/Pci30.h>
#include "AcpiPlatform.h"
#include <Protocol/CpuNvsArea.h>
#include <Library/PciSegmentLib.h>
#include <Library/PchInfoLib.h>
#include <Library/PchPcieRpLib.h>
#include <Library/PchSerialIoLib.h>
#include <Library/GpioLib.h>
#include <Library/PchEspiLib.h>
#include <MeBiosPayloadHob.h>
#include <PlatformBoardConfig.h>
#include <Board/Include/BoardHook.h>
#include <Library/CpuPlatformLib.h>
#include <PlatformBoardType.h>
#include <PlatformInfo.h>
#include <Guid/S3MemoryVariable.h>
#include <Protocol/VariableLock.h>
#include <Mcfg.h>
#include <SaTcssHob.h>
Include dependency graph for AcpiPlatform.c:

Go to the source code of this file.

Functions

VOID | InstallXhciAcpiTable (VOID)
Install Xhci ACPI Table.
EFI_STATUS | LocateSupportProtocol (IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol. More...
UINT32 | GetEcGpeNumber (VOID)
This function will provide the EC GPE number for ECDT update according to platform design. More...
EFI_STATUS | PlatformUpdateTables (IN OUT EFI_ACPI_COMMON_HEADER *Table, IN OUT EFI_ACPI_TABLE_VERSION *Version)
This function will update any runtime platform specific information. More...
VOID | IsHardwareChange (VOID)
This function calculates RCR based on PCI Device ID and Vendor ID from the devices available on the platform. More...
EFI_STATUS | AllocateMemoryBelow4G (IN EFI_MEMORY_TYPE MemoryType, IN UINTN Size, OUT VOID **Buffer)
Allocate MemoryType below 4G memory address. More...
EFI_STATUS | GuidStringToAcpiBuffer (IN CHAR16 *GuidString, OUT UINT64 *AcpiGuidPart1, OUT UINT64 *AcpiGuidPart2)
Convert string containing GUID in the canonical form: "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp" where aa - pp are unicode hexadecimal digits to the buffer format to be used in ACPI, byte ordering: [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7] [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16]. More...
EFI_STATUS | SetAcpiSetupVariables (VOID)
Save Acpi Setup relatived variables. More...
EFI_STATUS | InstallAcpiPlatform (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
ACPI Platform driver installation function. More...
EFI_STATUS | SortCpuLocalApicInTable (IN EFI_MP_SERVICES_PROTOCOL *MpService, IN UINTN NumberOfCPUs, IN UINTN NumberOfEnabledCPUs)
Sort ordering of CPUs according to the priorities of cores and threads. More...
EFI_STATUS | WaitInputEmpty (IN UINTN Timeout)
I/O work flow to wait input buffer empty in given time. More...
EFI_STATUS | WaitOutputFull (IN UINTN Timeout)
I/O work flow to wait output buffer full in given time. More...
EFI_STATUS | In8042AuxData (IN OUT UINT8 *Data)
I/O work flow of in 8042 Aux data. More...
EFI_STATUS | Out8042AuxCommand (IN UINT8 Command)
I/O work flow of outing 8042 Aux command. More...
EFI_STATUS | PS2MouseEnable (VOID)
Issue command to enable Ps2 mouse. More...
BOOLEAN | IsPs2MouseConnected (VOID)
Check whether there is Ps/2 mouse device in system. More...

Detailed Description

ACPI Platform Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiPlatform.c.

Function Documentation

EFI_STATUS AllocateMemoryBelow4G | ( | IN EFI_MEMORY_TYPE | MemoryType,
 |  | IN UINTN | Size,
 |  | OUT VOID ** | Buffer
 | ) |  |

Allocate MemoryType below 4G memory address.

Parameters
[in] | Size | - Size of memory to allocate.
[in] | Buffer | - Allocated address for output.
Return values
EFI_SUCCESS | - Memory successfully allocated.
Other | - Other errors occur.

Definition at line 2190 of file AcpiPlatform.c.

UINT32 GetEcGpeNumber ( VOID )

This function will provide the EC GPE number for ECDT update according to platform design.

Return values
EcGpeNumber EC GPE number to be reported in ECDT

Definition at line 424 of file AcpiPlatform.c.

EFI_STATUS GuidStringToAcpiBuffer | ( | IN CHAR16 * | GuidString,
 |  | OUT UINT64 * | AcpiGuidPart1,
 |  | OUT UINT64 * | AcpiGuidPart2
 | ) |  |

Convert string containing GUID in the canonical form: "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp" where aa - pp are unicode hexadecimal digits to the buffer format to be used in ACPI, byte ordering: [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7] [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16].

Parameters
[in] | GuidString | - GUID String null terminated (aligned on a 16-bit boundary)
[out] | AcpiGuidPart1 | - First half of buffer (bytes 0 - 7)
[out] | AcpiGuidPart2 | - Second half of buffer (bytes 8 - 16)
Return values
EFI_SUCCESS | - String converted successfully.
EFI_UNSUPPORTED | - Wrong input string format.

Definition at line 2341 of file AcpiPlatform.c.

EFI_STATUS In8042AuxData ( IN OUT UINT8 * Data )

I/O work flow of in 8042 Aux data.

Parameters
Data Buffer holding return value.
Return values
EFI_SUCCESS | Success to excute I/O work flow
EFI_TIMEOUT | Keyboard controller time out.

Definition at line 4034 of file AcpiPlatform.c.

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EFI_STATUS InstallAcpiPlatform | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

ACPI Platform driver installation function.

Entry point of the ACPI platform driver.

Parameters
[in] | ImageHandle | Handle for this drivers loaded image protocol.
[in] | SystemTable | EFI system table.
Return values
EFI_SUCCESS | The driver installed without error.
EFI_ABORTED | The driver encountered an error and could not complete installation of the ACPI tables.

Get SaTcssHob HOB

Definition at line 2462 of file AcpiPlatform.c.

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VOID IsHardwareChange ( VOID )

This function calculates RCR based on PCI Device ID and Vendor ID from the devices available on the platform.

It also includes other instances of BIOS change to calculate CRC and provides as HWSignature filed in FADT table.

Definition at line 1994 of file AcpiPlatform.c.

BOOLEAN IsPs2MouseConnected ( VOID )

Check whether there is Ps/2 mouse device in system.

Return values
TRUE | - Keyboard in System.
FALSE | - Keyboard not in System.

Definition at line 4149 of file AcpiPlatform.c.

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EFI_STATUS LocateSupportProtocol | ( | IN EFI_GUID * | Protocol,
 |  | IN EFI_GUID | gEfiAcpiMultiTableStorageGuid,
 |  | OUT VOID ** | Instance,
 |  | IN BOOLEAN | Type
 | ) |  |

Locate the first instance of a protocol.

If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table storage file.

Parameters
[in] | Protocol | The protocol to find.
[in] | Instance | Return pointer to the first instance of the protocol.
[in] | Type | TRUE if the desired protocol is a FV protocol.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The protocol could not be located.
EFI_OUT_OF_RESOURCES | There are not enough resources to find the protocol.

Definition at line 295 of file AcpiPlatform.c.

EFI_STATUS Out8042AuxCommand ( IN UINT8 Command )

I/O work flow of outing 8042 Aux command.

Parameters
Command Aux I/O command
Return values
EFI_SUCCESS | Success to excute I/O work flow
EFI_TIMEOUT | Keyboard controller time out.

Definition at line 4062 of file AcpiPlatform.c.

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EFI_STATUS PlatformUpdateTables | ( | IN OUT EFI_ACPI_COMMON_HEADER * | Table,
 |  | IN OUT EFI_ACPI_TABLE_VERSION * | Version
 | ) |  |

This function will update any runtime platform specific information.

This currently includes: Setting OEM table values, ID, table ID, creator ID and creator revision. Enabling the proper processor entries in the APIC tables It also indicates with which ACPI table version the table belongs.

Parameters
[in] | Table | The table to update
[in] | Version | Where to install this table
Return values
EFI_SUCCESS Updated tables commplete.

Definition at line 460 of file AcpiPlatform.c.

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EFI_STATUS PS2MouseEnable ( VOID )

Issue command to enable Ps2 mouse.

Returns
Status of command issuing.

Definition at line 4131 of file AcpiPlatform.c.

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EFI_STATUS SetAcpiSetupVariables ( VOID )

Save Acpi Setup relatived variables.

Locate table with matching ID

Definition at line 2398 of file AcpiPlatform.c.

EFI_STATUS SortCpuLocalApicInTable | ( | IN EFI_MP_SERVICES_PROTOCOL * | MpService,
 |  | IN UINTN | NumberOfCPUs,
 |  | IN UINTN | NumberOfEnabledCPUs
 | ) |  |

Sort ordering of CPUs according to the priorities of cores and threads.

ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core

Parameters
[in] | MpService | The MP servicde protocol (used to retrievel MP info)
[in] | NumberOfCPUs | Number of CPUs
[in] | NumberOfEnabledCPUs | Number of Enabled CPUs.
Return values
EFI_SUCCESS The driver installed without error.

Definition at line 3761 of file AcpiPlatform.c.

EFI_STATUS WaitInputEmpty ( IN UINTN Timeout )

I/O work flow to wait input buffer empty in given time.

Parameters
[in] Timeout Wating time.
Return values
EFI_TIMEOUT | if input is still not empty in given time.
EFI_SUCCESS | input is empty.

Definition at line 3955 of file AcpiPlatform.c.

EFI_STATUS WaitOutputFull ( IN UINTN Timeout )

I/O work flow to wait output buffer full in given time.

Parameters
[in] Timeout given time
Return values
EFI_TIMEOUT | output is not full in given time
EFI_SUCCESS | output is full in given time.

Definition at line 3994 of file AcpiPlatform.c.

Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AcpiPlatform.h File Reference

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe
Functions
AcpiPlatform.h File Reference

This is an implementation of the ACPI platform driver. More...

#include <IndustryStandard/Acpi.h>
#include <Guid/EventGroup.h>
#include <Guid/GlobalVariable.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Protocol/CpuIo2.h>
#include <Protocol/AcpiTable.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/MpService.h>
#include <Register/Cpuid.h>
#include <CpuAccess.h>
#include <PchAccess.h>
#include <Protocol/PciIo.h>
#include <Library/PchCycleDecodingLib.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
#include <Library/DxeAcpiGnvsInitLib.h>
#include <Protocol/PlatformNvsArea.h>
#include <Protocol/TbtNvsArea.h>
#include <Platform.h>
#include <Library/AslUpdateLib.h>
#include <SetupVariable.h>
#include <Library/EcMiscLib.h>
#include <Acpi/AcpiTables/Fadt/Fadt6.1.h>
#include <TbtBoardInfo.h>
Include dependency graph for AcpiPlatform.h:
This graph shows which files directly or indirectly include this file:

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Functions

EFI_STATUS | LocateSupportProtocol (IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol. More...
EFI_STATUS | InstallAcpiPlatform (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point of the ACPI platform driver. More...
EFI_STATUS | SortCpuLocalApicInTable (IN EFI_MP_SERVICES_PROTOCOL *MpService, IN UINTN NumberOfCPUs, IN UINTN NumberOfEnabledCPUs)
Sort ordering of CPUs according to the priorities of cores and threads. More...
BOOLEAN | IsPs2MouseConnected (VOID)
Check whether there is Ps/2 mouse device in system. More...

Detailed Description

This is an implementation of the ACPI platform driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiPlatform.h.

Function Documentation

EFI_STATUS InstallAcpiPlatform | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Entry point of the ACPI platform driver.

Parameters
[in] | ImageHandle | A handle for the image that is initializing this driver
[in] | SystemTable | A pointer to the EFI system table
Return values
EFI_SUCCESS | The driver installed without error.
EFI_ABORTED | The driver encountered an error and could not complete installation of the ACPI tables.

Entry point of the ACPI platform driver.

Parameters
[in] | ImageHandle | Handle for this drivers loaded image protocol.
[in] | SystemTable | EFI system table.
Return values
EFI_SUCCESS | The driver installed without error.
EFI_ABORTED | The driver encountered an error and could not complete installation of the ACPI tables.

Get SaTcssHob HOB

Definition at line 2462 of file AcpiPlatform.c.

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BOOLEAN IsPs2MouseConnected ( VOID )

Check whether there is Ps/2 mouse device in system.

Return values
TRUE | - Keyboard in System.
FALSE | - Keyboard not in System.

Definition at line 4149 of file AcpiPlatform.c.

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EFI_STATUS LocateSupportProtocol | ( | IN EFI_GUID * | Protocol,
 |  | IN EFI_GUID | gEfiAcpiMultiTableStorageGuid,
 |  | OUT VOID ** | Instance,
 |  | IN BOOLEAN | Type
 | ) |  |

Locate the first instance of a protocol.

If the protocol requested is an FV protocol, then it will return the first FV that contains the ACPI table storage file.

Parameters
[in] | Protocol | The protocol to find.
[in] | Instance | Return pointer to the first instance of the protocol.
[in] | Type | TRUE if the desired protocol is a FV protocol.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The protocol could not be located.
EFI_OUT_OF_RESOURCES | There are not enough resources to find the protocol.

Definition at line 295 of file AcpiPlatform.c.

EFI_STATUS SortCpuLocalApicInTable | ( | IN EFI_MP_SERVICES_PROTOCOL * | MpService,
 |  | IN UINTN | NumberOfCPUs,
 |  | IN UINTN | NumberOfEnabledCPUs
 | ) |  |

Sort ordering of CPUs according to the priorities of cores and threads.

ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core

Parameters
[in] | MpService | The MP servicde protocol (used to retrievel MP info)
[in] | NumberOfCPUs | Number of CPUs
[in] | NumberOfEnabledCPUs | Number of Enabled CPUs.
Return values
EFI_SUCCESS The driver installed without error.

Definition at line 3761 of file AcpiPlatform.c.


IceLake Platform Sample Code: AcpiVariable.h File Reference

  • Guid
AcpiVariable.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiVariable.h.


IceLake Platform Sample Code: AmtPolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
AmtPolicyInitDxe.c File Reference

This file is SampleCode for Intel AMT DXE Policy initialization. More...

#include "AmtPolicyInitDxe.h"
Include dependency graph for AmtPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS AmtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy. More...

Detailed Description

This file is SampleCode for Intel AMT DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AmtPolicyInitDxe.c.

Function Documentation

EFI_STATUS AmtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize Intel AMT DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file AmtPolicyInitDxe.c.

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IceLake Platform Sample Code: AmtPolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
AmtPolicyInitDxe.h File Reference

Header file for the AmtPolicyInitDxe Driver. More...

#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/MePolicy.h>
#include <Protocol/AmtPolicy.h>
#include <Library/DxeAmtPolicyLib.h>
#include <Library/DxePolicyBoardConfigLib.h>
#include <Library/DxeAmtPolicyUpdateLib.h>
Include dependency graph for AmtPolicyInitDxe.h:
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Functions

EFI_STATUS AmtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy. More...

Detailed Description

Header file for the AmtPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AmtPolicyInitDxe.h.

Function Documentation

EFI_STATUS AmtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize Intel AMT DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.
Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file AmtPolicyInitDxe.c.

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IceLake Platform Sample Code: AmtWrapperProtocol.h File Reference

  • Protocol
AmtWrapperProtocol.h File Reference

The header file includes the definition of EFI_SPI_PROTOCOL. More...

Go to the source code of this file.

Detailed Description

The header file includes the definition of EFI_SPI_PROTOCOL.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AmtWrapperProtocol.h.


IceLake Platform Sample Code: AttemptUsbFirst.h File Reference

AttemptUsbFirst.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AttemptUsbFirst.h.


IceLake Platform Sample Code: BaseCryptLib.h File Reference

  • Library
Macros | Enumerations | Functions
BaseCryptLib.h File Reference

Defines base cryptographic library APIs. More...

Go to the source code of this file.

Macros

#define | MD5_DIGEST_SIZE 16
MD5 digest size in bytes.
#define | SHA1_DIGEST_SIZE 20
SHA-1 digest size in bytes.
#define | SHA256_DIGEST_SIZE 32
SHA-256 digest size in bytes.
#define | TDES_BLOCK_SIZE 8
TDES block size in bytes.
#define | AES_BLOCK_SIZE 16
AES block size in bytes.

Enumerations

enum RSA_KEY_TAG
RSA Key Tags Definition used in RsaSetKey() function for key component identification. More...

Functions

UINTN | Md5GetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for MD5 hash operations. More...
BOOLEAN | Md5Init (OUT VOID *Md5Context)
Initializes user-supplied memory pointed by Md5Context as MD5 hash context for subsequent use. More...
BOOLEAN | Md5Duplicate (IN CONST VOID *Md5Context, OUT VOID *NewMd5Context)
Makes a copy of an existing MD5 context. More...
BOOLEAN | Md5Update (IN OUT VOID *Md5Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates MD5 context. More...
BOOLEAN | Md5Final (IN OUT VOID *Md5Context, OUT UINT8 *HashValue)
Completes computation of the MD5 digest value. More...
UINTN | Sha1GetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for SHA-1 hash operations. More...
BOOLEAN | Sha1Init (OUT VOID *Sha1Context)
Initializes user-supplied memory pointed by Sha1Context as SHA-1 hash context for subsequent use. More...
BOOLEAN | Sha1Duplicate (IN CONST VOID *Sha1Context, OUT VOID *NewSha1Context)
Makes a copy of an existing SHA-1 context. More...
BOOLEAN | Sha1Update (IN OUT VOID *Sha1Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates SHA-1 context. More...
BOOLEAN | Sha1Final (IN OUT VOID *Sha1Context, OUT UINT8 *HashValue)
Completes computation of the SHA-1 digest value. More...
UINTN | Sha256GetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for SHA-256 hash operations. More...
BOOLEAN | Sha256Init (OUT VOID *Sha256Context)
Initializes user-supplied memory pointed by Sha256Context as SHA-256 hash context for subsequent use. More...
BOOLEAN | Sha256Duplicate (IN CONST VOID *Sha256Context, OUT VOID *NewSha256Context)
Makes a copy of an existing SHA-256 context. More...
BOOLEAN | Sha256Update (IN OUT VOID *Sha256Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates SHA-256 context. More...
BOOLEAN | Sha256Final (IN OUT VOID *Sha256Context, OUT UINT8 *HashValue)
Completes computation of the SHA-256 digest value. More...
UINTN | HmacMd5GetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for HMAC-MD5 operations. More...
BOOLEAN | HmacMd5Init (OUT VOID *HmacMd5Context, IN CONST UINT8 *Key, IN UINTN KeySize)
Initializes user-supplied memory pointed by HmacMd5Context as HMAC-MD5 context for subsequent use. More...
BOOLEAN | HmacMd5Duplicate (IN CONST VOID *HmacMd5Context, OUT VOID *NewHmacMd5Context)
Makes a copy of an existing HMAC-MD5 context. More...
BOOLEAN | HmacMd5Update (IN OUT VOID *HmacMd5Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates HMAC-MD5 context. More...
BOOLEAN | HmacMd5Final (IN OUT VOID *HmacMd5Context, OUT UINT8 *HmacValue)
Completes computation of the HMAC-MD5 digest value. More...
UINTN | HmacSha1GetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for HMAC-SHA1 operations. More...
BOOLEAN | HmacSha1Init (OUT VOID *HmacSha1Context, IN CONST UINT8 *Key, IN UINTN KeySize)
Initializes user-supplied memory pointed by HmacSha1Context as HMAC-SHA1 context for subsequent use. More...
BOOLEAN | HmacSha1Duplicate (IN CONST VOID *HmacSha1Context, OUT VOID *NewHmacSha1Context)
Makes a copy of an existing HMAC-SHA1 context. More...
BOOLEAN | HmacSha1Update (IN OUT VOID *HmacSha1Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates HMAC-SHA1 context. More...
BOOLEAN | HmacSha1Final (IN OUT VOID *HmacSha1Context, OUT UINT8 *HmacValue)
Completes computation of the HMAC-SHA1 digest value. More...
UINTN | TdesGetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for TDES operations. More...
BOOLEAN | TdesInit (OUT VOID *TdesContext, IN CONST UINT8 *Key, IN UINTN KeyLength)
Initializes user-supplied memory as TDES context for subsequent use. More...
BOOLEAN | TdesEcbEncrypt (IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs TDES encryption on a data buffer of the specified size in ECB mode. More...
BOOLEAN | TdesEcbDecrypt (IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs TDES decryption on a data buffer of the specified size in ECB mode. More...
BOOLEAN | TdesCbcEncrypt (IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs TDES encryption on a data buffer of the specified size in CBC mode. More...
BOOLEAN | TdesCbcDecrypt (IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs TDES decryption on a data buffer of the specified size in CBC mode. More...
UINTN | AesGetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for AES operations. More...
BOOLEAN | AesInit (OUT VOID *AesContext, IN CONST UINT8 *Key, IN UINTN KeyLength)
Initializes user-supplied memory as AES context for subsequent use. More...
BOOLEAN | AesEcbEncrypt (IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs AES encryption on a data buffer of the specified size in ECB mode. More...
BOOLEAN | AesEcbDecrypt (IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs AES decryption on a data buffer of the specified size in ECB mode. More...
BOOLEAN | AesCbcEncrypt (IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs AES encryption on a data buffer of the specified size in CBC mode. More...
BOOLEAN | AesCbcDecrypt (IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs AES decryption on a data buffer of the specified size in CBC mode. More...
UINTN | Arc4GetContextSize (VOID)
Retrieves the size, in bytes, of the context buffer required for ARC4 operations. More...
BOOLEAN | Arc4Init (OUT VOID *Arc4Context, IN CONST UINT8 *Key, IN UINTN KeySize)
Initializes user-supplied memory as ARC4 context for subsequent use. More...
BOOLEAN | Arc4Encrypt (IN OUT VOID *Arc4Context, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs ARC4 encryption on a data buffer of the specified size. More...
BOOLEAN | Arc4Decrypt (IN OUT VOID *Arc4Context, IN UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs ARC4 decryption on a data buffer of the specified size. More...
BOOLEAN | Arc4Reset (IN OUT VOID *Arc4Context)
Resets the ARC4 context to the initial state. More...
VOID * | RsaNew (VOID)
Allocates and initializes one RSA context for subsequent use. More...
VOID | RsaFree (IN VOID *RsaContext)
Release the specified RSA context. More...
BOOLEAN | RsaSetKey (IN OUT VOID *RsaContext, IN RSA_KEY_TAG KeyTag, IN CONST UINT8 *BigNumber, IN UINTN BnSize)
Sets the tag-designated key component into the established RSA context. More...
BOOLEAN | RsaGetKey (IN OUT VOID *RsaContext, IN RSA_KEY_TAG KeyTag, OUT UINT8 *BigNumber, IN OUT UINTN *BnSize)
Gets the tag-designated RSA key component from the established RSA context. More...
BOOLEAN | RsaGenerateKey (IN OUT VOID *RsaContext, IN UINTN ModulusLength, IN CONST UINT8 *PublicExponent, IN UINTN PublicExponentSize)
Generates RSA key components. More...
BOOLEAN | RsaCheckKey (IN VOID *RsaContext)
Validates key components of RSA context. More...
BOOLEAN | RsaPkcs1Sign (IN VOID *RsaContext, IN CONST UINT8 *MessageHash, IN UINTN HashSize, OUT UINT8 *Signature, IN OUT UINTN *SigSize)
Carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme. More...
BOOLEAN | RsaPkcs1Verify (IN VOID *RsaContext, IN CONST UINT8 *MessageHash, IN UINTN HashSize, IN UINT8 *Signature, IN UINTN SigSize)
Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in RSA PKCS#1. More...
BOOLEAN | Pkcs7Verify (IN CONST UINT8 *P7Data, IN UINTN P7Size, IN CONST UINT8 *TrustedCert, IN UINTN CertSize, IN CONST UINT8 *InData, IN UINTN DataSize)
Verifies the validility of a PKCS#7 signed data as described in "PKCS #7: Cryptographic Message Syntax Standard". More...
VOID * | DhNew (VOID)
Allocates and Initializes one Diffie-Hellman Context for subsequent use. More...
VOID | DhFree (IN VOID *DhContext)
Release the specified DH context. More...
BOOLEAN | DhGenerateParameter (IN OUT VOID *DhContext, IN UINTN Generator, IN UINTN PrimeLength, OUT UINT8 *Prime)
Generates DH parameter. More...
BOOLEAN | DhSetParameter (IN OUT VOID *DhContext, IN UINTN Generator, IN UINTN PrimeLength, IN CONST UINT8 *Prime)
Sets generator and prime parameters for DH. More...
BOOLEAN | DhGenerateKey (IN OUT VOID *DhContext, OUT UINT8 *PublicKey, IN OUT UINTN *PublicKeySize)
Generates DH public key. More...
BOOLEAN | DhComputeKey (IN OUT VOID *DhContext, IN CONST UINT8 *PeerPublicKey, IN UINTN PeerPublicKeySize, OUT UINT8 *Key, IN OUT UINTN *KeySize)
Computes exchanged common key. More...
BOOLEAN | RandomSeed (IN CONST UINT8 *Seed OPTIONAL, IN UINTN SeedSize)
Sets up the seed value for the pseudorandom number generator. More...
BOOLEAN | RandomBytes (OUT UINT8 *Output, IN UINTN Size)
Generates a pseudorandom byte stream of the specified size. More...

Detailed Description

Defines base cryptographic library APIs.

The Base Cryptographic Library provides implementations of basic cryptography primitives (Hash Serials, HMAC, RSA, Diffie-Hellman, etc) for UEFI security functionality enabling.

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BaseCryptLib.h.

Enumeration Type Documentation

enum RSA_KEY_TAG

RSA Key Tags Definition used in RsaSetKey() function for key component identification.

Enumerator
RsaKeyN | RSA public Modulus (N)
RsaKeyE | RSA Public exponent (e)
RsaKeyD | RSA Private exponent (d)
RsaKeyP | RSA secret prime factor of Modulus (p)
RsaKeyQ | RSA secret prime factor of Modules (q)
RsaKeyDp | p's CRT exponent (== d mod (p - 1))
RsaKeyDq | q's CRT exponent (== d mod (q - 1))
RsaKeyQInv | The CRT coefficient (== 1/q mod p)

Definition at line 69 of file BaseCryptLib.h.

Function Documentation

BOOLEAN AesCbcDecrypt | ( | IN VOID * | AesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | IN CONST UINT8 * | Ivec,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs AES decryption on a data buffer of the specified size in CBC mode.

This function performs AES decryption on data buffer pointed by Input, of specified size of InputSize, in CBC mode. InputSize must be multiple of block size (16 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. Initialization vector should be one block size (16 bytes). AesContext should be already correctly initialized by AesInit(). Behavior with invalid AES context is undefined.

If AesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (16 bytes), then ASSERT(). If Ivec is NULL, then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | AesContext | Pointer to the AES context.
[in] | Input | Pointer to the buffer containing the data to be encrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[in] | Ivec | Pointer to initialization vector.
[out] | Output | Pointer to a buffer that receives the AES encryption output.
Return values
TRUE | AES decryption succeeded.
FALSE | AES decryption failed.
BOOLEAN AesCbcEncrypt | ( | IN VOID * | AesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | IN CONST UINT8 * | Ivec,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs AES encryption on a data buffer of the specified size in CBC mode.

This function performs AES encryption on data buffer pointed by Input, of specified size of InputSize, in CBC mode. InputSize must be multiple of block size (16 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. Initialization vector should be one block size (16 bytes). AesContext should be already correctly initialized by AesInit(). Behavior with invalid AES context is undefined.

If AesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (16 bytes), then ASSERT(). If Ivec is NULL, then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | AesContext | Pointer to the AES context.
[in] | Input | Pointer to the buffer containing the data to be encrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[in] | Ivec | Pointer to initialization vector.
[out] | Output | Pointer to a buffer that receives the AES encryption output.
Return values
TRUE | AES encryption succeeded.
FALSE | AES encryption failed.
BOOLEAN AesEcbDecrypt | ( | IN VOID * | AesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs AES decryption on a data buffer of the specified size in ECB mode.

This function performs AES decryption on data buffer pointed by Input, of specified size of InputSize, in ECB mode. InputSize must be multiple of block size (16 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. AesContext should be already correctly initialized by AesInit(). Behavior with invalid AES context is undefined.

If AesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (16 bytes), then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | AesContext | Pointer to the AES context.
[in] | Input | Pointer to the buffer containing the data to be decrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[out] | Output | Pointer to a buffer that receives the AES decryption output.
Return values
TRUE | AES decryption succeeded.
FALSE | AES decryption failed.
BOOLEAN AesEcbEncrypt | ( | IN VOID * | AesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs AES encryption on a data buffer of the specified size in ECB mode.

This function performs AES encryption on data buffer pointed by Input, of specified size of InputSize, in ECB mode. InputSize must be multiple of block size (16 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. AesContext should be already correctly initialized by AesInit(). Behavior with invalid AES context is undefined.

If AesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (16 bytes), then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | AesContext | Pointer to the AES context.
[in] | Input | Pointer to the buffer containing the data to be encrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[out] | Output | Pointer to a buffer that receives the AES encryption output.
Return values
TRUE | AES encryption succeeded.
FALSE | AES encryption failed.
UINTN AesGetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for AES operations.

Returns
The size, in bytes, of the context buffer required for AES operations.
BOOLEAN AesInit | ( | OUT VOID * | AesContext,
 |  | IN CONST UINT8 * | Key,
 |  | IN UINTN | KeyLength
 | ) |  |

Initializes user-supplied memory as AES context for subsequent use.

This function initializes user-supplied memory pointed by AesContext as AES context. In addtion, it sets up all AES key materials for subsequent encryption and decryption operations. There are 3 options for key length, 128 bits, 192 bits, and 256 bits.

If AesContext is NULL, then ASSERT(). If Key is NULL, then ASSERT(). If KeyLength is not valid, then ASSERT().

Parameters
[out] | AesContext | Pointer to AES context being initialized.
[in] | Key | Pointer to the user-supplied AES key.
[in] | KeyLength | Length of AES key in bits.
Return values
TRUE | AES context initialization succeeded.
FALSE | AES context initialization failed.
BOOLEAN Arc4Decrypt | ( | IN OUT VOID * | Arc4Context,
 |  | IN UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs ARC4 decryption on a data buffer of the specified size.

This function performs ARC4 decryption on data buffer pointed by Input, of specified size of InputSize. Arc4Context should be already correctly initialized by Arc4Init(). Behavior with invalid ARC4 context is undefined.

If Arc4Context is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | Arc4Context | Pointer to the ARC4 context.
[in] | Input | Pointer to the buffer containing the data to be decrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[out] | Output | Pointer to a buffer that receives the ARC4 decryption output.
Return values
TRUE | ARC4 decryption succeeded.
FALSE | ARC4 decryption failed.
BOOLEAN Arc4Encrypt | ( | IN OUT VOID * | Arc4Context,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs ARC4 encryption on a data buffer of the specified size.

This function performs ARC4 encryption on data buffer pointed by Input, of specified size of InputSize. Arc4Context should be already correctly initialized by Arc4Init(). Behavior with invalid ARC4 context is undefined.

If Arc4Context is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | Arc4Context | Pointer to the ARC4 context.
[in] | Input | Pointer to the buffer containing the data to be encrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[out] | Output | Pointer to a buffer that receives the ARC4 encryption output.
Return values
TRUE | ARC4 encryption succeeded.
FALSE | ARC4 encryption failed.
UINTN Arc4GetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for ARC4 operations.

Returns
The size, in bytes, of the context buffer required for ARC4 operations.
BOOLEAN Arc4Init | ( | OUT VOID * | Arc4Context,
 |  | IN CONST UINT8 * | Key,
 |  | IN UINTN | KeySize
 | ) |  |

Initializes user-supplied memory as ARC4 context for subsequent use.

This function initializes user-supplied memory pointed by Arc4Context as ARC4 context. In addtion, it sets up all ARC4 key materials for subsequent encryption and decryption operations.

If Arc4Context is NULL, then ASSERT(). If Key is NULL, then ASSERT(). If KeySize does not in the range of [5, 256] bytes, then ASSERT().

Parameters
[out] | Arc4Context | Pointer to ARC4 context being initialized.
[in] | Key | Pointer to the user-supplied ARC4 key.
[in] | KeySize | Size of ARC4 key in bytes.
Return values
TRUE | ARC4 context initialization succeeded.
FALSE | ARC4 context initialization failed.
BOOLEAN Arc4Reset ( IN OUT VOID * Arc4Context )

Resets the ARC4 context to the initial state.

The function resets the ARC4 context to the state it had immediately after the ARC4Init() function call. Contrary to ARC4Init(), Arc4Reset() requires no secret key as input, but ARC4 context should be already correctly initialized by ARC4Init().

If Arc4Context is NULL, then ASSERT().

Parameters
[in,out] Arc4Context Pointer to the ARC4 context.
Return values
TRUE | ARC4 reset succeeded.
FALSE | ARC4 reset failed.
BOOLEAN DhComputeKey | ( | IN OUT VOID * | DhContext,
 |  | IN CONST UINT8 * | PeerPublicKey,
 |  | IN UINTN | PeerPublicKeySize,
 |  | OUT UINT8 * | Key,
 |  | IN OUT UINTN * | KeySize
 | ) |  |

Computes exchanged common key.

Given peer's public key, this function computes the exchanged common key, based on its own context including value of prime modulus and random secret exponent.

If DhContext is NULL, then ASSERT(). If PeerPublicKey is NULL, then ASSERT(). If KeySize is NULL, then ASSERT(). If KeySize is large enough but Key is NULL, then ASSERT().

Parameters
[in,out] | DhContext | Pointer to the DH context.
[in] | PeerPublicKey | Pointer to the peer's public key.
[in] | PeerPublicKeySize | Size of peer's public key in bytes.
[out] | Key | Pointer to the buffer to receive generated key.
[in,out] | KeySize | On input, the size of Key buffer in bytes. On output, the size of data returned in Key buffer in bytes.
Return values
TRUE | DH exchanged key generation succeeded.
FALSE | DH exchanged key generation failed.
FALSE | KeySize is not large enough.
VOID DhFree ( IN VOID * DhContext )

Release the specified DH context.

If DhContext is NULL, then ASSERT().

Parameters
[in] DhContext Pointer to the DH context to be released.
BOOLEAN DhGenerateKey | ( | IN OUT VOID * | DhContext,
 |  | OUT UINT8 * | PublicKey,
 |  | IN OUT UINTN * | PublicKeySize
 | ) |  |

Generates DH public key.

This function generates random secret exponent, and computes the public key, which is returned via parameter PublicKey and PublicKeySize. DH context is updated accordingly. If the PublicKey buffer is too small to hold the public key, FALSE is returned and PublicKeySize is set to the required buffer size to obtain the public key.

If DhContext is NULL, then ASSERT(). If PublicKeySize is NULL, then ASSERT(). If PublicKeySize is large enough but PublicKey is NULL, then ASSERT().

Parameters
[in,out] | DhContext | Pointer to the DH context.
[out] | PublicKey | Pointer to the buffer to receive generated public key.
[in,out] | PublicKeySize | On input, the size of PublicKey buffer in bytes. On output, the size of data returned in PublicKey buffer in bytes.
Return values
TRUE | DH public key generation succeeded.
FALSE | DH public key generation failed.
FALSE | PublicKeySize is not large enough.
BOOLEAN DhGenerateParameter | ( | IN OUT VOID * | DhContext,
 |  | IN UINTN | Generator,
 |  | IN UINTN | PrimeLength,
 |  | OUT UINT8 * | Prime
 | ) |  |

Generates DH parameter.

Given generator g, and length of prime number p in bits, this function generates p, and sets DH context according to value of g and p.

Before this function can be invoked, pseudorandom number generator must be correctly initialized by RandomSeed().

If DhContext is NULL, then ASSERT(). If Prime is NULL, then ASSERT().

Parameters
[in,out] | DhContext | Pointer to the DH context.
[in] | Generator | Value of generator.
[in] | PrimeLength | Length in bits of prime to be generated.
[out] | Prime | Pointer to the buffer to receive the generated prime number.
Return values
TRUE | DH pamameter generation succeeded.
FALSE | Value of Generator is not supported.
FALSE | PRNG fails to generate random prime number with PrimeLength.
VOID* DhNew ( VOID )

Allocates and Initializes one Diffie-Hellman Context for subsequent use.

Returns
Pointer to the Diffie-Hellman Context that has been initialized. If the allocations fails, DhNew() returns NULL.
BOOLEAN DhSetParameter | ( | IN OUT VOID * | DhContext,
 |  | IN UINTN | Generator,
 |  | IN UINTN | PrimeLength,
 |  | IN CONST UINT8 * | Prime
 | ) |  |

Sets generator and prime parameters for DH.

Given generator g, and prime number p, this function and sets DH context accordingly.

If DhContext is NULL, then ASSERT(). If Prime is NULL, then ASSERT().

Parameters
[in,out] | DhContext | Pointer to the DH context.
[in] | Generator | Value of generator.
[in] | PrimeLength | Length in bits of prime to be generated.
[in] | Prime | Pointer to the prime number.
Return values
TRUE | DH pamameter setting succeeded.
FALSE | Value of Generator is not supported.
FALSE | Value of Generator is not suitable for the Prime.
FALSE | Value of Prime is not a prime number.
FALSE | Value of Prime is not a safe prime number.
BOOLEAN HmacMd5Duplicate | ( | IN CONST VOID * | HmacMd5Context,
 |  | OUT VOID * | NewHmacMd5Context
 | ) |  |

Makes a copy of an existing HMAC-MD5 context.

If HmacMd5Context is NULL, then ASSERT(). If NewHmacMd5Context is NULL, then ASSERT().

Parameters
[in] | HmacMd5Context | Pointer to HMAC-MD5 context being copied.
[out] | NewHmacMd5Context | Pointer to new HMAC-MD5 context.
Return values
TRUE | HMAC-MD5 context copy succeeded.
FALSE | HMAC-MD5 context copy failed.
BOOLEAN HmacMd5Final | ( | IN OUT VOID * | HmacMd5Context,
 |  | OUT UINT8 * | HmacValue
 | ) |  |

Completes computation of the HMAC-MD5 digest value.

This function completes HMAC-MD5 hash computation and retrieves the digest value into the specified memory. After this function has been called, the HMAC-MD5 context cannot be used again. HMAC-MD5 context should be already correctly intialized by HmacMd5Init(), and should not be finalized by HmacMd5Final(). Behavior with invalid HMAC-MD5 context is undefined.

If HmacMd5Context is NULL, then ASSERT(). If HashValue is NULL, then ASSERT().

Parameters
[in,out] | HmacMd5Context | Pointer to the HMAC-MD5 context.
[out] | HashValue | Pointer to a buffer that receives the HMAC-MD5 digest value (16 bytes).
Return values
TRUE | HMAC-MD5 digest computation succeeded.
FALSE | HMAC-MD5 digest computation failed.
UINTN HmacMd5GetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for HMAC-MD5 operations.

Returns
The size, in bytes, of the context buffer required for HMAC-MD5 operations.
BOOLEAN HmacMd5Init | ( | OUT VOID * | HmacMd5Context,
 |  | IN CONST UINT8 * | Key,
 |  | IN UINTN | KeySize
 | ) |  |

Initializes user-supplied memory pointed by HmacMd5Context as HMAC-MD5 context for subsequent use.

If HmacMd5Context is NULL, then ASSERT().

Parameters
[out] | HmacMd5Context | Pointer to HMAC-MD5 context being initialized.
[in] | Key | Pointer to the user-supplied key.
[in] | KeySize | Key size in bytes.
Return values
TRUE | HMAC-MD5 context initialization succeeded.
FALSE | HMAC-MD5 context initialization failed.
BOOLEAN HmacMd5Update | ( | IN OUT VOID * | HmacMd5Context,
 |  | IN CONST VOID * | Data,
 |  | IN UINTN | DataSize
 | ) |  |

Digests the input data and updates HMAC-MD5 context.

This function performs HMAC-MD5 digest on a data buffer of the specified size. It can be called multiple times to compute the digest of long or discontinuous data streams. HMAC-MD5 context should be already correctly intialized by HmacMd5Init(), and should not be finalized by HmacMd5Final(). Behavior with invalid context is undefined.

If HmacMd5Context is NULL, then ASSERT().

Parameters
[in,out] | HmacMd5Context | Pointer to the HMAC-MD5 context.
[in] | Data | Pointer to the buffer containing the data to be digested.
[in] | DataSize | Size of Data buffer in bytes.
Return values
TRUE | HMAC-MD5 data digest succeeded.
FALSE | HMAC-MD5 data digest failed.
BOOLEAN HmacSha1Duplicate | ( | IN CONST VOID * | HmacSha1Context,
 |  | OUT VOID * | NewHmacSha1Context
 | ) |  |

Makes a copy of an existing HMAC-SHA1 context.

If HmacSha1Context is NULL, then ASSERT(). If NewHmacSha1Context is NULL, then ASSERT().

Parameters
[in] | HmacSha1Context | Pointer to HMAC-SHA1 context being copied.
[out] | NewHmacSha1Context | Pointer to new HMAC-SHA1 context.
Return values
TRUE | HMAC-SHA1 context copy succeeded.
FALSE | HMAC-SHA1 context copy failed.
BOOLEAN HmacSha1Final | ( | IN OUT VOID * | HmacSha1Context,
 |  | OUT UINT8 * | HmacValue
 | ) |  |

Completes computation of the HMAC-SHA1 digest value.

This function completes HMAC-SHA1 hash computation and retrieves the digest value into the specified memory. After this function has been called, the HMAC-SHA1 context cannot be used again. HMAC-SHA1 context should be already correctly intialized by HmacSha1Init(), and should not be finalized by HmacSha1Final(). Behavior with invalid HMAC-SHA1 context is undefined.

If HmacSha1Context is NULL, then ASSERT(). If HashValue is NULL, then ASSERT().

Parameters
[in,out] | HmacSha1Context | Pointer to the HMAC-SHA1 context.
[out] | HashValue | Pointer to a buffer that receives the HMAC-SHA1 digest value (20 bytes).
Return values
TRUE | HMAC-SHA1 digest computation succeeded.
FALSE | HMAC-SHA1 digest computation failed.
UINTN HmacSha1GetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for HMAC-SHA1 operations.

Returns
The size, in bytes, of the context buffer required for HMAC-SHA1 operations.
BOOLEAN HmacSha1Init | ( | OUT VOID * | HmacSha1Context,
 |  | IN CONST UINT8 * | Key,
 |  | IN UINTN | KeySize
 | ) |  |

Initializes user-supplied memory pointed by HmacSha1Context as HMAC-SHA1 context for subsequent use.

If HmacSha1Context is NULL, then ASSERT().

Parameters
[out] | HmacSha1Context | Pointer to HMAC-SHA1 context being initialized.
[in] | Key | Pointer to the user-supplied key.
[in] | KeySize | Key size in bytes.
Return values
TRUE | HMAC-SHA1 context initialization succeeded.
FALSE | HMAC-SHA1 context initialization failed.
BOOLEAN HmacSha1Update | ( | IN OUT VOID * | HmacSha1Context,
 |  | IN CONST VOID * | Data,
 |  | IN UINTN | DataSize
 | ) |  |

Digests the input data and updates HMAC-SHA1 context.

This function performs HMAC-SHA1 digest on a data buffer of the specified size. It can be called multiple times to compute the digest of long or discontinuous data streams. HMAC-SHA1 context should be already correctly intialized by HmacSha1Init(), and should not be finalized by HmacSha1Final(). Behavior with invalid context is undefined.

If HmacSha1Context is NULL, then ASSERT().

Parameters
[in,out] | HmacSha1Context | Pointer to the HMAC-SHA1 context.
[in] | Data | Pointer to the buffer containing the data to be digested.
[in] | DataSize | Size of Data buffer in bytes.
Return values
TRUE | HMAC-SHA1 data digest succeeded.
FALSE | HMAC-SHA1 data digest failed.
BOOLEAN Md5Duplicate | ( | IN CONST VOID * | Md5Context,
 |  | OUT VOID * | NewMd5Context
 | ) |  |

Makes a copy of an existing MD5 context.

If Md5Context is NULL, then ASSERT(). If NewMd5Context is NULL, then ASSERT().

Parameters
[in] | Md5Context | Pointer to MD5 context being copied.
[out] | NewMd5Context | Pointer to new MD5 context.
Return values
TRUE | MD5 context copy succeeded.
FALSE | MD5 context copy failed.
BOOLEAN Md5Final | ( | IN OUT VOID * | Md5Context,
 |  | OUT UINT8 * | HashValue
 | ) |  |

Completes computation of the MD5 digest value.

This function completes MD5 hash computation and retrieves the digest value into the specified memory. After this function has been called, the MD5 context cannot be used again. MD5 context should be already correctly intialized by Md5Init(), and should not be finalized by Md5Final(). Behavior with invalid MD5 context is undefined.

If Md5Context is NULL, then ASSERT(). If HashValue is NULL, then ASSERT().

Parameters
[in,out] | Md5Context | Pointer to the MD5 context.
[out] | HashValue | Pointer to a buffer that receives the MD5 digest value (16 bytes).
Return values
TRUE | MD5 digest computation succeeded.
FALSE | MD5 digest computation failed.
UINTN Md5GetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for MD5 hash operations.

Returns
The size, in bytes, of the context buffer required for MD5 hash operations.
BOOLEAN Md5Init ( OUT VOID * Md5Context )

Initializes user-supplied memory pointed by Md5Context as MD5 hash context for subsequent use.

If Md5Context is NULL, then ASSERT().

Parameters
[out] Md5Context Pointer to MD5 context being initialized.
Return values
TRUE | MD5 context initialization succeeded.
FALSE | MD5 context initialization failed.
BOOLEAN Md5Update | ( | IN OUT VOID * | Md5Context,
 |  | IN CONST VOID * | Data,
 |  | IN UINTN | DataSize
 | ) |  |

Digests the input data and updates MD5 context.

This function performs MD5 digest on a data buffer of the specified size. It can be called multiple times to compute the digest of long or discontinuous data streams. MD5 context should be already correctly intialized by Md5Init(), and should not be finalized by Md5Final(). Behavior with invalid context is undefined.

If Md5Context is NULL, then ASSERT().

Parameters
[in,out] | Md5Context | Pointer to the MD5 context.
[in] | Data | Pointer to the buffer containing the data to be hashed.
[in] | DataSize | Size of Data buffer in bytes.
Return values
TRUE | MD5 data digest succeeded.
FALSE | MD5 data digest failed.
BOOLEAN Pkcs7Verify | ( | IN CONST UINT8 * | P7Data,
 |  | IN UINTN | P7Size,
 |  | IN CONST UINT8 * | TrustedCert,
 |  | IN UINTN | CertSize,
 |  | IN CONST UINT8 * | InData,
 |  | IN UINTN | DataSize
 | ) |  |

Verifies the validility of a PKCS#7 signed data as described in "PKCS #7: Cryptographic Message Syntax Standard".

If P7Data is NULL, then ASSERT().

Parameters
[in] | P7Data | Pointer to the PKCS#7 message to verify.
[in] | P7Size | Size of the PKCS#7 message in bytes.
[in] | TrustedCert | Pointer to a trusted/root certificate encoded in DER, which is used for certificate chain verification.
[in] | CertSize | Size of the trusted certificate in bytes.
[in] | InData | Pointer to the content to be verified.
[in] | DataSize | Size of InData in bytes.
Return values
TRUE | The specified PKCS#7 signed data is valid.
FALSE | Invalid PKCS#7 signed data.
BOOLEAN RandomBytes | ( | OUT UINT8 * | Output,
 |  | IN UINTN | Size
 | ) |  |

Generates a pseudorandom byte stream of the specified size.

If Output is NULL, then ASSERT().

Parameters
[out] | Output | Pointer to buffer to receive random value.
[in] | Size | Size of randome bytes to generate.
Return values
TRUE | Pseudorandom byte stream generated successfully.
FALSE | Pseudorandom number generator fails to generate due to lack of entropy.
BOOLEAN RandomSeed | ( | IN CONST UINT8 *Seed | OPTIONAL,
 |  | IN UINTN | SeedSize
 | ) |  |

Sets up the seed value for the pseudorandom number generator.

This function sets up the seed value for the pseudorandom number generator. If Seed is not NULL, then the seed passed in is used. If Seed is NULL, then default seed is used.

Parameters
[in] | Seed | Pointer to seed value. If NULL, default seed is used.
[in] | SeedSize | Size of seed value. If Seed is NULL, this parameter is ignored.
Return values
TRUE | Pseudorandom number generator has enough entropy for random generation.
FALSE | Pseudorandom number generator does not have enough entropy for random generation.
BOOLEAN RsaCheckKey ( IN VOID * RsaContext )

Validates key components of RSA context.

This function validates key compoents of RSA context in following aspects:

  • Whether p is a prime
  • Whether q is a prime
  • Whether n = p * q
  • Whether d*e = 1 mod lcm(p-1,q-1)

If RsaContext is NULL, then ASSERT().

Parameters
[in] RsaContext Pointer to RSA context to check.
Return values
TRUE | RSA key components are valid.
FALSE | RSA key components are not valid.
VOID RsaFree ( IN VOID * RsaContext )

Release the specified RSA context.

If RsaContext is NULL, then ASSERT().

Parameters
[in] RsaContext Pointer to the RSA context to be released.
BOOLEAN RsaGenerateKey | ( | IN OUT VOID * | RsaContext,
 |  | IN UINTN | ModulusLength,
 |  | IN CONST UINT8 * | PublicExponent,
 |  | IN UINTN | PublicExponentSize
 | ) |  |

Generates RSA key components.

This function generates RSA key components. It takes RSA public exponent E and length in bits of RSA modulus N as input, and generates all key components. If PublicExponent is NULL, the default RSA public exponent (0x10001) will be used.

Before this function can be invoked, pseudorandom number generator must be correctly initialized by RandomSeed().

If RsaContext is NULL, then ASSERT().

Parameters
[in,out] | RsaContext | Pointer to RSA context being set.
[in] | ModulusLength | Length of RSA modulus N in bits.
[in] | PublicExponent | Pointer to RSA public exponent.
[in] | PublicExponentSize | Size of RSA public exponent buffer in bytes.
Return values
TRUE | RSA key component was generated successfully.
FALSE | Invalid RSA key component tag.
BOOLEAN RsaGetKey | ( | IN OUT VOID * | RsaContext,
 |  | IN RSA_KEY_TAG | KeyTag,
 |  | OUT UINT8 * | BigNumber,
 |  | IN OUT UINTN * | BnSize
 | ) |  |

Gets the tag-designated RSA key component from the established RSA context.

This function retrieves the tag-designated RSA key component from the established RSA context as a non-negative integer (octet string format represented in RSA PKCS#1). If specified key component has not been set or has been cleared, then returned BnSize is set to 0. If the BigNumber buffer is too small to hold the contents of the key, FALSE is returned and BnSize is set to the required buffer size to obtain the key.

If RsaContext is NULL, then ASSERT(). If BnSize is NULL, then ASSERT(). If BnSize is large enough but BigNumber is NULL, then ASSERT().

Parameters
[in,out] | RsaContext | Pointer to RSA context being set.
[in] | KeyTag | Tag of RSA key component being set.
[out] | BigNumber | Pointer to octet integer buffer.
[in,out] | BnSize | On input, the size of big number buffer in bytes. On output, the size of data returned in big number buffer in bytes.
Return values
TRUE | RSA key component was retrieved successfully.
FALSE | Invalid RSA key component tag.
FALSE | BnSize is too small.
VOID* RsaNew ( VOID )

Allocates and initializes one RSA context for subsequent use.

Returns
Pointer to the RSA context that has been initialized. If the allocations fails, RsaNew() returns NULL.
BOOLEAN RsaPkcs1Sign | ( | IN VOID * | RsaContext,
 |  | IN CONST UINT8 * | MessageHash,
 |  | IN UINTN | HashSize,
 |  | OUT UINT8 * | Signature,
 |  | IN OUT UINTN * | SigSize
 | ) |  |

Carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme.

This function carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme defined in RSA PKCS#1. If the Signature buffer is too small to hold the contents of signature, FALSE is returned and SigSize is set to the required buffer size to obtain the signature.

If RsaContext is NULL, then ASSERT(). If MessageHash is NULL, then ASSERT(). If HashSize is not equal to the size of MD5, SHA-1, SHA-256, SHA-224, SHA-512 or SHA-384 digest, then ASSERT(). If SigSize is large enough but Signature is NULL, then ASSERT().

Parameters
[in] | RsaContext | Pointer to RSA context for signature generation.
[in] | MessageHash | Pointer to octet message hash to be signed.
[in] | HashSize | Size of the message hash in bytes.
[out] | Signature | Pointer to buffer to receive RSA PKCS1-v1_5 signature.
[in,out] | SigSize | On input, the size of Signature buffer in bytes. On output, the size of data returned in Signature buffer in bytes.
Return values
TRUE | Signature successfully generated in PKCS1-v1_5.
FALSE | Signature generation failed.
FALSE | SigSize is too small.
BOOLEAN RsaPkcs1Verify | ( | IN VOID * | RsaContext,
 |  | IN CONST UINT8 * | MessageHash,
 |  | IN UINTN | HashSize,
 |  | IN UINT8 * | Signature,
 |  | IN UINTN | SigSize
 | ) |  |

Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in RSA PKCS#1.

If RsaContext is NULL, then ASSERT(). If MessageHash is NULL, then ASSERT(). If Signature is NULL, then ASSERT(). If HashSize is not equal to the size of MD5, SHA-1, SHA-256, SHA-224, SHA-512 or SHA-384 digest, then ASSERT().

Parameters
[in] | RsaContext | Pointer to RSA context for signature verification.
[in] | MessageHash | Pointer to octet message hash to be checked.
[in] | HashSize | Size of the message hash in bytes.
[in] | Signature | Pointer to RSA PKCS1-v1_5 signature to be verified.
[in] | SigSize | Size of signature in bytes.
Return values
TRUE | Valid signature encoded in PKCS1-v1_5.
FALSE | Invalid signature or invalid RSA context.
BOOLEAN RsaSetKey | ( | IN OUT VOID * | RsaContext,
 |  | IN RSA_KEY_TAG | KeyTag,
 |  | IN CONST UINT8 * | BigNumber,
 |  | IN UINTN | BnSize
 | ) |  |

Sets the tag-designated key component into the established RSA context.

This function sets the tag-designated RSA key component into the established RSA context from the user-specified non-negative integer (octet string format represented in RSA PKCS#1). If BigNumber is NULL, then the specified key componenet in RSA context is cleared.

If RsaContext is NULL, then ASSERT().

Parameters
[in,out] | RsaContext | Pointer to RSA context being set.
[in] | KeyTag | Tag of RSA key component being set.
[in] | BigNumber | Pointer to octet integer buffer. If NULL, then the specified key componenet in RSA context is cleared.
[in] | BnSize | Size of big number buffer in bytes. If BigNumber is NULL, then it is ignored.
Return values
TRUE | RSA key component was set successfully.
FALSE | Invalid RSA key component tag.
BOOLEAN Sha1Duplicate | ( | IN CONST VOID * | Sha1Context,
 |  | OUT VOID * | NewSha1Context
 | ) |  |

Makes a copy of an existing SHA-1 context.

If Sha1Context is NULL, then ASSERT(). If NewSha1Context is NULL, then ASSERT().

Parameters
[in] | Sha1Context | Pointer to SHA-1 context being copied.
[out] | NewSha1Context | Pointer to new SHA-1 context.
Return values
TRUE | SHA-1 context copy succeeded.
FALSE | SHA-1 context copy failed.
BOOLEAN Sha1Final | ( | IN OUT VOID * | Sha1Context,
 |  | OUT UINT8 * | HashValue
 | ) |  |

Completes computation of the SHA-1 digest value.

This function completes SHA-1 hash computation and retrieves the digest value into the specified memory. After this function has been called, the SHA-1 context cannot be used again. SHA-1 context should be already correctly intialized by Sha1Init(), and should not be finalized by Sha1Final(). Behavior with invalid SHA-1 context is undefined.

If Sha1Context is NULL, then ASSERT(). If HashValue is NULL, then ASSERT().

Parameters
[in,out] | Sha1Context | Pointer to the SHA-1 context.
[out] | HashValue | Pointer to a buffer that receives the SHA-1 digest value (20 bytes).
Return values
TRUE | SHA-1 digest computation succeeded.
FALSE | SHA-1 digest computation failed.
UINTN Sha1GetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for SHA-1 hash operations.

Returns
The size, in bytes, of the context buffer required for SHA-1 hash operations.
BOOLEAN Sha1Init ( OUT VOID * Sha1Context )

Initializes user-supplied memory pointed by Sha1Context as SHA-1 hash context for subsequent use.

If Sha1Context is NULL, then ASSERT().

Parameters
[out] Sha1Context Pointer to SHA-1 context being initialized.
Return values
TRUE | SHA-1 context initialization succeeded.
FALSE | SHA-1 context initialization failed.
BOOLEAN Sha1Update | ( | IN OUT VOID * | Sha1Context,
 |  | IN CONST VOID * | Data,
 |  | IN UINTN | DataSize
 | ) |  |

Digests the input data and updates SHA-1 context.

This function performs SHA-1 digest on a data buffer of the specified size. It can be called multiple times to compute the digest of long or discontinuous data streams. SHA-1 context should be already correctly intialized by Sha1Init(), and should not be finalized by Sha1Final(). Behavior with invalid context is undefined.

If Sha1Context is NULL, then ASSERT().

Parameters
[in,out] | Sha1Context | Pointer to the SHA-1 context.
[in] | Data | Pointer to the buffer containing the data to be hashed.
[in] | DataSize | Size of Data buffer in bytes.
Return values
TRUE | SHA-1 data digest succeeded.
FALSE | SHA-1 data digest failed.
BOOLEAN Sha256Duplicate | ( | IN CONST VOID * | Sha256Context,
 |  | OUT VOID * | NewSha256Context
 | ) |  |

Makes a copy of an existing SHA-256 context.

If Sha256Context is NULL, then ASSERT(). If NewSha256Context is NULL, then ASSERT().

Parameters
[in] | Sha256Context | Pointer to SHA-256 context being copied.
[out] | NewSha256Context | Pointer to new SHA-256 context.
Return values
TRUE | SHA-256 context copy succeeded.
FALSE | SHA-256 context copy failed.
BOOLEAN Sha256Final | ( | IN OUT VOID * | Sha256Context,
 |  | OUT UINT8 * | HashValue
 | ) |  |

Completes computation of the SHA-256 digest value.

This function completes SHA-256 hash computation and retrieves the digest value into the specified memory. After this function has been called, the SHA-256 context cannot be used again. SHA-256 context should be already correctly intialized by Sha256Init(), and should not be finalized by Sha256Final(). Behavior with invalid SHA-256 context is undefined.

If Sha256Context is NULL, then ASSERT(). If HashValue is NULL, then ASSERT().

Parameters
[in,out] | Sha256Context | Pointer to the SHA-256 context.
[out] | HashValue | Pointer to a buffer that receives the SHA-256 digest value (32 bytes).
Return values
TRUE | SHA-256 digest computation succeeded.
FALSE | SHA-256 digest computation failed.
UINTN Sha256GetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for SHA-256 hash operations.

Returns
The size, in bytes, of the context buffer required for SHA-256 hash operations.
BOOLEAN Sha256Init ( OUT VOID * Sha256Context )

Initializes user-supplied memory pointed by Sha256Context as SHA-256 hash context for subsequent use.

If Sha256Context is NULL, then ASSERT().

Parameters
[out] Sha256Context Pointer to SHA-256 context being initialized.
Return values
TRUE | SHA-256 context initialization succeeded.
FALSE | SHA-256 context initialization failed.
BOOLEAN Sha256Update | ( | IN OUT VOID * | Sha256Context,
 |  | IN CONST VOID * | Data,
 |  | IN UINTN | DataSize
 | ) |  |

Digests the input data and updates SHA-256 context.

This function performs SHA-256 digest on a data buffer of the specified size. It can be called multiple times to compute the digest of long or discontinuous data streams. SHA-256 context should be already correctly intialized by Sha256Init(), and should not be finalized by Sha256Final(). Behavior with invalid context is undefined.

If Sha256Context is NULL, then ASSERT().

Parameters
[in,out] | Sha256Context | Pointer to the SHA-256 context.
[in] | Data | Pointer to the buffer containing the data to be hashed.
[in] | DataSize | Size of Data buffer in bytes.
Return values
TRUE | SHA-256 data digest succeeded.
FALSE | SHA-256 data digest failed.
BOOLEAN TdesCbcDecrypt | ( | IN VOID * | TdesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | IN CONST UINT8 * | Ivec,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs TDES decryption on a data buffer of the specified size in CBC mode.

This function performs TDES decryption on data buffer pointed by Input, of specified size of InputSize, in CBC mode. InputSize must be multiple of block size (8 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. Initialization vector should be one block size (8 bytes). TdesContext should be already correctly initialized by TdesInit(). Behavior with invalid TDES context is undefined.

If TdesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (8 bytes), then ASSERT(). If Ivec is NULL, then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | TdesContext | Pointer to the TDES context.
[in] | Input | Pointer to the buffer containing the data to be encrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[in] | Ivec | Pointer to initialization vector.
[out] | Output | Pointer to a buffer that receives the TDES encryption output.
Return values
TRUE | TDES decryption succeeded.
FALSE | TDES decryption failed.
BOOLEAN TdesCbcEncrypt | ( | IN VOID * | TdesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | IN CONST UINT8 * | Ivec,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs TDES encryption on a data buffer of the specified size in CBC mode.

This function performs TDES encryption on data buffer pointed by Input, of specified size of InputSize, in CBC mode. InputSize must be multiple of block size (8 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. Initialization vector should be one block size (8 bytes). TdesContext should be already correctly initialized by TdesInit(). Behavior with invalid TDES context is undefined.

If TdesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (8 bytes), then ASSERT(). If Ivec is NULL, then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | TdesContext | Pointer to the TDES context.
[in] | Input | Pointer to the buffer containing the data to be encrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[in] | Ivec | Pointer to initialization vector.
[out] | Output | Pointer to a buffer that receives the TDES encryption output.
Return values
TRUE | TDES encryption succeeded.
FALSE | TDES encryption failed.
BOOLEAN TdesEcbDecrypt | ( | IN VOID * | TdesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs TDES decryption on a data buffer of the specified size in ECB mode.

This function performs TDES decryption on data buffer pointed by Input, of specified size of InputSize, in ECB mode. InputSize must be multiple of block size (8 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. TdesContext should be already correctly initialized by TdesInit(). Behavior with invalid TDES context is undefined.

If TdesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (8 bytes), then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | TdesContext | Pointer to the TDES context.
[in] | Input | Pointer to the buffer containing the data to be decrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[out] | Output | Pointer to a buffer that receives the TDES decryption output.
Return values
TRUE | TDES decryption succeeded.
FALSE | TDES decryption failed.
BOOLEAN TdesEcbEncrypt | ( | IN VOID * | TdesContext,
 |  | IN CONST UINT8 * | Input,
 |  | IN UINTN | InputSize,
 |  | OUT UINT8 * | Output
 | ) |  |

Performs TDES encryption on a data buffer of the specified size in ECB mode.

This function performs TDES encryption on data buffer pointed by Input, of specified size of InputSize, in ECB mode. InputSize must be multiple of block size (8 bytes). This function does not perform padding. Caller must perform padding, if necessary, to ensure valid input data size. TdesContext should be already correctly initialized by TdesInit(). Behavior with invalid TDES context is undefined.

If TdesContext is NULL, then ASSERT(). If Input is NULL, then ASSERT(). If InputSize is not multiple of block size (8 bytes), then ASSERT(). If Output is NULL, then ASSERT().

Parameters
[in] | TdesContext | Pointer to the TDES context.
[in] | Input | Pointer to the buffer containing the data to be encrypted.
[in] | InputSize | Size of the Input buffer in bytes.
[out] | Output | Pointer to a buffer that receives the TDES encryption output.
Return values
TRUE | TDES encryption succeeded.
FALSE | TDES encryption failed.
UINTN TdesGetContextSize ( VOID )

Retrieves the size, in bytes, of the context buffer required for TDES operations.

Returns
The size, in bytes, of the context buffer required for TDES operations.
BOOLEAN TdesInit | ( | OUT VOID * | TdesContext,
 |  | IN CONST UINT8 * | Key,
 |  | IN UINTN | KeyLength
 | ) |  |

Initializes user-supplied memory as TDES context for subsequent use.

This function initializes user-supplied memory pointed by TdesContext as TDES context. In addtion, it sets up all TDES key materials for subsequent encryption and decryption operations. There are 3 key options as follows: KeyLength = 64, Keying option 1: K1 == K2 == K3 (Backward compatibility with DES) KeyLength = 128, Keying option 2: K1 != K2 and K3 = K1 (Less Security) KeyLength = 192 Keying option 3: K1 != K2 != K3 (Strongest)

If TdesContext is NULL, then ASSERT(). If Key is NULL, then ASSERT(). If KeyLength is not valid, then ASSERT().

Parameters
[out] | TdesContext | Pointer to TDES context being initialized.
[in] | Key | Pointer to the user-supplied TDES key.
[in] | KeyLength | Length of TDES key in bits.
Return values
TRUE | TDES context initialization succeeded.
FALSE | TDES context initialization failed.


IceLake Platform Sample Code: BaseEcFlashLib.h File Reference

  • Library
Macros
BaseEcFlashLib.h File Reference

Go to the source code of this file.

Macros

#define | EC_VIRTUAL_BAT_STATUS 48
Note that capacity and voltage are 16 bit values, thus you need to read them from ACPI space with two reads (little Endian). More...
#define | EC_VIRTUAL_BAT_PRESENT_MASK 0x10
Bit 4 is the indicator.
#define | EC_REAL_BAT1_STATUS 50
Status of the first real battery (present, charging)
#define | EC_REAL_BAT1_REMAINING_PERCENT 52
Remaining capacity in percentage.
#define | EC_REAL_BAT1_REMAINING_CAPACITY 89
Remaining capacity in mWh.
#define | EC_REAL_BAT1_RESOLUTION_VOLTAGE 93
Full resolution voltage in mV.
#define | EC_REAL_BAT2_STATUS 54
Status of the second real battery (present, charging)
#define | EC_REAL_BAT2_REMAINING_PERCENT 56
Remaining capacity in percentage.
#define | EC_REAL_BAT2_REMAINING_CAPACITY 99
Remaining capacity in mWh.
#define | EC_REAL_BAT2_RESOLUTION_VOLTAGE 103
Full resolution voltage in mV.
#define | EC_REAL_BAT_PRESENT_MASK 0x8
Bit 3 is the indicator.
#define | EC_REAL_BAT_CHARGING_MASK 0x1
Bit 1 is the indicator.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BaseEcFlashLib.h.

Macro Definition Documentation

#define EC_VIRTUAL_BAT_STATUS 48

Note that capacity and voltage are 16 bit values, thus you need to read them from ACPI space with two reads (little Endian).

Status of the virtual battery (present)

Definition at line 117 of file BaseEcFlashLib.h.


IceLake Platform Sample Code: BasePlatformVariableLib.h File Reference

  • Library
Functions
BasePlatformVariableLib.h File Reference
#include <Uefi.h>
Include dependency graph for BasePlatformVariableLib.h:

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Functions

EFI_STATUS CheckSataRaidMode (BOOLEAN *SataRaidModeEnabled)
Check the SATA RAID mode and report its status. More...

Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BasePlatformVariableLib.h.

Function Documentation

EFI_STATUS CheckSataRaidMode ( BOOLEAN * SataRaidModeEnabled )

Check the SATA RAID mode and report its status.

Parameters
[out] SataRaidModeEnabled The current status of SATA RAID mode.
Return values
EFI_SUCESS | This function always complete successfully.
EFI_ACCESS_DENIED | Cannot not retrieve PchSetup variables.


IceLake Platform Sample Code: BoardConfigLib.h File Reference

  • Library
Functions
BoardConfigLib.h File Reference

Function prototype of BoardConfigLib. More...

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Functions

VOID GetBoardConfig (VOID)
Procedure to detect current board HW configuration.

Detailed Description

Function prototype of BoardConfigLib.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BoardConfigLib.h.


IceLake Platform Sample Code: BootGuardRevocationLib.h File Reference

  • Library
Functions
BootGuardRevocationLib.h File Reference

Header file for Boot Guard revocation notification. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Protocol/SimpleTextIn.h>
Include dependency graph for BootGuardRevocationLib.h:
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Functions

VOID BootGuardOemRevocationHook (VOID)
Provide a hook for OEM to deal with Boot Guard revocation flow.

Detailed Description

Header file for Boot Guard revocation notification.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BootGuardRevocationLib.h.


IceLake Platform Sample Code: Build.h File Reference

  • Library
Macros
Build.h File Reference
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Macros

#define | VER_BUILD 1009
Build Version Number. More...
#define | VER_BUILD_STR "1009"
Build Version String. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2005 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Build.h.

Macro Definition Documentation

#define VER_BUILD 1009

Build Version Number.

Updated by Jamin

Definition at line 59 of file Build.h.

#define VER_BUILD_STR "1009"

Build Version String.

Updated by Jamin

Definition at line 61 of file Build.h.


IceLake Platform Sample Code: CeAta.h File Reference

  • IndustryStandard
CeAta.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file CeAta.h.


IceLake Platform Sample Code: Common.h File Reference

  • Library
Common.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2007 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Common.h.


IceLake Platform Sample Code: CommonDefinitions.h File Reference

CommonDefinitions.h File Reference
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file CommonDefinitions.h.


IceLake Platform Sample Code: CpuPolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
CpuPolicyInitDxe.c File Reference

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation. More...

#include <CpuPolicyInitDxe.h>
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Functions

EFI_STATUS CpuPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Platform Policy. More...

Detailed Description

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file CpuPolicyInitDxe.c.

Function Documentation

EFI_STATUS CpuPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel CPU DXE Platform Policy.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 50 of file CpuPolicyInitDxe.c.

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IceLake Platform Sample Code: CpuPolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
CpuPolicyInitDxe.h File Reference

Header file for the SiliconPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Protocol/CpuPolicyProtocol.h>
#include <Library/DxeCpuPolicyUpdateLib.h>
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Functions

EFI_STATUS CpuPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy. More...

Detailed Description

Header file for the SiliconPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file CpuPolicyInitDxe.h.

Function Documentation

EFI_STATUS CpuPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 50 of file CpuPolicyInitDxe.c.

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IceLake Platform Sample Code: CpuSmm.h File Reference

CpuSmm.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file CpuSmm.h.


IceLake Platform Sample Code: cse_basic_def.h File Reference

  • Library
cse_basic_def.h File Reference
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file cse_basic_def.h.


IceLake Platform Sample Code: cse_basic_types.h File Reference

  • Library
cse_basic_types.h File Reference
#include "cse_basic_def.h"
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file cse_basic_types.h.


IceLake Platform Sample Code: CustomOptionControl.h File Reference

CustomOptionControl.h File Reference
#include <SetupVariable.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Library/DebugLib.h>
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file CustomOptionControl.h.


IceLake Platform Sample Code: DimmInfo.h File Reference

DimmInfo.h File Reference

This header file provides Dimm info definitions used by other modules for dimm info presentation. More...

#include <Protocol/MemInfo.h>
Include dependency graph for DimmInfo.h:

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Detailed Description

This header file provides Dimm info definitions used by other modules for dimm info presentation.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DimmInfo.h.


IceLake Platform Sample Code: DoxygenAcpi.h File Reference

DoxygenAcpi.h File Reference

This file contains doxygen commands definitions for creating quality platform documentation. More...

Go to the source code of this file.

Detailed Description

This file contains doxygen commands definitions for creating quality platform documentation.

Copyright (c) 2013 - 2016 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Definition in file DoxygenAcpi.h.


IceLake Platform Sample Code: DoxygenPlat.h File Reference

DoxygenPlat.h File Reference

This file contains doxygen commands definitions for creating platform sample documentation. More...

Go to the source code of this file.

Detailed Description

This file contains doxygen commands definitions for creating platform sample documentation.

Copyright
Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Definition in file DoxygenPlat.h.


IceLake Platform Sample Code: DoxygenRpOverride.h File Reference

  • Override
DoxygenRpOverride.h File Reference

This file contains doxygen commands definitions for creating Platform override documentation. More...

Go to the source code of this file.

Detailed Description

This file contains doxygen commands definitions for creating Platform override documentation.

Copyright
Copyright (c) 2017 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Sample Driver' and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement

Definition in file DoxygenRpOverride.h.


IceLake Platform Sample Code: DsAllocation.h File Reference

DsAllocation.h File Reference
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DsAllocation.h.


IceLake Platform Sample Code: DsConfig.h File Reference

DsConfig.h File Reference
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DsConfig.h.


IceLake Platform Sample Code: DxeAcpiGnvsInitLib.h File Reference

  • Library
Functions
DxeAcpiGnvsInitLib.h File Reference

Acpi Gnvs Init Library header file. More...

#include <Base.h>
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Functions

EFI_STATUS AcpiGnvsInit (IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize. More...

Detailed Description

Acpi Gnvs Init Library header file.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeAcpiGnvsInitLib.h.

Function Documentation

EFI_STATUS AcpiGnvsInit ( IN OUT VOID ** PlatformNvsAreaPtr )

Global NVS initialize.

Parameters
[in] PlatformNvsAreaPtr - Pointer of global NVS area
Return values
EFI_SUCCESS | - Allocate Global NVS completed.
EFI_OUT_OF_RESOURCES | - Failed to allocate required page for PlatformNvsAreaProtocol.


IceLake Platform Sample Code: DxeAmtPolicyUpdateLib.h File Reference

  • Library
DxeAmtPolicyUpdateLib.h File Reference
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeAmtPolicyUpdateLib.h.


IceLake Platform Sample Code: DxeCpuPolicyUpdateLib.h File Reference

  • Library
Functions
DxeCpuPolicyUpdateLib.h File Reference
#include <PiDxe.h>
#include <PchAccess.h>
#include <SetupVariable.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/CpuPolicyProtocol.h>
Include dependency graph for DxeCpuPolicyUpdateLib.h:
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Functions

VOID | CpuDxePrintPolicyProtocol (IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
This function prints the CPU DXE phase policy. More...
EFI_STATUS | UpdateDxeSiCpuPolicy (IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
Routine Description: More...
EFI_STATUS | CpuInstallPolicyProtocol (IN EFI_HANDLE ImageHandle, IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
CpuInstallPolicyProtocol installs CPU Policy. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeCpuPolicyUpdateLib.h.

Function Documentation

VOID CpuDxePrintPolicyProtocol ( IN DXE_CPU_POLICY_PROTOCOL * DxeCpuPolicy )

This function prints the CPU DXE phase policy.

Parameters
[in] DxeCpuPolicy - CPU DXE Policy protocol
EFI_STATUS CpuInstallPolicyProtocol | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN DXE_CPU_POLICY_PROTOCOL * | DxeCpuPolicy
 | ) |  |

CpuInstallPolicyProtocol installs CPU Policy.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | DxeCpuPolicy | The pointer to CPU Policy Protocol instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer
EFI_STATUS UpdateDxeSiCpuPolicy ( IN OUT DXE_CPU_POLICY_PROTOCOL * DxeCpuPolicy )

Routine Description:

This function updates Dxe Cpu Policy Protocol

Arguments:

Parameters
[in] DxeCpuPolicy The Cpu Policy protocol instance

Returns:

Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.


IceLake Platform Sample Code: DxeFirmwareVersionInfoLib.h File Reference

  • Library
DxeFirmwareVersionInfoLib.h File Reference

Private data structures. More...

Go to the source code of this file.

Detailed Description

Private data structures.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeFirmwareVersionInfoLib.h.


IceLake Platform Sample Code: DxeMePolicyUpdateLib.h File Reference

  • Library
Functions
DxeMePolicyUpdateLib.h File Reference
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Functions

EFI_STATUS UpdateDxeMePolicy (IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
Update the ME Policy Library. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeMePolicyUpdateLib.h.

Function Documentation

EFI_STATUS UpdateDxeMePolicy ( IN OUT ME_POLICY_PROTOCOL * DxeMePolicy )

Update the ME Policy Library.

Parameters
[in] DxeMePolicy The pointer to get ME Policy protocol instance
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.


IceLake Platform Sample Code: DxeOpromPatchLib.h File Reference

  • Library
DxeOpromPatchLib.h File Reference
#include <Protocol/PciIo.h>
Include dependency graph for DxeOpromPatchLib.h:

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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeOpromPatchLib.h.


IceLake Platform Sample Code: DxePchPolicyUpdateLib.h File Reference

  • Library
Functions
DxePchPolicyUpdateLib.h File Reference
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Functions

EFI_STATUS UpdateDxePchPolicy (IN OUT PCH_POLICY_PROTOCOL *PchPolicy)
Get data for platform policy from setup options. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxePchPolicyUpdateLib.h.

Function Documentation

EFI_STATUS UpdateDxePchPolicy ( IN OUT PCH_POLICY_PROTOCOL * PchPolicy )

Get data for platform policy from setup options.

Parameters
[in] PchPolicy The pointer to get PCH Policy protocol instance
Return values
EFI_SUCCESS Operation success.


IceLake Platform Sample Code: DxePlatformBootManagerLib.h File Reference

  • Library
Functions
DxePlatformBootManagerLib.h File Reference

Header file for DxePlatformBootManagerLib. More...

Go to the source code of this file.

Functions

EFI_STATUS | ExpandPartitionsDevPath (IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption, OUT EFI_DEVICE_PATH_PROTOCOL **BootDevicePath)
Tries to expand the given partitions device path to start with physical HDD device path. More...
BOOLEAN | IsItPartitionsDevicePath (IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption)
Checks whenever a given load option starts with a partition device path. More...
CHAR16 * | DevicePathToStr (IN EFI_DEVICE_PATH_PROTOCOL *DevPath)
This function converts an input device structure to a Unicode string. More...

Detailed Description

Header file for DxePlatformBootManagerLib.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference

Definition in file DxePlatformBootManagerLib.h.

Function Documentation

CHAR16* DevicePathToStr ( IN EFI_DEVICE_PATH_PROTOCOL * DevPath )

This function converts an input device structure to a Unicode string.

Parameters
DevPath A pointer to the device path structure.
Returns
A new allocated Unicode string that represents the device path.
EFI_STATUS ExpandPartitionsDevPath | ( | IN EFI_BOOT_MANAGER_LOAD_OPTION * | LoadOption,
 |  | OUT EFI_DEVICE_PATH_PROTOCOL ** | BootDevicePath
 | ) |  |

Tries to expand the given partitions device path to start with physical HDD device path.

Parameters
[in] | LoadOption | pointer to an Efi Boot Manager boot option
[out] | BootDevicePath | indirect pointer to retrieved device path
Return values
EFI_SUCCESS Function found
BOOLEAN IsItPartitionsDevicePath ( IN EFI_BOOT_MANAGER_LOAD_OPTION * LoadOption )

Checks whenever a given load option starts with a partition device path.

Parameters
[in] LoadOption Pointer to load option to test
Return values
TRUE
FALSE
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxePolicyBoardConfigLib.h File Reference

  • Library
Functions
DxePolicyBoardConfigLib.h File Reference

Header file for the DxePolicyBoardConfig Library. More...

#include <Protocol/AmtPolicy.h>
#include <Protocol/MePolicy.h>
#include <Protocol/SaPolicy.h>
Include dependency graph for DxePolicyBoardConfigLib.h:
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Functions

EFI_STATUS | UpdateDxeAmtPolicyBoardConfig (IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function performs DXE AMT Policy update by board configuration. More...
EFI_STATUS | UpdateDxeMePolicyBoardConfig (IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
This function performs DXE ME Policy update by board configuration. More...
EFI_STATUS | UpdateDxeSaPolicyBoardConfig (IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy)
This function performs DXE SA Policy update by board configuration. More...

Detailed Description

Header file for the DxePolicyBoardConfig Library.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxePolicyBoardConfigLib.h.

Function Documentation

EFI_STATUS UpdateDxeAmtPolicyBoardConfig ( IN OUT AMT_POLICY_PROTOCOL * DxeAmtPolicy )

This function performs DXE AMT Policy update by board configuration.

Parameters
[in,out] DxeAmtPolicy DXE AMT Policy
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdateDxeMePolicyBoardConfig ( IN OUT ME_POLICY_PROTOCOL * DxeMePolicy )

This function performs DXE ME Policy update by board configuration.

Parameters
[in,out] DxeAmtPolicy DXE ME Policy
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdateDxeSaPolicyBoardConfig ( IN OUT SA_POLICY_PROTOCOL * DxeSaPolicy )

This function performs DXE SA Policy update by board configuration.

Parameters
[in,out] DxeAmtPolicy DXE SA Policy
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.


IceLake Platform Sample Code: DxePolicyUpdateProtocol.h File Reference

  • Protocol
DxePolicyUpdateProtocol.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxePolicyUpdateProtocol.h.


IceLake Platform Sample Code: DxeSaPolicyUpdateLib.h File Reference

  • Library
Functions
DxeSaPolicyUpdateLib.h File Reference
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Functions

EFI_STATUS UpdateDxeSaPolicy (IN OUT SA_POLICY_PROTOCOL *SaPolicy)
Get data for platform policy from setup options. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeSaPolicyUpdateLib.h.

Function Documentation

EFI_STATUS UpdateDxeSaPolicy ( IN OUT SA_POLICY_PROTOCOL * SaPolicy )

Get data for platform policy from setup options.

Parameters
[in] SaPolicy The pointer to get SA Policy protocol instance
Return values
EFI_SUCCESS Operation success.


IceLake Platform Sample Code: DxeSmmAcpiCustomLib.h File Reference

  • Library
DxeSmmAcpiCustomLib.h File Reference

This header file provides platform specific definitions used by other modules for platform specific initialization. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/EcLib.h>
#include <SaAccess.h>
#include <Protocol/PlatformNvsArea.h>
#include <Protocol/SmmThunk.h>
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Detailed Description

This header file provides platform specific definitions used by other modules for platform specific initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeSmmAcpiCustomLib.h.


IceLake Platform Sample Code: DxeSmmInternalGraphicDeviceLib.h File Reference

  • Library
DxeSmmInternalGraphicDeviceLib.h File Reference
#include <Protocol/LegacyBios.h>
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeSmmInternalGraphicDeviceLib.h.


IceLake Platform Sample Code: DxeTbtPolicyUpdateLib.h File Reference

  • Library
Functions
DxeTbtPolicyUpdateLib.h File Reference
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Functions

EFI_STATUS UpdateDxeTbtPolicy (IN OUT TBT_POLICY_PROTOCOL *TbtPolicy)
Get data for platform policy from setup options. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeTbtPolicyUpdateLib.h.

Function Documentation

EFI_STATUS UpdateDxeTbtPolicy ( IN OUT TBT_POLICY_PROTOCOL * TbtPolicy )

Get data for platform policy from setup options.

Parameters
[in] TbtPolicy The pointer to get TBT Policy protocol instance
Return values
EFI_SUCCESS Operation success.


IceLake Platform Sample Code: EcAccess.h File Reference

  • Protocol
EcAccess.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file EcAccess.h.


IceLake Platform Sample Code: EcCommands.h File Reference

  • Library
EcCommands.h File Reference
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Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcCommands.h.


IceLake Platform Sample Code: Ecdt.h File Reference

  • Acpi
  • AcpiTables
  • Ecdt
Ecdt.h File Reference

This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT). More...

#include <IndustryStandard/Acpi.h>
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Detailed Description

This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT).

All changes to the ECDT contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Ecdt.h.


IceLake Platform Sample Code: EcHwLib.h File Reference

  • Library
EcHwLib.h File Reference

EC hardware library functions and definitions. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/EcCommands.h>
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Detailed Description

EC hardware library functions and definitions.

This library provides basic Embedded Controller Hardware interface. It is keeped simple enough and used by other BaseEc libraries to abstacrt the usage

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcHwLib.h.


IceLake Platform Sample Code: EcLib.h File Reference

  • Library
Functions
EcLib.h File Reference

EC library functions and definitions. More...

#include <Base.h>
#include <Uefi.h>
#include "EcCommands.h"
#include <Library/EcHwLib.h>
Include dependency graph for EcLib.h:
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Functions

BOOLEAN | DetectEc (OUT UINT8 *EcMajorRevision, OUT UINT8 *EcMinorRevision)
Detect EC. More...
EFI_STATUS | LpcEcResetEcInNormalMode (VOID)
Initiate EC reset sequence. More...
EFI_STATUS | SendEcCommand (IN UINT8 Command)
Send a command to the Keyboard System Controller. More...
EFI_STATUS | SendEcData (IN UINT8 Data)
Sends data to Keyboard System Controller. More...
EFI_STATUS | ReceiveEcData (OUT UINT8 *Data)
Receives data from Keyboard System Controller. More...
EFI_STATUS | ReceiveEcStatus (OUT UINT8 *EcStatus)
Receives status from Keyboard System Controller. More...
EFI_STATUS | EcInterface (IN EC_ID EcId, IN UINT8 Command, IN OUT UINT8 *DataSize, IN OUT UINT8 *DataBuffer)
Sends data to the Embedded Controler. More...

Detailed Description

EC library functions and definitions.

This library provides basic EC interface.

There may be different libraries for different environments (PEI, BS, RT, SMM). Make sure you meet the requirements for the library (protocol dependencies, use restrictions, etc).

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcLib.h.

Function Documentation

BOOLEAN DetectEc | ( | OUT UINT8 * | EcMajorRevision,
 |  | OUT UINT8 * | EcMinorRevision
 | ) |  |

Detect EC.

Parameters
[out] | EcMajorRevision
[out] | EcMinorRevision
Return values
TRUE | EC is present on the system.
FALSE | EC is NOT present on the system.
EFI_STATUS EcInterface | ( | IN EC_ID | EcId,
 |  | IN UINT8 | Command,
 |  | IN OUT UINT8 * | DataSize,
 |  | IN OUT UINT8 * | DataBuffer
 | ) |  |

Sends data to the Embedded Controler.

Four use-cases: 1.Send command to EC (DataSize and DataBuffer can be NULL) 2.Send command to EC and send data to EC 3.Send command to EC and receive data from EC 4.Send command to EC, send data to EC and receive data from EC

Parameters
[in] | EcId | Embedded Controller identification - in case there is more then one.
[in] | Interface | Interface used to access the EC HW
[in] | Command | Command value to send to the EC
[in]
EFI_STATUS LpcEcResetEcInNormalMode ( VOID )

Initiate EC reset sequence.

EC is in Normal Mode.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS ReceiveEcData ( OUT UINT8 * Data )

Receives data from Keyboard System Controller.

Parameters
[out] Data Data byte received
Return values
EFI_SUCCESS | Read success
EFI_TIMEOUT | Read timeout
Other | Read failed
EFI_STATUS ReceiveEcStatus ( OUT UINT8 * EcStatus )

Receives status from Keyboard System Controller.

Parameters
[out] Status Status byte to receive
Return values
EFI_SUCCESS | Success
Other | Failed
EFI_STATUS SendEcCommand ( IN UINT8 Command )

Send a command to the Keyboard System Controller.

Parameters
[in] Command Command byte to send
Return values
EFI_SUCCESS | Command success
EFI_TIMEOUT | Command timeout
Other | Command failed
EFI_STATUS SendEcData ( IN UINT8 Data )

Sends data to Keyboard System Controller.

Parameters
[in] Data Data byte to send
Return values
EFI_SUCCESS | Success
EFI_TIMEOUT | Timeout
Other | Failed


IceLake Platform Sample Code: EcMiscLib.h File Reference

  • Library
Functions
EcMiscLib.h File Reference

EC miscellaneous library functions. More...

#include <Base.h>
#include <Uefi.h>
#include "EcCommands.h"
#include <Library/EcLib.h>
Include dependency graph for EcMiscLib.h:
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Functions

EFI_STATUS | UsbcSxEntry (IN OUT UINT8 *DataBuffer)
USBC Sx Entry Wait. More...
EFI_STATUS | UsbcSxExit (OUT UINT8 *DataBuffer)
USBC Sx Exit Wait. More...
EFI_STATUS | EnableEcAcpiMode (IN BOOLEAN Enable)
Send enable ACPI mode command to EC. More...
EFI_STATUS | DisableEcSmiMode (VOID)
Send disable SMI mode command to EC. More...
EFI_STATUS | SetEcCriticalShutdownTemperature (IN UINT8 DataBuffer)
Set EC critical shutdown temperature. More...
BOOLEAN | PowerStateIsAc (VOID)
Get power state from EC. More...
EFI_STATUS | EcReset (VOID)
Do EC reset. More...
EFI_STATUS | EcResetEcInNormalMode (VOID)
Initiate EC reset sequence. More...
EFI_STATUS | EnableLanPower (IN BOOLEAN Enable)
Enable LAN power. More...
EFI_STATUS | QuerySmiEvent (OUT UINT8 *DataBuffer)
Query SMI event. More...
EFI_STATUS | GetHotkeyScanCode (OUT UINT8 *DataBuffer)
Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key) More...
EFI_STATUS | GetBatteryNumber (OUT UINT8 *DataBuffer)
Get the number of battery. More...
EFI_STATUS | GetPcieDockStatus (OUT UINT8 *DataBuffer)
Get PCIe dock status. More...
VOID | ClearTenSecPwrButtonMode (VOID)
Clear ten second power button mode. More...
VOID | EnableSataPort2Power (VOID)
Enable SATA port2 power. More...
EFI_STATUS | SetSlpS0Voltage (IN UINT8 EcDataV085ACNT)
Set SLP_S0 Voltage. More...
EFI_STATUS | DetectPmicVendorID (OUT UINT8 *DataBuffer)
Detect Pmic Vendor ID. More...
EFI_STATUS | SetPmicVoltage (IN UINT8 EcDataVcc, IN UINT8 EcDataVddq)
Set Pmic Voltage. More...
EFI_STATUS | ReadEcRam (IN OUT UINT8 *DataBuffer)
Read data from EC RAM. More...
EFI_STATUS | WriteEcRam (IN OUT UINT8 *DataBuffer)
Write data to EC RAM. More...
EFI_STATUS | UpdateDevicePower (VOID)
Update Device Power. More...
EFI_STATUS | QuerySysStatus (OUT UINT8 *DataBuffer)
Query system status. More...
EFI_STATUS | GetBoardInfo (OUT UINT16 *BoardFabId)
Get board fab ID. More...
EFI_STATUS | ExitLowPowerMode (VOID)
Send Exit Low Power Mode command to EC. More...
EFI_STATUS | SystemPowerOff (VOID)
System power off. More...
EFI_STATUS | DetectEcRevision (OUT UINT8 *DataBuffer)
Detect EC revision. More...
EFI_STATUS | GetBaseEcFwVersion (OUT UINT8 *DataBuffer)
Get Base EC FW version. More...
EFI_STATUS | GetEc2EcProtocolVersion (OUT UINT8 *DataBuffer)
Get EC-EC Protocol version. More...
EFI_STATUS | DisablePchDtsReading (IN UINT8 Disable)
Disable PCH DTS reading on SMLink 1. More...
EFI_STATUS | WakeUpEc (VOID)
Wake up EC. More...
EFI_STATUS | UpdatePwm (VOID)
Send Update PWM command to EC. More...
EFI_STATUS | GetFanSpeed (IN UINT8 Pwmvalue, OUT UINT16 *Speed)
Updates the PWM to the given value and returns the Fan speed. More...
EFI_STATUS | DfctFastChargingMode (IN BOOLEAN Enable)
Select charging method. More...
VOID | EcForceResetAfterAcRemoval (IN UINT8 ForceResetAfterAcRemovalVar)
EcForceResetAfterAcRemoval. More...

Detailed Description

EC miscellaneous library functions.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcMiscLib.h.

Function Documentation

VOID ClearTenSecPwrButtonMode ( VOID )

Clear ten second power button mode.

EFI_STATUS DetectEcRevision ( OUT UINT8 * DataBuffer )

Detect EC revision.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS DetectPmicVendorID ( OUT UINT8 * DataBuffer )

Detect Pmic Vendor ID.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS DfctFastChargingMode ( IN BOOLEAN Enable )

Select charging method.

Parameters
[in] Enable TURE - Fast charging (DFCT) FALSE - Normal charging
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS DisableEcSmiMode ( VOID )

Send disable SMI mode command to EC.

Parameters
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS DisablePchDtsReading ( IN UINT8 Disable )

Disable PCH DTS reading on SMLink 1.

Parameters
[in] Disable 0: Enable PCH DTS reading 1: Disable PCH DTS reading
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
VOID EcForceResetAfterAcRemoval ( IN UINT8 ForceResetAfterAcRemovalVar )

EcForceResetAfterAcRemoval.

Parameters
[in] ForceResetAfterAcRemovalVar 0 : Clear AC Removal reset bit in EC 1 : Set AC Removal reset bit in EC
EFI_STATUS EcReset ( VOID )

Do EC reset.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS EcResetEcInNormalMode ( VOID )

Initiate EC reset sequence.

EC is in Normal Mode.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS EnableEcAcpiMode ( IN BOOLEAN Enable )

Send enable ACPI mode command to EC.

Parameters
[in] Enable TURE - Enable EC ACPI mode FALSE - Disable EC ACPI mode
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS EnableLanPower ( IN BOOLEAN Enable )

Enable LAN power.

Parameters
[in] Enable TURE - Enable LAN power FALSE - Disable LAN power
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
VOID EnableSataPort2Power ( VOID )

Enable SATA port2 power.

EFI_STATUS ExitLowPowerMode ( VOID )

Send Exit Low Power Mode command to EC.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS GetBaseEcFwVersion ( OUT UINT8 * DataBuffer )

Get Base EC FW version.

Parameters
[out] DataBuffer Byte 1: Base EC FW major version Byte 2: Base EC FW minor version
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS GetBatteryNumber ( OUT UINT8 * DataBuffer )

Get the number of battery.

Parameters
[out] DataBuffer The number of battery
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS GetBoardInfo ( OUT UINT16 * BoardFabId )

Get board fab ID.

Parameters
[out] BoardFabId
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS GetEc2EcProtocolVersion ( OUT UINT8 * DataBuffer )

Get EC-EC Protocol version.

Parameters
[out] DataBuffer Byte 1: Lid EC protocol version Byte 2: Base EC protocol version
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS GetFanSpeed | ( | IN UINT8 | Pwmvalue,
 |  | OUT UINT16 * | Speed
 | ) |  |

Updates the PWM to the given value and returns the Fan speed.

Parameters
Pwmvalue | Pwm ending value
Speed | Updates the Speed
Return values
EFI_SUCCESS | when successfully able to get the nominal data.
ERROR | Error if anything went wrong.
EFI_STATUS GetHotkeyScanCode ( OUT UINT8 * DataBuffer )

Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)

Parameters
[out] DataBuffer Scan code of hotkey
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS GetPcieDockStatus ( OUT UINT8 * DataBuffer )

Get PCIe dock status.

Parameters
[out] DataBuffer PCIe dock status
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
BOOLEAN PowerStateIsAc ( VOID )

Get power state from EC.

If power state cannot be determined, battery powered is assumed.

Parameters
TRUE | AC powered
FALSE | Battery powered
EFI_STATUS QuerySmiEvent ( OUT UINT8 * DataBuffer )

Query SMI event.

Parameters
[out] DataBuffer SMI event
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS QuerySysStatus ( OUT UINT8 * DataBuffer )

Query system status.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS ReadEcRam ( IN OUT UINT8 * DataBuffer )

Read data from EC RAM.

Parameters
[in]
EFI_STATUS SetEcCriticalShutdownTemperature ( IN UINT8 DataBuffer )

Set EC critical shutdown temperature.

Parameters
[in] DataBuffer Shutdown temperature
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS SetPmicVoltage | ( | IN UINT8 | EcDataVcc,
 |  | IN UINT8 | EcDataVddq
 | ) |  |

Set Pmic Voltage.

Parameters
[in] | EcDataVcc
[in] | EcDataVddq
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS SetSlpS0Voltage ( IN UINT8 EcDataV085ACNT )

Set SLP_S0 Voltage.

Parameters
[in] EcDataV085ACNT
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS SystemPowerOff ( VOID )

System power off.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS UpdateDevicePower ( VOID )

Update Device Power.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS UpdatePwm ( VOID )

Send Update PWM command to EC.

Parameters
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS UsbcSxEntry ( IN OUT UINT8 * DataBuffer )

USBC Sx Entry Wait.

Todo:
: it should move to BaseEcAcpiLib once BaseEcAcpiLib has been created.
Parameters
[in]
EFI_STATUS UsbcSxExit ( OUT UINT8 * DataBuffer )

USBC Sx Exit Wait.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error
EFI_STATUS WakeUpEc ( VOID )

Wake up EC.

Return values
TRUE | EC wake up successfully.
FALSE | Fail to wake up EC.
EFI_STATUS WriteEcRam ( IN OUT UINT8 * DataBuffer )

Write data to EC RAM.

Parameters
[in]


IceLake Platform Sample Code: EcPlatformInitDxe.c File Reference

  • PlatformInit
  • PlatformInitDxe
Functions
EcPlatformInitDxe.c File Reference

Source code file for the Platform Init DXE module. More...

#include "PlatformInitDxe.h"
#include <Include/Protocol/SimpleTextIn.h>
#include <Include/Library/UefiLib.h>
Include dependency graph for EcPlatformInitDxe.c:

Go to the source code of this file.

Functions

VOID CheckLidBaseEcProtocolVersion (VOID)
Check Lid and Base EC Protocol Version. More...

Detailed Description

Source code file for the Platform Init DXE module.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file EcPlatformInitDxe.c.

Function Documentation

VOID CheckLidBaseEcProtocolVersion ( VOID )

Check Lid and Base EC Protocol Version.

Verifies LID base EC protocol version

Definition at line 49 of file EcPlatformInitDxe.c.


IceLake Platform Sample Code: EcTcssLib.h File Reference

  • Library
Functions
EcTcssLib.h File Reference

EC TCSS library functions. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/EcCommands.h>
#include <Library/EcLib.h>
Include dependency graph for EcTcssLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | UsbcIomReadyNotify (IN OUT UINT8 *DataBuffer)
USBC IOM Ready Notify. More...
EFI_STATUS | UsbcGetUsbConnStatus (IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Entry Wait. More...
EFI_STATUS | UsbcSxEntry (IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
Send enable ACPI mode command to EC. More...
EFI_STATUS | UsbcSxExit (OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Exit Wait. More...

Detailed Description

EC TCSS library functions.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcTcssLib.h.

Function Documentation

EFI_STATUS UsbcGetUsbConnStatus | ( | IN OUT UINT8 * | DataBuffer,
 |  | IN UINT32 | Timeout
 | ) |  |

USBC Sx Entry Wait.

Parameters
[in]
EFI_STATUS UsbcIomReadyNotify ( IN OUT UINT8 * DataBuffer )

USBC IOM Ready Notify.

Parameters
[in]
EFI_STATUS UsbcSxEntry | ( | IN OUT UINT8 * | DataBuffer,
 |  | IN UINT32 | Timeout
 | ) |  |

Send enable ACPI mode command to EC.

Parameters
[in]
EFI_STATUS UsbcSxExit | ( | OUT UINT8 * | DataBuffer,
 |  | IN UINT32 | Timeout
 | ) |  |

USBC Sx Exit Wait.

Parameters
[out] | DataBuffer
[in] | Timeout
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error


IceLake Platform Sample Code: Efi.h File Reference

Efi.h File Reference
#include "Tiano.h"
Include dependency graph for Efi.h:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Efi.h.


IceLake Platform Sample Code: EfiUsbFnIo.h File Reference

  • Protocol
Classes | Typedefs
EfiUsbFnIo.h File Reference

EFI USB function IO Protocol This protocol supports Usb Function IO API. More...

#include <IndustryStandard/Usb.h>
Include dependency graph for EfiUsbFnIo.h:

Go to the source code of this file.

Classes

struct EFI_USB_INTERFACE_INFO
USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec. More...

Typedefs

typedef EFI_STATUS(* | EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINTN Size, OUT VOID **Buffer)
Allocates transfer buffer of the specified size that satisfies controller requirements. More...
typedef EFI_STATUS(* | EFI_USBFN_IO_FREE_TRANSFER_BUFFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN VOID *Buffer)
Deallocates the memory allocated for the transfer buffer by AllocateTransferBuffer function.
typedef EFI_STATUS(* | EFI_USBFN_IO_DETECT_PORT) (IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_PORT_TYPE *PortType)
Returns information about what type of device was attached.
typedef EFI_STATUS(* | EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_DEVICE_INFO *DeviceInfo)
Configure endpoints based on supplied device and configuration descriptors.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_ENDPOINT_TYPE EndpointType, IN EFI_USB_BUS_SPEED BusSpeed, OUT UINT16 *MaxPacketSize)
Returns the maximum packet size of the specified endpoint type for the supplied bus speed.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) (IN EFI_USBFN_IO_PROTOCOL *This, OUT UINTN *MaxTransferSize)
Returns the maximum supported transfer size.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_DEVICE_INFO) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USBFN_DEVICE_INFO_ID Id, IN OUT UINTN *BufferSize, OUT VOID *Buffer OPTIONAL)
Returns device specific information based on the supplied identifier as a Unicode string.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) (IN EFI_USBFN_IO_PROTOCOL *This, OUT UINT16 *Vid, OUT UINT16 *Pid)
Returns vendor-id and product-id of the device.
typedef EFI_STATUS(* | EFI_USBFN_IO_ABORT_TRANSFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction)
Aborts transfer on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT BOOLEAN *State)
Returns the stall state on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN BOOLEAN State)
Sets or clears the stall state on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_EVENTHANDLER) (IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_MESSAGE *Message, IN OUT UINTN *PayloadSize, OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload)
This function is called repeatedly to receive updates on USB bus states, receive, transmit status changes on endpoints and setup packet on endpoint 0.
typedef EFI_STATUS(* | EFI_USBFN_IO_TRANSFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
Primary function to handle transfer in either direction based on specified direction and on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_START_CONTROLLER) (IN EFI_USBFN_IO_PROTOCOL *This)
This function supplies power to the USB controller if needed, initialize hardware and internal data structures, and then return. More...
typedef EFI_STATUS(* | EFI_USBFN_IO_STOP_CONTROLLER) (IN EFI_USBFN_IO_PROTOCOL *This)
This function disables the hardware device by resetting the run/stop bit and power off the USB controller if needed.
typedef EFI_STATUS(* | EFI_USBFN_IO_SET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN UINTN BufferSize, IN VOID *Buffer)
This function sets the configuration policy for the specified non-control endpoint. More...
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
This function retrieves the configuration policy for the specified non-control endpoint. More...

Detailed Description

EFI USB function IO Protocol This protocol supports Usb Function IO API.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file EfiUsbFnIo.h.

Typedef Documentation

typedef EFI_STATUS( * EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINTN Size, OUT VOID **Buffer)

Allocates transfer buffer of the specified size that satisfies controller requirements.

The AllocateTransferBuffer function allocates a memory region of Size bytes and returns the address of the allocated memory that satisfies underlying controller requirements in the location referenced by Buffer.

Definition at line 221 of file EfiUsbFnIo.h.

typedef EFI_STATUS( * EFI_USBFN_IO_GET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)

This function retrieves the configuration policy for the specified non-control endpoint.

There are no associated calling restrictions for this function.

Definition at line 415 of file EfiUsbFnIo.h.

typedef EFI_STATUS( * EFI_USBFN_IO_SET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN UINTN BufferSize, IN VOID *Buffer)

This function sets the configuration policy for the specified non-control endpoint.

Refer to the description for calling restrictions.

Definition at line 399 of file EfiUsbFnIo.h.

typedef EFI_STATUS( * EFI_USBFN_IO_START_CONTROLLER) (IN EFI_USBFN_IO_PROTOCOL *This)

This function supplies power to the USB controller if needed, initialize hardware and internal data structures, and then return.

The port must not be activated by this function.

Definition at line 378 of file EfiUsbFnIo.h.


IceLake Platform Sample Code: EmmcCardInfoProtocol.h File Reference

  • Protocol
EmmcCardInfoProtocol.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file EmmcCardInfoProtocol.h.


IceLake Platform Sample Code: Facs.h File Reference

  • Acpi
  • AcpiTables
  • Facs
Facs.h File Reference

This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS). More...

#include <IndustryStandard/Acpi.h>
Include dependency graph for Facs.h:

Go to the source code of this file.

Detailed Description

This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS).

All changes to the FACS contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Facs.h.


IceLake Platform Sample Code: Fadt6.1.h File Reference

  • Acpi
  • AcpiTables
  • Fadt
Fadt6.1.h File Reference

This file describes the contents of the ACPI Fixed ACPI Description Table (FADT). More...

#include <IndustryStandard/Acpi.h>
#include "Register/PchRegsPmcCnl.h"
Include dependency graph for Fadt6.1.h:
This graph shows which files directly or indirectly include this file:

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Detailed Description

This file describes the contents of the ACPI Fixed ACPI Description Table (FADT).

All changes to the FADT contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Fadt6.1.h.


IceLake Platform Sample Code: FirwmareConfigurations.h File Reference

FirwmareConfigurations.h File Reference

This header file provides definitions of firmware configuration. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This header file provides definitions of firmware configuration.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file FirwmareConfigurations.h.


IceLake Platform Sample Code: FspPolicyInitLib.h File Reference

  • Library
FspPolicyInitLib.h File Reference

Function prototype of FspPolicyInitLib. More...

#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
Include dependency graph for FspPolicyInitLib.h:

Go to the source code of this file.

Detailed Description

Function prototype of FspPolicyInitLib.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file FspPolicyInitLib.h.


IceLake Platform Sample Code: Fwu_Common.h File Reference

  • Library
Classes | Macros | Typedefs
Fwu_Common.h File Reference
#include "ver.h"
#include "mkhi_hdrs.h"
Include dependency graph for Fwu_Common.h:

Go to the source code of this file.

Classes

struct | _FWU_FLASH_IMAGE_START_MSG_REPLY
FWU_FLASH_IMAGE_START_MSG - start the update process. More...
struct | _FWU_GET_VERSION_MSG_REPLY
FWU_GET_VERSION_MSG - start the update process. More...
struct | _FWU_START_MSG
FWU_START_MSG - start the update process. More...
struct | _FWU_DATA_MSG
FWU_DATA_MSG - send data during the update process. More...
struct | _FWU_END_MESSAGE
FWU_END_MSG - end the update process. More...
struct | _FWU_GET_INFO_MSG
FWU_GET_INFO_MSG - get info. More...
struct | _FWU_GET_FEATURE_STATE_MSG_REPLY
FWU_GET_FEATURE_STATE_MSG - get info. More...
struct | _FWU_GET_PLATFORM_TYPE_MSG_REPLY
FWU_GET_PLATFORM_TYPE_MSG - get plat type. More...
struct | _FWU_VERIFY_OEMID_MSG
FWU_VERIFY_OEMID_MSG - verify OEMID. More...
struct | _FWU_GET_OEMID_MSG_REPLY
FWU_GET_OEMID_MSG - verify OEMID. More...
struct | _FWU_IMAGE_COMPATABILITY_CHECK_MSG
FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability. More...
struct | _FWU_GET_UPDATE_DATA_EXTENSION_MSG
FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability. More...
struct | _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image. More...
struct | _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image. More...
struct | _FWU_GET_IPU_PT_ATTRB_MSG
FWU_GET_IPU_PT_ATTRB_MSG - get info status. More...
struct | _FWU_GET_FWU_INFO_STATUS_MSG
FWU_GET_FWU_INFO_STATUS_MSG - get info status. More...
struct | _ME_FWU_INFO_MSG
ME_FWU_INFO_MSG - get ME firmware update info message. More...
struct | _FWU_CONFIRM_LIVE_PING_MSG
FWU_CONFIRM_LIVE_PING_MSG - confirm live ping. More...
struct | _FWU_VERIFY_PWD_MSG
FWU_VERIFY_PWD_MSG - confirm live ping. More...
struct | _FWU_INVALID_MSG_REPLY
FWU_INVALID_MSG - confirm live ping. More...

Macros

#define STATUS_SUCCESS 0x0
The operation completed successfully.

Typedefs

typedef struct _FWU_FLASH_IMAGE_START_MSG_REPLY | FWU_FLASH_IMAGE_START_MSG_REPLY
FWU_FLASH_IMAGE_START_MSG - start the update process. More...
typedef struct _FWU_GET_VERSION_MSG_REPLY | FWU_GET_VERSION_MSG_REPLY
FWU_GET_VERSION_MSG - start the update process. More...
typedef struct _FWU_START_MSG | FWU_START_MSG
FWU_START_MSG - start the update process. More...
typedef struct _FWU_DATA_MSG | FWU_DATA_MSG
FWU_DATA_MSG - send data during the update process. More...
typedef struct _FWU_END_MESSAGE | FWU_END_MESSAGE
FWU_END_MSG - end the update process. More...
typedef struct _FWU_GET_INFO_MSG | FWU_GET_INFO_MSG
FWU_GET_INFO_MSG - get info. More...
typedef struct _FWU_GET_FEATURE_STATE_MSG_REPLY | FWU_GET_FEATURE_STATE_MSG_REPLY
FWU_GET_FEATURE_STATE_MSG - get info. More...
typedef struct _FWU_GET_PLATFORM_TYPE_MSG_REPLY | FWU_GET_PLATFORM_TYPE_MSG_REPLY
FWU_GET_PLATFORM_TYPE_MSG - get plat type. More...
typedef struct _FWU_VERIFY_OEMID_MSG | FWU_VERIFY_OEMID_MSG
FWU_VERIFY_OEMID_MSG - verify OEMID. More...
typedef struct _FWU_GET_OEMID_MSG_REPLY | FWU_GET_OEMID_MSG_REPLY
FWU_GET_OEMID_MSG - verify OEMID. More...
typedef struct _FWU_IMAGE_COMPATABILITY_CHECK_MSG | FWU_IMAGE_COMPATABILITY_CHECK_MSG
FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability. More...
typedef struct _FWU_GET_UPDATE_DATA_EXTENSION_MSG | FWU_GET_UPDATE_DATA_EXTENSION_MSG
FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability. More...
typedef struct _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE | FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image. More...
typedef struct _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE | FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image. More...
typedef struct _FWU_GET_IPU_PT_ATTRB_MSG | FWU_GET_IPU_PT_ATTRB_MSG
FWU_GET_IPU_PT_ATTRB_MSG - get info status. More...
typedef struct _FWU_GET_FWU_INFO_STATUS_MSG | FWU_GET_FWU_INFO_STATUS_MSG
FWU_GET_FWU_INFO_STATUS_MSG - get info status. More...
typedef struct _ME_FWU_INFO_MSG | ME_FWU_INFO_MSG
ME_FWU_INFO_MSG - get ME firmware update info message. More...
typedef struct _FWU_CONFIRM_LIVE_PING_MSG | FWU_CONFIRM_LIVE_PING_MSG
FWU_CONFIRM_LIVE_PING_MSG - confirm live ping. More...
typedef struct _FWU_VERIFY_PWD_MSG | FWU_VERIFY_PWD_MSG
FWU_VERIFY_PWD_MSG - confirm live ping. More...
typedef struct _FWU_INVALID_MSG_REPLY | FWU_INVALID_MSG_REPLY
FWU_INVALID_MSG - confirm live ping. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2005 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Fwu_Common.h.

Typedef Documentation

typedef struct _FWU_CONFIRM_LIVE_PING_MSG FWU_CONFIRM_LIVE_PING_MSG

FWU_CONFIRM_LIVE_PING_MSG - confirm live ping.

: FWU_CONFIRM_LIVE_PING_MSG

typedef struct _FWU_DATA_MSG FWU_DATA_MSG

FWU_DATA_MSG - send data during the update process.

: FWU_DATA_MSG

typedef struct _FWU_END_MESSAGE FWU_END_MESSAGE

FWU_END_MSG - end the update process.

: FWU_END_MSG

typedef struct _FWU_FLASH_IMAGE_START_MSG_REPLY FWU_FLASH_IMAGE_START_MSG_REPLY

FWU_FLASH_IMAGE_START_MSG - start the update process.

: FWU_FLASH_IMAGE_START_MSG

typedef struct _FWU_GET_FEATURE_STATE_MSG_REPLY FWU_GET_FEATURE_STATE_MSG_REPLY

FWU_GET_FEATURE_STATE_MSG - get info.

: FWU_GET_FEATURE_STATE_MSG

typedef struct _FWU_GET_FWU_INFO_STATUS_MSG FWU_GET_FWU_INFO_STATUS_MSG

FWU_GET_FWU_INFO_STATUS_MSG - get info status.

: FWU_GET_FWU_INFO_STATUS_MSG

typedef struct _FWU_GET_INFO_MSG FWU_GET_INFO_MSG

FWU_GET_INFO_MSG - get info.

: FWU_GET_INFO_MSG

typedef struct _FWU_GET_IPU_PT_ATTRB_MSG FWU_GET_IPU_PT_ATTRB_MSG

FWU_GET_IPU_PT_ATTRB_MSG - get info status.

: FWU_GET_IPU_PT_ATTRB_MSG

typedef struct _FWU_GET_OEMID_MSG_REPLY FWU_GET_OEMID_MSG_REPLY

FWU_GET_OEMID_MSG - verify OEMID.

: FWU_GET_OEMID_MSG

typedef struct _FWU_GET_PLATFORM_TYPE_MSG_REPLY FWU_GET_PLATFORM_TYPE_MSG_REPLY

FWU_GET_PLATFORM_TYPE_MSG - get plat type.

: FWU_GET_PLATFORM_TYPE_MSG

typedef struct _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE

FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.

: FWU_GET_RESTORE_POINT_IMAGE_MESSAGE

typedef struct _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE FWU_GET_RESTORE_POINT_IMAGE_MESSAGE

FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.

: FWU_GET_RESTORE_POINT_IMAGE_MESSAGE

typedef struct _FWU_GET_UPDATE_DATA_EXTENSION_MSG FWU_GET_UPDATE_DATA_EXTENSION_MSG

FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability.

: FWU_GET_UPDATE_DATA_EXTENSION_MSG

typedef struct _FWU_GET_VERSION_MSG_REPLY FWU_GET_VERSION_MSG_REPLY

FWU_GET_VERSION_MSG - start the update process.

: FWU_GET_VERSION_MSG

typedef struct _FWU_IMAGE_COMPATABILITY_CHECK_MSG FWU_IMAGE_COMPATABILITY_CHECK_MSG

FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability.

: FWU_IMAGE_COMPATABILITY_CHECK_MSG

typedef struct _FWU_INVALID_MSG_REPLY FWU_INVALID_MSG_REPLY

FWU_INVALID_MSG - confirm live ping.

: FWU_INVALID_MSG

typedef struct _FWU_START_MSG FWU_START_MSG

FWU_START_MSG - start the update process.

: FWU_START_MSG

typedef struct _FWU_VERIFY_OEMID_MSG FWU_VERIFY_OEMID_MSG

FWU_VERIFY_OEMID_MSG - verify OEMID.

: FWU_VERIFY_OEMID_MSG

typedef struct _FWU_VERIFY_PWD_MSG FWU_VERIFY_PWD_MSG

FWU_VERIFY_PWD_MSG - confirm live ping.

: FWU_VERIFY_PWD_MSG

typedef struct _ME_FWU_INFO_MSG ME_FWU_INFO_MSG

ME_FWU_INFO_MSG - get ME firmware update info message.

: ME_FWU_INFO_MSG

Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: FWUpdateLib.h File Reference

  • Library
Classes | Enumerations
FWUpdateLib.h File Reference

Go to the source code of this file.

Classes

struct | FWU_GET_INFO_MESSAGE
FWU_GET_INFO_MESSAGE - get version. More...
struct | FWU_DATA_MESSAGE
FWU_DATA_MESSAGE - data fragment of the image. More...

Enumerations

enum _FWUPD_POWER_SOURCE

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file FWUpdateLib.h.

Enumeration Type Documentation

enum _FWUPD_POWER_SOURCE
Enumerator
FWUPD_POWER_SOURCE_AC | AC Power source.
FWUPD_POWER_SOURCE_DC | DC Power source.
FWUPD_POWER_SOURCE_UNKOWN | Unable to determine power source.

Definition at line 94 of file FWUpdateLib.h.


IceLake Platform Sample Code: GfxInt15Interface.c File Reference

  • PlatformInit
  • PlatformInitDxe
Functions
GfxInt15Interface.c File Reference

This is a driver to produce Int15 hook. More...

#include "PlatformInitDxe.h"
#include <Uefi/UefiBaseType.h>
#include <Protocol/LegacyInterruptHandler.h>
#include <Protocol/FirmwareVolume2.h>
Include dependency graph for GfxInt15Interface.c:

Go to the source code of this file.

Functions

EFI_STATUS | LoadRealModeFile (EFI_GUID *Guid, VOID **Buffer, UINTN *BufferSize)
Loads real mode file form the FV. More...
VOID | InitializeGfxInt15 (VOID)
Inititialize Interrupt 15.

Detailed Description

This is a driver to produce Int15 hook.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GfxInt15Interface.c.

Function Documentation

EFI_STATUS LoadRealModeFile | ( | EFI_GUID * | Guid,
 |  | VOID ** | Buffer,
 |  | UINTN * | BufferSize
 | ) |  |

Loads real mode file form the FV.

Parameters
[in] | Guid
[in] | Buffer
[in] | BufferSize
Return values
EFI_SUCCESS Function has completed successfully.

Definition at line 55 of file GfxInt15Interface.c.


IceLake Platform Sample Code: GopPolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
GopPolicyInitDxe.c File Reference

This file initialises and Installs GopPolicy Protocol. More...

#include "GopPolicyInitDxe.h"
#include <Protocol/GopPolicy.h>
Include dependency graph for GopPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS | GetPlatformLidStatus (OUT LID_STATUS *CurrentLidStatus)
EFI_STATUS | GetPlatformDockStatus (OUT DOCK_STATUS CurrentDockStatus)
EFI_STATUS | GetVbtData (OUT EFI_PHYSICAL_ADDRESS *VbtAddress, OUT UINT32 *VbtSize)
EFI_STATUS | GopPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy. More...

Detailed Description

This file initialises and Installs GopPolicy Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GopPolicyInitDxe.c.

Function Documentation

EFI_STATUS GetPlatformDockStatus ( OUT DOCK_STATUS CurrentDockStatus )
Parameters
[out] CurrentDockStatus
Return values
EFI_SUCCESS
EFI_UNSUPPORTED

Definition at line 95 of file GopPolicyInitDxe.c.

EFI_STATUS GetPlatformLidStatus ( OUT LID_STATUS * CurrentLidStatus )
Parameters
[out] CurrentLidStatus
Return values
EFI_SUCCESS
EFI_UNSUPPORTED

Definition at line 55 of file GopPolicyInitDxe.c.

Here is the call graph for this function:

EFI_STATUS GetVbtData | ( | OUT EFI_PHYSICAL_ADDRESS * | VbtAddress,
 |  | OUT UINT32 * | VbtSize
 | ) |  |
Parameters
[out] | VbtAddress
[out] | VbtSize
Return values
EFI_SUCCESS
EFI_NOT_FOUND

Definition at line 113 of file GopPolicyInitDxe.c.

EFI_STATUS GopPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize GOP DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 210 of file GopPolicyInitDxe.c.

Here is the call graph for this function:


IceLake Platform Sample Code: GopPolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
GopPolicyInitDxe.h File Reference

Header file for the GopPolicyInitDxe Driver. More...

#include <Protocol/FirmwareVolume2.h>
#include <SetupVariable.h>
#include <Library/UefiLib.h>
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/EcMiscLib.h>
#include <PlatformBoardId.h>
#include <Library/PcdLib.h>
Include dependency graph for GopPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS GopPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy. More...

Detailed Description

Header file for the GopPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GopPolicyInitDxe.h.

Function Documentation

EFI_STATUS GopPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize GOP DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 210 of file GopPolicyInitDxe.c.

Here is the call graph for this function:


IceLake Platform Sample Code: GpioExpanderLib.h File Reference

  • Library
Functions
GpioExpanderLib.h File Reference

Support for IO expander TCA6424. More...

#include <Uefi.h>
#include <Library/DebugLib.h>
#include <Library/TimerLib.h>
#include <Library/IoLib.h>
#include <Library/UefiLib.h>
#include <PchAccess.h>
#include <Library/PchSerialIoLib.h>
Include dependency graph for GpioExpanderLib.h:

Go to the source code of this file.

Functions

VOID | GpioExpSetDirection (IN UINT8 Expander, IN UINT8 Pin, IN UINT8 Direction)
Set the Direction value for the given Expander Gpio pin. More...
VOID | GpioExpSetPolarity (IN UINT8 Expander, IN UINT8 Pin, IN UINT8 Polarity)
Set the input value for the given Expander Gpio pin. More...
VOID | GpioExpSetOutput (IN UINT8 Expander, IN UINT8 Pin, IN UINT8 Value)
Set the Output value for the given Expander Gpio pin. More...
UINT8 | GpioExpGetInput (IN UINT8 Expander, IN UINT8 Pin)
Returns the data from register value giving in the input. More...
VOID | GpioExpBulkConfig (IN UINT8 Expander, IN UINT32 Direction, IN UINT32 Polarity, IN UINT32 Output)
Configures all registers of a single IO Expander in one go. More...
EFI_STATUS | GpioExpGetController (OUT UINT8 *Controller)
Returns the Controller on which GPIO expander is present. More...

Detailed Description

Support for IO expander TCA6424.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GpioExpanderLib.h.

Function Documentation

VOID GpioExpBulkConfig | ( | IN UINT8 | Expander,
 |  | IN UINT32 | Direction,
 |  | IN UINT32 | Polarity,
 |  | IN UINT32 | Output
 | ) |  |

Configures all registers of a single IO Expander in one go.

Parameters
[in] | Expander | Expander number (0/1)
[in] | Direction | Bit-encoded direction values. BIT0 is for pin0, etc. 0=output, 1=input
[in] | Polarity | Bit-encoded input inversion values. BIT0 is for pin0, etc. 0=normal, 1=inversion
[in] | Output | Bit-encoded output state, ignores polarity, only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
EFI_STATUS GpioExpGetController ( OUT UINT8 * Controller )

Returns the Controller on which GPIO expander is present.

This function returns the Controller value

Parameters
[out] Controller Pointer to a Controller value on which I2C expander is configured.
Return values
EFI_SUCCESS non.
UINT8 GpioExpGetInput | ( | IN UINT8 | Expander,
 |  | IN UINT8 | Pin
 | ) |  |

Returns the data from register value giving in the input.

This function is to get the data from the Expander Registers by following the I2C Protocol communication

Parameters
[in] | Bar0 | Bar address of the SerialIo Controller
[in] | Address | Expander Value with in the Contoller
[in] | Register | Address of Input/Output/Configure/Polarity registers with in the Expander
Return values
UINT8 Value returned from the register
VOID GpioExpSetDirection | ( | IN UINT8 | Expander,
 |  | IN UINT8 | Pin,
 |  | IN UINT8 | Direction
 | ) |  |

Set the Direction value for the given Expander Gpio pin.

This function is to Set the direction value for the GPIO Pin within the giving Expander.

Parameters
[in] | Expander | Expander Value with in the Contoller
[in] | Pin | Pin with in the Expnader Value
[in] | Value | none
VOID GpioExpSetOutput | ( | IN UINT8 | Expander,
 |  | IN UINT8 | Pin,
 |  | IN UINT8 | Value
 | ) |  |

Set the Output value for the given Expander Gpio pin.

This function is to Set the Output value for the GPIO Pin within the giving Expander.

Parameters
[in] | Expander | Expander Value with in the Contoller
[in] | Pin | Pin with in the Expnader Value
[in] | Value | none
VOID GpioExpSetPolarity | ( | IN UINT8 | Expander,
 |  | IN UINT8 | Pin,
 |  | IN UINT8 | Polarity
 | ) |  |

Set the input value for the given Expander Gpio pin.

This function is to get the input value for the GPIO Pin within the giving Expander.

Parameters
[in] | Expander | Expander Value with in the Contoller
[in] | Pin | Pin with in the Expnader Value
[in] | Value | none


IceLake Platform Sample Code: HidI2cPlatformSupportLib.h File Reference

  • Library
HidI2cPlatformSupportLib.h File Reference

Support for IO expander TCA6424. More...

#include <Uefi.h>
Include dependency graph for HidI2cPlatformSupportLib.h:

Go to the source code of this file.

Detailed Description

Support for IO expander TCA6424.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file HidI2cPlatformSupportLib.h.


IceLake Platform Sample Code: Hpet.h File Reference

  • Acpi
  • AcpiTables
  • Hpet
Hpet.h File Reference

This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET). More...

#include <IndustryStandard/Acpi30.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
Include dependency graph for Hpet.h:

Go to the source code of this file.

Detailed Description

This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET).

All changes to the HPET contents should be done in this file.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Hpet.h.


IceLake Platform Sample Code: HstiIbvFeatureBit.h File Reference

HstiIbvFeatureBit.h File Reference

This file contains various definitions for IHV HSTI implementation including error string definitions. More...

Go to the source code of this file.

Detailed Description

This file contains various definitions for IHV HSTI implementation including error string definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file HstiIbvFeatureBit.h.


IceLake Platform Sample Code: I2cAccessLib.h File Reference

  • Library
I2cAccessLib.h File Reference

Support for IO expander TCA6424. More...

#include <Uefi.h>
#include <Library/DebugLib.h>
#include <Library/TimerLib.h>
#include <Library/IoLib.h>
#include <Library/UefiLib.h>
#include <PchAccess.h>
#include <Library/PchSerialIoLib.h>
Include dependency graph for I2cAccessLib.h:

Go to the source code of this file.

Detailed Description

Support for IO expander TCA6424.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file I2cAccessLib.h.


IceLake Platform Sample Code: I2cBusConfigurationManagement.h File Reference

  • Protocol
Classes | Typedefs
I2cBusConfigurationManagement.h File Reference

I2C bus configuration management interface. More...

#include <Protocol/I2cMaster.h>
Include dependency graph for I2cBusConfigurationManagement.h:

Go to the source code of this file.

Classes

struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2C bus configuration management protocol. More...

Typedefs

typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL | EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2C bus configuration management protocol. More...
typedef EFI_STATUS(* | EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION) (IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, IN UINTN I2cBusConfiguration, IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster, IN EFI_EVENT Event OPTIONAL, IN EFI_STATUS *Status OPTIONAL)
Enable access to an I2C bus configuration. More...

Detailed Description

I2C bus configuration management interface.

The I2C host driver uses this API to configure the switches and multiplexers in the I2C bus to gain access to the desired I2C device at its maximum clock frequency.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file I2cBusConfigurationManagement.h.

Typedef Documentation

typedef EFI_STATUS( * EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION) (IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, IN UINTN I2cBusConfiguration, IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster, IN EFI_EVENT Event OPTIONAL, IN EFI_STATUS *Status OPTIONAL)

Enable access to an I2C bus configuration.

This routine must be called at or below TPL_NOTIFY. For synchronous requests this routine must be called at or below TPL_CALLBACK.

Reconfigure the switches and multiplexers in the I2C bus to enable access to a specific I2C bus configuration. Also select the maximum clock frequency for this I2C bus configuration.

This routine uses the I2cMaster protocol when the platform routine needs to perform I2C operations on the local bus. This eliminates any recursion in the I2C stack for configuration operations on the local bus. This works because the local I2C bus is idle while the I2C bus configuration is being enabled.

The platform layer must perform I2C operations on other I2C busses by using the EFI_I2C_HOST_PROTOCOL or third party driver interface for the specific device. This requirement is because the I2C host driver controls the flow of requests to the I2C conroller. Use the EFI_I2C_HOST_PROTOCOL when the device is not defined in the platform's ACPI tables. Use the third party driver when it is available or EFI_I2C_BUS_PROTOCOL when the thrid party driver is not available but the device is defined in the platform's ACPI tables.

Parameters
[in] | This | Address of an EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL structure
[in] | I2cBusConfiguration | Index into a list or array of I2C bus configurations.
[in] | I2cMaster | Address of an EFI_I2C_MASTER_PROTOCOL structure. This protocol may only be used for this specific operation and should not be referenced after this operation completes!
[in] | Event | Event to set when the operation is complete.
[out] | Status | Buffer to receive the operation status.
Return values
EFI_SUCCESS | The operation completed successfully.
EFI_DEVICE_ERROR | There was an I2C error (NACK) during the operation. This could indicate the slave device is not present.
EFI_INVALID_PARAMETER | I2cMaster is NULL
EFI_INVALID_PARAMETER | TPL is too high
EFI_NO_MAPPING | Invalid I2cBusConfiguration value
EFI_NO_RESPONSE | The I2C device is not responding to the slave address. EFI_DEVICE_ERROR may also be returned if the controller can not distinguish when the NACK occurred.
EFI_NOT_FOUND | I2C slave address exceeds maximum address
EFI_NOT_READY | I2C bus is busy or operation pending, wait for the event and then read status.
EFI_OUT_OF_RESOURCES | Insufficient memory for I2C operation
EFI_TIMEOUT | The transaction did not complete within an internally specified timeout period.

Definition at line 166 of file I2cBusConfigurationManagement.h.

typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

I2C bus configuration management protocol.

The I2C driver stack uses the concept of an I2C bus configuration as a way to describe a particular state of the switches and multiplexers in the I2C bus.

A simple I2C bus does not have any multiplexers or switches is described to the I2C driver stack with a single I2C bus configuration.

An I2C bus with switches and multiplexers use an I2C bus configuration to describe each of the unique settings for the switches and multiplexers. However the I2C platform driver only needs to define the I2C bus configurations that the software uses, which is a subset of the total.

The I2C bus configuration description includes a list of I2C devices which may be accessed when this I2C bus configuration is enabled. I2C devices before a switch or multiplexer should be included in one I2C bus configuration while I2C devices after a switch or multiplexer should be on another I2C bus configuration.

The I2C bus configuration management protocol is an optional protocol provided by the I2C platform driver. When the I2C bus configuration protocol is not defined the host driver assumes a single I2C bus configuration and operates the I2C bus at 100 KHz. When the I2C bus configuration protocol is available, the I2C host driver uses the I2C bus configuration protocol to call into the I2C platform driver to set the switches and multiplexers and set the maximum I2C bus frequency.

The platform designers determine the maximum I2C bus frequency by selecting a frequency which supports all of the I2C devices on the I2C bus for the setting of switches and multiplexers. The platform designers must validate this against the I2C device data sheets and any limits of the I2C controller or bus length.

The I2C host driver uses an index into a list or array of I2C bus configurations to keep the platform implementation hidden from the rest of the I2C stack. The protocol exposes BusConfigurationCount to enable the I2C host driver to perform bounds checking on the I2C bus configuration value supplied by the upper layers. The I2C bus layer also is told during the I2C device enumeration which I2C bus configuration is in use for each of the I2C devices. While this is hidden from the upper layers the I2C bus configuration is provided to the I2C host driver when performing I2C requests.

When the I2C bus configuration protocol is available, the I2C host driver calls EnableBusConfiguration to enable access to the necessary I2C bus configuration. This host driver may optimize calls to EnableBusConfiguration by only calling the routine only when the I2C bus configuration value changes between I2C requests.

When I2C operations are necessary on the same I2C bus to change I2C GPIO devices, multiplexers or switches, the I2C platform layer uses the I2C master protocol to perform the necessary I2C operations.

It is up to the I2C platform driver to choose the proper I2C bus configuration when ExitBootServices is called.

Definition at line 105 of file I2cBusConfigurationManagement.h.


IceLake Platform Sample Code: I2cMaster.h File Reference

  • Protocol
Classes | Typedefs
I2cMaster.h File Reference

I2C Master interface. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | EFI_I2C_REQUEST_PACKET
I2C device operation. More...
struct | _EFI_I2C_MASTER_PROTOCOL
I2C master mode protocol. More...

Typedefs

typedef struct _EFI_I2C_MASTER_PROTOCOL | EFI_I2C_MASTER_PROTOCOL
Declare the forward references. More...
typedef EFI_STATUS(* | EFI_I2C_MASTER_BUS_FREQUENCY_SET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN BusClockHertz)
Set the I2C controller bus clock frequency. More...
typedef VOID(* | EFI_I2C_MASTER_RESET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This)
Reset the I2C controller and configure it for use. More...
typedef EFI_STATUS(* | EFI_I2C_MASTER_START_REQUEST) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN SlaveAddress, IN EFI_EVENT Event OPTIONAL, IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, OUT EFI_STATUS *I2cStatus OPTIONAL)
Start an I2C operation on the host controller. More...

Detailed Description

I2C Master interface.

A driver or application uses the I2C master protocol to manage the master mode of an I2C controller. Note that access is restricted to the current configuration of the I2C bus.

I2C Driver Stack

The following is a representation of the I2C (I2C) driver stack and an I2C bus layout.

              +-----------------+
              |   Application   |
              +-----------------+
                       |
                       | Third Party or UEFI
                       |
                       V
 +--------+   +-----------------+
 | Slave  |   |   Third Party   |
 | Driver |   |   I2C Device    |
 |        |   |     Driver      |
 +--------+   +-----------------+
      |                |
      |          BUS   |
      |                |
      |                V
      |       +-----------------+
      |       | I2C Bus Driver  |------------------.
      |       +-----------------+                  |
      |                |                           |
      |         HOST   |          BUS              |
      |                |          CONFIGURATION    |
SLAVE |                V          MANAGEMENT       | ACPI
      |       +-----------------+                  |
      |       | I2C Host Driver |----------.       |
      |       +-----------------+          |       |
      |                |                   |       |
      |        MASTER  |                   V       V
      |                |               +-------=-------------+
      |                V               | I2C Platform Driver |
      |       +-----------------+      +---------------------+
      `------>| I2C Port Driver |               |      |
              +-----------------+               |      |
                       |                        |      |
            Software   |                        |      |
            --------------------------------------------------
            Hardware   |                        |      |
                       |                        |      |
                       V                        |      |
              +-----------------+               |      |
              | I2C Controller  |               |      |
              +-----------------+               |      |
                       |                        |      |
            -----------------------             |      |
            I2C Bus    |                        |      |
                       |    +------------+      |      |
                       +----| High speed |      |      |
                       |    | I2C device |      |      |
                       |    |    0x01    |      |      |
                       |    +------------+      |      |
                       |                        |      |
                  +---------+  0                |      |
                  | Switch  |<------------------`      |
                  +---------+  1                       |
                       |                               |
                       |    +------------+             |
                       +----| Fast speed |             |
                       |    | I2C device |             |
                       |    |    0x02    |             |
                       |    +------------+             |
                       |                               |
                +-------------+                        |
                | Multiplexer |<-----------------------`
                +-------------+
                 0 |       | 1
                   |       |
                   |       |
                   |       |    +-------------+
                   |       +----| Third Party |
                   |       |    | I2C Device  |
                   |       |    |  0x03, 0x04 |
                   |       |    +-------------+
                   |       |
                   |
                   |            +-------------+
                   +------------| Third Party |
                   |            | I2C Device  |
                   |            |  0x03, 0x04 |
                   |            +-------------+
                   |

The platform hardware designer chooses the bus layout based upon the platform, I2C chip and software requirements. The design uses switches to truncate the bus to enable higher speed operation for a subset of devices which are placed closer to the controller. When the switch is on, the extended bus must operate at a lower speed. The design uses multiplexer to create separate address spaces enabling the use of multiple devices which would otherwise have conflicting addresses. See the I2C Specification for more details.

N.B. Some operating systems may prohibit the changing of switches and multiplexers in the I2C bus. In this case the platform hardware and software designers must select a single I2C bus configuration consisting of constant input values for the switches and multiplexers. The platform software designer must then ensure that this I2C bus configuration is enabled prior to passing control to the operating system.

The platform hardware designer needs to provide the platform software designer the following data for each I2C bus:

  1. Which controller controls this bus

  2. A list of logic blocks contained in one or more I2C devices:

    a. I2C device which contains this logic block

    b. Logic block slave address

    c. Logic block name

  3. For each configuration of the switches and multiplexer

    a. What is the maximum speed of operation

    b. What devices are accessible

  4. The settings for the switches and multiplexers when control is given to the operating system.

Third Party I2C Drivers

This layer is I2C chip specific but platform and host controller independent.

Third party I2C driver writers, typically silicon vendors, need to provide:

  1. The device path node data that is used to select their driver.
  2. The order for the blocks of logic that get referenced by the entries in the slave address array.
  3. The hardware version of the I2C device, this value is passed to the third party I2C driver to enable it to perform work arounds for the specific hardware version. This value should match the value in the ACPI _HRV tag.

The third party I2C driver uses relative addressing to abstract the platform specific details of the I2C device. Using an example I2C device containing an accelerometer and a magnetometer which consumes two slave addresses, one for each logic block. The third party I2C driver writer may choose to write two drivers, one for each block of logic, in which case each driver refers to the single I2C slave address using the relative value of zero (0). However if the third party I2C driver writer chooses to write a single driver which consumes multiple slave addresses then the third party I2C driver writer needs to convey the order of the I2C slave address entries in the slave address array to the platform software designer. For the example:

0: Accelerometer

1: Magnetometer

The platform hardware designer picks the actual slave addresses from the I2C device's data sheet and provides this information to the platform software designer. The platform software designer then places the slave addresses into the slave address array in the order specified by the third party I2C driver writer. The third party driver I2C writer then indirectly references this array by specifying the index value as the relative slave address. The relative value always starts at zero (0) and its maximum value is the number of entries in slave address array minus one.

The slave address is specified as a 32-bit integer to allow room for future slave address expansion. Only the port driver knows the maximum slave address value. All other drivers and applications must look for the EFI_NOT_FOUND status for the indication that the maximum slave address was exceeded.

I2C Bus Driver

This layer is platform, host controller, and I2C chip independent.

The I2C bus driver creates a handle for each of the I2C devices described within the platform driver. The I2C controller's device path is extended with the device path node provided by the platform driver and attached to the handle. The third party I2C device driver uses the device path to determine if it may connect. For ACPI nodes, the third party I2C driver should use the CID or CidString value.

The I2C bus driver validates the relative address for the I2C device and then converts the relative value to an actual I2C slave address. The request is then passed to the I2C host driver.

I2C Host Driver

This layer is platform, host controller, and I2C chip independent.

N.B. For proper operation of the I2C bus, only the I2C bus driver and the I2C test application should connect to the I2C host driver via the EFI_I2C_HOST_DRIVER_PROTOCOL.

The I2C host driver may access any device on the I2C bus. The I2C host driver has the following responsibilities:

  1. Limits the number of requests to the I2C port driver to one. The I2C host driver holds on to additional requests until the I2C port driver is available to process the request. The I2C requests are issued in FIFO order to the I2C port driver.
  2. Enable the proper I2C bus configuration before starting the I2C request on the I2C port driver

I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress. I2C bus configuration zero (0) is the portion of the I2C bus that connects to the host controller. The bus configuration specifies the control values for the switches and multiplexers in the I2C bus. After the switches and multiplexers are properly configured, the I2C controller uses the slave address to access the requested I2C device.

Since the I2C driver stack supports asynchronous operations this layer maintains a queue of I2C requests until the I2C controller is available them. When a request reaches the head of the queue the necessary bus configuration is enabled and then the request is sent to the I2C port driver.

I2C Port Driver

This layer is I2C controller specific but platform independent.

This layer manipulates the I2C controller to perform an operation on the I2C bus. This layer does not configure the I2C bus so it is up to the caller to ensure that the I2C bus is in the proper configuration before issuing the I2C request.

This layer typically needs the following information:

  1. Host controller address
  2. Controller's input clock frequency

Depending upon the I2C controller, more data may be necessary. This layer may use any method to get these values: hard coded values, PCD values, or may choose to communicate with the platform layer using an undefined mechanism to get these values.

If the I2C port driver requires data from the platform driver then the I2C port driver writer needs to provide the platform interface details to the platform software designer.

I2C Platform Driver

When enabling access to I2C devices within UEFI, this driver installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device descriptions to the I2C bus driver using the EFI_I2C_DEVICE structure. These descriptions include the bus configuration number required for the I2C device, the slave address array and the device path.

The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional. This protocol needs to be specified under the following conditions:

  1. The I2C bus must operate at a frequency greater than 100 KHz
  2. The I2C bus contains switches or multiplexers.

The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the I2C host driver to call into the I2C platform driver to enable a specific I2C bus configuration and set its maximum clock speed.

The platform software designer collects the data requirements from third party I2C driver writers, the I2C controller driver writer, the EFI_I2C_ACPI_PROTOCOL and EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL. The platform software designer gets the necessary data from the platform hardware designer. The platform software designer then builds the data structures and implements the necessary routines to construct the I2C platform driver.

Switches and Multiplexers

There are some I2C switches and I2C multiplexers where the control is done via I2C commands. When the control inputs come via the same I2C bus that is being configured then the platform driver must use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform driver. While the I2C host driver makes the call to the I2C platform driver to configure the bus, the host driver keeps the I2C port driver idle, to allow the I2C platform driver preform the necessary configuration operations.

If however the configuration control is done via and I2C device connected to a different I2C bus (host controller), then it is possible for the platform software designer may choose between the following:

  1. Call into a third party I2C driver to manipulate the I2C bus control device.
  2. Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C driver exists for the I2C bus control device
  3. Call into the EFI_I2C_HOST_PROTOCOL if the platform does not expose the I2C bus control device.
Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file I2cMaster.h.

Typedef Documentation

typedef EFI_STATUS( * EFI_I2C_MASTER_BUS_FREQUENCY_SET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN BusClockHertz)

Set the I2C controller bus clock frequency.

This routine must be called at or below TPL_NOTIFY.

The software and controller do a best case effort of using the specified frequency for the I2C bus. If the frequency does not match exactly then the controller will use a slightly lower frequency to avoid exceeding the operating conditions for any of the I2C devices on the bus. For example if 400 KHz was specified and the controller's divide network only supports 402 KHz or 398 KHz then the controller would be set to 398 KHz. However if the desired frequency is 400 KHz and the controller only supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTED.

Parameters
[in] | This | Address of an EFI_I2C_MASTER_PROTOCOL structure
[in] | BusClockHertz | New I2C bus clock frequency in Hertz
Return values
EFI_SUCCESS | The bus frequency was set successfully.
EFI_UNSUPPORTED | The controller does not support this frequency.

Definition at line 415 of file I2cMaster.h.

typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL

Declare the forward references.

I2C master protocol

Definition at line 352 of file I2cMaster.h.

typedef VOID( * EFI_I2C_MASTER_RESET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This)

Reset the I2C controller and configure it for use.

This routine must be called at or below TPL_NOTIFY.

The I2C controller is reset and the I2C bus frequency is set to 100 KHz.

Parameters
[in] This Address of an EFI_I2C_MASTER_PROTOCOL structure

Definition at line 433 of file I2cMaster.h.

typedef EFI_STATUS( * EFI_I2C_MASTER_START_REQUEST) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN SlaveAddress, IN EFI_EVENT Event OPTIONAL, IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, OUT EFI_STATUS *I2cStatus OPTIONAL)

Start an I2C operation on the host controller.

This routine must be called at or below TPL_NOTIFY. For synchronous requests this routine must be called at or below TPL_CALLBACK.

This function initiates an I2C operation on the controller.

The operation is performed by selecting the I2C device with its slave address and then sending all write data to the I2C device. If read data is requested, a restart is sent followed by the slave address and then the read data is clocked into the I2C controller and placed in the read buffer. When the operation completes, the status value is returned and then the event is set.

N.B. The typical consumer of this API is the I2C host driver. Extreme care must be taken by other consumers of this API to prevent confusing the third party I2C drivers due to a state change at the I2C device which the third party I2C drivers did not initiate. I2C platform drivers may use this API within these guidelines.

N.B. This API supports only one operation, no queuing support exists at this layer. This API assumes that the I2C bus is in the correct configuration for the I2C request.

Parameters
[in] | This | Address of an EFI_I2C_MASTER_PROTOCOL structure
[in] | SlaveAddress | Address of the device on the I2C bus.
[in] | Event | Event to set for asynchronous operations, NULL for synchronous operations
[in] | RequestPacket | Address of an EFI_I2C_REQUEST_PACKET structure describing the I2C operation
[out] | I2cStatus | Optional buffer to receive the I2C operation completion status
Return values
EFI_SUCCESS | The operation completed successfully.
EFI_ABORTED | The request did not complete because the driver was shutdown.
EFI_BAD_BUFFER_SIZE | The WriteBytes or ReadBytes buffer size is too large.
EFI_DEVICE_ERROR | There was an I2C error (NACK) during the operation. This could indicate the slave device is not present.
EFI_INVALID_PARAMETER | RequestPacket is NULL
EFI_INVALID_PARAMETER | TPL is too high
EFI_NOT_FOUND | SlaveAddress exceeds maximum address
EFI_NOT_READY | I2C bus is busy or operation pending, wait for the event and then read status pointed to by the request packet.
EFI_NO_RESPONSE | The I2C device is not responding to the slave address. EFI_DEVICE_ERROR may also be returned if the controller cannot distinguish when the NACK occurred.
EFI_OUT_OF_RESOURCES | Insufficient memory for I2C operation
EFI_TIMEOUT | The transaction did not complete within an internally specified timeout period.

Definition at line 496 of file I2cMaster.h.


IceLake Platform Sample Code: I2cMmioConfigLib.h File Reference

  • Library
Variables
I2cMmioConfigLib.h File Reference

Memory mapped I/O specific configuration declarations. More...

#include <Protocol/MmioDevice.h>
Include dependency graph for I2cMmioConfigLib.h:

Go to the source code of this file.

Variables

CONST EFI_MMIO_DEVICE_PROTOCOL gMmioDeviceList []
Declare the memory mapped I/O devices assocaited with the board.

Detailed Description

Memory mapped I/O specific configuration declarations.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file I2cMmioConfigLib.h.


IceLake Platform Sample Code: IccOverClocking.h File Reference

  • Protocol
IccOverClocking.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file IccOverClocking.h.


IceLake Platform Sample Code: IccSetupData.h File Reference

IccSetupData.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file IccSetupData.h.


IceLake Platform Sample Code: Madt.h File Reference

  • Acpi
  • AcpiTables
  • Madt
Madt.h File Reference

This file describes the contents of the ACPI Multiple APIC Description Table (MADT). More...

#include <IndustryStandard/Acpi.h>
Include dependency graph for Madt.h:

Go to the source code of this file.

Detailed Description

This file describes the contents of the ACPI Multiple APIC Description Table (MADT).

To make changes to the MADT, it is necessary to update the count for the APIC structure being updated, and to modify table found in Madt.c.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Madt.h.


IceLake Platform Sample Code: Mcfg.h File Reference

  • Acpi
  • AcpiTables
  • Mcfg
Mcfg.h File Reference

This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG). More...

#include <IndustryStandard/Acpi30.h>
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
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Detailed Description

This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG).

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Mcfg.h.


IceLake Platform Sample Code: me_status.h File Reference

  • Library
Macros
me_status.h File Reference

Go to the source code of this file.

Macros

#define STATUS_SUCCESS 0x0
The operation completed successfully.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2005 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file me_status.h.


IceLake Platform Sample Code: MePolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
MePolicyInitDxe.c File Reference

This file is SampleCode for Intel ME DXE Policy initialization. More...

#include "MePolicyInitDxe.h"
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Functions

EFI_STATUS MePolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy. More...

Detailed Description

This file is SampleCode for Intel ME DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file MePolicyInitDxe.c.

Function Documentation

EFI_STATUS MePolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize ME DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file MePolicyInitDxe.c.

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IceLake Platform Sample Code: MePolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
MePolicyInitDxe.h File Reference

Header file for the MePolicyInitDxe Driver. More...

#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <PchAccess.h>
#include <Protocol/MePolicy.h>
#include <Library/DxeMePolicyLib.h>
#include <Library/DxePolicyBoardConfigLib.h>
#include <Library/DxeMePolicyUpdateLib.h>
Include dependency graph for MePolicyInitDxe.h:
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Functions

EFI_STATUS | MePolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy. More...
VOID | HeciPlatformDebugCapabilityMsgCallback (IN EFI_EVENT Event, IN VOID *Context)
Checkes the HECI protocol and send MEI message. More...

Detailed Description

Header file for the MePolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file MePolicyInitDxe.h.

Function Documentation

VOID HeciPlatformDebugCapabilityMsgCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Checkes the HECI protocol and send MEI message.

Parameters
[in] | Event | Event objext
[in] | *Context | VOID Pointer
EFI_STATUS MePolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize ME DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file MePolicyInitDxe.c.

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IceLake Platform Sample Code: mkhi_hdrs.h File Reference

  • Library
mkhi_hdrs.h File Reference
#include "cse_basic_types.h"
#include "typedef.h"
Include dependency graph for mkhi_hdrs.h:
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file mkhi_hdrs.h.


IceLake Platform Sample Code: Mmc.h File Reference

  • IndustryStandard
Mmc.h File Reference

Header file for Industry MMC 4.2 spec. More...

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Detailed Description

Header file for Industry MMC 4.2 spec.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Mmc.h.


IceLake Platform Sample Code: MofSampleDev.h Source File

  • Acpi
  • AcpiTables
  • Dsdt
MofSampleDev.h
1 0x46,0x4F,0x4D,0x42,0x01,0x00,0x00,0x00,0x2D,0x04,0x00,0x00,0xB4,0x0F,0x00,0x00,
2 0x44,0x53,0x00,0x01,0x1A,0x7D,0xDA,0x54,0x28,0xCE,0x87,0x00,0x01,0x06,0x18,0x42,
3 0x10,0x07,0x10,0x22,0x21,0x04,0x12,0x01,0xA1,0xC8,0x2C,0x0C,0x86,0x10,0x38,0x2E,
4 0x24,0x15,0x07,0x85,0x12,0x02,0xA1,0xFE,0x04,0xF2,0x2B,0x00,0xA1,0x43,0x01,0x32,
5 0x05,0x18,0x14,0xE0,0x14,0x41,0x04,0xBD,0x0A,0xB0,0x29,0xC0,0xA4,0x00,0x8B,0x02,
6 0xB4,0x0B,0xB0,0x2C,0x40,0xB7,0x00,0xE9,0xB0,0x44,0x24,0x38,0x4A,0x0C,0x38,0x4A,
7 0x27,0xB6,0x70,0xC3,0x06,0x2F,0x14,0x45,0x33,0x88,0x92,0xA0,0x72,0x01,0xBE,0x11,
8 0x04,0x5E,0xAE,0x00,0xC9,0x13,0x90,0x66,0x01,0x86,0x05,0x58,0x17,0x20,0x7B,0x08,
9 0x54,0xEA,0x10,0x50,0x72,0x86,0x80,0x1A,0x40,0xAB,0x13,0x10,0x7E,0xA5,0x53,0x42,
10 0x12,0x84,0x33,0x56,0xF1,0xF8,0x9A,0x45,0xD3,0x73,0x92,0x73,0x0C,0x39,0x1E,0x17,
11 0x7A,0x10,0x3C,0x84,0x04,0x10,0x26,0x7B,0xC8,0x92,0x0D,0x83,0xD2,0x30,0x16,0xEA,
12 0x62,0xD4,0xA8,0x91,0xB2,0x01,0x19,0xA2,0x24,0x38,0xD4,0xA8,0x3D,0xBB,0xE6,0xC7,
13 0xA1,0xD9,0xB5,0x3D,0x16,0x02,0xC9,0xA4,0x0D,0x05,0x25,0x05,0x42,0xC2,0x67,0x4A,
14 0x66,0x14,0xF1,0x48,0x0D,0x93,0xC0,0xA3,0x88,0xEC,0x19,0x46,0x63,0xD0,0xD8,0x61,
15 0x78,0x98,0xC1,0x0E,0xE2,0x30,0x8E,0x39,0x72,0x02,0x4F,0xE8,0x48,0x8F,0xBC,0xB0,
16 0x79,0x0A,0x35,0x46,0x73,0x50,0x04,0xFF,0x51,0x00,0x2B,0x11,0x56,0xA3,0x8D,0x7D,
17 0xBE,0x1E,0xCD,0xC1,0xC6,0x38,0x82,0xE3,0x4A,0xF0,0xFF,0x0F,0x13,0xA4,0xF7,0xE9,
18 0x10,0x41,0x78,0x12,0x3D,0x0B,0x61,0xF5,0x0C,0x24,0x9C,0x10,0xC7,0xCD,0x61,0x0E,
19 0x58,0x83,0x40,0xC9,0x80,0x10,0xE4,0x33,0xC1,0xD1,0x99,0xC0,0xEE,0x8F,0x02,0xD2,
20 0x26,0x40,0xE3,0x1D,0x40,0x20,0x9D,0x21,0x08,0xA4,0xAD,0xC1,0x08,0xA6,0x42,0x28,
21 0xA1,0x1C,0x55,0x38,0x5B,0x43,0x11,0x90,0x6F,0x05,0xAF,0x0F,0xA1,0xD8,0xD4,0x42,
22 0x1E,0x5B,0x90,0xC6,0xC0,0x84,0x1C,0x2C,0x4C,0xBC,0xF6,0x17,0xC2,0x1E,0x12,0x3A,
23 0x0B,0x38,0xD2,0x68,0x50,0x07,0x05,0x9F,0x07,0x7C,0x16,0x78,0x3E,0xF0,0xA8,0x0E,
24 0xCD,0x83,0x3B,0xB0,0xC7,0x87,0x07,0x01,0x0F,0x99,0xDD,0x10,0x7C,0xAE,0xF0,0xC9,
25 0x00,0xEF,0x1A,0x50,0x57,0x82,0x07,0x02,0x36,0x46,0xC3,0xF1,0x21,0x7A,0xB8,0xE1,
26 0x4E,0xE0,0x10,0x19,0xA0,0x67,0xF5,0x2C,0x80,0x1D,0xD6,0xC9,0x3C,0x08,0xBC,0x4B,
27 0x34,0x7B,0x8B,0x20,0x04,0xC7,0xE3,0x0B,0x04,0x9B,0x70,0x02,0xCB,0x1F,0x04,0x6A,
28 0x64,0x86,0xF6,0x74,0x4F,0xEB,0x45,0xC0,0x07,0x00,0x13,0x58,0x2C,0x84,0x14,0x40,
29 0x68,0x3C,0xE0,0x57,0x7C,0xE8,0x20,0xB7,0x05,0xCF,0xD7,0x47,0x13,0xE6,0x64,0x3C,
30 0xA8,0x51,0xF8,0x14,0x10,0xEE,0xBC,0x4D,0xE0,0xC0,0x10,0xFA,0x5F,0x58,0xD4,0x31,
31 0x85,0x9F,0x26,0xE8,0x41,0x82,0xA1,0xB2,0xFF,0x3F,0xC4,0x91,0x9C,0x90,0x3F,0x2B,
32 0x1E,0x18,0x7C,0xC1,0xA7,0x08,0x20,0x03,0x83,0xBB,0x42,0xB0,0x01,0xC3,0xBF,0x4C,
33 0x18,0xD8,0x17,0x89,0xCA,0x20,0xC9,0x91,0xE3,0x89,0x06,0x0C,0xE8,0x7D,0x0E,0x56,
34 0x87,0x16,0x83,0xF9,0x3E,0x13,0xEC,0xE5,0xA1,0x47,0x20,0xDD,0x59,0xAC,0x15,0x42,
35 0x38,0xAF,0x30,0x3E,0xD6,0x00,0x93,0x51,0x3F,0xD6,0x80,0xED,0xE4,0x03,0x67,0x00,
36 0x3C,0x8E,0x09,0x10,0x26,0xFA,0x5D,0x20,0x29,0x0F,0x04,0x0A,0xE3,0x23,0x0D,0x70,
37 0xF9,0xFF,0x1F,0x69,0x80,0xDF,0xC9,0x00,0x77,0x7A,0x00,0xCF,0x84,0x5E,0x2B,0xD8,
38 0xFD,0xC1,0xE3,0x08,0x12,0x38,0xC2,0x13,0x11,0x39,0xD1,0x40,0x3E,0x35,0x3C,0xC2,
39 0x3C,0x07,0x9C,0xCE,0xE1,0x1C,0xC9,0x43,0xC0,0xEB,0x8C,0xBD,0x21,0xE9,0x1E,0xF3,
40 0x3A,0x63,0xAC,0x40,0x27,0x15,0xC5,0xF7,0x99,0x50,0x11,0xA2,0x45,0x09,0x19,0xE1,
41 0x15,0x22,0xA4,0x91,0xA3,0x45,0x8C,0x12,0x3F,0x64,0x9C,0x27,0x1A,0x16,0xEB,0x28,
42 0xA0,0xF3,0x87,0x4F,0x34,0x80,0xDF,0xFF,0xFF,0x89,0x06,0xFC,0xF2,0x4E,0x24,0xA0,
43 0x3B,0x36,0x79,0x0E,0x21,0x9E,0x46,0x80,0x8B,0xF4,0x47,0x87,0x4E,0x75,0x64,0xA1,
44 0xB2,0xB1,0x50,0x0F,0x82,0x0A,0x3F,0x21,0xE8,0xAC,0x12,0x37,0xE6,0xAB,0xCA,0x6B,
45 0x84,0x4F,0x6B,0xBE,0x4B,0xB0,0x41,0x0B,0x4E,0xA7,0x3D,0x2E,0x93,0x42,0x22,0x21,
46 0x34,0x20,0xC3,0x59,0x16,0x1C,0x05,0xF1,0xE8,0x7D,0xE2,0xF3,0x51,0x08,0x6E,0xC4,
47 0xA3,0x10,0x3D,0x2D,0xE0,0xC7,0x72,0x64,0x27,0xE6,0x59,0xF8,0x70,0x87,0x3B,0x72,
48 0xC0,0x1D,0x1C,0x5B,0xE1,0xF1,0xFB,0x02,0x10,0xE4,0x7C,0x83,0x9D,0xAC,0x51,0x5E,
49 0x11,0x3C,0x42,0xEC,0x60,0x7C,0x4C,0xE2,0xE3,0xF0,0xD5,0xE0,0x7D,0xC6,0x04,0xEC,
50 0x0C,0x04,0x9E,0xFF,0xFF,0x19,0x88,0x0B,0x3C,0x22,0x80,0x02,0xC8,0x97,0x02,0x1F,
51 0x11,0x1E,0x0C,0xD8,0x1C,0x9E,0x12,0x7C,0xC4,0x61,0xF0,0x3C,0xDA,0xA8,0xA8,0xAC,
52 0x71,0xA1,0x06,0xEB,0x33,0x0C,0xC3,0x3E,0x4F,0x5F,0x9A,0x8E,0xD2,0xC7,0x29,0x0C,
53 0xAC,0x87,0xCF,0x61,0x8D,0x16,0xF6,0xA8,0x9F,0x24,0x7C,0x0B,0xF1,0xCC,0x8C,0x11,
54 0xD6,0x47,0x00,0x20,0x76,0x7C,0x40,0x9D,0x79,0x7C,0x6E,0xF0,0x88,0x22,0x9E,0xE7,
55 0xDB,0x8F,0x2F,0x1B,0xA7,0xE4,0x01,0x59,0xE2,0xE9,0x01,0x25,0x8E,0x42,0xD2,0x4E,
56 0x0F,0x28,0x31,0x70,0x14,0xC4,0xA7,0x07,0x07,0x3D,0x3D,0x40,0x0F,0x76,0x7A,0x00,
57 0xC5,0xA9,0x00,0x37,0x56,0xB8,0x63,0xF3,0x21,0xCC,0x73,0xC3,0x1E,0x1C,0xC0,0xF2,
58 0xFF,0x3F,0x38,0x00,0xDF,0xE1,0xFA,0xE0,0x00,0xAE,0x33,0x80,0x0F,0x0E,0xE0,0x3A,
59 0x6E,0x82,0x67,0xF4,0xEC,0x08,0xF3,0x88,0x63,0xAC,0x73,0x7D,0xE4,0xF1,0x09,0x00,
60 0x8E,0x98,0x73,0x03,0x6A,0xB8,0x96,0x7B,0x8A,0x41,0xDC,0x11,0x30,0x07,0x18,0x1F,
61 0x1B,0xB8,0x40,0x0A,0xC9,0x3B,0x36,0xA0,0x04,0xC1,0x51,0x10,0x8F,0xD1,0x61,0x8F,
62 0x0D,0xD0,0xC3,0x1D,0x1B,0x40,0x71,0xFC,0xC1,0x9F,0x38,0xE0,0x9F,0xC3,0xE0,0x1C,
63 0x1C,0xF8,0xFF,0xFF,0xE0,0x00,0xF8,0x08,0x75,0x70,0x00,0x1D,0x2C,0x3F,0x38,0x80,
64 0x67,0xFC,0xC0,0x43,0xA1,0x4D,0x9F,0x1A,0x8D,0x5A,0x35,0x28,0x53,0xA3,0x4C,0x83,
65 0x5A,0x7D,0x2A,0x35,0x66,0xCC,0xC6,0x91,0x01,0x25,0x64,0x55,0x1A,0x96,0x63,0x80,
66 0xF0,0x47,0x82,0x40,0x1C,0xD5,0x02,0x20,0x8B,0xE2,0x01,0x88,0x09,0x59,0x92,0x40,
67 0x1C,0xEF,0xA8,0x28,0x23,0xE7,0x06,0x83,0x08,0xC8,0x71,0xD7,0x28,0x20,0x87,0x07,
68 0x11,0x90,0xE3,0xAF,0x43,0x40,0x16,0xA3,0x03,0x88,0xFD,0xFF,0x01
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: MofTestDev.h Source File

  • Acpi
  • AcpiTables
  • Dsdt
MofTestDev.h
1 0x46,0x4F,0x4D,0x42,0x01,0x00,0x00,0x00,0xE1,0x02,0x00,0x00,0xC2,0x06,0x00,0x00,
2 0x44,0x53,0x00,0x01,0x1A,0x7D,0xDA,0x54,0xA8,0x5D,0x83,0x00,0x01,0x06,0x18,0x42,
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18 0x5D,0x9D,0xE7,0x00,0x32,0x62,0x86,0x95,0xE0,0xD7,0xC0,0x07,0x03,0xBC,0x6B,0x40,
19 0xDD,0x08,0x9E,0x07,0xD8,0x30,0xC3,0x61,0x86,0xE8,0xD1,0x86,0xFB,0xFF,0x9F,0xC0,
20 0x21,0x32,0x40,0x0F,0xED,0x51,0x00,0xEB,0x70,0x32,0x3A,0x07,0x94,0x2A,0xC0,0xEC,
21 0x99,0x40,0x33,0x4B,0x70,0x3C,0x3E,0x00,0x78,0x3E,0x27,0x9C,0xC0,0xF2,0x07,0x81,
22 0x1A,0x99,0xA1,0x3D,0xE3,0xD3,0x7A,0x0F,0xF0,0xF1,0xE0,0xB0,0x98,0x58,0x08,0x29,
23 0x80,0xD0,0x78,0xC0,0xAF,0xF8,0x68,0x20,0x84,0x97,0x05,0xCF,0xD7,0x87,0x04,0x03,
24 0x63,0x07,0x64,0xBF,0x02,0x10,0x82,0xBF,0x2E,0x1C,0xD1,0x43,0x43,0x84,0x04,0x2F,
25 0x03,0x47,0x50,0x29,0xBE,0xB0,0x0E,0x21,0x46,0xA4,0x18,0x51,0x82,0xD4,0x0A,0xA1,
26 0xE9,0x87,0x49,0x50,0xE4,0xC9,0x01,0x3D,0x02,0x8E,0x77,0x02,0xC7,0x13,0xD9,0xE3,
27 0x89,0x72,0x12,0x07,0xE4,0x33,0x85,0x11,0x4E,0xF3,0x51,0xE2,0xD1,0xC2,0x9A,0x67,
28 0xA4,0x13,0xC3,0x39,0xBD,0x0D,0x98,0xA0,0xB2,0xE7,0x80,0x8E,0x1F,0x56,0x05,0x22,
29 0x1B,0x4B,0xF5,0x39,0x83,0x6A,0x5E,0xAE,0x46,0x74,0xCC,0xC7,0xEA,0x11,0x9C,0xB4,
30 0xA7,0x17,0xD9,0x4A,0xC1,0x04,0xEC,0x61,0x5B,0x23,0x85,0xD4,0xD0,0x68,0x3C,0x06,
31 0x77,0xFE,0x13,0x09,0x05,0x31,0xA0,0xC3,0x41,0xC8,0xC9,0x49,0x00,0xA5,0x62,0xBC,
32 0xE4,0x68,0xC1,0x08,0xA6,0x81,0xD0,0xDD,0xC1,0xF3,0xF3,0x3D,0x80,0xDF,0x4C,0x7C,
33 0x32,0x30,0xB0,0xEF,0x13,0x6F,0x1C,0xF0,0xFF,0xFF,0x37,0x0E,0x36,0x09,0x8C,0x9A,
34 0x23,0x04,0x9D,0x02,0xBF,0x00,0xBC,0x0A,0x98,0xC0,0xBA,0x2E,0x06,0xD0,0x4F,0x1D,
35 0x1E,0xA8,0xAF,0x1C,0x67,0x63,0x7D,0x07,0x03,0x50,0x00,0xF9,0x22,0xE0,0x93,0xC1,
36 0xC3,0x00,0xBB,0x19,0x18,0x26,0x9A,0xD1,0xB9,0xA8,0x69,0xA3,0x64,0xC0,0x68,0xDA,
37 0x06,0xF1,0xB4,0x1D,0x71,0xDA,0x68,0x68,0x5F,0x05,0x7C,0x11,0x70,0xA8,0x61,0xD3,
38 0x3B,0x07,0x7E,0xAE,0x67,0x16,0xD0,0x93,0xF0,0x91,0xE4,0xB8,0xC1,0x32,0x0A,0x06,
39 0x1E,0x24,0x8E,0x47,0xC1,0x26,0xCE,0x07,0xE0,0x89,0xF3,0x71,0xF9,0x86,0x01,0x7F,
40 0xE4,0x58,0x82,0x02,0x67,0x0E,0x72,0x78,0x4C,0xB0,0x51,0x51,0x59,0xE3,0x42,0x8D,
41 0xD2,0x57,0x20,0x86,0x7D,0x82,0x16,0x3D,0x48,0x9D,0x2F,0x0E,0xEA,0x69,0xC4,0x63,
42 0x33,0xAC,0xC7,0xFD,0xFF,0x0F,0x8B,0x41,0x0B,0x7B,0xB8,0x2F,0x22,0x3E,0xC5,0x78,
43 0x66,0xC6,0x08,0xEB,0xB1,0x7B,0x40,0x8F,0x10,0xE0,0x01,0x7B,0x35,0x39,0xD3,0x07,
44 0x97,0x3F,0x8E,0xEA,0x20,0x74,0xDF,0xE0,0x28,0x21,0x1E,0x38,0x30,0x04,0x15,0xDA,
45 0xF4,0xA9,0xD1,0xA8,0x55,0x83,0x32,0x35,0xCA,0x34,0xA8,0xD5,0xA7,0x52,0x63,0xC6,
46 0x3C,0x5C,0x8E,0xE8,0x41,0x81,0xBC,0x13,0x34,0x42,0x87,0x00,0xA1,0x42,0x9E,0x08,
47 0x32,0x72,0x0F,0x31,0x88,0x80,0xAC,0xCC,0x02,0x10,0xD3,0x09,0x22,0x20,0xFF,0xFF,
48 0x01
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: MultiPlatSupport.h File Reference

Classes | Macros | Enumerations
MultiPlatSupport.h File Reference

Go to the source code of this file.

Classes

struct | VARIABLE_STORE_HEADER
Variable Store region header. More...
struct | VARIABLE_HEADER
Single Variable Data Header Structure. More...
struct | AUTHENTICATED_VARIABLE_HEADER
Single Variable Data Header Structure for Auth variable. More...

Macros

#define | ALIGNMENT 1
Alignment of variable name and data, according to the architecture: More...
#define | HEADER_ALIGNMENT 4
Alignment of Variable Data Header in Variable Store region.
#define | VARIABLE_STORE_FORMATTED 0x5a
Variable Store Header Format and State.
#define | VARIABLE_DATA 0x55AA
Variable data start flag.
#define | VAR_IN_DELETED_TRANSITION 0xfe
Variable State flags. More...
#define | VAR_DELETED 0xfd
Variable is obsolete.
#define | VAR_HEADER_VALID_ONLY 0x7f
Variable header has been valid.
#define | VAR_ADDED 0x3f
Variable has been completely added.

Enumerations

enum VARIABLE_STORE_STATUS
Status of Variable Store Region.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file MultiPlatSupport.h.

Macro Definition Documentation

#define ALIGNMENT 1

Alignment of variable name and data, according to the architecture:

  • For IA-32 and Intel(R) 64 architectures: 1.
  • For IA-64 architecture: 8.

Definition at line 45 of file MultiPlatSupport.h.

#define VAR_IN_DELETED_TRANSITION 0xfe

Variable State flags.

Variable is in obsolete transition.

Definition at line 114 of file MultiPlatSupport.h.


IceLake Platform Sample Code: MultiPlatSupportLib.h File Reference

  • Library
Functions
MultiPlatSupportLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | GetVariableFromHob (IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, OUT UINT32 *Attributes, OPTIONAL IN OUT UINTN *DataSize, OUT VOID *Data)
Get variable from default variable HOB. More...
EFI_STATUS | SetVariableToHob (IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, IN UINT32 *Attributes, OPTIONAL IN UINTN DataSize, IN VOID *Data)
Set variable to default variable HOB. More...
EFI_STATUS | CreateDefaultVariableHob (IN UINT16 DefaultId)
This function finds the matched default data and create GUID hob for it. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file MultiPlatSupportLib.h.

Function Documentation

EFI_STATUS CreateDefaultVariableHob ( IN UINT16 DefaultId )

This function finds the matched default data and create GUID hob for it.

Parameters
[in] DefaultId - Specifies the type of defaults to retrieve.
Returns
EFI_SUCCESS - The matched default data is found.
EFI_NOT_FOUND - The matched default data is not found.
EFI_OUT_OF_RESOURCES - No enough resource to create HOB.
EFI_STATUS GetVariableFromHob | ( | IN CHAR16 * | VariableName,
 |  | IN EFI_GUID * | VendorGuid,
 |  | OUT UINT32 * | Attributes,
 |  | OPTIONAL IN OUT UINTN * | DataSize,
 |  | OUT VOID * | Data
 | ) |  |

Get variable from default variable HOB.

Parameters
[in] | VariableName | A Null-terminated string that is the name of the vendor's variable.
[in] | VendorGuid | A unique identifier for the vendor.
[out] | Attributes | If not NULL, a pointer to the memory location to return the attributes bitmask for the variable.
[in,out] | DataSize | On input, the size in bytes of the return Data buffer. On output the size of data returned in Data.
[out] | Data | The buffer to return the contents of the variable.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The variable was not found.
EFI_BUFFER_TOO_SMALL | The DataSize is too small for the result.
EFI_INVALID_PARAMETER | VariableName is NULL.
EFI_INVALID_PARAMETER | VendorGuid is NULL.
EFI_INVALID_PARAMETER | DataSize is NULL.
EFI_INVALID_PARAMETER | The DataSize is not too small and Data is NULL.
EFI_STATUS SetVariableToHob | ( | IN CHAR16 * | VariableName,
 |  | IN EFI_GUID * | VendorGuid,
 |  | IN UINT32 * | Attributes,
 |  | OPTIONAL IN UINTN | DataSize,
 |  | IN VOID * | Data
 | ) |  |

Set variable to default variable HOB.

Parameters
[in] | VariableName | A Null-terminated string that is the name of the vendor's variable.
[in] | VendorGuid | A unique identifier for the vendor.
[in] | Attributes | If not NULL, a pointer to the memory location to set the attributes bitmask for the variable.
[in] | DataSize | On input, the size in bytes of the return Data buffer. On output the size of data returned in Data.
[in] | Data | The buffer to return the contents of the variable.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The variable was not found.
EFI_INVALID_PARAMETER | VariableName is NULL.
EFI_INVALID_PARAMETER | VendorGuid is NULL.
EFI_INVALID_PARAMETER | Attributes is not NULL, but attributes value is 0.
EFI_INVALID_PARAMETER | DataSize is not equal to the variable data size.
EFI_INVALID_PARAMETER | The DataSize is equal to the variable data size, but Data is NULL.


IceLake Platform Sample Code: OcSetupVariable.h File Reference

OcSetupVariable.h File Reference

Variable definition for overclocking support. More...

Go to the source code of this file.

Detailed Description

Variable definition for overclocking support.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file OcSetupVariable.h.


IceLake Platform Sample Code: OemSetup.h File Reference

OemSetup.h File Reference

OEM Specific Setup Variables and Structures. More...

#include <PchLimits.h>
Include dependency graph for OemSetup.h:
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Detailed Description

OEM Specific Setup Variables and Structures.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file OemSetup.h.


IceLake Platform Sample Code: OverClockPpi.h File Reference

  • Ppi
OverClockPpi.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file OverClockPpi.h.


IceLake Platform Sample Code: PcdInitDxe.c File Reference

  • PlatformInit
  • PcdInitDxe
PcdInitDxe.c File Reference

Driver for initializing platform dynamic PCDs. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/PchInfoLib.h>
#include <Library/SataLib.h>
#include <SetupVariable.h>
#include <BootTime.h>
Include dependency graph for PcdInitDxe.c:

Go to the source code of this file.

Detailed Description

Driver for initializing platform dynamic PCDs.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PcdInitDxe.c.


IceLake Platform Sample Code: PchPolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
PchPolicyInitDxe.c File Reference

This file is SampleCode for PCH DXE Policy initialization. More...

#include "PchPolicyInitDxe.h"
Include dependency graph for PchPolicyInitDxe.c:

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Functions

EFI_STATUS PchPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize PCH DXE Policy. More...

Detailed Description

This file is SampleCode for PCH DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PchPolicyInitDxe.c.

Function Documentation

EFI_STATUS PchPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize PCH DXE Policy.

PCH DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 51 of file PchPolicyInitDxe.c.

Here is the call graph for this function:


IceLake Platform Sample Code: PchPolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
PchPolicyInitDxe.h File Reference

Header file for the PchPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/PchPolicy.h>
#include <Library/DxePchPolicyLib.h>
#include <Library/DxePchPolicyUpdateLib.h>
Include dependency graph for PchPolicyInitDxe.h:
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Functions

EFI_STATUS PchPolicyInitDxe (IN EFI_HANDLE ImageHandle)
PCH DXE Policy Driver Entry Point
More...

Detailed Description

Header file for the PchPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PchPolicyInitDxe.h.

Function Documentation

EFI_STATUS PchPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

PCH DXE Policy Driver Entry Point

  • Introduction
    Pch DXE drivers behavior can be controlled by platform policy without modifying reference code directly. Platform policy Protocol is initialized with default settings in this funciton. This policy Protocol has to be initialized prior to PCH initialization DXE drivers execution.
  • Precondition
    • Runtime variable service should be ready if policy initialization required.
  • Returns
    PCH_POLICY_PROTOCOL will be installed successfully and ready for Pch reference code use.
  • Porting Recommendations
    Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
Parameters
[in] ImageHandle - Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

PCH DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 51 of file PchPolicyInitDxe.c.

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IceLake Platform Sample Code: PdtUpdateLib.h File Reference

  • Library
Functions
PdtUpdateLib.h File Reference
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/UefiLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DxeMeLib.h>
Include dependency graph for PdtUpdateLib.h:

Go to the source code of this file.

Functions

EFI_STATUS PdtUpdate (IN UINT32 PlatformId, IN UINT8 *FileBuffer, IN UINT32 MultiPdtSize)
API to Update new PDT file by sending it to ME. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PdtUpdateLib.h.

Function Documentation

EFI_STATUS PdtUpdate | ( | IN UINT32 | PlatformId,
 |  | IN UINT8 * | FileBuffer,
 |  | IN UINT32 | MultiPdtSize
 | ) |  |

API to Update new PDT file by sending it to ME.

Parameters
[in] | PlatformId | Platform ID to be matched to in MultiPDT package
[in] | FileBuffer | The pointer to MultiPdt file
[in] | MultiPdtSize | MultiPDT file size
Return values
EFI_SUCCESS Bios2Ish file send complete.


IceLake Platform Sample Code: PeiBootGuardEventLogLib.h File Reference

  • Library
Functions
PeiBootGuardEventLogLib.h File Reference

This file contains functions for creating TPM Event Log. More...

Go to the source code of this file.

Functions

EFI_STATUS CreateBootguardEventLogEntries (IN BOOT_GUARD_INFO *BootGuardInfo)
Create various events in the event log as required for Bootguard Enabled Boot. More...

Detailed Description

This file contains functions for creating TPM Event Log.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PeiBootGuardEventLogLib.h.

Function Documentation

EFI_STATUS CreateBootguardEventLogEntries ( IN BOOT_GUARD_INFO * BootGuardInfo )

Create various events in the event log as required for Bootguard Enabled Boot.

Return values
EFI_SUCCES | Events created successfully
Others | Bootguard not supported


IceLake Platform Sample Code: PeiCpuPolicyDebugLib.h File Reference

  • Library
Functions
PeiCpuPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel CPU PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS | UpdatePeiCpuPolicyDebugPreMem (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs CPU PEI Debug Policy initialization. More...
EFI_STATUS | UpdatePeiCpuPolicyDebug (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs CPU PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel CPU PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiCpuPolicyDebugLib.h.

Function Documentation

EFI_STATUS UpdatePeiCpuPolicyDebug ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs CPU PEI Debug Policy initialization.

Parameters
[in] SiPolicyPpi The SI Policy PPI instance
Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.
EFI_STATUS UpdatePeiCpuPolicyDebugPreMem ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

This function performs CPU PEI Debug Policy initialization.

Parameters
[in] SiPreMemPolicyPpi The SI PreMem Policy PPI instance
Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


IceLake Platform Sample Code: PeiDxeBoardIdsLib.h File Reference

  • Library
PeiDxeBoardIdsLib.h File Reference

Header file for Board Information boot time changes. More...

Go to the source code of this file.

Detailed Description

Header file for Board Information boot time changes.

Revision Reference:
SMBIOS Specification version 2.8.0 from DMTF: http://www.dmtf.org/standards/smbios Intel Framework Specifications, all available at: http://www.intel.com/technology/framework/spec.htm
  • SMBUS Host Controller Protocol Specification Unified Extensible Firmware Interface (UEFI) Specifications: http://www.uefi.org/specs/
Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiDxeBoardIdsLib.h.


IceLake Platform Sample Code: PeiPchPolicyDebugLib.h File Reference

  • Library
Functions
PeiPchPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel PCH PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS | UpdatePeiPchPolicyDebug (IN OUT SI_POLICY_PPI *SiPolicy)
This function performs PCH PEI Debug Policy initialization. More...
EFI_STATUS | UpdatePeiPchPolicyDebugPreMem (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy)
This function performs PCH PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel PCH PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPchPolicyDebugLib.h.

Function Documentation

EFI_STATUS UpdatePeiPchPolicyDebug ( IN OUT SI_POLICY_PPI * SiPolicy )

This function performs PCH PEI Debug Policy initialization.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.
EFI_STATUS UpdatePeiPchPolicyDebugPreMem ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicy )

This function performs PCH PEI Debug Policy initialization.

Parameters
[in] PchPreMemPolicy The PCH PreMem Policy PPI instance
Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


IceLake Platform Sample Code: PeiPlatformLib.h File Reference

  • Library
PeiPlatformLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPlatformLib.h.


IceLake Platform Sample Code: PeiPlatformRecoveryLib.h File Reference

  • Library
Functions
PeiPlatformRecoveryLib.h File Reference

This library provides platform recovery module. More...

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Functions

EFI_STATUS InitializeRecovery (VOID)
Provide the functionality of the recovery module. More...

Detailed Description

This library provides platform recovery module.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPlatformRecoveryLib.h.

Function Documentation

EFI_STATUS InitializeRecovery ( VOID )

Provide the functionality of the recovery module.

Return values
EFI_SUCCESS The function completed successfully.


IceLake Platform Sample Code: PeiPolicyBoardConfigLib.h File Reference

  • Library
Functions
PeiPolicyBoardConfigLib.h File Reference

Header file for the PeiPolicyBoardConfig Library. More...

#include <Ppi/SiPolicy.h>
Include dependency graph for PeiPolicyBoardConfigLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | UpdatePeiCpuPolicyBoardConfigPreMem (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI CPU Pre-Memory Policy update by board configuration. More...
EFI_STATUS | UpdatePeiMePolicyBoardConfigPreMem (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI ME Pre-Memory Policy update by board configuration. More...
EFI_STATUS | UpdatePeiPchPolicyBoardConfigPreMem (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI PCH Pre-Memory Policy update by board configuration. More...
EFI_STATUS | UpdatePeiSaPolicyBoardConfigPreMem (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI SA Pre-Memory Policy update by board configuration. More...
EFI_STATUS | UpdatePeiAmtPolicyBoardConfig (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI AMT Policy update by board configuration. More...
EFI_STATUS | UpdatePeiCpuPolicyBoardConfig (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI CPU Policy update by board configuration. More...
EFI_STATUS | UpdatePeiMePolicyBoardConfig (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI ME Policy update by board configuration. More...
EFI_STATUS | UpdatePeiPchPolicyBoardConfig (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI PCH Policy update by board configuration. More...
EFI_STATUS | UpdatePeiSaPolicyBoardConfig (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI SA Policy update by board configuration. More...
EFI_STATUS | UpdatePeiTbtPolicyBoardConfig (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI TBT Policy update by board configuration. More...
EFI_STATUS | UpdatePeiSiPolicyBoardConfig (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI SI Policy update by board configuration. More...

Detailed Description

Header file for the PeiPolicyBoardConfig Library.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPolicyBoardConfigLib.h.

Function Documentation

EFI_STATUS UpdatePeiAmtPolicyBoardConfig ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs PEI AMT Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiCpuPolicyBoardConfig ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs PEI CPU Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiCpuPolicyBoardConfigPreMem ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

This function performs PEI CPU Pre-Memory Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI PreMem Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiMePolicyBoardConfig ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs PEI ME Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiMePolicyBoardConfigPreMem ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

This function performs PEI ME Pre-Memory Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI PreMem Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiPchPolicyBoardConfig ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs PEI PCH Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiPchPolicyBoardConfigPreMem ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

This function performs PEI PCH Pre-Memory Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI PreMem Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiSaPolicyBoardConfig ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs PEI SA Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiSaPolicyBoardConfigPreMem ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

This function performs PEI SA Pre-Memory Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI PreMem Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiSiPolicyBoardConfig ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs PEI SI Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.
EFI_STATUS UpdatePeiTbtPolicyBoardConfig ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs PEI TBT Policy update by board configuration.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.


IceLake Platform Sample Code: PeiPolicyInitLib.h File Reference

  • Library
Functions
PeiPolicyInitLib.h File Reference

Header file for the PolicyInitPei Library. More...

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Functions

VOID | PeiPolicyInitPreMem (IN UINT8 FirmwareConfiguration)
Initialize Intel PEI Platform Policy. More...
VOID | PeiPolicyInit (IN CONST EFI_PEI_SERVICES **PeiServices, IN UINT8 FirmwareConfiguration)
Initialize Intel PEI Platform Policy. More...

Detailed Description

Header file for the PolicyInitPei Library.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPolicyInitLib.h.

Function Documentation

VOID PeiPolicyInit | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN UINT8 | FirmwareConfiguration
 | ) |  |

Initialize Intel PEI Platform Policy.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | FirmwareConfiguration | It uses to skip specific policy init that depends on the 'FirmwareConfiguration' varaible.
VOID PeiPolicyInitPreMem ( IN UINT8 FirmwareConfiguration )

Initialize Intel PEI Platform Policy.

Parameters
[in] FirmwareConfiguration It uses to skip specific policy init that depends on the 'FirmwareConfiguration' varaible.


IceLake Platform Sample Code: PeiReadWriteVariableLib.h File Reference

  • Library
Functions
PeiReadWriteVariableLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS PeiReadWriteVariableInit (VOID)
Initialize PEI read write Variable PPI. More...

Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiReadWriteVariableLib.h.

Function Documentation

EFI_STATUS PeiReadWriteVariableInit ( VOID )

Initialize PEI read write Variable PPI.

Return values
Status
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiSaPolicyDebugLib.h File Reference

  • Library
Functions
PeiSaPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel SA PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS | UpdatePeiSaPolicyDebugPreMem (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs SA PEI Debug PreMem Policy initialization. More...
EFI_STATUS | UpdatePeiSaPolicyDebug (IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs SA PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel SA PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiSaPolicyDebugLib.h.

Function Documentation

EFI_STATUS UpdatePeiSaPolicyDebug ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

This function performs SA PEI Debug Policy initialization.

Parameters
[in] SiPolicyPpi The SA Policy PPI instance
Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.
EFI_STATUS UpdatePeiSaPolicyDebugPreMem ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

This function performs SA PEI Debug PreMem Policy initialization.

Parameters
[in] SiPreMemPolicyPpi The SA PreMem Policy PPI instance
Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


IceLake Platform Sample Code: PeiSiPolicyDebugLib.h File Reference

  • Library
Functions
PeiSiPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel SI PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS UpdatePeiSiPolicyDebug (IN OUT SI_POLICY_PPI *SiPolicy)
This function performs SI PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel SI PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiSiPolicyDebugLib.h.

Function Documentation

EFI_STATUS UpdatePeiSiPolicyDebug ( IN OUT SI_POLICY_PPI * SiPolicy )

This function performs SI PEI Debug Policy initialization.

Parameters
[in,out] SiPolicy The SI Policy PPI instance
Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


IceLake Platform Sample Code: PeiSwbpeLib.h File Reference

  • Library
PeiSwbpeLib.h File Reference
#include <DsAllocation.h>
#include <DsConfig.h>
#include <Swbpe.h>
Include dependency graph for PeiSwbpeLib.h:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiSwbpeLib.h.


IceLake Platform Sample Code: PeiWdtAppLib.h File Reference

  • Library
Functions
PeiWdtAppLib.h File Reference

PEI WDT App library definitions. More...

#include <Base.h>
#include <Uefi.h>
#include <Ppi/Wdt.h>
#include <Library/DebugLib.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Library/PeiServicesLib.h>
#include <WdtAppVariable.h>
Include dependency graph for PeiWdtAppLib.h:
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Functions

EFI_STATUS PeiWdtApp (IN WDT_PPI *WdtPei)
turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT status) and BIOS modules (through flash variable) More...

Detailed Description

PEI WDT App library definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiWdtAppLib.h.

Function Documentation

EFI_STATUS PeiWdtApp ( IN WDT_PPI * WdtPei )

turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT status) and BIOS modules (through flash variable)

Parameters
[in] WdtPei
Return values
EFI_SUCCESS
Generated on Sun Aug 13 2017 12:04:37 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Platform.h File Reference

Platform.h File Reference

This header file provides platform specific definitions used by other modules for platform specific initialization. More...

#include "CommonDefinitions.h"
#include "PchAccess.h"
#include "SaAccess.h"
Include dependency graph for Platform.h:
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Detailed Description

This header file provides platform specific definitions used by other modules for platform specific initialization.

This is not suitable for consumption by ASL or VRF files.

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Platform.h.


IceLake Platform Sample Code: PlatformBoardConfig.h File Reference

PlatformBoardConfig.h File Reference

Header file for Platform Boards Configurations. More...

#include <ConfigBlock.h>
#include <PchPolicyCommon.h>
#include <ConfigBlock/MemoryConfig.h>
#include <GpioConfig.h>
Include dependency graph for PlatformBoardConfig.h:
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Detailed Description

Header file for Platform Boards Configurations.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformBoardConfig.h.


IceLake Platform Sample Code: PlatformBoardId.h File Reference

PlatformBoardId.h File Reference

Defines Platform BoardIds. More...

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Detailed Description

Defines Platform BoardIds.

Copyright
"INTEL CONFIDENTIAL Copyright 2011 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way."

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformBoardId.h.


IceLake Platform Sample Code: PlatformClock.h File Reference

PlatformClock.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformClock.h.


IceLake Platform Sample Code: PlatformConfigurationChangeVariable.h File Reference

PlatformConfigurationChangeVariable.h File Reference

Platform configuration change variable definitions. More...

Go to the source code of this file.

Detailed Description

Platform configuration change variable definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PlatformConfigurationChangeVariable.h.


IceLake Platform Sample Code: PlatformEmmcHs400Info.h File Reference

  • Guid
Classes | Typedefs
PlatformEmmcHs400Info.h File Reference

GUID used for Platform Emmc Hs400 Tuning Info NVRAM Data. More...

Go to the source code of this file.

Classes

struct _PLATFORM_EMMC_TUNING_DATA
This structure describes the variable to be set with the returned EMMC_TUNING_DATA from EMMC_TUNE protocol. More...

Typedefs

typedef struct _PLATFORM_EMMC_TUNING_DATA PLATFORM_EMMC_TUNING_DATA
This structure describes the variable to be set with the returned EMMC_TUNING_DATA from EMMC_TUNE protocol.

Detailed Description

GUID used for Platform Emmc Hs400 Tuning Info NVRAM Data.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformEmmcHs400Info.h.


IceLake Platform Sample Code: PlatformGlobalVariable.h File Reference

  • Guid
PlatformGlobalVariable.h File Reference

GUID for Platform (NVRAM) Variables. More...

Go to the source code of this file.

Detailed Description

GUID for Platform (NVRAM) Variables.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PlatformGlobalVariable.h.


IceLake Platform Sample Code: PlatformInfo.h File Reference

Typedefs
PlatformInfo.h File Reference

GUID used for Platform Info Data entries in the HOB list. More...

#include <PlatformBoardType.h>
Include dependency graph for PlatformInfo.h:
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Typedefs

typedef UINT32 PCH_GPIO_PAD
PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h.

Detailed Description

GUID used for Platform Info Data entries in the HOB list.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file PlatformInfo.h.


IceLake Platform Sample Code: PlatformInit.c File Reference

  • PlatformInit
  • PlatformInitPei
Functions
PlatformInit.c File Reference

Source code file for Platform Init PEI module. More...

#include <Register/Msr.h>
#include <CpuRegs.h>
#include <PchAccess.h>
#include <MeChipset.h>
#include <SetupVariable.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Library/PchInfoLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/PciSegmentLib.h>
#include <IndustryStandard/Pci30.h>
#include <Library/PchCycleDecodingLib.h>
#include <Library/PmcLib.h>
#include <Library/GpioLib.h>
#include <Library/PeiPolicyInitLib.h>
#include <Ppi/EndOfPeiPhase.h>
#include <Library/MtrrLib.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Guid/SmramMemoryReserve.h>
#include <Library/PeiReadWriteVariableLib.h>
#include <Library/ConfigBlockLib.h>
#include <Ppi/SiPolicy.h>
#include <SaPolicyCommon.h>
#include <Library/SiPolicyLib.h>
#include <Board/Include/PeiPlatformHookLib.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Protocol/FirmwareVolumeBlock.h>
#include <Guid/SystemNvDataGuid.h>
#include <AttemptUsbFirst.h>
#include <Library/BoardConfigLib.h>
#include <Board/Include/BoardHook.h>
#include <Ppi/I2cMaster.h>
#include <Library/TimerLib.h>
#include "PlatformBoardId.h"
#include <Library/EcLib.h>
#include <Library/PostCodeLib.h>
#include <PlatformPostCode.h>
#include <Library/EcTcssLib.h>
#include <SaTcssHob.h>
#include <Library/ItbtPcieRpLib.h>
Include dependency graph for PlatformInit.c:

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Functions

EFI_STATUS | PlatformInitEndOfPei (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task at the end of PEI. More...
EFI_STATUS | SetCacheMtrrAfterEndOfPei (VOID)
Update MTRR setting and set write back as default memory attribute. More...
EFI_STATUS | ResetSarSensorSklSds (VOID)
Reset the SAR Sensor to ensure the SAR sensor can trigger an edge to the WWAN module on SKL SDS for FCC compliance. More...
EFI_STATUS | IOMReadyNotifyToEC (VOID)
This function sends IOM Ready Notify message to EC. More...
EFI_STATUS | CreateAttemptUsbFirstHotkeyInfoHob (VOID)
Create the HOB for hotkey status for 'Attempt USB First' feature. More...
EFI_STATUS | UpdateBiosGuardModulePtr (IN OUT EFI_PHYSICAL_ADDRESS *ModulePtr)
Get the BIOS Guard Module pointer. More...
EFI_STATUS | BiosGuardHobInit (IN CONST CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig)
Create and initialize BIOS Guard HOB. More...
VOID | DisableBiosLockForPeiWriteVariable (VOID)
Program SpiEiss and LE bit for Variable Write service.
EFI_STATUS | PlatformInitEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init PEI module entry point. More...

Detailed Description

Source code file for Platform Init PEI module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInit.c.

Function Documentation

EFI_STATUS BiosGuardHobInit ( IN CONST CPU_SECURITY_PREMEM_CONFIG * CpuSecurityPreMemConfig )

Create and initialize BIOS Guard HOB.

Parameters
[in] CpuSecurityPreMemConfig Pointer to a CPU_SECURITY_PREMEM_CONFIG
Return values
EFI_SUCCESS | HOB Creating successful.
Others | HOB Creating failed.

Definition at line 625 of file PlatformInit.c.

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EFI_STATUS CreateAttemptUsbFirstHotkeyInfoHob ( VOID )

Create the HOB for hotkey status for 'Attempt USB First' feature.

Return values
EFI_SUCCESS | HOB Creating successful.
Others | HOB Creating failed.

Build HOB for Attempt USB First feature

Definition at line 542 of file PlatformInit.c.

EFI_STATUS IOMReadyNotifyToEC ( VOID )

This function sends IOM Ready Notify message to EC.

Return values
EFI_SUCCESS | The function completed successfully
EFI_NOT_READY | IomReady bit is not set
others | Some error occurred

Locate HOB for TCSS Data and read IOM ready state

Definition at line 395 of file PlatformInit.c.

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EFI_STATUS PlatformInitEndOfPei | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

This function handles PlatformInit task at the end of PEI.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Ppi | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS The function completes successfully
others

Definition at line 503 of file PlatformInit.c.

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EFI_STATUS PlatformInitEntryPoint | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

Platform Init PEI module entry point.

Parameters
[in] | FileHandle | Not used.
[in] | PeiServices | General purpose services available to every PEIM.
Return values
EFI_SUCCESS | The function completes successfully
EFI_OUT_OF_RESOURCES | Insufficient resources to create database

Configure GPIO and SIO

Definition at line 912 of file PlatformInit.c.

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EFI_STATUS ResetSarSensorSklSds ( VOID )

Reset the SAR Sensor to ensure the SAR sensor can trigger an edge to the WWAN module on SKL SDS for FCC compliance.

Return values
EFI_SUCCESS | The function completes successfully.
Others | Some error occurs.

Definition at line 282 of file PlatformInit.c.

EFI_STATUS SetCacheMtrrAfterEndOfPei ( VOID )

Update MTRR setting and set write back as default memory attribute.

Return values
EFI_SUCCESS | The function completes successfully.
Others | Some error occurs.

Definition at line 107 of file PlatformInit.c.

EFI_STATUS UpdateBiosGuardModulePtr ( IN OUT EFI_PHYSICAL_ADDRESS * ModulePtr )

Get the BIOS Guard Module pointer.

Parameters
[in,out] ModulePtr - Input is a NULL pointer, and output points BIOS Guard module address if found.
Return values
EFI_SUCCESS | - BIOS Guard Module found.
EFI_NOT_FOUND | - BIOS Guard Module not found.

Locate Firmware Volume header

Locate Firmware File System file within Firmware Volume

Definition at line 582 of file PlatformInit.c.


IceLake Platform Sample Code: PlatformInitDxe.c File Reference

  • PlatformInit
  • PlatformInitDxe
Macros | Functions
PlatformInitDxe.c File Reference

Source code file for the Platform Init DXE module. More...

#include "PlatformInitDxe.h"
#include <CpuRegs.h>
#include <Guid/EventGroup.h>
#include <Library/BootGuardLib.h>
#include <Protocol/CpuInfo.h>
#include <Protocol/PlatformNvsArea.h>
#include <Protocol/VariableLock.h>
#include <Protocol/S3SaveState.h>
#include <SoftwareGuardSetupData.h>
#include <MeBiosPayloadHob.h>
#include <Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h>
#include <Library/CpuPlatformLib.h>
#include <Library/GpioLib.h>
#include <Library/PchPcrLib.h>
#include <Board/Include/BoardHook.h>
#include <Library/SmbiosProcessorLib.h>
#include <Protocol/PchReset.h>
#include <Guid/TpmInstance.h>
#include <Library/Tpm2CommandLib.h>
#include <Library/DxeSmbiosFirmwareVersionInfoLib.h>
#include <Library/PostCodeLib.h>
#include <PlatformPostCode.h>
#include <Private/CpuInitDataHob.h>
Include dependency graph for PlatformInitDxe.c:

Go to the source code of this file.

Macros

#define EPC_FRACTION_NUMERATOR 381
SGX EPC definitions.

Functions

EFI_STATUS | PlatformPchResetCallback (IN EFI_RESET_TYPE ResetType, IN EFI_GUID *ResetTypeGuid)
Call back function for Pch Reset. More...
VOID | EndofDxeCallback (IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInit task at the end of DXE. More...
VOID | RegisterEndOfDxeCallbacks (VOID)
Registers callback for.PlatformInitEndOfDxe. More...
VOID | PlatformDxeReadyToBootCallback (IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInitDxe task at the ready to boot. More...
VOID | RegisterReadyToBootCallback (VOID)
Registers callback for PlatformDxeReadyToBoot. More...
EPC_BIOS_CONFIG * | CreateSgxInfoForOs (VOID)
Creates a UEFI variable for OS with all data regarding SGX EPC. More...
VOID | UpdateEpcVariables (VOID)
Update BIOS and OS EPC UEFI variables. More...
VOID | UpdateSgxSvnVariable (VOID)
VOID | UpdateSgxPolicyStatusVariable (VOID)
Creates a UEFI variable for reporting platform SGX status information. More...
VOID | UpdatePlatformInfo (VOID)
Updates Platform information to the setup data. More...
EFI_STATUS | PlatformInitDxe (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point for the driver. More...

Detailed Description

Source code file for the Platform Init DXE module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitDxe.c.

Function Documentation

EPC_BIOS_CONFIG* CreateSgxInfoForOs ( VOID )

Creates a UEFI variable for OS with all data regarding SGX EPC.

Return values
EPC_BIOS_CONFIG Pointer to BIOS EPC variable structure

Presence of SGX feature is detectable by reading CPUID.(EAX=0x12, ECX=0):EAX[0]

If SGX was not activated

If SGX was enabled, this variable will hold the EPC length as it was read from CPUID SGX sub-leaf Else this variable will hold the value 0

Get CPU Init Data Hob

If C6DRAM is supported, then PRMRR size of 1MB will be supported. Reduce 0.5 MB from reported EPC size

Traverse over all SupportedPrmBins, skip the ones, that are lower or equal to 2 MB

No More supported PRM size

Current PRM size in MB

Don't include PRM sizes that are lower than 4MB

Calculate the supported EPC size: PRM_SIZE * (191/256) - 2MB - (0.5MB, if C6 DRAM is supported)

Definition at line 251 of file PlatformInitDxe.c.

VOID EndofDxeCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

This function handles PlatformInit task at the end of DXE.

Parameters
[in] | Event | The Event this notify function registered to.
[in] | Context | Pointer to the context data registered to the Event.

Verify if Boot Guard is supported

Identify if Revocation is requested by Boot Guard ACM

Definition at line 87 of file PlatformInitDxe.c.

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VOID PlatformDxeReadyToBootCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

This function handles PlatformInitDxe task at the ready to boot.

Parameters
[in] | Event | The Event this notify function registered to.
[in] | Context | Pointer to the context data registered to the Event.

Definition at line 185 of file PlatformInitDxe.c.

EFI_STATUS PlatformInitDxe | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Entry point for the driver.

Parameters
[in] | ImageHandle | Image Handle.
[in] | SystemTable | EFI System Table.
Return values
EFI_SUCCESS | Function has completed successfully.
Others | All other error conditions encountered result in an ASSERT.

Definition at line 736 of file PlatformInitDxe.c.

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EFI_STATUS PlatformPchResetCallback | ( | IN EFI_RESET_TYPE | ResetType,
 |  | IN EFI_GUID * | ResetTypeGuid
 | ) |  |

Call back function for Pch Reset.

Parameters
[in] | ResetType | Reset Types which includes GlobalReset.
[in] | ResetTypeGuid | Pointer to an EFI_GUID, which is the Reset Type Guid.
Return values
EFI_SUCCESS | The function completed successfully
Others | All other error conditions encountered result in an ASSERT.

Definition at line 228 of file PlatformInitDxe.c.

VOID RegisterEndOfDxeCallbacks ( VOID )

Registers callback for.PlatformInitEndOfDxe.

Performing PlatformInitEndOfDxe after the gEfiEndOfDxeEventGroup is signaled.

Definition at line 155 of file PlatformInitDxe.c.

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VOID RegisterReadyToBootCallback ( VOID )

Registers callback for PlatformDxeReadyToBoot.

Definition at line 200 of file PlatformInitDxe.c.

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VOID UpdateEpcVariables ( VOID )

Update BIOS and OS EPC UEFI variables.

Reading EPC_BIOS UEFI variable

Reading EPC_OS_CTRL UEFI variable

If SGX is not in 'Software Control' mode, delete EPC_BIOS (if found) & delete EPC_OS_CTRL variable (if found).

SGX is not in 'Software Control' mode and EPC_BIOS variable is found. Hence, deleting EPC_BIOS variable.

SGX is not in 'Software Control' mode and EPC_OS_CTRL variable is found. Hence, deleting EPC_OS_CTRL variable.

Get the CPU platform setup policy.

If BIOS EPC UEFI variable initialization fails

SGX is in 'Software Control' mode, need to update EPC_BIOS variable

Locking EPC_BIOS variable, setting it to be read only

If SGX was enabled and SGX setup option is set to auto

Updating PRMRR size setup option, to be compatible with current PRMRR size

Definition at line 383 of file PlatformInitDxe.c.

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VOID UpdatePlatformInfo ( VOID )

Updates Platform information to the setup data.

Definition at line 675 of file PlatformInitDxe.c.

VOID UpdateSgxPolicyStatusVariable ( VOID )

Creates a UEFI variable for reporting platform SGX status information.

Update SGX Status variables Initialize variables if CPU Setup data not found

Set SGX Status UEFI variable with updated values

Locking SOFTWARE_GUARD_STATUS variable, setting it to be read only

Definition at line 611 of file PlatformInitDxe.c.

VOID UpdateSgxSvnVariable ( VOID )

Locate CPU Info Protocol.

Locking SINIT_SVN_VARIABLE_NAME variable, setting it to be read only

Definition at line 561 of file PlatformInitDxe.c.


IceLake Platform Sample Code: PlatformInitDxe.h File Reference

  • PlatformInit
  • PlatformInitDxe
Functions
PlatformInitDxe.h File Reference

Platform Info Driver. More...

#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <PchAccess.h>
#include <SaAccess.h>
#include <Library/HobLib.h>
#include <SetupVariable.h>
#include <Library/DebugLib.h>
#include <Library/S3BootScriptLib.h>
#include <Library/BootGuardRevocationLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiLib.h>
#include <Uefi/UefiBaseType.h>
#include <OemSetup.h>
#include <Protocol/MemInfo.h>
#include <MemInfoHob.h>
#include <Library/PmcLib.h>
#include <Base.h>
#include "PlatformBoardId.h"
#include <PlatformBoardConfig.h>
#include <PlatformBoardType.h>
#include <Library/PciSegmentLib.h>
Include dependency graph for PlatformInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

VOID | SaPlatformInitDxe (VOID)
System Agent platform Initialization. More...
VOID | CheckLidBaseEcProtocolVersion (VOID)
Check Lid and Base EC Protocol Version. More...
VOID | UpdateDimmPopulation (VOID)
Updates DIMM slots status for Desktop,server and workstation boards. More...

Detailed Description

Platform Info Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitDxe.h.

Function Documentation

VOID CheckLidBaseEcProtocolVersion ( VOID )

Check Lid and Base EC Protocol Version.

Verifies LID base EC protocol version

Definition at line 49 of file EcPlatformInitDxe.c.

VOID SaPlatformInitDxe ( VOID )

System Agent platform Initialization.

Definition at line 406 of file SaPlatformInitDxe.c.

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VOID UpdateDimmPopulation ( VOID )

Updates DIMM slots status for Desktop,server and workstation boards.

Definition at line 252 of file SaPlatformInitDxe.c.

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IceLake Platform Sample Code: PlatformInitLib.h File Reference

  • Library
PlatformInitLib.h File Reference

Function prototype of PlatformInitLib. More...

Go to the source code of this file.

Detailed Description

Function prototype of PlatformInitLib.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitLib.h.


IceLake Platform Sample Code: PlatformInitPreMem.c File Reference

  • PlatformInit
  • PlatformInitPei
Classes | Macros | Functions | Variables
PlatformInitPreMem.c File Reference

Source code file for Platform Init Pre-Memory PEI module. More...

#include <Base.h>
#include <OemSetup.h>
#include <PchAccess.h>
#include <SetupVariable.h>
#include <PlatformBoardId.h>
#include <SaPolicyCommon.h>
#include <CpuAccess.h>
#include <Platform.h>
#include <MeChipset.h>
#include <IndustryStandard/Pci30.h>
#include <Library/IoLib.h>
#include <PlatformNvRamHookLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/TimerLib.h>
#include <Library/EcMiscLib.h>
#include <Library/EcCommands.h>
#include <Library/PciSegmentLib.h>
#include <Library/CpuPlatformLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PeiServicesLib.h>
#include <Board/Include/PeiPlatformHookLib.h>
#include <Library/PchCycleDecodingLib.h>
#include <Library/PchPcrLib.h>
#include <Library/MultiPlatSupportLib.h>
#include <Library/PeiPlatformRecoveryLib.h>
#include <Library/PeiPolicyInitLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/MtrrLib.h>
#include <Ppi/Smbus2.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Ppi/MemoryDiscovered.h>
#include <Ppi/FirmwareVolumeInfo.h>
#include <Ppi/Capsule.h>
#include <Ppi/BootInRecoveryMode.h>
#include <Ppi/MasterBootMode.h>
#include <Ppi/Reset.h>
#include <BootState.h>
#include <SimpleBootFlag.h>
#include <Guid/GlobalVariable.h>
#include <Guid/FirmwareFileSystem2.h>
#include <FastBootExceptionInfoHob.h>
#include <FastBootFunctionEnabledHob.h>
#include <Guid/TcoWdtHob.h>
#include <Guid/MemoryTypeInformation.h>
#include <Uefi/UefiInternalFormRepresentation.h>
#include <Library/PeiPlatformLib.h>
#include <Library/PeiWdtAppLib.h>
#include <Library/BiosIdLib.h>
#include <Include/Library/ConfigBlockLib.h>
#include <Library/PeiServicesTablePointerLib.h>
#include <Library/PchSerialIoLib.h>
#include <Library/SetupDataCacheLib.h>
#include <IndustryStandard/SmBios.h>
#include <FirwmareConfigurations.h>
#include <Library/BoardConfigLib.h>
#include <PlatformBoardConfig.h>
#include <Board/Include/BoardHook.h>
#include <Library/PmcLib.h>
#include <FastBootDataDef.h>
#include <Setup.h>
#include <Library/PostCodeLib.h>
#include <PlatformPostCode.h>
#include <Library/StallPpiLib.h>
#include <SaDataHob.h>
#include <Guid/ImageAuthentication.h>
#include "DsAllocation.h"

Go to the source code of this file.

Classes

struct MEMORY_MAP
If the debugger branch trace/data store debug feature is enabled This is an optional debug feature as enabling it will introduce significant changes in performance and system resources. More...

Macros

#define | RESET_GENERATOR_PORT 0xCF9
Reset Generator I/O Port.
#define | EC_GETWAKE_STATUS 0x35
Wake Event Types.

Functions

EFI_STATUS | PlatformInitPreMem (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced. More...
EFI_STATUS | MemoryDiscoveredPpiNotifyCallback (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Install Firmware Volume Hob's once there is main memory. More...
EFI_STATUS | SiPreMemPolicyPpiNotifyCallback (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after SaPolicy PPI to be installed. More...
EFI_STATUS | WdtAppPpiNotifyCallback (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after Wdt PPI to be installed. More...
EFI_STATUS | PlatformInitPreMemUpdateBootMode (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Interface)
EFI_STATUS | PchReset (IN CONST EFI_PEI_SERVICES **PeiServices)
Provide hard reset PPI service. More...
EFI_STATUS | PlatformVariableInit (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Interface)
Perform the default variable initializations after variable service is ready. More...
VOID | SetCacheMtrr (VOID)
Set Cache Mtrr. More...
VOID | GetCsmControlStatus (VOID)
figure out the CSM configuration and post it to PcdCsmEnable. More...
BOOLEAN | IsFastBootEnabled (VOID)
Check fast boot is enabled or not. More...
BOOLEAN | IsTimeOutOccurred (VOID)
Check Fast Boot 30-second WDT (TCO Timer) timeout has occurred. More...
BOOLEAN | IsPowerButtonOverride (VOID)
Check if this system boot is due to 4sec power button override has occurred. More...
BOOLEAN | IsPreviousBootSuccessful (VOID)
Check Boot Flag Status to determine if previous boot was successful. More...
BOOLEAN | IsBootWithNoChange (VOID)
Query PCH to determine if Intrusion Detection set. More...
EFI_STATUS | PrioritizeBootMode (IN OUT EFI_BOOT_MODE *CurrentBootMode, IN EFI_BOOT_MODE NewBootMode)
Given the current boot mode, and a proposed new boot mode, determine which has priority. More...
BOOLEAN | CheckOddParity (IN UINT8 Value)
Check if the value is of ODD parity. More...
UINT8 | GetSimpleBootFlag (VOID)
Get simple boot flag. More...
VOID | DetectBootMode (VOID)
Detect boot mode. More...
BOOLEAN | IsOverclockingEnabled (VOID)
Check to see the overclocking is enabled or not. More...
EFI_STATUS | CreateFastBootHob (IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Create Fast Boot HOB. More...
VOID | GetWakeupEventAndSaveToHob (OUT UINT8 *WakeUpType)
Parse the status registers for figuring out the wake-up event and save it into an GUID HOB which will be referenced later. More...
VOID | EarlyPlatformPchInit (VOID)
Early Platform PCH initialization. More...
VOID | SetTheStateToGoAfterG3 (IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Set the state to go after G3. More...
VOID | PlatformPchInit (IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers. More...
VOID | BuildDebugConfigDataHob (IN DEBUG_CONFIG_DATA *DebugConfigData)
Build a HOB for debug configure data. More...
EFI_STATUS | PlatformInitPreMemEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init before memory PEI module entry point. More...

Variables

GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE mBootModePriority []
Priority of our boot modes, highest priority first.

Detailed Description

Source code file for Platform Init Pre-Memory PEI module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitPreMem.c.

Function Documentation

VOID BuildDebugConfigDataHob ( IN DEBUG_CONFIG_DATA * DebugConfigData )

Build a HOB for debug configure data.

The DebugConfigHob is built by platform code and consumed by PeiDxeSmmDebugPrintErrorLevelLib and PeiDxeSmmSerialPortParameterLib library instances.

Parameters
[in] DebugConfigData A pointer to the DEBUG_CONFIG_DATA.

Definition at line 1916 of file PlatformInitPreMem.c.

BOOLEAN CheckOddParity ( IN UINT8 Value )

Check if the value is of ODD parity.

Parameters
[in] Value the 8 bits value
Return values
TRUE | the value is of ODD parity
FALSE | the value is not of ODD parity

Definition at line 1169 of file PlatformInitPreMem.c.

EFI_STATUS CreateFastBootHob ( IN EFI_PEI_READ_ONLY_VARIABLE2_PPI * VariableServices )

Create Fast Boot HOB.

Parameters
[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
Return values
EFI_SUCCESS The function completes successfully
others

If Fast Boot is enabled, create the FAST_BOOT_FUNCTION_ENABLED_HOB for other modules' reference.

When RTC battery is drained (RTC power loss) or Secondary NvRam content is cleared (via jumper short), this bit will get set. This is the Fast Boot Exception Type 2.

Check the EFI Globally-Defined variable which is nonexistent right after updating BIOS, to determine if BIOS was just updated.

If overclocking is enabled, then BIOS shall switch back to Full Boot mode

Definition at line 1513 of file PlatformInitPreMem.c.

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VOID DetectBootMode ( VOID )

Detect boot mode.

Clear Wake Status and Sleep Type

Report RTC battery failure

Definition at line 1383 of file PlatformInitPreMem.c.

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VOID EarlyPlatformPchInit ( VOID )

Early Platform PCH initialization.

Read the Second TO status bit

Create HOB

Clear the Second TO status bit

Definition at line 1705 of file PlatformInitPreMem.c.

VOID GetCsmControlStatus ( VOID )

figure out the CSM configuration and post it to PcdCsmEnable.

Parameters
[in] | Event | Event whose notification function is being invoked.
[in] | Context | Pointer to the notification function's context.

Read EFI variable

Definition at line 644 of file PlatformInitPreMem.c.

UINT8 GetSimpleBootFlag ( VOID )

Get simple boot flag.

Return values
LegacyValue
EfiValue

Read EFI variable

Read legacy simple boot flag

Definition at line 1195 of file PlatformInitPreMem.c.

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VOID GetWakeupEventAndSaveToHob ( OUT UINT8 * WakeUpType )

Parse the status registers for figuring out the wake-up event and save it into an GUID HOB which will be referenced later.

Parameters
[out] WakeUpType Updates the wakeuptype based on the status registers

Read the ACPI registers

Figure out the wake-up event

Definition at line 1615 of file PlatformInitPreMem.c.

BOOLEAN IsBootWithNoChange ( VOID )

Query PCH to determine if Intrusion Detection set.

Return values
TRUE No Change FALSE Change

Get last Boot State Variable From NVRAM

Read the TCO registers

This is the state of the hardware

Clear the bit for next boot.

Since it was OPEN, return that it cannot be in "no config. change boot"

Since it was CLOSED, return that can be "no config. change boot" Need variable to know that memory was tested AT LEAST one time!

Definition at line 1030 of file PlatformInitPreMem.c.

BOOLEAN IsFastBootEnabled ( VOID )

Check fast boot is enabled or not.

Return values
FastBootEnabledStatus TRUE means fast boot is enabled FALSE means fast boot is disabled

Definition at line 879 of file PlatformInitPreMem.c.

BOOLEAN IsOverclockingEnabled ( VOID )

Check to see the overclocking is enabled or not.

Return values
OverclockingEnabledStatus TRUE means overclocking is enabled FALSE means overclocking is disabled

Definition at line 1464 of file PlatformInitPreMem.c.

BOOLEAN IsPowerButtonOverride ( VOID )

Check if this system boot is due to 4sec power button override has occurred.

Return values
TRUE | Power Button Override occurred in last system boot
FALSE | Power Button Override didnt occur

Definition at line 946 of file PlatformInitPreMem.c.

BOOLEAN IsPreviousBootSuccessful ( VOID )

Check Boot Flag Status to determine if previous boot was successful.

Return values
TRUE | Previous Boot was success
FALSE | Previous Boot wasn't success

Get last Boot State Variable to confirm that it is not a first boot.

Definition at line 972 of file PlatformInitPreMem.c.

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BOOLEAN IsTimeOutOccurred ( VOID )

Check Fast Boot 30-second WDT (TCO Timer) timeout has occurred.

Return values
TRUE | Timeout has occurred
FALSE | Timeout didnt occur

Definition at line 924 of file PlatformInitPreMem.c.

EFI_STATUS MemoryDiscoveredPpiNotifyCallback | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Install Firmware Volume Hob's once there is main memory.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | Notify that this module published.
[in] | Ppi | PPI that was installed.
Return values
EFI_SUCCESS The function completed successfully.

Create a CPU hand-off information

If S3 resume, then we are done

Build HOB for DXE

Prepare the recovery service

Build Memory Mapped IO Resource which is used to build E820 Table in LegacyBios.

Definition at line 748 of file PlatformInitPreMem.c.

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EFI_STATUS PchReset ( IN CONST EFI_PEI_SERVICES ** PeiServices )

Provide hard reset PPI service.

To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).

Parameters
[in] PeiServices General purpose services available to every PEIM.
Return values
Not | return System reset occured.
EFI_DEVICE_ERROR | Device error, could not reset the system.

System reset occured, should never reach at this line.

Definition at line 1683 of file PlatformInitPreMem.c.

EFI_STATUS PlatformInitPreMem | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Ppi | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS The function completes successfully
others

Configure GPIO and SIO

Do basic PCH init

Set what state (S0/S5) to go to when power is re-applied after a power failure (G3 state)

Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.

BIOS should check the wake status before memory initialization to determine if ME has reset the system while the host was in a sleep state. If platform was not in a sleep state, BIOS should ensure a non-sleep exit path is taken by forcing an s5 exit.

Install Pre Memory PPIs

Definition at line 2015 of file PlatformInitPreMem.c.

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EFI_STATUS PlatformInitPreMemEntryPoint | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

Platform Init before memory PEI module entry point.

Parameters
[in] | FileHandle | Not used.
[in] | PeiServices | General purpose services available to every PEIM.
Return values
EFI_SUCCESS | The function completes successfully
EFI_OUT_OF_RESOURCES | Insufficient resources to create database
Todo:
this functionality should be moved to Si Pkg.

Allocate an initial buffer from heap for debugger use

Install Stall PPI

Todo:
it should be moved to Si Pkg.

Do Early PCH init

Performing PlatformInitPreMem after PeiReadOnlyVariable2 PPI produced

After code reorangized, memorycallback will run because the PPI is already installed when code run to here, it is supposed that the InstallEfiMemory is done before.

Definition at line 2249 of file PlatformInitPreMem.c.

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EFI_STATUS PlatformInitPreMemUpdateBootMode | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Interface
 | ) |  |

Check Simple Boot Flag

Don't set Diagnostics boot it will significantly impact boot performance. e.g.: MRC extensive memory test Current platform boot flow is very complex and it may reset before booting to OS. Need to design a hook machanism: bios calls PreReset() before resetting system when the BOOTING bit gets cleared.

PrioritizeBootMode (&BootMode, BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS);

Determine if we're in capsule update mode

if Fast Boot is enabled, check other excption conditions before prioritizing BootMode to BOOT_WITH_MINIMAL_CONFIGURATION

FastBoot - set boot progress bit to indicate boot is in progress bit will be cleared before booting to OS

Signal possible dependent modules that there has been a final boot mode determination, it is used to build BIST Hob for Dxe use.

If not in S3 mode, signal it.

Definition at line 1253 of file PlatformInitPreMem.c.

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VOID PlatformPchInit ( IN EFI_PEI_READ_ONLY_VARIABLE2_PPI * VariableServices )

Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers.

Parameters
[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.

Enable the LPC I/O decoding for 0x6A0~0x6A7 as EC's extra I/O port, where 0x6A0 is the Data port and 0x6A4 is the Command/Status port.

Definition at line 1825 of file PlatformInitPreMem.c.

EFI_STATUS PlatformVariableInit | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Interface
 | ) |  |

Perform the default variable initializations after variable service is ready.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Interface | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS The function completes successfully
others

Check whether OS defaults need to be loaded

To verify if secondary NvRam corrupted and see if resetting to default variable is required or not.

Check BootMode on Recovery boot or Boot with Default settings.

Check whether Setup Variable does exist to know the first boot or not.

Setup variable is not found. So, set the default setting.

Print default Setup variable.

Definition at line 327 of file PlatformInitPreMem.c.

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EFI_STATUS PrioritizeBootMode | ( | IN OUT EFI_BOOT_MODE * | CurrentBootMode,
 |  | IN EFI_BOOT_MODE | NewBootMode
 | ) |  |

Given the current boot mode, and a proposed new boot mode, determine which has priority.

If the new boot mode has higher priority, then make it the current boot mode.

Parameters
[in]

Find the position of the current boot mode in our priority array

Find the position of the new boot mode in our priority array

If this new boot mode occurs before the current boot mode in the priority array, then take it.

Definition at line 1118 of file PlatformInitPreMem.c.

VOID SetCacheMtrr ( VOID )

Set Cache Mtrr.

Reset all MTRR setting.

Cache the Flash area as WP to boost performance Set WP cache size to fixed at 16MB for saving MTRR usage.

Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance

Set low to 1 MB. Since 1MB cacheability will always be set until override by CSM. Initialize high memory to 0.

Assume size of main memory is multiple of 256MB

Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB

VGA-MMIO - 0xA0000 to 0xC0000 to be UC

Update MTRR setting from MTRR buffer

Definition at line 472 of file PlatformInitPreMem.c.

VOID SetTheStateToGoAfterG3 ( IN EFI_PEI_READ_ONLY_VARIABLE2_PPI * VariableServices )

Set the state to go after G3.

Parameters
[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.

Definition at line 1783 of file PlatformInitPreMem.c.

EFI_STATUS SiPreMemPolicyPpiNotifyCallback | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Run this function after SaPolicy PPI to be installed.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | Notify that this module published.
[in] | Ppi | PPI that was installed.
Return values
EFI_SUCCESS The function completed successfully.

Platform specific programming. It may have Chipset, EC or some platform specific programming here.

Definition at line 1858 of file PlatformInitPreMem.c.

EFI_STATUS WdtAppPpiNotifyCallback | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Run this function after Wdt PPI to be installed.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | Notify that this module published.
[in] | Ppi | PPI that was installed.
Return values
EFI_SUCCESS The function completed successfully.

Definition at line 1888 of file PlatformInitPreMem.c.

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IceLake Platform Sample Code: PlatformNvRamHookLib.h File Reference

Functions
PlatformNvRamHookLib.h File Reference

Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

BOOLEAN | IsChecksumBad (VOID)
Test to see if Checksum is bad. More...
VOID | ClearDiagnosticStatus (VOID)
Clear Diagnostic Status.
BOOLEAN | NeedResetBoardDefaultVariableHob (VOID)
Check to reset setup variable and Clear CMOS 0E when CMOS content is bad. More...
VOID | SecondaryNvRamInit (VOID)
Load CMOS default on RTC battery failure.
UINT8 | GetBootFlagStatus (VOID)
Get Boot Flag Status. More...
VOID | UpdateBootFlagStatus (UINT8 BootStatus)
Update Boot Flag Status. More...
UINT8 | GetRtc3Address (VOID)
Get RTC 3 Address. More...
VOID | GetPostCodeBreak (UINT8 *Port80, UINT8 *Port81)
Get Post Code Break for Port 80 and 81. More...
UINT8 | GetTxtAliasCheckAndReset (VOID)
Get TXT Alias Check Request and Reset it. More...
VOID | SaveTxtAliasCheck (UINT8 ACheckRequest)
Save the TXT Alias Check Request. More...
VOID | SaveCpuRatio (UINT8 CpuRatio)
Save the CPU Ratio. More...
VOID | SetBclkRampFlag (UINT8 BclkRampFlag)
Set the BCLK Ramp Flag. More...
VOID | SaveSaDisplayRegisters (VOID *SaSetupData, UINT8 DDISelection)
Save the SA settings related to Display. More...
UINT8 | GetTbtHostRouterStatus (VOID)
Get TBT Host Router Status. More...
VOID | SaveTbtHostRouterStatus (UINT8 TbtHrStatus)
Save TBT Host Router Status. More...

Detailed Description

Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2017 Intel Corporation. All rights reserved

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformNvRamHookLib.h.

Function Documentation

UINT8 GetBootFlagStatus ( VOID )

Get Boot Flag Status.

Return values
Value of current boot status
VOID GetPostCodeBreak | ( | UINT8 * | Port80,
 |  | UINT8 * | Port81
 | ) |  |

Get Post Code Break for Port 80 and 81.

Parameters
[out] | *Port80 | Pointer to return value of post code 80
[out] | *Port81 | Pointer to return value of post code 81
UINT8 GetRtc3Address ( VOID )

Get RTC 3 Address.

Return values
Current value of RTC 3 Address
UINT8 GetTbtHostRouterStatus ( VOID )

Get TBT Host Router Status.

CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)

Return values
Current value of TBT Host Router Status
UINT8 GetTxtAliasCheckAndReset ( VOID )

Get TXT Alias Check Request and Reset it.

Return values
TXT Alias Check Request
BOOLEAN IsChecksumBad ( VOID )

Test to see if Checksum is bad.

Return values
TRUE - Checksum content is bad FALSE - Checksum content is good
BOOLEAN NeedResetBoardDefaultVariableHob ( VOID )

Check to reset setup variable and Clear CMOS 0E when CMOS content is bad.

Return values
Flag to Reset Setup variable : TRUE - When CMOS content is bad FALSE - Otherwise
VOID SaveCpuRatio ( UINT8 CpuRatio )

Save the CPU Ratio.

Parameters
[in] CpuRatio The Cpu ratio value to be saved.
VOID SaveSaDisplayRegisters | ( | VOID * | SaSetupData,
 |  | UINT8 | DDISelection
 | ) |  |

Save the SA settings related to Display.

Parameters
[in] | SaSetup | Display related SA data to be saved
[in] | DDISelection | DDI Selection
VOID SaveTbtHostRouterStatus ( UINT8 TbtHrStatus )

Save TBT Host Router Status.

CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)

Parameters
[in] TbtHrStatus The TBT Host Router Status to be udpated.
VOID SaveTxtAliasCheck ( UINT8 ACheckRequest )

Save the TXT Alias Check Request.

Parameters
[in] ACheckRequest Request of TXT Alias Check.
VOID SetBclkRampFlag ( UINT8 BclkRampFlag )

Set the BCLK Ramp Flag.

Parameters
[in] BclkRampFlag The BCLK Ramp Flag to be set.
VOID UpdateBootFlagStatus ( UINT8 BootStatus )

Update Boot Flag Status.

Parameters
[in] BootStatus Current Boot value which to be updated.


IceLake Platform Sample Code: PlatformNvsArea.h File Reference

  • Protocol
PlatformNvsArea.h File Reference

This file defines the Platform NVS Area Protocol. More...

#include <PlatformNvsAreaDef.h>
Include dependency graph for PlatformNvsArea.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This file defines the Platform NVS Area Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformNvsArea.h.


IceLake Platform Sample Code: PlatformNvsAreaDef.h File Reference

PlatformNvsAreaDef.h File Reference

ACPI DSDT table. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

ACPI DSDT table.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PlatformNvsAreaDef.h.


IceLake Platform Sample Code: PlatformOpRomTable.h Source File

  • MultiPlatform
PlatformOpRomTable.h
1 /*++
2 Copyright (c) 2005 - 2007 Intel Corporation. All rights reserved
3 This software and associated documentation (if any) is furnished
4 under a license and may only be used or copied in accordance
5 with the terms of the license. Except as permitted by such
6 license, no part of this software or documentation may be
7 reproduced, stored in a retrieval system, or transmitted in any
8 form or by any means without the express written consent of
9 Intel Corporation.
10
11 Module Name:
12
13 PlatformOpRomTable.h
14
15 --*/
16
17 //
18 // Automatically generated by ACE ver 1.63 PIRQTRANS
19 // Please DO NOT modify !!!
20 //
21
22
23 //
24 // Global variables for Option Roms
25 //
26 #define NULL_ROM_FILE_GUID \
27 { \
28 0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 \
29 }
30
31 //
32 // {6A5F1EF9-C478-42ba-A4DB-C7846CC7DB57}
33 //
34 #define MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID \
35 { \
36 0x6A5F1EF9, 0xC478, 0x42ba, 0xA4, 0xDB, 0xC7, 0x84, 0x6C, 0xC7, 0xDB, 0x57 \
37 }
38
39 //
40 // {2BB1381D-AE4F-4b37-B999-812F93811282}
41 //
42 #define RAID_OPTION_ROM_FILE_GUID \
43 { \
44 0x2BB1381D, 0xAE4F, 0x4b37, 0xB9, 0x99, 0x81, 0x2F, 0x93, 0x81, 0x12, 0x82 \
45 }
46
47 //
48 // {BF3CE2C0-FCEE-11E1-A21F-0800200C9A66}
49 //
50 #define RSTE_OPTION_ROM_FILE_GUID \
51 { \
52 0xBF3CE2C0, 0xFCEE, 0x11E1, 0xA2, 0x1F, 0x08, 0x00, 0x20, 0x0C, 0x9A, 0x66 \
53 }
54
55 //
56 // {58531F11-5C10-4dea-A54C-0A017FA03425}
57 //
58 #define PXE_OPTION_ROM_FILE_GUID \
59 { \
60 0x58531F11, 0x5C10, 0x4dea, 0xA5, 0x4C, 0x0A, 0x01, 0x7F, 0xA0, 0x34, 0x25 \
61 }
62
63 #define MAX_ROM_NUMBER 4
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformOptionRomTable_Default.h Source File

  • MultiPlatform
PlatformOptionRomTable_Default.h
1 /*++
2 Copyright (c) 2005 - 2007 Intel Corporation. All rights reserved
3 This software and associated documentation (if any) is furnished
4 under a license and may only be used or copied in accordance
5 with the terms of the license. Except as permitted by such
6 license, no part of this software or documentation may be
7 reproduced, stored in a retrieval system, or transmitted in any
8 form or by any means without the express written consent of
9 Intel Corporation.
10
11 Module Name:
12
13 PlatformOptionRomTable_Default.h
14
15 --*/
16
17 //
18 // Automatically generated by ACE ver 1.63 PIRQTRANS
19 // Please DO NOT modify !!!
20 //
21
22
23 PCI_OPTION_ROM_TABLE mPciOptionRomTable_Default[] = {
24 //
25 // Option Rom for
26 //
27 {
28 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
29 0x0, // Segment
30 0x0, // Bus Number
31 0x2, // Device Number
32 0x0, // Function Number
33 0x8086, // Vendor ID
34 0x1906, // Device ID
35 },
36 //
37 // Option Rom for
38 //
39 {
40 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
41 0x0, // Segment
42 0x0, // Bus Number
43 0x2, // Device Number
44 0x0, // Function Number
45 0x8086, // Vendor ID
46 0x1913, // Device ID
47 },
48 //
49 // Option Rom for
50 //
51 {
52 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
53 0x0, // Segment
54 0x0, // Bus Number
55 0x2, // Device Number
56 0x0, // Function Number
57 0x8086, // Vendor ID
58 0x1916, // Device ID
59 },
60 //
61 // Option Rom for
62 //
63 {
64 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
65 0x0, // Segment
66 0x0, // Bus Number
67 0x2, // Device Number
68 0x0, // Function Number
69 0x8086, // Vendor ID
70 0x1921, // Device ID
71 },
72 //
73 // Option Rom for
74 //
75 {
76 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
77 0x0, // Segment
78 0x0, // Bus Number
79 0x2, // Device Number
80 0x0, // Function Number
81 0x8086, // Vendor ID
82 0x1926, // Device ID
83 },
84 //
85 // Option Rom for
86 //
87 {
88 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
89 0x0, // Segment
90 0x0, // Bus Number
91 0x2, // Device Number
92 0x0, // Function Number
93 0x8086, // Vendor ID
94 0x190b, // Device ID
95 },
96 //
97 // Option Rom for
98 //
99 {
100 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
101 0x0, // Segment
102 0x0, // Bus Number
103 0x2, // Device Number
104 0x0, // Function Number
105 0x8086, // Vendor ID
106 0x191b, // Device ID
107 },
108 //
109 // Option Rom for
110 //
111 {
112 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
113 0x0, // Segment
114 0x0, // Bus Number
115 0x2, // Device Number
116 0x0, // Function Number
117 0x8086, // Vendor ID
118 0x192b, // Device ID
119 },
120 //
121 // Option Rom for
122 //
123 {
124 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
125 0x0, // Segment
126 0x0, // Bus Number
127 0x2, // Device Number
128 0x0, // Function Number
129 0x8086, // Vendor ID
130 0x193b, // Device ID
131 },
132 //
133 // Option Rom for
134 //
135 {
136 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
137 0x0, // Segment
138 0x0, // Bus Number
139 0x2, // Device Number
140 0x0, // Function Number
141 0x8086, // Vendor ID
142 0x192d, // Device ID
143 },
144 //
145 // Option Rom for
146 //
147 {
148 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
149 0x0, // Segment
150 0x0, // Bus Number
151 0x2, // Device Number
152 0x0, // Function Number
153 0x8086, // Vendor ID
154 0x193d, // Device ID
155 },
156 //
157 // Option Rom for
158 //
159 {
160 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
161 0x0, // Segment
162 0x0, // Bus Number
163 0x2, // Device Number
164 0x0, // Function Number
165 0x8086, // Vendor ID
166 0x190e, // Device ID
167 },
168 //
169 // Option Rom for
170 //
171 {
172 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
173 0x0, // Segment
174 0x0, // Bus Number
175 0x2, // Device Number
176 0x0, // Function Number
177 0x8086, // Vendor ID
178 0x1915, // Device ID
179 },
180 //
181 // Option Rom for
182 //
183 {
184 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
185 0x0, // Segment
186 0x0, // Bus Number
187 0x2, // Device Number
188 0x0, // Function Number
189 0x8086, // Vendor ID
190 0x191e, // Device ID
191 },
192 //
193 // Option Rom for
194 //
195 {
196 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
197 0x0, // Segment
198 0x0, // Bus Number
199 0x2, // Device Number
200 0x0, // Function Number
201 0x8086, // Vendor ID
202 0x190a, // Device ID
203 },
204 //
205 // Option Rom for
206 //
207 {
208 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
209 0x0, // Segment
210 0x0, // Bus Number
211 0x2, // Device Number
212 0x0, // Function Number
213 0x8086, // Vendor ID
214 0x191a, // Device ID
215 },
216 //
217 // Option Rom for
218 //
219 {
220 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
221 0x0, // Segment
222 0x0, // Bus Number
223 0x2, // Device Number
224 0x0, // Function Number
225 0x8086, // Vendor ID
226 0x192a, // Device ID
227 },
228 //
229 // Option Rom for
230 //
231 {
232 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
233 0x0, // Segment
234 0x0, // Bus Number
235 0x2, // Device Number
236 0x0, // Function Number
237 0x8086, // Vendor ID
238 0x193a, // Device ID
239 },
240 //
241 // Option Rom for
242 //
243 {
244 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
245 0x0, // Segment
246 0x0, // Bus Number
247 0x2, // Device Number
248 0x0, // Function Number
249 0x8086, // Vendor ID
250 0x1902, // Device ID
251 },
252 //
253 // Option Rom for
254 //
255 {
256 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
257 0x0, // Segment
258 0x0, // Bus Number
259 0x2, // Device Number
260 0x0, // Function Number
261 0x8086, // Vendor ID
262 0x1912, // Device ID
263 },
264 //
265 // Option Rom for
266 //
267 {
268 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
269 0x0, // Segment
270 0x0, // Bus Number
271 0x2, // Device Number
272 0x0, // Function Number
273 0x8086, // Vendor ID
274 0x1917, // Device ID
275 },
276 //
277 // Option Rom for
278 //
279 {
280 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
281 0x0, // Segment
282 0x0, // Bus Number
283 0x2, // Device Number
284 0x0, // Function Number
285 0x8086, // Vendor ID
286 0x1932, // Device ID
287 },
288 //
289 // Option Rom for
290 //
291 {
292 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
293 0x0, // Segment
294 0x0, // Bus Number
295 0x2, // Device Number
296 0x0, // Function Number
297 0x8086, // Vendor ID
298 0x191d, // Device ID
299 },
300 //
301 // Option Rom for
302 //
303 {
304 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
305 0x0, // Segment
306 0x0, // Bus Number
307 0x2, // Device Number
308 0x0, // Function Number
309 0x8086, // Vendor ID
310 0x5906, // Device ID
311 },
312 //
313 // Option Rom for
314 //
315 {
316 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
317 0x0, // Segment
318 0x0, // Bus Number
319 0x2, // Device Number
320 0x0, // Function Number
321 0x8086, // Vendor ID
322 0x5913, // Device ID
323 },
324 //
325 // Option Rom for
326 //
327 {
328 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
329 0x0, // Segment
330 0x0, // Bus Number
331 0x2, // Device Number
332 0x0, // Function Number
333 0x8086, // Vendor ID
334 0x5916, // Device ID
335 },
336 //
337 // Option Rom for
338 //
339 {
340 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
341 0x0, // Segment
342 0x0, // Bus Number
343 0x2, // Device Number
344 0x0, // Function Number
345 0x8086, // Vendor ID
346 0x5921, // Device ID
347 },
348 //
349 // Option Rom for
350 //
351 {
352 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
353 0x0, // Segment
354 0x0, // Bus Number
355 0x2, // Device Number
356 0x0, // Function Number
357 0x8086, // Vendor ID
358 0x5926, // Device ID
359 },
360 //
361 // Option Rom for
362 //
363 {
364 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
365 0x0, // Segment
366 0x0, // Bus Number
367 0x2, // Device Number
368 0x0, // Function Number
369 0x8086, // Vendor ID
370 0x590b, // Device ID
371 },
372 //
373 // Option Rom for
374 //
375 {
376 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
377 0x0, // Segment
378 0x0, // Bus Number
379 0x2, // Device Number
380 0x0, // Function Number
381 0x8086, // Vendor ID
382 0x591b, // Device ID
383 },
384 //
385 // Option Rom for
386 //
387 {
388 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
389 0x0, // Segment
390 0x0, // Bus Number
391 0x2, // Device Number
392 0x0, // Function Number
393 0x8086, // Vendor ID
394 0x592b, // Device ID
395 },
396 //
397 // Option Rom for
398 //
399 {
400 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
401 0x0, // Segment
402 0x0, // Bus Number
403 0x2, // Device Number
404 0x0, // Function Number
405 0x8086, // Vendor ID
406 0x593b, // Device ID
407 },
408 //
409 // Option Rom for
410 //
411 {
412 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
413 0x0, // Segment
414 0x0, // Bus Number
415 0x2, // Device Number
416 0x0, // Function Number
417 0x8086, // Vendor ID
418 0x590e, // Device ID
419 },
420 //
421 // Option Rom for
422 //
423 {
424 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
425 0x0, // Segment
426 0x0, // Bus Number
427 0x2, // Device Number
428 0x0, // Function Number
429 0x8086, // Vendor ID
430 0x5915, // Device ID
431 },
432 //
433 // Option Rom for
434 //
435 {
436 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
437 0x0, // Segment
438 0x0, // Bus Number
439 0x2, // Device Number
440 0x0, // Function Number
441 0x8086, // Vendor ID
442 0x591e, // Device ID
443 },
444 //
445 // Option Rom for
446 //
447 {
448 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
449 0x0, // Segment
450 0x0, // Bus Number
451 0x2, // Device Number
452 0x0, // Function Number
453 0x8086, // Vendor ID
454 0x590a, // Device ID
455 },
456 //
457 // Option Rom for
458 //
459 {
460 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
461 0x0, // Segment
462 0x0, // Bus Number
463 0x2, // Device Number
464 0x0, // Function Number
465 0x8086, // Vendor ID
466 0x591a, // Device ID
467 },
468 //
469 // Option Rom for
470 //
471 {
472 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
473 0x0, // Segment
474 0x0, // Bus Number
475 0x2, // Device Number
476 0x0, // Function Number
477 0x8086, // Vendor ID
478 0x592a, // Device ID
479 },
480 //
481 // Option Rom for
482 //
483 {
484 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
485 0x0, // Segment
486 0x0, // Bus Number
487 0x2, // Device Number
488 0x0, // Function Number
489 0x8086, // Vendor ID
490 0x593a, // Device ID
491 },
492 //
493 // Option Rom for
494 //
495 {
496 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
497 0x0, // Segment
498 0x0, // Bus Number
499 0x2, // Device Number
500 0x0, // Function Number
501 0x8086, // Vendor ID
502 0x5902, // Device ID
503 },
504 //
505 // Option Rom for
506 //
507 {
508 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
509 0x0, // Segment
510 0x0, // Bus Number
511 0x2, // Device Number
512 0x0, // Function Number
513 0x8086, // Vendor ID
514 0x5912, // Device ID
515 },
516 //
517 // Option Rom for
518 //
519 {
520 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
521 0x0, // Segment
522 0x0, // Bus Number
523 0x2, // Device Number
524 0x0, // Function Number
525 0x8086, // Vendor ID
526 0x5917, // Device ID
527 },
528 //
529 // Option Rom for
530 //
531 {
532 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
533 0x0, // Segment
534 0x0, // Bus Number
535 0x2, // Device Number
536 0x0, // Function Number
537 0x8086, // Vendor ID
538 0x5932, // Device ID
539 },
540 //
541 // Option Rom for
542 //
543 {
544 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
545 0x0, // Segment
546 0x0, // Bus Number
547 0x2, // Device Number
548 0x0, // Function Number
549 0x8086, // Vendor ID
550 0x591d, // Device ID
551 },
552 //
553 // Option Rom for
554 //
555 {
556 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
557 0x0, // Segment
558 0x0, // Bus Number
559 0x2, // Device Number
560 0x0, // Function Number
561 0x8086, // Vendor ID
562 0x593d, // Device ID
563 },
564 //
565 // Option Rom for
566 //
567 {
568 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
569 0x0, // Segment
570 0x0, // Bus Number
571 0x2, // Device Number
572 0x0, // Function Number
573 0x8086, // Vendor ID
574 0x2a42, // Device ID
575 },
576 //
577 // Option Rom for
578 //
579 {
580 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
581 0x0, // Segment
582 0x0, // Bus Number
583 0x2, // Device Number
584 0x0, // Function Number
585 0x8086, // Vendor ID
586 0x106, // Device ID
587 },
588 //
589 // Option Rom for
590 //
591 {
592 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
593 0x0, // Segment
594 0x0, // Bus Number
595 0x2, // Device Number
596 0x0, // Function Number
597 0x8086, // Vendor ID
598 0x116, // Device ID
599 },
600 //
601 // Option Rom for
602 //
603 {
604 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
605 0x0, // Segment
606 0x0, // Bus Number
607 0x2, // Device Number
608 0x0, // Function Number
609 0x8086, // Vendor ID
610 0x126, // Device ID
611 },
612 //
613 // Option Rom for
614 //
615 {
616 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
617 0x0, // Segment
618 0x0, // Bus Number
619 0x2, // Device Number
620 0x0, // Function Number
621 0x8086, // Vendor ID
622 0xa02, // Device ID
623 },
624 //
625 // Option Rom for
626 //
627 {
628 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
629 0x0, // Segment
630 0x0, // Bus Number
631 0x2, // Device Number
632 0x0, // Function Number
633 0x8086, // Vendor ID
634 0x102, // Device ID
635 },
636 //
637 // Option Rom for
638 //
639 {
640 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
641 0x0, // Segment
642 0x0, // Bus Number
643 0x2, // Device Number
644 0x0, // Function Number
645 0x8086, // Vendor ID
646 0x112, // Device ID
647 },
648 //
649 // Option Rom for
650 //
651 {
652 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
653 0x0, // Segment
654 0x0, // Bus Number
655 0x2, // Device Number
656 0x0, // Function Number
657 0x8086, // Vendor ID
658 0x122, // Device ID
659 },
660 //
661 // Option Rom for
662 //
663 {
664 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
665 0x0, // Segment
666 0x0, // Bus Number
667 0x2, // Device Number
668 0x0, // Function Number
669 0x8086, // Vendor ID
670 0x10a, // Device ID
671 },
672 //
673 // Option Rom for
674 //
675 {
676 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
677 0x0, // Segment
678 0x0, // Bus Number
679 0x2, // Device Number
680 0x0, // Function Number
681 0x8086, // Vendor ID
682 0x5a51, // Device ID
683 },
684 //
685 // Option Rom for
686 //
687 {
688 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
689 0x0, // Segment
690 0x0, // Bus Number
691 0x2, // Device Number
692 0x0, // Function Number
693 0x8086, // Vendor ID
694 0x5a52, // Device ID
695 },
696 //
697 // Option Rom for
698 //
699 {
700 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
701 0x0, // Segment
702 0x0, // Bus Number
703 0x2, // Device Number
704 0x0, // Function Number
705 0x8086, // Vendor ID
706 0x5a5a, // Device ID
707 },
708 //
709 // Option Rom for
710 //
711 {
712 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
713 0x0, // Segment
714 0x0, // Bus Number
715 0x2, // Device Number
716 0x0, // Function Number
717 0x8086, // Vendor ID
718 0x5a42, // Device ID
719 },
720 //
721 // Option Rom for
722 //
723 {
724 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
725 0x0, // Segment
726 0x0, // Bus Number
727 0x2, // Device Number
728 0x0, // Function Number
729 0x8086, // Vendor ID
730 0x5a4a, // Device ID
731 },
732 //
733 // Option Rom for
734 //
735 {
736 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
737 0x0, // Segment
738 0x0, // Bus Number
739 0x2, // Device Number
740 0x0, // Function Number
741 0x8086, // Vendor ID
742 0x5a62, // Device ID
743 },
744 //
745 // Option Rom for
746 //
747 {
748 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
749 0x0, // Segment
750 0x0, // Bus Number
751 0x2, // Device Number
752 0x0, // Function Number
753 0x8086, // Vendor ID
754 0x5a54, // Device ID
755 },
756 //
757 // Option Rom for
758 //
759 {
760 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
761 0x0, // Segment
762 0x0, // Bus Number
763 0x2, // Device Number
764 0x0, // Function Number
765 0x8086, // Vendor ID
766 0x5a44, // Device ID
767 },
768 //
769 // Option Rom for
770 //
771 {
772 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
773 0x0, // Segment
774 0x0, // Bus Number
775 0x2, // Device Number
776 0x0, // Function Number
777 0x8086, // Vendor ID
778 0x5a55, // Device ID
779 },
780 //
781 // Option Rom for
782 //
783 {
784 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
785 0x0, // Segment
786 0x0, // Bus Number
787 0x2, // Device Number
788 0x0, // Function Number
789 0x8086, // Vendor ID
790 0x5a45, // Device ID
791 },
792 //
793 // Option Rom for
794 //
795 {
796 RAID_OPTION_ROM_FILE_GUID, // Guid
797 0x0, // Segment
798 0x0, // Bus Number
799 0x17, // Device Number
800 0x0, // Function Number
801 0x8086, // Vendor ID
802 0x282a, // Device ID
803 },
804 //
805 // Option Rom for
806 //
807 {
808 RAID_OPTION_ROM_FILE_GUID, // Guid
809 0x0, // Segment
810 0x0, // Bus Number
811 0x17, // Device Number
812 0x0, // Function Number
813 0x8086, // Vendor ID
814 0x2822, // Device ID
815 },
816 //
817 // Option Rom for
818 //
819 {
820 RSTE_OPTION_ROM_FILE_GUID, // Guid
821 0x0, // Segment
822 0x0, // Bus Number
823 0x17, // Device Number
824 0x0, // Function Number
825 0x8086, // Vendor ID
826 0x2826, // Device ID
827 },
828 //
829 // Option Rom for
830 //
831 {
832 PXE_OPTION_ROM_FILE_GUID, // Guid
833 0x0, // Segment
834 0x0, // Bus Number
835 0x1f, // Device Number
836 0x6, // Function Number
837 0xffff, // Vendor ID
838 0xffff, // Device ID
839 },
840 //
841 // End of OptionRom Entries
842 //
843 {
844 NULL_ROM_FILE_GUID, // Guid
845 0, // Segment
846 0, // Bus Number
847 0, // Device Number
848 0, // Function Number
849 0xffff, // Vendor ID
850 0xffff, // Device ID
851 }
852 };
853
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformOptionRomTable_Rvp.h Source File

  • MultiPlatform
PlatformOptionRomTable_Rvp.h
1 /*++
2 Copyright (c) 2005 - 2007 Intel Corporation. All rights reserved
3 This software and associated documentation (if any) is furnished
4 under a license and may only be used or copied in accordance
5 with the terms of the license. Except as permitted by such
6 license, no part of this software or documentation may be
7 reproduced, stored in a retrieval system, or transmitted in any
8 form or by any means without the express written consent of
9 Intel Corporation.
10
11 Module Name:
12
13 PlatformOptionRomTable_Rvp.h
14
15 --*/
16
17 //
18 // Automatically generated by ACE ver 1.63 PIRQTRANS
19 // Please DO NOT modify !!!
20 //
21
22
23 PCI_OPTION_ROM_TABLE mPciOptionRomTable_Rvp[] = {
24 //
25 // Option Rom for
26 //
27 {
28 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
29 0x0, // Segment
30 0x0, // Bus Number
31 0x2, // Device Number
32 0x0, // Function Number
33 0x8086, // Vendor ID
34 0x1906, // Device ID
35 },
36 //
37 // Option Rom for
38 //
39 {
40 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
41 0x0, // Segment
42 0x0, // Bus Number
43 0x2, // Device Number
44 0x0, // Function Number
45 0x8086, // Vendor ID
46 0x1913, // Device ID
47 },
48 //
49 // Option Rom for
50 //
51 {
52 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
53 0x0, // Segment
54 0x0, // Bus Number
55 0x2, // Device Number
56 0x0, // Function Number
57 0x8086, // Vendor ID
58 0x1916, // Device ID
59 },
60 //
61 // Option Rom for
62 //
63 {
64 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
65 0x0, // Segment
66 0x0, // Bus Number
67 0x2, // Device Number
68 0x0, // Function Number
69 0x8086, // Vendor ID
70 0x1921, // Device ID
71 },
72 //
73 // Option Rom for
74 //
75 {
76 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
77 0x0, // Segment
78 0x0, // Bus Number
79 0x2, // Device Number
80 0x0, // Function Number
81 0x8086, // Vendor ID
82 0x1926, // Device ID
83 },
84 //
85 // Option Rom for
86 //
87 {
88 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
89 0x0, // Segment
90 0x0, // Bus Number
91 0x2, // Device Number
92 0x0, // Function Number
93 0x8086, // Vendor ID
94 0x190b, // Device ID
95 },
96 //
97 // Option Rom for
98 //
99 {
100 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
101 0x0, // Segment
102 0x0, // Bus Number
103 0x2, // Device Number
104 0x0, // Function Number
105 0x8086, // Vendor ID
106 0x191b, // Device ID
107 },
108 //
109 // Option Rom for
110 //
111 {
112 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
113 0x0, // Segment
114 0x0, // Bus Number
115 0x2, // Device Number
116 0x0, // Function Number
117 0x8086, // Vendor ID
118 0x192b, // Device ID
119 },
120 //
121 // Option Rom for
122 //
123 {
124 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
125 0x0, // Segment
126 0x0, // Bus Number
127 0x2, // Device Number
128 0x0, // Function Number
129 0x8086, // Vendor ID
130 0x193b, // Device ID
131 },
132 //
133 // Option Rom for
134 //
135 {
136 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
137 0x0, // Segment
138 0x0, // Bus Number
139 0x2, // Device Number
140 0x0, // Function Number
141 0x8086, // Vendor ID
142 0x192d, // Device ID
143 },
144 //
145 // Option Rom for
146 //
147 {
148 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
149 0x0, // Segment
150 0x0, // Bus Number
151 0x2, // Device Number
152 0x0, // Function Number
153 0x8086, // Vendor ID
154 0x193d, // Device ID
155 },
156 //
157 // Option Rom for
158 //
159 {
160 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
161 0x0, // Segment
162 0x0, // Bus Number
163 0x2, // Device Number
164 0x0, // Function Number
165 0x8086, // Vendor ID
166 0x190e, // Device ID
167 },
168 //
169 // Option Rom for
170 //
171 {
172 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
173 0x0, // Segment
174 0x0, // Bus Number
175 0x2, // Device Number
176 0x0, // Function Number
177 0x8086, // Vendor ID
178 0x1915, // Device ID
179 },
180 //
181 // Option Rom for
182 //
183 {
184 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
185 0x0, // Segment
186 0x0, // Bus Number
187 0x2, // Device Number
188 0x0, // Function Number
189 0x8086, // Vendor ID
190 0x191e, // Device ID
191 },
192 //
193 // Option Rom for
194 //
195 {
196 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
197 0x0, // Segment
198 0x0, // Bus Number
199 0x2, // Device Number
200 0x0, // Function Number
201 0x8086, // Vendor ID
202 0x190a, // Device ID
203 },
204 //
205 // Option Rom for
206 //
207 {
208 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
209 0x0, // Segment
210 0x0, // Bus Number
211 0x2, // Device Number
212 0x0, // Function Number
213 0x8086, // Vendor ID
214 0x191a, // Device ID
215 },
216 //
217 // Option Rom for
218 //
219 {
220 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
221 0x0, // Segment
222 0x0, // Bus Number
223 0x2, // Device Number
224 0x0, // Function Number
225 0x8086, // Vendor ID
226 0x192a, // Device ID
227 },
228 //
229 // Option Rom for
230 //
231 {
232 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
233 0x0, // Segment
234 0x0, // Bus Number
235 0x2, // Device Number
236 0x0, // Function Number
237 0x8086, // Vendor ID
238 0x193a, // Device ID
239 },
240 //
241 // Option Rom for
242 //
243 {
244 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
245 0x0, // Segment
246 0x0, // Bus Number
247 0x2, // Device Number
248 0x0, // Function Number
249 0x8086, // Vendor ID
250 0x1902, // Device ID
251 },
252 //
253 // Option Rom for
254 //
255 {
256 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
257 0x0, // Segment
258 0x0, // Bus Number
259 0x2, // Device Number
260 0x0, // Function Number
261 0x8086, // Vendor ID
262 0x1912, // Device ID
263 },
264 //
265 // Option Rom for
266 //
267 {
268 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
269 0x0, // Segment
270 0x0, // Bus Number
271 0x2, // Device Number
272 0x0, // Function Number
273 0x8086, // Vendor ID
274 0x1917, // Device ID
275 },
276 //
277 // Option Rom for
278 //
279 {
280 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
281 0x0, // Segment
282 0x0, // Bus Number
283 0x2, // Device Number
284 0x0, // Function Number
285 0x8086, // Vendor ID
286 0x1932, // Device ID
287 },
288 //
289 // Option Rom for
290 //
291 {
292 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
293 0x0, // Segment
294 0x0, // Bus Number
295 0x2, // Device Number
296 0x0, // Function Number
297 0x8086, // Vendor ID
298 0x191d, // Device ID
299 },
300 //
301 // Option Rom for
302 //
303 {
304 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
305 0x0, // Segment
306 0x0, // Bus Number
307 0x2, // Device Number
308 0x0, // Function Number
309 0x8086, // Vendor ID
310 0x5906, // Device ID
311 },
312 //
313 // Option Rom for
314 //
315 {
316 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
317 0x0, // Segment
318 0x0, // Bus Number
319 0x2, // Device Number
320 0x0, // Function Number
321 0x8086, // Vendor ID
322 0x5913, // Device ID
323 },
324 //
325 // Option Rom for
326 //
327 {
328 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
329 0x0, // Segment
330 0x0, // Bus Number
331 0x2, // Device Number
332 0x0, // Function Number
333 0x8086, // Vendor ID
334 0x5916, // Device ID
335 },
336 //
337 // Option Rom for
338 //
339 {
340 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
341 0x0, // Segment
342 0x0, // Bus Number
343 0x2, // Device Number
344 0x0, // Function Number
345 0x8086, // Vendor ID
346 0x5921, // Device ID
347 },
348 //
349 // Option Rom for
350 //
351 {
352 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
353 0x0, // Segment
354 0x0, // Bus Number
355 0x2, // Device Number
356 0x0, // Function Number
357 0x8086, // Vendor ID
358 0x5926, // Device ID
359 },
360 //
361 // Option Rom for
362 //
363 {
364 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
365 0x0, // Segment
366 0x0, // Bus Number
367 0x2, // Device Number
368 0x0, // Function Number
369 0x8086, // Vendor ID
370 0x590b, // Device ID
371 },
372 //
373 // Option Rom for
374 //
375 {
376 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
377 0x0, // Segment
378 0x0, // Bus Number
379 0x2, // Device Number
380 0x0, // Function Number
381 0x8086, // Vendor ID
382 0x591b, // Device ID
383 },
384 //
385 // Option Rom for
386 //
387 {
388 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
389 0x0, // Segment
390 0x0, // Bus Number
391 0x2, // Device Number
392 0x0, // Function Number
393 0x8086, // Vendor ID
394 0x592b, // Device ID
395 },
396 //
397 // Option Rom for
398 //
399 {
400 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
401 0x0, // Segment
402 0x0, // Bus Number
403 0x2, // Device Number
404 0x0, // Function Number
405 0x8086, // Vendor ID
406 0x593b, // Device ID
407 },
408 //
409 // Option Rom for
410 //
411 {
412 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
413 0x0, // Segment
414 0x0, // Bus Number
415 0x2, // Device Number
416 0x0, // Function Number
417 0x8086, // Vendor ID
418 0x590e, // Device ID
419 },
420 //
421 // Option Rom for
422 //
423 {
424 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
425 0x0, // Segment
426 0x0, // Bus Number
427 0x2, // Device Number
428 0x0, // Function Number
429 0x8086, // Vendor ID
430 0x5915, // Device ID
431 },
432 //
433 // Option Rom for
434 //
435 {
436 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
437 0x0, // Segment
438 0x0, // Bus Number
439 0x2, // Device Number
440 0x0, // Function Number
441 0x8086, // Vendor ID
442 0x591e, // Device ID
443 },
444 //
445 // Option Rom for
446 //
447 {
448 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
449 0x0, // Segment
450 0x0, // Bus Number
451 0x2, // Device Number
452 0x0, // Function Number
453 0x8086, // Vendor ID
454 0x590a, // Device ID
455 },
456 //
457 // Option Rom for
458 //
459 {
460 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
461 0x0, // Segment
462 0x0, // Bus Number
463 0x2, // Device Number
464 0x0, // Function Number
465 0x8086, // Vendor ID
466 0x591a, // Device ID
467 },
468 //
469 // Option Rom for
470 //
471 {
472 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
473 0x0, // Segment
474 0x0, // Bus Number
475 0x2, // Device Number
476 0x0, // Function Number
477 0x8086, // Vendor ID
478 0x592a, // Device ID
479 },
480 //
481 // Option Rom for
482 //
483 {
484 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
485 0x0, // Segment
486 0x0, // Bus Number
487 0x2, // Device Number
488 0x0, // Function Number
489 0x8086, // Vendor ID
490 0x593a, // Device ID
491 },
492 //
493 // Option Rom for
494 //
495 {
496 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
497 0x0, // Segment
498 0x0, // Bus Number
499 0x2, // Device Number
500 0x0, // Function Number
501 0x8086, // Vendor ID
502 0x5902, // Device ID
503 },
504 //
505 // Option Rom for
506 //
507 {
508 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
509 0x0, // Segment
510 0x0, // Bus Number
511 0x2, // Device Number
512 0x0, // Function Number
513 0x8086, // Vendor ID
514 0x5912, // Device ID
515 },
516 //
517 // Option Rom for
518 //
519 {
520 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
521 0x0, // Segment
522 0x0, // Bus Number
523 0x2, // Device Number
524 0x0, // Function Number
525 0x8086, // Vendor ID
526 0x5917, // Device ID
527 },
528 //
529 // Option Rom for
530 //
531 {
532 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
533 0x0, // Segment
534 0x0, // Bus Number
535 0x2, // Device Number
536 0x0, // Function Number
537 0x8086, // Vendor ID
538 0x5932, // Device ID
539 },
540 //
541 // Option Rom for
542 //
543 {
544 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
545 0x0, // Segment
546 0x0, // Bus Number
547 0x2, // Device Number
548 0x0, // Function Number
549 0x8086, // Vendor ID
550 0x591d, // Device ID
551 },
552 //
553 // Option Rom for
554 //
555 {
556 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
557 0x0, // Segment
558 0x0, // Bus Number
559 0x2, // Device Number
560 0x0, // Function Number
561 0x8086, // Vendor ID
562 0x593d, // Device ID
563 },
564 //
565 // Option Rom for
566 //
567 {
568 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
569 0x0, // Segment
570 0x0, // Bus Number
571 0x2, // Device Number
572 0x0, // Function Number
573 0x8086, // Vendor ID
574 0x2a42, // Device ID
575 },
576 //
577 // Option Rom for
578 //
579 {
580 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
581 0x0, // Segment
582 0x0, // Bus Number
583 0x2, // Device Number
584 0x0, // Function Number
585 0x8086, // Vendor ID
586 0x106, // Device ID
587 },
588 //
589 // Option Rom for
590 //
591 {
592 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
593 0x0, // Segment
594 0x0, // Bus Number
595 0x2, // Device Number
596 0x0, // Function Number
597 0x8086, // Vendor ID
598 0x116, // Device ID
599 },
600 //
601 // Option Rom for
602 //
603 {
604 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
605 0x0, // Segment
606 0x0, // Bus Number
607 0x2, // Device Number
608 0x0, // Function Number
609 0x8086, // Vendor ID
610 0x126, // Device ID
611 },
612 //
613 // Option Rom for
614 //
615 {
616 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
617 0x0, // Segment
618 0x0, // Bus Number
619 0x2, // Device Number
620 0x0, // Function Number
621 0x8086, // Vendor ID
622 0xa02, // Device ID
623 },
624 //
625 // Option Rom for
626 //
627 {
628 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
629 0x0, // Segment
630 0x0, // Bus Number
631 0x2, // Device Number
632 0x0, // Function Number
633 0x8086, // Vendor ID
634 0x102, // Device ID
635 },
636 //
637 // Option Rom for
638 //
639 {
640 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
641 0x0, // Segment
642 0x0, // Bus Number
643 0x2, // Device Number
644 0x0, // Function Number
645 0x8086, // Vendor ID
646 0x112, // Device ID
647 },
648 //
649 // Option Rom for
650 //
651 {
652 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
653 0x0, // Segment
654 0x0, // Bus Number
655 0x2, // Device Number
656 0x0, // Function Number
657 0x8086, // Vendor ID
658 0x122, // Device ID
659 },
660 //
661 // Option Rom for
662 //
663 {
664 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
665 0x0, // Segment
666 0x0, // Bus Number
667 0x2, // Device Number
668 0x0, // Function Number
669 0x8086, // Vendor ID
670 0x10a, // Device ID
671 },
672 //
673 // Option Rom for
674 //
675 {
676 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
677 0x0, // Segment
678 0x0, // Bus Number
679 0x2, // Device Number
680 0x0, // Function Number
681 0x8086, // Vendor ID
682 0x5a51, // Device ID
683 },
684 //
685 // Option Rom for
686 //
687 {
688 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
689 0x0, // Segment
690 0x0, // Bus Number
691 0x2, // Device Number
692 0x0, // Function Number
693 0x8086, // Vendor ID
694 0x5a52, // Device ID
695 },
696 //
697 // Option Rom for
698 //
699 {
700 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
701 0x0, // Segment
702 0x0, // Bus Number
703 0x2, // Device Number
704 0x0, // Function Number
705 0x8086, // Vendor ID
706 0x5a5a, // Device ID
707 },
708 //
709 // Option Rom for
710 //
711 {
712 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
713 0x0, // Segment
714 0x0, // Bus Number
715 0x2, // Device Number
716 0x0, // Function Number
717 0x8086, // Vendor ID
718 0x5a42, // Device ID
719 },
720 //
721 // Option Rom for
722 //
723 {
724 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
725 0x0, // Segment
726 0x0, // Bus Number
727 0x2, // Device Number
728 0x0, // Function Number
729 0x8086, // Vendor ID
730 0x5a4a, // Device ID
731 },
732 //
733 // Option Rom for
734 //
735 {
736 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
737 0x0, // Segment
738 0x0, // Bus Number
739 0x2, // Device Number
740 0x0, // Function Number
741 0x8086, // Vendor ID
742 0x5a62, // Device ID
743 },
744 //
745 // Option Rom for
746 //
747 {
748 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
749 0x0, // Segment
750 0x0, // Bus Number
751 0x2, // Device Number
752 0x0, // Function Number
753 0x8086, // Vendor ID
754 0x5a54, // Device ID
755 },
756 //
757 // Option Rom for
758 //
759 {
760 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
761 0x0, // Segment
762 0x0, // Bus Number
763 0x2, // Device Number
764 0x0, // Function Number
765 0x8086, // Vendor ID
766 0x5a44, // Device ID
767 },
768 //
769 // Option Rom for
770 //
771 {
772 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
773 0x0, // Segment
774 0x0, // Bus Number
775 0x2, // Device Number
776 0x0, // Function Number
777 0x8086, // Vendor ID
778 0x5a55, // Device ID
779 },
780 //
781 // Option Rom for
782 //
783 {
784 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
785 0x0, // Segment
786 0x0, // Bus Number
787 0x2, // Device Number
788 0x0, // Function Number
789 0x8086, // Vendor ID
790 0x5a45, // Device ID
791 },
792 //
793 // Option Rom for
794 //
795 {
796 RAID_OPTION_ROM_FILE_GUID, // Guid
797 0x0, // Segment
798 0x0, // Bus Number
799 0x17, // Device Number
800 0x0, // Function Number
801 0x8086, // Vendor ID
802 0x282a, // Device ID
803 },
804 //
805 // Option Rom for
806 //
807 {
808 RAID_OPTION_ROM_FILE_GUID, // Guid
809 0x0, // Segment
810 0x0, // Bus Number
811 0x17, // Device Number
812 0x0, // Function Number
813 0x8086, // Vendor ID
814 0x2822, // Device ID
815 },
816 //
817 // Option Rom for
818 //
819 {
820 RSTE_OPTION_ROM_FILE_GUID, // Guid
821 0x0, // Segment
822 0x0, // Bus Number
823 0x17, // Device Number
824 0x0, // Function Number
825 0x8086, // Vendor ID
826 0x2826, // Device ID
827 },
828 //
829 // Option Rom for
830 //
831 {
832 PXE_OPTION_ROM_FILE_GUID, // Guid
833 0x0, // Segment
834 0x0, // Bus Number
835 0x1f, // Device Number
836 0x6, // Function Number
837 0xffff, // Vendor ID
838 0xffff, // Device ID
839 },
840 //
841 // End of OptionRom Entries
842 //
843 {
844 NULL_ROM_FILE_GUID, // Guid
845 0, // Segment
846 0, // Bus Number
847 0, // Device Number
848 0, // Function Number
849 0xffff, // Vendor ID
850 0xffff, // Device ID
851 }
852 };
853
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformOptionRomTable_RvpDt.h Source File

  • MultiPlatform
PlatformOptionRomTable_RvpDt.h
1 /*++
2 Copyright (c) 2005 - 2007 Intel Corporation. All rights reserved
3 This software and associated documentation (if any) is furnished
4 under a license and may only be used or copied in accordance
5 with the terms of the license. Except as permitted by such
6 license, no part of this software or documentation may be
7 reproduced, stored in a retrieval system, or transmitted in any
8 form or by any means without the express written consent of
9 Intel Corporation.
10
11 Module Name:
12
13 PlatformOptionRomTable_RvpDt.h
14
15 --*/
16
17 //
18 // Automatically generated by ACE ver 1.63 PIRQTRANS
19 // Please DO NOT modify !!!
20 //
21
22
23 PCI_OPTION_ROM_TABLE mPciOptionRomTable_RvpDt[] = {
24 //
25 // Option Rom for
26 //
27 {
28 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
29 0x0, // Segment
30 0x0, // Bus Number
31 0x2, // Device Number
32 0x0, // Function Number
33 0x8086, // Vendor ID
34 0x1906, // Device ID
35 },
36 //
37 // Option Rom for
38 //
39 {
40 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
41 0x0, // Segment
42 0x0, // Bus Number
43 0x2, // Device Number
44 0x0, // Function Number
45 0x8086, // Vendor ID
46 0x1913, // Device ID
47 },
48 //
49 // Option Rom for
50 //
51 {
52 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
53 0x0, // Segment
54 0x0, // Bus Number
55 0x2, // Device Number
56 0x0, // Function Number
57 0x8086, // Vendor ID
58 0x1916, // Device ID
59 },
60 //
61 // Option Rom for
62 //
63 {
64 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
65 0x0, // Segment
66 0x0, // Bus Number
67 0x2, // Device Number
68 0x0, // Function Number
69 0x8086, // Vendor ID
70 0x1921, // Device ID
71 },
72 //
73 // Option Rom for
74 //
75 {
76 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
77 0x0, // Segment
78 0x0, // Bus Number
79 0x2, // Device Number
80 0x0, // Function Number
81 0x8086, // Vendor ID
82 0x1926, // Device ID
83 },
84 //
85 // Option Rom for
86 //
87 {
88 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
89 0x0, // Segment
90 0x0, // Bus Number
91 0x2, // Device Number
92 0x0, // Function Number
93 0x8086, // Vendor ID
94 0x190b, // Device ID
95 },
96 //
97 // Option Rom for
98 //
99 {
100 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
101 0x0, // Segment
102 0x0, // Bus Number
103 0x2, // Device Number
104 0x0, // Function Number
105 0x8086, // Vendor ID
106 0x191b, // Device ID
107 },
108 //
109 // Option Rom for
110 //
111 {
112 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
113 0x0, // Segment
114 0x0, // Bus Number
115 0x2, // Device Number
116 0x0, // Function Number
117 0x8086, // Vendor ID
118 0x192b, // Device ID
119 },
120 //
121 // Option Rom for
122 //
123 {
124 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
125 0x0, // Segment
126 0x0, // Bus Number
127 0x2, // Device Number
128 0x0, // Function Number
129 0x8086, // Vendor ID
130 0x193b, // Device ID
131 },
132 //
133 // Option Rom for
134 //
135 {
136 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
137 0x0, // Segment
138 0x0, // Bus Number
139 0x2, // Device Number
140 0x0, // Function Number
141 0x8086, // Vendor ID
142 0x192d, // Device ID
143 },
144 //
145 // Option Rom for
146 //
147 {
148 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
149 0x0, // Segment
150 0x0, // Bus Number
151 0x2, // Device Number
152 0x0, // Function Number
153 0x8086, // Vendor ID
154 0x193d, // Device ID
155 },
156 //
157 // Option Rom for
158 //
159 {
160 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
161 0x0, // Segment
162 0x0, // Bus Number
163 0x2, // Device Number
164 0x0, // Function Number
165 0x8086, // Vendor ID
166 0x190e, // Device ID
167 },
168 //
169 // Option Rom for
170 //
171 {
172 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
173 0x0, // Segment
174 0x0, // Bus Number
175 0x2, // Device Number
176 0x0, // Function Number
177 0x8086, // Vendor ID
178 0x1915, // Device ID
179 },
180 //
181 // Option Rom for
182 //
183 {
184 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
185 0x0, // Segment
186 0x0, // Bus Number
187 0x2, // Device Number
188 0x0, // Function Number
189 0x8086, // Vendor ID
190 0x191e, // Device ID
191 },
192 //
193 // Option Rom for
194 //
195 {
196 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
197 0x0, // Segment
198 0x0, // Bus Number
199 0x2, // Device Number
200 0x0, // Function Number
201 0x8086, // Vendor ID
202 0x190a, // Device ID
203 },
204 //
205 // Option Rom for
206 //
207 {
208 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
209 0x0, // Segment
210 0x0, // Bus Number
211 0x2, // Device Number
212 0x0, // Function Number
213 0x8086, // Vendor ID
214 0x191a, // Device ID
215 },
216 //
217 // Option Rom for
218 //
219 {
220 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
221 0x0, // Segment
222 0x0, // Bus Number
223 0x2, // Device Number
224 0x0, // Function Number
225 0x8086, // Vendor ID
226 0x192a, // Device ID
227 },
228 //
229 // Option Rom for
230 //
231 {
232 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
233 0x0, // Segment
234 0x0, // Bus Number
235 0x2, // Device Number
236 0x0, // Function Number
237 0x8086, // Vendor ID
238 0x193a, // Device ID
239 },
240 //
241 // Option Rom for
242 //
243 {
244 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
245 0x0, // Segment
246 0x0, // Bus Number
247 0x2, // Device Number
248 0x0, // Function Number
249 0x8086, // Vendor ID
250 0x1902, // Device ID
251 },
252 //
253 // Option Rom for
254 //
255 {
256 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
257 0x0, // Segment
258 0x0, // Bus Number
259 0x2, // Device Number
260 0x0, // Function Number
261 0x8086, // Vendor ID
262 0x1912, // Device ID
263 },
264 //
265 // Option Rom for
266 //
267 {
268 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
269 0x0, // Segment
270 0x0, // Bus Number
271 0x2, // Device Number
272 0x0, // Function Number
273 0x8086, // Vendor ID
274 0x1917, // Device ID
275 },
276 //
277 // Option Rom for
278 //
279 {
280 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
281 0x0, // Segment
282 0x0, // Bus Number
283 0x2, // Device Number
284 0x0, // Function Number
285 0x8086, // Vendor ID
286 0x1932, // Device ID
287 },
288 //
289 // Option Rom for
290 //
291 {
292 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
293 0x0, // Segment
294 0x0, // Bus Number
295 0x2, // Device Number
296 0x0, // Function Number
297 0x8086, // Vendor ID
298 0x191d, // Device ID
299 },
300 //
301 // Option Rom for
302 //
303 {
304 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
305 0x0, // Segment
306 0x0, // Bus Number
307 0x2, // Device Number
308 0x0, // Function Number
309 0x8086, // Vendor ID
310 0x5906, // Device ID
311 },
312 //
313 // Option Rom for
314 //
315 {
316 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
317 0x0, // Segment
318 0x0, // Bus Number
319 0x2, // Device Number
320 0x0, // Function Number
321 0x8086, // Vendor ID
322 0x5913, // Device ID
323 },
324 //
325 // Option Rom for
326 //
327 {
328 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
329 0x0, // Segment
330 0x0, // Bus Number
331 0x2, // Device Number
332 0x0, // Function Number
333 0x8086, // Vendor ID
334 0x5916, // Device ID
335 },
336 //
337 // Option Rom for
338 //
339 {
340 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
341 0x0, // Segment
342 0x0, // Bus Number
343 0x2, // Device Number
344 0x0, // Function Number
345 0x8086, // Vendor ID
346 0x5921, // Device ID
347 },
348 //
349 // Option Rom for
350 //
351 {
352 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
353 0x0, // Segment
354 0x0, // Bus Number
355 0x2, // Device Number
356 0x0, // Function Number
357 0x8086, // Vendor ID
358 0x5926, // Device ID
359 },
360 //
361 // Option Rom for
362 //
363 {
364 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
365 0x0, // Segment
366 0x0, // Bus Number
367 0x2, // Device Number
368 0x0, // Function Number
369 0x8086, // Vendor ID
370 0x590b, // Device ID
371 },
372 //
373 // Option Rom for
374 //
375 {
376 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
377 0x0, // Segment
378 0x0, // Bus Number
379 0x2, // Device Number
380 0x0, // Function Number
381 0x8086, // Vendor ID
382 0x591b, // Device ID
383 },
384 //
385 // Option Rom for
386 //
387 {
388 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
389 0x0, // Segment
390 0x0, // Bus Number
391 0x2, // Device Number
392 0x0, // Function Number
393 0x8086, // Vendor ID
394 0x592b, // Device ID
395 },
396 //
397 // Option Rom for
398 //
399 {
400 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
401 0x0, // Segment
402 0x0, // Bus Number
403 0x2, // Device Number
404 0x0, // Function Number
405 0x8086, // Vendor ID
406 0x593b, // Device ID
407 },
408 //
409 // Option Rom for
410 //
411 {
412 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
413 0x0, // Segment
414 0x0, // Bus Number
415 0x2, // Device Number
416 0x0, // Function Number
417 0x8086, // Vendor ID
418 0x590e, // Device ID
419 },
420 //
421 // Option Rom for
422 //
423 {
424 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
425 0x0, // Segment
426 0x0, // Bus Number
427 0x2, // Device Number
428 0x0, // Function Number
429 0x8086, // Vendor ID
430 0x5915, // Device ID
431 },
432 //
433 // Option Rom for
434 //
435 {
436 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
437 0x0, // Segment
438 0x0, // Bus Number
439 0x2, // Device Number
440 0x0, // Function Number
441 0x8086, // Vendor ID
442 0x591e, // Device ID
443 },
444 //
445 // Option Rom for
446 //
447 {
448 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
449 0x0, // Segment
450 0x0, // Bus Number
451 0x2, // Device Number
452 0x0, // Function Number
453 0x8086, // Vendor ID
454 0x590a, // Device ID
455 },
456 //
457 // Option Rom for
458 //
459 {
460 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
461 0x0, // Segment
462 0x0, // Bus Number
463 0x2, // Device Number
464 0x0, // Function Number
465 0x8086, // Vendor ID
466 0x591a, // Device ID
467 },
468 //
469 // Option Rom for
470 //
471 {
472 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
473 0x0, // Segment
474 0x0, // Bus Number
475 0x2, // Device Number
476 0x0, // Function Number
477 0x8086, // Vendor ID
478 0x592a, // Device ID
479 },
480 //
481 // Option Rom for
482 //
483 {
484 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
485 0x0, // Segment
486 0x0, // Bus Number
487 0x2, // Device Number
488 0x0, // Function Number
489 0x8086, // Vendor ID
490 0x593a, // Device ID
491 },
492 //
493 // Option Rom for
494 //
495 {
496 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
497 0x0, // Segment
498 0x0, // Bus Number
499 0x2, // Device Number
500 0x0, // Function Number
501 0x8086, // Vendor ID
502 0x5902, // Device ID
503 },
504 //
505 // Option Rom for
506 //
507 {
508 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
509 0x0, // Segment
510 0x0, // Bus Number
511 0x2, // Device Number
512 0x0, // Function Number
513 0x8086, // Vendor ID
514 0x5912, // Device ID
515 },
516 //
517 // Option Rom for
518 //
519 {
520 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
521 0x0, // Segment
522 0x0, // Bus Number
523 0x2, // Device Number
524 0x0, // Function Number
525 0x8086, // Vendor ID
526 0x5917, // Device ID
527 },
528 //
529 // Option Rom for
530 //
531 {
532 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
533 0x0, // Segment
534 0x0, // Bus Number
535 0x2, // Device Number
536 0x0, // Function Number
537 0x8086, // Vendor ID
538 0x5932, // Device ID
539 },
540 //
541 // Option Rom for
542 //
543 {
544 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
545 0x0, // Segment
546 0x0, // Bus Number
547 0x2, // Device Number
548 0x0, // Function Number
549 0x8086, // Vendor ID
550 0x591d, // Device ID
551 },
552 //
553 // Option Rom for
554 //
555 {
556 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
557 0x0, // Segment
558 0x0, // Bus Number
559 0x2, // Device Number
560 0x0, // Function Number
561 0x8086, // Vendor ID
562 0x593d, // Device ID
563 },
564 //
565 // Option Rom for
566 //
567 {
568 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
569 0x0, // Segment
570 0x0, // Bus Number
571 0x2, // Device Number
572 0x0, // Function Number
573 0x8086, // Vendor ID
574 0x2a42, // Device ID
575 },
576 //
577 // Option Rom for
578 //
579 {
580 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
581 0x0, // Segment
582 0x0, // Bus Number
583 0x2, // Device Number
584 0x0, // Function Number
585 0x8086, // Vendor ID
586 0x106, // Device ID
587 },
588 //
589 // Option Rom for
590 //
591 {
592 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
593 0x0, // Segment
594 0x0, // Bus Number
595 0x2, // Device Number
596 0x0, // Function Number
597 0x8086, // Vendor ID
598 0x116, // Device ID
599 },
600 //
601 // Option Rom for
602 //
603 {
604 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
605 0x0, // Segment
606 0x0, // Bus Number
607 0x2, // Device Number
608 0x0, // Function Number
609 0x8086, // Vendor ID
610 0x126, // Device ID
611 },
612 //
613 // Option Rom for
614 //
615 {
616 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
617 0x0, // Segment
618 0x0, // Bus Number
619 0x2, // Device Number
620 0x0, // Function Number
621 0x8086, // Vendor ID
622 0xa02, // Device ID
623 },
624 //
625 // Option Rom for
626 //
627 {
628 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
629 0x0, // Segment
630 0x0, // Bus Number
631 0x2, // Device Number
632 0x0, // Function Number
633 0x8086, // Vendor ID
634 0x102, // Device ID
635 },
636 //
637 // Option Rom for
638 //
639 {
640 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
641 0x0, // Segment
642 0x0, // Bus Number
643 0x2, // Device Number
644 0x0, // Function Number
645 0x8086, // Vendor ID
646 0x112, // Device ID
647 },
648 //
649 // Option Rom for
650 //
651 {
652 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
653 0x0, // Segment
654 0x0, // Bus Number
655 0x2, // Device Number
656 0x0, // Function Number
657 0x8086, // Vendor ID
658 0x122, // Device ID
659 },
660 //
661 // Option Rom for
662 //
663 {
664 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
665 0x0, // Segment
666 0x0, // Bus Number
667 0x2, // Device Number
668 0x0, // Function Number
669 0x8086, // Vendor ID
670 0x10a, // Device ID
671 },
672 //
673 // Option Rom for
674 //
675 {
676 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
677 0x0, // Segment
678 0x0, // Bus Number
679 0x2, // Device Number
680 0x0, // Function Number
681 0x8086, // Vendor ID
682 0x5a51, // Device ID
683 },
684 //
685 // Option Rom for
686 //
687 {
688 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
689 0x0, // Segment
690 0x0, // Bus Number
691 0x2, // Device Number
692 0x0, // Function Number
693 0x8086, // Vendor ID
694 0x5a52, // Device ID
695 },
696 //
697 // Option Rom for
698 //
699 {
700 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
701 0x0, // Segment
702 0x0, // Bus Number
703 0x2, // Device Number
704 0x0, // Function Number
705 0x8086, // Vendor ID
706 0x5a5a, // Device ID
707 },
708 //
709 // Option Rom for
710 //
711 {
712 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
713 0x0, // Segment
714 0x0, // Bus Number
715 0x2, // Device Number
716 0x0, // Function Number
717 0x8086, // Vendor ID
718 0x5a42, // Device ID
719 },
720 //
721 // Option Rom for
722 //
723 {
724 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
725 0x0, // Segment
726 0x0, // Bus Number
727 0x2, // Device Number
728 0x0, // Function Number
729 0x8086, // Vendor ID
730 0x5a4a, // Device ID
731 },
732 //
733 // Option Rom for
734 //
735 {
736 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
737 0x0, // Segment
738 0x0, // Bus Number
739 0x2, // Device Number
740 0x0, // Function Number
741 0x8086, // Vendor ID
742 0x5a62, // Device ID
743 },
744 //
745 // Option Rom for
746 //
747 {
748 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
749 0x0, // Segment
750 0x0, // Bus Number
751 0x2, // Device Number
752 0x0, // Function Number
753 0x8086, // Vendor ID
754 0x5a54, // Device ID
755 },
756 //
757 // Option Rom for
758 //
759 {
760 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
761 0x0, // Segment
762 0x0, // Bus Number
763 0x2, // Device Number
764 0x0, // Function Number
765 0x8086, // Vendor ID
766 0x5a44, // Device ID
767 },
768 //
769 // Option Rom for
770 //
771 {
772 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
773 0x0, // Segment
774 0x0, // Bus Number
775 0x2, // Device Number
776 0x0, // Function Number
777 0x8086, // Vendor ID
778 0x5a55, // Device ID
779 },
780 //
781 // Option Rom for
782 //
783 {
784 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
785 0x0, // Segment
786 0x0, // Bus Number
787 0x2, // Device Number
788 0x0, // Function Number
789 0x8086, // Vendor ID
790 0x5a45, // Device ID
791 },
792 //
793 // Option Rom for
794 //
795 {
796 RAID_OPTION_ROM_FILE_GUID, // Guid
797 0x0, // Segment
798 0x0, // Bus Number
799 0x17, // Device Number
800 0x0, // Function Number
801 0x8086, // Vendor ID
802 0x282a, // Device ID
803 },
804 //
805 // Option Rom for
806 //
807 {
808 RAID_OPTION_ROM_FILE_GUID, // Guid
809 0x0, // Segment
810 0x0, // Bus Number
811 0x17, // Device Number
812 0x0, // Function Number
813 0x8086, // Vendor ID
814 0x2822, // Device ID
815 },
816 //
817 // Option Rom for
818 //
819 {
820 RSTE_OPTION_ROM_FILE_GUID, // Guid
821 0x0, // Segment
822 0x0, // Bus Number
823 0x17, // Device Number
824 0x0, // Function Number
825 0x8086, // Vendor ID
826 0x2826, // Device ID
827 },
828 //
829 // Option Rom for
830 //
831 {
832 PXE_OPTION_ROM_FILE_GUID, // Guid
833 0x0, // Segment
834 0x0, // Bus Number
835 0x1f, // Device Number
836 0x6, // Function Number
837 0xffff, // Vendor ID
838 0xffff, // Device ID
839 },
840 //
841 // End of OptionRom Entries
842 //
843 {
844 NULL_ROM_FILE_GUID, // Guid
845 0, // Segment
846 0, // Bus Number
847 0, // Device Number
848 0, // Function Number
849 0xffff, // Vendor ID
850 0xffff, // Device ID
851 }
852 };
853
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformOptionRomTable_RvpM.h Source File

  • MultiPlatform
PlatformOptionRomTable_RvpM.h
1 /*++
2 Copyright (c) 2005 - 2007 Intel Corporation. All rights reserved
3 This software and associated documentation (if any) is furnished
4 under a license and may only be used or copied in accordance
5 with the terms of the license. Except as permitted by such
6 license, no part of this software or documentation may be
7 reproduced, stored in a retrieval system, or transmitted in any
8 form or by any means without the express written consent of
9 Intel Corporation.
10
11 Module Name:
12
13 PlatformOptionRomTable_RvpM.h
14
15 --*/
16
17 //
18 // Automatically generated by ACE ver 1.63 PIRQTRANS
19 // Please DO NOT modify !!!
20 //
21
22
23 PCI_OPTION_ROM_TABLE mPciOptionRomTable_RvpM[] = {
24 //
25 // Option Rom for
26 //
27 {
28 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
29 0x0, // Segment
30 0x0, // Bus Number
31 0x2, // Device Number
32 0x0, // Function Number
33 0x8086, // Vendor ID
34 0x1906, // Device ID
35 },
36 //
37 // Option Rom for
38 //
39 {
40 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
41 0x0, // Segment
42 0x0, // Bus Number
43 0x2, // Device Number
44 0x0, // Function Number
45 0x8086, // Vendor ID
46 0x1913, // Device ID
47 },
48 //
49 // Option Rom for
50 //
51 {
52 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
53 0x0, // Segment
54 0x0, // Bus Number
55 0x2, // Device Number
56 0x0, // Function Number
57 0x8086, // Vendor ID
58 0x1916, // Device ID
59 },
60 //
61 // Option Rom for
62 //
63 {
64 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
65 0x0, // Segment
66 0x0, // Bus Number
67 0x2, // Device Number
68 0x0, // Function Number
69 0x8086, // Vendor ID
70 0x1921, // Device ID
71 },
72 //
73 // Option Rom for
74 //
75 {
76 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
77 0x0, // Segment
78 0x0, // Bus Number
79 0x2, // Device Number
80 0x0, // Function Number
81 0x8086, // Vendor ID
82 0x1926, // Device ID
83 },
84 //
85 // Option Rom for
86 //
87 {
88 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
89 0x0, // Segment
90 0x0, // Bus Number
91 0x2, // Device Number
92 0x0, // Function Number
93 0x8086, // Vendor ID
94 0x190b, // Device ID
95 },
96 //
97 // Option Rom for
98 //
99 {
100 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
101 0x0, // Segment
102 0x0, // Bus Number
103 0x2, // Device Number
104 0x0, // Function Number
105 0x8086, // Vendor ID
106 0x191b, // Device ID
107 },
108 //
109 // Option Rom for
110 //
111 {
112 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
113 0x0, // Segment
114 0x0, // Bus Number
115 0x2, // Device Number
116 0x0, // Function Number
117 0x8086, // Vendor ID
118 0x192b, // Device ID
119 },
120 //
121 // Option Rom for
122 //
123 {
124 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
125 0x0, // Segment
126 0x0, // Bus Number
127 0x2, // Device Number
128 0x0, // Function Number
129 0x8086, // Vendor ID
130 0x193b, // Device ID
131 },
132 //
133 // Option Rom for
134 //
135 {
136 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
137 0x0, // Segment
138 0x0, // Bus Number
139 0x2, // Device Number
140 0x0, // Function Number
141 0x8086, // Vendor ID
142 0x192d, // Device ID
143 },
144 //
145 // Option Rom for
146 //
147 {
148 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
149 0x0, // Segment
150 0x0, // Bus Number
151 0x2, // Device Number
152 0x0, // Function Number
153 0x8086, // Vendor ID
154 0x193d, // Device ID
155 },
156 //
157 // Option Rom for
158 //
159 {
160 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
161 0x0, // Segment
162 0x0, // Bus Number
163 0x2, // Device Number
164 0x0, // Function Number
165 0x8086, // Vendor ID
166 0x190e, // Device ID
167 },
168 //
169 // Option Rom for
170 //
171 {
172 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
173 0x0, // Segment
174 0x0, // Bus Number
175 0x2, // Device Number
176 0x0, // Function Number
177 0x8086, // Vendor ID
178 0x1915, // Device ID
179 },
180 //
181 // Option Rom for
182 //
183 {
184 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
185 0x0, // Segment
186 0x0, // Bus Number
187 0x2, // Device Number
188 0x0, // Function Number
189 0x8086, // Vendor ID
190 0x191e, // Device ID
191 },
192 //
193 // Option Rom for
194 //
195 {
196 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
197 0x0, // Segment
198 0x0, // Bus Number
199 0x2, // Device Number
200 0x0, // Function Number
201 0x8086, // Vendor ID
202 0x190a, // Device ID
203 },
204 //
205 // Option Rom for
206 //
207 {
208 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
209 0x0, // Segment
210 0x0, // Bus Number
211 0x2, // Device Number
212 0x0, // Function Number
213 0x8086, // Vendor ID
214 0x191a, // Device ID
215 },
216 //
217 // Option Rom for
218 //
219 {
220 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
221 0x0, // Segment
222 0x0, // Bus Number
223 0x2, // Device Number
224 0x0, // Function Number
225 0x8086, // Vendor ID
226 0x192a, // Device ID
227 },
228 //
229 // Option Rom for
230 //
231 {
232 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
233 0x0, // Segment
234 0x0, // Bus Number
235 0x2, // Device Number
236 0x0, // Function Number
237 0x8086, // Vendor ID
238 0x193a, // Device ID
239 },
240 //
241 // Option Rom for
242 //
243 {
244 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
245 0x0, // Segment
246 0x0, // Bus Number
247 0x2, // Device Number
248 0x0, // Function Number
249 0x8086, // Vendor ID
250 0x1902, // Device ID
251 },
252 //
253 // Option Rom for
254 //
255 {
256 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
257 0x0, // Segment
258 0x0, // Bus Number
259 0x2, // Device Number
260 0x0, // Function Number
261 0x8086, // Vendor ID
262 0x1912, // Device ID
263 },
264 //
265 // Option Rom for
266 //
267 {
268 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
269 0x0, // Segment
270 0x0, // Bus Number
271 0x2, // Device Number
272 0x0, // Function Number
273 0x8086, // Vendor ID
274 0x1917, // Device ID
275 },
276 //
277 // Option Rom for
278 //
279 {
280 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
281 0x0, // Segment
282 0x0, // Bus Number
283 0x2, // Device Number
284 0x0, // Function Number
285 0x8086, // Vendor ID
286 0x1932, // Device ID
287 },
288 //
289 // Option Rom for
290 //
291 {
292 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
293 0x0, // Segment
294 0x0, // Bus Number
295 0x2, // Device Number
296 0x0, // Function Number
297 0x8086, // Vendor ID
298 0x191d, // Device ID
299 },
300 //
301 // Option Rom for
302 //
303 {
304 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
305 0x0, // Segment
306 0x0, // Bus Number
307 0x2, // Device Number
308 0x0, // Function Number
309 0x8086, // Vendor ID
310 0x5906, // Device ID
311 },
312 //
313 // Option Rom for
314 //
315 {
316 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
317 0x0, // Segment
318 0x0, // Bus Number
319 0x2, // Device Number
320 0x0, // Function Number
321 0x8086, // Vendor ID
322 0x5913, // Device ID
323 },
324 //
325 // Option Rom for
326 //
327 {
328 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
329 0x0, // Segment
330 0x0, // Bus Number
331 0x2, // Device Number
332 0x0, // Function Number
333 0x8086, // Vendor ID
334 0x5916, // Device ID
335 },
336 //
337 // Option Rom for
338 //
339 {
340 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
341 0x0, // Segment
342 0x0, // Bus Number
343 0x2, // Device Number
344 0x0, // Function Number
345 0x8086, // Vendor ID
346 0x5921, // Device ID
347 },
348 //
349 // Option Rom for
350 //
351 {
352 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
353 0x0, // Segment
354 0x0, // Bus Number
355 0x2, // Device Number
356 0x0, // Function Number
357 0x8086, // Vendor ID
358 0x5926, // Device ID
359 },
360 //
361 // Option Rom for
362 //
363 {
364 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
365 0x0, // Segment
366 0x0, // Bus Number
367 0x2, // Device Number
368 0x0, // Function Number
369 0x8086, // Vendor ID
370 0x590b, // Device ID
371 },
372 //
373 // Option Rom for
374 //
375 {
376 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
377 0x0, // Segment
378 0x0, // Bus Number
379 0x2, // Device Number
380 0x0, // Function Number
381 0x8086, // Vendor ID
382 0x591b, // Device ID
383 },
384 //
385 // Option Rom for
386 //
387 {
388 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
389 0x0, // Segment
390 0x0, // Bus Number
391 0x2, // Device Number
392 0x0, // Function Number
393 0x8086, // Vendor ID
394 0x592b, // Device ID
395 },
396 //
397 // Option Rom for
398 //
399 {
400 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
401 0x0, // Segment
402 0x0, // Bus Number
403 0x2, // Device Number
404 0x0, // Function Number
405 0x8086, // Vendor ID
406 0x593b, // Device ID
407 },
408 //
409 // Option Rom for
410 //
411 {
412 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
413 0x0, // Segment
414 0x0, // Bus Number
415 0x2, // Device Number
416 0x0, // Function Number
417 0x8086, // Vendor ID
418 0x590e, // Device ID
419 },
420 //
421 // Option Rom for
422 //
423 {
424 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
425 0x0, // Segment
426 0x0, // Bus Number
427 0x2, // Device Number
428 0x0, // Function Number
429 0x8086, // Vendor ID
430 0x5915, // Device ID
431 },
432 //
433 // Option Rom for
434 //
435 {
436 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
437 0x0, // Segment
438 0x0, // Bus Number
439 0x2, // Device Number
440 0x0, // Function Number
441 0x8086, // Vendor ID
442 0x591e, // Device ID
443 },
444 //
445 // Option Rom for
446 //
447 {
448 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
449 0x0, // Segment
450 0x0, // Bus Number
451 0x2, // Device Number
452 0x0, // Function Number
453 0x8086, // Vendor ID
454 0x590a, // Device ID
455 },
456 //
457 // Option Rom for
458 //
459 {
460 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
461 0x0, // Segment
462 0x0, // Bus Number
463 0x2, // Device Number
464 0x0, // Function Number
465 0x8086, // Vendor ID
466 0x591a, // Device ID
467 },
468 //
469 // Option Rom for
470 //
471 {
472 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
473 0x0, // Segment
474 0x0, // Bus Number
475 0x2, // Device Number
476 0x0, // Function Number
477 0x8086, // Vendor ID
478 0x592a, // Device ID
479 },
480 //
481 // Option Rom for
482 //
483 {
484 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
485 0x0, // Segment
486 0x0, // Bus Number
487 0x2, // Device Number
488 0x0, // Function Number
489 0x8086, // Vendor ID
490 0x593a, // Device ID
491 },
492 //
493 // Option Rom for
494 //
495 {
496 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
497 0x0, // Segment
498 0x0, // Bus Number
499 0x2, // Device Number
500 0x0, // Function Number
501 0x8086, // Vendor ID
502 0x5902, // Device ID
503 },
504 //
505 // Option Rom for
506 //
507 {
508 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
509 0x0, // Segment
510 0x0, // Bus Number
511 0x2, // Device Number
512 0x0, // Function Number
513 0x8086, // Vendor ID
514 0x5912, // Device ID
515 },
516 //
517 // Option Rom for
518 //
519 {
520 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
521 0x0, // Segment
522 0x0, // Bus Number
523 0x2, // Device Number
524 0x0, // Function Number
525 0x8086, // Vendor ID
526 0x5917, // Device ID
527 },
528 //
529 // Option Rom for
530 //
531 {
532 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
533 0x0, // Segment
534 0x0, // Bus Number
535 0x2, // Device Number
536 0x0, // Function Number
537 0x8086, // Vendor ID
538 0x5932, // Device ID
539 },
540 //
541 // Option Rom for
542 //
543 {
544 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
545 0x0, // Segment
546 0x0, // Bus Number
547 0x2, // Device Number
548 0x0, // Function Number
549 0x8086, // Vendor ID
550 0x591d, // Device ID
551 },
552 //
553 // Option Rom for
554 //
555 {
556 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
557 0x0, // Segment
558 0x0, // Bus Number
559 0x2, // Device Number
560 0x0, // Function Number
561 0x8086, // Vendor ID
562 0x593d, // Device ID
563 },
564 //
565 // Option Rom for
566 //
567 {
568 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
569 0x0, // Segment
570 0x0, // Bus Number
571 0x2, // Device Number
572 0x0, // Function Number
573 0x8086, // Vendor ID
574 0x2a42, // Device ID
575 },
576 //
577 // Option Rom for
578 //
579 {
580 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
581 0x0, // Segment
582 0x0, // Bus Number
583 0x2, // Device Number
584 0x0, // Function Number
585 0x8086, // Vendor ID
586 0x106, // Device ID
587 },
588 //
589 // Option Rom for
590 //
591 {
592 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
593 0x0, // Segment
594 0x0, // Bus Number
595 0x2, // Device Number
596 0x0, // Function Number
597 0x8086, // Vendor ID
598 0x116, // Device ID
599 },
600 //
601 // Option Rom for
602 //
603 {
604 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
605 0x0, // Segment
606 0x0, // Bus Number
607 0x2, // Device Number
608 0x0, // Function Number
609 0x8086, // Vendor ID
610 0x126, // Device ID
611 },
612 //
613 // Option Rom for
614 //
615 {
616 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
617 0x0, // Segment
618 0x0, // Bus Number
619 0x2, // Device Number
620 0x0, // Function Number
621 0x8086, // Vendor ID
622 0xa02, // Device ID
623 },
624 //
625 // Option Rom for
626 //
627 {
628 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
629 0x0, // Segment
630 0x0, // Bus Number
631 0x2, // Device Number
632 0x0, // Function Number
633 0x8086, // Vendor ID
634 0x102, // Device ID
635 },
636 //
637 // Option Rom for
638 //
639 {
640 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
641 0x0, // Segment
642 0x0, // Bus Number
643 0x2, // Device Number
644 0x0, // Function Number
645 0x8086, // Vendor ID
646 0x112, // Device ID
647 },
648 //
649 // Option Rom for
650 //
651 {
652 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
653 0x0, // Segment
654 0x0, // Bus Number
655 0x2, // Device Number
656 0x0, // Function Number
657 0x8086, // Vendor ID
658 0x122, // Device ID
659 },
660 //
661 // Option Rom for
662 //
663 {
664 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
665 0x0, // Segment
666 0x0, // Bus Number
667 0x2, // Device Number
668 0x0, // Function Number
669 0x8086, // Vendor ID
670 0x10a, // Device ID
671 },
672 //
673 // Option Rom for
674 //
675 {
676 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
677 0x0, // Segment
678 0x0, // Bus Number
679 0x2, // Device Number
680 0x0, // Function Number
681 0x8086, // Vendor ID
682 0x5a51, // Device ID
683 },
684 //
685 // Option Rom for
686 //
687 {
688 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
689 0x0, // Segment
690 0x0, // Bus Number
691 0x2, // Device Number
692 0x0, // Function Number
693 0x8086, // Vendor ID
694 0x5a52, // Device ID
695 },
696 //
697 // Option Rom for
698 //
699 {
700 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
701 0x0, // Segment
702 0x0, // Bus Number
703 0x2, // Device Number
704 0x0, // Function Number
705 0x8086, // Vendor ID
706 0x5a5a, // Device ID
707 },
708 //
709 // Option Rom for
710 //
711 {
712 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
713 0x0, // Segment
714 0x0, // Bus Number
715 0x2, // Device Number
716 0x0, // Function Number
717 0x8086, // Vendor ID
718 0x5a42, // Device ID
719 },
720 //
721 // Option Rom for
722 //
723 {
724 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
725 0x0, // Segment
726 0x0, // Bus Number
727 0x2, // Device Number
728 0x0, // Function Number
729 0x8086, // Vendor ID
730 0x5a4a, // Device ID
731 },
732 //
733 // Option Rom for
734 //
735 {
736 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
737 0x0, // Segment
738 0x0, // Bus Number
739 0x2, // Device Number
740 0x0, // Function Number
741 0x8086, // Vendor ID
742 0x5a62, // Device ID
743 },
744 //
745 // Option Rom for
746 //
747 {
748 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
749 0x0, // Segment
750 0x0, // Bus Number
751 0x2, // Device Number
752 0x0, // Function Number
753 0x8086, // Vendor ID
754 0x5a54, // Device ID
755 },
756 //
757 // Option Rom for
758 //
759 {
760 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
761 0x0, // Segment
762 0x0, // Bus Number
763 0x2, // Device Number
764 0x0, // Function Number
765 0x8086, // Vendor ID
766 0x5a44, // Device ID
767 },
768 //
769 // Option Rom for
770 //
771 {
772 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
773 0x0, // Segment
774 0x0, // Bus Number
775 0x2, // Device Number
776 0x0, // Function Number
777 0x8086, // Vendor ID
778 0x5a55, // Device ID
779 },
780 //
781 // Option Rom for
782 //
783 {
784 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
785 0x0, // Segment
786 0x0, // Bus Number
787 0x2, // Device Number
788 0x0, // Function Number
789 0x8086, // Vendor ID
790 0x5a45, // Device ID
791 },
792 //
793 // Option Rom for
794 //
795 {
796 RAID_OPTION_ROM_FILE_GUID, // Guid
797 0x0, // Segment
798 0x0, // Bus Number
799 0x17, // Device Number
800 0x0, // Function Number
801 0x8086, // Vendor ID
802 0x282a, // Device ID
803 },
804 //
805 // Option Rom for
806 //
807 {
808 RAID_OPTION_ROM_FILE_GUID, // Guid
809 0x0, // Segment
810 0x0, // Bus Number
811 0x17, // Device Number
812 0x0, // Function Number
813 0x8086, // Vendor ID
814 0x2822, // Device ID
815 },
816 //
817 // Option Rom for
818 //
819 {
820 RSTE_OPTION_ROM_FILE_GUID, // Guid
821 0x0, // Segment
822 0x0, // Bus Number
823 0x17, // Device Number
824 0x0, // Function Number
825 0x8086, // Vendor ID
826 0x2826, // Device ID
827 },
828 //
829 // Option Rom for
830 //
831 {
832 PXE_OPTION_ROM_FILE_GUID, // Guid
833 0x0, // Segment
834 0x0, // Bus Number
835 0x1f, // Device Number
836 0x6, // Function Number
837 0xffff, // Vendor ID
838 0xffff, // Device ID
839 },
840 //
841 // End of OptionRom Entries
842 //
843 {
844 NULL_ROM_FILE_GUID, // Guid
845 0, // Segment
846 0, // Bus Number
847 0, // Device Number
848 0, // Function Number
849 0xffff, // Vendor ID
850 0xffff, // Device ID
851 }
852 };
853
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformOptionRomTable_Sds.h Source File

  • MultiPlatform
PlatformOptionRomTable_Sds.h
1 /*++
2 Copyright (c) 2005 - 2007 Intel Corporation. All rights reserved
3 This software and associated documentation (if any) is furnished
4 under a license and may only be used or copied in accordance
5 with the terms of the license. Except as permitted by such
6 license, no part of this software or documentation may be
7 reproduced, stored in a retrieval system, or transmitted in any
8 form or by any means without the express written consent of
9 Intel Corporation.
10
11 Module Name:
12
13 PlatformOptionRomTable_Sds.h
14
15 --*/
16
17 //
18 // Automatically generated by ACE ver 1.63 PIRQTRANS
19 // Please DO NOT modify !!!
20 //
21
22
23 PCI_OPTION_ROM_TABLE mPciOptionRomTable_Sds[] = {
24 //
25 // Option Rom for
26 //
27 {
28 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
29 0x0, // Segment
30 0x0, // Bus Number
31 0x2, // Device Number
32 0x0, // Function Number
33 0x8086, // Vendor ID
34 0x1906, // Device ID
35 },
36 //
37 // Option Rom for
38 //
39 {
40 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
41 0x0, // Segment
42 0x0, // Bus Number
43 0x2, // Device Number
44 0x0, // Function Number
45 0x8086, // Vendor ID
46 0x1913, // Device ID
47 },
48 //
49 // Option Rom for
50 //
51 {
52 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
53 0x0, // Segment
54 0x0, // Bus Number
55 0x2, // Device Number
56 0x0, // Function Number
57 0x8086, // Vendor ID
58 0x1916, // Device ID
59 },
60 //
61 // Option Rom for
62 //
63 {
64 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
65 0x0, // Segment
66 0x0, // Bus Number
67 0x2, // Device Number
68 0x0, // Function Number
69 0x8086, // Vendor ID
70 0x1921, // Device ID
71 },
72 //
73 // Option Rom for
74 //
75 {
76 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
77 0x0, // Segment
78 0x0, // Bus Number
79 0x2, // Device Number
80 0x0, // Function Number
81 0x8086, // Vendor ID
82 0x1926, // Device ID
83 },
84 //
85 // Option Rom for
86 //
87 {
88 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
89 0x0, // Segment
90 0x0, // Bus Number
91 0x2, // Device Number
92 0x0, // Function Number
93 0x8086, // Vendor ID
94 0x190b, // Device ID
95 },
96 //
97 // Option Rom for
98 //
99 {
100 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
101 0x0, // Segment
102 0x0, // Bus Number
103 0x2, // Device Number
104 0x0, // Function Number
105 0x8086, // Vendor ID
106 0x191b, // Device ID
107 },
108 //
109 // Option Rom for
110 //
111 {
112 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
113 0x0, // Segment
114 0x0, // Bus Number
115 0x2, // Device Number
116 0x0, // Function Number
117 0x8086, // Vendor ID
118 0x192b, // Device ID
119 },
120 //
121 // Option Rom for
122 //
123 {
124 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
125 0x0, // Segment
126 0x0, // Bus Number
127 0x2, // Device Number
128 0x0, // Function Number
129 0x8086, // Vendor ID
130 0x193b, // Device ID
131 },
132 //
133 // Option Rom for
134 //
135 {
136 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
137 0x0, // Segment
138 0x0, // Bus Number
139 0x2, // Device Number
140 0x0, // Function Number
141 0x8086, // Vendor ID
142 0x192d, // Device ID
143 },
144 //
145 // Option Rom for
146 //
147 {
148 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
149 0x0, // Segment
150 0x0, // Bus Number
151 0x2, // Device Number
152 0x0, // Function Number
153 0x8086, // Vendor ID
154 0x193d, // Device ID
155 },
156 //
157 // Option Rom for
158 //
159 {
160 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
161 0x0, // Segment
162 0x0, // Bus Number
163 0x2, // Device Number
164 0x0, // Function Number
165 0x8086, // Vendor ID
166 0x190e, // Device ID
167 },
168 //
169 // Option Rom for
170 //
171 {
172 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
173 0x0, // Segment
174 0x0, // Bus Number
175 0x2, // Device Number
176 0x0, // Function Number
177 0x8086, // Vendor ID
178 0x1915, // Device ID
179 },
180 //
181 // Option Rom for
182 //
183 {
184 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
185 0x0, // Segment
186 0x0, // Bus Number
187 0x2, // Device Number
188 0x0, // Function Number
189 0x8086, // Vendor ID
190 0x191e, // Device ID
191 },
192 //
193 // Option Rom for
194 //
195 {
196 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
197 0x0, // Segment
198 0x0, // Bus Number
199 0x2, // Device Number
200 0x0, // Function Number
201 0x8086, // Vendor ID
202 0x190a, // Device ID
203 },
204 //
205 // Option Rom for
206 //
207 {
208 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
209 0x0, // Segment
210 0x0, // Bus Number
211 0x2, // Device Number
212 0x0, // Function Number
213 0x8086, // Vendor ID
214 0x191a, // Device ID
215 },
216 //
217 // Option Rom for
218 //
219 {
220 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
221 0x0, // Segment
222 0x0, // Bus Number
223 0x2, // Device Number
224 0x0, // Function Number
225 0x8086, // Vendor ID
226 0x192a, // Device ID
227 },
228 //
229 // Option Rom for
230 //
231 {
232 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
233 0x0, // Segment
234 0x0, // Bus Number
235 0x2, // Device Number
236 0x0, // Function Number
237 0x8086, // Vendor ID
238 0x193a, // Device ID
239 },
240 //
241 // Option Rom for
242 //
243 {
244 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
245 0x0, // Segment
246 0x0, // Bus Number
247 0x2, // Device Number
248 0x0, // Function Number
249 0x8086, // Vendor ID
250 0x1902, // Device ID
251 },
252 //
253 // Option Rom for
254 //
255 {
256 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
257 0x0, // Segment
258 0x0, // Bus Number
259 0x2, // Device Number
260 0x0, // Function Number
261 0x8086, // Vendor ID
262 0x1912, // Device ID
263 },
264 //
265 // Option Rom for
266 //
267 {
268 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
269 0x0, // Segment
270 0x0, // Bus Number
271 0x2, // Device Number
272 0x0, // Function Number
273 0x8086, // Vendor ID
274 0x1917, // Device ID
275 },
276 //
277 // Option Rom for
278 //
279 {
280 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
281 0x0, // Segment
282 0x0, // Bus Number
283 0x2, // Device Number
284 0x0, // Function Number
285 0x8086, // Vendor ID
286 0x1932, // Device ID
287 },
288 //
289 // Option Rom for
290 //
291 {
292 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
293 0x0, // Segment
294 0x0, // Bus Number
295 0x2, // Device Number
296 0x0, // Function Number
297 0x8086, // Vendor ID
298 0x191d, // Device ID
299 },
300 //
301 // Option Rom for
302 //
303 {
304 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
305 0x0, // Segment
306 0x0, // Bus Number
307 0x2, // Device Number
308 0x0, // Function Number
309 0x8086, // Vendor ID
310 0x5906, // Device ID
311 },
312 //
313 // Option Rom for
314 //
315 {
316 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
317 0x0, // Segment
318 0x0, // Bus Number
319 0x2, // Device Number
320 0x0, // Function Number
321 0x8086, // Vendor ID
322 0x5913, // Device ID
323 },
324 //
325 // Option Rom for
326 //
327 {
328 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
329 0x0, // Segment
330 0x0, // Bus Number
331 0x2, // Device Number
332 0x0, // Function Number
333 0x8086, // Vendor ID
334 0x5916, // Device ID
335 },
336 //
337 // Option Rom for
338 //
339 {
340 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
341 0x0, // Segment
342 0x0, // Bus Number
343 0x2, // Device Number
344 0x0, // Function Number
345 0x8086, // Vendor ID
346 0x5921, // Device ID
347 },
348 //
349 // Option Rom for
350 //
351 {
352 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
353 0x0, // Segment
354 0x0, // Bus Number
355 0x2, // Device Number
356 0x0, // Function Number
357 0x8086, // Vendor ID
358 0x5926, // Device ID
359 },
360 //
361 // Option Rom for
362 //
363 {
364 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
365 0x0, // Segment
366 0x0, // Bus Number
367 0x2, // Device Number
368 0x0, // Function Number
369 0x8086, // Vendor ID
370 0x590b, // Device ID
371 },
372 //
373 // Option Rom for
374 //
375 {
376 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
377 0x0, // Segment
378 0x0, // Bus Number
379 0x2, // Device Number
380 0x0, // Function Number
381 0x8086, // Vendor ID
382 0x591b, // Device ID
383 },
384 //
385 // Option Rom for
386 //
387 {
388 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
389 0x0, // Segment
390 0x0, // Bus Number
391 0x2, // Device Number
392 0x0, // Function Number
393 0x8086, // Vendor ID
394 0x592b, // Device ID
395 },
396 //
397 // Option Rom for
398 //
399 {
400 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
401 0x0, // Segment
402 0x0, // Bus Number
403 0x2, // Device Number
404 0x0, // Function Number
405 0x8086, // Vendor ID
406 0x593b, // Device ID
407 },
408 //
409 // Option Rom for
410 //
411 {
412 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
413 0x0, // Segment
414 0x0, // Bus Number
415 0x2, // Device Number
416 0x0, // Function Number
417 0x8086, // Vendor ID
418 0x590e, // Device ID
419 },
420 //
421 // Option Rom for
422 //
423 {
424 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
425 0x0, // Segment
426 0x0, // Bus Number
427 0x2, // Device Number
428 0x0, // Function Number
429 0x8086, // Vendor ID
430 0x5915, // Device ID
431 },
432 //
433 // Option Rom for
434 //
435 {
436 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
437 0x0, // Segment
438 0x0, // Bus Number
439 0x2, // Device Number
440 0x0, // Function Number
441 0x8086, // Vendor ID
442 0x591e, // Device ID
443 },
444 //
445 // Option Rom for
446 //
447 {
448 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
449 0x0, // Segment
450 0x0, // Bus Number
451 0x2, // Device Number
452 0x0, // Function Number
453 0x8086, // Vendor ID
454 0x590a, // Device ID
455 },
456 //
457 // Option Rom for
458 //
459 {
460 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
461 0x0, // Segment
462 0x0, // Bus Number
463 0x2, // Device Number
464 0x0, // Function Number
465 0x8086, // Vendor ID
466 0x591a, // Device ID
467 },
468 //
469 // Option Rom for
470 //
471 {
472 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
473 0x0, // Segment
474 0x0, // Bus Number
475 0x2, // Device Number
476 0x0, // Function Number
477 0x8086, // Vendor ID
478 0x592a, // Device ID
479 },
480 //
481 // Option Rom for
482 //
483 {
484 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
485 0x0, // Segment
486 0x0, // Bus Number
487 0x2, // Device Number
488 0x0, // Function Number
489 0x8086, // Vendor ID
490 0x593a, // Device ID
491 },
492 //
493 // Option Rom for
494 //
495 {
496 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
497 0x0, // Segment
498 0x0, // Bus Number
499 0x2, // Device Number
500 0x0, // Function Number
501 0x8086, // Vendor ID
502 0x5902, // Device ID
503 },
504 //
505 // Option Rom for
506 //
507 {
508 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
509 0x0, // Segment
510 0x0, // Bus Number
511 0x2, // Device Number
512 0x0, // Function Number
513 0x8086, // Vendor ID
514 0x5912, // Device ID
515 },
516 //
517 // Option Rom for
518 //
519 {
520 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
521 0x0, // Segment
522 0x0, // Bus Number
523 0x2, // Device Number
524 0x0, // Function Number
525 0x8086, // Vendor ID
526 0x5917, // Device ID
527 },
528 //
529 // Option Rom for
530 //
531 {
532 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
533 0x0, // Segment
534 0x0, // Bus Number
535 0x2, // Device Number
536 0x0, // Function Number
537 0x8086, // Vendor ID
538 0x5932, // Device ID
539 },
540 //
541 // Option Rom for
542 //
543 {
544 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
545 0x0, // Segment
546 0x0, // Bus Number
547 0x2, // Device Number
548 0x0, // Function Number
549 0x8086, // Vendor ID
550 0x591d, // Device ID
551 },
552 //
553 // Option Rom for
554 //
555 {
556 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
557 0x0, // Segment
558 0x0, // Bus Number
559 0x2, // Device Number
560 0x0, // Function Number
561 0x8086, // Vendor ID
562 0x593d, // Device ID
563 },
564 //
565 // Option Rom for
566 //
567 {
568 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
569 0x0, // Segment
570 0x0, // Bus Number
571 0x2, // Device Number
572 0x0, // Function Number
573 0x8086, // Vendor ID
574 0x2a42, // Device ID
575 },
576 //
577 // Option Rom for
578 //
579 {
580 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
581 0x0, // Segment
582 0x0, // Bus Number
583 0x2, // Device Number
584 0x0, // Function Number
585 0x8086, // Vendor ID
586 0x106, // Device ID
587 },
588 //
589 // Option Rom for
590 //
591 {
592 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
593 0x0, // Segment
594 0x0, // Bus Number
595 0x2, // Device Number
596 0x0, // Function Number
597 0x8086, // Vendor ID
598 0x116, // Device ID
599 },
600 //
601 // Option Rom for
602 //
603 {
604 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
605 0x0, // Segment
606 0x0, // Bus Number
607 0x2, // Device Number
608 0x0, // Function Number
609 0x8086, // Vendor ID
610 0x126, // Device ID
611 },
612 //
613 // Option Rom for
614 //
615 {
616 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
617 0x0, // Segment
618 0x0, // Bus Number
619 0x2, // Device Number
620 0x0, // Function Number
621 0x8086, // Vendor ID
622 0xa02, // Device ID
623 },
624 //
625 // Option Rom for
626 //
627 {
628 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
629 0x0, // Segment
630 0x0, // Bus Number
631 0x2, // Device Number
632 0x0, // Function Number
633 0x8086, // Vendor ID
634 0x102, // Device ID
635 },
636 //
637 // Option Rom for
638 //
639 {
640 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
641 0x0, // Segment
642 0x0, // Bus Number
643 0x2, // Device Number
644 0x0, // Function Number
645 0x8086, // Vendor ID
646 0x112, // Device ID
647 },
648 //
649 // Option Rom for
650 //
651 {
652 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
653 0x0, // Segment
654 0x0, // Bus Number
655 0x2, // Device Number
656 0x0, // Function Number
657 0x8086, // Vendor ID
658 0x122, // Device ID
659 },
660 //
661 // Option Rom for
662 //
663 {
664 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
665 0x0, // Segment
666 0x0, // Bus Number
667 0x2, // Device Number
668 0x0, // Function Number
669 0x8086, // Vendor ID
670 0x10a, // Device ID
671 },
672 //
673 // Option Rom for
674 //
675 {
676 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
677 0x0, // Segment
678 0x0, // Bus Number
679 0x2, // Device Number
680 0x0, // Function Number
681 0x8086, // Vendor ID
682 0x5a51, // Device ID
683 },
684 //
685 // Option Rom for
686 //
687 {
688 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
689 0x0, // Segment
690 0x0, // Bus Number
691 0x2, // Device Number
692 0x0, // Function Number
693 0x8086, // Vendor ID
694 0x5a52, // Device ID
695 },
696 //
697 // Option Rom for
698 //
699 {
700 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
701 0x0, // Segment
702 0x0, // Bus Number
703 0x2, // Device Number
704 0x0, // Function Number
705 0x8086, // Vendor ID
706 0x5a5a, // Device ID
707 },
708 //
709 // Option Rom for
710 //
711 {
712 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
713 0x0, // Segment
714 0x0, // Bus Number
715 0x2, // Device Number
716 0x0, // Function Number
717 0x8086, // Vendor ID
718 0x5a42, // Device ID
719 },
720 //
721 // Option Rom for
722 //
723 {
724 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
725 0x0, // Segment
726 0x0, // Bus Number
727 0x2, // Device Number
728 0x0, // Function Number
729 0x8086, // Vendor ID
730 0x5a4a, // Device ID
731 },
732 //
733 // Option Rom for
734 //
735 {
736 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
737 0x0, // Segment
738 0x0, // Bus Number
739 0x2, // Device Number
740 0x0, // Function Number
741 0x8086, // Vendor ID
742 0x5a62, // Device ID
743 },
744 //
745 // Option Rom for
746 //
747 {
748 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
749 0x0, // Segment
750 0x0, // Bus Number
751 0x2, // Device Number
752 0x0, // Function Number
753 0x8086, // Vendor ID
754 0x5a54, // Device ID
755 },
756 //
757 // Option Rom for
758 //
759 {
760 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
761 0x0, // Segment
762 0x0, // Bus Number
763 0x2, // Device Number
764 0x0, // Function Number
765 0x8086, // Vendor ID
766 0x5a44, // Device ID
767 },
768 //
769 // Option Rom for
770 //
771 {
772 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
773 0x0, // Segment
774 0x0, // Bus Number
775 0x2, // Device Number
776 0x0, // Function Number
777 0x8086, // Vendor ID
778 0x5a55, // Device ID
779 },
780 //
781 // Option Rom for
782 //
783 {
784 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
785 0x0, // Segment
786 0x0, // Bus Number
787 0x2, // Device Number
788 0x0, // Function Number
789 0x8086, // Vendor ID
790 0x5a45, // Device ID
791 },
792 //
793 // Option Rom for
794 //
795 {
796 RAID_OPTION_ROM_FILE_GUID, // Guid
797 0x0, // Segment
798 0x0, // Bus Number
799 0x17, // Device Number
800 0x0, // Function Number
801 0x8086, // Vendor ID
802 0x282a, // Device ID
803 },
804 //
805 // Option Rom for
806 //
807 {
808 RAID_OPTION_ROM_FILE_GUID, // Guid
809 0x0, // Segment
810 0x0, // Bus Number
811 0x17, // Device Number
812 0x0, // Function Number
813 0x8086, // Vendor ID
814 0x2822, // Device ID
815 },
816 //
817 // Option Rom for
818 //
819 {
820 RSTE_OPTION_ROM_FILE_GUID, // Guid
821 0x0, // Segment
822 0x0, // Bus Number
823 0x17, // Device Number
824 0x0, // Function Number
825 0x8086, // Vendor ID
826 0x2826, // Device ID
827 },
828 //
829 // Option Rom for
830 //
831 {
832 PXE_OPTION_ROM_FILE_GUID, // Guid
833 0x0, // Segment
834 0x0, // Bus Number
835 0x1f, // Device Number
836 0x6, // Function Number
837 0xffff, // Vendor ID
838 0xffff, // Device ID
839 },
840 //
841 // End of OptionRom Entries
842 //
843 {
844 NULL_ROM_FILE_GUID, // Guid
845 0, // Segment
846 0, // Bus Number
847 0, // Device Number
848 0, // Function Number
849 0xffff, // Vendor ID
850 0xffff, // Device ID
851 }
852 };
853
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformPostCode.h File Reference

Macros
PlatformPostCode.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define BOARD_INIT_PREMEM_ENTRY 0xD500
[definition] PostCode = XYZZ X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE Y - "6"=platform driver, "5"=board driver ZZ - "00"=entry, "7F"=exit More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright (c) 2016-2017 Intel Corporation. All rights reserved

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformPostCode.h.

Macro Definition Documentation

#define BOARD_INIT_PREMEM_ENTRY 0xD500

[definition] PostCode = XYZZ X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE Y - "6"=platform driver, "5"=board driver ZZ - "00"=entry, "7F"=exit

  • 1 - board init premem: entry/exit (0xD500/0xD57F)
  • 2 - platform init premem: entry/exit (0xD600/0xD67F)
  • 3 - board init postmem: entry/exit (0x9500/0x957F)
  • 4 - platform init postmem: entry/exit (0x9600/0x967F)
  • 5 - board init DXE: entry/exit (0x7500/0x757F)
  • 6 - platform init DXE: entry/exit (0x7600/0x767F)
  • 7 - platform SMM init: entry/exit (0x8600/0x867F)
  • 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC
  • 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC
  • 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with ACPI _PTS PC

Definition at line 58 of file PlatformPostCode.h.


IceLake Platform Sample Code: PlatformSecureLib.h File Reference

  • Library
Functions
PlatformSecureLib.h File Reference

Provides a secure platform-specific method to detect physically present user. More...

Go to the source code of this file.

Functions

EFI_STATUS PlatformSecureLibTestConstructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) BOOLEAN UserPhysicalPresent(VOID)
Constructor function for Platform Security library. More...

Detailed Description

Provides a secure platform-specific method to detect physically present user.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PlatformSecureLib.h.

Function Documentation

EFI_STATUS PlatformSecureLibTestConstructor | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Constructor function for Platform Security library.

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS When this function completed.

This function provides a platform-specific method to detect whether the platform is operating by a physically present user.

Programmatic changing of platform security policy (such as disable Secure Boot, or switch between Standard/Custom Secure Boot mode) MUST NOT be possible during Boot Services or after exiting EFI Boot Services. Only a physically present user is allowed to perform these operations.

NOTE THAT: This function cannot depend on any EFI Variable Service since they are not available when this function is called in AuthenticateVariable driver.

Return values
TRUE | The platform is operated by a physically present user.
FALSE | The platform is NOT operated by a physically present user.


IceLake Platform Sample Code: PlatformSmmIoLib.h File Reference

  • Library
Macros | Enumerations | Functions
PlatformSmmIoLib.h File Reference

This library provides SMM functions for IO and PCI IO access. More...

#include <Uefi/UefiBaseType.h>
#include <Uefi/UefiMultiPhase.h>
#include <Uefi/UefiSpec.h>
#include <Library/DebugLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Pi/PiDxeCis.h>
#include <Library/SmmServicesTableLib.h>
#include <IndustryStandard/Pci22.h>
Include dependency graph for PlatformSmmIoLib.h:

Go to the source code of this file.

Macros

#define ICH_ACPI_TIMER_MAX_VALUE 0x1000000
Global variables that must be defined and initialized to use this library. More...

Enumerations

enum SMM_PCI_IO_WIDTH
Pci I/O related data structure deifinition.

Functions

UINT8 | SmmIoRead8 (IN UINT16 Address)
CPU I/O Access Functions. More...
VOID | SmmIoWrite8 (IN UINT16 Address, IN UINT8 Data)
Do a one byte IO write. More...
UINT16 | SmmIoRead16 (IN UINT16 Address)
Do a two byte IO read. More...
VOID | SmmIoWrite16 (IN UINT16 Address, IN UINT16 Data)
Do a two byte IO write. More...
UINT32 | SmmIoRead32 (IN UINT16 Address)
Do a four byte IO read. More...
VOID | SmmIoWrite32 (IN UINT16 Address, IN UINT32 Data)
Do a four byte IO write. More...
VOID | SmmMemWrite8 (IN UINT64 Dest, IN UINT8 Data)
Do a one byte Memory write. More...
UINT8 | SmmMemRead8 (IN UINT64 Dest)
Do a one byte Memory read. More...
VOID | SmmMemWrite16 (IN UINT64 Dest, IN UINT16 Data)
Do a two bytes Memory write. More...
UINT16 | SmmMemRead16 (IN UINT64 Dest)
Do a two bytes Memory read. More...
VOID | SmmMemWrite32 (IN UINT64 Dest, IN UINT32 Data)
Do a four bytes Memory write. More...
UINT32 | SmmMemRead32 (IN UINT64 Dest)
Do a four bytes Memory read. More...
VOID | SmmMemAnd32 (IN UINT64 Dest, IN UINT32 Data)
Do a four bytes Memory read, then AND with Data, then write back to the same address. More...
EFI_STATUS | SmmPciCfgRead (IN SMM_PCI_IO_WIDTH Width, IN SMM_PCI_IO_ADDRESS *Address, IN OUT VOID *Buffer)
Pci Configuration Space access functions definition. More...
EFI_STATUS | SmmPciCfgWrite (IN SMM_PCI_IO_WIDTH Width, IN SMM_PCI_IO_ADDRESS *Address, IN OUT VOID *Buffer)
Write value into the specified PCI config space register. More...

Detailed Description

This library provides SMM functions for IO and PCI IO access.

These can be used to save size and simplify code. All contents must be runtime and SMM safe.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformSmmIoLib.h.

Macro Definition Documentation

#define ICH_ACPI_TIMER_MAX_VALUE 0x1000000

Global variables that must be defined and initialized to use this library.

DefinitionsThe timer is 24 bit overflow

Definition at line 59 of file PlatformSmmIoLib.h.

Function Documentation

UINT16 SmmIoRead16 ( IN UINT16 Address )

Do a two byte IO read.

Parameters
[in] Address - IO address to read
Return values
Data read
UINT32 SmmIoRead32 ( IN UINT16 Address )

Do a four byte IO read.

Parameters
[in] Address - IO address to read
Return values
Data read
UINT8 SmmIoRead8 ( IN UINT16 Address )

CPU I/O Access Functions.

Do a one byte IO read

Parameters
[in] Address - IO address to read
Return values
Data read
VOID SmmIoWrite16 | ( | IN UINT16 | Address,
 |  | IN UINT16 | Data
 | ) |  |

Do a two byte IO write.

Parameters
[in] | Address | - IO address to write
[in] | Data | - Data to write
VOID SmmIoWrite32 | ( | IN UINT16 | Address,
 |  | IN UINT32 | Data
 | ) |  |

Do a four byte IO write.

Parameters
[in] | Address | - IO address to write
[in] | Data | - Data to write
VOID SmmIoWrite8 | ( | IN UINT16 | Address,
 |  | IN UINT8 | Data
 | ) |  |

Do a one byte IO write.

Parameters
[in] | Address | - IO address to write
[in] | Data | - Data to write
VOID SmmMemAnd32 | ( | IN UINT64 | Dest,
 |  | IN UINT32 | Data
 | ) |  |

Do a four bytes Memory read, then AND with Data, then write back to the same address.

Parameters
[in] | Dest | - Memory address to write
[in] | Data | - Data to do AND
UINT16 SmmMemRead16 ( IN UINT64 Dest )

Do a two bytes Memory read.

Parameters
[in] Dest - Memory address to read
Return values
Data read
UINT32 SmmMemRead32 ( IN UINT64 Dest )

Do a four bytes Memory read.

Parameters
[in] Dest - Memory address to read
Return values
Data read
UINT8 SmmMemRead8 ( IN UINT64 Dest )

Do a one byte Memory read.

Parameters
[in] Dest - Memory address to read
Return values
Data read
VOID SmmMemWrite16 | ( | IN UINT64 | Dest,
 |  | IN UINT16 | Data
 | ) |  |

Do a two bytes Memory write.

Parameters
[in] | Dest | - Memory address to write
[in] | Data | - Data to write
VOID SmmMemWrite32 | ( | IN UINT64 | Dest,
 |  | IN UINT32 | Data
 | ) |  |

Do a four bytes Memory write.

Parameters
[in] | Dest | - Memory address to write
[in] | Data | - Data to write
VOID SmmMemWrite8 | ( | IN UINT64 | Dest,
 |  | IN UINT8 | Data
 | ) |  |

Do a one byte Memory write.

Parameters
[in] | Dest | - Memory address to write
[in] | Data | - Data to write
EFI_STATUS SmmPciCfgRead | ( | IN SMM_PCI_IO_WIDTH | Width,
 |  | IN SMM_PCI_IO_ADDRESS * | Address,
 |  | IN OUT VOID * | Buffer
 | ) |  |

Pci Configuration Space access functions definition.

Read value from the specified PCI config space register

Parameters
[in] | Width | - The width (8, 16 or 32 bits) of accessed pci config space register
[in] | Address | - The address of the accessed pci register (bus, dev, func, offset)
[in] | Buffer | - The returned value
Return values
EFI_SUCCESS | - All operations successfully
EFI_INVALID_PARAMETER | - Width is not valid or dosn't match register address
Other | error code - If any error occured when calling libiary functions
EFI_STATUS SmmPciCfgWrite | ( | IN SMM_PCI_IO_WIDTH | Width,
 |  | IN SMM_PCI_IO_ADDRESS * | Address,
 |  | IN OUT VOID * | Buffer
 | ) |  |

Write value into the specified PCI config space register.

Parameters
[in] | Width | - The width (8, 16 or 32 bits) of accessed pci config space register
[in] | Address | - The address of the accessed pci register (bus, dev, func, offset)
[in] | Buffer | - The returned value
Return values
EFI_SUCCESS | - All operations successfully
EFI_INVALID_PARAMETER | - Width is not valid or dosn't match register address
Other | error code - If any error occured when calling libiary functions


IceLake Platform Sample Code: PolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
PolicyInitDxe.c File Reference

This file is a wrapper for Platform Policy driver. More...

#include "PolicyInitDxe.h"
Include dependency graph for PolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS PolicyInitDxeEntryPoint (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy. More...

Detailed Description

This file is a wrapper for Platform Policy driver.

Get Setup Value to initialize Intel DXE Platform Policy.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PolicyInitDxe.c.

Function Documentation

EFI_STATUS PolicyInitDxeEntryPoint | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Initialize DXE Platform Policy.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | SystemTable | Global system service table.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file PolicyInitDxe.c.

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IceLake Platform Sample Code: PolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
PolicyInitDxe.h File Reference

Header file for the PolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <SetupVariable.h>
#include "AmtPolicyInitDxe.h"
#include "MePolicyInitDxe.h"
#include "SaPolicyInitDxe.h"
#include "PchPolicyInitDxe.h"
#include "SiliconPolicyInitDxe.h"
#include "GopPolicyInitDxe.h"
#include "CpuPolicyInitDxe.h"
#include "TbtPolicyInitDxe.h"
#include <Library/DxeTbtPolicyLib.h>
Include dependency graph for PolicyInitDxe.h:
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Functions

EFI_STATUS PolicyInitDxeEntryPoint (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy. More...

Detailed Description

Header file for the PolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PolicyInitDxe.h.

Function Documentation

EFI_STATUS PolicyInitDxeEntryPoint | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Initialize DXE Platform Policy.

Parameters
[in] | ImageHandle | - Image handle of this driver.
[in] | SystemTable | - Global system service table.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.
Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | SystemTable | Global system service table.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file PolicyInitDxe.c.

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IceLake Platform Sample Code: PttInstance.h File Reference

  • Guid
PttInstance.h File Reference

GUID definition for the PTT device instance. More...

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Detailed Description

GUID definition for the PTT device instance.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PttInstance.h.


IceLake Platform Sample Code: PttPTPInstanceGuid.h File Reference

  • Guid
PttPTPInstanceGuid.h File Reference

GUID definition for the PTT device instance. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

GUID definition for the PTT device instance.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PttPTPInstanceGuid.h.


IceLake Platform Sample Code: S3MemoryVariable.h File Reference

  • Guid
S3MemoryVariable.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file S3MemoryVariable.h.


IceLake Platform Sample Code: SaPlatformInitDxe.c File Reference

  • PlatformInit
  • PlatformInitDxe
Functions
SaPlatformInitDxe.c File Reference

Source code file for the Platform Init DXE module. More...

#include "PlatformInitDxe.h"
#include <Protocol/BlockIo.h>
#include <Protocol/GopPolicy.h>
#include <LegacyUsb/Protocol/UsbController.h>
#include <Protocol/SaPolicy.h>
#include <Library/DebugLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/PciEnumerationComplete.h>
#include <PlatformNvRamHookLib.h>
#include <TbtBoardInfo.h>
Include dependency graph for SaPlatformInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS | RegisterDisplayDimmPopulationErrMsg (VOID)
Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation. More...
VOID | DisplayDimmPopulationErrMsg (IN EFI_EVENT Event, IN VOID *Context)
Display DIMM population error message, while Wrong DIMM Population is found. More...
VOID | UpdateGmAdrRegionToWriteCombine (VOID)
This function will update the GT Aperture Region to Write Combining. More...
VOID | PciEnumCompleteCallback (IN EFI_EVENT Event, IN VOID *Context)
This function gets registered as a callback to perform SA functions after PCI enumeration completes. More...
VOID | UpdateRmrrUsbAddress (VOID)
Update RMRR Base and Limit Address for USB.
EFI_STATUS | UpdateSaPolicyGopVbtPointer (VOID)
Update SaPolicyGopVbtPointer and Size. More...
VOID | UpdateItbtDmaUuidVariable (VOID)
Update Setup variable for keep DMA UUID. More...
VOID | UpdateDimmPopulation (VOID)
Updates DIMM slots status for Desktop,server and workstation boards. More...
VOID | SaPlatformInitDxe (VOID)
System Agent platform Initialization. More...

Detailed Description

Source code file for the Platform Init DXE module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SaPlatformInitDxe.c.

Function Documentation

VOID DisplayDimmPopulationErrMsg | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Display DIMM population error message, while Wrong DIMM Population is found.

Parameters
[in] | Event | A pointer to the Event that triggered the callback
[in] | Context | A pointer to private data registered with the callback function.
Return values
EFI_SUCCESS If Successfully exectuted else returns the error status

Definition at line 309 of file SaPlatformInitDxe.c.

VOID PciEnumCompleteCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

This function gets registered as a callback to perform SA functions after PCI enumeration completes.

Parameters
[in] | Event | - A pointer to the Event that triggered the callback.
[in] | Context | - A pointer to private data registered with the callback function.

Check if this is first time called by EfiCreateProtocolNotifyEvent() or not, if it is, we will skip it until real event is triggered

If device 0:2:0 (Internal Graphics Device, or GT) is not present, skip it.

Definition at line 465 of file SaPlatformInitDxe.c.

EFI_STATUS RegisterDisplayDimmPopulationErrMsg ( VOID )

Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation.

Parameters
[in] SystemTable Pointer to the System Table
Return values
EFI_SUCCESS return EFI_STATUS as success

Definition at line 271 of file SaPlatformInitDxe.c.

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VOID SaPlatformInitDxe ( VOID )

System Agent platform Initialization.

Definition at line 406 of file SaPlatformInitDxe.c.

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VOID UpdateDimmPopulation ( VOID )

Updates DIMM slots status for Desktop,server and workstation boards.

Definition at line 252 of file SaPlatformInitDxe.c.

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VOID UpdateGmAdrRegionToWriteCombine ( VOID )

This function will update the GT Aperture Region to Write Combining.

Create PCI Enumeration Completed callback

Definition at line 437 of file SaPlatformInitDxe.c.

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VOID UpdateItbtDmaUuidVariable ( VOID )

Update Setup variable for keep DMA UUID.

Get ITBT DMA UUID value from HOB of gSaTcssHobGuid

Set ITBT DMA UUID to Setup Data variable with updated values

Definition at line 186 of file SaPlatformInitDxe.c.

EFI_STATUS UpdateSaPolicyGopVbtPointer ( VOID )

Update SaPolicyGopVbtPointer and Size.

Locate the GOP Policy Protocol.

Get VBT data

Definition at line 132 of file SaPlatformInitDxe.c.


IceLake Platform Sample Code: SaPolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
SaPolicyInitDxe.c File Reference

This file is SampleCode for SA DXE Policy initialization. More...

#include "SaPolicyInitDxe.h"
Include dependency graph for SaPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS SaPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize SA DXE Policy. More...

Detailed Description

This file is SampleCode for SA DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SaPolicyInitDxe.c.

Function Documentation

EFI_STATUS SaPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize SA DXE Policy.

SA DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file SaPolicyInitDxe.c.

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IceLake Platform Sample Code: SaPolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
SaPolicyInitDxe.h File Reference

Header file for the SaPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/SaPolicy.h>
#include <Library/DxeSaPolicyLib.h>
#include <Library/DxePolicyBoardConfigLib.h>
#include <Library/DxeSaPolicyUpdateLib.h>
#include <SaAccess.h>
Include dependency graph for SaPolicyInitDxe.h:
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Functions

EFI_STATUS SaPolicyInitDxe (IN EFI_HANDLE ImageHandle)
SA DXE Policy Driver Entry Point
More...

Detailed Description

Header file for the SaPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SaPolicyInitDxe.h.

Function Documentation

EFI_STATUS SaPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

SA DXE Policy Driver Entry Point

  • Introduction
    System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly. Platform policy Protocol is initialized with default settings in this funciton. This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
  • Precondition
    • Runtime variable service should be ready if policy initialization required.
  • Returns
    SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use.
  • Porting Recommendations
    Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
Parameters
[in] ImageHandle - Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

SA DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file SaPolicyInitDxe.c.

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IceLake Platform Sample Code: SdCard.h File Reference

  • IndustryStandard
Macros
SdCard.h File Reference

Header file for Industry SD Card 2.0 spec. More...

#include <IndustryStandard/Mmc.h>
Include dependency graph for SdCard.h:

Go to the source code of this file.

Macros

#define CHECK_PATTERN 0xAA
Physical Layer Simplified Specification Version 3.01 recommended 0xAA.

Detailed Description

Header file for Industry SD Card 2.0 spec.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SdCard.h.


IceLake Platform Sample Code: SdHostIo.h File Reference

  • Protocol
Typedefs
SdHostIo.h File Reference

Header file for interface definition of EFI_SD_HOST_IO_PROTOCOL. More...

Go to the source code of this file.

Typedefs

typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT16 CommandIndex, IN UINT32 Argument, IN TRANSFER_TYPE DataType, IN UINT8 *Buffer, OPTIONAL IN UINT32 BufferSize, IN RESPONSE_TYPE ResponseType, IN UINT32 TimeOut, OUT UINT32 *ResponseData OPTIONAL)
The main function used to send the command to the card inserted into the SD/MMC host slot. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 MaxFrequency)
Set max clock frequency of the host, the actual frequency may not be the same as MaxFrequency. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 BusWidth)
Set bus width of the host. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 Voltage)
Set voltage which could supported by the host. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 HighSpeed)
Set Host High Speed. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 DdrMode)
Set Host DDR Mode. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 SdrMode)
Set Host SDR Mode. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN RESET_TYPE ResetType)
Reset the host. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN BOOLEAN Enable)
Enable Auto Stop Command. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) (IN EFI_SD_HOST_IO_PROTOCOL *This)
Find whether these is a card inserted into the slot. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 BlockLength)
Set the Block length. More...
typedef EFI_STATUS(* | EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE) (IN EFI_SD_HOST_IO_PROTOCOL *This)
Setup Device for card initialization. More...

Detailed Description

Header file for interface definition of EFI_SD_HOST_IO_PROTOCOL.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SdHostIo.h.

Typedef Documentation

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) (IN EFI_SD_HOST_IO_PROTOCOL *This)

Find whether these is a card inserted into the slot.

If so init the host. If not, return EFI_NOT_FOUND.

Parameters
[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
Return values
EFI_SUCCESS | The function completed successfully
EFI_NOT_FOUND | The item was not found.

Definition at line 334 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN BOOLEAN Enable)

Enable Auto Stop Command.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | Enable | TRUE to enable Auto Stop Command
Return values
EFI_SUCCESS | The function completed successfully
EFI_TIMEOUT | The timeout time expired.

Definition at line 318 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN RESET_TYPE ResetType)

Reset the host.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | ResetAll | TRUE to reset all
Return values
EFI_SUCCESS | The function completed successfully
EFI_TIMEOUT | The timeout time expired.

Definition at line 302 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT16 CommandIndex, IN UINT32 Argument, IN TRANSFER_TYPE DataType, IN UINT8 *Buffer, OPTIONAL IN UINT32 BufferSize, IN RESPONSE_TYPE ResponseType, IN UINT32 TimeOut, OUT UINT32 *ResponseData OPTIONAL)

The main function used to send the command to the card inserted into the SD/MMC host slot.

It will assemble the arguments to set the command register and wait for the command and transfer completed until timeout. Then it will read the response register to fill the ResponseData.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | CommandIndex | The command index to set the command index field of command register
[in] | Argument | Command argument to set the argument field of command register
[in] | DataType | TRANSFER_TYPE, indicates no data, data in or data out
[in] | Buffer | Contains the data read from / write to the device
[in] | BufferSize | The size of the buffer
[in] | ResponseType | RESPONSE_TYPE
[in] | TimeOut | Time out value in 1 ms unit
[in] | ResponseData | Depending on the ResponseType, such as CSD or card status
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | A parameter was incorrect.
EFI_OUT_OF_RESOURCES | A resource has run out.
EFI_TIMEOUT | The timeout time expired.
EFI_DEVICE_ERROR | The physical device reported an error while attempting the operation

Definition at line 180 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 BlockLength)

Set the Block length.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | BlockLength | Card supported block length
Return values
EFI_SUCCESS | The function completed successfully
EFI_TIMEOUT | The timeout time expired.

Definition at line 349 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 BusWidth)

Set bus width of the host.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | BusWidth | Bus width in 1, 4, 8 bits
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | A parameter was incorrect.

Definition at line 221 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 MaxFrequency)

Set max clock frequency of the host, the actual frequency may not be the same as MaxFrequency.

It depends on the max frequency the host can support, divider, and host speed mode.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | MaxFrequency | Max frequency in HZ
Return values
EFI_SUCCESS | The function completed successfully
EFI_TIMEOUT | The timeout time expired.

Definition at line 205 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 DdrMode)

Set Host DDR Mode.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | DdrMode | True for DDR Mode set, false for normal mode
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | A parameter was incorrect.

Definition at line 270 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 SdrMode)

Set Host SDR Mode.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | DdrMode | True for SDR Mode set, false for normal mode
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | A parameter was incorrect.

Definition at line 286 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 HighSpeed)

Set Host High Speed.

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | HighSpeed | True for High Speed Mode set, false for normal mode
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | A parameter was incorrect.

Definition at line 254 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) (IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 Voltage)

Set voltage which could supported by the host.

Support 0(Power off the host), 1.8V, 3.0V, 3.3V

Parameters
[in] | This | Pointer to EFI_SD_HOST_IO_PROTOCOL
[in] | Voltage | Units in 0.1 V
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | A parameter was incorrect.

Definition at line 238 of file SdHostIo.h.

typedef EFI_STATUS( * EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE) (IN EFI_SD_HOST_IO_PROTOCOL *This)

Setup Device for card initialization.

Parameters
[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
Return values
EFI_SUCCESS The function completed successfully

Definition at line 362 of file SdHostIo.h.


IceLake Platform Sample Code: Setup.h File Reference

Macros
Setup.h File Reference
#include "SetupConfiguration.h"
#include "SetupVariable.h"
Include dependency graph for Setup.h:
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Macros

#define SHA256_DIGEST_SIZE 32
SHA-256 digest size in bytes.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Setup.h.


IceLake Platform Sample Code: SetupConfiguration.h File Reference

SetupConfiguration.h File Reference

Default platform setup configuration settings. More...

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Detailed Description

Default platform setup configuration settings.

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SetupConfiguration.h.


IceLake Platform Sample Code: SetupVariable.h File Reference

Macros
SetupVariable.h File Reference
#include <PchLimits.h>
Include dependency graph for SetupVariable.h:
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Macros

#define | SETUP_DATA_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | CPU_SETUP_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | ME_SETUP_REVISION 2
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | SA_SETUP_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | PCH_SETUP_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | SI_SETUP_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SetupVariable.h.

Macro Definition Documentation

#define ME_SETUP_REVISION 2

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Add MctpBroadcastCycle

Definition at line 1295 of file SetupVariable.h.

#define SI_SETUP_REVISION 1

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table.

Revision 1: - Initial version.

Definition at line 2244 of file SetupVariable.h.


IceLake Platform Sample Code: SiliconPolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
SiliconPolicyInitDxe.c File Reference

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation. More...

#include <SiliconPolicyInitDxe.h>
#include <Library/BaseLib.h>
Include dependency graph for SiliconPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS SiliconPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel Cpu DXE Platform Policy. More...

Detailed Description

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file SiliconPolicyInitDxe.c.

Function Documentation

EFI_STATUS SiliconPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel Cpu DXE Platform Policy.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Install the DXE_SI_POLICY_PROTOCOL interface

Definition at line 51 of file SiliconPolicyInitDxe.c.


IceLake Platform Sample Code: SiliconPolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
SiliconPolicyInitDxe.h File Reference

Header file for the SiliconPolicyInitDxe Driver. More...

#include <Protocol/FirmwareVolume2.h>
#include <Guid/StatusCodeDataTypeId.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Protocol/SiPolicyProtocol.h>
Include dependency graph for SiliconPolicyInitDxe.h:
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Functions

EFI_STATUS SiliconPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy. More...

Detailed Description

Header file for the SiliconPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file SiliconPolicyInitDxe.h.

Function Documentation

EFI_STATUS SiliconPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Install the DXE_SI_POLICY_PROTOCOL interface

Definition at line 51 of file SiliconPolicyInitDxe.c.


IceLake Platform Sample Code: SioRegs.h File Reference

SioRegs.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SioRegs.h.


IceLake Platform Sample Code: SmbiosPlatformInfoDefault.h File Reference

Macros
SmbiosPlatformInfoDefault.h File Reference

This file contains Default data for Platform SMBIOS tables. More...

#include <SmbiosPlatformInfoDefinition.h>
#include <../Features/Smbios/SmbiosMiscDxe/SmbiosMiscStrings.h>
Include dependency graph for SmbiosPlatformInfoDefault.h:

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Macros

#define | DEFAULT_BIOSVENDOR_CHARS { 0,0,0,0,0,0,1,0,0,0,1,1,0,0,1,1,0,0,1,0,0,0,0,0,0,1,1,1,1,0,0,0 }
MISC_BIOS_CHARACTERISTICS.BiosCharacteristics Bit0-1 Reserved1, Bit02 Unknown, Bit03 BiosCharacteristicsNotSupported, Bit04 IsaIsSupported, Bit05 McaIsSupported, Bit06 EisaIsSupported, Bit07 PciIsSupported, Bit08 PcmciaIsSupported, Bit09 PlugAndPlayIsSupported, Bit10 ApmIsSupported, Bit11 BiosIsUpgradable, Bit12 BiosShadowingAllowed, Bit13 VLVesaIsSupported, Bit14 EscdSupportIsAvailable, Bit15 BootFromCdIsSupported Bit16 SelectableBootIsSupported, Bit17 RomBiosIsSocketed, Bit18 BootFromPcmciaIsSupported, Bit19 EDDSpecificationIsSupported, Bit20 JapaneseNecFloppyIsSupported, Bit21 JapaneseToshibaFloppyIsSupported, Bit22 Floppy525_360IsSupported, Bit23 Floppy525_12IsSupported, Bit24 Floppy35_720IsSupported, Bit25 Floppy35_288IsSupported, Bit26 PrintScreenIsSupported, Bit27 Keyboard8042IsSupported, Bit28 SerialIsSupported, Bit29 PrinterIsSupported, Bit30 CgaMonoIsSupported, Bit31 NecPc98, Bit32-63 Reserved for BIOS/System Vendor.
#define | DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS (UINT8)(BIT0 | BIT1 | BIT4 | BIT5)
MISC_BIOS_CHARACTERISTICS_EXTENSION.BiosReserved Bit0 AcpiIsSupported, Bit1 UsbLegacyIsSupported, Bit2 AgpIsSupported, Bit3 I20BootIsSupported, Bit4 Ls120BootIsSupported, Bit5 AtapiZipDriveBootIsSupported, Bit6 Boot1394IsSupported, Bit7 SmartBatteryIsSupported.
#define | DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM (UINT8)(BIT0 | BIT1 | BIT2 | BIT3)
MISC_BIOS_CHARACTERISTICS_EXTENSION.SystemReserved Bit0 BiosBootSpecIsSupported, Bit1 FunctionKeyNetworkBootIsSupported, Bit2 TargetContentDistributionEnabled, Bit3 UefiSpecificationSupported, Bit4 VirtualMachineSupported, Bit5-7 ExtensionByte2Reserved.

Detailed Description

This file contains Default data for Platform SMBIOS tables.

This file should not be altered unless update in SMBIOS Specification.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file SmbiosPlatformInfoDefault.h.


IceLake Platform Sample Code: SmbiosPlatformInfoDefinition.h File Reference

SmbiosPlatformInfoDefinition.h File Reference

This file contains definition for Platform SMBIOS Info. More...

#include <IndustryStandard/SmBios.h>
Include dependency graph for SmbiosPlatformInfoDefinition.h:
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Detailed Description

This file contains definition for Platform SMBIOS Info.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file SmbiosPlatformInfoDefinition.h.


IceLake Platform Sample Code: SmmCpuSaveState.h File Reference

  • Protocol
Classes
SmmCpuSaveState.h File Reference

This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors. More...

Go to the source code of this file.

Classes

struct | EFI_SMM_CPU_STATE32
CPU save-state strcuture for IA32 and X64. More...
struct | EFI_SMM_CPU_STATE64
This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. More...
union | EFI_SMM_CPU_STATE
Union of CPU save-state strcutures for IA32 and X64. More...
struct | _EFI_SMM_CPU_SAVE_STATE_PROTOCOL
Provides a programatic means to access SMM save state. More...

Detailed Description

This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification
This Protocol is defined in Framework of EFI SMM Core Interface Spec Version 0.91.

Definition in file SmmCpuSaveState.h.


IceLake Platform Sample Code: SmmStmConfTable.h File Reference

Macros | Typedefs
SmmStmConfTable.h File Reference

GUID definition for the Smm Stm Configuraion Table. More...

#include <Protocol/SmmTxtResource.h>
Include dependency graph for SmmStmConfTable.h:

Go to the source code of this file.

Macros

#define STM_OPT_OUT 0
Definitions.

Typedefs

typedef struct _SMM_ENTRY_INIT_STRUCT SMM_ENTRY_INIT_STRUCT
STM Configuration Table.

Detailed Description

GUID definition for the Smm Stm Configuraion Table.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SmmStmConfTable.h.


IceLake Platform Sample Code: SmmStmConfTableLib.h File Reference

  • Library
Functions
SmmStmConfTableLib.h File Reference

Txt Protocol definition include file. More...

Go to the source code of this file.

Functions

EFI_STATUS | SmmStmConfTableInit (IN EFI_SYSTEM_TABLE *SystemTable)
BIOS must updated the value depends on how CPU driver designs. More...
UINT64 | GetMsegSize (VOID)
Get Mseg Size. More...
VOID | FillMseg (IN UINT32 Base, IN UINT32 Size)
Fill Mseg Base/Size to TxtHobInfo. More...
VOID | FillTseg (IN UINT32 Base, IN UINT32 Size)
Fill Tseg Base/Size to TxtHobInfo. More...

Detailed Description

Txt Protocol definition include file.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SmmStmConfTableLib.h.

Function Documentation

VOID FillMseg | ( | IN UINT32 | Base,
 |  | IN UINT32 | Size
 | ) |  |

Fill Mseg Base/Size to TxtHobInfo.

Parameters
[in] | Base | Mseg base address
[in] | Size | Mseg Size
VOID FillTseg | ( | IN UINT32 | Base,
 |  | IN UINT32 | Size
 | ) |  |

Fill Tseg Base/Size to TxtHobInfo.

Parameters
[in] | Base | Mseg base address
[in] | Size | Mseg Size
UINT64 GetMsegSize ( VOID )

Get Mseg Size.

Return values
Size Get Mseg Size
EFI_STATUS SmmStmConfTableInit ( IN EFI_SYSTEM_TABLE * SystemTable )

BIOS must updated the value depends on how CPU driver designs.

STM library Initial Entry

Parameters
[in] SystemTable A pointer to the EFI System Table
Return values
EFI_SUCCESS | If TXT initialization succeed
EFI_UNLOAD_IMAGE | If TXT criterias are not met


IceLake Platform Sample Code: SmmTxtResource.h File Reference

  • Protocol
Macros | Typedefs
SmmTxtResource.h File Reference

This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM. More...

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Macros

#define END_OF_RESOURCES 0
Resource definitions.

Typedefs

typedef union _RESOURCE | RESOURCE
Resource database header.
typedef EFI_STATUS(* | STM_MAP_ADDRESS_RANGE) (STM_MAP_ADDRESS_RANGE_DESCRIPTOR *Buf)
Member functions.

Detailed Description

This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SmmTxtResource.h.


IceLake Platform Sample Code: SmmTxtStmService.h File Reference

  • Protocol
SmmTxtStmService.h File Reference

This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM. More...

Go to the source code of this file.

Detailed Description

This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SmmTxtStmService.h.


IceLake Platform Sample Code: SoftwareGuardSetupData.h File Reference

Classes | Typedefs
SoftwareGuardSetupData.h File Reference

Software Guard Setup Variables and Structures. More...

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Classes

struct | EPC_OS_CONFIG
EPC data structure for OS Variable. More...
struct | _EPC_BIOS_CONFIG
EPC data structure for BIOS Variable. More...
struct | SOFTWARE_GUARD_STATUS
Data structure for SGX Policy Status The presence of this variable implies that SGX is supported For backward compatibility: Absence of this variable implies that SGX is supported and defaulted to 'Software Controlled'. More...

Typedefs

typedef struct _EPC_BIOS_CONFIG EPC_BIOS_CONFIG
EPC data structure for BIOS Variable.

Detailed Description

Software Guard Setup Variables and Structures.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SoftwareGuardSetupData.h.


IceLake Platform Sample Code: SpiFlashCommon.h File Reference

  • Library
Functions
SpiFlashCommon.h File Reference

The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/Spi.h>
Include dependency graph for SpiFlashCommon.h:

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Functions

EFI_STATUS | SpiFlashLock (VOID)
Enable block protection on the Serial Flash device. More...
EFI_STATUS | SpiFlashRead (IN UINTN Address, IN OUT UINT32 *NumBytes, OUT UINT8 *Buffer)
Read NumBytes bytes of data from the address specified by PAddress into Buffer. More...
EFI_STATUS | SpiFlashWrite (IN UINTN Address, IN OUT UINT32 *NumBytes, IN UINT8 *Buffer)
Write NumBytes bytes of data from Buffer to the address specified by PAddresss. More...
EFI_STATUS | SpiFlashBlockErase (IN UINTN Address, IN UINTN *NumBytes)
Erase the block starting at Address. More...

Detailed Description

The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SpiFlashCommon.h.

Function Documentation

EFI_STATUS SpiFlashBlockErase | ( | IN UINTN | Address,
 |  | IN UINTN * | NumBytes
 | ) |  |

Erase the block starting at Address.

Parameters
[in] | Address | The starting physical address of the block to be erased. This library assume that caller garantee that the PAddress is at the starting address of this block.
[in] | NumBytes | On input, the number of bytes of the logical block to be erased. On output, the actual number of bytes erased.
Return values
EFI_SUCCESS. | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.
EFI_STATUS SpiFlashLock ( VOID )

Enable block protection on the Serial Flash device.

Return values
EFI_SUCCESS | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.
EFI_STATUS SpiFlashRead | ( | IN UINTN | Address,
 |  | IN OUT UINT32 * | NumBytes,
 |  | OUT UINT8 * | Buffer
 | ) |  |

Read NumBytes bytes of data from the address specified by PAddress into Buffer.

Parameters
[in] | Address | The starting physical address of the read.
[in,out] | NumBytes | On input, the number of bytes to read. On output, the number of bytes actually read.
[out] | Buffer | The destination data buffer for the read.
Return values
EFI_SUCCESS | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.
EFI_STATUS SpiFlashWrite | ( | IN UINTN | Address,
 |  | IN OUT UINT32 * | NumBytes,
 |  | IN UINT8 * | Buffer
 | ) |  |

Write NumBytes bytes of data from Buffer to the address specified by PAddresss.

Parameters
[in] | Address | The starting physical address of the write.
[in,out] | NumBytes | On input, the number of bytes to write. On output, the actual number of bytes written.
[in] | Buffer | The source data buffer for the write.
Return values
EFI_SUCCESS | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.


IceLake Platform Sample Code: StmDefinition.h File Reference

Macros
StmDefinition.h File Reference

This file contains definitions required to use the TXT STM. More...

Go to the source code of this file.

Macros

#define | MSR_PLATFORM_INFORMATION 0x000000CE
MSR definitions.
#define | SMM_SUCCESS 0
STM Definitions. More...
#define | SW_SMI_STM_GET_BIOS_AC_STATUS_CMD 0x10
API values.

Detailed Description

This file contains definitions required to use the TXT STM.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file StmDefinition.h.

Macro Definition Documentation

#define SMM_SUCCESS 0

STM Definitions.

Errors

Definition at line 69 of file StmDefinition.h.


IceLake Platform Sample Code: Swbpe.h File Reference

Swbpe.h File Reference
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Swbpe.h.


IceLake Platform Sample Code: SysFwUpdatePlatformProtocol.h File Reference

  • Protocol
SysFwUpdatePlatformProtocol.h File Reference

Define the data structure and GUID of SysFwUpdatePlatform Protocol. More...

Go to the source code of this file.

Detailed Description

Define the data structure and GUID of SysFwUpdatePlatform Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SysFwUpdatePlatformProtocol.h.


IceLake Platform Sample Code: SystemMonitor.h File Reference

  • Protocol
SystemMonitor.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SystemMonitor.h.


IceLake Platform Sample Code: SystemNvDataGuid.h File Reference

  • Guid
SystemNvDataGuid.h File Reference
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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SystemNvDataGuid.h.


IceLake Platform Sample Code: TbtPolicyInitDxe.c File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
TbtPolicyInitDxe.c File Reference

This file is SampleCode for TBT DXE Policy initialization. More...

#include "TbtPolicyInitDxe.h"
Include dependency graph for TbtPolicyInitDxe.c:

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Functions

EFI_STATUS TbtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize TBT DXE Policy. More...

Detailed Description

This file is SampleCode for TBT DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TbtPolicyInitDxe.c.

Function Documentation

EFI_STATUS TbtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize TBT DXE Policy.

TBT DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file TbtPolicyInitDxe.c.

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IceLake Platform Sample Code: TbtPolicyInitDxe.h File Reference

  • PlatformInit
  • PolicyInitDxe
Functions
TbtPolicyInitDxe.h File Reference

Header file for the TbtPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/TbtPolicy.h>
#include <Library/DxeTbtPolicyLib.h>
#include <Library/DxeTbtPolicyUpdateLib.h>
Include dependency graph for TbtPolicyInitDxe.h:
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Functions

EFI_STATUS TbtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
TBT DXE Policy Driver Entry Point
More...

Detailed Description

Header file for the TbtPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TbtPolicyInitDxe.h.

Function Documentation

EFI_STATUS TbtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

TBT DXE Policy Driver Entry Point

  • Introduction
    TBT DXE drivers behavior can be controlled by platform policy without modifying reference code directly. Platform policy Protocol is initialized with default settings in this funciton. This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
  • Precondition
    • Runtime variable service should be ready if policy initialization required.
  • Returns
    TBT_POLICY_PROTOCOL will be installed successfully and ready for TBT reference code use.
  • Porting Recommendations
    Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
Parameters
[in] ImageHandle - Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

TBT DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file TbtPolicyInitDxe.c.

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IceLake Platform Sample Code: Tcg.h File Reference

  • Library
Typedefs
Tcg.h File Reference

TCG defined values and structures used by the Tcg Core library. More...

#include <Base.h>
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Typedefs

typedef UINT64 TcgUid
UID in host native byte order.

Detailed Description

TCG defined values and structures used by the Tcg Core library.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Tcg.h.


IceLake Platform Sample Code: Tcg2ConfigHii.h File Reference

  • Guid
Tcg2ConfigHii.h File Reference

GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver. More...

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Detailed Description

GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Tcg2ConfigHii.h.


IceLake Platform Sample Code: Tcg2ConfigNvData.h File Reference

Tcg2ConfigNvData.h File Reference

Header file for NV data structure definition. More...

#include <Guid/HiiPlatformSetupFormset.h>
#include <Guid/Tcg2ConfigHii.h>
#include <IndustryStandard/TcgPhysicalPresence.h>
#include <Guid/PttInstance.h>
#include <Guid/PttPTPInstanceGuid.h>
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Detailed Description

Header file for NV data structure definition.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Tcg2ConfigNvData.h.


IceLake Platform Sample Code: Tcg2PhysicalPresenceLib.h File Reference

  • Library
Functions
Tcg2PhysicalPresenceLib.h File Reference

Ihis library is intended to be used by BDS modules. More...

#include <IndustryStandard/Tpm20.h>
#include <IndustryStandard/TcgPhysicalPresence.h>
#include <Protocol/Tcg2Protocol.h>
Include dependency graph for Tcg2PhysicalPresenceLib.h:

Go to the source code of this file.

Functions

VOID | Tcg2PhysicalPresenceLibProcessRequest (IN TPM2B_AUTH *PlatformAuth OPTIONAL)
Check and execute the pending TPM request. More...
BOOLEAN | Tcg2PhysicalPresenceLibNeedUserConfirm (VOID)
Check if the pending TPM request needs user input to confirm. More...
UINT32 | Tcg2PhysicalPresenceLibGetManagementFlags (VOID)
Return TPM2 ManagementFlags set by PP interface. More...
UINT32 | Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction (OUT UINT32 *MostRecentRequest, OUT UINT32 *Response)
The handler for TPM physical presence function: Return TPM Operation Response to OS Environment. More...
UINT32 | Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction (IN UINT32 OperationRequest, IN UINT32 RequestParameter)
The handler for TPM physical presence function: Submit TPM Operation Request to Pre-OS Environment and Submit TPM Operation Request to Pre-OS Environment 2. More...
UINT32 | Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction (IN UINT32 OperationRequest)
The handler for TPM physical presence function: Get User Confirmation Status for Operation. More...

Detailed Description

Ihis library is intended to be used by BDS modules.

This library will execute TPM2 request.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Tcg2PhysicalPresenceLib.h.

Function Documentation

UINT32 Tcg2PhysicalPresenceLibGetManagementFlags ( VOID )

Return TPM2 ManagementFlags set by PP interface.

Return values
ManagementFlags TPM2 Management Flags.
UINT32 Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction ( IN UINT32 OperationRequest )

The handler for TPM physical presence function: Get User Confirmation Status for Operation.

This API should be invoked in OS runtime phase to interface with ACPI method.

Caution: This function may receive untrusted input.

Parameters
[in] OperationRequest TPM physical presence operation request.
Returns
Return Code for Get User Confirmation Status for Operation.
BOOLEAN Tcg2PhysicalPresenceLibNeedUserConfirm ( VOID )

Check if the pending TPM request needs user input to confirm.

The TPM request may come from OS. This API will check if TPM request exists and need user input to confirmation.

Return values
TRUE | TPM needs input to confirm user physical presence.
FALSE | TPM doesn't need input to confirm user physical presence.
VOID Tcg2PhysicalPresenceLibProcessRequest ( IN TPM2B_AUTH *PlatformAuth OPTIONAL )

Check and execute the pending TPM request.

The TPM request may come from OS or BIOS. This API will display request information and wait for user confirmation if TPM request exists. The TPM request will be sent to TPM device after the TPM request is confirmed, and one or more reset may be required to make TPM request to take effect.

This API should be invoked after console in and console out are all ready as they are required to display request information and get user input to confirm the request.

Parameters
PlatformAuth platform auth value. NULL means no platform auth change.
UINT32 Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction | ( | OUT UINT32 * | MostRecentRequest,
 |  | OUT UINT32 * | Response
 | ) |  |

The handler for TPM physical presence function: Return TPM Operation Response to OS Environment.

This API should be invoked in OS runtime phase to interface with ACPI method.

Parameters
[out] | MostRecentRequest | Most recent operation request.
[out] | Response | Response to the most recent operation request.
Returns
Return Code for Return TPM Operation Response to OS Environment.
UINT32 Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction | ( | IN UINT32 | OperationRequest,
 |  | IN UINT32 | RequestParameter
 | ) |  |

The handler for TPM physical presence function: Submit TPM Operation Request to Pre-OS Environment and Submit TPM Operation Request to Pre-OS Environment 2.

This API should be invoked in OS runtime phase to interface with ACPI method.

Caution: This function may receive untrusted input.

Parameters
[in] | OperationRequest | TPM physical presence operation request.
[in] | RequestParameter | TPM physical presence operation request parameter.
Returns
Return Code for Submit TPM Operation Request to Pre-OS Environment and Submit TPM Operation Request to Pre-OS Environment 2.


IceLake Platform Sample Code: TcgCore.h File Reference

  • Library
Classes | Typedefs | Enumerations | Functions
TcgCore.h File Reference

Public API for the Tcg Core library to perform the lowest level TCG data encoding. More...

#include <Library/Tcg.h>
Include dependency graph for TcgCore.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...
struct | _TcgParseStruct
Structure that is used to parse the Tcg response received. More...
struct | _TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions. More...

Typedefs

typedef struct _TcgCreateStruct | TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...
typedef struct _TcgParseStruct | TcgParseStruct
Structure that is used to parse the Tcg response received. More...
typedef struct _TcgToken | TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.

Enumerations

enum TcgResult
Tcg result codes. More...

Functions

TcgResult TCG_CALL | tcgInitTcgCreateStruct (TcgCreateStruct *createStruct, void *buffer, UINT32 bufferSize)
Required to be called before calling any other Tcg functions with the TcgCreateStruct. More...
TcgResult TCG_CALL | tcgStartComPacket (TcgCreateStruct *createStruct, UINT16 comId, UINT16 comIdExtension)
Encodes the ComPacket header to the data structure. More...
TcgResult TCG_CALL | tcgStartPacket (TcgCreateStruct *createStruct, UINT32 tsn, UINT32 hsn, UINT32 seqNumber, UINT16 ackType, UINT32 ack)
Starts a new ComPacket in the data structure. More...
TcgResult TCG_CALL | tcgStartSubPacket (TcgCreateStruct *createStruct, UINT16 kind)
Starts a new SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndSubPacket (TcgCreateStruct *createStruct)
Ends the current SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndPacket (TcgCreateStruct *createStruct)
Ends the current Packet in the data structure. More...
TcgResult TCG_CALL | tcgEndComPacket (TcgCreateStruct *createStruct, UINT32 *size)
Ends the ComPacket in the data structure and ret. More...
TcgResult TCG_CALL | tcgAddRawByte (TcgCreateStruct *createStruct, UINT8 byte)
Adds a single raw token byte to the data structure. More...
TcgResult TCG_CALL | tcgAddByteSequence (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN continued)
Adds the data parameter as a byte sequence to the data structure. More...
TcgResult TCG_CALL | tcgAddInteger (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN signedInteger)
Adds an arbitrary-length integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT8 (TcgCreateStruct *createStruct, UINT8 value)
Adds an 8-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT16 (TcgCreateStruct *createStruct, UINT16 value)
Adds a 16-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT32 (TcgCreateStruct *createStruct, UINT32 value)
Adds a 32-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT64 (TcgCreateStruct *createStruct, UINT64 value)
Adds a 64-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddBOOLEAN (TcgCreateStruct *createStruct, BOOLEAN value)
Adds a BOOLEAN to the data structure. More...
TcgResult TCG_CALL | tcgAddTcgUid (TcgCreateStruct *createStruct, TcgUid uid)
Adds a TcgUid to the data structure. More...
TcgResult TCG_CALL | tcgAddStartList (TcgCreateStruct *createStruct)
Adds a Start List token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndList (TcgCreateStruct *createStruct)
Adds an End List token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartName (TcgCreateStruct *createStruct)
Adds a Start Name token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndName (TcgCreateStruct *createStruct)
Adds an End Name token to the data structure. More...
TcgResult TCG_CALL | tcgAddCall (TcgCreateStruct *createStruct)
Adds a Call token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfData (TcgCreateStruct *createStruct)
Adds an End of Data token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfSession (TcgCreateStruct *createStruct)
Adds an End of Session token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartTransaction (TcgCreateStruct *createStruct)
Adds a Start Transaction token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndTransaction (TcgCreateStruct *createStruct)
Adds an End Transaction token to the data structure. More...
TcgResult TCG_CALL | tcgInitTcgParseStruct (TcgParseStruct *parseStruct, const void *buffer, UINT32 bufferSize)
Intializes the parsing structure used to parse the Tcg response. More...
TcgResult TCG_CALL | tcgGetNextToken (TcgParseStruct *parseStruct, TcgToken *tcgToken)
Retrieves next Tcg Token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetNextTokenType (TcgParseStruct *parseStruct, TcgTokenType type)
Retrieves the next TCG token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetAtomInfo (const TcgToken *tcgToken, UINT32 *headerLength, UINT32 *dataLength, UINT8 *byteOrInt, UINT8 *signOrCont)
Retrieves information about a simple token containing an atom. More...
const UINT8 *TCG_CALL | tcgGetTokenByteSequence (const TcgToken *tcgToken, UINT32 *length)
Retrieves byte sequence from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetTokenUINT64 (const TcgToken *tcgToken, UINT64 *value)
Retrieves Integer value up to 64-bits in size from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetNextUINT8 (TcgParseStruct *parseStruct, UINT8 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT16 (TcgParseStruct *parseStruct, UINT16 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT32 (TcgParseStruct *parseStruct, UINT32 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT64 (TcgParseStruct *parseStruct, UINT64 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextBOOLEAN (TcgParseStruct *parseStruct, BOOLEAN *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextTcgUid (TcgParseStruct *parseStruct, TcgUid *uid)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextByteSequence (TcgParseStruct *parseStruct, const void **data, UINT32 *length)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextCall (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfData (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfSession (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...

Detailed Description

Public API for the Tcg Core library to perform the lowest level TCG data encoding.

TCG Core public interface header.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcgCore.h.

Enumeration Type Documentation

enum TcgResult

Tcg result codes.

The result code indicates if the Tcg function call was successful or not

Enumerator
TcgResult_Success

This is the return result upon successful completion of a Tcg function call.

TcgResult_Failure

This is the return "catchall" result for the failure of a Tcg function call.

TcgResult_Failure_NullPointer

This is the return result if a required parameter was Null for a Tcg function call.

TcgResult_Failure_ZeroSize

This is the return result if a required buffersize was 0 for a Tcg function call.

TcgResult_Failure_InvalidAction

This is the return result if a Tcg function call was executed out of order.

For instance, starting a Tcg subpacket before starting its Tcg packet.

TcgResult_Failure_BufferTooSmall

This is the return result if the buffersize provided is not big enough to add a requested Tcg encoded item.

TcgResult_Failure_EndBuffer

This is the return result for a Tcg parse function if the end of the parsed buffer is reached, yet data is still attempted to be retrieved.

For instance, attempting to retrieve another Tcg token from the buffer after it has reached the end of the Tcg subpacket payload.

TcgResult_Failure_InvalidType

This is the return result for a Tcg parse function if the Tcg Token item requested is not the expected type.

For instance, the caller requested to receive an integer and the Tcg token was a byte sequence.

Definition at line 68 of file TcgCore.h.


IceLake Platform Sample Code: TcgSetup.h File Reference

TcgSetup.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcgSetup.h.


IceLake Platform Sample Code: TcgUtil.h File Reference

  • Library
Functions
TcgUtil.h File Reference

Provides TCG high-level API to perform common TCG actions on a TCG data packet. More...

#include <Library/TcgCore.h>
Include dependency graph for TcgUtil.h:

Go to the source code of this file.

Functions

TcgResult TCG_CALL | tcgStartMethodCall (TcgCreateStruct *createStruct, TcgUid invokingId, TcgUid methodId)
Adds start Method Call to the data structure using invoking id and method Id provided. More...
TcgResult TCG_CALL | tcgStartParameters (TcgCreateStruct *createStruct)
Adds start parameters (STARTLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndParameters (TcgCreateStruct *createStruct)
Adds end parameters (ENDLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndMethodCall (TcgCreateStruct *createStruct)
Adds end method call (ENDDATA) to the data structure in addition to the method status list. More...
TcgResult TCG_CALL | tcgCreateStartSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, TcgUid spId, BOOLEAN write, UINT32 hostChallengeLength, const void *hostChallenge, TcgUid HostSigningAuthority)
Adds Start Session call to the data structure. More...
TcgResult TCG_CALL | tcgCreateSetCPin (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid sidRow, const void *password, UINT32 passwordSize)
Creates ComPacket with a Method call that sets the PIN column for the row specified. More...
TcgResult TCG_CALL | tcgSetAuthorityEnabled (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid authorityUid, BOOLEAN enabled)
Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified. More...
TcgResult TCG_CALL | tcgCreateEndSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSession, UINT32 tpSessionId)
Creates ComPacket with EndSession. More...
const char *TCG_CALL | tcgTokenTypeString (TcgTokenType type)
Retrieves human-readable token type name. More...
TcgResult TCG_CALL | tcgGetMethodStatus (const TcgParseStruct *parseStruct, UINT8 *methodStatus)
Returns the method status of the current subpacket. More...
const char *TCG_CALL | tcgMethodStatusString (UINT8 methodStatus)
Returns a human-readable string representing a method status return code. More...
TcgResult TCG_CALL | tcgGetComIds (const TcgParseStruct *parseStruct, UINT16 *comId, UINT16 *comIdExtension)
Retrieves the comID and Extended comID of the ComPacket in the Tcg response. More...
TcgResult TCG_CALL | tcgCheckComIds (const TcgParseStruct *parseStruct, UINT16 expectedComId, UINT16 expectedComIdExtension)
Checks if the ComIDs of the response match the expected values. More...
TcgResult TCG_CALL | tcgParseSyncSession (const TcgParseStruct *parseStruct, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, UINT32 *tperSessionId)
Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID. More...
BOOLEAN TCG_CALL | tcgIsProtocolSupported (const TCG_SUPPORTED_SECURITY_PROTOCOLS *protocolList, UINT16 protocol)
Determines if the protocol provided is part of the provided supported protocol list. More...
BOOLEAN TCG_CALL | tcgIsLocked (const TCG_LEVEL0_DISCOVERY_HEADER *discovery)
Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response. More...

Detailed Description

Provides TCG high-level API to perform common TCG actions on a TCG data packet.

TCG Core utility public interface header.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcgUtil.h.


IceLake Platform Sample Code: TcoWdtHob.h File Reference

  • Guid
TcoWdtHob.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcoWdtHob.h.


IceLake Platform Sample Code: TxtOneTouch.h File Reference

  • Guid
TxtOneTouch.h File Reference

This file contains definitions required for One-Touch function. More...

Go to the source code of this file.

Detailed Description

This file contains definitions required for One-Touch function.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TxtOneTouch.h.


IceLake Platform Sample Code: TxtOneTouchOp.h File Reference

  • Protocol
Typedefs
TxtOneTouchOp.h File Reference

Txt specific PPI operation definition. More...

Go to the source code of this file.

Typedefs

typedef EFI_STATUS(* TXT_RESET_SYSTEM) (IN TXT_ONE_TOUCH_OP_PROTOCOL *This, IN UINT8 Command)
Reset system. More...

Detailed Description

Txt specific PPI operation definition.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TxtOneTouchOp.h.

Typedef Documentation

typedef EFI_STATUS( * TXT_RESET_SYSTEM) (IN TXT_ONE_TOUCH_OP_PROTOCOL *This, IN UINT8 Command)

Reset system.

Parameters
[in] | This | - Point of TXT_ONE_TOUCH_OP_PROTOCOL
[in] | Command | - Operation value for TxT
Return values
EFI_SUCCESS - Always return EFI_SUCCESS

Definition at line 83 of file TxtOneTouchOp.h.


IceLake Platform Sample Code: typedef.h File Reference

  • Library
Macros
typedef.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define FORWARD_DECLARATION(x) typedef struct _##x x
Declare a structure before it is used to allow of structure pointers within the structure.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file typedef.h.


IceLake Platform Sample Code: UsbDeviceLib.h File Reference

  • Library
UsbDeviceLib.h File Reference

Header file for USBFN library definition. More...

#include <Uefi.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/UsbIo.h>
Include dependency graph for UsbDeviceLib.h:
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Detailed Description

Header file for USBFN library definition.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file UsbDeviceLib.h.


IceLake Platform Sample Code: UsbDeviceModeProtocol.h File Reference

  • Protocol
Classes | Macros
UsbDeviceModeProtocol.h File Reference

Header file for definition of USBFN device mode protocol. More...

#include <Library/UsbDeviceLib.h>
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Classes

struct _EFI_USB_DEVICE_MODE_PROTOCOL
Usb Device Mode Protocol Structure. More...

Macros

#define EFI_USB_DEVICE_MODE_PROTOCOL_GUID {0xC9923F7E, 0x1746, 0x4802, { 0x86, 0x2e, 0x1, 0x1c, 0x2c, 0x2d, 0x9d, 0x86 } }
UsbDeviceMode Protocol GUID.

Detailed Description

Header file for definition of USBFN device mode protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file UsbDeviceModeProtocol.h.


IceLake Platform Sample Code: ver.h File Reference

  • Library
Classes | Macros | Typedefs
ver.h File Reference

Contains definitions of the MAJOR, MINOR, & HOTFIX versions used throughout the code. More...

#include "Build.h"
#include "typedef.h"
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Classes

struct _VERSION
Defines a generic version structure used in the software build process. More...

Macros

#define | VER_MAJOR 11
Major Version.
#define | VER_MAJOR_STR "11"
Major Version String.
#define | VER_MINOR 5
Minor Version.
#define | VER_MINOR_STR "5"
Minor Version String.
#define | VER_HOTFIX 0
Default Hotfix Version.
#define | VER_HOTFIX_STR "0"
Default Hotfix Version String.
#define | VER_SEPARATOR_STR "."
Separator String used between major, minor, hotfix and build strings.
#define | VER_DEBUG_TAG
Define string that is attached to version string when release build.
#define | VERSION_STR VER_MAJOR_STR VER_SEPARATOR_STR VER_MINOR_STR VER_SEPARATOR_STR VER_HOTFIX_STR VER_SEPARATOR_STR VER_BUILD_STR VER_DEBUG_TAG
Combined file version information.
#define | CURRENT_YEAR_STRING "2015"
Adding the current year date string for use in updating the year component of the displayed copyright message. More...

Typedefs

typedef struct _VERSION VERSION
Defines a generic version structure used in the software build process. More...

Detailed Description

Contains definitions of the MAJOR, MINOR, & HOTFIX versions used throughout the code.

Author
Christopher Spiegel and John Traver
Copyright
INTEL CONFIDENTIAL Copyright 2005 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file ver.h.

Macro Definition Documentation

#define CURRENT_YEAR_STRING "2015"

Adding the current year date string for use in updating the year component of the displayed copyright message.

the string needs to be the full 4 char value without spaces or special characters. For example: "2012"

Definition at line 101 of file ver.h.

Typedef Documentation

typedef struct _VERSION VERSION

Defines a generic version structure used in the software build process.

This structure will be used to represent versions of ROM, FW and Recovery modules.


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- _ -

  • _FWUPD_POWER_SOURCE : FWUpdateLib.h


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- a -

  • AcpiGnvsInit() : DxeAcpiGnvsInitLib.h
  • AES_BLOCK_SIZE : BaseCryptLib.h
  • AesCbcDecrypt() : BaseCryptLib.h
  • AesCbcEncrypt() : BaseCryptLib.h
  • AesEcbDecrypt() : BaseCryptLib.h
  • AesEcbEncrypt() : BaseCryptLib.h
  • AesGetContextSize() : BaseCryptLib.h
  • AesInit() : BaseCryptLib.h
  • ALIGNMENT : MultiPlatSupport.h
  • AllocateMemoryBelow4G() : AcpiPlatform.c
  • AmtPolicyInitDxe() : AmtPolicyInitDxe.c , AmtPolicyInitDxe.h
  • Arc4Decrypt() : BaseCryptLib.h
  • Arc4Encrypt() : BaseCryptLib.h
  • Arc4GetContextSize() : BaseCryptLib.h
  • Arc4Init() : BaseCryptLib.h
  • Arc4Reset() : BaseCryptLib.h


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- b -

  • BiosGuardHobInit() : PlatformInit.c
  • BOARD_INIT_PREMEM_ENTRY : PlatformPostCode.h
  • BootGuardOemRevocationHook() : BootGuardRevocationLib.h
  • BuildDebugConfigDataHob() : PlatformInitPreMem.c


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- c -

  • CHECK_PATTERN : SdCard.h
  • CheckLidBaseEcProtocolVersion() : EcPlatformInitDxe.c , PlatformInitDxe.h
  • CheckOddParity() : PlatformInitPreMem.c
  • CheckSataRaidMode() : BasePlatformVariableLib.h
  • ClearDiagnosticStatus() : PlatformNvRamHookLib.h
  • ClearTenSecPwrButtonMode() : EcMiscLib.h
  • CPU_SETUP_REVISION : SetupVariable.h
  • CpuDxePrintPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuInstallPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuPolicyInitDxe() : CpuPolicyInitDxe.c , CpuPolicyInitDxe.h
  • CreateAttemptUsbFirstHotkeyInfoHob() : PlatformInit.c
  • CreateBootguardEventLogEntries() : PeiBootGuardEventLogLib.h
  • CreateDefaultVariableHob() : MultiPlatSupportLib.h
  • CreateFastBootHob() : PlatformInitPreMem.c
  • CreateSgxInfoForOs() : PlatformInitDxe.c
  • CURRENT_YEAR_STRING : ver.h


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- d -

  • DEFAULT_BIOSVENDOR_CHARS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM : SmbiosPlatformInfoDefault.h
  • DetectBootMode() : PlatformInitPreMem.c
  • DetectEc() : EcLib.h
  • DetectEcRevision() : EcMiscLib.h
  • DetectPmicVendorID() : EcMiscLib.h
  • DevicePathToStr() : DxePlatformBootManagerLib.h
  • DfctFastChargingMode() : EcMiscLib.h
  • DhComputeKey() : BaseCryptLib.h
  • DhFree() : BaseCryptLib.h
  • DhGenerateKey() : BaseCryptLib.h
  • DhGenerateParameter() : BaseCryptLib.h
  • DhNew() : BaseCryptLib.h
  • DhSetParameter() : BaseCryptLib.h
  • DisableBiosLockForPeiWriteVariable() : PlatformInit.c
  • DisableEcSmiMode() : EcMiscLib.h
  • DisablePchDtsReading() : EcMiscLib.h
  • DisplayDimmPopulationErrMsg() : SaPlatformInitDxe.c


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- e -

  • EarlyPlatformPchInit() : PlatformInitPreMem.c
  • EC_GETWAKE_STATUS : PlatformInitPreMem.c
  • EC_REAL_BAT1_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT1_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT1_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT1_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT2_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT2_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT_CHARGING_MASK : BaseEcFlashLib.h
  • EC_REAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_STATUS : BaseEcFlashLib.h
  • EcForceResetAfterAcRemoval() : EcMiscLib.h
  • EcInterface() : EcLib.h
  • EcReset() : EcMiscLib.h
  • EcResetEcInNormalMode() : EcMiscLib.h
  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION : I2cBusConfigurationManagement.h
  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL : I2cBusConfigurationManagement.h
  • EFI_I2C_MASTER_BUS_FREQUENCY_SET : I2cMaster.h
  • EFI_I2C_MASTER_PROTOCOL : I2cMaster.h
  • EFI_I2C_MASTER_RESET : I2cMaster.h
  • EFI_I2C_MASTER_START_REQUEST : I2cMaster.h
  • EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE : SdHostIo.h
  • EFI_USB_DEVICE_MODE_PROTOCOL_GUID : UsbDeviceModeProtocol.h
  • EFI_USBFN_IO_ABORT_TRANSFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS : EfiUsbFnIo.h
  • EFI_USBFN_IO_DETECT_PORT : EfiUsbFnIo.h
  • EFI_USBFN_IO_EVENTHANDLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_FREE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_DEVICE_INFO : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_MAXTRANSFER_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_START_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_STOP_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_TRANSFER : EfiUsbFnIo.h
  • EnableEcAcpiMode() : EcMiscLib.h
  • EnableLanPower() : EcMiscLib.h
  • EnableSataPort2Power() : EcMiscLib.h
  • END_OF_RESOURCES : SmmTxtResource.h
  • EndofDxeCallback() : PlatformInitDxe.c
  • EPC_BIOS_CONFIG : SoftwareGuardSetupData.h
  • EPC_FRACTION_NUMERATOR : PlatformInitDxe.c
  • ExitLowPowerMode() : EcMiscLib.h
  • ExpandPartitionsDevPath() : DxePlatformBootManagerLib.h


IceLake Platform Sample Code: File Members

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- f -

  • FillMseg() : SmmStmConfTableLib.h
  • FillTseg() : SmmStmConfTableLib.h
  • FORWARD_DECLARATION : typedef.h
  • FWU_CONFIRM_LIVE_PING_MSG : Fwu_Common.h
  • FWU_DATA_MSG : Fwu_Common.h
  • FWU_END_MESSAGE : Fwu_Common.h
  • FWU_FLASH_IMAGE_START_MSG_REPLY : Fwu_Common.h
  • FWU_GET_FEATURE_STATE_MSG_REPLY : Fwu_Common.h
  • FWU_GET_FWU_INFO_STATUS_MSG : Fwu_Common.h
  • FWU_GET_INFO_MSG : Fwu_Common.h
  • FWU_GET_IPU_PT_ATTRB_MSG : Fwu_Common.h
  • FWU_GET_OEMID_MSG_REPLY : Fwu_Common.h
  • FWU_GET_PLATFORM_TYPE_MSG_REPLY : Fwu_Common.h
  • FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE : Fwu_Common.h
  • FWU_GET_RESTORE_POINT_IMAGE_MESSAGE : Fwu_Common.h
  • FWU_GET_UPDATE_DATA_EXTENSION_MSG : Fwu_Common.h
  • FWU_GET_VERSION_MSG_REPLY : Fwu_Common.h
  • FWU_IMAGE_COMPATABILITY_CHECK_MSG : Fwu_Common.h
  • FWU_INVALID_MSG_REPLY : Fwu_Common.h
  • FWU_START_MSG : Fwu_Common.h
  • FWU_VERIFY_OEMID_MSG : Fwu_Common.h
  • FWU_VERIFY_PWD_MSG : Fwu_Common.h
  • FWUPD_POWER_SOURCE_AC : FWUpdateLib.h
  • FWUPD_POWER_SOURCE_DC : FWUpdateLib.h
  • FWUPD_POWER_SOURCE_UNKOWN : FWUpdateLib.h


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- g -

  • GetBaseEcFwVersion() : EcMiscLib.h
  • GetBatteryNumber() : EcMiscLib.h
  • GetBoardConfig() : BoardConfigLib.h
  • GetBoardInfo() : EcMiscLib.h
  • GetBootFlagStatus() : PlatformNvRamHookLib.h
  • GetCsmControlStatus() : PlatformInitPreMem.c
  • GetEc2EcProtocolVersion() : EcMiscLib.h
  • GetEcGpeNumber() : AcpiPlatform.c
  • GetFanSpeed() : EcMiscLib.h
  • GetHotkeyScanCode() : EcMiscLib.h
  • GetMsegSize() : SmmStmConfTableLib.h
  • GetPcieDockStatus() : EcMiscLib.h
  • GetPlatformDockStatus() : GopPolicyInitDxe.c
  • GetPlatformLidStatus() : GopPolicyInitDxe.c
  • GetPostCodeBreak() : PlatformNvRamHookLib.h
  • GetRtc3Address() : PlatformNvRamHookLib.h
  • GetSimpleBootFlag() : PlatformInitPreMem.c
  • GetTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • GetTxtAliasCheckAndReset() : PlatformNvRamHookLib.h
  • GetVariableFromHob() : MultiPlatSupportLib.h
  • GetVbtData() : GopPolicyInitDxe.c
  • GetWakeupEventAndSaveToHob() : PlatformInitPreMem.c
  • gMmioDeviceList : I2cMmioConfigLib.h
  • GopPolicyInitDxe() : GopPolicyInitDxe.h , GopPolicyInitDxe.c
  • GpioExpBulkConfig() : GpioExpanderLib.h
  • GpioExpGetController() : GpioExpanderLib.h
  • GpioExpGetInput() : GpioExpanderLib.h
  • GpioExpSetDirection() : GpioExpanderLib.h
  • GpioExpSetOutput() : GpioExpanderLib.h
  • GpioExpSetPolarity() : GpioExpanderLib.h
  • GuidStringToAcpiBuffer() : AcpiPlatform.c


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- h -

  • HEADER_ALIGNMENT : MultiPlatSupport.h
  • HeciPlatformDebugCapabilityMsgCallback() : MePolicyInitDxe.h
  • HmacMd5Duplicate() : BaseCryptLib.h
  • HmacMd5Final() : BaseCryptLib.h
  • HmacMd5GetContextSize() : BaseCryptLib.h
  • HmacMd5Init() : BaseCryptLib.h
  • HmacMd5Update() : BaseCryptLib.h
  • HmacSha1Duplicate() : BaseCryptLib.h
  • HmacSha1Final() : BaseCryptLib.h
  • HmacSha1GetContextSize() : BaseCryptLib.h
  • HmacSha1Init() : BaseCryptLib.h
  • HmacSha1Update() : BaseCryptLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- i -

  • ICH_ACPI_TIMER_MAX_VALUE : PlatformSmmIoLib.h
  • In8042AuxData() : AcpiPlatform.c
  • InitializeGfxInt15() : GfxInt15Interface.c
  • InitializeRecovery() : PeiPlatformRecoveryLib.h
  • InstallAcpiPlatform() : AcpiPlatform.c , AcpiPlatform.h
  • InstallXhciAcpiTable() : AcpiPlatform.c
  • IOMReadyNotifyToEC() : PlatformInit.c
  • IsBootWithNoChange() : PlatformInitPreMem.c
  • IsChecksumBad() : PlatformNvRamHookLib.h
  • IsFastBootEnabled() : PlatformInitPreMem.c
  • IsHardwareChange() : AcpiPlatform.c
  • IsItPartitionsDevicePath() : DxePlatformBootManagerLib.h
  • IsOverclockingEnabled() : PlatformInitPreMem.c
  • IsPowerButtonOverride() : PlatformInitPreMem.c
  • IsPreviousBootSuccessful() : PlatformInitPreMem.c
  • IsPs2MouseConnected() : AcpiPlatform.h , AcpiPlatform.c
  • IsTimeOutOccurred() : PlatformInitPreMem.c
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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Here is a list of all documented file members with links to the documentation:

- l -

  • LoadRealModeFile() : GfxInt15Interface.c
  • LocateSupportProtocol() : AcpiPlatform.c , AcpiPlatform.h
  • LpcEcResetEcInNormalMode() : EcLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- m -

  • mBootModePriority : PlatformInitPreMem.c
  • MD5_DIGEST_SIZE : BaseCryptLib.h
  • Md5Duplicate() : BaseCryptLib.h
  • Md5Final() : BaseCryptLib.h
  • Md5GetContextSize() : BaseCryptLib.h
  • Md5Init() : BaseCryptLib.h
  • Md5Update() : BaseCryptLib.h
  • ME_FWU_INFO_MSG : Fwu_Common.h
  • ME_SETUP_REVISION : SetupVariable.h
  • MemoryDiscoveredPpiNotifyCallback() : PlatformInitPreMem.c
  • MePolicyInitDxe() : MePolicyInitDxe.c , MePolicyInitDxe.h
  • MSR_PLATFORM_INFORMATION : StmDefinition.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- n -

  • NeedResetBoardDefaultVariableHob() : PlatformNvRamHookLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- o -

  • Out8042AuxCommand() : AcpiPlatform.c
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- p -

  • PCH_GPIO_PAD : PlatformInfo.h
  • PCH_SETUP_REVISION : SetupVariable.h
  • PchPolicyInitDxe() : PchPolicyInitDxe.h , PchPolicyInitDxe.c
  • PchReset() : PlatformInitPreMem.c
  • PciEnumCompleteCallback() : SaPlatformInitDxe.c
  • PdtUpdate() : PdtUpdateLib.h
  • PeiPolicyInit() : PeiPolicyInitLib.h
  • PeiPolicyInitPreMem() : PeiPolicyInitLib.h
  • PeiReadWriteVariableInit() : PeiReadWriteVariableLib.h
  • PeiWdtApp() : PeiWdtAppLib.h
  • Pkcs7Verify() : BaseCryptLib.h
  • PLATFORM_EMMC_TUNING_DATA : PlatformEmmcHs400Info.h
  • PlatformDxeReadyToBootCallback() : PlatformInitDxe.c
  • PlatformInitDxe() : PlatformInitDxe.c
  • PlatformInitEndOfPei() : PlatformInit.c
  • PlatformInitEntryPoint() : PlatformInit.c
  • PlatformInitPreMem() : PlatformInitPreMem.c
  • PlatformInitPreMemEntryPoint() : PlatformInitPreMem.c
  • PlatformInitPreMemUpdateBootMode() : PlatformInitPreMem.c
  • PlatformPchInit() : PlatformInitPreMem.c
  • PlatformPchResetCallback() : PlatformInitDxe.c
  • PlatformSecureLibTestConstructor() : PlatformSecureLib.h
  • PlatformUpdateTables() : AcpiPlatform.c
  • PlatformVariableInit() : PlatformInitPreMem.c
  • PolicyInitDxeEntryPoint() : PolicyInitDxe.h , PolicyInitDxe.c
  • PowerStateIsAc() : EcMiscLib.h
  • PrioritizeBootMode() : PlatformInitPreMem.c
  • PS2MouseEnable() : AcpiPlatform.c
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- q -

  • QuerySmiEvent() : EcMiscLib.h
  • QuerySysStatus() : EcMiscLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- r -

  • RandomBytes() : BaseCryptLib.h
  • RandomSeed() : BaseCryptLib.h
  • ReadEcRam() : EcMiscLib.h
  • ReceiveEcData() : EcLib.h
  • ReceiveEcStatus() : EcLib.h
  • RegisterDisplayDimmPopulationErrMsg() : SaPlatformInitDxe.c
  • RegisterEndOfDxeCallbacks() : PlatformInitDxe.c
  • RegisterReadyToBootCallback() : PlatformInitDxe.c
  • RESET_GENERATOR_PORT : PlatformInitPreMem.c
  • ResetSarSensorSklSds() : PlatformInit.c
  • RESOURCE : SmmTxtResource.h
  • RSA_KEY_TAG : BaseCryptLib.h
  • RsaCheckKey() : BaseCryptLib.h
  • RsaFree() : BaseCryptLib.h
  • RsaGenerateKey() : BaseCryptLib.h
  • RsaGetKey() : BaseCryptLib.h
  • RsaKeyD : BaseCryptLib.h
  • RsaKeyDp : BaseCryptLib.h
  • RsaKeyDq : BaseCryptLib.h
  • RsaKeyE : BaseCryptLib.h
  • RsaKeyN : BaseCryptLib.h
  • RsaKeyP : BaseCryptLib.h
  • RsaKeyQ : BaseCryptLib.h
  • RsaKeyQInv : BaseCryptLib.h
  • RsaNew() : BaseCryptLib.h
  • RsaPkcs1Sign() : BaseCryptLib.h
  • RsaPkcs1Verify() : BaseCryptLib.h
  • RsaSetKey() : BaseCryptLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- s -

  • SA_SETUP_REVISION : SetupVariable.h
  • SaPlatformInitDxe() : PlatformInitDxe.h , SaPlatformInitDxe.c
  • SaPolicyInitDxe() : SaPolicyInitDxe.c , SaPolicyInitDxe.h
  • SaveCpuRatio() : PlatformNvRamHookLib.h
  • SaveSaDisplayRegisters() : PlatformNvRamHookLib.h
  • SaveTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • SaveTxtAliasCheck() : PlatformNvRamHookLib.h
  • SecondaryNvRamInit() : PlatformNvRamHookLib.h
  • SendEcCommand() : EcLib.h
  • SendEcData() : EcLib.h
  • SetAcpiSetupVariables() : AcpiPlatform.c
  • SetBclkRampFlag() : PlatformNvRamHookLib.h
  • SetCacheMtrr() : PlatformInitPreMem.c
  • SetCacheMtrrAfterEndOfPei() : PlatformInit.c
  • SetEcCriticalShutdownTemperature() : EcMiscLib.h
  • SetPmicVoltage() : EcMiscLib.h
  • SetSlpS0Voltage() : EcMiscLib.h
  • SetTheStateToGoAfterG3() : PlatformInitPreMem.c
  • SETUP_DATA_REVISION : SetupVariable.h
  • SetVariableToHob() : MultiPlatSupportLib.h
  • SHA1_DIGEST_SIZE : BaseCryptLib.h
  • Sha1Duplicate() : BaseCryptLib.h
  • Sha1Final() : BaseCryptLib.h
  • Sha1GetContextSize() : BaseCryptLib.h
  • Sha1Init() : BaseCryptLib.h
  • Sha1Update() : BaseCryptLib.h
  • SHA256_DIGEST_SIZE : BaseCryptLib.h , Setup.h
  • Sha256Duplicate() : BaseCryptLib.h
  • Sha256Final() : BaseCryptLib.h
  • Sha256GetContextSize() : BaseCryptLib.h
  • Sha256Init() : BaseCryptLib.h
  • Sha256Update() : BaseCryptLib.h
  • SI_SETUP_REVISION : SetupVariable.h
  • SiliconPolicyInitDxe() : SiliconPolicyInitDxe.c , SiliconPolicyInitDxe.h
  • SiPreMemPolicyPpiNotifyCallback() : PlatformInitPreMem.c
  • SMM_ENTRY_INIT_STRUCT : SmmStmConfTable.h
  • SMM_PCI_IO_WIDTH : PlatformSmmIoLib.h
  • SMM_SUCCESS : StmDefinition.h
  • SmmIoRead16() : PlatformSmmIoLib.h
  • SmmIoRead32() : PlatformSmmIoLib.h
  • SmmIoRead8() : PlatformSmmIoLib.h
  • SmmIoWrite16() : PlatformSmmIoLib.h
  • SmmIoWrite32() : PlatformSmmIoLib.h
  • SmmIoWrite8() : PlatformSmmIoLib.h
  • SmmMemAnd32() : PlatformSmmIoLib.h
  • SmmMemRead16() : PlatformSmmIoLib.h
  • SmmMemRead32() : PlatformSmmIoLib.h
  • SmmMemRead8() : PlatformSmmIoLib.h
  • SmmMemWrite16() : PlatformSmmIoLib.h
  • SmmMemWrite32() : PlatformSmmIoLib.h
  • SmmMemWrite8() : PlatformSmmIoLib.h
  • SmmPciCfgRead() : PlatformSmmIoLib.h
  • SmmPciCfgWrite() : PlatformSmmIoLib.h
  • SmmStmConfTableInit() : SmmStmConfTableLib.h
  • SortCpuLocalApicInTable() : AcpiPlatform.h , AcpiPlatform.c
  • SpiFlashBlockErase() : SpiFlashCommon.h
  • SpiFlashLock() : SpiFlashCommon.h
  • SpiFlashRead() : SpiFlashCommon.h
  • SpiFlashWrite() : SpiFlashCommon.h
  • STATUS_SUCCESS : me_status.h , Fwu_Common.h
  • STM_MAP_ADDRESS_RANGE : SmmTxtResource.h
  • STM_OPT_OUT : SmmStmConfTable.h
  • SW_SMI_STM_GET_BIOS_AC_STATUS_CMD : StmDefinition.h
  • SystemPowerOff() : EcMiscLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- t -

  • TbtPolicyInitDxe() : TbtPolicyInitDxe.c , TbtPolicyInitDxe.h
  • Tcg2PhysicalPresenceLibGetManagementFlags() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibNeedUserConfirm() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibProcessRequest() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction() : Tcg2PhysicalPresenceLib.h
  • tcgAddBOOLEAN() : TcgCore.h
  • tcgAddByteSequence() : TcgCore.h
  • tcgAddCall() : TcgCore.h
  • tcgAddEndList() : TcgCore.h
  • tcgAddEndName() : TcgCore.h
  • tcgAddEndOfData() : TcgCore.h
  • tcgAddEndOfSession() : TcgCore.h
  • tcgAddEndTransaction() : TcgCore.h
  • tcgAddInteger() : TcgCore.h
  • tcgAddRawByte() : TcgCore.h
  • tcgAddStartList() : TcgCore.h
  • tcgAddStartName() : TcgCore.h
  • tcgAddStartTransaction() : TcgCore.h
  • tcgAddTcgUid() : TcgCore.h
  • tcgAddUINT16() : TcgCore.h
  • tcgAddUINT32() : TcgCore.h
  • tcgAddUINT64() : TcgCore.h
  • tcgAddUINT8() : TcgCore.h
  • tcgCheckComIds() : TcgUtil.h
  • tcgCreateEndSession() : TcgUtil.h
  • tcgCreateSetCPin() : TcgUtil.h
  • tcgCreateStartSession() : TcgUtil.h
  • TcgCreateStruct : TcgCore.h
  • tcgEndComPacket() : TcgCore.h
  • tcgEndMethodCall() : TcgUtil.h
  • tcgEndPacket() : TcgCore.h
  • tcgEndParameters() : TcgUtil.h
  • tcgEndSubPacket() : TcgCore.h
  • tcgGetAtomInfo() : TcgCore.h
  • tcgGetComIds() : TcgUtil.h
  • tcgGetMethodStatus() : TcgUtil.h
  • tcgGetNextBOOLEAN() : TcgCore.h
  • tcgGetNextByteSequence() : TcgCore.h
  • tcgGetNextCall() : TcgCore.h
  • tcgGetNextEndList() : TcgCore.h
  • tcgGetNextEndName() : TcgCore.h
  • tcgGetNextEndOfData() : TcgCore.h
  • tcgGetNextEndOfSession() : TcgCore.h
  • tcgGetNextEndTransaction() : TcgCore.h
  • tcgGetNextStartList() : TcgCore.h
  • tcgGetNextStartName() : TcgCore.h
  • tcgGetNextStartTransaction() : TcgCore.h
  • tcgGetNextTcgUid() : TcgCore.h
  • tcgGetNextToken() : TcgCore.h
  • tcgGetNextTokenType() : TcgCore.h
  • tcgGetNextUINT16() : TcgCore.h
  • tcgGetNextUINT32() : TcgCore.h
  • tcgGetNextUINT64() : TcgCore.h
  • tcgGetNextUINT8() : TcgCore.h
  • tcgGetTokenByteSequence() : TcgCore.h
  • tcgGetTokenUINT64() : TcgCore.h
  • tcgInitTcgCreateStruct() : TcgCore.h
  • tcgInitTcgParseStruct() : TcgCore.h
  • tcgIsLocked() : TcgUtil.h
  • tcgIsProtocolSupported() : TcgUtil.h
  • tcgMethodStatusString() : TcgUtil.h
  • TcgParseStruct : TcgCore.h
  • tcgParseSyncSession() : TcgUtil.h
  • TcgResult : TcgCore.h
  • TcgResult_Failure : TcgCore.h
  • TcgResult_Failure_BufferTooSmall : TcgCore.h
  • TcgResult_Failure_EndBuffer : TcgCore.h
  • TcgResult_Failure_InvalidAction : TcgCore.h
  • TcgResult_Failure_InvalidType : TcgCore.h
  • TcgResult_Failure_NullPointer : TcgCore.h
  • TcgResult_Failure_ZeroSize : TcgCore.h
  • TcgResult_Success : TcgCore.h
  • tcgSetAuthorityEnabled() : TcgUtil.h
  • tcgStartComPacket() : TcgCore.h
  • tcgStartMethodCall() : TcgUtil.h
  • tcgStartPacket() : TcgCore.h
  • tcgStartParameters() : TcgUtil.h
  • tcgStartSubPacket() : TcgCore.h
  • TcgToken : TcgCore.h
  • tcgTokenTypeString() : TcgUtil.h
  • TcgUid : Tcg.h
  • TDES_BLOCK_SIZE : BaseCryptLib.h
  • TdesCbcDecrypt() : BaseCryptLib.h
  • TdesCbcEncrypt() : BaseCryptLib.h
  • TdesEcbDecrypt() : BaseCryptLib.h
  • TdesEcbEncrypt() : BaseCryptLib.h
  • TdesGetContextSize() : BaseCryptLib.h
  • TdesInit() : BaseCryptLib.h
  • TXT_RESET_SYSTEM : TxtOneTouchOp.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- u -

  • UpdateBiosGuardModulePtr() : PlatformInit.c
  • UpdateBootFlagStatus() : PlatformNvRamHookLib.h
  • UpdateDevicePower() : EcMiscLib.h
  • UpdateDimmPopulation() : PlatformInitDxe.h , SaPlatformInitDxe.c
  • UpdateDxeAmtPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeMePolicy() : DxeMePolicyUpdateLib.h
  • UpdateDxeMePolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxePchPolicy() : DxePchPolicyUpdateLib.h
  • UpdateDxeSaPolicy() : DxeSaPolicyUpdateLib.h
  • UpdateDxeSaPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeSiCpuPolicy() : DxeCpuPolicyUpdateLib.h
  • UpdateDxeTbtPolicy() : DxeTbtPolicyUpdateLib.h
  • UpdateEpcVariables() : PlatformInitDxe.c
  • UpdateGmAdrRegionToWriteCombine() : SaPlatformInitDxe.c
  • UpdateItbtDmaUuidVariable() : SaPlatformInitDxe.c
  • UpdatePeiAmtPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiCpuPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiCpuPolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiCpuPolicyDebug() : PeiCpuPolicyDebugLib.h
  • UpdatePeiCpuPolicyDebugPreMem() : PeiCpuPolicyDebugLib.h
  • UpdatePeiMePolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiMePolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiPchPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiPchPolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiPchPolicyDebug() : PeiPchPolicyDebugLib.h
  • UpdatePeiPchPolicyDebugPreMem() : PeiPchPolicyDebugLib.h
  • UpdatePeiSaPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiSaPolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiSaPolicyDebug() : PeiSaPolicyDebugLib.h
  • UpdatePeiSaPolicyDebugPreMem() : PeiSaPolicyDebugLib.h
  • UpdatePeiSiPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiSiPolicyDebug() : PeiSiPolicyDebugLib.h
  • UpdatePeiTbtPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePlatformInfo() : PlatformInitDxe.c
  • UpdatePwm() : EcMiscLib.h
  • UpdateRmrrUsbAddress() : SaPlatformInitDxe.c
  • UpdateSaPolicyGopVbtPointer() : SaPlatformInitDxe.c
  • UpdateSgxPolicyStatusVariable() : PlatformInitDxe.c
  • UpdateSgxSvnVariable() : PlatformInitDxe.c
  • UsbcGetUsbConnStatus() : EcTcssLib.h
  • UsbcIomReadyNotify() : EcTcssLib.h
  • UsbcSxEntry() : EcMiscLib.h , EcTcssLib.h
  • UsbcSxExit() : EcMiscLib.h , EcTcssLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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Here is a list of all documented file members with links to the documentation:

- v -

  • VAR_ADDED : MultiPlatSupport.h
  • VAR_DELETED : MultiPlatSupport.h
  • VAR_HEADER_VALID_ONLY : MultiPlatSupport.h
  • VAR_IN_DELETED_TRANSITION : MultiPlatSupport.h
  • VARIABLE_DATA : MultiPlatSupport.h
  • VARIABLE_STORE_FORMATTED : MultiPlatSupport.h
  • VARIABLE_STORE_STATUS : MultiPlatSupport.h
  • VER_BUILD : Build.h
  • VER_BUILD_STR : Build.h
  • VER_DEBUG_TAG : ver.h
  • VER_HOTFIX : ver.h
  • VER_HOTFIX_STR : ver.h
  • VER_MAJOR : ver.h
  • VER_MAJOR_STR : ver.h
  • VER_MINOR : ver.h
  • VER_MINOR_STR : ver.h
  • VER_SEPARATOR_STR : ver.h
  • VERSION : ver.h
  • VERSION_STR : ver.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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Here is a list of all documented file members with links to the documentation:

- w -

  • WaitInputEmpty() : AcpiPlatform.c
  • WaitOutputFull() : AcpiPlatform.c
  • WakeUpEc() : EcMiscLib.h
  • WdtAppPpiNotifyCallback() : PlatformInitPreMem.c
  • WriteEcRam() : EcMiscLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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- a -

  • AcpiGnvsInit() : DxeAcpiGnvsInitLib.h
  • AesCbcDecrypt() : BaseCryptLib.h
  • AesCbcEncrypt() : BaseCryptLib.h
  • AesEcbDecrypt() : BaseCryptLib.h
  • AesEcbEncrypt() : BaseCryptLib.h
  • AesGetContextSize() : BaseCryptLib.h
  • AesInit() : BaseCryptLib.h
  • AllocateMemoryBelow4G() : AcpiPlatform.c
  • AmtPolicyInitDxe() : AmtPolicyInitDxe.c , AmtPolicyInitDxe.h
  • Arc4Decrypt() : BaseCryptLib.h
  • Arc4Encrypt() : BaseCryptLib.h
  • Arc4GetContextSize() : BaseCryptLib.h
  • Arc4Init() : BaseCryptLib.h
  • Arc4Reset() : BaseCryptLib.h
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- b -

  • BiosGuardHobInit() : PlatformInit.c
  • BootGuardOemRevocationHook() : BootGuardRevocationLib.h
  • BuildDebugConfigDataHob() : PlatformInitPreMem.c
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- c -

  • CheckLidBaseEcProtocolVersion() : EcPlatformInitDxe.c , PlatformInitDxe.h
  • CheckOddParity() : PlatformInitPreMem.c
  • CheckSataRaidMode() : BasePlatformVariableLib.h
  • ClearDiagnosticStatus() : PlatformNvRamHookLib.h
  • ClearTenSecPwrButtonMode() : EcMiscLib.h
  • CpuDxePrintPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuInstallPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuPolicyInitDxe() : CpuPolicyInitDxe.c , CpuPolicyInitDxe.h
  • CreateAttemptUsbFirstHotkeyInfoHob() : PlatformInit.c
  • CreateBootguardEventLogEntries() : PeiBootGuardEventLogLib.h
  • CreateDefaultVariableHob() : MultiPlatSupportLib.h
  • CreateFastBootHob() : PlatformInitPreMem.c
  • CreateSgxInfoForOs() : PlatformInitDxe.c
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- d -

  • DetectBootMode() : PlatformInitPreMem.c
  • DetectEc() : EcLib.h
  • DetectEcRevision() : EcMiscLib.h
  • DetectPmicVendorID() : EcMiscLib.h
  • DevicePathToStr() : DxePlatformBootManagerLib.h
  • DfctFastChargingMode() : EcMiscLib.h
  • DhComputeKey() : BaseCryptLib.h
  • DhFree() : BaseCryptLib.h
  • DhGenerateKey() : BaseCryptLib.h
  • DhGenerateParameter() : BaseCryptLib.h
  • DhNew() : BaseCryptLib.h
  • DhSetParameter() : BaseCryptLib.h
  • DisableBiosLockForPeiWriteVariable() : PlatformInit.c
  • DisableEcSmiMode() : EcMiscLib.h
  • DisablePchDtsReading() : EcMiscLib.h
  • DisplayDimmPopulationErrMsg() : SaPlatformInitDxe.c
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- e -

  • EarlyPlatformPchInit() : PlatformInitPreMem.c
  • EcForceResetAfterAcRemoval() : EcMiscLib.h
  • EcInterface() : EcLib.h
  • EcReset() : EcMiscLib.h
  • EcResetEcInNormalMode() : EcMiscLib.h
  • EnableEcAcpiMode() : EcMiscLib.h
  • EnableLanPower() : EcMiscLib.h
  • EnableSataPort2Power() : EcMiscLib.h
  • EndofDxeCallback() : PlatformInitDxe.c
  • ExitLowPowerMode() : EcMiscLib.h
  • ExpandPartitionsDevPath() : DxePlatformBootManagerLib.h
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- f -

  • FillMseg() : SmmStmConfTableLib.h
  • FillTseg() : SmmStmConfTableLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- g -

  • GetBaseEcFwVersion() : EcMiscLib.h
  • GetBatteryNumber() : EcMiscLib.h
  • GetBoardConfig() : BoardConfigLib.h
  • GetBoardInfo() : EcMiscLib.h
  • GetBootFlagStatus() : PlatformNvRamHookLib.h
  • GetCsmControlStatus() : PlatformInitPreMem.c
  • GetEc2EcProtocolVersion() : EcMiscLib.h
  • GetEcGpeNumber() : AcpiPlatform.c
  • GetFanSpeed() : EcMiscLib.h
  • GetHotkeyScanCode() : EcMiscLib.h
  • GetMsegSize() : SmmStmConfTableLib.h
  • GetPcieDockStatus() : EcMiscLib.h
  • GetPlatformDockStatus() : GopPolicyInitDxe.c
  • GetPlatformLidStatus() : GopPolicyInitDxe.c
  • GetPostCodeBreak() : PlatformNvRamHookLib.h
  • GetRtc3Address() : PlatformNvRamHookLib.h
  • GetSimpleBootFlag() : PlatformInitPreMem.c
  • GetTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • GetTxtAliasCheckAndReset() : PlatformNvRamHookLib.h
  • GetVariableFromHob() : MultiPlatSupportLib.h
  • GetVbtData() : GopPolicyInitDxe.c
  • GetWakeupEventAndSaveToHob() : PlatformInitPreMem.c
  • GopPolicyInitDxe() : GopPolicyInitDxe.c , GopPolicyInitDxe.h
  • GpioExpBulkConfig() : GpioExpanderLib.h
  • GpioExpGetController() : GpioExpanderLib.h
  • GpioExpGetInput() : GpioExpanderLib.h
  • GpioExpSetDirection() : GpioExpanderLib.h
  • GpioExpSetOutput() : GpioExpanderLib.h
  • GpioExpSetPolarity() : GpioExpanderLib.h
  • GuidStringToAcpiBuffer() : AcpiPlatform.c
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- h -

  • HeciPlatformDebugCapabilityMsgCallback() : MePolicyInitDxe.h
  • HmacMd5Duplicate() : BaseCryptLib.h
  • HmacMd5Final() : BaseCryptLib.h
  • HmacMd5GetContextSize() : BaseCryptLib.h
  • HmacMd5Init() : BaseCryptLib.h
  • HmacMd5Update() : BaseCryptLib.h
  • HmacSha1Duplicate() : BaseCryptLib.h
  • HmacSha1Final() : BaseCryptLib.h
  • HmacSha1GetContextSize() : BaseCryptLib.h
  • HmacSha1Init() : BaseCryptLib.h
  • HmacSha1Update() : BaseCryptLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- i -

  • In8042AuxData() : AcpiPlatform.c
  • InitializeGfxInt15() : GfxInt15Interface.c
  • InitializeRecovery() : PeiPlatformRecoveryLib.h
  • InstallAcpiPlatform() : AcpiPlatform.c , AcpiPlatform.h
  • InstallXhciAcpiTable() : AcpiPlatform.c
  • IOMReadyNotifyToEC() : PlatformInit.c
  • IsBootWithNoChange() : PlatformInitPreMem.c
  • IsChecksumBad() : PlatformNvRamHookLib.h
  • IsFastBootEnabled() : PlatformInitPreMem.c
  • IsHardwareChange() : AcpiPlatform.c
  • IsItPartitionsDevicePath() : DxePlatformBootManagerLib.h
  • IsOverclockingEnabled() : PlatformInitPreMem.c
  • IsPowerButtonOverride() : PlatformInitPreMem.c
  • IsPreviousBootSuccessful() : PlatformInitPreMem.c
  • IsPs2MouseConnected() : AcpiPlatform.h , AcpiPlatform.c
  • IsTimeOutOccurred() : PlatformInitPreMem.c
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- l -

  • LoadRealModeFile() : GfxInt15Interface.c
  • LocateSupportProtocol() : AcpiPlatform.c , AcpiPlatform.h
  • LpcEcResetEcInNormalMode() : EcLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- m -

  • Md5Duplicate() : BaseCryptLib.h
  • Md5Final() : BaseCryptLib.h
  • Md5GetContextSize() : BaseCryptLib.h
  • Md5Init() : BaseCryptLib.h
  • Md5Update() : BaseCryptLib.h
  • MemoryDiscoveredPpiNotifyCallback() : PlatformInitPreMem.c
  • MePolicyInitDxe() : MePolicyInitDxe.h , MePolicyInitDxe.c
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- n -

  • NeedResetBoardDefaultVariableHob() : PlatformNvRamHookLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- o -

  • Out8042AuxCommand() : AcpiPlatform.c
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- p -

  • PchPolicyInitDxe() : PchPolicyInitDxe.c , PchPolicyInitDxe.h
  • PchReset() : PlatformInitPreMem.c
  • PciEnumCompleteCallback() : SaPlatformInitDxe.c
  • PdtUpdate() : PdtUpdateLib.h
  • PeiPolicyInit() : PeiPolicyInitLib.h
  • PeiPolicyInitPreMem() : PeiPolicyInitLib.h
  • PeiReadWriteVariableInit() : PeiReadWriteVariableLib.h
  • PeiWdtApp() : PeiWdtAppLib.h
  • Pkcs7Verify() : BaseCryptLib.h
  • PlatformDxeReadyToBootCallback() : PlatformInitDxe.c
  • PlatformInitDxe() : PlatformInitDxe.c
  • PlatformInitEndOfPei() : PlatformInit.c
  • PlatformInitEntryPoint() : PlatformInit.c
  • PlatformInitPreMem() : PlatformInitPreMem.c
  • PlatformInitPreMemEntryPoint() : PlatformInitPreMem.c
  • PlatformInitPreMemUpdateBootMode() : PlatformInitPreMem.c
  • PlatformPchInit() : PlatformInitPreMem.c
  • PlatformPchResetCallback() : PlatformInitDxe.c
  • PlatformSecureLibTestConstructor() : PlatformSecureLib.h
  • PlatformUpdateTables() : AcpiPlatform.c
  • PlatformVariableInit() : PlatformInitPreMem.c
  • PolicyInitDxeEntryPoint() : PolicyInitDxe.h , PolicyInitDxe.c
  • PowerStateIsAc() : EcMiscLib.h
  • PrioritizeBootMode() : PlatformInitPreMem.c
  • PS2MouseEnable() : AcpiPlatform.c
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- q -

  • QuerySmiEvent() : EcMiscLib.h
  • QuerySysStatus() : EcMiscLib.h
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- r -

  • RandomBytes() : BaseCryptLib.h
  • RandomSeed() : BaseCryptLib.h
  • ReadEcRam() : EcMiscLib.h
  • ReceiveEcData() : EcLib.h
  • ReceiveEcStatus() : EcLib.h
  • RegisterDisplayDimmPopulationErrMsg() : SaPlatformInitDxe.c
  • RegisterEndOfDxeCallbacks() : PlatformInitDxe.c
  • RegisterReadyToBootCallback() : PlatformInitDxe.c
  • ResetSarSensorSklSds() : PlatformInit.c
  • RsaCheckKey() : BaseCryptLib.h
  • RsaFree() : BaseCryptLib.h
  • RsaGenerateKey() : BaseCryptLib.h
  • RsaGetKey() : BaseCryptLib.h
  • RsaNew() : BaseCryptLib.h
  • RsaPkcs1Sign() : BaseCryptLib.h
  • RsaPkcs1Verify() : BaseCryptLib.h
  • RsaSetKey() : BaseCryptLib.h
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- s -

  • SaPlatformInitDxe() : PlatformInitDxe.h , SaPlatformInitDxe.c
  • SaPolicyInitDxe() : SaPolicyInitDxe.h , SaPolicyInitDxe.c
  • SaveCpuRatio() : PlatformNvRamHookLib.h
  • SaveSaDisplayRegisters() : PlatformNvRamHookLib.h
  • SaveTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • SaveTxtAliasCheck() : PlatformNvRamHookLib.h
  • SecondaryNvRamInit() : PlatformNvRamHookLib.h
  • SendEcCommand() : EcLib.h
  • SendEcData() : EcLib.h
  • SetAcpiSetupVariables() : AcpiPlatform.c
  • SetBclkRampFlag() : PlatformNvRamHookLib.h
  • SetCacheMtrr() : PlatformInitPreMem.c
  • SetCacheMtrrAfterEndOfPei() : PlatformInit.c
  • SetEcCriticalShutdownTemperature() : EcMiscLib.h
  • SetPmicVoltage() : EcMiscLib.h
  • SetSlpS0Voltage() : EcMiscLib.h
  • SetTheStateToGoAfterG3() : PlatformInitPreMem.c
  • SetVariableToHob() : MultiPlatSupportLib.h
  • Sha1Duplicate() : BaseCryptLib.h
  • Sha1Final() : BaseCryptLib.h
  • Sha1GetContextSize() : BaseCryptLib.h
  • Sha1Init() : BaseCryptLib.h
  • Sha1Update() : BaseCryptLib.h
  • Sha256Duplicate() : BaseCryptLib.h
  • Sha256Final() : BaseCryptLib.h
  • Sha256GetContextSize() : BaseCryptLib.h
  • Sha256Init() : BaseCryptLib.h
  • Sha256Update() : BaseCryptLib.h
  • SiliconPolicyInitDxe() : SiliconPolicyInitDxe.h , SiliconPolicyInitDxe.c
  • SiPreMemPolicyPpiNotifyCallback() : PlatformInitPreMem.c
  • SmmIoRead16() : PlatformSmmIoLib.h
  • SmmIoRead32() : PlatformSmmIoLib.h
  • SmmIoRead8() : PlatformSmmIoLib.h
  • SmmIoWrite16() : PlatformSmmIoLib.h
  • SmmIoWrite32() : PlatformSmmIoLib.h
  • SmmIoWrite8() : PlatformSmmIoLib.h
  • SmmMemAnd32() : PlatformSmmIoLib.h
  • SmmMemRead16() : PlatformSmmIoLib.h
  • SmmMemRead32() : PlatformSmmIoLib.h
  • SmmMemRead8() : PlatformSmmIoLib.h
  • SmmMemWrite16() : PlatformSmmIoLib.h
  • SmmMemWrite32() : PlatformSmmIoLib.h
  • SmmMemWrite8() : PlatformSmmIoLib.h
  • SmmPciCfgRead() : PlatformSmmIoLib.h
  • SmmPciCfgWrite() : PlatformSmmIoLib.h
  • SmmStmConfTableInit() : SmmStmConfTableLib.h
  • SortCpuLocalApicInTable() : AcpiPlatform.c , AcpiPlatform.h
  • SpiFlashBlockErase() : SpiFlashCommon.h
  • SpiFlashLock() : SpiFlashCommon.h
  • SpiFlashRead() : SpiFlashCommon.h
  • SpiFlashWrite() : SpiFlashCommon.h
  • SystemPowerOff() : EcMiscLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


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- t -

  • TbtPolicyInitDxe() : TbtPolicyInitDxe.c , TbtPolicyInitDxe.h
  • Tcg2PhysicalPresenceLibGetManagementFlags() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibNeedUserConfirm() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibProcessRequest() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction() : Tcg2PhysicalPresenceLib.h
  • tcgAddBOOLEAN() : TcgCore.h
  • tcgAddByteSequence() : TcgCore.h
  • tcgAddCall() : TcgCore.h
  • tcgAddEndList() : TcgCore.h
  • tcgAddEndName() : TcgCore.h
  • tcgAddEndOfData() : TcgCore.h
  • tcgAddEndOfSession() : TcgCore.h
  • tcgAddEndTransaction() : TcgCore.h
  • tcgAddInteger() : TcgCore.h
  • tcgAddRawByte() : TcgCore.h
  • tcgAddStartList() : TcgCore.h
  • tcgAddStartName() : TcgCore.h
  • tcgAddStartTransaction() : TcgCore.h
  • tcgAddTcgUid() : TcgCore.h
  • tcgAddUINT16() : TcgCore.h
  • tcgAddUINT32() : TcgCore.h
  • tcgAddUINT64() : TcgCore.h
  • tcgAddUINT8() : TcgCore.h
  • tcgCheckComIds() : TcgUtil.h
  • tcgCreateEndSession() : TcgUtil.h
  • tcgCreateSetCPin() : TcgUtil.h
  • tcgCreateStartSession() : TcgUtil.h
  • tcgEndComPacket() : TcgCore.h
  • tcgEndMethodCall() : TcgUtil.h
  • tcgEndPacket() : TcgCore.h
  • tcgEndParameters() : TcgUtil.h
  • tcgEndSubPacket() : TcgCore.h
  • tcgGetAtomInfo() : TcgCore.h
  • tcgGetComIds() : TcgUtil.h
  • tcgGetMethodStatus() : TcgUtil.h
  • tcgGetNextBOOLEAN() : TcgCore.h
  • tcgGetNextByteSequence() : TcgCore.h
  • tcgGetNextCall() : TcgCore.h
  • tcgGetNextEndList() : TcgCore.h
  • tcgGetNextEndName() : TcgCore.h
  • tcgGetNextEndOfData() : TcgCore.h
  • tcgGetNextEndOfSession() : TcgCore.h
  • tcgGetNextEndTransaction() : TcgCore.h
  • tcgGetNextStartList() : TcgCore.h
  • tcgGetNextStartName() : TcgCore.h
  • tcgGetNextStartTransaction() : TcgCore.h
  • tcgGetNextTcgUid() : TcgCore.h
  • tcgGetNextToken() : TcgCore.h
  • tcgGetNextTokenType() : TcgCore.h
  • tcgGetNextUINT16() : TcgCore.h
  • tcgGetNextUINT32() : TcgCore.h
  • tcgGetNextUINT64() : TcgCore.h
  • tcgGetNextUINT8() : TcgCore.h
  • tcgGetTokenByteSequence() : TcgCore.h
  • tcgGetTokenUINT64() : TcgCore.h
  • tcgInitTcgCreateStruct() : TcgCore.h
  • tcgInitTcgParseStruct() : TcgCore.h
  • tcgIsLocked() : TcgUtil.h
  • tcgIsProtocolSupported() : TcgUtil.h
  • tcgMethodStatusString() : TcgUtil.h
  • tcgParseSyncSession() : TcgUtil.h
  • tcgSetAuthorityEnabled() : TcgUtil.h
  • tcgStartComPacket() : TcgCore.h
  • tcgStartMethodCall() : TcgUtil.h
  • tcgStartPacket() : TcgCore.h
  • tcgStartParameters() : TcgUtil.h
  • tcgStartSubPacket() : TcgCore.h
  • tcgTokenTypeString() : TcgUtil.h
  • TdesCbcDecrypt() : BaseCryptLib.h
  • TdesCbcEncrypt() : BaseCryptLib.h
  • TdesEcbDecrypt() : BaseCryptLib.h
  • TdesEcbEncrypt() : BaseCryptLib.h
  • TdesGetContextSize() : BaseCryptLib.h
  • TdesInit() : BaseCryptLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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  • u
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- u -

  • UpdateBiosGuardModulePtr() : PlatformInit.c
  • UpdateBootFlagStatus() : PlatformNvRamHookLib.h
  • UpdateDevicePower() : EcMiscLib.h
  • UpdateDimmPopulation() : PlatformInitDxe.h , SaPlatformInitDxe.c
  • UpdateDxeAmtPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeMePolicy() : DxeMePolicyUpdateLib.h
  • UpdateDxeMePolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxePchPolicy() : DxePchPolicyUpdateLib.h
  • UpdateDxeSaPolicy() : DxeSaPolicyUpdateLib.h
  • UpdateDxeSaPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeSiCpuPolicy() : DxeCpuPolicyUpdateLib.h
  • UpdateDxeTbtPolicy() : DxeTbtPolicyUpdateLib.h
  • UpdateEpcVariables() : PlatformInitDxe.c
  • UpdateGmAdrRegionToWriteCombine() : SaPlatformInitDxe.c
  • UpdateItbtDmaUuidVariable() : SaPlatformInitDxe.c
  • UpdatePeiAmtPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiCpuPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiCpuPolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiCpuPolicyDebug() : PeiCpuPolicyDebugLib.h
  • UpdatePeiCpuPolicyDebugPreMem() : PeiCpuPolicyDebugLib.h
  • UpdatePeiMePolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiMePolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiPchPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiPchPolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiPchPolicyDebug() : PeiPchPolicyDebugLib.h
  • UpdatePeiPchPolicyDebugPreMem() : PeiPchPolicyDebugLib.h
  • UpdatePeiSaPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiSaPolicyBoardConfigPreMem() : PeiPolicyBoardConfigLib.h
  • UpdatePeiSaPolicyDebug() : PeiSaPolicyDebugLib.h
  • UpdatePeiSaPolicyDebugPreMem() : PeiSaPolicyDebugLib.h
  • UpdatePeiSiPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePeiSiPolicyDebug() : PeiSiPolicyDebugLib.h
  • UpdatePeiTbtPolicyBoardConfig() : PeiPolicyBoardConfigLib.h
  • UpdatePlatformInfo() : PlatformInitDxe.c
  • UpdatePwm() : EcMiscLib.h
  • UpdateRmrrUsbAddress() : SaPlatformInitDxe.c
  • UpdateSaPolicyGopVbtPointer() : SaPlatformInitDxe.c
  • UpdateSgxPolicyStatusVariable() : PlatformInitDxe.c
  • UpdateSgxSvnVariable() : PlatformInitDxe.c
  • UsbcGetUsbConnStatus() : EcTcssLib.h
  • UsbcIomReadyNotify() : EcTcssLib.h
  • UsbcSxEntry() : EcMiscLib.h , EcTcssLib.h
  • UsbcSxExit() : EcMiscLib.h , EcTcssLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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  • t
  • u
  • w

- w -

  • WaitInputEmpty() : AcpiPlatform.c
  • WaitOutputFull() : AcpiPlatform.c
  • WakeUpEc() : EcMiscLib.h
  • WdtAppPpiNotifyCallback() : PlatformInitPreMem.c
  • WriteEcRam() : EcMiscLib.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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  • Enumerator
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  • gMmioDeviceList : I2cMmioConfigLib.h
  • mBootModePriority : PlatformInitPreMem.c
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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  • Enumerations
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  • e
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  • s
  • t
  • v

- e -

  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION : I2cBusConfigurationManagement.h
  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL : I2cBusConfigurationManagement.h
  • EFI_I2C_MASTER_BUS_FREQUENCY_SET : I2cMaster.h
  • EFI_I2C_MASTER_PROTOCOL : I2cMaster.h
  • EFI_I2C_MASTER_RESET : I2cMaster.h
  • EFI_I2C_MASTER_START_REQUEST : I2cMaster.h
  • EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE : SdHostIo.h
  • EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE : SdHostIo.h
  • EFI_USBFN_IO_ABORT_TRANSFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS : EfiUsbFnIo.h
  • EFI_USBFN_IO_DETECT_PORT : EfiUsbFnIo.h
  • EFI_USBFN_IO_EVENTHANDLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_FREE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_DEVICE_INFO : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_MAXTRANSFER_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_START_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_STOP_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_TRANSFER : EfiUsbFnIo.h
  • EPC_BIOS_CONFIG : SoftwareGuardSetupData.h

- f -

  • FWU_CONFIRM_LIVE_PING_MSG : Fwu_Common.h
  • FWU_DATA_MSG : Fwu_Common.h
  • FWU_END_MESSAGE : Fwu_Common.h
  • FWU_FLASH_IMAGE_START_MSG_REPLY : Fwu_Common.h
  • FWU_GET_FEATURE_STATE_MSG_REPLY : Fwu_Common.h
  • FWU_GET_FWU_INFO_STATUS_MSG : Fwu_Common.h
  • FWU_GET_INFO_MSG : Fwu_Common.h
  • FWU_GET_IPU_PT_ATTRB_MSG : Fwu_Common.h
  • FWU_GET_OEMID_MSG_REPLY : Fwu_Common.h
  • FWU_GET_PLATFORM_TYPE_MSG_REPLY : Fwu_Common.h
  • FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE : Fwu_Common.h
  • FWU_GET_RESTORE_POINT_IMAGE_MESSAGE : Fwu_Common.h
  • FWU_GET_UPDATE_DATA_EXTENSION_MSG : Fwu_Common.h
  • FWU_GET_VERSION_MSG_REPLY : Fwu_Common.h
  • FWU_IMAGE_COMPATABILITY_CHECK_MSG : Fwu_Common.h
  • FWU_INVALID_MSG_REPLY : Fwu_Common.h
  • FWU_START_MSG : Fwu_Common.h
  • FWU_VERIFY_OEMID_MSG : Fwu_Common.h
  • FWU_VERIFY_PWD_MSG : Fwu_Common.h

- m -

  • ME_FWU_INFO_MSG : Fwu_Common.h

- p -

  • PCH_GPIO_PAD : PlatformInfo.h
  • PLATFORM_EMMC_TUNING_DATA : PlatformEmmcHs400Info.h

- r -

  • RESOURCE : SmmTxtResource.h

- s -

  • SMM_ENTRY_INIT_STRUCT : SmmStmConfTable.h
  • STM_MAP_ADDRESS_RANGE : SmmTxtResource.h

- t -

  • TcgCreateStruct : TcgCore.h
  • TcgParseStruct : TcgCore.h
  • TcgToken : TcgCore.h
  • TcgUid : Tcg.h
  • TXT_RESET_SYSTEM : TxtOneTouchOp.h

- v -

  • VERSION : ver.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _FWUPD_POWER_SOURCE : FWUpdateLib.h
  • RSA_KEY_TAG : BaseCryptLib.h
  • SMM_PCI_IO_WIDTH : PlatformSmmIoLib.h
  • TcgResult : TcgCore.h
  • VARIABLE_STORE_STATUS : MultiPlatSupport.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • FWUPD_POWER_SOURCE_AC : FWUpdateLib.h
  • FWUPD_POWER_SOURCE_DC : FWUpdateLib.h
  • FWUPD_POWER_SOURCE_UNKOWN : FWUpdateLib.h
  • RsaKeyD : BaseCryptLib.h
  • RsaKeyDp : BaseCryptLib.h
  • RsaKeyDq : BaseCryptLib.h
  • RsaKeyE : BaseCryptLib.h
  • RsaKeyN : BaseCryptLib.h
  • RsaKeyP : BaseCryptLib.h
  • RsaKeyQ : BaseCryptLib.h
  • RsaKeyQInv : BaseCryptLib.h
  • TcgResult_Failure : TcgCore.h
  • TcgResult_Failure_BufferTooSmall : TcgCore.h
  • TcgResult_Failure_EndBuffer : TcgCore.h
  • TcgResult_Failure_InvalidAction : TcgCore.h
  • TcgResult_Failure_InvalidType : TcgCore.h
  • TcgResult_Failure_NullPointer : TcgCore.h
  • TcgResult_Failure_ZeroSize : TcgCore.h
  • TcgResult_Success : TcgCore.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: File Members

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- a -

  • AES_BLOCK_SIZE : BaseCryptLib.h
  • ALIGNMENT : MultiPlatSupport.h

- b -

  • BOARD_INIT_PREMEM_ENTRY : PlatformPostCode.h

- c -

  • CHECK_PATTERN : SdCard.h
  • CPU_SETUP_REVISION : SetupVariable.h
  • CURRENT_YEAR_STRING : ver.h

- d -

  • DEFAULT_BIOSVENDOR_CHARS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM : SmbiosPlatformInfoDefault.h

- e -

  • EC_GETWAKE_STATUS : PlatformInitPreMem.c
  • EC_REAL_BAT1_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT1_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT1_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT1_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT2_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT2_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT_CHARGING_MASK : BaseEcFlashLib.h
  • EC_REAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_STATUS : BaseEcFlashLib.h
  • EFI_USB_DEVICE_MODE_PROTOCOL_GUID : UsbDeviceModeProtocol.h
  • END_OF_RESOURCES : SmmTxtResource.h
  • EPC_FRACTION_NUMERATOR : PlatformInitDxe.c

- f -

  • FORWARD_DECLARATION : typedef.h

- h -

  • HEADER_ALIGNMENT : MultiPlatSupport.h

- i -

  • ICH_ACPI_TIMER_MAX_VALUE : PlatformSmmIoLib.h

- m -

  • MD5_DIGEST_SIZE : BaseCryptLib.h
  • ME_SETUP_REVISION : SetupVariable.h
  • MSR_PLATFORM_INFORMATION : StmDefinition.h

- p -

  • PCH_SETUP_REVISION : SetupVariable.h

- r -

  • RESET_GENERATOR_PORT : PlatformInitPreMem.c

- s -

  • SA_SETUP_REVISION : SetupVariable.h
  • SETUP_DATA_REVISION : SetupVariable.h
  • SHA1_DIGEST_SIZE : BaseCryptLib.h
  • SHA256_DIGEST_SIZE : BaseCryptLib.h , Setup.h
  • SI_SETUP_REVISION : SetupVariable.h
  • SMM_SUCCESS : StmDefinition.h
  • STATUS_SUCCESS : Fwu_Common.h , me_status.h
  • STM_OPT_OUT : SmmStmConfTable.h
  • SW_SMI_STM_GET_BIOS_AC_STATUS_CMD : StmDefinition.h

- t -

  • TDES_BLOCK_SIZE : BaseCryptLib.h

- v -

  • VAR_ADDED : MultiPlatSupport.h
  • VAR_DELETED : MultiPlatSupport.h
  • VAR_HEADER_VALID_ONLY : MultiPlatSupport.h
  • VAR_IN_DELETED_TRANSITION : MultiPlatSupport.h
  • VARIABLE_DATA : MultiPlatSupport.h
  • VARIABLE_STORE_FORMATTED : MultiPlatSupport.h
  • VER_BUILD : Build.h
  • VER_BUILD_STR : Build.h
  • VER_DEBUG_TAG : ver.h
  • VER_HOTFIX : ver.h
  • VER_HOTFIX_STR : ver.h
  • VER_MAJOR : ver.h
  • VER_MAJOR_STR : ver.h
  • VER_MINOR : ver.h
  • VER_MINOR_STR : ver.h
  • VER_SEPARATOR_STR : ver.h
  • VERSION_STR : ver.h
Generated on Sun Aug 13 2017 12:04:38 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Default_BusNumberTranslator.h Source File

  • MultiPlatform
_Default_BusNumberTranslator.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define BUS_NUMBER_TRANSLATOR_DATA { \
20 /* Bus#(Build), Bus#(RUN), BridgeDevFun#, BridgeDevFun#, ..., -1 */ \
21 /* --------------------------------------------------------------------------- */ \
22 0x00, 0, 0x00, (UINT8)-1, /* Host Bridge*/ \
23 0x01, 0, 0x00, 0x08, (UINT8)-1, /* P.E.G. Root Port D1F0 -> Host Bridge*/ \
24 0x02, 0, 0x00, 0x09, (UINT8)-1, /* P.E.G. Root Port D1F1 -> Host Bridge*/ \
25 0x03, 0, 0x00, 0x0A, (UINT8)-1, /* P.E.G. Root Port D1F2 -> Host Bridge*/ \
26 0x04, 0, 0x00, 0xD8, (UINT8)-1, /* PCIE Root Port #17 -> Host Bridge*/ \
27 0x05, 0, 0x00, 0xD9, (UINT8)-1, /* PCIE Root Port #18 -> Host Bridge*/ \
28 0x06, 0, 0x00, 0xDA, (UINT8)-1, /* PCIE Root Port #19 -> Host Bridge*/ \
29 0x07, 0, 0x00, 0xDB, (UINT8)-1, /* PCIE Root Port #20 -> Host Bridge*/ \
30 0x08, 0, 0x00, 0xE0, (UINT8)-1, /* PCIE Root Port #1 -> Host Bridge*/ \
31 0x09, 0, 0x00, 0xE1, (UINT8)-1, /* PCIE Root Port #2 -> Host Bridge*/ \
32 0x0a, 0, 0x00, 0xE2, (UINT8)-1, /* PCIE Root Port #3 -> Host Bridge*/ \
33 0x0b, 0, 0x00, 0xE3, (UINT8)-1, /* PCIE Root Port #4 -> Host Bridge*/ \
34 0x0c, 0, 0x00, 0xE4, (UINT8)-1, /* PCIE Root Port #5 -> Host Bridge*/ \
35 0x0d, 0, 0x00, 0xE5, (UINT8)-1, /* PCIE Root Port #6 -> Host Bridge*/ \
36 0x0e, 0, 0x00, 0xE6, (UINT8)-1, /* PCIE Root Port #7 -> Host Bridge*/ \
37 0x0f, 0, 0x00, 0xE7, (UINT8)-1, /* PCIE Root Port #8 -> Host Bridge*/ \
38 0x10, 0, 0x00, 0xE8, (UINT8)-1, /* PCIE Root Port #9 -> Host Bridge*/ \
39 0x11, 0, 0x00, 0xE9, (UINT8)-1, /* PCIE Root Port #10 -> Host Bridge*/ \
40 0x12, 0, 0x00, 0xEA, (UINT8)-1, /* PCIE Root Port #11 -> Host Bridge*/ \
41 0x13, 0, 0x00, 0xEB, (UINT8)-1, /* PCIE Root Port #12 -> Host Bridge*/ \
42 0x14, 0, 0x00, 0xEC, (UINT8)-1, /* PCIE Root Port #13 -> Host Bridge*/ \
43 0x15, 0, 0x00, 0xED, (UINT8)-1, /* PCIE Root Port #14 -> Host Bridge*/ \
44 0x16, 0, 0x00, 0xEE, (UINT8)-1, /* PCIE Root Port #15 -> Host Bridge*/ \
45 0x17, 0, 0x00, 0xEF, (UINT8)-1, /* PCIE Root Port #16 -> Host Bridge*/ \
46 /* NOTE: Bus#(RUN) is filled by IrqBoardInfo code after enumerating all PCI devices */ \
47 /* and reassigning the bus numbers in IRQ routing table. */ \
48 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Default_MpTableData.h Source File

  • MultiPlatform
_Default_MpTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define MP_TABLE_IRQ_DATA { \
20 /*+-------------------+----------------+----------------+----------------+----------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin |*/ \
22 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
23 /*| PCI Bus Device | APIC IO APIC| APIC IO APIC| APIC IO APIC| APIC IO APIC| Reserved |*/ \
24 /*| Number Number | Input# ID# | Input# ID# | Input# ID# | Input# ID# | must be 0 |*/ \
25 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
26 { 0x00, 0x01, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x01 :Pin0: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin1: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin2: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin3: P.E.G. Root Port D1F0 ( Fn# 0x00)*/ \
27 { 0x01, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
28 { 0x02, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
29 { 0x03, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
30 { 0x00, 0x02, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x02 :Pin0: I.G.D. ( Fn# 0x00)*/ \
31 { 0x00, 0x03, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x03 :Pin0: SA Audio Device ( Fn# 0x00)*/ \
32 { 0x00, 0x04, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x04 :Pin0: SA Thermal Device ( Fn# 0x00)*/ \
33 { 0x00, 0x07, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x07 :Pin0: SA Chap Device ( Fn# 0x00)*/ \
34 { 0x00, 0x13, 20, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x13 :Pin0: Integrated Sensor Hub(ISH) ( Fn# 0x00)*/ \
35 { 0x00, 0x14, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x14 :Pin0: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin1: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin2: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin3: USB 3.0 xHCI Controller ( Fn# 0x00)*/ \
36 { 0x00, 0x16, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x16 :Pin0: ME ( Fn# 0x00) :Pin1: ME ( Fn# 0x00) :Pin2: ME ( Fn# 0x00) :Pin3: ME ( Fn# 0x00)*/ \
37 { 0x00, 0x17, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x17 :Pin0: SATA Controller ( Fn# 0x00)*/ \
38 { 0x00, 0x1B, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1B :Pin0: PCIE Root Port #17 ( Fn# 0x00) :Pin1: PCIE Root Port #17 ( Fn# 0x00) :Pin2: PCIE Root Port #17 ( Fn# 0x00) :Pin3: PCIE Root Port #17 ( Fn# 0x00)*/ \
39 { 0x04, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
40 { 0x05, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
41 { 0x06, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
42 { 0x07, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
43 { 0x00, 0x1C, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1C :Pin0: PCIE Root Port #1 ( Fn# 0x00) :Pin1: PCIE Root Port #1 ( Fn# 0x00) :Pin2: PCIE Root Port #1 ( Fn# 0x00) :Pin3: PCIE Root Port #1 ( Fn# 0x00)*/ \
44 { 0x08, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 33 */ \
45 { 0x09, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 34 */ \
46 { 0x0A, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 08 */ \
47 { 0x0B, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 09 */ \
48 { 0x0C, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 10 */ \
49 { 0x0D, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
50 { 0x0E, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
51 { 0x0F, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
52 { 0x00, 0x1D, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1D :Pin0: PCIE Root Port #9 ( Fn# 0x00) :Pin1: PCIE Root Port #9 ( Fn# 0x00) :Pin2: PCIE Root Port #9 ( Fn# 0x00) :Pin3: PCIE Root Port #9 ( Fn# 0x00)*/ \
53 { 0x10, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
54 { 0x11, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
55 { 0x12, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
56 { 0x13, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
57 { 0x14, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
58 { 0x15, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
59 { 0x16, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
60 { 0x17, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
61 { 0x00, 0x1F, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1F :Pin0: LPC Bridge ( Fn# 0x00) :Pin1: LPC Bridge ( Fn# 0x00) :Pin2: LPC Bridge ( Fn# 0x00) :Pin3: LPC Bridge ( Fn# 0x00)*/ \
62 }
63
64 #define MP_TABLE_APIC_DATA { \
65 /*+----------------------+----------+*/ \
66 /*| IO APIC IO APIC | IO APIC |*/ \
67 /*| Address ID(BUILD)| ID(POST) |*/ \
68 /*+----------------------+----------+*/ \
69 { 0xFEC00000, 0x02, 0x00 }, /* 000 : Int vector base. IO APIC to serve Legacy Interrupts */ \
70 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Default_PirqTableData.h Source File

  • MultiPlatform
_Default_PirqTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define PIRQ_TABLE_IRQ_DATA { \
20 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin | |*/ \
22 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
23 /*| PCI Bus Dev Num | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Physical Reserved |*/ \
24 /*| Number (Shl 3) | Reg Routable to Pin | Reg Routable Pin | Reg Routable Pin | Reg Routable Pin | Slot Num Byte |*/ \
25 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
26 { 0x00, 0x08, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #01h :Pin0: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin1: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin2: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin3: P.E.G. Root Port D1F0 ( Fn# 002X)*/ \
27 { 0x01, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
28 { 0x02, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
29 { 0x03, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
30 { 0x00, 0x10, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #02h :Pin0: I.G.D. ( Fn# 002X)*/ \
31 { 0x00, 0x18, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #03h :Pin0: SA Audio Device ( Fn# 002X)*/ \
32 { 0x00, 0x20, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #04h :Pin0: SA Thermal Device ( Fn# 002X)*/ \
33 { 0x00, 0x38, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #07h :Pin0: SA Chap Device ( Fn# 002X)*/ \
34 { 0x00, 0x98, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #13h :Pin0: Integrated Sensor Hub(ISH) ( Fn# 002X)*/ \
35 { 0x00, 0xA0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #14h :Pin0: USB 3.0 xHCI Controller ( Fn# 002X) :Pin1: USB 3.0 xHCI Controller ( Fn# 002X) :Pin2: USB 3.0 xHCI Controller ( Fn# 002X) :Pin3: USB 3.0 xHCI Controller ( Fn# 002X)*/ \
36 { 0x00, 0xB0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #16h :Pin0: ME ( Fn# 002X) :Pin1: ME ( Fn# 002X) :Pin2: ME ( Fn# 002X) :Pin3: ME ( Fn# 002X)*/ \
37 { 0x00, 0xB8, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #17h :Pin0: SATA Controller ( Fn# 002X)*/ \
38 { 0x00, 0xD8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Bh :Pin0: PCIE Root Port #17 ( Fn# 002X) :Pin1: PCIE Root Port #17 ( Fn# 002X) :Pin2: PCIE Root Port #17 ( Fn# 002X) :Pin3: PCIE Root Port #17 ( Fn# 002X)*/ \
39 { 0x04, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
40 { 0x05, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
41 { 0x06, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
42 { 0x07, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
43 { 0x00, 0xE0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Ch :Pin0: PCIE Root Port #1 ( Fn# 002X) :Pin1: PCIE Root Port #1 ( Fn# 002X) :Pin2: PCIE Root Port #1 ( Fn# 002X) :Pin3: PCIE Root Port #1 ( Fn# 002X)*/ \
44 { 0x08, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 33, 0 }, /* Slot (Device #0x00) */ \
45 { 0x09, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 34, 0 }, /* Slot (Device #0x00) */ \
46 { 0x0A, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 8, 0 }, /* Slot (Device #0x00) */ \
47 { 0x0B, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 9, 0 }, /* Slot (Device #0x00) */ \
48 { 0x0C, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 10, 0 }, /* Slot (Device #0x00) */ \
49 { 0x0D, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
50 { 0x0E, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
51 { 0x0F, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
52 { 0x00, 0xE8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Dh :Pin0: PCIE Root Port #9 ( Fn# 002X) :Pin1: PCIE Root Port #9 ( Fn# 002X) :Pin2: PCIE Root Port #9 ( Fn# 002X) :Pin3: PCIE Root Port #9 ( Fn# 002X)*/ \
53 { 0x10, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
54 { 0x11, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
55 { 0x12, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
56 { 0x13, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
57 { 0x14, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
58 { 0x15, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
59 { 0x16, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
60 { 0x17, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
61 { 0x00, 0xF8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Fh :Pin0: LPC Bridge ( Fn# 002X) :Pin1: LPC Bridge ( Fn# 002X) :Pin2: LPC Bridge ( Fn# 002X) :Pin3: LPC Bridge ( Fn# 002X)*/ \
62 }
63
64 #define PCI_DEDICATED_IRQS 0xDC78
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Rvp_BusNumberTranslator.h Source File

  • MultiPlatform
_Rvp_BusNumberTranslator.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define BUS_NUMBER_TRANSLATOR_DATA { \
20 /* Bus#(Build), Bus#(RUN), BridgeDevFun#, BridgeDevFun#, ..., -1 */ \
21 /* --------------------------------------------------------------------------- */ \
22 0x00, 0, 0x00, (UINT8)-1, /* Host Bridge*/ \
23 0x01, 0, 0x00, 0xE0, (UINT8)-1, /* PCIE Root Port #1 -> Host Bridge*/ \
24 0x02, 0, 0x00, 0xE1, (UINT8)-1, /* PCIE Root Port #2 -> Host Bridge*/ \
25 0x03, 0, 0x00, 0xE2, (UINT8)-1, /* PCIE Root Port #3 -> Host Bridge*/ \
26 0x04, 0, 0x00, 0xE3, (UINT8)-1, /* PCIE Root Port #4 -> Host Bridge*/ \
27 0x05, 0, 0x00, 0xE4, (UINT8)-1, /* PCIE Root Port #5 -> Host Bridge*/ \
28 0x06, 0, 0x00, 0xE5, (UINT8)-1, /* PCIE Root Port #6 -> Host Bridge*/ \
29 0x07, 0, 0x00, 0xE6, (UINT8)-1, /* PCIE Root Port #7 -> Host Bridge*/ \
30 0x08, 0, 0x00, 0xE7, (UINT8)-1, /* PCIE Root Port #8 -> Host Bridge*/ \
31 0x09, 0, 0x00, 0xE8, (UINT8)-1, /* PCIE Root Port #9 -> Host Bridge*/ \
32 0x0a, 0, 0x00, 0xE9, (UINT8)-1, /* PCIE Root Port #10 -> Host Bridge*/ \
33 0x0b, 0, 0x00, 0xEA, (UINT8)-1, /* PCIE Root Port #11 -> Host Bridge*/ \
34 0x0c, 0, 0x00, 0xEB, (UINT8)-1, /* PCIE Root Port #12 -> Host Bridge*/ \
35 /* NOTE: Bus#(RUN) is filled by IrqBoardInfo code after enumerating all PCI devices */ \
36 /* and reassigning the bus numbers in IRQ routing table. */ \
37 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Rvp_MpTableData.h Source File

  • MultiPlatform
_Rvp_MpTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define MP_TABLE_IRQ_DATA { \
20 /*+-------------------+----------------+----------------+----------------+----------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin |*/ \
22 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
23 /*| PCI Bus Device | APIC IO APIC| APIC IO APIC| APIC IO APIC| APIC IO APIC| Reserved |*/ \
24 /*| Number Number | Input# ID# | Input# ID# | Input# ID# | Input# ID# | must be 0 |*/ \
25 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
26 { 0x00, 0x02, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x02 :Pin0: I.G.D. ( Fn# 0x00)*/ \
27 { 0x00, 0x03, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x03 :Pin0: SA Audio Device ( Fn# 0x00)*/ \
28 { 0x00, 0x04, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x04 :Pin0: SA Thermal Device ( Fn# 0x00)*/ \
29 { 0x00, 0x07, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x07 :Pin0: SA Chap Device ( Fn# 0x00)*/ \
30 { 0x00, 0x13, 20, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x13 :Pin0: Integrated Sensor Hub(ISH) ( Fn# 0x00)*/ \
31 { 0x00, 0x14, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x14 :Pin0: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin1: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin2: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin3: USB 3.0 xHCI Controller ( Fn# 0x00)*/ \
32 { 0x00, 0x15, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x15 :Pin0: SERIALIO I2C Controller #0 ( Fn# 0x00) :Pin1: SERIALIO I2C Controller #0 ( Fn# 0x00) :Pin2: SERIALIO I2C Controller #0 ( Fn# 0x00) :Pin3: SERIALIO I2C Controller #0 ( Fn# 0x00)*/ \
33 { 0x00, 0x16, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x16 :Pin0: ME ( Fn# 0x00) :Pin1: ME ( Fn# 0x00) :Pin2: ME ( Fn# 0x00) :Pin3: ME ( Fn# 0x00)*/ \
34 { 0x00, 0x17, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x17 :Pin0: SATA Controller ( Fn# 0x00)*/ \
35 { 0x00, 0x19, 32, 0x02, 33, 0x02, 34, 0x02, 35, 0x02, 0 }, /* Device #0x19 :Pin0: SERIALIO UART Controller #2 ( Fn# 0x00) :Pin1: SERIALIO UART Controller #2 ( Fn# 0x00) :Pin2: SERIALIO UART Controller #2 ( Fn# 0x00) :Pin3: SERIALIO UART Controller #2 ( Fn# 0x00)*/ \
36 { 0x00, 0x1C, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1C :Pin0: PCIE Root Port #1 ( Fn# 0x00) :Pin1: PCIE Root Port #1 ( Fn# 0x00) :Pin2: PCIE Root Port #1 ( Fn# 0x00) :Pin3: PCIE Root Port #1 ( Fn# 0x00)*/ \
37 { 0x01, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 33 */ \
38 { 0x02, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 34 */ \
39 { 0x03, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 08 */ \
40 { 0x04, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 09 */ \
41 { 0x05, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 10 */ \
42 { 0x06, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
43 { 0x07, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
44 { 0x08, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
45 { 0x00, 0x1D, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1D :Pin0: PCIE Root Port #9 ( Fn# 0x00) :Pin1: PCIE Root Port #9 ( Fn# 0x00) :Pin2: PCIE Root Port #9 ( Fn# 0x00) :Pin3: PCIE Root Port #9 ( Fn# 0x00)*/ \
46 { 0x09, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
47 { 0x0A, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
48 { 0x0B, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
49 { 0x0C, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
50 { 0x00, 0x1E, 20, 0x02, 21, 0x02, 22, 0x02, 23, 0x02, 0 }, /* Device #0x1E :Pin0: SERIALIO(UART #0) ( Fn# 0x00) :Pin1: SERIALIO(UART #0) ( Fn# 0x00) :Pin2: SERIALIO(UART #0) ( Fn# 0x00) :Pin3: SERIALIO(UART #0) ( Fn# 0x00)*/ \
51 { 0x00, 0x1F, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1F :Pin0: LPC Bridge ( Fn# 0x00) :Pin1: LPC Bridge ( Fn# 0x00) :Pin2: LPC Bridge ( Fn# 0x00) :Pin3: LPC Bridge ( Fn# 0x00)*/ \
52 }
53
54 #define MP_TABLE_APIC_DATA { \
55 /*+----------------------+----------+*/ \
56 /*| IO APIC IO APIC | IO APIC |*/ \
57 /*| Address ID(BUILD)| ID(POST) |*/ \
58 /*+----------------------+----------+*/ \
59 { 0xFEC00000, 0x02, 0x00 }, /* 000 : Int vector base. IO APIC to serve Legacy Interrupts */ \
60 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Rvp_PirqTableData.h Source File

  • MultiPlatform
_Rvp_PirqTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define PIRQ_TABLE_IRQ_DATA { \
20 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin | |*/ \
22 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
23 /*| PCI Bus Dev Num | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Physical Reserved |*/ \
24 /*| Number (Shl 3) | Reg Routable to Pin | Reg Routable Pin | Reg Routable Pin | Reg Routable Pin | Slot Num Byte |*/ \
25 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
26 { 0x00, 0x10, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #02h :Pin0: I.G.D. ( Fn# 002X)*/ \
27 { 0x00, 0x18, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #03h :Pin0: SA Audio Device ( Fn# 002X)*/ \
28 { 0x00, 0x20, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #04h :Pin0: SA Thermal Device ( Fn# 002X)*/ \
29 { 0x00, 0x38, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #07h :Pin0: SA Chap Device ( Fn# 002X)*/ \
30 { 0x00, 0x98, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #13h :Pin0: Integrated Sensor Hub(ISH) ( Fn# 002X)*/ \
31 { 0x00, 0xA0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #14h :Pin0: USB 3.0 xHCI Controller ( Fn# 002X) :Pin1: USB 3.0 xHCI Controller ( Fn# 002X) :Pin2: USB 3.0 xHCI Controller ( Fn# 002X) :Pin3: USB 3.0 xHCI Controller ( Fn# 002X)*/ \
32 { 0x00, 0xA8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #15h :Pin0: SERIALIO I2C Controller #0 ( Fn# 002X) :Pin1: SERIALIO I2C Controller #0 ( Fn# 002X) :Pin2: SERIALIO I2C Controller #0 ( Fn# 002X) :Pin3: SERIALIO I2C Controller #0 ( Fn# 002X)*/ \
33 { 0x00, 0xB0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #16h :Pin0: ME ( Fn# 002X) :Pin1: ME ( Fn# 002X) :Pin2: ME ( Fn# 002X) :Pin3: ME ( Fn# 002X)*/ \
34 { 0x00, 0xB8, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #17h :Pin0: SATA Controller ( Fn# 002X)*/ \
35 { 0x00, 0xC8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #19h :Pin0: SERIALIO UART Controller #2 ( Fn# 002X) :Pin1: SERIALIO UART Controller #2 ( Fn# 002X) :Pin2: SERIALIO UART Controller #2 ( Fn# 002X) :Pin3: SERIALIO UART Controller #2 ( Fn# 002X)*/ \
36 { 0x00, 0xE0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Ch :Pin0: PCIE Root Port #1 ( Fn# 002X) :Pin1: PCIE Root Port #1 ( Fn# 002X) :Pin2: PCIE Root Port #1 ( Fn# 002X) :Pin3: PCIE Root Port #1 ( Fn# 002X)*/ \
37 { 0x01, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 33, 0 }, /* Slot (Device #0x00) */ \
38 { 0x02, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 34, 0 }, /* Slot (Device #0x00) */ \
39 { 0x03, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 8, 0 }, /* Slot (Device #0x00) */ \
40 { 0x04, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 9, 0 }, /* Slot (Device #0x00) */ \
41 { 0x05, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 10, 0 }, /* Slot (Device #0x00) */ \
42 { 0x06, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
43 { 0x07, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
44 { 0x08, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
45 { 0x00, 0xE8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Dh :Pin0: PCIE Root Port #9 ( Fn# 002X) :Pin1: PCIE Root Port #9 ( Fn# 002X) :Pin2: PCIE Root Port #9 ( Fn# 002X) :Pin3: PCIE Root Port #9 ( Fn# 002X)*/ \
46 { 0x09, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
47 { 0x0A, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
48 { 0x0B, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
49 { 0x0C, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
50 { 0x00, 0xF0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Eh :Pin0: SERIALIO(UART #0) ( Fn# 002X) :Pin1: SERIALIO(UART #0) ( Fn# 002X) :Pin2: SERIALIO(UART #0) ( Fn# 002X) :Pin3: SERIALIO(UART #0) ( Fn# 002X)*/ \
51 { 0x00, 0xF8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Fh :Pin0: LPC Bridge ( Fn# 002X) :Pin1: LPC Bridge ( Fn# 002X) :Pin2: LPC Bridge ( Fn# 002X) :Pin3: LPC Bridge ( Fn# 002X)*/ \
52 }
53
54 #define PCI_DEDICATED_IRQS 0xDC78
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpDt_BusNumberTranslator.h Source File

  • MultiPlatform
_RvpDt_BusNumberTranslator.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define BUS_NUMBER_TRANSLATOR_DATA { \
20 /* Bus#(Build), Bus#(RUN), BridgeDevFun#, BridgeDevFun#, ..., -1 */ \
21 /* --------------------------------------------------------------------------- */ \
22 0x00, 0, 0x00, (UINT8)-1, /* Host Bridge*/ \
23 0x01, 0, 0x00, 0x08, (UINT8)-1, /* P.E.G. Root Port D1F0 -> Host Bridge*/ \
24 0x02, 0, 0x00, 0x09, (UINT8)-1, /* P.E.G. Root Port D1F1 -> Host Bridge*/ \
25 0x03, 0, 0x00, 0x0A, (UINT8)-1, /* P.E.G. Root Port D1F2 -> Host Bridge*/ \
26 0x04, 0, 0x00, 0xD8, (UINT8)-1, /* PCIE Root Port #17 -> Host Bridge*/ \
27 0x05, 0, 0x00, 0xD9, (UINT8)-1, /* PCIE Root Port #18 -> Host Bridge*/ \
28 0x06, 0, 0x00, 0xDA, (UINT8)-1, /* PCIE Root Port #19 -> Host Bridge*/ \
29 0x07, 0, 0x00, 0xDB, (UINT8)-1, /* PCIE Root Port #20 -> Host Bridge*/ \
30 0x08, 0, 0x00, 0xE0, (UINT8)-1, /* PCIE Root Port #1 -> Host Bridge*/ \
31 0x09, 0, 0x00, 0xE1, (UINT8)-1, /* PCIE Root Port #2 -> Host Bridge*/ \
32 0x0a, 0, 0x00, 0xE2, (UINT8)-1, /* PCIE Root Port #3 -> Host Bridge*/ \
33 0x0b, 0, 0x00, 0xE3, (UINT8)-1, /* PCIE Root Port #4 -> Host Bridge*/ \
34 0x0c, 0, 0x00, 0xE4, (UINT8)-1, /* PCIE Root Port #5 -> Host Bridge*/ \
35 0x0d, 0, 0x00, 0xE5, (UINT8)-1, /* PCIE Root Port #6 -> Host Bridge*/ \
36 0x0e, 0, 0x00, 0xE6, (UINT8)-1, /* PCIE Root Port #7 -> Host Bridge*/ \
37 0x0f, 0, 0x00, 0xE7, (UINT8)-1, /* PCIE Root Port #8 -> Host Bridge*/ \
38 0x10, 0, 0x00, 0xE8, (UINT8)-1, /* PCIE Root Port #9 -> Host Bridge*/ \
39 0x11, 0, 0x00, 0xE9, (UINT8)-1, /* PCIE Root Port #10 -> Host Bridge*/ \
40 0x12, 0, 0x00, 0xEA, (UINT8)-1, /* PCIE Root Port #11 -> Host Bridge*/ \
41 0x13, 0, 0x00, 0xEB, (UINT8)-1, /* PCIE Root Port #12 -> Host Bridge*/ \
42 0x14, 0, 0x00, 0xEC, (UINT8)-1, /* PCIE Root Port #13 -> Host Bridge*/ \
43 0x15, 0, 0x00, 0xED, (UINT8)-1, /* PCIE Root Port #14 -> Host Bridge*/ \
44 0x16, 0, 0x00, 0xEE, (UINT8)-1, /* PCIE Root Port #15 -> Host Bridge*/ \
45 0x17, 0, 0x00, 0xEF, (UINT8)-1, /* PCIE Root Port #16 -> Host Bridge*/ \
46 /* NOTE: Bus#(RUN) is filled by IrqBoardInfo code after enumerating all PCI devices */ \
47 /* and reassigning the bus numbers in IRQ routing table. */ \
48 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpDt_MpTableData.h Source File

  • MultiPlatform
_RvpDt_MpTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define MP_TABLE_IRQ_DATA { \
20 /*+-------------------+----------------+----------------+----------------+----------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin |*/ \
22 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
23 /*| PCI Bus Device | APIC IO APIC| APIC IO APIC| APIC IO APIC| APIC IO APIC| Reserved |*/ \
24 /*| Number Number | Input# ID# | Input# ID# | Input# ID# | Input# ID# | must be 0 |*/ \
25 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
26 { 0x00, 0x01, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x01 :Pin0: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin1: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin2: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin3: P.E.G. Root Port D1F0 ( Fn# 0x00)*/ \
27 { 0x01, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
28 { 0x02, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
29 { 0x03, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
30 { 0x00, 0x02, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x02 :Pin0: I.G.D. ( Fn# 0x00)*/ \
31 { 0x00, 0x03, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x03 :Pin0: SA Audio Device ( Fn# 0x00)*/ \
32 { 0x00, 0x04, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x04 :Pin0: SA Thermal Device ( Fn# 0x00)*/ \
33 { 0x00, 0x07, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x07 :Pin0: SA Chap Device ( Fn# 0x00)*/ \
34 { 0x00, 0x13, 20, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x13 :Pin0: Integrated Sensor Hub(ISH) ( Fn# 0x00)*/ \
35 { 0x00, 0x14, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x14 :Pin0: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin1: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin2: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin3: USB 3.0 xHCI Controller ( Fn# 0x00)*/ \
36 { 0x00, 0x16, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x16 :Pin0: ME ( Fn# 0x00) :Pin1: ME ( Fn# 0x00) :Pin2: ME ( Fn# 0x00) :Pin3: ME ( Fn# 0x00)*/ \
37 { 0x00, 0x17, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x17 :Pin0: SATA Controller ( Fn# 0x00)*/ \
38 { 0x00, 0x1B, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1B :Pin0: PCIE Root Port #17 ( Fn# 0x00) :Pin1: PCIE Root Port #17 ( Fn# 0x00) :Pin2: PCIE Root Port #17 ( Fn# 0x00) :Pin3: PCIE Root Port #17 ( Fn# 0x00)*/ \
39 { 0x04, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
40 { 0x05, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
41 { 0x06, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
42 { 0x07, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
43 { 0x00, 0x1C, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1C :Pin0: PCIE Root Port #1 ( Fn# 0x00) :Pin1: PCIE Root Port #1 ( Fn# 0x00) :Pin2: PCIE Root Port #1 ( Fn# 0x00) :Pin3: PCIE Root Port #1 ( Fn# 0x00)*/ \
44 { 0x08, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 33 */ \
45 { 0x09, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 34 */ \
46 { 0x0A, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 08 */ \
47 { 0x0B, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 09 */ \
48 { 0x0C, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 10 */ \
49 { 0x0D, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
50 { 0x0E, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
51 { 0x0F, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
52 { 0x00, 0x1D, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1D :Pin0: PCIE Root Port #9 ( Fn# 0x00) :Pin1: PCIE Root Port #9 ( Fn# 0x00) :Pin2: PCIE Root Port #9 ( Fn# 0x00) :Pin3: PCIE Root Port #9 ( Fn# 0x00)*/ \
53 { 0x10, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
54 { 0x11, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
55 { 0x12, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
56 { 0x13, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
57 { 0x14, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
58 { 0x15, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
59 { 0x16, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
60 { 0x17, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
61 { 0x00, 0x1F, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1F :Pin0: LPC Bridge ( Fn# 0x00) :Pin1: LPC Bridge ( Fn# 0x00) :Pin2: LPC Bridge ( Fn# 0x00) :Pin3: LPC Bridge ( Fn# 0x00)*/ \
62 }
63
64 #define MP_TABLE_APIC_DATA { \
65 /*+----------------------+----------+*/ \
66 /*| IO APIC IO APIC | IO APIC |*/ \
67 /*| Address ID(BUILD)| ID(POST) |*/ \
68 /*+----------------------+----------+*/ \
69 { 0xFEC00000, 0x02, 0x00 }, /* 000 : Int vector base. IO APIC to serve Legacy Interrupts */ \
70 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpDt_PirqTableData.h Source File

  • MultiPlatform
_RvpDt_PirqTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define PIRQ_TABLE_IRQ_DATA { \
20 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin | |*/ \
22 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
23 /*| PCI Bus Dev Num | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Physical Reserved |*/ \
24 /*| Number (Shl 3) | Reg Routable to Pin | Reg Routable Pin | Reg Routable Pin | Reg Routable Pin | Slot Num Byte |*/ \
25 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
26 { 0x00, 0x08, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #01h :Pin0: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin1: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin2: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin3: P.E.G. Root Port D1F0 ( Fn# 002X)*/ \
27 { 0x01, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
28 { 0x02, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
29 { 0x03, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
30 { 0x00, 0x10, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #02h :Pin0: I.G.D. ( Fn# 002X)*/ \
31 { 0x00, 0x18, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #03h :Pin0: SA Audio Device ( Fn# 002X)*/ \
32 { 0x00, 0x20, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #04h :Pin0: SA Thermal Device ( Fn# 002X)*/ \
33 { 0x00, 0x38, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #07h :Pin0: SA Chap Device ( Fn# 002X)*/ \
34 { 0x00, 0x98, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #13h :Pin0: Integrated Sensor Hub(ISH) ( Fn# 002X)*/ \
35 { 0x00, 0xA0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #14h :Pin0: USB 3.0 xHCI Controller ( Fn# 002X) :Pin1: USB 3.0 xHCI Controller ( Fn# 002X) :Pin2: USB 3.0 xHCI Controller ( Fn# 002X) :Pin3: USB 3.0 xHCI Controller ( Fn# 002X)*/ \
36 { 0x00, 0xB0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #16h :Pin0: ME ( Fn# 002X) :Pin1: ME ( Fn# 002X) :Pin2: ME ( Fn# 002X) :Pin3: ME ( Fn# 002X)*/ \
37 { 0x00, 0xB8, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #17h :Pin0: SATA Controller ( Fn# 002X)*/ \
38 { 0x00, 0xD8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Bh :Pin0: PCIE Root Port #17 ( Fn# 002X) :Pin1: PCIE Root Port #17 ( Fn# 002X) :Pin2: PCIE Root Port #17 ( Fn# 002X) :Pin3: PCIE Root Port #17 ( Fn# 002X)*/ \
39 { 0x04, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
40 { 0x05, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
41 { 0x06, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
42 { 0x07, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
43 { 0x00, 0xE0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Ch :Pin0: PCIE Root Port #1 ( Fn# 002X) :Pin1: PCIE Root Port #1 ( Fn# 002X) :Pin2: PCIE Root Port #1 ( Fn# 002X) :Pin3: PCIE Root Port #1 ( Fn# 002X)*/ \
44 { 0x08, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 33, 0 }, /* Slot (Device #0x00) */ \
45 { 0x09, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 34, 0 }, /* Slot (Device #0x00) */ \
46 { 0x0A, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 8, 0 }, /* Slot (Device #0x00) */ \
47 { 0x0B, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 9, 0 }, /* Slot (Device #0x00) */ \
48 { 0x0C, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 10, 0 }, /* Slot (Device #0x00) */ \
49 { 0x0D, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
50 { 0x0E, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
51 { 0x0F, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
52 { 0x00, 0xE8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Dh :Pin0: PCIE Root Port #9 ( Fn# 002X) :Pin1: PCIE Root Port #9 ( Fn# 002X) :Pin2: PCIE Root Port #9 ( Fn# 002X) :Pin3: PCIE Root Port #9 ( Fn# 002X)*/ \
53 { 0x10, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
54 { 0x11, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
55 { 0x12, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
56 { 0x13, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
57 { 0x14, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
58 { 0x15, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
59 { 0x16, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
60 { 0x17, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
61 { 0x00, 0xF8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Fh :Pin0: LPC Bridge ( Fn# 002X) :Pin1: LPC Bridge ( Fn# 002X) :Pin2: LPC Bridge ( Fn# 002X) :Pin3: LPC Bridge ( Fn# 002X)*/ \
62 }
63
64 #define PCI_DEDICATED_IRQS 0xDC78
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpM_BusNumberTranslator.h Source File

  • MultiPlatform
_RvpM_BusNumberTranslator.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define BUS_NUMBER_TRANSLATOR_DATA { \
20 /* Bus#(Build), Bus#(RUN), BridgeDevFun#, BridgeDevFun#, ..., -1 */ \
21 /* --------------------------------------------------------------------------- */ \
22 0x00, 0, 0x00, (UINT8)-1, /* Host Bridge*/ \
23 0x01, 0, 0x00, 0x08, (UINT8)-1, /* P.E.G. Root Port D1F0 -> Host Bridge*/ \
24 0x02, 0, 0x00, 0x09, (UINT8)-1, /* P.E.G. Root Port D1F1 -> Host Bridge*/ \
25 0x03, 0, 0x00, 0x0A, (UINT8)-1, /* P.E.G. Root Port D1F2 -> Host Bridge*/ \
26 0x04, 0, 0x00, 0xD8, (UINT8)-1, /* PCIE Root Port #17 -> Host Bridge*/ \
27 0x05, 0, 0x00, 0xD9, (UINT8)-1, /* PCIE Root Port #18 -> Host Bridge*/ \
28 0x06, 0, 0x00, 0xDA, (UINT8)-1, /* PCIE Root Port #19 -> Host Bridge*/ \
29 0x07, 0, 0x00, 0xDB, (UINT8)-1, /* PCIE Root Port #20 -> Host Bridge*/ \
30 0x08, 0, 0x00, 0xE0, (UINT8)-1, /* PCIE Root Port #1 -> Host Bridge*/ \
31 0x09, 0, 0x00, 0xE1, (UINT8)-1, /* PCIE Root Port #2 -> Host Bridge*/ \
32 0x0a, 0, 0x00, 0xE2, (UINT8)-1, /* PCIE Root Port #3 -> Host Bridge*/ \
33 0x0b, 0, 0x00, 0xE3, (UINT8)-1, /* PCIE Root Port #4 -> Host Bridge*/ \
34 0x0c, 0, 0x00, 0xE4, (UINT8)-1, /* PCIE Root Port #5 -> Host Bridge*/ \
35 0x0d, 0, 0x00, 0xE5, (UINT8)-1, /* PCIE Root Port #6 -> Host Bridge*/ \
36 0x0e, 0, 0x00, 0xE6, (UINT8)-1, /* PCIE Root Port #7 -> Host Bridge*/ \
37 0x0f, 0, 0x00, 0xE7, (UINT8)-1, /* PCIE Root Port #8 -> Host Bridge*/ \
38 0x10, 0, 0x00, 0xE8, (UINT8)-1, /* PCIE Root Port #9 -> Host Bridge*/ \
39 0x11, 0, 0x00, 0xE9, (UINT8)-1, /* PCIE Root Port #10 -> Host Bridge*/ \
40 0x12, 0, 0x00, 0xEA, (UINT8)-1, /* PCIE Root Port #11 -> Host Bridge*/ \
41 0x13, 0, 0x00, 0xEB, (UINT8)-1, /* PCIE Root Port #12 -> Host Bridge*/ \
42 0x14, 0, 0x00, 0xEC, (UINT8)-1, /* PCIE Root Port #13 -> Host Bridge*/ \
43 0x15, 0, 0x00, 0xED, (UINT8)-1, /* PCIE Root Port #14 -> Host Bridge*/ \
44 0x16, 0, 0x00, 0xEE, (UINT8)-1, /* PCIE Root Port #15 -> Host Bridge*/ \
45 0x17, 0, 0x00, 0xEF, (UINT8)-1, /* PCIE Root Port #16 -> Host Bridge*/ \
46 /* NOTE: Bus#(RUN) is filled by IrqBoardInfo code after enumerating all PCI devices */ \
47 /* and reassigning the bus numbers in IRQ routing table. */ \
48 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpM_MpTableData.h Source File

  • MultiPlatform
_RvpM_MpTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define MP_TABLE_IRQ_DATA { \
20 /*+-------------------+----------------+----------------+----------------+----------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin |*/ \
22 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
23 /*| PCI Bus Device | APIC IO APIC| APIC IO APIC| APIC IO APIC| APIC IO APIC| Reserved |*/ \
24 /*| Number Number | Input# ID# | Input# ID# | Input# ID# | Input# ID# | must be 0 |*/ \
25 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
26 { 0x00, 0x01, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x01 :Pin0: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin1: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin2: P.E.G. Root Port D1F0 ( Fn# 0x00) :Pin3: P.E.G. Root Port D1F0 ( Fn# 0x00)*/ \
27 { 0x01, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
28 { 0x02, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
29 { 0x03, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
30 { 0x00, 0x02, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x02 :Pin0: I.G.D. ( Fn# 0x00)*/ \
31 { 0x00, 0x03, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x03 :Pin0: SA Audio Device ( Fn# 0x00)*/ \
32 { 0x00, 0x04, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x04 :Pin0: SA Thermal Device ( Fn# 0x00)*/ \
33 { 0x00, 0x07, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x07 :Pin0: SA Chap Device ( Fn# 0x00)*/ \
34 { 0x00, 0x13, 20, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x13 :Pin0: Integrated Sensor Hub(ISH) ( Fn# 0x00)*/ \
35 { 0x00, 0x14, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x14 :Pin0: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin1: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin2: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin3: USB 3.0 xHCI Controller ( Fn# 0x00)*/ \
36 { 0x00, 0x16, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x16 :Pin0: ME ( Fn# 0x00) :Pin1: ME ( Fn# 0x00) :Pin2: ME ( Fn# 0x00) :Pin3: ME ( Fn# 0x00)*/ \
37 { 0x00, 0x17, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x17 :Pin0: SATA Controller ( Fn# 0x00)*/ \
38 { 0x00, 0x1B, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1B :Pin0: PCIE Root Port #17 ( Fn# 0x00) :Pin1: PCIE Root Port #17 ( Fn# 0x00) :Pin2: PCIE Root Port #17 ( Fn# 0x00) :Pin3: PCIE Root Port #17 ( Fn# 0x00)*/ \
39 { 0x04, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
40 { 0x05, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
41 { 0x06, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
42 { 0x07, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
43 { 0x00, 0x1C, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1C :Pin0: PCIE Root Port #1 ( Fn# 0x00) :Pin1: PCIE Root Port #1 ( Fn# 0x00) :Pin2: PCIE Root Port #1 ( Fn# 0x00) :Pin3: PCIE Root Port #1 ( Fn# 0x00)*/ \
44 { 0x08, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 33 */ \
45 { 0x09, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 34 */ \
46 { 0x0A, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 08 */ \
47 { 0x0B, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 09 */ \
48 { 0x0C, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 10 */ \
49 { 0x0D, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
50 { 0x0E, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
51 { 0x0F, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
52 { 0x00, 0x1D, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1D :Pin0: PCIE Root Port #9 ( Fn# 0x00) :Pin1: PCIE Root Port #9 ( Fn# 0x00) :Pin2: PCIE Root Port #9 ( Fn# 0x00) :Pin3: PCIE Root Port #9 ( Fn# 0x00)*/ \
53 { 0x10, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
54 { 0x11, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
55 { 0x12, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
56 { 0x13, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
57 { 0x14, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
58 { 0x15, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
59 { 0x16, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
60 { 0x17, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
61 { 0x00, 0x1F, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1F :Pin0: LPC Bridge ( Fn# 0x00) :Pin1: LPC Bridge ( Fn# 0x00) :Pin2: LPC Bridge ( Fn# 0x00) :Pin3: LPC Bridge ( Fn# 0x00)*/ \
62 }
63
64 #define MP_TABLE_APIC_DATA { \
65 /*+----------------------+----------+*/ \
66 /*| IO APIC IO APIC | IO APIC |*/ \
67 /*| Address ID(BUILD)| ID(POST) |*/ \
68 /*+----------------------+----------+*/ \
69 { 0xFEC00000, 0x02, 0x00 }, /* 000 : Int vector base. IO APIC to serve Legacy Interrupts */ \
70 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _RvpM_PirqTableData.h Source File

  • MultiPlatform
_RvpM_PirqTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define PIRQ_TABLE_IRQ_DATA { \
20 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin | |*/ \
22 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
23 /*| PCI Bus Dev Num | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Physical Reserved |*/ \
24 /*| Number (Shl 3) | Reg Routable to Pin | Reg Routable Pin | Reg Routable Pin | Reg Routable Pin | Slot Num Byte |*/ \
25 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
26 { 0x00, 0x08, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #01h :Pin0: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin1: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin2: P.E.G. Root Port D1F0 ( Fn# 002X) :Pin3: P.E.G. Root Port D1F0 ( Fn# 002X)*/ \
27 { 0x01, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
28 { 0x02, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
29 { 0x03, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
30 { 0x00, 0x10, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #02h :Pin0: I.G.D. ( Fn# 002X)*/ \
31 { 0x00, 0x18, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #03h :Pin0: SA Audio Device ( Fn# 002X)*/ \
32 { 0x00, 0x20, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #04h :Pin0: SA Thermal Device ( Fn# 002X)*/ \
33 { 0x00, 0x38, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #07h :Pin0: SA Chap Device ( Fn# 002X)*/ \
34 { 0x00, 0x98, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #13h :Pin0: Integrated Sensor Hub(ISH) ( Fn# 002X)*/ \
35 { 0x00, 0xA0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #14h :Pin0: USB 3.0 xHCI Controller ( Fn# 002X) :Pin1: USB 3.0 xHCI Controller ( Fn# 002X) :Pin2: USB 3.0 xHCI Controller ( Fn# 002X) :Pin3: USB 3.0 xHCI Controller ( Fn# 002X)*/ \
36 { 0x00, 0xB0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #16h :Pin0: ME ( Fn# 002X) :Pin1: ME ( Fn# 002X) :Pin2: ME ( Fn# 002X) :Pin3: ME ( Fn# 002X)*/ \
37 { 0x00, 0xB8, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #17h :Pin0: SATA Controller ( Fn# 002X)*/ \
38 { 0x00, 0xD8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Bh :Pin0: PCIE Root Port #17 ( Fn# 002X) :Pin1: PCIE Root Port #17 ( Fn# 002X) :Pin2: PCIE Root Port #17 ( Fn# 002X) :Pin3: PCIE Root Port #17 ( Fn# 002X)*/ \
39 { 0x04, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
40 { 0x05, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
41 { 0x06, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
42 { 0x07, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
43 { 0x00, 0xE0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Ch :Pin0: PCIE Root Port #1 ( Fn# 002X) :Pin1: PCIE Root Port #1 ( Fn# 002X) :Pin2: PCIE Root Port #1 ( Fn# 002X) :Pin3: PCIE Root Port #1 ( Fn# 002X)*/ \
44 { 0x08, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 33, 0 }, /* Slot (Device #0x00) */ \
45 { 0x09, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 34, 0 }, /* Slot (Device #0x00) */ \
46 { 0x0A, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 8, 0 }, /* Slot (Device #0x00) */ \
47 { 0x0B, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 9, 0 }, /* Slot (Device #0x00) */ \
48 { 0x0C, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 10, 0 }, /* Slot (Device #0x00) */ \
49 { 0x0D, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
50 { 0x0E, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
51 { 0x0F, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
52 { 0x00, 0xE8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Dh :Pin0: PCIE Root Port #9 ( Fn# 002X) :Pin1: PCIE Root Port #9 ( Fn# 002X) :Pin2: PCIE Root Port #9 ( Fn# 002X) :Pin3: PCIE Root Port #9 ( Fn# 002X)*/ \
53 { 0x10, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
54 { 0x11, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
55 { 0x12, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
56 { 0x13, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
57 { 0x14, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
58 { 0x15, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
59 { 0x16, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
60 { 0x17, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
61 { 0x00, 0xF8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Fh :Pin0: LPC Bridge ( Fn# 002X) :Pin1: LPC Bridge ( Fn# 002X) :Pin2: LPC Bridge ( Fn# 002X) :Pin3: LPC Bridge ( Fn# 002X)*/ \
62 }
63
64 #define PCI_DEDICATED_IRQS 0xDC78
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Sds_BusNumberTranslator.h Source File

  • MultiPlatform
_Sds_BusNumberTranslator.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define BUS_NUMBER_TRANSLATOR_DATA { \
20 /* Bus#(Build), Bus#(RUN), BridgeDevFun#, BridgeDevFun#, ..., -1 */ \
21 /* --------------------------------------------------------------------------- */ \
22 0x00, 0, 0x00, (UINT8)-1, /* Host Bridge*/ \
23 0x01, 0, 0x00, 0xE0, (UINT8)-1, /* PCIE Root Port #1 -> Host Bridge*/ \
24 0x02, 0, 0x00, 0xE1, (UINT8)-1, /* PCIE Root Port #2 -> Host Bridge*/ \
25 0x03, 0, 0x00, 0xE2, (UINT8)-1, /* PCIE Root Port #3 -> Host Bridge*/ \
26 0x04, 0, 0x00, 0xE3, (UINT8)-1, /* PCIE Root Port #4 -> Host Bridge*/ \
27 0x05, 0, 0x00, 0xE4, (UINT8)-1, /* PCIE Root Port #5 -> Host Bridge*/ \
28 0x06, 0, 0x00, 0xE5, (UINT8)-1, /* PCIE Root Port #6 -> Host Bridge*/ \
29 0x07, 0, 0x00, 0xE6, (UINT8)-1, /* PCIE Root Port #7 -> Host Bridge*/ \
30 0x08, 0, 0x00, 0xE7, (UINT8)-1, /* PCIE Root Port #8 -> Host Bridge*/ \
31 0x09, 0, 0x00, 0xE8, (UINT8)-1, /* PCIE Root Port #9 -> Host Bridge*/ \
32 0x0a, 0, 0x00, 0xE9, (UINT8)-1, /* PCIE Root Port #10 -> Host Bridge*/ \
33 0x0b, 0, 0x00, 0xEA, (UINT8)-1, /* PCIE Root Port #11 -> Host Bridge*/ \
34 0x0c, 0, 0x00, 0xEB, (UINT8)-1, /* PCIE Root Port #12 -> Host Bridge*/ \
35 /* NOTE: Bus#(RUN) is filled by IrqBoardInfo code after enumerating all PCI devices */ \
36 /* and reassigning the bus numbers in IRQ routing table. */ \
37 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Sds_MpTableData.h Source File

  • MultiPlatform
_Sds_MpTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define MP_TABLE_IRQ_DATA { \
20 /*+-------------------+----------------+----------------+----------------+----------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin |*/ \
22 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
23 /*| PCI Bus Device | APIC IO APIC| APIC IO APIC| APIC IO APIC| APIC IO APIC| Reserved |*/ \
24 /*| Number Number | Input# ID# | Input# ID# | Input# ID# | Input# ID# | must be 0 |*/ \
25 /*+-------------------+----------------+----------------+----------------+----------------+-----------+*/ \
26 { 0x00, 0x02, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x02 :Pin0: I.G.D. ( Fn# 0x00)*/ \
27 { 0x00, 0x03, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x03 :Pin0: SA Audio Device ( Fn# 0x00)*/ \
28 { 0x00, 0x04, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x04 :Pin0: SA Thermal Device ( Fn# 0x00)*/ \
29 { 0x00, 0x07, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x07 :Pin0: SA Chap Device ( Fn# 0x00)*/ \
30 { 0x00, 0x13, 20, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x13 :Pin0: Integrated Sensor Hub(ISH) ( Fn# 0x00)*/ \
31 { 0x00, 0x14, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x14 :Pin0: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin1: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin2: USB 3.0 xHCI Controller ( Fn# 0x00) :Pin3: USB 3.0 xHCI Controller ( Fn# 0x00)*/ \
32 { 0x00, 0x15, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x15 :Pin0: SERIALIO I2C Controller #0 ( Fn# 0x00) :Pin1: SERIALIO I2C Controller #0 ( Fn# 0x00) :Pin2: SERIALIO I2C Controller #0 ( Fn# 0x00) :Pin3: SERIALIO I2C Controller #0 ( Fn# 0x00)*/ \
33 { 0x00, 0x16, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x16 :Pin0: ME ( Fn# 0x00) :Pin1: ME ( Fn# 0x00) :Pin2: ME ( Fn# 0x00) :Pin3: ME ( Fn# 0x00)*/ \
34 { 0x00, 0x17, 16, 0x02, 00, 0x00, 00, 0x00, 00, 0x00, 0 }, /* Device #0x17 :Pin0: SATA Controller ( Fn# 0x00)*/ \
35 { 0x00, 0x19, 32, 0x02, 33, 0x02, 34, 0x02, 35, 0x02, 0 }, /* Device #0x19 :Pin0: SERIALIO UART Controller #2 ( Fn# 0x00) :Pin1: SERIALIO UART Controller #2 ( Fn# 0x00) :Pin2: SERIALIO UART Controller #2 ( Fn# 0x00) :Pin3: SERIALIO UART Controller #2 ( Fn# 0x00)*/ \
36 { 0x00, 0x1C, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1C :Pin0: PCIE Root Port #1 ( Fn# 0x00) :Pin1: PCIE Root Port #1 ( Fn# 0x00) :Pin2: PCIE Root Port #1 ( Fn# 0x00) :Pin3: PCIE Root Port #1 ( Fn# 0x00)*/ \
37 { 0x01, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 33 */ \
38 { 0x02, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 34 */ \
39 { 0x03, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 08 */ \
40 { 0x04, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 09 */ \
41 { 0x05, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 10 */ \
42 { 0x06, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 16 */ \
43 { 0x07, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 17 */ \
44 { 0x08, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 18 */ \
45 { 0x00, 0x1D, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1D :Pin0: PCIE Root Port #9 ( Fn# 0x00) :Pin1: PCIE Root Port #9 ( Fn# 0x00) :Pin2: PCIE Root Port #9 ( Fn# 0x00) :Pin3: PCIE Root Port #9 ( Fn# 0x00)*/ \
46 { 0x09, 0x00, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
47 { 0x0A, 0x00, 17, 0x02, 18, 0x02, 19, 0x02, 16, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
48 { 0x0B, 0x00, 18, 0x02, 19, 0x02, 16, 0x02, 17, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
49 { 0x0C, 0x00, 19, 0x02, 16, 0x02, 17, 0x02, 18, 0x02, 0 }, /* Device #0x00, Slot 00 */ \
50 { 0x00, 0x1E, 20, 0x02, 21, 0x02, 22, 0x02, 23, 0x02, 0 }, /* Device #0x1E :Pin0: SERIALIO(UART #0) ( Fn# 0x00) :Pin1: SERIALIO(UART #0) ( Fn# 0x00) :Pin2: SERIALIO(UART #0) ( Fn# 0x00) :Pin3: SERIALIO(UART #0) ( Fn# 0x00)*/ \
51 { 0x00, 0x1F, 16, 0x02, 17, 0x02, 18, 0x02, 19, 0x02, 0 }, /* Device #0x1F :Pin0: LPC Bridge ( Fn# 0x00) :Pin1: LPC Bridge ( Fn# 0x00) :Pin2: LPC Bridge ( Fn# 0x00) :Pin3: LPC Bridge ( Fn# 0x00)*/ \
52 }
53
54 #define MP_TABLE_APIC_DATA { \
55 /*+----------------------+----------+*/ \
56 /*| IO APIC IO APIC | IO APIC |*/ \
57 /*| Address ID(BUILD)| ID(POST) |*/ \
58 /*+----------------------+----------+*/ \
59 { 0xFEC00000, 0x02, 0x00 }, /* 000 : Int vector base. IO APIC to serve Legacy Interrupts */ \
60 }
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: _Sds_PirqTableData.h Source File

  • MultiPlatform
_Sds_PirqTableData.h
Go to the documentation of this file.
1 /** @file
2
3 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
4 This software and associated documentation (if any) is furnished
5 under a license and may only be used or copied in accordance
6 with the terms of the license. Except as permitted by such
7 license, no part of this software or documentation may be
8 reproduced, stored in a retrieval system, or transmitted in any
9 form or by any means without the express written consent of
10 Intel Corporation.
11
12 **/
13
14 //
15 // Automatically generated by ACE ver 1.63 PIRQTRANS
16 // Please DO NOT modify !!!
17 //
18
19 #define PIRQ_TABLE_IRQ_DATA { \
20 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
21 /*| Device Location | Int A Pin | Int B Pin | Int C Pin | Int D Pin | |*/ \
22 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
23 /*| PCI Bus Dev Num | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Chipset Bitmap of IRQs | Physical Reserved |*/ \
24 /*| Number (Shl 3) | Reg Routable to Pin | Reg Routable Pin | Reg Routable Pin | Reg Routable Pin | Slot Num Byte |*/ \
25 /*+-------------------+---------------------------+---------------------------+---------------------------+---------------------------+--------------------+*/ \
26 { 0x00, 0x10, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #02h :Pin0: I.G.D. ( Fn# 002X)*/ \
27 { 0x00, 0x18, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #03h :Pin0: SA Audio Device ( Fn# 002X)*/ \
28 { 0x00, 0x20, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #04h :Pin0: SA Thermal Device ( Fn# 002X)*/ \
29 { 0x00, 0x38, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #07h :Pin0: SA Chap Device ( Fn# 002X)*/ \
30 { 0x00, 0x98, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #13h :Pin0: Integrated Sensor Hub(ISH) ( Fn# 002X)*/ \
31 { 0x00, 0xA0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #14h :Pin0: USB 3.0 xHCI Controller ( Fn# 002X) :Pin1: USB 3.0 xHCI Controller ( Fn# 002X) :Pin2: USB 3.0 xHCI Controller ( Fn# 002X) :Pin3: USB 3.0 xHCI Controller ( Fn# 002X)*/ \
32 { 0x00, 0xA8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #15h :Pin0: SERIALIO I2C Controller #0 ( Fn# 002X) :Pin1: SERIALIO I2C Controller #0 ( Fn# 002X) :Pin2: SERIALIO I2C Controller #0 ( Fn# 002X) :Pin3: SERIALIO I2C Controller #0 ( Fn# 002X)*/ \
33 { 0x00, 0xB0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #16h :Pin0: ME ( Fn# 002X) :Pin1: ME ( Fn# 002X) :Pin2: ME ( Fn# 002X) :Pin3: ME ( Fn# 002X)*/ \
34 { 0x00, 0xB8, 0x60, 0xDC78, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0, 0 }, /* Device #17h :Pin0: SATA Controller ( Fn# 002X)*/ \
35 { 0x00, 0xC8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #19h :Pin0: SERIALIO UART Controller #2 ( Fn# 002X) :Pin1: SERIALIO UART Controller #2 ( Fn# 002X) :Pin2: SERIALIO UART Controller #2 ( Fn# 002X) :Pin3: SERIALIO UART Controller #2 ( Fn# 002X)*/ \
36 { 0x00, 0xE0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Ch :Pin0: PCIE Root Port #1 ( Fn# 002X) :Pin1: PCIE Root Port #1 ( Fn# 002X) :Pin2: PCIE Root Port #1 ( Fn# 002X) :Pin3: PCIE Root Port #1 ( Fn# 002X)*/ \
37 { 0x01, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 33, 0 }, /* Slot (Device #0x00) */ \
38 { 0x02, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 34, 0 }, /* Slot (Device #0x00) */ \
39 { 0x03, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 8, 0 }, /* Slot (Device #0x00) */ \
40 { 0x04, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 9, 0 }, /* Slot (Device #0x00) */ \
41 { 0x05, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 10, 0 }, /* Slot (Device #0x00) */ \
42 { 0x06, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 16, 0 }, /* Slot (Device #0x00) */ \
43 { 0x07, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 17, 0 }, /* Slot (Device #0x00) */ \
44 { 0x08, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 18, 0 }, /* Slot (Device #0x00) */ \
45 { 0x00, 0xE8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Dh :Pin0: PCIE Root Port #9 ( Fn# 002X) :Pin1: PCIE Root Port #9 ( Fn# 002X) :Pin2: PCIE Root Port #9 ( Fn# 002X) :Pin3: PCIE Root Port #9 ( Fn# 002X)*/ \
46 { 0x09, 0x00, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
47 { 0x0A, 0x00, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
48 { 0x0B, 0x00, 0x62, 0xDC78, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
49 { 0x0C, 0x00, 0x63, 0xDC78, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0, 0 }, /* Slot (Device #0x00) */ \
50 { 0x00, 0xF0, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Eh :Pin0: SERIALIO(UART #0) ( Fn# 002X) :Pin1: SERIALIO(UART #0) ( Fn# 002X) :Pin2: SERIALIO(UART #0) ( Fn# 002X) :Pin3: SERIALIO(UART #0) ( Fn# 002X)*/ \
51 { 0x00, 0xF8, 0x60, 0xDC78, 0x61, 0xDC78, 0x62, 0xDC78, 0x63, 0xDC78, 0, 0 }, /* Device #1Fh :Pin0: LPC Bridge ( Fn# 002X) :Pin1: LPC Bridge ( Fn# 002X) :Pin2: LPC Bridge ( Fn# 002X) :Pin3: LPC Bridge ( Fn# 002X)*/ \
52 }
53
54 #define PCI_DEDICATED_IRQS 0xDC78
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AcpiCommon.h Source File

  • Acpi
  • AcpiTables
  • Include
AcpiCommon.h
Go to the documentation of this file.
1 /** @file
2 Header file for ACPI common Initialization Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ACPI_COMMON_H_
36 #define _ACPI_COMMON_H_
37
38 #define EFI_ACPI_S3_RESUME_SCRIPT_TABLE 0x00
39
40
41
42
43 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AcpiPlatform.c Source File

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe
AcpiPlatform.c
Go to the documentation of this file.
1 /** @file
2 ACPI Platform Driver
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include <Base.h>
35 #include <Uefi.h>
36 #include <Library/HobLib.h>
37 #include <Guid/HobList.h>
38 #include <Protocol/FirmwareVolume2.h>
39 #include <PlatformBoardId.h>
40 #include <IndustryStandard/AcpiAml.h>
41 #include <IndustryStandard/Pci30.h>
42 #include "AcpiPlatform.h"
43 #include <Protocol/CpuNvsArea.h>
44 #include <Library/PciSegmentLib.h>
45 #include <Library/PchInfoLib.h>
46 #include <Library/PchPcieRpLib.h>
47 #include <Library/PchSerialIoLib.h>
48 #include <Library/GpioLib.h>
49 #include <Library/PchEspiLib.h>
50 #include <MeBiosPayloadHob.h>
51 #include <PlatformBoardConfig.h>
52 #include <Board/Include/BoardHook.h>
53 #include <Library/CpuPlatformLib.h>
54 #include <PlatformBoardType.h>
55 #include <PlatformInfo.h>
56 #include <Guid/S3MemoryVariable.h>
57 #include <Protocol/VariableLock.h>
58 #include <Mcfg.h>
59 #include <SaTcssHob.h>
60
61
62 //
63 // Global variables
64 //
65 GLOBAL_REMOVE_IF_UNREFERENCED VOID *mGfxNvsAddress;
66 GLOBAL_REMOVE_IF_UNREFERENCED ME_SETUP mMeSetup;
67 GLOBAL_REMOVE_IF_UNREFERENCED PCH_SETUP mPchSetup;
68 GLOBAL_REMOVE_IF_UNREFERENCED SETUP_DATA mSystemConfiguration;
69 GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL mPlatformNvsAreaProtocol;
70 GLOBAL_REMOVE_IF_UNREFERENCED CPU_NVS_AREA_PROTOCOL mCpuNvsArea;
71
72 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_IO2_PROTOCOL *mCpuIo;
73 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_ID_ORDER_MAP mCpuApicIdOrderTable[MAX_CPU_NUM];
74 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_APIC_ID_REORDER_MAP mCpuApicIdReorderTable[MAX_CPU_NUM];
75
76 GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_PACKAGE_INFO mSbspPackageInfo;
77 GLOBAL_REMOVE_IF_UNREFERENCED SA_TCSS_HOB *mSaTcssHob;
78
79 //
80 // Function implementations
81 //
82
83 /**
84 Install Xhci ACPI Table
85 **/
86 VOID
87 InstallXhciAcpiTable (
88 VOID
89 )
90 {
91 EFI_HANDLE *HandleBuffer;
92 EFI_STATUS Status;
93 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
94 EFI_ACPI_COMMON_HEADER *CurrentTable;
95 UINT32 FvStatus;
96 UINTN Size;
97 UINTN TableHandle;
98 INTN Instance;
99 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
100 EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
101 EFI_GUID EfiAcpiMultiTableStorageGuid;
102
103 EfiAcpiMultiTableStorageGuid = gEfiAcpiTableStorageGuid;
104 HandleBuffer = 0;
105 Instance = 0;
106 TableHandle = 0;
107 CurrentTable = NULL;
108 FwVol = NULL;
109
110 DEBUG ((DEBUG_INFO, "InstallXhciAcpiTable\n"));
111 //
112 // Update OEM table ID
113 //
114 if (PcdGet64 (PcdXhciAcpiTableSignature) == 0) {
115 return;
116 }
117
118 //
119 // Find the AcpiSupport protocol
120 //
121 Status = LocateSupportProtocol (
122 &gEfiAcpiTableProtocolGuid,
123 EfiAcpiMultiTableStorageGuid,
124 (VOID **) &AcpiTable,
125 FALSE
126 );
127 ASSERT_EFI_ERROR (Status);
128
129 //
130 // Locate the firmware volume protocol
131 //
132 Status = LocateSupportProtocol (
133 &gEfiFirmwareVolume2ProtocolGuid,
134 EfiAcpiMultiTableStorageGuid,
135 (VOID **) &FwVol,
136 TRUE
137 );
138
139 //
140 // Read tables from the storage file.
141 //
142 while (Status == EFI_SUCCESS) {
143 Status = FwVol->ReadSection (
144 FwVol,
145 &EfiAcpiMultiTableStorageGuid,
146 EFI_SECTION_RAW,
147 Instance,
148 (VOID **) &CurrentTable,
149 &Size,
150 &FvStatus
151 );
152
153 if (!EFI_ERROR (Status)) {
154
155 TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
156
157 if (TableHeader->OemTableId == PcdGet64 (PcdXhciAcpiTableSignature)) {
158 DEBUG ((DEBUG_INFO, "Install xhci table: %x\n", TableHeader->OemTableId));
159 //
160 // Add the table
161 //
162 TableHandle = 0;
163
164 Status = AcpiTable->InstallAcpiTable (
165 AcpiTable,
166 CurrentTable,
167 CurrentTable->Length,
168 &TableHandle
169 );
170
171 break;
172 }
173
174 //
175 // Increment the instance
176 //
177 Instance++;
178 CurrentTable = NULL;
179 }
180 }
181 }
182
183 VOID
184 PublishOverClockingAcpiTable (
185 VOID
186 )
187 {
188 EFI_STATUS Status;
189 EFI_HANDLE *HandleBuffer;
190 UINTN NumberOfHandles;
191 UINTN Index;
192 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
193 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
194 EFI_ACPI_COMMON_HEADER *Table;
195 UINTN Size;
196 UINT32 FvStatus;
197 EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
198 UINTN TableHandle;
199 EFI_ACPI_TABLE_VERSION Version;
200
201 FwVol = NULL;
202 Table = NULL;
203
204 DEBUG ((DEBUG_INFO, "PublishOverClockingAcpiTable\n"));
205
206 //
207 // Locate FV protocol.
208 //
209 Status = gBS->LocateHandleBuffer (
210 ByProtocol,
211 &gEfiFirmwareVolume2ProtocolGuid,
212 NULL,
213 &NumberOfHandles,
214 &HandleBuffer
215 );
216 ASSERT_EFI_ERROR (Status);
217
218 //
219 // Look for FV with ACPI storage file
220 //
221 for (Index = 0; Index < NumberOfHandles; Index++) {
222
223 //
224 // Get the protocol on this handle
225 // This should not fail because of LocateHandleBuffer
226 //
227 Status = gBS->HandleProtocol (
228 HandleBuffer[Index],
229 &gEfiFirmwareVolume2ProtocolGuid,
230 (VOID **) &FwVol
231 );
232 ASSERT_EFI_ERROR (Status);
233
234 //
235 // See if it has the OverClocking Acpi Table file
236 //
237 Status = FwVol->ReadSection (
238 FwVol,
239 &gOcAcpiTableStorageGuid,
240 EFI_SECTION_RAW,
241 0,
242 (VOID **) &Table,
243 &Size,
244 &FvStatus
245 );
246 if (!EFI_ERROR (Status)) {
247 break;
248 }
249 }
250 //
251 // Free any allocated buffers
252 //
253 FreePool (HandleBuffer);
254
255 //
256 // Not find the table, it's fine the over clocking support is not enabled
257 //
258 if (Table == NULL) {
259 return;
260 }
261
262 //
263 // By default, publish it in all ACPI table versions.
264 //
265 Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
266
267 Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
268
269 TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
270 if (CompareMem (&TableHeader->OemTableId, "PerfTune", 8) == 0) {
271 TableHandle = 0;
272 Status = AcpiTable->InstallAcpiTable (
273 AcpiTable,
274 Table,
275 Table->Length,
276 &TableHandle
277 );
278 }
279 }
280
281 /**
282 Locate the first instance of a protocol. If the protocol requested is an
283 FV protocol, then it will return the first FV that contains the ACPI table
284 storage file.
285
286 @param[in] Protocol The protocol to find.
287 @param[in] Instance Return pointer to the first instance of the protocol.
288 @param[in] Type TRUE if the desired protocol is a FV protocol.
289
290 @retval EFI_SUCCESS The function completed successfully.
291 @retval EFI_NOT_FOUND The protocol could not be located.
292 @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
293 **/
294 EFI_STATUS
295 LocateSupportProtocol (
296 IN EFI_GUID *Protocol,
297 IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
298 OUT VOID **Instance,
299 IN BOOLEAN Type
300 )
301 {
302 EFI_STATUS Status;
303 EFI_HANDLE *HandleBuffer;
304 UINTN NumberOfHandles;
305 EFI_FV_FILETYPE FileType;
306 UINT32 FvStatus;
307 EFI_FV_FILE_ATTRIBUTES Attributes;
308 UINTN Size;
309 UINTN Index;
310
311 //
312 // Locate protocol.
313 //
314 Status = gBS->LocateHandleBuffer (
315 ByProtocol,
316 Protocol,
317 NULL,
318 &NumberOfHandles,
319 &HandleBuffer
320 );
321 if (EFI_ERROR (Status)) {
322 //
323 // Defined errors at this time are not found and out of resources.
324 //
325 return Status;
326 }
327
328 //
329 // Looking for FV with ACPI storage file
330 //
331 for (Index = 0; Index < NumberOfHandles; Index++) {
332
333 //
334 // Get the protocol on this handle
335 // This should not fail because of LocateHandleBuffer
336 //
337 Status = gBS->HandleProtocol (
338 HandleBuffer[Index],
339 Protocol,
340 Instance
341 );
342 ASSERT_EFI_ERROR (Status);
343
344 if (!Type) {
345
346 //
347 // Not looking for the FV protocol, so find the first instance of the
348 // protocol. There should not be any errors because our handle buffer
349 // should always contain at least one or LocateHandleBuffer would have
350 // returned not found.
351 //
352 break;
353 }
354
355 //
356 // See if it has the ACPI storage file
357 //
358 Size = 0;
359 FvStatus = 0;
360 Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
361 *Instance,
362 &gEfiAcpiMultiTableStorageGuid,
363 NULL,
364 &Size,
365 &FileType,
366 &Attributes,
367 &FvStatus
368 );
369
370 //
371 // If we found it, then we are done
372 //
373 if (Status == EFI_SUCCESS) {
374 break;
375 }
376 }
377
378 //
379 // Our exit status is determined by the success of the previous operations
380 // If the protocol was found, Instance already points to it.
381 //
382 //
383 // Free any allocated buffers
384 //
385 FreePool (HandleBuffer);
386
387 return Status;
388 }
389
390 /*
391 This function will determine whether Native ASPM is supported on the platform.
392
393 @param[in] SystemConfiguration System configuration data
394
395 @return TRUE if Native ASPM is supported, FALSE otherwise
396 */
397 BOOLEAN
398 IsNativeAspmSupported (
399 CONST SETUP_DATA* SystemConfiguration
400 )
401 {
402 if (SystemConfiguration->PciExpNative == 0) {
403 return FALSE;
404 }
405 switch (SystemConfiguration->NativeAspmEnable) {
406 case 0:
407 return FALSE;
408 case 1:
409 return TRUE;
410 case 2: /* AUTO */
411 return PchIsPcieNativeAspmSupported ();
412 default:
413 ASSERT (0);
414 }
415 return TRUE;
416 }
417
418 /**
419 This function will provide the EC GPE number for ECDT update according to platform design
420
421 @retval EcGpeNumber EC GPE number to be reported in ECDT
422 **/
423 UINT32
424 GetEcGpeNumber (
425 VOID
426 )
427 {
428 UINT32 EcGpeNumber;
429
430 //
431 // EC GPE number assignment should be same as Method _GPE under ACPI EC Device which is used for OS without ECDT support
432 //
433 if (IsEspiEnabled ()) {
434 EcGpeNumber = 0x6E;
435 } else {
436 EcGpeNumber = 23;
437 if (mPlatformNvsAreaProtocol.Area->PcdSmcRuntimeSciPin != 0) {
438 GpioGetGpeNumber ((GPIO_PAD) mPlatformNvsAreaProtocol.Area->PcdSmcRuntimeSciPin, &EcGpeNumber);
439 }
440 }
441
442 DEBUG((DEBUG_INFO, "ACPI EcGpeNumber = 0x%x\n ", EcGpeNumber));
443
444 return EcGpeNumber;
445 }
446
447 /**
448 This function will update any runtime platform specific information.
449 This currently includes:
450 Setting OEM table values, ID, table ID, creator ID and creator revision.
451 Enabling the proper processor entries in the APIC tables
452 It also indicates with which ACPI table version the table belongs.
453
454 @param[in] Table The table to update
455 @param[in] Version Where to install this table
456
457 @retval EFI_SUCCESS Updated tables commplete.
458 **/
459 EFI_STATUS
460 PlatformUpdateTables (
461 IN OUT EFI_ACPI_COMMON_HEADER *Table,
462 IN OUT EFI_ACPI_TABLE_VERSION *Version
463 )
464 {
465 EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
466 UINT8 *CurrPtr;
467 UINT8 *TmpDsdtPointer;
468 UINT8 *EndPtr;
469 UINT8 *TempPtr;
470 EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ApicPtr;
471 UINT8 CurrProcessor;
472 EFI_STATUS Status;
473 EFI_MP_SERVICES_PROTOCOL *MpService;
474 UINTN NumberOfCPUs;
475 UINT8 MaximumDsdtPointLength;
476 UINTN NumberOfEnabledCPUs;
477 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
478 UINT32 HpetBaseAdress;
479 UINT8 LocalApicCounter;
480 //UINT32 GcsRegister;
481 CPU_GENERATION CpuGeneration;
482
483 CurrPtr = NULL;
484 EndPtr = NULL;
485 ApicPtr = NULL;
486 TempPtr = NULL;
487 CurrProcessor = 0;
488 NumberOfCPUs = 1;
489 LocalApicCounter = 0;
490 MaximumDsdtPointLength = 20;
491 CpuGeneration = GetCpuGeneration ();
492
493 //
494 // This will be accurate except for FACS structure
495 //
496 TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
497
498 //
499 // Update the OEM and creator information for every table except FACS.
500 //
501 if (Table->Signature != EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {
502 *(UINT32 *) (TableHeader->OemId) = 'I' + ('N' << 8) + ('T' << 16) + ('E' << 24);
503 *(UINT16 *) (TableHeader->OemId + 4) = 'L' + (' ' << 8);
504
505 //
506 // Skip OEM table ID and creator information for SSDT tables, since these are
507 // created by an ASL compiler and the creator information is useful.
508 //
509 if (Table->Signature != EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
510 //
511 // Set through patchable PCD value
512 //
513 TableHeader->OemTableId = PcdGet64 (PcdAcpiDefaultOemTableId);
514 TableHeader->OemRevision = PcdGet32(PcdAcpiDefaultOemRevision);
515
516 //
517 // Update creator information
518 //
519 TableHeader->CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId);
520 TableHeader->CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision) ;
521 }
522 }
523
524 //
525 // Locate the PCI IO protocol
526 //
527 Status = gBS->LocateProtocol (
528 &gEfiPciRootBridgeIoProtocolGuid,
529 NULL,
530 (VOID **) &PciRootBridgeIo
531 );
532 ASSERT_EFI_ERROR (Status);
533
534 //
535 // Locate the MP services protocol
536 // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
537 //
538 Status = gBS->LocateProtocol (
539 &gEfiMpServiceProtocolGuid,
540 NULL,
541 (VOID **) &MpService
542 );
543 ASSERT_EFI_ERROR (Status);
544
545 //
546 // Determine the number of processors
547 //
548 MpService->GetNumberOfProcessors (
549 MpService,
550 &NumberOfCPUs,
551 &NumberOfEnabledCPUs
552 );
553
554 //
555 // By default, a table belongs in all ACPI table versions published.
556 // Some tables will override this because they have different versions of the table.
557 //
558 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
559
560 //
561 // Update the various table types with the necessary updates
562 //
563 switch (Table->Signature) {
564
565 case EFI_ACPI_1_0_APIC_SIGNATURE:
566 //
567 // if not MP and not APIC then don't publish the APIC tables.
568 //
569 //@todo mSystemConfiguration.ApicEnabled default value is 1. So, the following logic is not executed.
570 //if (mSystemConfiguration.ApicEnabled == 0) {
571 // *Version = EFI_ACPI_TABLE_VERSION_NONE;
572 // break;
573 //}
574 //
575 // Call for Local APIC ID Reorder
576 //
577 SortCpuLocalApicInTable (
578 MpService,
579 NumberOfCPUs,
580 NumberOfEnabledCPUs
581 );
582
583 CurrPtr = (UINT8 *) &((EFI_ACPI_DESCRIPTION_HEADER *) Table)[1];
584 CurrPtr = CurrPtr + 8;
585 //
586 // Size of Local APIC Address & Flag
587 //
588 EndPtr = (UINT8 *) Table;
589 EndPtr = EndPtr + Table->Length;
590
591 while (CurrPtr < EndPtr) {
592 ApicPtr = (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) CurrPtr;
593
594 //
595 // Check table entry type
596 //
597 if (ApicPtr->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) {
598 AppendCpuMapTableEntry (
599 ApicPtr,
600 NumberOfCPUs,
601 NumberOfEnabledCPUs,
602 LocalApicCounter
603 );
604 LocalApicCounter++;
605 }
606
607 //
608 // Go to the next structure in the APIC table
609 //
610 CurrPtr = CurrPtr + ApicPtr->Length;
611 }
612 break;
613
614 case EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
615 //
616 // Fix up all FACP Table values if configuration requires it.
617 // This code fixes up the following Table values:
618 // (1) C2/C3/CST Enable FACP values
619 // (2) RTC S4 Flag
620 //
621 {
622 EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
623
624 FadtPointer = (EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
625
626 //
627 // Check the version of the table
628 //
629 *Version = EFI_ACPI_TABLE_VERSION_NONE;
630 if (FadtPointer->Header.Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
631 *Version = EFI_ACPI_TABLE_VERSION_NONE;
632 } else if (FadtPointer->Header.Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
633 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0;
634 } else if (FadtPointer->Header.Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
635 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_3_0;
636 } else if (FadtPointer->Header.Revision == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
637 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_5_0;
638 } else if (FadtPointer->Header.Revision == EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
639 *Version = EFI_ACPI_TABLE_VERSION_5_0;
640 }
641
642 //
643 // Modify MSI capability based on setup
644 //
645 if((mSystemConfiguration.DiscreteTbtSupport == 1) && (mSystemConfiguration.EnableMsiInFadt == 0)) {
646 FadtPointer->IaPcBootArch |= (1 << 3);
647 }
648
649 //
650 // Modify Preferred_PM_Profile field based on Board SKU's. Default is set to Mobile
651 //
652 FadtPointer->PreferredPmProfile = PcdGet8 (PcdPreferredPmProfile);
653
654 //
655 // if Native ASPM is disabled, set FACP table to skip Native ASPM
656 //
657 if (!IsNativeAspmSupported (&mSystemConfiguration)) {
658 FadtPointer->IaPcBootArch |= 0x10;
659 }
660
661 //
662 // PME WAKE supported, set PCI_EXP_WAK, BIT14 of Fixed feature flags.
663 //
664 FadtPointer->Flags |= (EFI_ACPI_6_0_PCI_EXP_WAK);
665
666 if (mSystemConfiguration.LowPowerS0Idle) {
667 // The Flags field within the FADT (offset 112)
668 // 1) will have a new Low Power S0 Idle Capable ACPI flag (bit offset 21).
669 FadtPointer->Flags = (BIT21 | FadtPointer->Flags);
670 //Only passive docking available in Conected Standby mode. Clear Docking capability Bit
671 FadtPointer->Flags &= ~BIT9;
672 }
673 //
674 // Modify FADT Fixed Feature Flag to support 10 sec Power button.
675 // If 10sec Power button is enabled: Set PWR_BUTTON(bit4) in Fixed Feature Flag(FACP offset 112)
676 //
677 if ((mSystemConfiguration.LowPowerS0Idle == 1) || (mSystemConfiguration.TenSecondPowerButtonEnable == 1)) {
678 FadtPointer->Flags |= EFI_ACPI_2_0_PWR_BUTTON; // Set Fixed Power Button flag (Disabling Fixed Power button and enabling Control Method PB)
679 } else {
680 FadtPointer->Flags &= ~(EFI_ACPI_2_0_PWR_BUTTON); // Default clear fixed Power Button flag
681 }
682
683 //
684 // 1. set header revision.
685 //
686 FadtPointer->Header.Revision = EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION;
687
688 //
689 // 2. set all GAR register AccessSize to valid value.
690 //
691 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->ResetReg.AccessSize = EFI_ACPI_6_1_BYTE;
692 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aEvtBlk.AccessSize = EFI_ACPI_6_1_WORD;
693 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bEvtBlk.AccessSize = EFI_ACPI_6_1_WORD;
694 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aCntBlk.AccessSize = EFI_ACPI_6_1_WORD;
695 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bCntBlk.AccessSize = EFI_ACPI_6_1_WORD;
696 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm2CntBlk.AccessSize = EFI_ACPI_6_1_BYTE;
697 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPmTmrBlk.AccessSize = EFI_ACPI_6_1_DWORD;
698 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe0Blk.AccessSize = EFI_ACPI_6_1_BYTE;
699 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe1Blk.AccessSize = EFI_ACPI_6_1_BYTE;
700
701 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AddressSpaceId = 0x1;
702 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitWidth = 0x8;
703 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitOffset = 0;
704 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AccessSize = EFI_ACPI_6_1_DWORD;
705 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 4;
706
707 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AddressSpaceId = 0x1;
708 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitWidth = 0x8;
709 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitOffset = 0;
710 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AccessSize = EFI_ACPI_6_1_DWORD;
711 ((EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS;
712
713 //
714 // Set the S4BiosReq to 0 as we don't support it in the FACS for ICL.
715 //
716 FadtPointer->S4BiosReq = 0;
717
718 //
719 //BIOS should expose either 64 bits or 32 bits address, not both.
720 //
721 if (FadtPointer->XPm1aEvtBlk.Address != 0) {
722 FadtPointer->Pm1aEvtBlk = 0;
723 FadtPointer->Pm1aCntBlk = 0;
724 FadtPointer->Pm1EvtLen = 0;
725 FadtPointer->Pm1CntLen = 0;
726 }
727
728 if (FadtPointer->XPm2CntBlk.Address != 0) {
729 FadtPointer->Pm2CntBlk = 0;
730 FadtPointer->Pm2CntLen = 0;
731 }
732
733 //@todo RtcS4WakeEnable and PmTimerEnable default value is 1. So, the following logic is not executed.
734 ////
735 //// Check if RTC S4 is enabled
736 ////
737 //if (!mSystemConfiguration.RtcS4WakeEnable) {
738
739 // //
740 // // Clear the S4 RTC flag
741 // //
742 // FadtPointer->Flags &= ~EFI_ACPI_2_0_RTC_S4;
743 //}
744
745 ////
746 //// Check if PM timer is enabled
747 ////
748 //if (!mSystemConfiguration.PmTimerEnable) {
749
750 // //
751 // // Clear the PM timer flag
752 // //
753 // FadtPointer->Flags &= ~EFI_ACPI_3_0_USE_PLATFORM_CLOCK;
754 //}
755 }
756 break;
757
758 case EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
759 //
760 // These items only belong in the 1.0 tables.
761 //
762 *Version = EFI_ACPI_TABLE_VERSION_1_0B;
763 break;
764
765 case EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
766 //
767 // Fix up the AML code in the DSDT affected by end user options.
768 // Fix up the following ASL Code:
769 // (1) ACPI Global NVS Memory Base and Size.
770 // (2) ACPI Graphics NVS Memory Base and Size.
771 // (3) SMBus I/O Base.
772 // (4) Thermal Management Methods.
773 //
774 {
775 UINT8 *DsdtPointer;
776 UINT32 *Signature;
777 UINT8 *Operation;
778 UINT32 *Address;
779 UINT8 *Value;
780 UINT16 *Size;
781 BOOLEAN EnterDock = FALSE;
782 //
783 // Loop through the ASL looking for values that we must fix up.
784 //
785 CurrPtr = (UINT8 *) Table;
786 for (DsdtPointer = CurrPtr;
787 DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
788 DsdtPointer++
789 ) {
790 Signature = (UINT32 *) DsdtPointer;
791 switch (*Signature) {
792 //
793 // GNVS operation region
794 //
795 case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
796 //
797 // Conditional match. For Region Objects, the Operator will always be the
798 // byte immediately before the specific name. Therefore, subtract 1 to check
799 // the Operator.
800 //
801 Operation = DsdtPointer - 1;
802 if (*Operation == AML_EXT_REGION_OP) {
803 Address = (UINT32 *) (DsdtPointer + 6);
804 *Address = (UINT32) (UINTN) mPlatformNvsAreaProtocol.Area;
805 Size = (UINT16 *) (DsdtPointer + 11);
806 *Size = sizeof (PLATFORM_NVS_AREA);
807 }
808 break;
809
810 //
811 // _AC0 method
812 //
813 case (SIGNATURE_32 ('_', 'A', 'C', '0')):
814 //
815 // Conditional match. _AC0 is >63 and <4095 bytes, so the package length is 2 bytes.
816 // Therefore, subtract 3 to check the Operator.
817 //
818 Operation = DsdtPointer - 3;
819 if (*Operation == AML_METHOD_OP) {
820 //
821 // Check if we want _AC0 enabled
822 //
823 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
824 Signature = (UINT32 *) DsdtPointer;
825 *Signature = SIGNATURE_32 ('X', 'A', 'C', '0');
826 }
827 }
828 break;
829
830 //
831 // _AL0 method
832 //
833 case (SIGNATURE_32 ('_', 'A', 'L', '0')):
834 //
835 // Conditional match. For Name Objects, the Operator will always be the byte
836 // immediately before the specific name. Therefore, subtract 1 to check the
837 // Operator.
838 //
839 Operation = DsdtPointer - 1;
840 if (*Operation == AML_NAME_OP) {
841
842 //
843 // Check if we want _AL0 enabled
844 //
845 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
846 Signature = (UINT32 *) DsdtPointer;
847 *Signature = SIGNATURE_32 ('X', 'A', 'L', '0');
848 }
849 }
850 break;
851
852 //
853 // _AC1 method
854 //
855 case (SIGNATURE_32 ('_', 'A', 'C', '1')):
856 //
857 // Conditional match. _AC1 is < 63 bytes, so the package length is 1 byte.
858 // Therefore, subtract 2 to check the Operator.
859 //
860 Operation = DsdtPointer - 2;
861 if (*Operation == AML_METHOD_OP) {
862
863 //
864 // Check if we want _AC1 enabled
865 //
866 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
867 Signature = (UINT32 *) DsdtPointer;
868 *Signature = SIGNATURE_32 ('X', 'A', 'C', '1');
869 }
870 }
871 break;
872
873 //
874 // _AL1 method
875 //
876 case (SIGNATURE_32 ('_', 'A', 'L', '1')):
877 //
878 // Conditional match. For Name Objects, the Operator will always be the byte
879 // immediately before the specific name. Therefore, subtract 1 to check the
880 // Operator.
881 //
882 Operation = DsdtPointer - 1;
883 if (*Operation == AML_NAME_OP) {
884
885 //
886 // Check if we want _AL1 enabled
887 //
888 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
889 Signature = (UINT32 *) DsdtPointer;
890 *Signature = SIGNATURE_32 ('X', 'A', 'L', '1');
891 }
892 }
893 break;
894
895 //
896 // _AC2 method
897 //
898 case (SIGNATURE_32 ('_', 'A', 'C', '2')):
899 //
900 // Conditional match. _AC2 is < 63 bytes, so the package length is 1 byte.
901 // Therefore, subtract 2 to check the Operator.
902 //
903 Operation = DsdtPointer - 2;
904 if (*Operation == AML_METHOD_OP) {
905
906 //
907 // Check if we want _AC2 enabled
908 //
909 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
910 Signature = (UINT32 *) DsdtPointer;
911 *Signature = SIGNATURE_32 ('X', 'A', 'C', '2');
912 }
913 }
914 break;
915
916 //
917 // _AL2 method
918 //
919 case (SIGNATURE_32 ('_', 'A', 'L', '2')):
920 //
921 // Conditional match. For Name Objects, the Operator will always be the byte
922 // immediately before the specific name. Therefore, subtract 1 to check the
923 // Operator.
924 //
925 Operation = DsdtPointer - 1;
926 if (*Operation == AML_NAME_OP) {
927
928 //
929 // Check if we want _AL2 enabled
930 //
931 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
932 Signature = (UINT32 *) DsdtPointer;
933 *Signature = SIGNATURE_32 ('X', 'A', 'L', '2');
934 }
935 }
936 break;
937
938 //
939 // _AC3 method
940 //
941 case (SIGNATURE_32 ('_', 'A', 'C', '3')):
942 //
943 // Conditional match. _AC3 is < 63 bytes, so the package length is 1 byte.
944 // Therefore, subtract 2 to check the Operator.
945 //
946 Operation = DsdtPointer - 2;
947 if (*Operation == AML_METHOD_OP) {
948
949 //
950 // Check if we want _AC3 enabled
951 //
952 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
953 Signature = (UINT32 *) DsdtPointer;
954 *Signature = SIGNATURE_32 ('X', 'A', 'C', '3');
955 }
956 }
957 break;
958
959 //
960 // _AL3 method
961 //
962 case (SIGNATURE_32 ('_', 'A', 'L', '3')):
963 //
964 // Conditional match. For Name Objects, the Operator will always be the byte
965 // immediately before the specific name. Therefore, subtract 1 to check the
966 // Operator.
967 //
968 Operation = DsdtPointer - 1;
969 if (*Operation == AML_NAME_OP) {
970
971 //
972 // Check if we want _AL3 enabled
973 //
974 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
975 Signature = (UINT32 *) DsdtPointer;
976 *Signature = SIGNATURE_32 ('X', 'A', 'L', '3');
977 }
978 }
979 break;
980
981 //
982 // _AC4 method
983 //
984 case (SIGNATURE_32 ('_', 'A', 'C', '4')):
985 //
986 // Conditional match. _AC4 is < 63 bytes, so the package length is 1 byte.
987 // Therefore, subtract 2 to check the Operator.
988 //
989 Operation = DsdtPointer - 2;
990 if (*Operation == AML_METHOD_OP) {
991
992 //
993 // Check if we want _AC4 enabled
994 //
995 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
996 Signature = (UINT32 *) DsdtPointer;
997 *Signature = SIGNATURE_32 ('X', 'A', 'C', '4');
998 }
999 }
1000 break;
1001
1002 //
1003 // _AL4 method
1004 //
1005 case (SIGNATURE_32 ('_', 'A', 'L', '4')):
1006 //
1007 // Conditional match. For Name Objects, the Operator will always be the byte
1008 // immediately before the specific name. Therefore, subtract 1 to check the
1009 // Operator.
1010 //
1011 Operation = DsdtPointer - 1;
1012 if (*Operation == AML_NAME_OP) {
1013
1014 //
1015 // Check if we want _AL4 enabled
1016 //
1017 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1018 Signature = (UINT32 *) DsdtPointer;
1019 *Signature = SIGNATURE_32 ('X', 'A', 'L', '4');
1020 }
1021 }
1022 break;
1023
1024 //
1025 // _AC5 method
1026 //
1027 case (SIGNATURE_32 ('_', 'A', 'C', '5')):
1028 //
1029 // Conditional match. _AC5 is < 63 bytes, so the package length is 1 byte.
1030 // Therefore, subtract 2 to check the Operator.
1031 //
1032 Operation = DsdtPointer - 2;
1033 if (*Operation == AML_METHOD_OP) {
1034
1035 //
1036 // Check if we want _AC5 enabled
1037 //
1038 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1039 Signature = (UINT32 *) DsdtPointer;
1040 *Signature = SIGNATURE_32 ('X', 'A', 'C', '5');
1041 }
1042 }
1043 break;
1044
1045 //
1046 // _AL5 method
1047 //
1048 case (SIGNATURE_32 ('_', 'A', 'L', '5')):
1049 //
1050 // Conditional match. For Name Objects, the Operator will always be the byte
1051 // immediately before the specific name. Therefore, subtract 1 to check the
1052 // Operator.
1053 //
1054 Operation = DsdtPointer - 1;
1055 if (*Operation == AML_NAME_OP) {
1056
1057 //
1058 // Check if we want _AL5 enabled
1059 //
1060 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1061 Signature = (UINT32 *) DsdtPointer;
1062 *Signature = SIGNATURE_32 ('X', 'A', 'L', '5');
1063 }
1064 }
1065 break;
1066
1067 //
1068 // _AC6 method
1069 //
1070 case (SIGNATURE_32 ('_', 'A', 'C', '6')):
1071 //
1072 // Conditional match. _AC6 is < 63 bytes, so the package length is 1 byte.
1073 // Therefore, subtract 2 to check the Operator.
1074 //
1075 Operation = DsdtPointer - 2;
1076 if (*Operation == AML_METHOD_OP) {
1077
1078 //
1079 // Check if we want _AC6 enabled
1080 //
1081 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1082 Signature = (UINT32 *) DsdtPointer;
1083 *Signature = SIGNATURE_32 ('X', 'A', 'C', '6');
1084 }
1085 }
1086 break;
1087
1088 //
1089 // _AL6 method
1090 //
1091 case (SIGNATURE_32 ('_', 'A', 'L', '6')):
1092 //
1093 // Conditional match. For Name Objects, the Operator will always be the byte
1094 // immediately before the specific name. Therefore, subtract 1 to check the
1095 // Operator.
1096 //
1097 Operation = DsdtPointer - 1;
1098 if (*Operation == AML_NAME_OP) {
1099
1100 //
1101 // Check if we want _AL6 enabled
1102 //
1103 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1104 Signature = (UINT32 *) DsdtPointer;
1105 *Signature = SIGNATURE_32 ('X', 'A', 'L', '6');
1106 }
1107 }
1108 break;
1109
1110 //
1111 // _AC7 method
1112 //
1113 case (SIGNATURE_32 ('_', 'A', 'C', '7')):
1114 //
1115 // Conditional match. _AC7 is < 63 bytes, so the package length is 1 byte.
1116 // Therefore, subtract 2 to check the Operator.
1117 //
1118 Operation = DsdtPointer - 2;
1119 if (*Operation == AML_METHOD_OP) {
1120
1121 //
1122 // Check if we want _AC7 enabled
1123 //
1124 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1125 Signature = (UINT32 *) DsdtPointer;
1126 *Signature = SIGNATURE_32 ('X', 'A', 'C', '7');
1127 }
1128 }
1129 break;
1130
1131 //
1132 // _AL7 method
1133 //
1134 case (SIGNATURE_32 ('_', 'A', 'L', '7')):
1135 //
1136 // Conditional match. For Name Objects, the Operator will always be the byte
1137 // immediately before the specific name. Therefore, subtract 1 to check the
1138 // Operator.
1139 //
1140 Operation = DsdtPointer - 1;
1141 if (*Operation == AML_NAME_OP) {
1142
1143 //
1144 // Check if we want _AL7 enabled
1145 //
1146 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1147 Signature = (UINT32 *) DsdtPointer;
1148 *Signature = SIGNATURE_32 ('X', 'A', 'L', '7');
1149 }
1150 }
1151 break;
1152
1153 //
1154 // _AC8 method
1155 //
1156 case (SIGNATURE_32 ('_', 'A', 'C', '8')):
1157 //
1158 // Conditional match. _AC8 is < 63 bytes, so the package length is 1 byte.
1159 // Therefore, subtract 2 to check the Operator.
1160 //
1161 Operation = DsdtPointer - 2;
1162 if (*Operation == AML_METHOD_OP) {
1163
1164 //
1165 // Check if we want _AC8 enabled
1166 //
1167 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1168 Signature = (UINT32 *) DsdtPointer;
1169 *Signature = SIGNATURE_32 ('X', 'A', 'C', '8');
1170 }
1171 }
1172 break;
1173
1174 //
1175 // _AL8 method
1176 //
1177 case (SIGNATURE_32 ('_', 'A', 'L', '8')):
1178 //
1179 // Conditional match. For Name Objects, the Operator will always be the byte
1180 // immediately before the specific name. Therefore, subtract 1 to check the
1181 // Operator.
1182 //
1183 Operation = DsdtPointer - 1;
1184 if (*Operation == AML_NAME_OP) {
1185
1186 //
1187 // Check if we want _AL8 enabled
1188 //
1189 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1190 Signature = (UINT32 *) DsdtPointer;
1191 *Signature = SIGNATURE_32 ('X', 'A', 'L', '8');
1192 }
1193 }
1194 break;
1195
1196 //
1197 // _AC9 method
1198 //
1199 case (SIGNATURE_32 ('_', 'A', 'C', '9')):
1200 //
1201 // Conditional match. _AC9 is < 63 bytes, so the package length is 1 byte.
1202 // Therefore, subtract 2 to check the Operator.
1203 //
1204 Operation = DsdtPointer - 2;
1205 if (*Operation == AML_METHOD_OP) {
1206
1207 //
1208 // Check if we want _AC9 enabled
1209 //
1210 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1211 Signature = (UINT32 *) DsdtPointer;
1212 *Signature = SIGNATURE_32 ('X', 'A', 'C', '9');
1213 }
1214 }
1215 break;
1216
1217 //
1218 // _AL9 method
1219 //
1220 case (SIGNATURE_32 ('_', 'A', 'L', '9')):
1221 //
1222 // Conditional match. For Name Objects, the Operator will always be the byte
1223 // immediately before the specific name. Therefore, subtract 1 to check the
1224 // Operator.
1225 //
1226 Operation = DsdtPointer - 1;
1227 if (*Operation == AML_NAME_OP) {
1228
1229 //
1230 // Check if we want _AL9 enabled
1231 //
1232 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1233 Signature = (UINT32 *) DsdtPointer;
1234 *Signature = SIGNATURE_32 ('X', 'A', 'L', '9');
1235 }
1236 }
1237 break;
1238
1239 //
1240 // _PSL method
1241 //
1242 case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
1243 //
1244 // Conditional match. _PSL is < 256 bytes, so the package length is 1 byte.
1245 // Therefore, subtract 2 to check the Operator.
1246 //
1247 Operation = DsdtPointer - 3;
1248 if (*Operation == AML_METHOD_OP) {
1249
1250 //
1251 // Check if we want _PSL enabled
1252 //
1253 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1254 Signature = (UINT32 *) DsdtPointer;
1255 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'L');
1256 }
1257 }
1258 break;
1259
1260 //
1261 // _PSV method
1262 //
1263 case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
1264 //
1265 // Conditional match. _PSV is < 256 bytes, so the package length is 1 byte.
1266 // Therefore, subtract 2 to check the Operator.
1267 //
1268 Operation = DsdtPointer - 3;
1269 if (*Operation == AML_METHOD_OP) {
1270
1271 //
1272 // Check if we want _PSV enabled
1273 //
1274 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1275 Signature = (UINT32 *) DsdtPointer;
1276 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'V');
1277 }
1278 }
1279 break;
1280
1281 //
1282 // _CRT method
1283 //
1284 case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
1285 //
1286 // Conditional match. _CRT is < 256 bytes, so the package length is 1 byte.
1287 // Subtract 3 to check the Operator for CRB, subract 2 for Harris Beach.
1288 //
1289 Operation = DsdtPointer - 3;
1290 if (*Operation == AML_METHOD_OP) {
1291
1292 //
1293 // Check if we want _CRT enabled
1294 //
1295 if (mSystemConfiguration.DisableCriticalTripPoints == 0) {
1296 Signature = (UINT32 *) DsdtPointer;
1297 *Signature = SIGNATURE_32 ('X', 'C', 'R', 'T');
1298 }
1299 }
1300 break;
1301
1302 //
1303 // _TC1 method
1304 //
1305 case (SIGNATURE_32 ('_', 'T', 'C', '1')):
1306 //
1307 // Conditional match. _TC1 is < 256 bytes, so the package length is 1 byte.
1308 // Therefore, subtract 2 to check the Operator.
1309 //
1310 Operation = DsdtPointer - 2;
1311 if (*Operation == AML_METHOD_OP) {
1312
1313 //
1314 // Check if we want _TC1 enabled
1315 //
1316 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1317 Signature = (UINT32 *) DsdtPointer;
1318 *Signature = SIGNATURE_32 ('X', 'T', 'C', '1');
1319 }
1320 }
1321 break;
1322
1323 //
1324 // _TC2 method
1325 //
1326 case (SIGNATURE_32 ('_', 'T', 'C', '2')):
1327 //
1328 // Conditional match. _TC2 is < 256 bytes, so the package length is 1 byte.
1329 // Therefore, subtract 2 to check the Operator.
1330 //
1331 Operation = DsdtPointer - 2;
1332 if (*Operation == AML_METHOD_OP) {
1333
1334 //
1335 // Check if we want _TC2 enabled
1336 //
1337 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1338 Signature = (UINT32 *) DsdtPointer;
1339 *Signature = SIGNATURE_32 ('X', 'T', 'C', '2');
1340 }
1341 }
1342 break;
1343
1344 //
1345 // _TSP method
1346 //
1347 case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
1348 //
1349 // Conditional match. _TSP is < 256 bytes, so the package length is 1 byte.
1350 // Therefore, subtract 2 to check the Operator.
1351 //
1352 Operation = DsdtPointer - 2;
1353 if (*Operation == AML_METHOD_OP) {
1354
1355 //
1356 // Check if we want _TSP enabled
1357 //
1358 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1359 Signature = (UINT32 *) DsdtPointer;
1360 *Signature = SIGNATURE_32 ('X', 'T', 'S', 'P');
1361 }
1362 }
1363 break;
1364
1365 //
1366 // Update SS3 Name with Setup value
1367 //
1368 case (SIGNATURE_32 ('S', 'S', '3', '_')):
1369 Operation = DsdtPointer - 1;
1370 if (*Operation == AML_NAME_OP) {
1371 Value = (UINT8 *) DsdtPointer + 4;
1372 *Value = (UINT8)mSystemConfiguration.AcpiSleepState;
1373 }
1374 break;
1375 //
1376 // Update SS4 Name with Setup value
1377 //
1378 case (SIGNATURE_32 ('S', 'S', '4', '_')):
1379 Operation = DsdtPointer - 1;
1380 if (*Operation == AML_NAME_OP) {
1381 Value = (UINT8 *) DsdtPointer + 4;
1382 *Value = mSystemConfiguration.AcpiHibernate;
1383 }
1384 break;
1385 //
1386 // _EJ0 method
1387 //
1388 case (SIGNATURE_32 ('_', 'E', 'J', '0')):
1389 if (mSystemConfiguration.LowPowerS0Idle) {
1390 //
1391 // Remove _EJ0 for SOC
1392 //
1393 if (*(DsdtPointer-3) == AML_METHOD_OP) {
1394 Signature = (UINT32 *) DsdtPointer;
1395 *Signature = SIGNATURE_32 ('X', 'E', 'J', '0');
1396 EnterDock = TRUE;
1397 }
1398 }
1399 break;
1400 //
1401 // _STA method for Device (\_SB.PCI0.DOCK)
1402 //
1403 case (SIGNATURE_32 ('_', 'S', 'T', 'A')):
1404 if (mSystemConfiguration.LowPowerS0Idle) {
1405 //
1406 // Remove _STA in (\_SB.PCI0.DOCK) for SOC
1407 //
1408 if ((*(DsdtPointer-3) == AML_METHOD_OP) && (EnterDock)) {
1409 Signature = (UINT32 *) DsdtPointer;
1410 *Signature = SIGNATURE_32 ('X', 'S', 'T', 'A');
1411 EnterDock = FALSE;
1412 }
1413 }
1414 break;
1415 //
1416 // _UPC method for Device (\_SB.PCI0.XHC.RHUB)
1417 //
1418 case (SIGNATURE_32('H', 'S', '1', '3')):
1419 for (TmpDsdtPointer = DsdtPointer;
1420 TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength;
1421 TmpDsdtPointer++){
1422 Signature = (UINT32 *) TmpDsdtPointer;
1423 switch (*Signature) {
1424 case(SIGNATURE_32('U', 'P', 'C', 'P')):
1425 Value = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
1426 break;
1427 default:
1428 //
1429 // Do nothing.
1430 //
1431 break;
1432 }
1433 }
1434 break;
1435
1436
1437 //
1438 // _DCK method
1439 //
1440 case (SIGNATURE_32 ('_', 'D', 'C', 'K')):
1441 if (mSystemConfiguration.LowPowerS0Idle) {
1442 //
1443 // Remove _DCK for SOC
1444 //
1445 if (*(DsdtPointer-3) == AML_METHOD_OP) {
1446 Signature = (UINT32 *) DsdtPointer;
1447 *Signature = SIGNATURE_32 ('X', 'D', 'C', 'K');
1448 }
1449 }
1450 break;
1451
1452 //
1453 // mask _DEP from CPU's scope if CS disabled.
1454 //
1455 case (SIGNATURE_32 ('P', 'R', '0', '0')):
1456 case (SIGNATURE_32 ('P', 'R', '0', '1')):
1457 case (SIGNATURE_32 ('P', 'R', '0', '2')):
1458 case (SIGNATURE_32 ('P', 'R', '0', '3')):
1459 case (SIGNATURE_32 ('P', 'R', '0', '4')):
1460 case (SIGNATURE_32 ('P', 'R', '0', '5')):
1461 case (SIGNATURE_32 ('P', 'R', '0', '6')):
1462 case (SIGNATURE_32 ('P', 'R', '0', '7')):
1463 case (SIGNATURE_32 ('P', 'R', '0', '8')):
1464 case (SIGNATURE_32 ('P', 'R', '0', '9')):
1465 case (SIGNATURE_32 ('P', 'R', '1', '0')):
1466 case (SIGNATURE_32 ('P', 'R', '1', '1')):
1467 case (SIGNATURE_32 ('P', 'R', '1', '2')):
1468 case (SIGNATURE_32 ('P', 'R', '1', '3')):
1469 case (SIGNATURE_32 ('P', 'R', '1', '4')):
1470 case (SIGNATURE_32 ('P', 'R', '1', '5')):
1471 if (mSystemConfiguration.LowPowerS0Idle == 0) {
1472 for (TmpDsdtPointer = DsdtPointer; TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength; TmpDsdtPointer++){
1473 Signature = (UINT32 *) TmpDsdtPointer;
1474 switch (*Signature) {
1475 case(SIGNATURE_32('_', 'D', 'E', 'P')):
1476 *(UINT8 *) TmpDsdtPointer = 'X';
1477 break;
1478 default:
1479 //
1480 // Do nothing.
1481 //
1482 break;
1483 }
1484 }
1485 }
1486 break;
1487
1488 //
1489 // _EDL name
1490 //
1491 case (SIGNATURE_32 ('_', 'E', 'D', 'L')):
1492 if (mSystemConfiguration.LowPowerS0Idle) {
1493 //
1494 // Remove _EDL for SOC
1495 //
1496 if (*(DsdtPointer-1) == AML_NAME_OP) {
1497 Signature = (UINT32 *) DsdtPointer;
1498 *Signature = SIGNATURE_32 ('X', 'E', 'D', 'L');
1499 }
1500 }
1501 break;
1502
1503 default:
1504 //
1505 // Do nothing.
1506 //
1507 break;
1508 }
1509 }
1510 }
1511 break;
1512
1513 case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
1514 //
1515 // If HPET is disabled in setup, don't publish the table.
1516 //
1517 if (mPchSetup.Hpet == FALSE) {
1518 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1519 } else {
1520 //
1521 // Get HPET base address
1522 //
1523 PchHpetBaseGet (&HpetBaseAdress);
1524 //
1525 // Adjust HPET Table to correct the Base Address
1526 //
1527 ((EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER*) Table)->BaseAddressLower32Bit.Address = HpetBaseAdress;
1528 }
1529 break;
1530
1531 case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
1532 //
1533 // Update MCFG base and end bus number
1534 //
1535 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].BaseAddress
1536 = PcdGet64 (PcdPciExpressBaseAddress);
1537
1538 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].EndBusNumber
1539 = (UINT8)(PcdGet32 (PcdPciExpressRegionLength) / 0x100000) - 1;
1540 if (mSaTcssHob->TcssData.PcieMultipleSegmentEnabled) {
1541 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[1].BaseAddress
1542 = PcdGet64 (PcdPciExpressBaseAddress) + SIZE_256MB;
1543 } else {
1544 ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->Header.Length -= sizeof (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
1545 }
1546 break;
1547
1548 case EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:
1549 //
1550 // If EC is not present, don't publish the table.
1551 //
1552 if (mPlatformNvsAreaProtocol.Area->EcAvailable == PLATFORM_NVS_DEVICE_DISABLE) {
1553 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1554 } else {
1555 //
1556 // Update GPE Number
1557 //
1558 ((EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE *) Table)->GpeBit = (UINT8) GetEcGpeNumber ();
1559 }
1560 break;
1561
1562 /* @todo Need to uncomment once MSFT fully implements uPEP
1563 case SIGNATURE_32 ('L', 'P', 'I', 'T'):
1564 //
1565 // If L0s is disabled in setup, don't publish the table.
1566 //
1567 if (mSystemConfiguration.LowPowerS0Idle == 0) {
1568 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1569 }
1570 break;
1571 */
1572 case EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
1573 {
1574 UINT8 *TablePointer;
1575 UINT32 *Signature;
1576 UINT8 *Operation;
1577
1578 //
1579 // Do not load the xHCI table. It is handled by separate function.
1580 //
1581 if (CompareMem (&TableHeader->OemTableId, "xh_", 3) == 0) {
1582 DEBUG((DEBUG_INFO,"TableHeader->OemTableId = %x\n ", TableHeader->OemTableId));
1583 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1584 }
1585
1586 //
1587 // Load SSDT tables for the platforms based on boardID; default to RVP tables.
1588 // Load Ther_Sds for Skylake SDS, PantherMtn, or StarBrook.
1589 // Load Ther_Rvp for all others.
1590 //
1591 if (CompareMem (&TableHeader->OemTableId, "Ther_Sds", 8) == 0) {
1592 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1593 }
1594
1595 if (CompareMem (&TableHeader->OemTableId, "Ther_Rvp", 8) == 0) {
1596 CurrPtr = (UINT8 *) Table;
1597 for (TablePointer = CurrPtr;TablePointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);TablePointer++)
1598 {
1599 Signature = (UINT32 *) TablePointer;
1600 switch (*Signature) {
1601 //
1602 // _AC0 method
1603 //
1604 case (SIGNATURE_32 ('_', 'A', 'C', '0')):
1605 //
1606 // Conditional match. _AC0 is >63 and <4095 bytes, so the package length is 2 bytes.
1607 // Therefore, subtract 3 to check the Operator.
1608 //
1609 Operation = TablePointer - 3;
1610 if (*Operation == AML_METHOD_OP) {
1611 //
1612 // Check if we want _AC0 enabled
1613 //
1614 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1615 Signature = (UINT32 *) TablePointer;
1616 *Signature = SIGNATURE_32 ('X', 'A', 'C', '0');
1617 }
1618 }
1619 break;
1620 //
1621 // _AL0 method
1622 //
1623 case (SIGNATURE_32 ('_', 'A', 'L', '0')):
1624 //
1625 // Conditional match. For Name Objects, the Operator will always be the byte
1626 // immediately before the specific name. Therefore, subtract 1 to check the
1627 // Operator.
1628 //
1629 Operation = TablePointer - 1;
1630 if (*Operation == AML_NAME_OP) {
1631 //
1632 // Check if we want _AL0 enabled
1633 //
1634 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1635 Signature = (UINT32 *) TablePointer;
1636 *Signature = SIGNATURE_32 ('X', 'A', 'L', '0');
1637 }
1638 }
1639 break;
1640 //
1641 // _AC1 method
1642 //
1643 case (SIGNATURE_32 ('_', 'A', 'C', '1')):
1644 //
1645 // Conditional match. _AC1 is < 63 bytes, so the package length is 1 byte.
1646 // Therefore, subtract 2 to check the Operator.
1647 //
1648 Operation = TablePointer - 2;
1649 if (*Operation == AML_METHOD_OP) {
1650 //
1651 // Check if we want _AC1 enabled
1652 //
1653 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1654 Signature = (UINT32 *) TablePointer;
1655 *Signature = SIGNATURE_32 ('X', 'A', 'C', '1');
1656 }
1657 }
1658 break;
1659 //
1660 // _AL1 method
1661 //
1662 case (SIGNATURE_32 ('_', 'A', 'L', '1')):
1663 //
1664 // Conditional match. For Name Objects, the Operator will always be the byte
1665 // immediately before the specific name. Therefore, subtract 1 to check the
1666 // Operator.
1667 //
1668 Operation = TablePointer - 1;
1669 if (*Operation == AML_NAME_OP) {
1670 //
1671 // Check if we want _AL1 enabled
1672 //
1673 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1674 Signature = (UINT32 *) TablePointer;
1675 *Signature = SIGNATURE_32 ('X', 'A', 'L', '1');
1676 }
1677 }
1678 break;
1679 //
1680 // _AC2 method
1681 //
1682 case (SIGNATURE_32 ('_', 'A', 'C', '2')):
1683 //
1684 // Conditional match. _AC2 is < 63 bytes, so the package length is 1 byte.
1685 // Therefore, subtract 2 to check the Operator.
1686 //
1687 Operation = TablePointer - 2;
1688 if (*Operation == AML_METHOD_OP) {
1689 //
1690 // Check if we want _AC2 enabled
1691 //
1692 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1693 Signature = (UINT32 *) TablePointer;
1694 *Signature = SIGNATURE_32 ('X', 'A', 'C', '2');
1695 }
1696 }
1697 break;
1698 //
1699 // _AL2 method
1700 //
1701 case (SIGNATURE_32 ('_', 'A', 'L', '2')):
1702 //
1703 // Conditional match. For Name Objects, the Operator will always be the byte
1704 // immediately before the specific name. Therefore, subtract 1 to check the
1705 // Operator.
1706 //
1707 Operation = TablePointer - 1;
1708 if (*Operation == AML_NAME_OP) {
1709 //
1710 // Check if we want _AL2 enabled
1711 //
1712 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1713 Signature = (UINT32 *) TablePointer;
1714 *Signature = SIGNATURE_32 ('X', 'A', 'L', '2');
1715 }
1716 }
1717 break;
1718 //
1719 // _AC3 method
1720 //
1721 case (SIGNATURE_32 ('_', 'A', 'C', '3')):
1722 //
1723 // Conditional match. _AC3 is < 63 bytes, so the package length is 1 byte.
1724 // Therefore, subtract 2 to check the Operator.
1725 //
1726 Operation = TablePointer - 2;
1727 if (*Operation == AML_METHOD_OP) {
1728 //
1729 // Check if we want _AC3 enabled
1730 //
1731 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1732 Signature = (UINT32 *) TablePointer;
1733 *Signature = SIGNATURE_32 ('X', 'A', 'C', '3');
1734 }
1735 }
1736 break;
1737 //
1738 // _AL3 method
1739 //
1740 case (SIGNATURE_32 ('_', 'A', 'L', '3')):
1741 //
1742 // Conditional match. For Name Objects, the Operator will always be the byte
1743 // immediately before the specific name. Therefore, subtract 1 to check the
1744 // Operator.
1745 //
1746 Operation = TablePointer - 1;
1747 if (*Operation == AML_NAME_OP) {
1748 //
1749 // Check if we want _AL3 enabled
1750 //
1751 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1752 Signature = (UINT32 *) TablePointer;
1753 *Signature = SIGNATURE_32 ('X', 'A', 'L', '3');
1754 }
1755 }
1756 break;
1757 //
1758 // _AC4 method
1759 //
1760 case (SIGNATURE_32 ('_', 'A', 'C', '4')):
1761 //
1762 // Conditional match. _AC4 is < 63 bytes, so the package length is 1 byte.
1763 // Therefore, subtract 2 to check the Operator.
1764 //
1765 Operation = TablePointer - 2;
1766 if (*Operation == AML_METHOD_OP) {
1767 //
1768 // Check if we want _AC4 enabled
1769 //
1770 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1771 Signature = (UINT32 *) TablePointer;
1772 *Signature = SIGNATURE_32 ('X', 'A', 'C', '4');
1773 }
1774 }
1775 break;
1776 //
1777 // _AL4 method
1778 //
1779 case (SIGNATURE_32 ('_', 'A', 'L', '4')):
1780 //
1781 // Conditional match. For Name Objects, the Operator will always be the byte
1782 // immediately before the specific name. Therefore, subtract 1 to check the
1783 // Operator.
1784 //
1785 Operation = TablePointer - 1;
1786 if (*Operation == AML_NAME_OP) {
1787 //
1788 // Check if we want _AL4 enabled
1789 //
1790 if (mSystemConfiguration.DisableActiveTripPoints == 0) {
1791 Signature = (UINT32 *) TablePointer;
1792 *Signature = SIGNATURE_32 ('X', 'A', 'L', '4');
1793 }
1794 }
1795 break;
1796 // _PSL method
1797 //
1798 case (SIGNATURE_32 ('_', 'P', 'S', 'L')):
1799 //
1800 // Conditional match. _PSL is < 256 bytes, so the package length is 1 byte.
1801 // Therefore, subtract 2 to check the Operator.
1802 //
1803 Operation = TablePointer - 3;
1804 if (*Operation == AML_METHOD_OP) {
1805 //
1806 // Check if we want _PSL enabled
1807 //
1808 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1809 Signature = (UINT32 *) TablePointer;
1810 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'L');
1811 }
1812 }
1813 break;
1814 //
1815 // _PSV method
1816 //
1817 case (SIGNATURE_32 ('_', 'P', 'S', 'V')):
1818 //
1819 // Conditional match. _PSV is < 256 bytes, so the package length is 1 byte.
1820 // Therefore, subtract 2 to check the Operator.
1821 //
1822 Operation = TablePointer - 3;
1823 if (*Operation == AML_METHOD_OP) {
1824 //
1825 // Check if we want _PSV enabled
1826 //
1827 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1828 Signature = (UINT32 *) TablePointer;
1829 *Signature = SIGNATURE_32 ('X', 'P', 'S', 'V');
1830 }
1831 }
1832 break;
1833 //
1834 // _CRT method
1835 //
1836 case (SIGNATURE_32 ('_', 'C', 'R', 'T')):
1837 //
1838 // Conditional match. _CRT is < 256 bytes, so the package length is 1 byte.
1839 // Subtract 3 to check the Operator for CRB, subract 2 for Harris Beach.
1840 //
1841 Operation = TablePointer - 3;
1842 if (*Operation == AML_METHOD_OP) {
1843 //
1844 // Check if we want _CRT enabled
1845 //
1846 if (mSystemConfiguration.DisableCriticalTripPoints == 0) {
1847 Signature = (UINT32 *) TablePointer;
1848 *Signature = SIGNATURE_32 ('X', 'C', 'R', 'T');
1849 }
1850 }
1851 break;
1852 //
1853 // _TC1 method
1854 //
1855 case (SIGNATURE_32 ('_', 'T', 'C', '1')):
1856 //
1857 // Conditional match. _TC1 is < 256 bytes, so the package length is 1 byte.
1858 // Therefore, subtract 2 to check the Operator.
1859 //
1860 Operation = TablePointer - 2;
1861 if (*Operation == AML_METHOD_OP) {
1862 //
1863 // Check if we want _TC1 enabled
1864 //
1865 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1866 Signature = (UINT32 *) TablePointer;
1867 *Signature = SIGNATURE_32 ('X', 'T', 'C', '1');
1868 }
1869 }
1870 break;
1871 //
1872 // _TC2 method
1873 //
1874 case (SIGNATURE_32 ('_', 'T', 'C', '2')):
1875 //
1876 // Conditional match. _TC2 is < 256 bytes, so the package length is 1 byte.
1877 // Therefore, subtract 2 to check the Operator.
1878 //
1879 Operation = TablePointer - 2;
1880 if (*Operation == AML_METHOD_OP) {
1881 //
1882 // Check if we want _TC2 enabled
1883 //
1884 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1885 Signature = (UINT32 *) TablePointer;
1886 *Signature = SIGNATURE_32 ('X', 'T', 'C', '2');
1887 }
1888 }
1889 break;
1890 //
1891 // _TSP method
1892 //
1893 case (SIGNATURE_32 ('_', 'T', 'S', 'P')):
1894 //
1895 // Conditional match. _TSP is < 256 bytes, so the package length is 1 byte.
1896 // Therefore, subtract 2 to check the Operator.
1897 //
1898 Operation = TablePointer - 2;
1899 if (*Operation == AML_METHOD_OP) {
1900 //
1901 // Check if we want _TSP enabled
1902 //
1903 if (mSystemConfiguration.DisablePassiveTripPoints == 0) {
1904 Signature = (UINT32 *) TablePointer;
1905 *Signature = SIGNATURE_32 ('X', 'T', 'S', 'P');
1906 }
1907 }
1908 break;
1909 }
1910 }
1911 }
1912
1913 //
1914 // Load RTD3 SSDT table for CNL U RVP and ICL U RVP
1915 //
1916 if ((CompareMem (&TableHeader->OemTableId, "SDS_Rtd3", 8) == 0) ||
1917 (CompareMem (&TableHeader->OemTableId, "CnlU_Rvp", 8) == 0) ||
1918 (CompareMem (&TableHeader->OemTableId, "CnlY_Rvp", 8) == 0) ||
1919 (CompareMem (&TableHeader->OemTableId, "CflH_Rvp", 8) == 0) ||
1920 (CompareMem (&TableHeader->OemTableId, "CflS_Rvp", 8) == 0) ||
1921 (CompareMem (&TableHeader->OemTableId, "CnlH_Rvp", 8) == 0) ||
1922 (CompareMem (&TableHeader->OemTableId, "IclU_Rvp", 8) == 0)){
1923 //
1924 // set default = none
1925 //
1926 *Version = EFI_ACPI_TABLE_VERSION_NONE;
1927
1928 //
1929 // check RTD3 enabled in setup
1930 //
1931 if (mSystemConfiguration.Rtd3Support == 1) {
1932 //
1933 // match table ID and BoardId
1934 //
1935
1936 // load RTD3 table for CNL U RVP
1937 if (CompareMem (&TableHeader->OemTableId, "CnlU_Rvp", 8) == 0) {
1938 if (PcdGetBool (PcdCnlURvpRtd3TableEnable)) {
1939 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
1940 }
1941 }
1942 // load RTD3 table for CNL Y RVP
1943 if (CompareMem (&TableHeader->OemTableId, "CnlY_Rvp", 8) == 0) {
1944 if (PcdGetBool (PcdCnlYRvpRtd3TableEnable)) {
1945 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
1946 }
1947 }
1948
1949 // load RTD3 table for CFL H RVP
1950 if (CompareMem (&TableHeader->OemTableId, "CflH_Rvp", 8) == 0) {
1951 if (PcdGetBool (PcdCflHRvpRtd3TableEnable)) {
1952 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
1953 }
1954 }
1955
1956 // load RTD3 table for CNL H RVP
1957 if (CompareMem (&TableHeader->OemTableId, "CnlH_Rvp", 8) == 0) {
1958 if (PcdGetBool (PcdCnlHRvpRtd3TableEnable)) {
1959 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
1960 }
1961 }
1962
1963 // load RTD3 table for CFL S RVP
1964 if (CompareMem (&TableHeader->OemTableId, "CflS_Rvp", 8) == 0) {
1965 if (PcdGetBool (PcdCflSRvpRtd3TableEnable)) {
1966 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
1967 }
1968 }
1969
1970 // load RTD3 table for ICL U RVP
1971 if (CompareMem (&TableHeader->OemTableId, "IclU_Rvp", 8) == 0) {
1972 if (PcdGetBool (PcdIclURvpRtd3TableEnable)) {
1973 *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
1974 }
1975 }
1976 } // Rtd3Support
1977 } // Load RTD3 SSDT table
1978 }
1979 break;
1980
1981 default:
1982 break;
1983 }
1984 return EFI_SUCCESS;
1985 }
1986
1987 /**
1988 This function calculates RCR based on PCI Device ID and Vendor ID from the devices
1989 available on the platform.
1990 It also includes other instances of BIOS change to calculate CRC and provides as
1991 HWSignature filed in FADT table.
1992 **/
1993 VOID
1994 IsHardwareChange (
1995 VOID
1996 )
1997 {
1998 EFI_STATUS Status;
1999 UINTN Index;
2000 UINTN HandleCount;
2001 EFI_HANDLE *HandleBuffer;
2002 EFI_PCI_IO_PROTOCOL *PciIo;
2003 UINT32 CRC;
2004 UINT32 *HWChange;
2005 UINTN HWChangeSize;
2006 UINT32 PciId;
2007 UINTN Handle;
2008 EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
2009 EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
2010
2011 HandleCount = 0;
2012 HandleBuffer = NULL;
2013
2014 Status = gBS->LocateHandleBuffer (
2015 ByProtocol,
2016 &gEfiPciIoProtocolGuid,
2017 NULL,
2018 &HandleCount,
2019 &HandleBuffer
2020 );
2021 if (EFI_ERROR (Status)) {
2022 return; // PciIO protocol not installed yet!
2023 }
2024
2025 //
2026 // Allocate memory for HWChange and add additional entrie for
2027 // pFADT->XDsdt
2028 //
2029 HWChangeSize = HandleCount + 1;
2030 HWChange = AllocateZeroPool( sizeof(UINT32) * HWChangeSize );
2031 ASSERT( HWChange != NULL );
2032
2033 if (HWChange == NULL) return;
2034
2035 //
2036 // add HWChange inputs: PCI devices
2037 //
2038 for (Index = 0; HandleCount > 0; HandleCount--) {
2039 PciId = 0;
2040 Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **) &PciIo);
2041 if (!EFI_ERROR (Status)) {
2042 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0, 1, &PciId);
2043 if (EFI_ERROR (Status)) {
2044 continue;
2045 }
2046 HWChange[Index++] = PciId;
2047 }
2048 }
2049
2050 //
2051 // Locate FACP Table
2052 //
2053 Handle = 0;
2054 Status = LocateAcpiTableBySignature (
2055 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
2056 (EFI_ACPI_DESCRIPTION_HEADER **) &pFADT,
2057 &Handle
2058 );
2059 if (EFI_ERROR (Status) || (pFADT == NULL)) {
2060 return; //Table not found or out of memory resource for pFADT table
2061 }
2062
2063 //
2064 // add HWChange inputs: others
2065 //
2066 HWChange[Index++] = (UINT32)pFADT->XDsdt;
2067
2068 //
2069 // Calculate CRC value with HWChange data.
2070 //
2071 Status = gBS->CalculateCrc32(HWChange, HWChangeSize, &CRC);
2072 DEBUG((DEBUG_INFO,"CRC = %x and Status = %r\n", CRC, Status));
2073
2074 //
2075 // Set HardwareSignature value based on CRC value.
2076 //
2077 FacsPtr = (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT->FirmwareCtrl;
2078 FacsPtr->HardwareSignature = CRC;
2079 FreePool( HWChange );
2080 }
2081
2082 EFI_STATUS
2083 PublishAcpiTablesFromFv (
2084 IN EFI_GUID gEfiAcpiMultiTableStorageGuid
2085 )
2086 {
2087 EFI_STATUS Status;
2088 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
2089 EFI_ACPI_COMMON_HEADER *CurrentTable;
2090 UINT32 FvStatus;
2091 UINTN Size;
2092 EFI_ACPI_TABLE_VERSION Version;
2093 UINTN TableHandle;
2094 INTN Instance;
2095 EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
2096
2097 Instance = 0;
2098 TableHandle = 0;
2099 CurrentTable = NULL;
2100 FwVol = NULL;
2101
2102 //
2103 // Find the AcpiSupport protocol
2104 //
2105 Status = LocateSupportProtocol (
2106 &gEfiAcpiTableProtocolGuid,
2107 gEfiAcpiMultiTableStorageGuid,
2108 (VOID **) &AcpiTable,
2109 FALSE
2110 );
2111 ASSERT_EFI_ERROR (Status);
2112
2113 //
2114 // Locate the firmware volume protocol
2115 //
2116 Status = LocateSupportProtocol (
2117 &gEfiFirmwareVolume2ProtocolGuid,
2118 gEfiAcpiMultiTableStorageGuid,
2119 (VOID **) &FwVol,
2120 TRUE
2121 );
2122
2123 /* TODO: Hang at native mode. Need to find the cause
2124 * when the related drivers are finished for native support. */
2125 //ASSERT_EFI_ERROR (Status);
2126
2127 //
2128 // Read tables from the storage file.
2129 //
2130 while (Status == EFI_SUCCESS) {
2131 Status = FwVol->ReadSection (
2132 FwVol,
2133 &gEfiAcpiMultiTableStorageGuid,
2134 EFI_SECTION_RAW,
2135 Instance,
2136 (VOID **) &CurrentTable,
2137 &Size,
2138 &FvStatus
2139 );
2140
2141 if (!EFI_ERROR (Status)) {
2142
2143 //
2144 // Perform any table specific updates.
2145 //
2146 PlatformUpdateTables (CurrentTable, &Version);
2147
2148 //
2149 // Add the table
2150 //
2151 TableHandle = 0;
2152
2153 if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
2154 Status = AcpiTable->InstallAcpiTable (
2155 AcpiTable,
2156 CurrentTable,
2157 CurrentTable->Length,
2158 &TableHandle
2159 );
2160 }
2161
2162 ASSERT_EFI_ERROR (Status);
2163
2164 //
2165 // Increment the instance
2166 //
2167 Instance++;
2168 CurrentTable = NULL;
2169 }
2170 }
2171
2172 //
2173 // Finished
2174 //
2175 return EFI_SUCCESS;
2176 }
2177
2178
2179 /**
2180 Allocate MemoryType below 4G memory address.
2181
2182 @param[in] Size - Size of memory to allocate.
2183 @param[in] Buffer - Allocated address for output.
2184
2185 @retval EFI_SUCCESS - Memory successfully allocated.
2186 @retval Other - Other errors occur.
2187
2188 **/
2189 EFI_STATUS
2190 AllocateMemoryBelow4G (
2191 IN EFI_MEMORY_TYPE MemoryType,
2192 IN UINTN Size,
2193 OUT VOID **Buffer
2194 )
2195 {
2196 UINTN Pages;
2197 EFI_PHYSICAL_ADDRESS Address;
2198 EFI_STATUS Status;
2199
2200 Pages = EFI_SIZE_TO_PAGES (Size);
2201 Address = 0xffffffff;
2202
2203 Status = (gBS->AllocatePages) (
2204 AllocateMaxAddress,
2205 MemoryType,
2206 Pages,
2207 &Address
2208 );
2209
2210 *Buffer = (VOID *) (UINTN) Address;
2211
2212 return Status;
2213 }
2214
2215 EFI_STATUS
2216 ReserveS3Memory (
2217 VOID
2218 )
2219 {
2220 VOID *AcpiMemoryBase;
2221 UINT32 AcpiMemorySize;
2222 EFI_PEI_HOB_POINTERS Hob;
2223 UINT64 MemoryLength;
2224 S3_MEMORY_VARIABLE S3MemVariable;
2225 VOID *VariableData;
2226 UINTN VarSize;
2227 EFI_STATUS Status;
2228 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock;
2229
2230 DEBUG ((DEBUG_INFO, "ReserveS3Memory\n"));
2231
2232 //
2233 // Allocate ACPI reserved memory under 4G
2234 //
2235 Status = AllocateMemoryBelow4G (EfiReservedMemoryType, PcdGet32 (PcdS3AcpiReservedMemorySize), &AcpiMemoryBase);
2236 ASSERT (AcpiMemoryBase != 0);
2237 AcpiMemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);
2238
2239 //
2240 // Calculate the system memory length by memory hobs
2241 //
2242 MemoryLength = 0x100000;
2243 Hob.Raw = GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
2244 ASSERT (Hob.Raw != NULL);
2245 while ((Hob.Raw != NULL) && (!END_OF_HOB_LIST (Hob))) {
2246 if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
2247 //
2248 // Skip the memory region below 1MB
2249 //
2250 if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
2251 MemoryLength += Hob.ResourceDescriptor->ResourceLength;
2252 }
2253 }
2254 Hob.Raw = GET_NEXT_HOB (Hob);
2255 Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw);
2256 }
2257
2258 S3MemVariable.AcpiReservedMemoryBase = (EFI_PHYSICAL_ADDRESS)(UINTN) AcpiMemoryBase;
2259 S3MemVariable.AcpiReservedMemorySize = AcpiMemorySize;
2260 S3MemVariable.SystemMemoryLength = MemoryLength;
2261
2262 DEBUG((DEBUG_INFO, "ReserveS3Memory: AcpiMemoryBase is 0x%8x\n", S3MemVariable.AcpiReservedMemoryBase));
2263 DEBUG((DEBUG_INFO, "ReserveS3Memory: AcpiMemorySize is 0x%8x\n", S3MemVariable.AcpiReservedMemorySize));
2264 DEBUG((DEBUG_INFO, "ReserveS3Memory: SystemMemoryLength is 0x%8x\n", S3MemVariable.SystemMemoryLength));
2265
2266 VarSize = sizeof(S3_MEMORY_VARIABLE);
2267 Status = gBS->AllocatePool(
2268 EfiBootServicesData,
2269 VarSize,
2270 (VOID **) &VariableData
2271 );
2272 Status = gRT->GetVariable (
2273 S3_MEMORY_VARIABLE_NAME,
2274 &gS3MemoryVariableGuid,
2275 NULL,
2276 &VarSize,
2277 VariableData
2278 );
2279 if (EFI_ERROR (Status) || (0 != CompareMem (&S3MemVariable, VariableData, VarSize))) {
2280 DEBUG((DEBUG_INFO, "Update S3MemVariable.\n"));
2281 Status = gRT->SetVariable (
2282 S3_MEMORY_VARIABLE_NAME,
2283 &gS3MemoryVariableGuid,
2284 EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
2285 VarSize,
2286 &S3MemVariable
2287 );
2288 }
2289 gBS->FreePool(VariableData);
2290
2291 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
2292 if (!EFI_ERROR (Status)) {
2293 Status = VariableLock->RequestToLock (VariableLock, S3_MEMORY_VARIABLE_NAME, &gS3MemoryVariableGuid);
2294 ASSERT_EFI_ERROR (Status);
2295 }
2296
2297 return EFI_SUCCESS;
2298 }
2299
2300 VOID
2301 EFIAPI
2302 AcpiEndOfDxeEvent (
2303 EFI_EVENT Event,
2304 VOID *ParentImageHandle
2305 )
2306 {
2307
2308 if (Event != NULL) {
2309 gBS->CloseEvent(Event);
2310 }
2311
2312
2313 //
2314 // Calculate Hardware Signature value based on current platform configurations
2315 //
2316 IsHardwareChange();
2317
2318 //
2319 // Reserve memory for S3 resume
2320 //
2321 ReserveS3Memory ();
2322 }
2323
2324 /**
2325 Convert string containing GUID in the canonical form:
2326 "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp"
2327 where aa - pp are unicode hexadecimal digits
2328 to the buffer format to be used in ACPI, byte ordering:
2329 [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7]
2330 [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16]
2331
2332 @param[in] GuidString - GUID String null terminated (aligned on a 16-bit boundary)
2333 @param[out] AcpiGuidPart1 - First half of buffer (bytes 0 - 7)
2334 @param[out] AcpiGuidPart2 - Second half of buffer (bytes 8 - 16)
2335
2336 @retval EFI_SUCCESS - String converted successfully.
2337 @retval EFI_UNSUPPORTED - Wrong input string format.
2338
2339 **/
2340 EFI_STATUS
2341 GuidStringToAcpiBuffer (
2342 IN CHAR16 *GuidString,
2343 OUT UINT64 *AcpiGuidPart1,
2344 OUT UINT64 *AcpiGuidPart2
2345 )
2346 {
2347 UINT32 GuidTempPart32 = 0;
2348 UINT16 GuidTempPart16 = 0;
2349 UINT8 GuidPartIndex;
2350
2351 DEBUG((DEBUG_INFO,"GuidStringToAcpiBuffer() - GUID = %s\n", GuidString));
2352
2353 for (GuidPartIndex = 0; GuidPartIndex < 4; GuidPartIndex++) {
2354 switch (GuidPartIndex){
2355 case 0:
2356 GuidTempPart32 = SwapBytes32((UINT32)StrHexToUint64(GuidString));
2357 *AcpiGuidPart1 = ((UINT64)GuidTempPart32 << 0x20);
2358 break;
2359 case 1:
2360 GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
2361 *AcpiGuidPart1 += ((UINT64)GuidTempPart16 << 0x10);
2362 break;
2363 case 2:
2364 GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
2365 *AcpiGuidPart1 += ((UINT64)GuidTempPart16);
2366 break;
2367 case 3:
2368 GuidTempPart16 = (UINT16)StrHexToUint64(GuidString);
2369 break;
2370 default:
2371 return EFI_UNSUPPORTED;
2372 }
2373
2374 while ((*GuidString != L'-') && (*GuidString != L'\0')) {
2375 GuidString++;
2376 }
2377
2378 if (*GuidString == L'-') {
2379 GuidString++;
2380 } else {
2381 return EFI_UNSUPPORTED;
2382 }
2383 }
2384
2385 *AcpiGuidPart2 = ((UINT64)GuidTempPart16 << 0x30) + StrHexToUint64(GuidString);
2386
2387 // Switch endianess because it will be swapped again in ACPI Buffer object
2388 *AcpiGuidPart1 = SwapBytes64(*AcpiGuidPart1);
2389 *AcpiGuidPart2 = SwapBytes64(*AcpiGuidPart2);
2390
2391 return EFI_SUCCESS;
2392 }
2393
2394 /**
2395 Save Acpi Setup relatived variables.
2396 **/
2397 EFI_STATUS
2398 SetAcpiSetupVariables (
2399 VOID
2400 )
2401 {
2402 EFI_STATUS Status;
2403 UINTN Handle;
2404 SETUP_DATA SetupData;
2405 UINTN VariableSize;
2406 UINT32 VariableAttributes;
2407 EFI_ACPI_DESCRIPTION_HEADER *Table;
2408
2409 VariableSize = sizeof (SETUP_DATA);
2410 Status = gRT->GetVariable (
2411 L"Setup",
2412 &gSetupVariableGuid,
2413 &VariableAttributes,
2414 &VariableSize,
2415 &SetupData
2416 );
2417 if (EFI_ERROR (Status)) {
2418 return Status;
2419 }
2420
2421 ///
2422 /// Locate table with matching ID
2423 ///
2424 Handle = 0;
2425 Table = NULL;
2426 Status = LocateAcpiTableBySignature (
2427 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
2428 (EFI_ACPI_DESCRIPTION_HEADER **) &Table,
2429 &Handle
2430 );
2431 if (EFI_ERROR (Status) || (Table == NULL)) {
2432 return Status;
2433 }
2434
2435 SetupData.AcpiTableRevision = Table->Revision;
2436 Status = gRT->SetVariable (
2437 L"Setup",
2438 &gSetupVariableGuid,
2439 VariableAttributes,
2440 VariableSize,
2441 &SetupData
2442 );
2443 ASSERT_EFI_ERROR(Status);
2444 DEBUG ((DEBUG_INFO, "Acpi table revision: 0x%x, saved successfully.\n", Table->Revision));
2445
2446 return Status;
2447 }
2448
2449 /**
2450 ACPI Platform driver installation function.
2451
2452 @param[in] ImageHandle Handle for this drivers loaded image protocol.
2453 @param[in] SystemTable EFI system table.
2454
2455 @retval EFI_SUCCESS The driver installed without error.
2456 @retval EFI_ABORTED The driver encountered an error and could not complete installation of
2457 the ACPI tables.
2458
2459 **/
2460 EFI_STATUS
2461 EFIAPI
2462 InstallAcpiPlatform (
2463 IN EFI_HANDLE ImageHandle,
2464 IN EFI_SYSTEM_TABLE *SystemTable
2465 )
2466 {
2467 EFI_STATUS Status;
2468 INTN Instance;
2469 EFI_ACPI_COMMON_HEADER *CurrentTable;
2470 UINTN TableHandle;
2471 UINTN VarDataSize;
2472 EFI_HANDLE Handle;
2473 UINT8 PortData;
2474 //UINT8 BatteryNum;
2475 EFI_CPUID_REGISTER CpuidRegs;
2476 EFI_MP_SERVICES_PROTOCOL *MpService;
2477 UINTN NumberOfCPUs;
2478 UINTN NumberOfEnabledCPUs;
2479 UINTN Index;
2480 UINT8 CtdpLevels;
2481 EFI_EVENT EndOfDxeEvent;
2482 SA_SETUP SaSetup;
2483 CPU_SETUP CpuSetup;
2484 GPIO_INIT_CONFIG *UcmcGpioTable;
2485 UINT16 UcmcGpioTableSize = 0;
2486
2487
2488 UINT16 ModuleName[MIPICAM_MODULE_NAME_LENGTH];
2489 UINT64 AcpiGuidPart1;
2490 UINT64 AcpiGuidPart2;
2491 CHAR16 LocalGuidString[GUID_CHARS_NUMBER];
2492 ME_BIOS_PAYLOAD_HOB *MbpHob = NULL;
2493
2494
2495 Instance = 0;
2496 CurrentTable = NULL;
2497 TableHandle = 0;
2498 Handle = NULL;
2499
2500 AsmCpuid (
2501 1,
2502 &CpuidRegs.RegEax,
2503 &CpuidRegs.RegEbx,
2504 &CpuidRegs.RegEcx,
2505 &CpuidRegs.RegEdx
2506 );
2507
2508 PublishOverClockingAcpiTable ();
2509
2510 //
2511 // Locate the setup configuration data
2512 // We assert if it is not found because we have a dependency on PlatformCpu,
2513 // published by the platform setup driver.
2514 // This should ensure that we only get called after the setup has updated the
2515 // variable.
2516 //
2517 VarDataSize = sizeof (SETUP_DATA);
2518 Status = gRT->GetVariable (
2519 L"Setup",
2520 &gSetupVariableGuid,
2521 NULL,
2522 &VarDataSize,
2523 &mSystemConfiguration
2524 );
2525
2526 VarDataSize = sizeof (SA_SETUP);
2527 Status = gRT->GetVariable (
2528 L"SaSetup",
2529 &gSaSetupVariableGuid,
2530 NULL,
2531 &VarDataSize,
2532 &SaSetup
2533 );
2534
2535 VarDataSize = sizeof (ME_SETUP);
2536 Status = gRT->GetVariable (
2537 L"MeSetup",
2538 &gMeSetupVariableGuid,
2539 NULL,
2540 &VarDataSize,
2541 &mMeSetup
2542 );
2543
2544 VarDataSize = sizeof (CPU_SETUP);
2545 Status = gRT->GetVariable (
2546 L"CpuSetup",
2547 &gCpuSetupVariableGuid,
2548 NULL,
2549 &VarDataSize,
2550 &CpuSetup
2551 );
2552
2553 VarDataSize = sizeof (PCH_SETUP);
2554 Status = gRT->GetVariable (
2555 L"PchSetup",
2556 &gPchSetupVariableGuid,
2557 NULL,
2558 &VarDataSize,
2559 &mPchSetup
2560 );
2561 //
2562 // Locate the MP services protocol
2563 // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
2564 //
2565 Status = gBS->LocateProtocol (
2566 &gEfiMpServiceProtocolGuid,
2567 NULL,
2568 (VOID **) &MpService
2569 );
2570 if (EFI_ERROR (Status)) {
2571 return Status;
2572 }
2573
2574 //
2575 // Determine the number of processors
2576 //
2577 MpService->GetNumberOfProcessors (
2578 MpService,
2579 &NumberOfCPUs,
2580 &NumberOfEnabledCPUs
2581 );
2582
2583 //
2584 // Allocate and initialize the NVS area for SMM and ASL communication.
2585 //
2586 AcpiGnvsInit((VOID **) &mPlatformNvsAreaProtocol.Area);
2587
2588 //
2589 // Update global NVS area for ASL and SMM init code to use
2590 //
2591 //mPlatformNvsAreaProtocol.Area->EnableThermalOffset = mSystemConfiguration.EnableThermalOffset;
2592 mPlatformNvsAreaProtocol.Area->Ac1TripPoint = mSystemConfiguration.Ac1TripPoint;
2593 mPlatformNvsAreaProtocol.Area->Ac0TripPoint = mSystemConfiguration.Ac0TripPoint;
2594 mPlatformNvsAreaProtocol.Area->Ac1FanSpeed = mSystemConfiguration.Ac1FanSpeed;
2595 mPlatformNvsAreaProtocol.Area->Ac0FanSpeed = mSystemConfiguration.Ac0FanSpeed;
2596 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;
2597 mPlatformNvsAreaProtocol.Area->PassiveTc1Value = mSystemConfiguration.PassiveTc1Value;
2598 mPlatformNvsAreaProtocol.Area->PassiveTc2Value = mSystemConfiguration.PassiveTc2Value;
2599 mPlatformNvsAreaProtocol.Area->PassiveTspValue = mSystemConfiguration.PassiveTspValue;
2600 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;
2601 mPlatformNvsAreaProtocol.Area->EmaEnable = 0; //mSystemConfiguration.EmaEnable; //todo
2602 mPlatformNvsAreaProtocol.Area->ThreadCount = (UINT8) NumberOfEnabledCPUs;
2603 mPlatformNvsAreaProtocol.Area->MefEnable = 0; //mSystemConfiguration.MefEnable; //todo
2604
2605 //
2606 // DPTF Devices and trip points
2607 //
2608 mPlatformNvsAreaProtocol.Area->EnableDptf = mSystemConfiguration.EnableDptf;
2609
2610 if (mSystemConfiguration.EnableDptf == 1) {
2611
2612 mPlatformNvsAreaProtocol.Area->EnableDCFG = mSystemConfiguration.EnableDCFG;
2613 mPlatformNvsAreaProtocol.Area->EnableSaDevice = mSystemConfiguration.EnableSaDevice;
2614 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointSA = mSystemConfiguration.ActiveThermalTripPointSA;
2615 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointSA = mSystemConfiguration.PassiveThermalTripPointSA;
2616 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSA = mSystemConfiguration.CriticalThermalTripPointSA;
2617 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSaS3 = mSystemConfiguration.CriticalThermalTripPointSaS3;
2618 mPlatformNvsAreaProtocol.Area->HotThermalTripPointSA = mSystemConfiguration.HotThermalTripPointSA;
2619 mPlatformNvsAreaProtocol.Area->ThermalSamplingPeriodSA = mSystemConfiguration.ThermalSamplingPeriodSA;
2620 mPlatformNvsAreaProtocol.Area->PpccStepSize = mSystemConfiguration.PpccStepSize;
2621 mPlatformNvsAreaProtocol.Area->MinPowerLimit0 = mSystemConfiguration.MinPowerLimit0;
2622 mPlatformNvsAreaProtocol.Area->MinPowerLimit1 = mSystemConfiguration.MinPowerLimit1;
2623 mPlatformNvsAreaProtocol.Area->MinPowerLimit2 = mSystemConfiguration.MinPowerLimit2;
2624
2625 //
2626 // DPTF Policies
2627 //
2628 CtdpLevels = (UINT8) (RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO),33) & 0x03);
2629 if ((CtdpLevels == 1) || (CtdpLevels == 2)) {
2630 mPlatformNvsAreaProtocol.Area->EnableCtdpPolicy = mSystemConfiguration.EnableCtdpPolicy;
2631 } else {
2632 mPlatformNvsAreaProtocol.Area->EnableCtdpPolicy = 0;
2633 }
2634
2635 //
2636 // DPTF Devices and trip points
2637 //
2638 mPlatformNvsAreaProtocol.Area->EnableFan1Device = mSystemConfiguration.EnableFan1Device;
2639
2640 //
2641 // DPTF Policies
2642 //
2643 mPlatformNvsAreaProtocol.Area->EnableActivePolicy = mSystemConfiguration.EnableActivePolicy;
2644 mPlatformNvsAreaProtocol.Area->EnablePassivePolicy = mSystemConfiguration.EnablePassivePolicy;
2645 mPlatformNvsAreaProtocol.Area->EnableCriticalPolicy = mSystemConfiguration.EnableCriticalPolicy;
2646 mPlatformNvsAreaProtocol.Area->TrtRevision = mSystemConfiguration.TrtRevision;
2647 mPlatformNvsAreaProtocol.Area->EnableAPPolicy = mSystemConfiguration.EnableAPPolicy;
2648 mPlatformNvsAreaProtocol.Area->EnablePIDPolicy = mSystemConfiguration.EnablePIDPolicy;
2649
2650 mPlatformNvsAreaProtocol.Area->OemDesignVariable0 = mSystemConfiguration.OemDesignVariable0;
2651 mPlatformNvsAreaProtocol.Area->OemDesignVariable1 = mSystemConfiguration.OemDesignVariable1;
2652 mPlatformNvsAreaProtocol.Area->OemDesignVariable2 = mSystemConfiguration.OemDesignVariable2;
2653 mPlatformNvsAreaProtocol.Area->OemDesignVariable3 = mSystemConfiguration.OemDesignVariable3;
2654 mPlatformNvsAreaProtocol.Area->OemDesignVariable4 = mSystemConfiguration.OemDesignVariable4;
2655 mPlatformNvsAreaProtocol.Area->OemDesignVariable5 = mSystemConfiguration.OemDesignVariable5;
2656
2657 //
2658 // CLPO (Current Logical Processor Off lining Setting)
2659 //
2660 mPlatformNvsAreaProtocol.Area->LPOEnable = mSystemConfiguration.LPOEnable;
2661 mPlatformNvsAreaProtocol.Area->LPOStartPState = mSystemConfiguration.LPOStartPState;
2662 mPlatformNvsAreaProtocol.Area->LPOStepSize = mSystemConfiguration.LPOStepSize;
2663 mPlatformNvsAreaProtocol.Area->LPOPowerControlSetting = mSystemConfiguration.LPOPowerControlSetting;
2664 mPlatformNvsAreaProtocol.Area->LPOPerformanceControlSetting = mSystemConfiguration.LPOPerformanceControlSetting;
2665
2666 mPlatformNvsAreaProtocol.Area->EnableDisplayParticipant = mSystemConfiguration.EnableDisplayParticipant;
2667 mPlatformNvsAreaProtocol.Area->DisplayDepthLowerLimit = mSystemConfiguration.DisplayDepthLowerLimit;
2668 mPlatformNvsAreaProtocol.Area->DisplayDepthUpperLimit = mSystemConfiguration.DisplayDepthUpperLimit;
2669
2670 mPlatformNvsAreaProtocol.Area->EnableChargerParticipant = mSystemConfiguration.EnableChargerParticipant;
2671 mPlatformNvsAreaProtocol.Area->EnablePowerParticipant = mSystemConfiguration.EnablePowerParticipant;
2672 mPlatformNvsAreaProtocol.Area->PowerParticipantPollingRate = mSystemConfiguration.PowerParticipantPollingRate;
2673 mPlatformNvsAreaProtocol.Area->EnablePowerBossPolicy = mSystemConfiguration.EnablePowerBossPolicy;
2674
2675 mPlatformNvsAreaProtocol.Area->Enable2DCameraParticipant = mSystemConfiguration.Enable2DCameraParticipant;
2676
2677 mPlatformNvsAreaProtocol.Area->EnableVSPolicy = mSystemConfiguration.EnableVSPolicy;
2678
2679 mPlatformNvsAreaProtocol.Area->EnableVS1Participant = mSystemConfiguration.EnableVS1Participant;
2680 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointVS1 = mSystemConfiguration.ActiveThermalTripPointVS1;
2681 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointVS1 = mSystemConfiguration.PassiveThermalTripPointVS1;
2682 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointVS1 = mSystemConfiguration.CriticalThermalTripPointVS1;
2683 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointVS1S3 = mSystemConfiguration.CriticalThermalTripPointVS1S3;
2684 mPlatformNvsAreaProtocol.Area->HotThermalTripPointVS1 = mSystemConfiguration.HotThermalTripPointVS1;
2685
2686 mPlatformNvsAreaProtocol.Area->EnableVS2Participant = mSystemConfiguration.EnableVS2Participant;
2687 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointVS2 = mSystemConfiguration.ActiveThermalTripPointVS2;
2688 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointVS2 = mSystemConfiguration.PassiveThermalTripPointVS2;
2689 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointVS2 = mSystemConfiguration.CriticalThermalTripPointVS2;
2690 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointVS2S3 = mSystemConfiguration.CriticalThermalTripPointVS2S3;
2691 mPlatformNvsAreaProtocol.Area->HotThermalTripPointVS2 = mSystemConfiguration.HotThermalTripPointVS2;
2692
2693 mPlatformNvsAreaProtocol.Area->EnableStorageParticipantST1 = mSystemConfiguration.EnableStorageParticipantST1;
2694 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointST1 = mSystemConfiguration.ActiveThermalTripPointST1;
2695 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointST1 = mSystemConfiguration.PassiveThermalTripPointST1;
2696 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointST1 = mSystemConfiguration.CriticalThermalTripPointST1;
2697 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointS3ST1 = mSystemConfiguration.CriticalThermalTripPointS3ST1;
2698 mPlatformNvsAreaProtocol.Area->HotThermalTripPointST1 = mSystemConfiguration.HotThermalTripPointST1;
2699 mPlatformNvsAreaProtocol.Area->EnableStorageParticipantST2 = mSystemConfiguration.EnableStorageParticipantST2;
2700 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointST2 = mSystemConfiguration.ActiveThermalTripPointST2;
2701 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointST2 = mSystemConfiguration.PassiveThermalTripPointST2;
2702 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointST2 = mSystemConfiguration.CriticalThermalTripPointST2;
2703 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointS3ST2 = mSystemConfiguration.CriticalThermalTripPointS3ST2;
2704 mPlatformNvsAreaProtocol.Area->HotThermalTripPointST2 = mSystemConfiguration.HotThermalTripPointST2;
2705
2706 #ifdef PCH_ICL
2707 mPlatformNvsAreaProtocol.Area->EnablePchFivrParticipant = mSystemConfiguration.EnablePchFivrParticipant;
2708 #endif
2709
2710 mPlatformNvsAreaProtocol.Area->EnableRFIMPolicy = mSystemConfiguration.EnableRFIMPolicy;
2711
2712 mPlatformNvsAreaProtocol.Area->EnableWWANParticipant = mSystemConfiguration.EnableWWANParticipant;
2713 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointWWAN = mSystemConfiguration.ActiveThermalTripPointWWAN;
2714 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointWWAN = mSystemConfiguration.PassiveThermalTripPointWWAN;
2715 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointWWAN = mSystemConfiguration.CriticalThermalTripPointWWAN;
2716 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointWwanS3 = mSystemConfiguration.CriticalThermalTripPointWwanS3;
2717 mPlatformNvsAreaProtocol.Area->HotThermalTripPointWWAN = mSystemConfiguration.HotThermalTripPointWWAN;
2718
2719 mPlatformNvsAreaProtocol.Area->EnableWrlsParticipant = mSystemConfiguration.EnableWrlsParticipant;
2720 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointWrls = mSystemConfiguration.ActiveThermalTripPointWrls;
2721 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointWrls = mSystemConfiguration.PassiveThermalTripPointWrls;
2722 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointWrls = mSystemConfiguration.CriticalThermalTripPointWrls;
2723 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointWrlsS3 = mSystemConfiguration.CriticalThermalTripPointWrlsS3;
2724 mPlatformNvsAreaProtocol.Area->HotThermalTripPointWrls = mSystemConfiguration.HotThermalTripPointWrls;
2725 mPlatformNvsAreaProtocol.Area->ThermalSamplingPeriodWrls = mSystemConfiguration.ThermalSamplingPeriodWrls;
2726
2727 mPlatformNvsAreaProtocol.Area->EnableSen1Participant = mSystemConfiguration.EnableSen1Participant;
2728 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointSen1 = mSystemConfiguration.ActiveThermalTripPointSen1;
2729 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointSen1 = mSystemConfiguration.PassiveThermalTripPointSen1;
2730 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen1 = mSystemConfiguration.CriticalThermalTripPointSen1;
2731 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen1S3 = mSystemConfiguration.CriticalThermalTripPointSen1S3;
2732 mPlatformNvsAreaProtocol.Area->HotThermalTripPointSen1 = mSystemConfiguration.HotThermalTripPointSen1;
2733 mPlatformNvsAreaProtocol.Area->SensorSamplingPeriodSen1 = mSystemConfiguration.SensorSamplingPeriodSen1;
2734
2735 mPlatformNvsAreaProtocol.Area->EnableSen2Participant = mSystemConfiguration.EnableSen2Participant;
2736 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointSen2 = mSystemConfiguration.ActiveThermalTripPointSen2;
2737 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointSen2 = mSystemConfiguration.PassiveThermalTripPointSen2;
2738 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen2 = mSystemConfiguration.CriticalThermalTripPointSen2;
2739 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen2S3 = mSystemConfiguration.CriticalThermalTripPointSen2S3;
2740 mPlatformNvsAreaProtocol.Area->HotThermalTripPointSen2 = mSystemConfiguration.HotThermalTripPointSen2;
2741 mPlatformNvsAreaProtocol.Area->SensorSamplingPeriodSen2 = mSystemConfiguration.SensorSamplingPeriodSen2;
2742
2743 mPlatformNvsAreaProtocol.Area->EnableSen3Participant = mSystemConfiguration.EnableSen3Participant;
2744 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointSen3 = mSystemConfiguration.ActiveThermalTripPointSen3;
2745 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointSen3 = mSystemConfiguration.PassiveThermalTripPointSen3;
2746 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen3 = mSystemConfiguration.CriticalThermalTripPointSen3;
2747 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen3S3 = mSystemConfiguration.CriticalThermalTripPointSen3S3;
2748 mPlatformNvsAreaProtocol.Area->HotThermalTripPointSen3 = mSystemConfiguration.HotThermalTripPointSen3;
2749 mPlatformNvsAreaProtocol.Area->SensorSamplingPeriodSen3 = mSystemConfiguration.SensorSamplingPeriodSen3;
2750
2751 mPlatformNvsAreaProtocol.Area->EnableSen4Participant = mSystemConfiguration.EnableSen4Participant;
2752 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointSen4 = mSystemConfiguration.ActiveThermalTripPointSen4;
2753 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointSen4 = mSystemConfiguration.PassiveThermalTripPointSen4;
2754 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen4 = mSystemConfiguration.CriticalThermalTripPointSen4;
2755 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen4S3 = mSystemConfiguration.CriticalThermalTripPointSen4S3;
2756 mPlatformNvsAreaProtocol.Area->HotThermalTripPointSen4 = mSystemConfiguration.HotThermalTripPointSen4;
2757 mPlatformNvsAreaProtocol.Area->SensorSamplingPeriodSen4 = mSystemConfiguration.SensorSamplingPeriodSen4;
2758
2759 mPlatformNvsAreaProtocol.Area->EnableSen5Participant = mSystemConfiguration.EnableSen5Participant;
2760 mPlatformNvsAreaProtocol.Area->ActiveThermalTripPointSen5 = mSystemConfiguration.ActiveThermalTripPointSen5;
2761 mPlatformNvsAreaProtocol.Area->PassiveThermalTripPointSen5 = mSystemConfiguration.PassiveThermalTripPointSen5;
2762 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen5 = mSystemConfiguration.CriticalThermalTripPointSen5;
2763 mPlatformNvsAreaProtocol.Area->CriticalThermalTripPointSen5S3 = mSystemConfiguration.CriticalThermalTripPointSen5S3;
2764 mPlatformNvsAreaProtocol.Area->HotThermalTripPointSen5 = mSystemConfiguration.HotThermalTripPointSen5;
2765 mPlatformNvsAreaProtocol.Area->SensorSamplingPeriodSen5 = mSystemConfiguration.SensorSamplingPeriodSen5;
2766
2767 }
2768
2769 mPlatformNvsAreaProtocol.Area->HebcValue = mSystemConfiguration.HebcValue;
2770
2771 //
2772 // BIOS only version of CTDP. (CTDP without using DPTF)
2773 //
2774 if (CpuSetup.ConfigTdpLock == 1 || mSystemConfiguration.EnableDptf == 1) {
2775 mPlatformNvsAreaProtocol.Area->ConfigTdpBios = 0;
2776 } else {
2777 mPlatformNvsAreaProtocol.Area->ConfigTdpBios = CpuSetup.ConfigTdpBios;
2778 }
2779
2780 //
2781 // PECI Access Method
2782 //
2783 mPlatformNvsAreaProtocol.Area->PeciAccessMethod = mSystemConfiguration.PeciAccessMethod;
2784
2785 //
2786 // Wireless support
2787 //
2788 mPlatformNvsAreaProtocol.Area->PowerSharingManagerEnable = mSystemConfiguration.PowerSharingManagerEnable;
2789 mPlatformNvsAreaProtocol.Area->PsmSplcDomainType1 = mSystemConfiguration.PsmSplcDomainType1;
2790 mPlatformNvsAreaProtocol.Area->PsmSplcPowerLimit1 = mSystemConfiguration.PsmSplcPowerLimit1;
2791 mPlatformNvsAreaProtocol.Area->PsmSplcTimeWindow1 = mSystemConfiguration.PsmSplcTimeWindow1;
2792 mPlatformNvsAreaProtocol.Area->PsmSplcDomainType2 = mSystemConfiguration.PsmSplcDomainType2;
2793 mPlatformNvsAreaProtocol.Area->PsmSplcPowerLimit2 = mSystemConfiguration.PsmSplcPowerLimit2;
2794 mPlatformNvsAreaProtocol.Area->PsmSplcTimeWindow2 = mSystemConfiguration.PsmSplcTimeWindow2;
2795
2796 mPlatformNvsAreaProtocol.Area->PsmDplcDomainType1 = mSystemConfiguration.PsmDplcDomainType1;
2797 mPlatformNvsAreaProtocol.Area->PsmDplcDomainPreference1 = mSystemConfiguration.PsmDplcDomainPreference1;
2798 mPlatformNvsAreaProtocol.Area->PsmDplcPowerLimitIndex1 = mSystemConfiguration.PsmDplcPowerLimitIndex1;
2799 mPlatformNvsAreaProtocol.Area->PsmDplcDefaultPowerLimit1 = mSystemConfiguration.PsmDplcDefaultPowerLimit1;
2800 mPlatformNvsAreaProtocol.Area->PsmDplcDefaultTimeWindow1 = mSystemConfiguration.PsmDplcDefaultTimeWindow1;
2801 mPlatformNvsAreaProtocol.Area->PsmDplcMinimumPowerLimit1 = mSystemConfiguration.PsmDplcMinimumPowerLimit1;
2802 mPlatformNvsAreaProtocol.Area->PsmDplcMaximumPowerLimit1 = mSystemConfiguration.PsmDplcMaximumPowerLimit1;
2803 mPlatformNvsAreaProtocol.Area->PsmDplcMaximumTimeWindow1 = mSystemConfiguration.PsmDplcMaximumTimeWindow1;
2804
2805 mPlatformNvsAreaProtocol.Area->PsmDplcDomainType2 = mSystemConfiguration.PsmDplcDomainType2;
2806 mPlatformNvsAreaProtocol.Area->PsmDplcDomainPreference2 = mSystemConfiguration.PsmDplcDomainPreference2;
2807 mPlatformNvsAreaProtocol.Area->PsmDplcPowerLimitIndex2 = mSystemConfiguration.PsmDplcPowerLimitIndex2;
2808 mPlatformNvsAreaProtocol.Area->PsmDplcDefaultPowerLimit2 = mSystemConfiguration.PsmDplcDefaultPowerLimit2;
2809 mPlatformNvsAreaProtocol.Area->PsmDplcDefaultTimeWindow2 = mSystemConfiguration.PsmDplcDefaultTimeWindow2;
2810 mPlatformNvsAreaProtocol.Area->PsmDplcMinimumPowerLimit2 = mSystemConfiguration.PsmDplcMinimumPowerLimit2;
2811 mPlatformNvsAreaProtocol.Area->PsmDplcMaximumPowerLimit2 = mSystemConfiguration.PsmDplcMaximumPowerLimit2;
2812 mPlatformNvsAreaProtocol.Area->PsmDplcMaximumTimeWindow2 = mSystemConfiguration.PsmDplcMaximumTimeWindow2;
2813
2814 mPlatformNvsAreaProtocol.Area->WifiEnable = mSystemConfiguration.WifiEnable;
2815 if (mSystemConfiguration.WifiEnable == 1) {
2816 mPlatformNvsAreaProtocol.Area->WifiDomainType1 = mSystemConfiguration.WifiDomainType1;
2817 mPlatformNvsAreaProtocol.Area->WifiPowerLimit1 = mSystemConfiguration.WifiPowerLimit1;
2818 mPlatformNvsAreaProtocol.Area->WifiTimeWindow1 = mSystemConfiguration.WifiTimeWindow1;
2819 mPlatformNvsAreaProtocol.Area->WifiDomainType2 = mSystemConfiguration.WifiDomainType2;
2820 mPlatformNvsAreaProtocol.Area->WifiPowerLimit2 = mSystemConfiguration.WifiPowerLimit2;
2821 mPlatformNvsAreaProtocol.Area->WifiTimeWindow2 = mSystemConfiguration.WifiTimeWindow2;
2822 mPlatformNvsAreaProtocol.Area->WifiDomainType3 = mSystemConfiguration.WifiDomainType3;
2823 mPlatformNvsAreaProtocol.Area->WifiPowerLimit3 = mSystemConfiguration.WifiPowerLimit3;
2824 mPlatformNvsAreaProtocol.Area->WifiTimeWindow3 = mSystemConfiguration.WifiTimeWindow3;
2825 mPlatformNvsAreaProtocol.Area->TRxDelay0 = mSystemConfiguration.TRxDelay0;
2826 mPlatformNvsAreaProtocol.Area->TRxCableLength0 = mSystemConfiguration.TRxCableLength0;
2827 mPlatformNvsAreaProtocol.Area->TRxDelay1 = mSystemConfiguration.TRxDelay1;
2828 mPlatformNvsAreaProtocol.Area->TRxCableLength1 = mSystemConfiguration.TRxCableLength1;
2829 mPlatformNvsAreaProtocol.Area->WrddDomainType1 = mSystemConfiguration.WrddDomainType1;
2830 mPlatformNvsAreaProtocol.Area->WrddCountryIndentifier1 = mSystemConfiguration.WrddCountryIndentifier1;
2831 mPlatformNvsAreaProtocol.Area->WrddDomainType2 = mSystemConfiguration.WrddDomainType2;
2832 mPlatformNvsAreaProtocol.Area->WrddCountryIndentifier2 = mSystemConfiguration.WrddCountryIndentifier2;
2833 mPlatformNvsAreaProtocol.Area->WrdsWiFiSarEnable = mSystemConfiguration.WrdsWiFiSarEnable;
2834 mPlatformNvsAreaProtocol.Area->WigigRfe = mSystemConfiguration.WigigRfe;
2835 if (mPlatformNvsAreaProtocol.Area->WigigRfe == 1) {
2836 mPlatformNvsAreaProtocol.Area->WiGigRfeCh1 = mSystemConfiguration.WiGigRfeCh1;
2837 mPlatformNvsAreaProtocol.Area->WiGigRfeCh2 = mSystemConfiguration.WiGigRfeCh2;
2838 mPlatformNvsAreaProtocol.Area->WiGigRfeCh3 = mSystemConfiguration.WiGigRfeCh3;
2839 mPlatformNvsAreaProtocol.Area->WiGigRfeCh4 = mSystemConfiguration.WiGigRfeCh4;
2840 } else {
2841 mPlatformNvsAreaProtocol.Area->WiGigRfeCh1 = 0x0;
2842 mPlatformNvsAreaProtocol.Area->WiGigRfeCh2 = 0x0;
2843 mPlatformNvsAreaProtocol.Area->WiGigRfeCh3 = 0x0;
2844 mPlatformNvsAreaProtocol.Area->WiGigRfeCh4 = 0x0;
2845 }
2846 mPlatformNvsAreaProtocol.Area->AwvClassIndex = mSystemConfiguration.AwvClassIndex;
2847 mPlatformNvsAreaProtocol.Area->WakeOnWiGigSupport = mSystemConfiguration.WakeOnWiGigSupport;
2848
2849 mPlatformNvsAreaProtocol.Area->BluetoothSar = mSystemConfiguration.BluetoothSar;
2850 if (mPlatformNvsAreaProtocol.Area->BluetoothSar == 1) {
2851 mPlatformNvsAreaProtocol.Area->BluetoothSarBr = mSystemConfiguration.BluetoothSarBr;
2852 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr2 = mSystemConfiguration.BluetoothSarEdr2;
2853 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr3 = mSystemConfiguration.BluetoothSarEdr3;
2854 mPlatformNvsAreaProtocol.Area->BluetoothSarLe = mSystemConfiguration.BluetoothSarLe;
2855 } else {
2856 mPlatformNvsAreaProtocol.Area->BluetoothSarBr = 0x0;
2857 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr2 = 0x0;
2858 mPlatformNvsAreaProtocol.Area->BluetoothSarEdr3 = 0x0;
2859 mPlatformNvsAreaProtocol.Area->BluetoothSarLe = 0x0;
2860 }
2861 }
2862
2863 mPlatformNvsAreaProtocol.Area->CoExistenceManager = mSystemConfiguration.CoExistenceManager;
2864 mPlatformNvsAreaProtocol.Area->XdciFnEnable = mPchSetup.PchXdciSupport;
2865 //
2866 // Initilize platform ID in Global NVS Area
2867 //
2868 mPlatformNvsAreaProtocol.Area->GenerationId = PcdGet8 (PcdPlatformGeneration);
2869 mPlatformNvsAreaProtocol.Area->PlatformFlavor = PcdGet8 (PcdPlatformFlavor);
2870 mPlatformNvsAreaProtocol.Area->BoardRev = PcdGet8 (PcdBoardRev);
2871 mPlatformNvsAreaProtocol.Area->BoardType = PcdGet8 (PcdBoardType);
2872
2873 mPlatformNvsAreaProtocol.Area->SerialPortAcpiDebug = mSystemConfiguration.AcpiDebug && mSystemConfiguration.SerialPortAcpiDebug;
2874
2875 mPlatformNvsAreaProtocol.Area->Rtd3Support = mSystemConfiguration.Rtd3Support;
2876 mPlatformNvsAreaProtocol.Area->Rtd3P0dl = mSystemConfiguration.Rtd3P0dl;
2877 mPlatformNvsAreaProtocol.Area->Rtd3AudioDelay = mSystemConfiguration.Rtd3AudioDelay;
2878 mPlatformNvsAreaProtocol.Area->Rtd3SensorHub = mSystemConfiguration.Rtd3SensorHub;
2879 mPlatformNvsAreaProtocol.Area->Rtd3TouchPanelDelay = mSystemConfiguration.Rtd3TouchPanelDelay;
2880 mPlatformNvsAreaProtocol.Area->Rtd3TouchPadDelay = mSystemConfiguration.Rtd3TouchPadDelay;
2881 mPlatformNvsAreaProtocol.Area->VRRampUpDelay = mSystemConfiguration.VRRampUpDelay;
2882 mPlatformNvsAreaProtocol.Area->PstateCapping = mSystemConfiguration.PstateCapping;
2883 mPlatformNvsAreaProtocol.Area->UsbPowerResourceTest = (mSystemConfiguration.Rtd3UsbPt2 << 4)
2884 | mSystemConfiguration.Rtd3UsbPt1;
2885 mPlatformNvsAreaProtocol.Area->SensorStandby = mSystemConfiguration.SensorStandby;
2886 mPlatformNvsAreaProtocol.Area->Rtd3Config0 = (mSystemConfiguration.Rtd3WWAN << 7)
2887 | (mSystemConfiguration.Rtd3I2CTouchPanel << 4); // Applicable for SKL SDS RTD3 SIP only
2888 mPlatformNvsAreaProtocol.Area->Rtd3Config1 = (mSystemConfiguration.Rtd3RemapCR3 << 8)
2889 | (mSystemConfiguration.Rtd3RemapCR2 << 7)
2890 | (mSystemConfiguration.Rtd3RemapCR1 << 6)
2891 | (mSystemConfiguration.Rtd3SataPort5 << 5)
2892 | (mSystemConfiguration.Rtd3SataPort4 << 4)
2893 | (mSystemConfiguration.Rtd3SataPort3 << 3)
2894 | (mSystemConfiguration.Rtd3SataPort2 << 2)
2895 | (mSystemConfiguration.Rtd3SataPort1 << 1)
2896 | mSystemConfiguration.Rtd3SataPort0;
2897
2898 mPlatformNvsAreaProtocol.Area->DiscreteWifiRtd3ColdSupport = PcdGetBool (PcdDiscreteWifiRtd3ColdSupport);
2899 mPlatformNvsAreaProtocol.Area->DiscreteWigigRtd3ColdSupport = PcdGetBool (PcdDiscreteWigigRtd3ColdSupport);
2900 mPlatformNvsAreaProtocol.Area->DiscreteWwanRtd3ColdSupport = PcdGetBool (PcdDiscreteWwanRtd3ColdSupport);
2901 //
2902 // Enable PowerState
2903 //
2904 mPlatformNvsAreaProtocol.Area->PowerState = 1; // AC =1; for mobile platform, will update this value in SmmPlatform.c
2905 /*
2906 if (mSystemConfiguration.IgdLcdIBia == 0) {
2907 //
2908 // Re-change the ALS to disable according to setup.
2909 //
2910 mPlatformNvsAreaProtocol.Area->AlsEnable = 0;
2911 } else if (mSystemConfiguration.IgdLcdIBia < 6) {
2912 //
2913 // Re-change the ALS to enable (2 accepted in ACPI) according to setup.
2914 //
2915 mPlatformNvsAreaProtocol.Area->AlsEnable = 2;
2916 mPlatformNvsAreaProtocol.Area->AlsAdjustmentFactor = mSystemConfiguration.IgdLcdIBia * 20;
2917 } else if (mSystemConfiguration.IgdLcdIBia == 6) {
2918 //
2919 // The default value from VBT
2920 //
2921 mPlatformNvsAreaProtocol.Area->AlsAdjustmentFactor = 100;
2922 }
2923 */
2924
2925 //
2926 // These don't have setup controls yet
2927 //
2928 mPlatformNvsAreaProtocol.Area->IdeMode = 0;
2929
2930 if (PcdGetBool (PcdEcPresent) == TRUE) {
2931 //
2932 // Call EC lib to get PCIe dock status
2933 //
2934 PortData = 0;
2935 Status = GetPcieDockStatus (&PortData);
2936
2937 //
2938 // the bit0 is PCIe Dock Status, 1 = docked
2939 //
2940 mPlatformNvsAreaProtocol.Area->PcieDockStatus = (PortData & 1);
2941 }
2942
2943 mPlatformNvsAreaProtocol.Area->NativePCIESupport = mSystemConfiguration.PciExpNative;
2944 mPlatformNvsAreaProtocol.Area->PlatformCpuId = (CpuidRegs.RegEax & 0x0FFFFF);
2945
2946 //
2947 // Create an End of DXE event.
2948 //
2949 Status = gBS->CreateEventEx (
2950 EVT_NOTIFY_SIGNAL,
2951 TPL_CALLBACK,
2952 AcpiEndOfDxeEvent,
2953 NULL,
2954 &gEfiEndOfDxeEventGroupGuid,
2955 &EndOfDxeEvent
2956 );
2957 ASSERT_EFI_ERROR (Status);
2958
2959 //
2960 // SIO related option
2961 //
2962 Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) &mCpuIo);
2963 ASSERT_EFI_ERROR (Status);
2964
2965 mPlatformNvsAreaProtocol.Area->WPCN381U = PLATFORM_NVS_DEVICE_DISABLE;
2966
2967 mPlatformNvsAreaProtocol.Area->DockedSioPresent = PLATFORM_NVS_DEVICE_DISABLE;
2968 mPlatformNvsAreaProtocol.Area->DockComA = PLATFORM_NVS_DEVICE_DISABLE;
2969 mPlatformNvsAreaProtocol.Area->DockComB = PLATFORM_NVS_DEVICE_DISABLE;
2970 mPlatformNvsAreaProtocol.Area->DockLpt = PLATFORM_NVS_DEVICE_DISABLE;
2971 mPlatformNvsAreaProtocol.Area->DockFdc = PLATFORM_NVS_DEVICE_DISABLE;
2972
2973 //
2974 // Check ID for NS87393 SIO, which is connected to Thimble Peak.
2975 //
2976 PortData = 0x20;
2977 Status = mCpuIo->Io.Write (
2978 mCpuIo,
2979 EfiCpuIoWidthUint8,
2980 NAT_CONFIG_INDEX,
2981 1,
2982 &PortData
2983 );
2984 ASSERT_EFI_ERROR (Status);
2985
2986 Status = mCpuIo->Io.Read (
2987 mCpuIo,
2988 EfiCpuIoWidthUint8,
2989 NAT_CONFIG_DATA,
2990 1,
2991 &PortData
2992 );
2993 ASSERT_EFI_ERROR (Status);
2994
2995 if (PortData == 0xEA) {
2996 mPlatformNvsAreaProtocol.Area->DockedSioPresent = PLATFORM_NVS_DEVICE_ENABLE;
2997 mPlatformNvsAreaProtocol.Area->DockComA = PLATFORM_NVS_DEVICE_ENABLE;
2998 mPlatformNvsAreaProtocol.Area->DockComB = PLATFORM_NVS_DEVICE_ENABLE;
2999 }
3000
3001 if (mPlatformNvsAreaProtocol.Area->DockedSioPresent != PLATFORM_NVS_DEVICE_ENABLE) {
3002 //
3003 // Check ID for SIO WPCN381U
3004 //
3005 Status = mCpuIo->Io.Read (
3006 mCpuIo,
3007 EfiCpuIoWidthUint8,
3008 WPCN381U_CONFIG_INDEX,
3009 1,
3010 &PortData
3011 );
3012 ASSERT_EFI_ERROR (Status);
3013 if (PortData != 0xFF) {
3014 PortData = 0x20;
3015 Status = mCpuIo->Io.Write (
3016 mCpuIo,
3017 EfiCpuIoWidthUint8,
3018 WPCN381U_CONFIG_INDEX,
3019 1,
3020 &PortData
3021 );
3022 ASSERT_EFI_ERROR (Status);
3023 Status = mCpuIo->Io.Read (
3024 mCpuIo,
3025 EfiCpuIoWidthUint8,
3026 WPCN381U_CONFIG_DATA,
3027 1,
3028 &PortData
3029 );
3030 ASSERT_EFI_ERROR (Status);
3031 if ((PortData == WPCN381U_CHIP_ID) || (PortData == WDCP376_CHIP_ID)) {
3032 mPlatformNvsAreaProtocol.Area->WPCN381U = PLATFORM_NVS_DEVICE_ENABLE;
3033 }
3034 }
3035 }
3036
3037 //
3038 // Enable APIC
3039 //
3040 mPlatformNvsAreaProtocol.Area->ApicEnable = PLATFORM_NVS_DEVICE_ENABLE;
3041
3042 //
3043 // EC function
3044 //
3045 if (PcdGetBool (PcdEcPresent) == TRUE) {
3046 mPlatformNvsAreaProtocol.Area->EcAvailable = TRUE;
3047 mPlatformNvsAreaProtocol.Area->EcLowPowerMode = mSystemConfiguration.EcLowPowerMode;
3048 mPlatformNvsAreaProtocol.Area->EcSmiGpioPin = PcdGet32(PcdEcSmiGpio);
3049 mPlatformNvsAreaProtocol.Area->EcLowPowerModeGpioPin = PcdGet32(PcdEcLowPowerExitGpio);
3050 } else {
3051 mPlatformNvsAreaProtocol.Area->EcAvailable = FALSE;
3052 mPlatformNvsAreaProtocol.Area->EcLowPowerMode = 0;
3053 mPlatformNvsAreaProtocol.Area->EcSmiGpioPin = 0;
3054 mPlatformNvsAreaProtocol.Area->EcLowPowerModeGpioPin = 0;
3055 }
3056 mPlatformNvsAreaProtocol.Area->EnableVoltageMargining = PcdGetBool (PcdEnableVoltageMargining);
3057
3058 //
3059 // Comms Hub Support Enable/Disable
3060 //
3061 mPlatformNvsAreaProtocol.Area->CommsHubEnable = mMeSetup.CommsHubEnable;
3062
3063 mPlatformNvsAreaProtocol.Area->IuerButtonEnable = SaSetup.IuerButtonEnable;
3064
3065 //
3066 // Enable 10sec Power Button Override only if CS is enabled.
3067 //
3068 if ((mSystemConfiguration.LowPowerS0Idle == 1) && (mSystemConfiguration.TenSecondPowerButtonEnable == 1)) {
3069 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable |= BIT0; // Enable 10sec Power Button OVR.
3070 } else {
3071 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable &= ~(BIT0); // Disable 10sec Power Button OVR.
3072 }
3073 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable |= (SaSetup.SlateIndicatorRT << 3);
3074 mPlatformNvsAreaProtocol.Area->TenSecondPowerButtonEnable |= (SaSetup.DockIndicatorRT << 4);
3075 mPlatformNvsAreaProtocol.Area->IuerConvertibleEnable = SaSetup.IuerConvertibleEnable;
3076 mPlatformNvsAreaProtocol.Area->IuerDockEnable = SaSetup.IuerDockEnable;
3077
3078 mPlatformNvsAreaProtocol.Area->VirtualGpioButtonSxBitmask = 0x00;
3079 mPlatformNvsAreaProtocol.Area->VirtualGpioButtonSxBitmask |= SaSetup.SlateIndicatorSx << 6;
3080 mPlatformNvsAreaProtocol.Area->VirtualGpioButtonSxBitmask |= SaSetup.DockIndicatorSx << 7;
3081
3082 //
3083 // Low Power S0 Idle - Enabled/Disabled
3084 //
3085 mPlatformNvsAreaProtocol.Area->LowPowerS0Idle = mSystemConfiguration.LowPowerS0Idle;
3086
3087 //
3088 //Disable PEP constarints for devices which are not present in CNL-H platform
3089 //
3090 if ((PchGeneration () == CNL_PCH) && IsPchH ()) {
3091 mSystemConfiguration.PepEmmc = 0;
3092 mSystemConfiguration.PepI2c4 = 0;
3093 }
3094 //
3095 // Micro-PEP constraint list
3096 //
3097 mPlatformNvsAreaProtocol.Area->LowPowerS0IdleConstraint = ( mSystemConfiguration.PepSataContraints << 0) | // Bit[1:0] - Storage (0:None, 1:Storage Controller, 2:Raid)
3098 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexUart0] && mSystemConfiguration.PepUart) << 2) | // Bit[2] - En/Dis UART0
3099 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexUart1] && mSystemConfiguration.PepUart) << 3) | // Bit[3] - En/Dis UART1
3100 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexI2C0] && mSystemConfiguration.PepI2c0) << 5) | // Bit[5] - En/Dis I2C0
3101 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexI2C1] && mSystemConfiguration.PepI2c1) << 6) | // Bit[6] - En/Dis I2C1
3102 ( mSystemConfiguration.PepXhci << 7) | // Bit[7] - En/Dis XHCI
3103 (((mPchSetup.PchHdAudio && mSystemConfiguration.PepAudio)) << 8) | // Bit[8] - En/Dis HD Audio (includes ADSP)
3104 ( mSystemConfiguration.PepGfx << 9) | // Bit[9] - En/Dis GFX
3105 ( mSystemConfiguration.PepCpu << 10) | // Bit[10] - En/Dis CPU
3106 ((mPchSetup.PchScsEmmcEnabled && mSystemConfiguration.PepEmmc) << 11) | // Bit[11] - En/Dis EMMC
3107 ((mPchSetup.PchScsSdCardEnabled && mSystemConfiguration.PepSdxc) << 12) | // Bit[12] - En/Dis SDXC
3108 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexI2C2] && mSystemConfiguration.PepI2c2) << 13) | // Bit[13] - En/Dis I2C2
3109 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexI2C3] && mSystemConfiguration.PepI2c3) << 14) | // Bit[14] - En/Dis I2C3
3110 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexI2C4] && mSystemConfiguration.PepI2c4) << 15) | // Bit[15] - En/Dis I2C4
3111 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexI2C5] && mSystemConfiguration.PepI2c5) << 16) | // Bit[16] - En/Dis I2C5
3112 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexUart2] && mSystemConfiguration.PepUart) << 17) | // Bit[17] - En/Dis UART2
3113 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexSpi0] && mSystemConfiguration.PepSpi) << 18) | // Bit[18] - En/Dis SPI0
3114 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexSpi1] && mSystemConfiguration.PepSpi) << 19) | // Bit[19] - En/Dis SPI1
3115 ((mPchSetup.PchSerialIoDevice[PchSerialIoIndexSpi2] && mSystemConfiguration.PepSpi) << 20) | // Bit[20] -En/Dis SPI2
3116 ((SaSetup.SaIpuEnable && mSystemConfiguration.PepIpu) << 21) | // Bit[21] - En/Dis IPU0
3117 ( mSystemConfiguration.PepCsme << 22); // Bit[22] -En/Dis CSME
3118
3119
3120 DEBUG((DEBUG_INFO, "ACPI NVS, LowPowerS0IdleConstraint(Micro-pep constraints) = 0x%X \n", mPlatformNvsAreaProtocol.Area->LowPowerS0IdleConstraint ));
3121
3122 //
3123 // Disable / Enable PEP F1 constraints for WiGig device based on user settings
3124 //
3125 mPlatformNvsAreaProtocol.Area->PepWiGigF1 = mSystemConfiguration.PepWiGigF1;
3126
3127
3128 //
3129 // Update SATA port connect status for PEPD. This needs to be done only when CS is enabled.
3130 // Note: We cannot do this inside ASL code since SATA device has a dependency to PEPD device and PEPD device
3131 // needs to know SATA device connect status. Deadlock situation between SATA and PEPD.
3132 //
3133 if (mSystemConfiguration.LowPowerS0Idle == 1) {
3134 //
3135 // Read SATA device PCS field for SATA Port Present status bits if SATA Controller is present.
3136 //
3137 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, PCI_VENDOR_ID_OFFSET)) != 0xFFFF) {
3138 mPlatformNvsAreaProtocol.Area->SataPortState = PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_SATA_CFG_PCS + 2));
3139 }
3140 }
3141
3142 mPlatformNvsAreaProtocol.Area->CSNotifyEC = mSystemConfiguration.CSNotifyEC;
3143 mPlatformNvsAreaProtocol.Area->CSDebugLightEC = mSystemConfiguration.CSDebugLightEC;
3144
3145 mPlatformNvsAreaProtocol.Area->PL1LimitCS = mSystemConfiguration.PL1LimitCS;
3146 mPlatformNvsAreaProtocol.Area->PL1LimitCSValue = mSystemConfiguration.PL1LimitCSValue;
3147
3148 mPlatformNvsAreaProtocol.Area->SDS0 = mSystemConfiguration.PchI2c0SensorDevice;
3149 mPlatformNvsAreaProtocol.Area->SDM0 = mSystemConfiguration.PchI2c0SensorIrqMode;
3150 mPlatformNvsAreaProtocol.Area->TPDB = mSystemConfiguration.PchI2c0TouchpadBusAddress;
3151 mPlatformNvsAreaProtocol.Area->TPDH = mSystemConfiguration.PchI2c0TouchpadHidAddress;
3152 mPlatformNvsAreaProtocol.Area->TPDS = mSystemConfiguration.PchI2c0TouchpadSpeed;
3153
3154 mPlatformNvsAreaProtocol.Area->SDS1 = mSystemConfiguration.PchI2c1SensorDevice;
3155 mPlatformNvsAreaProtocol.Area->SDM1 = mSystemConfiguration.PchI2c1SensorIrqMode;
3156 mPlatformNvsAreaProtocol.Area->TPLB = mSystemConfiguration.PchI2c1TouchpanelBusAddress;
3157 mPlatformNvsAreaProtocol.Area->TPLH = mSystemConfiguration.PchI2c1TouchpanelHidAddress;
3158 mPlatformNvsAreaProtocol.Area->TPLS = mSystemConfiguration.PchI2c1TouchpanelSpeed;
3159
3160 mPlatformNvsAreaProtocol.Area->SDS2 = mSystemConfiguration.PchI2c2SensorDevice;
3161 mPlatformNvsAreaProtocol.Area->SDM2 = mSystemConfiguration.PchI2c2SensorIrqMode;
3162 mPlatformNvsAreaProtocol.Area->TPDB = mSystemConfiguration.PchI2c2TouchpadBusAddress;
3163 mPlatformNvsAreaProtocol.Area->TPDH = mSystemConfiguration.PchI2c2TouchpadHidAddress;
3164 mPlatformNvsAreaProtocol.Area->TPDS = mSystemConfiguration.PchI2c2TouchpadSpeed;
3165
3166 mPlatformNvsAreaProtocol.Area->SDS3 = mSystemConfiguration.PchI2c3SensorDevice;
3167 mPlatformNvsAreaProtocol.Area->SDS4 = mSystemConfiguration.PchI2c4SensorDevice;
3168 mPlatformNvsAreaProtocol.Area->SDS5 = mSystemConfiguration.PchI2c5SensorDevice;
3169
3170 //mPlatformNvsAreaProtocol.Area->SDS6 = mSystemConfiguration.PchSpi0SensorDevice;
3171 //mPlatformNvsAreaProtocol.Area->SDM6 = mSystemConfiguration.PchI2c0SensorIrqMode;
3172
3173 //
3174 // Get Mbp Hob
3175 //
3176 MbpHob = GetFirstGuidHob (&gMeBiosPayloadHobGuid);
3177 mPlatformNvsAreaProtocol.Area->SDS7 = mSystemConfiguration.PchSpi1SensorDevice;
3178 mPlatformNvsAreaProtocol.Area->SDM7 = mSystemConfiguration.PchSpi1SensorIrqMode;
3179
3180 mPlatformNvsAreaProtocol.Area->SDS9 = mSystemConfiguration.DiscreteBtModule;
3181 mPlatformNvsAreaProtocol.Area->SDM9 = mSystemConfiguration.DiscreteBtModuleIrqMode;
3182
3183 mPlatformNvsAreaProtocol.Area->WTVX = mSystemConfiguration.PchI2cWittVersion;
3184 mPlatformNvsAreaProtocol.Area->WITX = mSystemConfiguration.PchI2cWittDevice;
3185 mPlatformNvsAreaProtocol.Area->UTKX = mSystemConfiguration.PchUartUtkDevice;
3186 mPlatformNvsAreaProtocol.Area->GDBT = mPchSetup.PchGpioDebounce;
3187 mPlatformNvsAreaProtocol.Area->GPTD = mPchSetup.PchGpioTestDevices;
3188 mPlatformNvsAreaProtocol.Area->SPTD = mPchSetup.PchAdditionalSerialIoDevices;
3189
3190 //
3191 // UCMC support
3192 //
3193 UcmcGpioTable = (GPIO_INIT_CONFIG *)(UINTN)PcdGet32(PcdBoardUcmcGpioTable);
3194 UcmcGpioTableSize = (UINT16)PcdGet16(PcdBoardUcmcGpioTableSize);
3195 mPlatformNvsAreaProtocol.Area->UCSI = mPchSetup.PchUcsiUcmcDevice;
3196
3197 if (UcmcGpioTableSize) {
3198 ASSERT(UcmcGpioTableSize == 2);
3199
3200 mPlatformNvsAreaProtocol.Area->UcmcPort1Gpio = UcmcGpioTable[0].GpioPad;
3201 mPlatformNvsAreaProtocol.Area->UcmcPort2Gpio = UcmcGpioTable[1].GpioPad;
3202 }
3203
3204 //
3205 // Serial IO timing parameters
3206 //
3207 mPlatformNvsAreaProtocol.Area->USTP = mSystemConfiguration.PchSerialIoUseTimingParameters;
3208
3209 mPlatformNvsAreaProtocol.Area->SSH0 = mSystemConfiguration.PchSerialIoTimingSSH0; // [SSH0] SSCN-HIGH for I2C0
3210 mPlatformNvsAreaProtocol.Area->SSL0 = mSystemConfiguration.PchSerialIoTimingSSL0; // [SSL0] SSCN-LOW for I2C0
3211 mPlatformNvsAreaProtocol.Area->SSD0 = mSystemConfiguration.PchSerialIoTimingSSD0; // [SSD0] SSCN-HOLD for I2C0
3212 mPlatformNvsAreaProtocol.Area->FMH0 = mSystemConfiguration.PchSerialIoTimingFMH0; // [FMH0] FMCN-HIGH for I2C0
3213 mPlatformNvsAreaProtocol.Area->FML0 = mSystemConfiguration.PchSerialIoTimingFML0; // [FML0] FMCN-LOW for I2C0
3214 mPlatformNvsAreaProtocol.Area->FMD0 = mSystemConfiguration.PchSerialIoTimingFMD0; // [FMD0] FMCN-HOLD for I2C0
3215 mPlatformNvsAreaProtocol.Area->FPH0 = mSystemConfiguration.PchSerialIoTimingFPH0; // [FPH0] FPCN-HIGH for I2C0
3216 mPlatformNvsAreaProtocol.Area->FPL0 = mSystemConfiguration.PchSerialIoTimingFPL0; // [FPL0] FPCN-LOW for I2C0
3217 mPlatformNvsAreaProtocol.Area->FPD0 = mSystemConfiguration.PchSerialIoTimingFPD0; // [FPD0] FPCN-HOLD for I2C0
3218 mPlatformNvsAreaProtocol.Area->HMH0 = mSystemConfiguration.PchSerialIoTimingHMH0; // [HMH0] HMCN-HIGH for I2C0
3219 mPlatformNvsAreaProtocol.Area->HML0 = mSystemConfiguration.PchSerialIoTimingHML0; // [HML0] HMCN-LOW for I2C0
3220 mPlatformNvsAreaProtocol.Area->HMD0 = mSystemConfiguration.PchSerialIoTimingHMD0; // [HMD0] HMCN-HOLD for I2C0
3221
3222 mPlatformNvsAreaProtocol.Area->SSH1 = mSystemConfiguration.PchSerialIoTimingSSH1; // [SSH1] SSCN-HIGH for I2C1
3223 mPlatformNvsAreaProtocol.Area->SSL1 = mSystemConfiguration.PchSerialIoTimingSSL1; // [SSL1] SSCN-LOW for I2C1
3224 mPlatformNvsAreaProtocol.Area->SSD1 = mSystemConfiguration.PchSerialIoTimingSSD1; // [SSD1] SSCN-HOLD for I2C1
3225 mPlatformNvsAreaProtocol.Area->FMH1 = mSystemConfiguration.PchSerialIoTimingFMH1; // [FMH1] FMCN-HIGH for I2C1
3226 mPlatformNvsAreaProtocol.Area->FML1 = mSystemConfiguration.PchSerialIoTimingFML1; // [FML1] FMCN-LOW for I2C1
3227 mPlatformNvsAreaProtocol.Area->FMD1 = mSystemConfiguration.PchSerialIoTimingFMD1; // [FMD1] FMCN-HOLD for I2C1
3228 mPlatformNvsAreaProtocol.Area->FPH1 = mSystemConfiguration.PchSerialIoTimingFPH1; // [FPH1] FPCN-HIGH for I2C1
3229 mPlatformNvsAreaProtocol.Area->FPL1 = mSystemConfiguration.PchSerialIoTimingFPL1; // [FPL1] FPCN-LOW for I2C1
3230 mPlatformNvsAreaProtocol.Area->FPD1 = mSystemConfiguration.PchSerialIoTimingFPD1; // [FPD1] FPCN-HOLD for I2C1
3231 mPlatformNvsAreaProtocol.Area->HMH1 = mSystemConfiguration.PchSerialIoTimingHMH1; // [HMH1] HMCN-HIGH for I2C1
3232 mPlatformNvsAreaProtocol.Area->HML1 = mSystemConfiguration.PchSerialIoTimingHML1; // [HML1] HMCN-LOW for I2C1
3233 mPlatformNvsAreaProtocol.Area->HMD1 = mSystemConfiguration.PchSerialIoTimingHMD1; // [HMD1] HMCN-HOLD for I2C1
3234
3235 mPlatformNvsAreaProtocol.Area->SSH2 = mSystemConfiguration.PchSerialIoTimingSSH2; // [SSH2] SSCN-HIGH for I2C2
3236 mPlatformNvsAreaProtocol.Area->SSL2 = mSystemConfiguration.PchSerialIoTimingSSL2; // [SSL2] SSCN-LOW for I2C2
3237 mPlatformNvsAreaProtocol.Area->SSD2 = mSystemConfiguration.PchSerialIoTimingSSD2; // [SSD2] SSCN-HOLD for I2C2
3238 mPlatformNvsAreaProtocol.Area->FMH2 = mSystemConfiguration.PchSerialIoTimingFMH2; // [FMH2] FMCN-HIGH for I2C2
3239 mPlatformNvsAreaProtocol.Area->FML2 = mSystemConfiguration.PchSerialIoTimingFML2; // [FML2] FMCN-LOW for I2C2
3240 mPlatformNvsAreaProtocol.Area->FMD2 = mSystemConfiguration.PchSerialIoTimingFMD2; // [FMD2] FMCN-HOLD for I2C2
3241 mPlatformNvsAreaProtocol.Area->FPH2 = mSystemConfiguration.PchSerialIoTimingFPH2; // [FPH2] FPCN-HIGH for I2C2
3242 mPlatformNvsAreaProtocol.Area->FPL2 = mSystemConfiguration.PchSerialIoTimingFPL2; // [FPL2] FPCN-LOW for I2C2
3243 mPlatformNvsAreaProtocol.Area->FPD2 = mSystemConfiguration.PchSerialIoTimingFPD2; // [FPD2] FPCN-HOLD for I2C2
3244 mPlatformNvsAreaProtocol.Area->HMH2 = mSystemConfiguration.PchSerialIoTimingHMH2; // [HMH2] HMCN-HIGH for I2C2
3245 mPlatformNvsAreaProtocol.Area->HML2 = mSystemConfiguration.PchSerialIoTimingHML2; // [HML2] HMCN-LOW for I2C2
3246 mPlatformNvsAreaProtocol.Area->HMD2 = mSystemConfiguration.PchSerialIoTimingHMD2; // [HMD2] HMCN-HOLD for I2C2
3247
3248 mPlatformNvsAreaProtocol.Area->SSH3 = mSystemConfiguration.PchSerialIoTimingSSH3; // [SSH3] SSCN-HIGH for I2C3
3249 mPlatformNvsAreaProtocol.Area->SSL3 = mSystemConfiguration.PchSerialIoTimingSSL3; // [SSL3] SSCN-LOW for I2C3
3250 mPlatformNvsAreaProtocol.Area->SSD3 = mSystemConfiguration.PchSerialIoTimingSSD3; // [SSD3] SSCN-HOLD for I2C3
3251 mPlatformNvsAreaProtocol.Area->FMH3 = mSystemConfiguration.PchSerialIoTimingFMH3; // [FMH3] FMCN-HIGH for I2C3
3252 mPlatformNvsAreaProtocol.Area->FML3 = mSystemConfiguration.PchSerialIoTimingFML3; // [FML3] FMCN-LOW for I2C3
3253 mPlatformNvsAreaProtocol.Area->FMD3 = mSystemConfiguration.PchSerialIoTimingFMD3; // [FMD3] FMCN-HOLD for I2C3
3254 mPlatformNvsAreaProtocol.Area->FPH3 = mSystemConfiguration.PchSerialIoTimingFPH3; // [FPH3] FPCN-HIGH for I2C3
3255 mPlatformNvsAreaProtocol.Area->FPL3 = mSystemConfiguration.PchSerialIoTimingFPL3; // [FPL3] FPCN-LOW for I2C3
3256 mPlatformNvsAreaProtocol.Area->FPD3 = mSystemConfiguration.PchSerialIoTimingFPD3; // [FPD3] FPCN-HOLD for I2C3
3257 mPlatformNvsAreaProtocol.Area->HMH3 = mSystemConfiguration.PchSerialIoTimingHMH3; // [HMH3] HMCN-HIGH for I2C3
3258 mPlatformNvsAreaProtocol.Area->HML3 = mSystemConfiguration.PchSerialIoTimingHML3; // [HML3] HMCN-LOW for I2C3
3259 mPlatformNvsAreaProtocol.Area->HMD3 = mSystemConfiguration.PchSerialIoTimingHMD3; // [HMD3] HMCN-HOLD for I2C3
3260
3261 mPlatformNvsAreaProtocol.Area->SSH4 = mSystemConfiguration.PchSerialIoTimingSSH4; // [SSH4] SSCN-HIGH for I2C4
3262 mPlatformNvsAreaProtocol.Area->SSL4 = mSystemConfiguration.PchSerialIoTimingSSL4; // [SSL4] SSCN-LOW for I2C4
3263 mPlatformNvsAreaProtocol.Area->SSD4 = mSystemConfiguration.PchSerialIoTimingSSD4; // [SSD4] SSCN-HOLD for I2C4
3264 mPlatformNvsAreaProtocol.Area->FMH4 = mSystemConfiguration.PchSerialIoTimingFMH4; // [FMH4] FMCN-HIGH for I2C4
3265 mPlatformNvsAreaProtocol.Area->FML4 = mSystemConfiguration.PchSerialIoTimingFML4; // [FML4] FMCN-LOW for I2C4
3266 mPlatformNvsAreaProtocol.Area->FMD4 = mSystemConfiguration.PchSerialIoTimingFMD4; // [FMD4] FMCN-HOLD for I2C4
3267 mPlatformNvsAreaProtocol.Area->FPH4 = mSystemConfiguration.PchSerialIoTimingFPH4; // [FPH4] FPCN-HIGH for I2C4
3268 mPlatformNvsAreaProtocol.Area->FPL4 = mSystemConfiguration.PchSerialIoTimingFPL4; // [FPL4] FPCN-LOW for I2C4
3269 mPlatformNvsAreaProtocol.Area->FPD4 = mSystemConfiguration.PchSerialIoTimingFPD4; // [FPD4] FPCN-HOLD for I2C4
3270 mPlatformNvsAreaProtocol.Area->HMH4 = mSystemConfiguration.PchSerialIoTimingHMH4; // [HMH4] HMCN-HIGH for I2C4
3271 mPlatformNvsAreaProtocol.Area->HML4 = mSystemConfiguration.PchSerialIoTimingHML4; // [HML4] HMCN-LOW for I2C4
3272 mPlatformNvsAreaProtocol.Area->HMD4 = mSystemConfiguration.PchSerialIoTimingHMD4; // [HMD4] HMCN-HOLD for I2C4
3273
3274 mPlatformNvsAreaProtocol.Area->SSH5 = mSystemConfiguration.PchSerialIoTimingSSH5; // [SSH5] SSCN-HIGH for I2C5
3275 mPlatformNvsAreaProtocol.Area->SSL5 = mSystemConfiguration.PchSerialIoTimingSSL5; // [SSL5] SSCN-LOW for I2C5
3276 mPlatformNvsAreaProtocol.Area->SSD5 = mSystemConfiguration.PchSerialIoTimingSSD5; // [SSD5] SSCN-HOLD for I2C5
3277 mPlatformNvsAreaProtocol.Area->FMH5 = mSystemConfiguration.PchSerialIoTimingFMH5; // [FMH5] FMCN-HIGH for I2C5
3278 mPlatformNvsAreaProtocol.Area->FML5 = mSystemConfiguration.PchSerialIoTimingFML5; // [FML5] FMCN-LOW for I2C5
3279 mPlatformNvsAreaProtocol.Area->FMD5 = mSystemConfiguration.PchSerialIoTimingFMD5; // [FMD5] FMCN-HOLD for I2C5
3280 mPlatformNvsAreaProtocol.Area->FPH5 = mSystemConfiguration.PchSerialIoTimingFPH5; // [FPH5] FPCN-HIGH for I2C5
3281 mPlatformNvsAreaProtocol.Area->FPL5 = mSystemConfiguration.PchSerialIoTimingFPL5; // [FPL5] FPCN-LOW for I2C5
3282 mPlatformNvsAreaProtocol.Area->FPD5 = mSystemConfiguration.PchSerialIoTimingFPD5; // [FPD5] FPCN-HOLD for I2C5
3283 mPlatformNvsAreaProtocol.Area->HMH5 = mSystemConfiguration.PchSerialIoTimingHMH5; // [HMH5] HMCN-HIGH for I2C5
3284 mPlatformNvsAreaProtocol.Area->HML5 = mSystemConfiguration.PchSerialIoTimingHML5; // [HML5] HMCN-LOW for I2C5
3285 mPlatformNvsAreaProtocol.Area->HMD5 = mSystemConfiguration.PchSerialIoTimingHMD5; // [HMD5] HMCN-HOLD for I2C5
3286
3287 mPlatformNvsAreaProtocol.Area->M0C0 = mSystemConfiguration.PchSerialIoTimingM0C0; // [M0C0] M0D3 for I2C0
3288 mPlatformNvsAreaProtocol.Area->M1C0 = mSystemConfiguration.PchSerialIoTimingM1C0; // [M1C0] M1D3 for I2C0
3289 mPlatformNvsAreaProtocol.Area->M0C1 = mSystemConfiguration.PchSerialIoTimingM0C1; // [M0C1] M0D3 for I2C1
3290 mPlatformNvsAreaProtocol.Area->M1C1 = mSystemConfiguration.PchSerialIoTimingM1C1; // [M1C1] M1D3 for I2C1
3291 mPlatformNvsAreaProtocol.Area->M0C2 = mSystemConfiguration.PchSerialIoTimingM0C2; // [M0C2] M0D3 for I2C2
3292 mPlatformNvsAreaProtocol.Area->M1C2 = mSystemConfiguration.PchSerialIoTimingM1C2; // [M1C2] M1D3 for I2C2
3293 mPlatformNvsAreaProtocol.Area->M0C3 = mSystemConfiguration.PchSerialIoTimingM0C3; // [M0C3] M0D3 for I2C3
3294 mPlatformNvsAreaProtocol.Area->M1C3 = mSystemConfiguration.PchSerialIoTimingM1C3; // [M1C3] M1D3 for I2C3
3295 mPlatformNvsAreaProtocol.Area->M0C4 = mSystemConfiguration.PchSerialIoTimingM0C4; // [M0C4] M0D3 for I2C4
3296 mPlatformNvsAreaProtocol.Area->M1C4 = mSystemConfiguration.PchSerialIoTimingM1C4; // [M1C4] M1D3 for I2C4
3297 mPlatformNvsAreaProtocol.Area->M0C5 = mSystemConfiguration.PchSerialIoTimingM0C5; // [M0C5] M0D3 for I2C5
3298 mPlatformNvsAreaProtocol.Area->M1C5 = mSystemConfiguration.PchSerialIoTimingM1C5; // [M1C5] M1D3 for I2C5
3299 mPlatformNvsAreaProtocol.Area->M0C6 = mSystemConfiguration.PchSerialIoTimingM0C6; // [M0C6] M0D3 for SPI0
3300 mPlatformNvsAreaProtocol.Area->M1C6 = mSystemConfiguration.PchSerialIoTimingM1C6; // [M1C6] M1D3 for SPI0
3301 mPlatformNvsAreaProtocol.Area->M0C7 = mSystemConfiguration.PchSerialIoTimingM0C7; // [M0C7] M0D3 for SPI1
3302 mPlatformNvsAreaProtocol.Area->M1C7 = mSystemConfiguration.PchSerialIoTimingM1C7; // [M1C7] M1D3 for SPI1
3303 mPlatformNvsAreaProtocol.Area->M0C8 = mSystemConfiguration.PchSerialIoTimingM0C8; // [M0C8] M0D3 for SPI2
3304 mPlatformNvsAreaProtocol.Area->M1C8 = mSystemConfiguration.PchSerialIoTimingM1C8; // [M1C8] M1D3 for SPI2
3305 mPlatformNvsAreaProtocol.Area->M0C9 = mSystemConfiguration.PchSerialIoTimingM0C9; // [M0C9] M0D3 for UART0
3306 mPlatformNvsAreaProtocol.Area->M1C9 = mSystemConfiguration.PchSerialIoTimingM1C9; // [M1C9] M1D3 for UART0
3307 mPlatformNvsAreaProtocol.Area->M0CA = mSystemConfiguration.PchSerialIoTimingM0CA; // [M0CA] M0D3 for UART1
3308 mPlatformNvsAreaProtocol.Area->M1CA = mSystemConfiguration.PchSerialIoTimingM1CA; // [M1CA] M1D3 for UART1
3309 mPlatformNvsAreaProtocol.Area->M0CB = mSystemConfiguration.PchSerialIoTimingM0CB; // [M0CB] M0D3 for UART2
3310 mPlatformNvsAreaProtocol.Area->M1CB = mSystemConfiguration.PchSerialIoTimingM1CB; // [M1CB] M1D3 for UART2
3311
3312 mPlatformNvsAreaProtocol.Area->FingerPrintSleepGpio = PcdGet32 (PcdFingerPrintSleepGpio);
3313 mPlatformNvsAreaProtocol.Area->FingerPrintIrqGpio = PcdGet32 (PcdFingerPrintIrqGpio);
3314 mPlatformNvsAreaProtocol.Area->DiscreteGnssModuleResetGpio = PcdGet32 (PcdGnssResetGpio);
3315 mPlatformNvsAreaProtocol.Area->DiscreteBtModuleRfKillGpio = PcdGet32 (PcdBtRfKillGpio);
3316 mPlatformNvsAreaProtocol.Area->DiscreteBtModuleIrqGpio = PcdGet32 (PcdBtIrqGpio);
3317 mPlatformNvsAreaProtocol.Area->TouchpadIrqGpio = PcdGet32 (PcdTouchpadIrqGpio);
3318 mPlatformNvsAreaProtocol.Area->TouchpanelIrqGpio = PcdGet32 (PcdTouchpanelIrqGpio);
3319 mPlatformNvsAreaProtocol.Area->DiscreteBtUartSupport = PcdGetBool (PcdDiscreteBtUartSupport);
3320
3321 mPlatformNvsAreaProtocol.Area->Revision = PLATFORM_NVS_AREA_REVISION_1; // for TPM related fields
3322 mPlatformNvsAreaProtocol.Area->Ps2MouseEnable = IsPs2MouseConnected ();
3323 mPlatformNvsAreaProtocol.Area->Ps2KbMsEnable = mSystemConfiguration.Ps2KbMsEnable;
3324
3325 //
3326 // Feature Specific RVP Details
3327 //
3328 mPlatformNvsAreaProtocol.Area->UsbTypeCSupport = PcdGetBool (PcdUsbTypeCSupport);
3329 mPlatformNvsAreaProtocol.Area->PcdTsOnDimmTemperature = PcdGetBool (PcdTsOnDimmTemperature);
3330 mPlatformNvsAreaProtocol.Area->PcdRealBattery1Control = PcdGet8 (PcdRealBattery1Control);
3331 mPlatformNvsAreaProtocol.Area->PcdRealBattery2Control = PcdGet8 (PcdRealBattery2Control);
3332 mPlatformNvsAreaProtocol.Area->PcdMipiCamSensor = PcdGetBool (PcdMipiCamSensor);
3333 mPlatformNvsAreaProtocol.Area->PcdNCT6776FCOM = PcdGetBool (PcdNCT6776FCOM);
3334 mPlatformNvsAreaProtocol.Area->PcdNCT6776FSIO = PcdGetBool (PcdNCT6776FSIO);
3335 mPlatformNvsAreaProtocol.Area->PcdNCT6776FHWMON = PcdGetBool (PcdNCT6776FHWMON);
3336 mPlatformNvsAreaProtocol.Area->PcdH8S2113SIO = PcdGetBool (PcdH8S2113SIO);
3337 mPlatformNvsAreaProtocol.Area->PcdPowerParticipant = PcdGetBool (PcdPowerParticipant);
3338 mPlatformNvsAreaProtocol.Area->PcdSmcRuntimeSciPin = PcdGet32 (PcdSmcRuntimeSciPin);
3339 mPlatformNvsAreaProtocol.Area->PcdConvertableDockSupport = PcdGetBool (PcdConvertableDockSupport);
3340 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF3Support = PcdGet8 (PcdEcHotKeyF3Support);
3341 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF4Support = PcdGet8 (PcdEcHotKeyF4Support);
3342 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF5Support = PcdGet8 (PcdEcHotKeyF5Support);
3343 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF6Support = PcdGet8 (PcdEcHotKeyF6Support);
3344 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF7Support = PcdGet8 (PcdEcHotKeyF7Support);
3345 mPlatformNvsAreaProtocol.Area->PcdEcHotKeyF8Support = PcdGet8 (PcdEcHotKeyF8Support);
3346 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonVolumeUpSupport = PcdGetBool (PcdVirtualButtonVolumeUpSupport);
3347 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonVolumeDownSupport = PcdGetBool (PcdVirtualButtonVolumeDownSupport);
3348 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonHomeButtonSupport = PcdGetBool (PcdVirtualButtonHomeButtonSupport);
3349 mPlatformNvsAreaProtocol.Area->PcdVirtualButtonRotationLockSupport = PcdGetBool (PcdVirtualButtonRotationLockSupport);
3350 mPlatformNvsAreaProtocol.Area->PcdSlateModeSwitchSupport = PcdGetBool (PcdSlateModeSwitchSupport);
3351 mPlatformNvsAreaProtocol.Area->PcdAcDcAutoSwitchSupport = PcdGetBool (PcdAcDcAutoSwitchSupport);
3352 mPlatformNvsAreaProtocol.Area->PcdPmPowerButtonGpioPin = PcdGet32 (PcdPmPowerButtonGpioPin);
3353 mPlatformNvsAreaProtocol.Area->PcdAcpiEnableAllButtonSupport = PcdGetBool (PcdAcpiEnableAllButtonSupport);
3354 mPlatformNvsAreaProtocol.Area->PcdAcpiHidDriverButtonSupport = PcdGetBool (PcdAcpiHidDriverButtonSupport);
3355 mPlatformNvsAreaProtocol.Area->PcdBatteryPresent = PcdGet8 (PcdBatteryPresent);
3356
3357 //
3358 // Always report PS2MouseEnable for non-EC board
3359 //
3360 if (mPlatformNvsAreaProtocol.Area->EcAvailable == PLATFORM_NVS_DEVICE_DISABLE) {
3361 mPlatformNvsAreaProtocol.Area->Ps2MouseEnable = 1;
3362 }
3363
3364
3365 mPlatformNvsAreaProtocol.Area->UsbSensorHub = mSystemConfiguration.UsbSensorHub;
3366
3367 //
3368 // MipiCam sensor configuration
3369 //
3370 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic0 = mSystemConfiguration.MipiCam_ControlLogic0;
3371 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic1 = mSystemConfiguration.MipiCam_ControlLogic1;
3372 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic2 = mSystemConfiguration.MipiCam_ControlLogic2;
3373 mPlatformNvsAreaProtocol.Area->MipiCamControlLogic3 = mSystemConfiguration.MipiCam_ControlLogic3;
3374 mPlatformNvsAreaProtocol.Area->MipiCamLink0Enabled = mSystemConfiguration.MipiCam_Link0;
3375 mPlatformNvsAreaProtocol.Area->MipiCamLink1Enabled = mSystemConfiguration.MipiCam_Link1;
3376 mPlatformNvsAreaProtocol.Area->MipiCamLink2Enabled = mSystemConfiguration.MipiCam_Link2;
3377 mPlatformNvsAreaProtocol.Area->MipiCamLink3Enabled = mSystemConfiguration.MipiCam_Link3;
3378
3379 mPlatformNvsAreaProtocol.Area->MipiCamLanesClkDiv = mSystemConfiguration.MipiCam_LanesClkDiv;
3380
3381 // MipiCam Control Logic 0 specific
3382 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Version = 1;
3383 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Type = mSystemConfiguration.MipiCam_ControlLogic0_Type;
3384 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic0_CrdVersion;
3385 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_InputClock = mSystemConfiguration.MipiCam_ControlLogic0_InputClock;
3386 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic0_GpioPinsEnabled;
3387 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_I2cBus = mSystemConfiguration.MipiCam_ControlLogic0_I2cChannel;
3388 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic0_I2cAddress;
3389 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Pld = mSystemConfiguration.MipiCam_ControlLogic0_Pld;
3390 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled1FlashMaxCurrent;
3391 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled1TorchMaxCurrent;
3392 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled2FlashMaxCurrent;
3393 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic0_Wled2TorchMaxCurrent;
3394 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic0_SubPlatformId;
3395 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic0_Wled1Type;
3396 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic0_Wled2Type;
3397 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic0_PchClockSource;
3398
3399 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
3400 if (Index < mSystemConfiguration.MipiCam_ControlLogic0_GpioPinsEnabled) {
3401 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioGroupPadNumber[Index];
3402 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioGroupNumber[Index];
3403 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioFunction[Index];
3404 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioActiveValue[Index];
3405 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic0_GpioInitialValue[Index];
3406 } else {
3407 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupPadNumber[Index] = 0;
3408 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioGroupNumber[Index] = 0;
3409 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioFunction[Index] = 0;
3410 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioActiveValue[Index] = 1;
3411 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic0_GpioInitialValue[Index] = 0;
3412 }
3413 }
3414
3415 // MipiCam Control Logic 1 specific
3416 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Version = 1;
3417 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Type = mSystemConfiguration.MipiCam_ControlLogic1_Type;
3418 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic1_CrdVersion;
3419 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_InputClock = mSystemConfiguration.MipiCam_ControlLogic1_InputClock;
3420 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic1_GpioPinsEnabled;
3421 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_I2cBus = mSystemConfiguration.MipiCam_ControlLogic1_I2cChannel;
3422 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic1_I2cAddress;
3423 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Pld = mSystemConfiguration.MipiCam_ControlLogic1_Pld;
3424 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled1FlashMaxCurrent;
3425 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled1TorchMaxCurrent;
3426 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled2FlashMaxCurrent;
3427 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic1_Wled2TorchMaxCurrent;
3428 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic1_SubPlatformId;
3429 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic1_Wled1Type;
3430 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic1_Wled2Type;
3431 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic1_PchClockSource;
3432
3433 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
3434 if (Index < mSystemConfiguration.MipiCam_ControlLogic1_GpioPinsEnabled) {
3435 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioGroupPadNumber[Index];
3436 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioGroupNumber[Index];
3437 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioFunction[Index];
3438 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioActiveValue[Index];
3439 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic1_GpioInitialValue[Index];
3440 } else {
3441 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupPadNumber[Index] = 0;
3442 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioGroupNumber[Index] = 0;
3443 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioFunction[Index] = 0;
3444 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioActiveValue[Index] = 1;
3445 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic1_GpioInitialValue[Index] = 0;
3446 }
3447 }
3448
3449 // MipiCam Control Logic 2 specific
3450 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Version = 1;
3451 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Type = mSystemConfiguration.MipiCam_ControlLogic2_Type;
3452 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic2_CrdVersion;
3453 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_InputClock = mSystemConfiguration.MipiCam_ControlLogic2_InputClock;
3454 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic2_GpioPinsEnabled;
3455 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_I2cBus = mSystemConfiguration.MipiCam_ControlLogic2_I2cChannel;
3456 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic2_I2cAddress;
3457 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Pld = mSystemConfiguration.MipiCam_ControlLogic2_Pld;
3458 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled1FlashMaxCurrent;
3459 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled1TorchMaxCurrent;
3460 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled2FlashMaxCurrent;
3461 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic2_Wled2TorchMaxCurrent;
3462 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic2_SubPlatformId;
3463 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic2_Wled1Type;
3464 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic2_Wled2Type;
3465 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic2_PchClockSource;
3466
3467 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
3468 if (Index < mSystemConfiguration.MipiCam_ControlLogic2_GpioPinsEnabled) {
3469 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioGroupPadNumber[Index];
3470 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioGroupNumber[Index];
3471 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioFunction[Index];
3472 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioActiveValue[Index];
3473 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic2_GpioInitialValue[Index];
3474 } else {
3475 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupPadNumber[Index] = 0;
3476 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioGroupNumber[Index] = 0;
3477 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioFunction[Index] = 0;
3478 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioActiveValue[Index] = 1;
3479 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic2_GpioInitialValue[Index] = 0;
3480 }
3481 }
3482
3483 // MipiCam Control Logic 3 specific
3484 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Version = 1;
3485 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Type = mSystemConfiguration.MipiCam_ControlLogic3_Type;
3486 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_CrdVersion = mSystemConfiguration.MipiCam_ControlLogic3_CrdVersion;
3487 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_InputClock = mSystemConfiguration.MipiCam_ControlLogic3_InputClock;
3488 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioPinsEnabled = mSystemConfiguration.MipiCam_ControlLogic3_GpioPinsEnabled;
3489 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_I2cBus = mSystemConfiguration.MipiCam_ControlLogic3_I2cChannel;
3490 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_I2cAddress = mSystemConfiguration.MipiCam_ControlLogic3_I2cAddress;
3491 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Pld = mSystemConfiguration.MipiCam_ControlLogic3_Pld;
3492 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled1FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled1FlashMaxCurrent;
3493 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled1TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled1TorchMaxCurrent;
3494 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled2FlashMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled2FlashMaxCurrent;
3495 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled2TorchMaxCurrent = mSystemConfiguration.MipiCam_ControlLogic3_Wled2TorchMaxCurrent;
3496 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_SubPlatformId = mSystemConfiguration.MipiCam_ControlLogic3_SubPlatformId;
3497 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled1Type = mSystemConfiguration.MipiCam_ControlLogic3_Wled1Type;
3498 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_Wled2Type = mSystemConfiguration.MipiCam_ControlLogic3_Wled2Type;
3499 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_PchClockSource = mSystemConfiguration.MipiCam_ControlLogic3_PchClockSource;
3500
3501 for (Index = 0; Index < MIPICAM_GPIO_COUNT; Index++) {
3502 if (Index < mSystemConfiguration.MipiCam_ControlLogic3_GpioPinsEnabled) {
3503 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupPadNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioGroupPadNumber[Index];
3504 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupNumber[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioGroupNumber[Index];
3505 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioFunction[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioFunction[Index];
3506 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioActiveValue[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioActiveValue[Index];
3507 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioInitialValue[Index] = mSystemConfiguration.MipiCam_ControlLogic3_GpioInitialValue[Index];
3508 } else {
3509 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupPadNumber[Index] = 0;
3510 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioGroupNumber[Index] = 0;
3511 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioFunction[Index] = 0;
3512 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioActiveValue[Index] = 1;
3513 mPlatformNvsAreaProtocol.Area->MipiCamCtrlLogic3_GpioInitialValue[Index] = 0;
3514 }
3515 }
3516
3517 // MipiCam Link0 specific
3518 mPlatformNvsAreaProtocol.Area->MipiCamLink0SensorModel = mSystemConfiguration.MipiCam_Link0_SensorModel;
3519 mPlatformNvsAreaProtocol.Area->MipiCamLink0Pld = mSystemConfiguration.MipiCam_Link0_CameraPhysicalLocation;
3520 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3521 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
3522 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link0_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3523 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink0ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink0ModuleName));
3524 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3525 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link0_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
3526 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink0UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink0UserHid));
3527 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link0_I2cDevicesEnabled;
3528 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cBus = mSystemConfiguration.MipiCam_Link0_I2cChannel;
3529
3530 // MipiCam Link0 I2C Devices
3531 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
3532 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link0_I2cAddress[Index];
3533 mPlatformNvsAreaProtocol.Area->MipiCamLink0I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link0_I2cDeviceType[Index];
3534 }
3535
3536 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_Version = 1;
3537 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_CrdVersion = mSystemConfiguration.MipiCam_Link0_DriverData_CrdVersion;
3538 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_LinkUsed = 3;
3539 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_LaneUsed = mSystemConfiguration.MipiCam_Link0_DriverData_LaneUsed;
3540 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_EepromType = mSystemConfiguration.MipiCam_Link0_DriverData_EepromType;
3541 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_VcmType = mSystemConfiguration.MipiCam_Link0_DriverData_VcmType;
3542 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_Mclk = mSystemConfiguration.MipiCam_Link0_DriverData_Mclk;
3543 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_ControlLogic = mSystemConfiguration.MipiCam_Link0_DriverData_ControlLogic;
3544 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_FlashSupport = mSystemConfiguration.MipiCam_Link0_DriverData_FlashSupport;
3545 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_PrivacyLed = mSystemConfiguration.MipiCam_Link0_DriverData_PrivacyLed;
3546 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_Degree = mSystemConfiguration.MipiCam_Link0_DriverData_Degree;
3547 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_PmicPosition = mSystemConfiguration.MipiCam_Link0_DriverData_PmicPosition;
3548 mPlatformNvsAreaProtocol.Area->MipiCamLink0DD_VoltageRail = mSystemConfiguration.MipiCam_Link0_DriverData_VoltageRail;
3549
3550 // MipiCam Link1 specific
3551 mPlatformNvsAreaProtocol.Area->MipiCamLink1SensorModel = mSystemConfiguration.MipiCam_Link1_SensorModel;
3552 mPlatformNvsAreaProtocol.Area->MipiCamLink1Pld = mSystemConfiguration.MipiCam_Link1_CameraPhysicalLocation;
3553 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3554 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
3555 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link1_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3556 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink1ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink1ModuleName));
3557 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3558 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link1_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
3559 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink1UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink1UserHid));
3560 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link1_I2cDevicesEnabled;
3561 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cBus = mSystemConfiguration.MipiCam_Link1_I2cChannel;
3562
3563 // MipiCam Link1 I2C Devices
3564 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
3565 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link1_I2cAddress[Index];
3566 mPlatformNvsAreaProtocol.Area->MipiCamLink1I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link1_I2cDeviceType[Index];
3567 }
3568 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_Version = 1;
3569 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_CrdVersion = mSystemConfiguration.MipiCam_Link1_DriverData_CrdVersion;
3570 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_LinkUsed = 6;
3571 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_LaneUsed = mSystemConfiguration.MipiCam_Link1_DriverData_LaneUsed;
3572 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_EepromType = mSystemConfiguration.MipiCam_Link1_DriverData_EepromType;
3573 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_VcmType = mSystemConfiguration.MipiCam_Link1_DriverData_VcmType;
3574 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_Mclk = mSystemConfiguration.MipiCam_Link1_DriverData_Mclk;
3575 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_ControlLogic = mSystemConfiguration.MipiCam_Link1_DriverData_ControlLogic;
3576 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_FlashSupport = mSystemConfiguration.MipiCam_Link1_DriverData_FlashSupport;
3577 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_PrivacyLed = mSystemConfiguration.MipiCam_Link1_DriverData_PrivacyLed;
3578 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_Degree = mSystemConfiguration.MipiCam_Link1_DriverData_Degree;
3579 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_PmicPosition = mSystemConfiguration.MipiCam_Link1_DriverData_PmicPosition;
3580 mPlatformNvsAreaProtocol.Area->MipiCamLink1DD_VoltageRail = mSystemConfiguration.MipiCam_Link1_DriverData_VoltageRail;
3581
3582 // MipiCam Link2 specific
3583 mPlatformNvsAreaProtocol.Area->MipiCamLink2SensorModel = mSystemConfiguration.MipiCam_Link2_SensorModel;
3584 mPlatformNvsAreaProtocol.Area->MipiCamLink2Pld = mSystemConfiguration.MipiCam_Link2_CameraPhysicalLocation;
3585 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3586 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
3587 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link2_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3588 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink2ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink2ModuleName));
3589 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3590 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link2_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
3591 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink2UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink2UserHid));
3592 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link2_I2cDevicesEnabled;
3593 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cBus = mSystemConfiguration.MipiCam_Link2_I2cChannel;
3594
3595 // MipiCam Link2 I2C Devices
3596 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
3597 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link2_I2cAddress[Index];
3598 mPlatformNvsAreaProtocol.Area->MipiCamLink2I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link2_I2cDeviceType[Index];
3599 }
3600 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_Version = 1;
3601 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_CrdVersion = mSystemConfiguration.MipiCam_Link2_DriverData_CrdVersion;
3602 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_LinkUsed = 9;
3603 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_LaneUsed = mSystemConfiguration.MipiCam_Link2_DriverData_LaneUsed;
3604 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_EepromType = mSystemConfiguration.MipiCam_Link2_DriverData_EepromType;
3605 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_VcmType = mSystemConfiguration.MipiCam_Link2_DriverData_VcmType;
3606 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_Mclk = mSystemConfiguration.MipiCam_Link2_DriverData_Mclk;
3607 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_ControlLogic = mSystemConfiguration.MipiCam_Link2_DriverData_ControlLogic;
3608 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_FlashSupport = mSystemConfiguration.MipiCam_Link2_DriverData_FlashSupport;
3609 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_PrivacyLed = mSystemConfiguration.MipiCam_Link2_DriverData_PrivacyLed;
3610 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_Degree = mSystemConfiguration.MipiCam_Link2_DriverData_Degree;
3611 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_PmicPosition = mSystemConfiguration.MipiCam_Link2_DriverData_PmicPosition;
3612 mPlatformNvsAreaProtocol.Area->MipiCamLink2DD_VoltageRail = mSystemConfiguration.MipiCam_Link2_DriverData_VoltageRail;
3613
3614 // MipiCam Link3 specific
3615 mPlatformNvsAreaProtocol.Area->MipiCamLink3SensorModel = mSystemConfiguration.MipiCam_Link3_SensorModel;
3616 mPlatformNvsAreaProtocol.Area->MipiCamLink3Pld = mSystemConfiguration.MipiCam_Link3_CameraPhysicalLocation;
3617 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3618 // Need to copy to temporary alligned buffer due to pack(1) in SetupVariables.h
3619 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link3_ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3620 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink3ModuleName, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink3ModuleName));
3621 ZeroMem(ModuleName, sizeof(UINT16) * MIPICAM_MODULE_NAME_LENGTH);
3622 CopyMem(ModuleName,mSystemConfiguration.MipiCam_Link3_UserHid, sizeof(UINT16) * MIPICAM_HID_LENGTH);
3623 UnicodeStrToAsciiStrS (ModuleName, (CHAR8 *) mPlatformNvsAreaProtocol.Area->MipiCamLink3UserHid, sizeof(mPlatformNvsAreaProtocol.Area->MipiCamLink3UserHid));
3624 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cDevicesEnabled = mSystemConfiguration.MipiCam_Link3_I2cDevicesEnabled;
3625 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cBus = mSystemConfiguration.MipiCam_Link3_I2cChannel;
3626
3627 // MipiCam Link3 I2C Devices
3628 for (Index = 0; Index < MIPICAM_I2C_DEVICES_COUNT; Index++) {
3629 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cAddrDev[Index] = mSystemConfiguration.MipiCam_Link3_I2cAddress[Index];
3630 mPlatformNvsAreaProtocol.Area->MipiCamLink3I2cDeviceType[Index] = mSystemConfiguration.MipiCam_Link3_I2cDeviceType[Index];
3631 }
3632 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_Version = 1;
3633 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_CrdVersion = mSystemConfiguration.MipiCam_Link3_DriverData_CrdVersion;
3634 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_LinkUsed = 7;
3635 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_LaneUsed = mSystemConfiguration.MipiCam_Link3_DriverData_LaneUsed;
3636 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_EepromType = mSystemConfiguration.MipiCam_Link3_DriverData_EepromType;
3637 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_VcmType = mSystemConfiguration.MipiCam_Link3_DriverData_VcmType;
3638 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_Mclk = mSystemConfiguration.MipiCam_Link3_DriverData_Mclk;
3639 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_ControlLogic = mSystemConfiguration.MipiCam_Link3_DriverData_ControlLogic;
3640 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_FlashSupport = mSystemConfiguration.MipiCam_Link3_DriverData_FlashSupport;
3641 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_PrivacyLed = mSystemConfiguration.MipiCam_Link3_DriverData_PrivacyLed;
3642 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_Degree = mSystemConfiguration.MipiCam_Link3_DriverData_Degree;
3643 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_PmicPosition = mSystemConfiguration.MipiCam_Link3_DriverData_PmicPosition;
3644 mPlatformNvsAreaProtocol.Area->MipiCamLink3DD_VoltageRail = mSystemConfiguration.MipiCam_Link3_DriverData_VoltageRail;
3645
3646 //
3647 // HDAudio Configuration
3648 //
3649 mPlatformNvsAreaProtocol.Area->I2SC = mPchSetup.PchHdAudioI2sCodecSelect;
3650 mPlatformNvsAreaProtocol.Area->I2SI = PcdGet32 (PcdHdaI2sCodecIrqGpio);
3651
3652 for (Index = 0; Index < HDAUDIO_PP_MODULES; Index++) {
3653 mPlatformNvsAreaProtocol.Area->HdaDspPpModuleMask |= (UINT32)(mPchSetup.PchHdAudioPostProcessingMod[Index] ? (1 << Index) : 0);
3654 }
3655 DEBUG((DEBUG_INFO,"HDA: HdaDspPpModuleMask [ADPM] = 0x%08x\n", mPlatformNvsAreaProtocol.Area->HdaDspPpModuleMask));
3656
3657 if (mPchSetup.PchHdAudioPostProcessingMod[29]){
3658 DEBUG((DEBUG_INFO,"HDA: AudioDSP Pre/Post-Processing custom module 'Alpha' enabled (BIT29)\n"));
3659
3660 CopyMem(LocalGuidString, mPchSetup.PchHdAudioPostProcessingModCustomGuid1, GUID_CHARS_NUMBER * sizeof(CHAR16));
3661 GuidStringToAcpiBuffer (LocalGuidString, &AcpiGuidPart1, &AcpiGuidPart2);
3662 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1Low = AcpiGuidPart1;
3663 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1High = AcpiGuidPart2;
3664 DEBUG((DEBUG_INFO,"HdaDspPpModCustomGuid1Low = 0x%016Lx\nHdaDspPpModCustomGuid2High = 0x%016Lx\n",
3665 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1Low, mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid1High));
3666 }
3667
3668 if (mPchSetup.PchHdAudioPostProcessingMod[30]){
3669 DEBUG((DEBUG_INFO,"HDA: AudioDSP Pre/Post-Processing custom module 'Beta' enabled (BIT30)\n"));
3670
3671 CopyMem(LocalGuidString, mPchSetup.PchHdAudioPostProcessingModCustomGuid2, GUID_CHARS_NUMBER * sizeof(CHAR16));
3672 GuidStringToAcpiBuffer (LocalGuidString, &AcpiGuidPart1, &AcpiGuidPart2);
3673 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2Low = AcpiGuidPart1;
3674 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2High = AcpiGuidPart2;
3675 DEBUG((DEBUG_INFO,"HdaDspPpModCustomGuid2Low = 0x%016Lx\nHdaDspPpModCustomGuid2High = 0x%016Lx\n",
3676 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2Low, mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid2High));
3677 }
3678
3679 if (mPchSetup.PchHdAudioPostProcessingMod[31]){
3680 DEBUG((DEBUG_INFO,"HDA: AudioDSP Pre/Post-Processing custom module 'Gamma' enabled (BIT31)\n"));
3681
3682 CopyMem(LocalGuidString, mPchSetup.PchHdAudioPostProcessingModCustomGuid3, GUID_CHARS_NUMBER * sizeof(CHAR16));
3683 GuidStringToAcpiBuffer (LocalGuidString, &AcpiGuidPart1, &AcpiGuidPart2);
3684 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3Low = AcpiGuidPart1;
3685 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3High = AcpiGuidPart2;
3686 DEBUG((DEBUG_INFO,"HdaDspPpModCustomGuid3Low = 0x%016Lx\nHdaDspPpModCustomGuid3High = 0x%016Lx\n",
3687 mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3Low, mPlatformNvsAreaProtocol.Area->HdaDspPpModCustomGuid3High));
3688 }
3689
3690 ///
3691 /// Get SaTcssHob HOB
3692 ///
3693 mSaTcssHob = (SA_TCSS_HOB *) GetFirstGuidHob (&gSaTcssHobGuid);
3694
3695 mPlatformNvsAreaProtocol.Area->PciDelayOptimizationEcr = mSystemConfiguration.PciDelayOptimizationEcr;
3696
3697 //
3698 // HID Event Filter Enable/Disable
3699 //
3700 mPlatformNvsAreaProtocol.Area->HidEventFilterEnable = mSystemConfiguration.HidEventFilterDriverEnable;
3701
3702
3703
3704 Status = gBS->InstallMultipleProtocolInterfaces (
3705 &Handle,
3706 &gPlatformNvsAreaProtocolGuid,
3707 &mPlatformNvsAreaProtocol,
3708 NULL
3709 );
3710 ASSERT_EFI_ERROR (Status);
3711
3712 //
3713 // Allocate NVS area for VBIOS. This is not currently used.
3714 //
3715 Status = AllocateMemoryBelow4G (
3716 EfiACPIMemoryNVS,
3717 0x10000,
3718 &mGfxNvsAddress
3719 );
3720 ASSERT_EFI_ERROR (Status);
3721
3722 //
3723 // Platform ACPI Tables
3724 //
3725 PublishAcpiTablesFromFv(gEfiAcpiTableStorageGuid);
3726
3727 //
3728 // Reference Code ACPI Tables
3729 //
3730 PublishAcpiTablesFromFv(gRcAcpiTableStorageGuid);
3731
3732 //
3733 // Install xHCI ACPI Table
3734 //
3735 InstallXhciAcpiTable ();
3736
3737 //
3738 // Save Acpi Setup Variables
3739 //
3740 Status = SetAcpiSetupVariables ();
3741 ASSERT_EFI_ERROR (Status);
3742
3743 //
3744 // Finished
3745 //
3746 return EFI_SUCCESS;
3747 }
3748
3749 /**
3750 Sort ordering of CPUs according to the priorities of cores and threads.
3751 ** ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core
3752
3753 @param[in] MpService The MP servicde protocol (used to retrievel MP info)
3754 @param[in] NumberOfCPUs Number of CPUs
3755 @param[in] NumberOfEnabledCPUs Number of Enabled CPUs.
3756
3757 @retval EFI_SUCCESS The driver installed without error.
3758
3759 **/
3760 EFI_STATUS
3761 SortCpuLocalApicInTable (
3762 IN EFI_MP_SERVICES_PROTOCOL *MpService,
3763 IN UINTN NumberOfCPUs,
3764 IN UINTN NumberOfEnabledCPUs
3765 )
3766 {
3767 EFI_PROCESSOR_INFORMATION *MpContext;
3768 UINTN BufferSize;
3769 UINT8 Index1;
3770 UINT8 Index;
3771 UINT8 CpuThreadIndex;
3772 UINTN BspIndex;
3773 UINT8 CurrProcessor;
3774 EFI_STATUS Status;
3775 UINT8 MaxCpuCore;
3776 UINT8 MaxCpuThread;
3777
3778 BufferSize = 0;
3779 MpContext = NULL;
3780 MaxCpuCore = 0;
3781 MaxCpuThread = 0;
3782
3783 Status = MpService->WhoAmI (
3784 MpService,
3785 &BspIndex
3786 );
3787
3788 //
3789 // Fill mCpuApicIdOrderTable
3790 //
3791 for (CurrProcessor = 0; CurrProcessor < NumberOfCPUs; CurrProcessor++) {
3792
3793 MpContext = AllocatePool (sizeof(EFI_PROCESSOR_INFORMATION));
3794 ASSERT (MpContext != NULL);
3795 Status = MpService->GetProcessorInfo (
3796 MpService,
3797 CurrProcessor,
3798 MpContext
3799 );
3800 ASSERT_EFI_ERROR (Status);
3801
3802 if (MpContext == NULL) {
3803 return Status;
3804 }
3805 mCpuApicIdOrderTable[CurrProcessor].ApicId = (UINT8) MpContext->ProcessorId;
3806 DEBUG((DEBUG_INFO, "The CurrProcessor 0x%x ApicId is 0x%x\n", CurrProcessor, mCpuApicIdOrderTable[CurrProcessor].ApicId));
3807 mCpuApicIdOrderTable[CurrProcessor].Flags = (MpContext->StatusFlag | PROCESSOR_ENABLED_BIT)? 1: 0;
3808 mCpuApicIdOrderTable[CurrProcessor].Package = (UINT8) MpContext->Location.Package;
3809 mCpuApicIdOrderTable[CurrProcessor].Die = (UINT8) 0;
3810 mCpuApicIdOrderTable[CurrProcessor].Core = (UINT8) MpContext->Location.Core;
3811 mCpuApicIdOrderTable[CurrProcessor].Thread = (UINT8) MpContext->Location.Thread;
3812
3813 if (MaxCpuThread < (UINT8) MpContext->Location.Thread) {
3814 MaxCpuThread = (UINT8) MpContext->Location.Thread;
3815 }
3816
3817 if (MaxCpuCore < (UINT8) MpContext->Location.Core) {
3818 MaxCpuCore = (UINT8) MpContext->Location.Core;
3819 }
3820 }
3821
3822 //
3823 // Do some statistics about the SBSP package
3824 //
3825 for (CurrProcessor = 0; CurrProcessor < NumberOfCPUs; CurrProcessor++) {
3826 if (CurrProcessor == BspIndex) {
3827 mSbspPackageInfo.BspApicId = mCpuApicIdOrderTable[CurrProcessor].ApicId;
3828 mSbspPackageInfo.PackageNo = mCpuApicIdOrderTable[CurrProcessor].Package;
3829 mSbspPackageInfo.TotalThreads = 0;
3830 mSbspPackageInfo.CoreNo = 0;
3831 mSbspPackageInfo.LogicalThreadNo = 0;
3832 }
3833 }
3834
3835 for (CurrProcessor = 0; CurrProcessor < NumberOfCPUs; CurrProcessor++) {
3836 if (mCpuApicIdOrderTable[CurrProcessor].Package == mSbspPackageInfo.PackageNo) {
3837 mSbspPackageInfo.TotalThreads++;
3838 if (mCpuApicIdOrderTable[CurrProcessor].Thread == 0) {
3839 mSbspPackageInfo.CoreNo++;
3840 } else {
3841 mSbspPackageInfo.LogicalThreadNo++;
3842 }
3843 }
3844 }
3845
3846 //
3847 // Output debug info
3848 //
3849 for (Index = 0; Index < NumberOfCPUs; Index++) {
3850 DEBUG((DEBUG_INFO, "Package = %x, Die = %x, Core = %x, Thread = %x, ApicId = %x\n", \
3851 mCpuApicIdOrderTable[Index].Package, \
3852 mCpuApicIdOrderTable[Index].Die, \
3853 mCpuApicIdOrderTable[Index].Core, \
3854 mCpuApicIdOrderTable[Index].Thread, \
3855 mCpuApicIdOrderTable[Index].ApicId));
3856 }
3857
3858 DEBUG((DEBUG_INFO, "MaxCpuCore = %x\n", MaxCpuCore));
3859 DEBUG((DEBUG_INFO, "MaxCpuThread = %x\n\n", MaxCpuThread));
3860 DEBUG((DEBUG_INFO, "mSbspPackageInfo.BspApicId = %x\n", mSbspPackageInfo.BspApicId));
3861 DEBUG((DEBUG_INFO, "mSbspPackageInfo.TotalThreads = %x\n", mSbspPackageInfo.TotalThreads));
3862 DEBUG((DEBUG_INFO, "mSbspPackageInfo.PackageNo = %x\n", mSbspPackageInfo.PackageNo));
3863 DEBUG((DEBUG_INFO, "mSbspPackageInfo.CoreNo = %x\n", mSbspPackageInfo.CoreNo));
3864 DEBUG((DEBUG_INFO, "mSbspPackageInfo.LogicalThreadNo = %x\n", mSbspPackageInfo.LogicalThreadNo));
3865
3866 //
3867 // First entry is always SBSP
3868 //
3869 CurrProcessor = 0;
3870 mCpuApicIdReorderTable[CurrProcessor].ApicId = mSbspPackageInfo.BspApicId;
3871 mCpuApicIdReorderTable[CurrProcessor].Package = mSbspPackageInfo.PackageNo;
3872 mCpuApicIdReorderTable[CurrProcessor].Flags = 1;
3873 CurrProcessor++;
3874
3875 //
3876 // Reorder Core and threads
3877 //
3878 for (Index1 = 0; Index1 <= MaxCpuThread; Index1 ++) {
3879 for (Index = 0; Index <= MaxCpuCore; Index++) {
3880 for (CpuThreadIndex = 0; CpuThreadIndex < NumberOfCPUs; CpuThreadIndex++) {
3881 if ((mCpuApicIdOrderTable[CpuThreadIndex].Package == mSbspPackageInfo.PackageNo) &&
3882 (mCpuApicIdOrderTable[CpuThreadIndex].Thread == Index1) &&
3883 (mCpuApicIdOrderTable[CpuThreadIndex].Core == Index) &&
3884 (mCpuApicIdOrderTable[CpuThreadIndex].ApicId != mCpuApicIdReorderTable[0].ApicId)) {
3885 mCpuApicIdReorderTable[CurrProcessor].ApicId = mCpuApicIdOrderTable[CpuThreadIndex].ApicId;
3886 mCpuApicIdReorderTable[CurrProcessor].Package = mSbspPackageInfo.PackageNo;
3887 mCpuApicIdReorderTable[CurrProcessor].Flags = mCpuApicIdOrderTable[CpuThreadIndex].Flags;
3888 CurrProcessor++;
3889 break;
3890 }
3891 }
3892 }
3893 }
3894
3895 //
3896 // Output debug info
3897 //
3898 for (Index = 0; Index < NumberOfCPUs; Index++) {
3899 DEBUG((DEBUG_INFO, "Index = %x, ApicId = %x, Package = %x\n", \
3900 Index, \
3901 mCpuApicIdReorderTable[Index].ApicId, \
3902 mCpuApicIdReorderTable[Index].Package));
3903 }
3904
3905 FreePool (MpContext);
3906
3907 return EFI_SUCCESS;
3908 }
3909
3910
3911 EFI_STATUS
3912 AppendCpuMapTableEntry (
3913 IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
3914 IN UINTN NumberOfCPUs,
3915 IN UINTN NumberOfEnabledCPUs,
3916 IN UINT8 LocalApicCounter
3917 )
3918 {
3919 if (LocalApicCounter < NumberOfCPUs) {
3920 AcpiLocalApic->Flags = mCpuApicIdReorderTable[LocalApicCounter].Flags;
3921 AcpiLocalApic->ApicId = mCpuApicIdReorderTable[LocalApicCounter].ApicId;
3922 //
3923 // Make AcpiProcessorIds 1-based, matching the ones in Processor() definitions
3924 //
3925 AcpiLocalApic->AcpiProcessorId = LocalApicCounter + 1;
3926 } else {
3927 AcpiLocalApic->Flags = 0;
3928 AcpiLocalApic->ApicId = 0xFF;
3929 //
3930 // Make AcpiProcessorIds 1-based, matching the ones in Processor() definitions
3931 //
3932 AcpiLocalApic->AcpiProcessorId = LocalApicCounter + 1;
3933 }
3934
3935 //
3936 // Display the results
3937 //
3938 DEBUG((DEBUG_INFO, "AcpiLocalApic: AcpiProcessorId=%x, ApicId=%x, Flags=%x\n", \
3939 AcpiLocalApic->AcpiProcessorId, \
3940 AcpiLocalApic->ApicId, \
3941 AcpiLocalApic->Flags));
3942
3943 return EFI_SUCCESS;
3944 }
3945
3946 /**
3947 I/O work flow to wait input buffer empty in given time.
3948
3949 @param[in] Timeout Wating time.
3950
3951 @retval EFI_TIMEOUT if input is still not empty in given time.
3952 @retval EFI_SUCCESS input is empty.
3953 **/
3954 EFI_STATUS
3955 WaitInputEmpty (
3956 IN UINTN Timeout
3957 )
3958 {
3959 UINTN Delay;
3960 UINT8 Data;
3961
3962 Delay = Timeout / 50;
3963
3964 do {
3965 Data = IoRead8 (KBC_CMD_STS_PORT);
3966
3967 //
3968 // Check keyboard controller status bit 1(input buffer status)
3969 //
3970 if ((Data & KBC_INPB) == 0) {
3971 break;
3972 }
3973
3974 gBS->Stall (50);
3975 Delay--;
3976 } while (Delay != 0);
3977
3978 if (Delay == 0) {
3979 return EFI_TIMEOUT;
3980 }
3981
3982 return EFI_SUCCESS;
3983 }
3984
3985 /**
3986 I/O work flow to wait output buffer full in given time.
3987
3988 @param[in] Timeout given time
3989
3990 @retval EFI_TIMEOUT output is not full in given time
3991 @retval EFI_SUCCESS output is full in given time.
3992 **/
3993 EFI_STATUS
3994 WaitOutputFull (
3995 IN UINTN Timeout
3996 )
3997 {
3998 UINTN Delay;
3999 UINT8 Data;
4000
4001 Delay = Timeout / 50;
4002
4003 do {
4004 Data = IoRead8 (KBC_CMD_STS_PORT);
4005
4006 //
4007 // Check keyboard controller status bit 0(output buffer status)
4008 // & bit5(output buffer for auxiliary device)
4009 //
4010 if ((Data & (KBC_OUTB | KBC_AUXB)) == (KBC_OUTB | KBC_AUXB)) {
4011 break;
4012 }
4013
4014 gBS->Stall (50);
4015 Delay--;
4016 } while (Delay != 0);
4017
4018 if (Delay == 0) {
4019 return EFI_TIMEOUT;
4020 }
4021
4022 return EFI_SUCCESS;
4023 }
4024
4025 /**
4026 I/O work flow of in 8042 Aux data.
4027
4028 @param Data Buffer holding return value.
4029
4030 @retval EFI_SUCCESS Success to excute I/O work flow
4031 @retval EFI_TIMEOUT Keyboard controller time out.
4032 **/
4033 EFI_STATUS
4034 In8042AuxData (
4035 IN OUT UINT8 *Data
4036 )
4037 {
4038 EFI_STATUS Status;
4039
4040 //
4041 // wait for output data
4042 //
4043 Status = WaitOutputFull (BAT_TIMEOUT);
4044 if (EFI_ERROR (Status)) {
4045 return Status;
4046 }
4047
4048 *Data = IoRead8 (KBC_DATA_PORT);
4049
4050 return EFI_SUCCESS;
4051 }
4052
4053 /**
4054 I/O work flow of outing 8042 Aux command.
4055
4056 @param Command Aux I/O command
4057
4058 @retval EFI_SUCCESS Success to excute I/O work flow
4059 @retval EFI_TIMEOUT Keyboard controller time out.
4060 **/
4061 EFI_STATUS
4062 Out8042AuxCommand (
4063 IN UINT8 Command
4064 )
4065 {
4066 EFI_STATUS Status;
4067 UINT8 Data;
4068
4069 //
4070 // Wait keyboard controller input buffer empty
4071 //
4072 Status = WaitInputEmpty (TIMEOUT);
4073 if (EFI_ERROR (Status)) {
4074 return Status;
4075 }
4076 //
4077 // Send write to auxiliary device command
4078 //
4079 Data = WRITE_AUX_DEV;
4080 IoWrite8 (KBC_CMD_STS_PORT, Data);
4081
4082 Status = WaitInputEmpty (TIMEOUT);
4083 if (EFI_ERROR (Status)) {
4084 return Status;
4085 }
4086 //
4087 // Send auxiliary device command
4088 //
4089 IoWrite8 (KBC_DATA_PORT, Command);
4090
4091 //
4092 // Read return code
4093 //
4094 Status = In8042AuxData (&Data);
4095 if (EFI_ERROR (Status)) {
4096 return Status;
4097 }
4098
4099 if (Data == PS2_ACK) {
4100 //
4101 // Receive mouse acknowledge, command send success
4102 //
4103 return EFI_SUCCESS;
4104
4105 } else if (Data == PS2_RESEND) {
4106 //
4107 // Resend command
4108 //
4109 Status = Out8042AuxCommand (Command);
4110 if (EFI_ERROR (Status)) {
4111 return Status;
4112 }
4113
4114 } else {
4115 //
4116 // Invalid return code
4117 //
4118 return EFI_DEVICE_ERROR;
4119
4120 }
4121
4122 return EFI_SUCCESS;
4123 }
4124
4125 /**
4126 Issue command to enable Ps2 mouse.
4127
4128 @return Status of command issuing.
4129 **/
4130 EFI_STATUS
4131 PS2MouseEnable (
4132 VOID
4133 )
4134 {
4135 //
4136 // Send auxiliary command to enable mouse
4137 //
4138 return Out8042AuxCommand (ENABLE_CMD);
4139 }
4140
4141 /**
4142 Check whether there is Ps/2 mouse device in system
4143
4144 @retval TRUE - Keyboard in System.
4145 @retval FALSE - Keyboard not in System.
4146
4147 **/
4148 BOOLEAN
4149 IsPs2MouseConnected (
4150 VOID
4151 )
4152 {
4153 EFI_STATUS Status;
4154
4155 Status = PS2MouseEnable ();
4156
4157 if (!EFI_ERROR (Status)) {
4158 return TRUE;
4159 }
4160
4161 return FALSE;
4162 }
GetEcGpeNumber
UINT32 GetEcGpeNumber(VOID)
This function will provide the EC GPE number for ECDT update according to platform design...
Definition: AcpiPlatform.c:424
AcpiGnvsInit
EFI_STATUS AcpiGnvsInit(IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize.
IsHardwareChange
VOID IsHardwareChange(VOID)
This function calculates RCR based on PCI Device ID and Vendor ID from the devices available on the p...
Definition: AcpiPlatform.c:1994
SortCpuLocalApicInTable
EFI_STATUS SortCpuLocalApicInTable(IN EFI_MP_SERVICES_PROTOCOL *MpService, IN UINTN NumberOfCPUs, IN UINTN NumberOfEnabledCPUs)
Sort ordering of CPUs according to the priorities of cores and threads.
Definition: AcpiPlatform.c:3761
GetPcieDockStatus
EFI_STATUS GetPcieDockStatus(OUT UINT8 *DataBuffer)
Get PCIe dock status.
Mcfg.h
This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG)...
S3MemoryVariable.h
AllocateMemoryBelow4G
EFI_STATUS AllocateMemoryBelow4G(IN EFI_MEMORY_TYPE MemoryType, IN UINTN Size, OUT VOID **Buffer)
Allocate MemoryType below 4G memory address.
Definition: AcpiPlatform.c:2190
Out8042AuxCommand
EFI_STATUS Out8042AuxCommand(IN UINT8 Command)
I/O work flow of outing 8042 Aux command.
Definition: AcpiPlatform.c:4062
InstallAcpiPlatform
EFI_STATUS InstallAcpiPlatform(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
ACPI Platform driver installation function.
Definition: AcpiPlatform.c:2462
PlatformInfo.h
GUID used for Platform Info Data entries in the HOB list.
SetAcpiSetupVariables
EFI_STATUS SetAcpiSetupVariables(VOID)
Save Acpi Setup relatived variables.
Definition: AcpiPlatform.c:2398
AcpiPlatform.h
This is an implementation of the ACPI platform driver.
WaitInputEmpty
EFI_STATUS WaitInputEmpty(IN UINTN Timeout)
I/O work flow to wait input buffer empty in given time.
Definition: AcpiPlatform.c:3955
PlatformBoardConfig.h
Header file for Platform Boards Configurations.
WaitOutputFull
EFI_STATUS WaitOutputFull(IN UINTN Timeout)
I/O work flow to wait output buffer full in given time.
Definition: AcpiPlatform.c:3994
GuidStringToAcpiBuffer
EFI_STATUS GuidStringToAcpiBuffer(IN CHAR16 *GuidString, OUT UINT64 *AcpiGuidPart1, OUT UINT64 *AcpiGuidPart2)
Convert string containing GUID in the canonical form: "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp" where aa...
Definition: AcpiPlatform.c:2341
PlatformBoardId.h
Defines Platform BoardIds.
PS2MouseEnable
EFI_STATUS PS2MouseEnable(VOID)
Issue command to enable Ps2 mouse.
Definition: AcpiPlatform.c:4131
LocateSupportProtocol
EFI_STATUS LocateSupportProtocol(IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol.
Definition: AcpiPlatform.c:295
PlatformUpdateTables
EFI_STATUS PlatformUpdateTables(IN OUT EFI_ACPI_COMMON_HEADER *Table, IN OUT EFI_ACPI_TABLE_VERSION *Version)
This function will update any runtime platform specific information.
Definition: AcpiPlatform.c:460
InstallXhciAcpiTable
VOID InstallXhciAcpiTable(VOID)
Install Xhci ACPI Table.
Definition: AcpiPlatform.c:87
IsPs2MouseConnected
BOOLEAN IsPs2MouseConnected(VOID)
Check whether there is Ps/2 mouse device in system.
Definition: AcpiPlatform.c:4149
In8042AuxData
EFI_STATUS In8042AuxData(IN OUT UINT8 *Data)
I/O work flow of in 8042 Aux data.
Definition: AcpiPlatform.c:4034
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AcpiPlatform.h Source File

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe
AcpiPlatform.h
Go to the documentation of this file.
1 /** @file
2 This is an implementation of the ACPI platform driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ACPI_PLATFORM_H_
36 #define _ACPI_PLATFORM_H_
37
38 //
39 // Statements that include other header files
40 //
41
42 #include <IndustryStandard/Acpi.h>
43 #include <Guid/EventGroup.h>
44 #include <Guid/GlobalVariable.h>
45 #include <Library/UefiLib.h>
46 #include <Library/UefiBootServicesTableLib.h>
47 #include <Library/UefiRuntimeServicesTableLib.h>
48 #include <Library/DebugLib.h>
49 #include <Library/BaseMemoryLib.h>
50 #include <Library/MemoryAllocationLib.h>
51 #include <Library/IoLib.h>
52 #include <Library/PcdLib.h>
53 #include <Protocol/CpuIo2.h>
54 #include <Protocol/AcpiTable.h>
55 #include <Protocol/PciRootBridgeIo.h>
56 #include <Protocol/MpService.h>
57 #include <Register/Cpuid.h>
58 #include <CpuAccess.h>
59 #include <PchAccess.h>
60 #include <Protocol/PciIo.h>
61 #include <Library/PchCycleDecodingLib.h>
62
63 #include <IndustryStandard/HighPrecisionEventTimerTable.h>
64 #include <Library/DxeAcpiGnvsInitLib.h>
65
66 //
67 // Produced protocols
68 //
69 #include <Protocol/PlatformNvsArea.h>
70 #include <Protocol/TbtNvsArea.h>
71
72 #include <Platform.h>
73 #include <Library/AslUpdateLib.h>
74 #include <SetupVariable.h>
75 #include <Library/EcMiscLib.h>
76
77 #include <Acpi/AcpiTables/Fadt/Fadt6.1.h>
78 #include <TbtBoardInfo.h>
79
80 //
81 // ACPI table information used to initialize tables.
82 //
83
84 #define NAT_CONFIG_INDEX 0x2E
85 #define NAT_CONFIG_DATA 0x2F
86 #define WPCN381U_CONFIG_INDEX 0x2E
87 #define WPCN381U_CONFIG_DATA 0x2F
88 #define WPCN381U_CHIP_ID 0xF4
89 #define WDCP376_CHIP_ID 0xF1
90 #define Smsc1007_CONFIG_INDEX 0x164E
91 #define SMSC1000_CONFIG_INDEX 0x4E
92
93 #define MAX_CPU_NUM 16
94
95 #define KBC_DATA_PORT 0x60
96 #define KBC_CMD_STS_PORT 0x64
97
98 #define ENABLE_CMD 0xf4
99 #define WRITE_AUX_DEV 0xd4
100
101 #define PS2_ACK 0xfa
102 #define PS2_RESEND 0xfe
103
104 #define KBC_INPB 0x02
105 #define KBC_OUTB 0x01
106 #define KBC_AUXB 0x20
107
108 #define TIMEOUT 50000
109 #define BAT_TIMEOUT 5000
110
111 #define IO_EXPANDER_DISABLED 0xFF
112
113 typedef struct {
114 UINT8 ApicId;
115 UINT32 Flags;
116 UINT8 Package;
117 UINT8 Die;
118 UINT8 Core;
119 UINT8 Thread;
120 } EFI_CPU_ID_ORDER_MAP;
121
122 typedef struct {
123 UINT8 Package;
124 UINT8 ApicId;
125 UINT32 Flags;
126 } EFI_CPU_APIC_ID_REORDER_MAP;
127
128 typedef struct {
129 UINT8 BspApicId;
130 UINT8 TotalThreads;
131 UINT8 PackageNo;
132 UINT8 CoreNo;
133 UINT8 LogicalThreadNo;
134 } EFI_CPU_PACKAGE_INFO;
135
136 //
137 // Function definitions
138 //
139 EFI_STATUS
140 LocateSupportProtocol (
141 IN EFI_GUID *Protocol,
142 IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
143 OUT VOID **Instance,
144 IN BOOLEAN Type
145 );
146
147 /**
148 Entry point of the ACPI platform driver.
149
150 @param[in] ImageHandle A handle for the image that is initializing this driver
151 @param[in] SystemTable A pointer to the EFI system table
152
153 @retval EFI_SUCCESS The driver installed without error.
154 @retval EFI_ABORTED The driver encountered an error and could not complete
155 installation of the ACPI tables.
156 **/
157 EFI_STATUS
158 EFIAPI
159 InstallAcpiPlatform (
160 IN EFI_HANDLE ImageHandle,
161 IN EFI_SYSTEM_TABLE *SystemTable
162 );
163
164 EFI_STATUS
165 SortCpuLocalApicInTable (
166 IN EFI_MP_SERVICES_PROTOCOL *MpService,
167 IN UINTN NumberOfCPUs,
168 IN UINTN NumberOfEnabledCPUs
169 );
170
171 EFI_STATUS
172 AppendCpuMapTableEntry (
173 IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
174 IN UINTN NumberOfCPUs,
175 IN UINTN NumberOfEnabledCPUs,
176 IN UINT8 LocalApicCounter
177 );
178
179 BOOLEAN
180 IsPs2MouseConnected (
181 VOID
182 );
183
184 #endif
LocateSupportProtocol
EFI_STATUS LocateSupportProtocol(IN EFI_GUID *Protocol, IN EFI_GUID gEfiAcpiMultiTableStorageGuid, OUT VOID **Instance, IN BOOLEAN Type)
Locate the first instance of a protocol.
Definition: AcpiPlatform.c:295
SortCpuLocalApicInTable
EFI_STATUS SortCpuLocalApicInTable(IN EFI_MP_SERVICES_PROTOCOL *MpService, IN UINTN NumberOfCPUs, IN UINTN NumberOfEnabledCPUs)
Sort ordering of CPUs according to the priorities of cores and threads.
Definition: AcpiPlatform.c:3761
IsPs2MouseConnected
BOOLEAN IsPs2MouseConnected(VOID)
Check whether there is Ps/2 mouse device in system.
Definition: AcpiPlatform.c:4149
Platform.h
This header file provides platform specific definitions used by other modules for platform specific i...
PlatformNvsArea.h
This file defines the Platform NVS Area Protocol.
DxeAcpiGnvsInitLib.h
Acpi Gnvs Init Library header file.
Fadt6.1.h
This file describes the contents of the ACPI Fixed ACPI Description Table (FADT). ...
EcMiscLib.h
EC miscellaneous library functions.
InstallAcpiPlatform
EFI_STATUS InstallAcpiPlatform(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point of the ACPI platform driver.
Definition: AcpiPlatform.c:2462
SetupVariable.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AcpiVariable.h Source File

  • Guid
AcpiVariable.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _ACPI_VARIABLE_H_
36 #define _ACPI_VARIABLE_H_
37 #define ACPI_GLOBAL_VARIABLE L"AcpiGlobalVariable"
38
39 //
40 // The following structure combine all ACPI related variables into one in order
41 // to boost performance
42 //
43
44 typedef struct {
45 //
46 // Acpi Related variables
47 //
48 EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase;
49 UINT32 AcpiReservedMemorySize;
50 EFI_PHYSICAL_ADDRESS S3ReservedLowMemoryBase;
51 EFI_PHYSICAL_ADDRESS AcpiBootScriptTable;
52 EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase;
53 EFI_PHYSICAL_ADDRESS AcpiFacsTable;
54 UINT64 SystemMemoryLength;
55 //
56 // VGA OPROM to support Video Re-POST for Linux S3
57 //
58 EFI_PHYSICAL_ADDRESS VideoOpromAddress;
59 UINT32 VideoOpromSize;
60
61 //
62 // S3 Debug extension
63 //
64 EFI_PHYSICAL_ADDRESS S3DebugBufferAddress;
65 EFI_PHYSICAL_ADDRESS S3ResumeNvsEntryPoint;
66 } ACPI_VARIABLE_SET;
67
68 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AmtPolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
AmtPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel AMT DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "AmtPolicyInitDxe.h"
35
36 /**
37 Initialize Intel AMT DXE Policy
38
39 @param[in] ImageHandle Image handle of this driver.
40
41 @retval EFI_SUCCESS Initialization complete.
42 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
43 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
44 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
45 **/
46 EFI_STATUS
47 EFIAPI
48 AmtPolicyInitDxe (
49 IN EFI_HANDLE ImageHandle
50 )
51 {
52 EFI_STATUS Status;
53 AMT_POLICY_PROTOCOL *AmtPolicyProtocol;
54
55 DEBUG ((DEBUG_INFO, "AmtPolicyInitDxe\n"));
56 //
57 // Call AmtCreatePolicyDefaults to initialize platform policy structure
58 // and get all default policy settings.
59 //
60 Status = AmtCreatePolicyDefaults (&AmtPolicyProtocol);
61 if (Status == EFI_UNSUPPORTED) {
62 return EFI_SUCCESS;
63 }
64
65 UpdateDxeAmtPolicyBoardConfig (AmtPolicyProtocol);
66
67 if (mFirmwareConfiguration != FwConfigDefault) {
68 UpdateDxeAmtPolicy (AmtPolicyProtocol);
69 }
70
71 //
72 // Install AmtInstallPolicyProtocol.
73 // While installed, RC assumes the Policy is ready and finalized. So please
74 // update and override any setting before calling this function.
75 //
76 Status = AmtInstallPolicyProtocol (ImageHandle, AmtPolicyProtocol);
77
78 return Status;
79 }
80
AmtPolicyInitDxe.h
Header file for the AmtPolicyInitDxe Driver.
AmtPolicyInitDxe
EFI_STATUS AmtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy.
Definition: AmtPolicyInitDxe.c:48
UpdateDxeAmtPolicyBoardConfig
EFI_STATUS UpdateDxeAmtPolicyBoardConfig(IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function performs DXE AMT Policy update by board configuration.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AmtPolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
AmtPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the AmtPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _AMT_POLICY_INIT_DXE_H_
35 #define _AMT_POLICY_INIT_DXE_H_
36
37 #include <Library/DebugLib.h>
38 #include <Library/UefiBootServicesTableLib.h>
39 #include <FirwmareConfigurations.h>
40
41 #include <Protocol/MePolicy.h>
42 #include <Protocol/AmtPolicy.h>
43 #include <Library/DxeAmtPolicyLib.h>
44 #include <Library/DxePolicyBoardConfigLib.h>
45 #include <Library/DxeAmtPolicyUpdateLib.h>
46
47 extern UINT8 mFirmwareConfiguration;
48
49 /**
50 Initialize Intel AMT DXE Policy
51
52 @param[in] ImageHandle Image handle of this driver.
53
54 @retval EFI_SUCCESS Initialization complete.
55 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
56 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
57 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
58 **/
59 EFI_STATUS
60 EFIAPI
61 AmtPolicyInitDxe (
62 IN EFI_HANDLE ImageHandle
63 )
64 ;
65
66 #endif
DxePolicyBoardConfigLib.h
Header file for the DxePolicyBoardConfig Library.
AmtPolicyInitDxe
EFI_STATUS AmtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy.
Definition: AmtPolicyInitDxe.c:48
DxeAmtPolicyUpdateLib.h
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AmtWrapperProtocol.h Source File

  • Protocol
AmtWrapperProtocol.h
Go to the documentation of this file.
1 /** @file
2
3 The header file includes the definition of EFI_SPI_PROTOCOL.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2011 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _EFI_AMT_WRAPPER_PROTOCOL_H_
37 #define _EFI_AMT_WRAPPER_PROTOCOL_H_
38
39
40 #define EFI_AMT_WRAPPER_PROTOCOL_GUID \
41 {0xd54f49f6, 0x0dd4, 0x4276, {0xb0, 0x9c, 0xdf, 0xe1, 0xfd, 0x80, 0x85, 0xf0}}
42
43 //
44 // Forward reference for ANSI C compatibility
45 //
46 typedef struct _AMT_WRAPPER_PROTOCOL AMT_WRAPPER_PROTOCOL;
47
48 typedef
49 EFI_STATUS
50 (EFIAPI *AMT_WRAPPER_INIT) (
51 EFI_HANDLE ImageHandle,
52 EFI_SYSTEM_TABLE *SystemTable
53 );
54
55 typedef
56 BOOLEAN
57 (EFIAPI *AMT_WRAPPER_GET) (
58 UINTN Index,
59 VOID *Variable
60 );
61
62 typedef
63 BOOLEAN
64 (EFIAPI *AMT_WRAPPER_SET) (
65 UINTN Index,
66 VOID *Variable
67 );
68
69 typedef
70 BOOLEAN
71 (EFIAPI *ACTIVE_MANAGEMENT_ENABLE_KVM) (
72 VOID
73 );
74
75 typedef
76 BOOLEAN
77 (EFIAPI *ACTIVE_MANAGEMENT_ENABLE_SOL) (
78 VOID
79 );
80
81 typedef
82 BOOLEAN
83 (EFIAPI *ACTIVE_MANAGEMENT_ENABLE_STORAGE_REDIR) (
84 VOID
85 );
86
87 typedef
88 BOOLEAN
89 (EFIAPI *ACTIVE_MANAGEMENT_BOOT_OPTION_EXIST) (
90 IN VOID
91 );
92
93 typedef
94 EFI_STATUS
95 (EFIAPI *BDS_BOOT_VIA_ASF) (
96 VOID
97 );
98
99 typedef
100 BOOLEAN
101 (EFIAPI *ACTIVE_MANAGEMENT_PAUSE_BOOT) (
102 VOID
103 );
104
105 typedef
106 BOOLEAN
107 (EFIAPI *ACTIVE_MANAGEMENT_ENTER_SETUP) (
108 VOID
109 );
110
111 typedef
112 BOOLEAN
113 (EFIAPI *ACTIVE_MANAGEMENT_CONSOLE_LOCKED) (
114 VOID
115 );
116
117 typedef
118 BOOLEAN
119 (EFIAPI *ACTIVE_MANAGEMENT_ENABLE_SECURE_ERASE) (
120 VOID
121 );
122
123
124 typedef
125 EFI_STATUS
126 (EFIAPI *GET_SETUP_PROMPT) (
127 IN OUT UINTN *PromptIndex,
128 OUT CHAR16 **String
129 );
130
131 typedef
132 EFI_STATUS
133 (EFIAPI *DETERMINE_SETUP_HOTKEY) (
134 IN EFI_KEY_DATA *KeyData
135 );
136
137 typedef
138 EFI_STATUS
139 (EFIAPI *GET_SUPPORTED_HOTKEYS) (
140 OUT UINTN *KeyCnt,
141 OUT EFI_KEY_DATA **KeyData
142 );
143
144 typedef struct _AMT_WRAPPER_PROTOCOL {
145 AMT_WRAPPER_INIT AmtWrapperInit;
146 AMT_WRAPPER_GET AmtWrapperGet;
147 AMT_WRAPPER_SET AmtWrapperSet;
148 ACTIVE_MANAGEMENT_BOOT_OPTION_EXIST ActiveManagementBootOptionExist;
149 ACTIVE_MANAGEMENT_ENABLE_STORAGE_REDIR ActiveManagementIsStorageRedirectionEnabled;
150 ACTIVE_MANAGEMENT_ENTER_SETUP ActiveManagementIsEnterSetupEnabled;
151 ACTIVE_MANAGEMENT_PAUSE_BOOT ActiveManagementIsPauseBootEnabled;
152 ACTIVE_MANAGEMENT_ENABLE_KVM ActiveManagementIsKvmEnabled;
153 ACTIVE_MANAGEMENT_ENABLE_SECURE_ERASE ActiveManagementIsSecureEraseEnabled;
154 ACTIVE_MANAGEMENT_CONSOLE_LOCKED ActiveManagementIsConsoleLocked;
155 ACTIVE_MANAGEMENT_ENABLE_SOL ActiveManagementIsSolEnabled;
156 BDS_BOOT_VIA_ASF BdsBootViaAsf;
157 GET_SETUP_PROMPT GetSetupPrompt;
158 DETERMINE_SETUP_HOTKEY DetermineSetupHotKey;
159 GET_SUPPORTED_HOTKEYS GetSupportedHotkeys;
160 } AMT_WRAPPER_PROTOCOL;
161
162 #define GET_SOL_DP 1
163 #define GET_BOOT_OPTION 2
164 #define GET_IS_SOL 3
165
166 #define SET_BIOS_WDT_START 1
167 #define SET_WDT_STOP 2
168 #define SET_OS_SOL 3
169 #define SET_OS_WDT_START 4
170
171 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: AttemptUsbFirst.h Source File

AttemptUsbFirst.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _ATTEMPT_USB_FIRST_H_
35 #define _ATTEMPT_USB_FIRST_H_
36
37 #pragma pack(1)
38 typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO {
39 UINT8 RevisonId; // Structure Revision ID
40 UINT8 HotkeyTriggered; // Hot key status
41 } ATTEMPT_USB_FIRST_HOTKEY_INFO;
42 #pragma pack()
43
44 #pragma pack(1)
45 typedef struct _ATTEMPT_USB_FIRST_VARIABLE {
46 UINT8 UsbBootPrior;
47 } ATTEMPT_USB_FIRST_VARIABLE;
48 #pragma pack()
49
50 //
51 // Volatile variable definition for Attempt USB first features
52 //
53 #pragma pack(1)
54 typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE {
55 UINT8 RevisonId; // Structure Revision ID
56 UINT8 UsbFirstEnable; // Attempt USB First is enabled or not
57 } ATTEMPT_USB_FIRST_RUNTIME_VARIABLE;
58 #pragma pack()
59
60 //
61 // Volatile variable definition for third party Default Enabling via UEFI Variable.
62 //
63 #pragma pack(1)
64 typedef struct _ENABLE_CUSTOM_DEFAULTS{
65 UINT32 EnableCustomDefaults;
66 } ENABLE_CUSTOM_DEFAULTS;
67 #pragma pack()
68
69 #define COENG_DEFAULTS_UNKNOWN 0
70 #define COENG_DEFAULTS_SUPPORTED 1
71 #define COENG_DEFAULTS_VAR_EXITS 2
72 #define COENG_DEFAULTS_VAR_SET 4
73 #define COENG_DEFAULTS_AVAILABLE (COENG_DEFAULTS_SUPPORTED | COENG_DEFAULTS_VAR_EXITS |COENG_DEFAULTS_VAR_SET)
74
75 extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid;
76 extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid;
77 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: BaseCryptLib.h Source File

  • Library
BaseCryptLib.h
Go to the documentation of this file.
1 /** @file
2 Defines base cryptographic library APIs.
3 The Base Cryptographic Library provides implementations of basic cryptography
4 primitives (Hash Serials, HMAC, RSA, Diffie-Hellman, etc) for UEFI security
5 functionality enabling.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 2009 - 2016 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37
38 #ifndef __BASE_CRYPT_LIB_H__
39 #define __BASE_CRYPT_LIB_H__
40
41 ///
42 /// MD5 digest size in bytes
43 ///
44 #define MD5_DIGEST_SIZE 16
45
46 ///
47 /// SHA-1 digest size in bytes.
48 ///
49 #define SHA1_DIGEST_SIZE 20
50
51 ///
52 /// SHA-256 digest size in bytes
53 ///
54 #define SHA256_DIGEST_SIZE 32
55
56 ///
57 /// TDES block size in bytes
58 ///
59 #define TDES_BLOCK_SIZE 8
60
61 ///
62 /// AES block size in bytes
63 ///
64 #define AES_BLOCK_SIZE 16
65
66 ///
67 /// RSA Key Tags Definition used in RsaSetKey() function for key component identification.
68 ///
69 typedef enum {
70 RsaKeyN, ///< RSA public Modulus (N)
71 RsaKeyE, ///< RSA Public exponent (e)
72 RsaKeyD, ///< RSA Private exponent (d)
73 RsaKeyP, ///< RSA secret prime factor of Modulus (p)
74 RsaKeyQ, ///< RSA secret prime factor of Modules (q)
75 RsaKeyDp, ///< p's CRT exponent (== d mod (p - 1))
76 RsaKeyDq, ///< q's CRT exponent (== d mod (q - 1))
77 RsaKeyQInv ///< The CRT coefficient (== 1/q mod p)
78 } RSA_KEY_TAG;
79
80 //=====================================================================================
81 // One-Way Cryptographic Hash Primitives
82 //=====================================================================================
83
84 /**
85 Retrieves the size, in bytes, of the context buffer required for MD5 hash operations.
86
87 @return The size, in bytes, of the context buffer required for MD5 hash operations.
88
89 **/
90 UINTN
91 EFIAPI
92 Md5GetContextSize (
93 VOID
94 );
95
96 /**
97 Initializes user-supplied memory pointed by Md5Context as MD5 hash context for
98 subsequent use.
99
100 If Md5Context is NULL, then ASSERT().
101
102 @param[out] Md5Context Pointer to MD5 context being initialized.
103
104 @retval TRUE MD5 context initialization succeeded.
105 @retval FALSE MD5 context initialization failed.
106
107 **/
108 BOOLEAN
109 EFIAPI
110 Md5Init (
111 OUT VOID *Md5Context
112 );
113
114 /**
115 Makes a copy of an existing MD5 context.
116
117 If Md5Context is NULL, then ASSERT().
118 If NewMd5Context is NULL, then ASSERT().
119
120 @param[in] Md5Context Pointer to MD5 context being copied.
121 @param[out] NewMd5Context Pointer to new MD5 context.
122
123 @retval TRUE MD5 context copy succeeded.
124 @retval FALSE MD5 context copy failed.
125
126 **/
127 BOOLEAN
128 EFIAPI
129 Md5Duplicate (
130 IN CONST VOID *Md5Context,
131 OUT VOID *NewMd5Context
132 );
133
134 /**
135 Digests the input data and updates MD5 context.
136
137 This function performs MD5 digest on a data buffer of the specified size.
138 It can be called multiple times to compute the digest of long or discontinuous data streams.
139 MD5 context should be already correctly intialized by Md5Init(), and should not be finalized
140 by Md5Final(). Behavior with invalid context is undefined.
141
142 If Md5Context is NULL, then ASSERT().
143
144 @param[in, out] Md5Context Pointer to the MD5 context.
145 @param[in] Data Pointer to the buffer containing the data to be hashed.
146 @param[in] DataSize Size of Data buffer in bytes.
147
148 @retval TRUE MD5 data digest succeeded.
149 @retval FALSE MD5 data digest failed.
150
151 **/
152 BOOLEAN
153 EFIAPI
154 Md5Update (
155 IN OUT VOID *Md5Context,
156 IN CONST VOID *Data,
157 IN UINTN DataSize
158 );
159
160 /**
161 Completes computation of the MD5 digest value.
162
163 This function completes MD5 hash computation and retrieves the digest value into
164 the specified memory. After this function has been called, the MD5 context cannot
165 be used again.
166 MD5 context should be already correctly intialized by Md5Init(), and should not be
167 finalized by Md5Final(). Behavior with invalid MD5 context is undefined.
168
169 If Md5Context is NULL, then ASSERT().
170 If HashValue is NULL, then ASSERT().
171
172 @param[in, out] Md5Context Pointer to the MD5 context.
173 @param[out] HashValue Pointer to a buffer that receives the MD5 digest
174 value (16 bytes).
175
176 @retval TRUE MD5 digest computation succeeded.
177 @retval FALSE MD5 digest computation failed.
178
179 **/
180 BOOLEAN
181 EFIAPI
182 Md5Final (
183 IN OUT VOID *Md5Context,
184 OUT UINT8 *HashValue
185 );
186
187 /**
188 Retrieves the size, in bytes, of the context buffer required for SHA-1 hash operations.
189
190 @return The size, in bytes, of the context buffer required for SHA-1 hash operations.
191
192 **/
193 UINTN
194 EFIAPI
195 Sha1GetContextSize (
196 VOID
197 );
198
199 /**
200 Initializes user-supplied memory pointed by Sha1Context as SHA-1 hash context for
201 subsequent use.
202
203 If Sha1Context is NULL, then ASSERT().
204
205 @param[out] Sha1Context Pointer to SHA-1 context being initialized.
206
207 @retval TRUE SHA-1 context initialization succeeded.
208 @retval FALSE SHA-1 context initialization failed.
209
210 **/
211 BOOLEAN
212 EFIAPI
213 Sha1Init (
214 OUT VOID *Sha1Context
215 );
216
217 /**
218 Makes a copy of an existing SHA-1 context.
219
220 If Sha1Context is NULL, then ASSERT().
221 If NewSha1Context is NULL, then ASSERT().
222
223 @param[in] Sha1Context Pointer to SHA-1 context being copied.
224 @param[out] NewSha1Context Pointer to new SHA-1 context.
225
226 @retval TRUE SHA-1 context copy succeeded.
227 @retval FALSE SHA-1 context copy failed.
228
229 **/
230 BOOLEAN
231 EFIAPI
232 Sha1Duplicate (
233 IN CONST VOID *Sha1Context,
234 OUT VOID *NewSha1Context
235 );
236
237 /**
238 Digests the input data and updates SHA-1 context.
239
240 This function performs SHA-1 digest on a data buffer of the specified size.
241 It can be called multiple times to compute the digest of long or discontinuous data streams.
242 SHA-1 context should be already correctly intialized by Sha1Init(), and should not be finalized
243 by Sha1Final(). Behavior with invalid context is undefined.
244
245 If Sha1Context is NULL, then ASSERT().
246
247 @param[in, out] Sha1Context Pointer to the SHA-1 context.
248 @param[in] Data Pointer to the buffer containing the data to be hashed.
249 @param[in] DataSize Size of Data buffer in bytes.
250
251 @retval TRUE SHA-1 data digest succeeded.
252 @retval FALSE SHA-1 data digest failed.
253
254 **/
255 BOOLEAN
256 EFIAPI
257 Sha1Update (
258 IN OUT VOID *Sha1Context,
259 IN CONST VOID *Data,
260 IN UINTN DataSize
261 );
262
263 /**
264 Completes computation of the SHA-1 digest value.
265
266 This function completes SHA-1 hash computation and retrieves the digest value into
267 the specified memory. After this function has been called, the SHA-1 context cannot
268 be used again.
269 SHA-1 context should be already correctly intialized by Sha1Init(), and should not be
270 finalized by Sha1Final(). Behavior with invalid SHA-1 context is undefined.
271
272 If Sha1Context is NULL, then ASSERT().
273 If HashValue is NULL, then ASSERT().
274
275 @param[in, out] Sha1Context Pointer to the SHA-1 context.
276 @param[out] HashValue Pointer to a buffer that receives the SHA-1 digest
277 value (20 bytes).
278
279 @retval TRUE SHA-1 digest computation succeeded.
280 @retval FALSE SHA-1 digest computation failed.
281
282 **/
283 BOOLEAN
284 EFIAPI
285 Sha1Final (
286 IN OUT VOID *Sha1Context,
287 OUT UINT8 *HashValue
288 );
289
290 /**
291 Retrieves the size, in bytes, of the context buffer required for SHA-256 hash operations.
292
293 @return The size, in bytes, of the context buffer required for SHA-256 hash operations.
294
295 **/
296 UINTN
297 EFIAPI
298 Sha256GetContextSize (
299 VOID
300 );
301
302 /**
303 Initializes user-supplied memory pointed by Sha256Context as SHA-256 hash context for
304 subsequent use.
305
306 If Sha256Context is NULL, then ASSERT().
307
308 @param[out] Sha256Context Pointer to SHA-256 context being initialized.
309
310 @retval TRUE SHA-256 context initialization succeeded.
311 @retval FALSE SHA-256 context initialization failed.
312
313 **/
314 BOOLEAN
315 EFIAPI
316 Sha256Init (
317 OUT VOID *Sha256Context
318 );
319
320 /**
321 Makes a copy of an existing SHA-256 context.
322
323 If Sha256Context is NULL, then ASSERT().
324 If NewSha256Context is NULL, then ASSERT().
325
326 @param[in] Sha256Context Pointer to SHA-256 context being copied.
327 @param[out] NewSha256Context Pointer to new SHA-256 context.
328
329 @retval TRUE SHA-256 context copy succeeded.
330 @retval FALSE SHA-256 context copy failed.
331
332 **/
333 BOOLEAN
334 EFIAPI
335 Sha256Duplicate (
336 IN CONST VOID *Sha256Context,
337 OUT VOID *NewSha256Context
338 );
339
340 /**
341 Digests the input data and updates SHA-256 context.
342
343 This function performs SHA-256 digest on a data buffer of the specified size.
344 It can be called multiple times to compute the digest of long or discontinuous data streams.
345 SHA-256 context should be already correctly intialized by Sha256Init(), and should not be finalized
346 by Sha256Final(). Behavior with invalid context is undefined.
347
348 If Sha256Context is NULL, then ASSERT().
349
350 @param[in, out] Sha256Context Pointer to the SHA-256 context.
351 @param[in] Data Pointer to the buffer containing the data to be hashed.
352 @param[in] DataSize Size of Data buffer in bytes.
353
354 @retval TRUE SHA-256 data digest succeeded.
355 @retval FALSE SHA-256 data digest failed.
356
357 **/
358 BOOLEAN
359 EFIAPI
360 Sha256Update (
361 IN OUT VOID *Sha256Context,
362 IN CONST VOID *Data,
363 IN UINTN DataSize
364 );
365
366 /**
367 Completes computation of the SHA-256 digest value.
368
369 This function completes SHA-256 hash computation and retrieves the digest value into
370 the specified memory. After this function has been called, the SHA-256 context cannot
371 be used again.
372 SHA-256 context should be already correctly intialized by Sha256Init(), and should not be
373 finalized by Sha256Final(). Behavior with invalid SHA-256 context is undefined.
374
375 If Sha256Context is NULL, then ASSERT().
376 If HashValue is NULL, then ASSERT().
377
378 @param[in, out] Sha256Context Pointer to the SHA-256 context.
379 @param[out] HashValue Pointer to a buffer that receives the SHA-256 digest
380 value (32 bytes).
381
382 @retval TRUE SHA-256 digest computation succeeded.
383 @retval FALSE SHA-256 digest computation failed.
384
385 **/
386 BOOLEAN
387 EFIAPI
388 Sha256Final (
389 IN OUT VOID *Sha256Context,
390 OUT UINT8 *HashValue
391 );
392
393
394 //=====================================================================================
395 // MAC (Message Authentication Code) Primitive
396 //=====================================================================================
397
398 /**
399 Retrieves the size, in bytes, of the context buffer required for HMAC-MD5 operations.
400
401 @return The size, in bytes, of the context buffer required for HMAC-MD5 operations.
402
403 **/
404 UINTN
405 EFIAPI
406 HmacMd5GetContextSize (
407 VOID
408 );
409
410 /**
411 Initializes user-supplied memory pointed by HmacMd5Context as HMAC-MD5 context for
412 subsequent use.
413
414 If HmacMd5Context is NULL, then ASSERT().
415
416 @param[out] HmacMd5Context Pointer to HMAC-MD5 context being initialized.
417 @param[in] Key Pointer to the user-supplied key.
418 @param[in] KeySize Key size in bytes.
419
420 @retval TRUE HMAC-MD5 context initialization succeeded.
421 @retval FALSE HMAC-MD5 context initialization failed.
422
423 **/
424 BOOLEAN
425 EFIAPI
426 HmacMd5Init (
427 OUT VOID *HmacMd5Context,
428 IN CONST UINT8 *Key,
429 IN UINTN KeySize
430 );
431
432 /**
433 Makes a copy of an existing HMAC-MD5 context.
434
435 If HmacMd5Context is NULL, then ASSERT().
436 If NewHmacMd5Context is NULL, then ASSERT().
437
438 @param[in] HmacMd5Context Pointer to HMAC-MD5 context being copied.
439 @param[out] NewHmacMd5Context Pointer to new HMAC-MD5 context.
440
441 @retval TRUE HMAC-MD5 context copy succeeded.
442 @retval FALSE HMAC-MD5 context copy failed.
443
444 **/
445 BOOLEAN
446 EFIAPI
447 HmacMd5Duplicate (
448 IN CONST VOID *HmacMd5Context,
449 OUT VOID *NewHmacMd5Context
450 );
451
452 /**
453 Digests the input data and updates HMAC-MD5 context.
454
455 This function performs HMAC-MD5 digest on a data buffer of the specified size.
456 It can be called multiple times to compute the digest of long or discontinuous data streams.
457 HMAC-MD5 context should be already correctly intialized by HmacMd5Init(), and should not be
458 finalized by HmacMd5Final(). Behavior with invalid context is undefined.
459
460 If HmacMd5Context is NULL, then ASSERT().
461
462 @param[in, out] HmacMd5Context Pointer to the HMAC-MD5 context.
463 @param[in] Data Pointer to the buffer containing the data to be digested.
464 @param[in] DataSize Size of Data buffer in bytes.
465
466 @retval TRUE HMAC-MD5 data digest succeeded.
467 @retval FALSE HMAC-MD5 data digest failed.
468
469 **/
470 BOOLEAN
471 EFIAPI
472 HmacMd5Update (
473 IN OUT VOID *HmacMd5Context,
474 IN CONST VOID *Data,
475 IN UINTN DataSize
476 );
477
478 /**
479 Completes computation of the HMAC-MD5 digest value.
480
481 This function completes HMAC-MD5 hash computation and retrieves the digest value into
482 the specified memory. After this function has been called, the HMAC-MD5 context cannot
483 be used again.
484 HMAC-MD5 context should be already correctly intialized by HmacMd5Init(), and should not be
485 finalized by HmacMd5Final(). Behavior with invalid HMAC-MD5 context is undefined.
486
487 If HmacMd5Context is NULL, then ASSERT().
488 If HashValue is NULL, then ASSERT().
489
490 @param[in, out] HmacMd5Context Pointer to the HMAC-MD5 context.
491 @param[out] HashValue Pointer to a buffer that receives the HMAC-MD5 digest
492 value (16 bytes).
493
494 @retval TRUE HMAC-MD5 digest computation succeeded.
495 @retval FALSE HMAC-MD5 digest computation failed.
496
497 **/
498 BOOLEAN
499 EFIAPI
500 HmacMd5Final (
501 IN OUT VOID *HmacMd5Context,
502 OUT UINT8 *HmacValue
503 );
504
505 /**
506 Retrieves the size, in bytes, of the context buffer required for HMAC-SHA1 operations.
507
508 @return The size, in bytes, of the context buffer required for HMAC-SHA1 operations.
509
510 **/
511 UINTN
512 EFIAPI
513 HmacSha1GetContextSize (
514 VOID
515 );
516
517 /**
518 Initializes user-supplied memory pointed by HmacSha1Context as HMAC-SHA1 context for
519 subsequent use.
520
521 If HmacSha1Context is NULL, then ASSERT().
522
523 @param[out] HmacSha1Context Pointer to HMAC-SHA1 context being initialized.
524 @param[in] Key Pointer to the user-supplied key.
525 @param[in] KeySize Key size in bytes.
526
527 @retval TRUE HMAC-SHA1 context initialization succeeded.
528 @retval FALSE HMAC-SHA1 context initialization failed.
529
530 **/
531 BOOLEAN
532 EFIAPI
533 HmacSha1Init (
534 OUT VOID *HmacSha1Context,
535 IN CONST UINT8 *Key,
536 IN UINTN KeySize
537 );
538
539 /**
540 Makes a copy of an existing HMAC-SHA1 context.
541
542 If HmacSha1Context is NULL, then ASSERT().
543 If NewHmacSha1Context is NULL, then ASSERT().
544
545 @param[in] HmacSha1Context Pointer to HMAC-SHA1 context being copied.
546 @param[out] NewHmacSha1Context Pointer to new HMAC-SHA1 context.
547
548 @retval TRUE HMAC-SHA1 context copy succeeded.
549 @retval FALSE HMAC-SHA1 context copy failed.
550
551 **/
552 BOOLEAN
553 EFIAPI
554 HmacSha1Duplicate (
555 IN CONST VOID *HmacSha1Context,
556 OUT VOID *NewHmacSha1Context
557 );
558
559 /**
560 Digests the input data and updates HMAC-SHA1 context.
561
562 This function performs HMAC-SHA1 digest on a data buffer of the specified size.
563 It can be called multiple times to compute the digest of long or discontinuous data streams.
564 HMAC-SHA1 context should be already correctly intialized by HmacSha1Init(), and should not
565 be finalized by HmacSha1Final(). Behavior with invalid context is undefined.
566
567 If HmacSha1Context is NULL, then ASSERT().
568
569 @param[in, out] HmacSha1Context Pointer to the HMAC-SHA1 context.
570 @param[in] Data Pointer to the buffer containing the data to be digested.
571 @param[in] DataSize Size of Data buffer in bytes.
572
573 @retval TRUE HMAC-SHA1 data digest succeeded.
574 @retval FALSE HMAC-SHA1 data digest failed.
575
576 **/
577 BOOLEAN
578 EFIAPI
579 HmacSha1Update (
580 IN OUT VOID *HmacSha1Context,
581 IN CONST VOID *Data,
582 IN UINTN DataSize
583 );
584
585 /**
586 Completes computation of the HMAC-SHA1 digest value.
587
588 This function completes HMAC-SHA1 hash computation and retrieves the digest value into
589 the specified memory. After this function has been called, the HMAC-SHA1 context cannot
590 be used again.
591 HMAC-SHA1 context should be already correctly intialized by HmacSha1Init(), and should
592 not be finalized by HmacSha1Final(). Behavior with invalid HMAC-SHA1 context is undefined.
593
594 If HmacSha1Context is NULL, then ASSERT().
595 If HashValue is NULL, then ASSERT().
596
597 @param[in, out] HmacSha1Context Pointer to the HMAC-SHA1 context.
598 @param[out] HashValue Pointer to a buffer that receives the HMAC-SHA1 digest
599 value (20 bytes).
600
601 @retval TRUE HMAC-SHA1 digest computation succeeded.
602 @retval FALSE HMAC-SHA1 digest computation failed.
603
604 **/
605 BOOLEAN
606 EFIAPI
607 HmacSha1Final (
608 IN OUT VOID *HmacSha1Context,
609 OUT UINT8 *HmacValue
610 );
611
612
613 //=====================================================================================
614 // Symmetric Cryptography Primitive
615 //=====================================================================================
616
617 /**
618 Retrieves the size, in bytes, of the context buffer required for TDES operations.
619
620 @return The size, in bytes, of the context buffer required for TDES operations.
621
622 **/
623 UINTN
624 EFIAPI
625 TdesGetContextSize (
626 VOID
627 );
628
629 /**
630 Initializes user-supplied memory as TDES context for subsequent use.
631
632 This function initializes user-supplied memory pointed by TdesContext as TDES context.
633 In addtion, it sets up all TDES key materials for subsequent encryption and decryption
634 operations.
635 There are 3 key options as follows:
636 KeyLength = 64, Keying option 1: K1 == K2 == K3 (Backward compatibility with DES)
637 KeyLength = 128, Keying option 2: K1 != K2 and K3 = K1 (Less Security)
638 KeyLength = 192 Keying option 3: K1 != K2 != K3 (Strongest)
639
640 If TdesContext is NULL, then ASSERT().
641 If Key is NULL, then ASSERT().
642 If KeyLength is not valid, then ASSERT().
643
644 @param[out] TdesContext Pointer to TDES context being initialized.
645 @param[in] Key Pointer to the user-supplied TDES key.
646 @param[in] KeyLength Length of TDES key in bits.
647
648 @retval TRUE TDES context initialization succeeded.
649 @retval FALSE TDES context initialization failed.
650
651 **/
652 BOOLEAN
653 EFIAPI
654 TdesInit (
655 OUT VOID *TdesContext,
656 IN CONST UINT8 *Key,
657 IN UINTN KeyLength
658 );
659
660 /**
661 Performs TDES encryption on a data buffer of the specified size in ECB mode.
662
663 This function performs TDES encryption on data buffer pointed by Input, of specified
664 size of InputSize, in ECB mode.
665 InputSize must be multiple of block size (8 bytes). This function does not perform
666 padding. Caller must perform padding, if necessary, to ensure valid input data size.
667 TdesContext should be already correctly initialized by TdesInit(). Behavior with
668 invalid TDES context is undefined.
669
670 If TdesContext is NULL, then ASSERT().
671 If Input is NULL, then ASSERT().
672 If InputSize is not multiple of block size (8 bytes), then ASSERT().
673 If Output is NULL, then ASSERT().
674
675 @param[in] TdesContext Pointer to the TDES context.
676 @param[in] Input Pointer to the buffer containing the data to be encrypted.
677 @param[in] InputSize Size of the Input buffer in bytes.
678 @param[out] Output Pointer to a buffer that receives the TDES encryption output.
679
680 @retval TRUE TDES encryption succeeded.
681 @retval FALSE TDES encryption failed.
682
683 **/
684 BOOLEAN
685 EFIAPI
686 TdesEcbEncrypt (
687 IN VOID *TdesContext,
688 IN CONST UINT8 *Input,
689 IN UINTN InputSize,
690 OUT UINT8 *Output
691 );
692
693 /**
694 Performs TDES decryption on a data buffer of the specified size in ECB mode.
695
696 This function performs TDES decryption on data buffer pointed by Input, of specified
697 size of InputSize, in ECB mode.
698 InputSize must be multiple of block size (8 bytes). This function does not perform
699 padding. Caller must perform padding, if necessary, to ensure valid input data size.
700 TdesContext should be already correctly initialized by TdesInit(). Behavior with
701 invalid TDES context is undefined.
702
703 If TdesContext is NULL, then ASSERT().
704 If Input is NULL, then ASSERT().
705 If InputSize is not multiple of block size (8 bytes), then ASSERT().
706 If Output is NULL, then ASSERT().
707
708 @param[in] TdesContext Pointer to the TDES context.
709 @param[in] Input Pointer to the buffer containing the data to be decrypted.
710 @param[in] InputSize Size of the Input buffer in bytes.
711 @param[out] Output Pointer to a buffer that receives the TDES decryption output.
712
713 @retval TRUE TDES decryption succeeded.
714 @retval FALSE TDES decryption failed.
715
716 **/
717 BOOLEAN
718 EFIAPI
719 TdesEcbDecrypt (
720 IN VOID *TdesContext,
721 IN CONST UINT8 *Input,
722 IN UINTN InputSize,
723 OUT UINT8 *Output
724 );
725
726 /**
727 Performs TDES encryption on a data buffer of the specified size in CBC mode.
728
729 This function performs TDES encryption on data buffer pointed by Input, of specified
730 size of InputSize, in CBC mode.
731 InputSize must be multiple of block size (8 bytes). This function does not perform
732 padding. Caller must perform padding, if necessary, to ensure valid input data size.
733 Initialization vector should be one block size (8 bytes).
734 TdesContext should be already correctly initialized by TdesInit(). Behavior with
735 invalid TDES context is undefined.
736
737 If TdesContext is NULL, then ASSERT().
738 If Input is NULL, then ASSERT().
739 If InputSize is not multiple of block size (8 bytes), then ASSERT().
740 If Ivec is NULL, then ASSERT().
741 If Output is NULL, then ASSERT().
742
743 @param[in] TdesContext Pointer to the TDES context.
744 @param[in] Input Pointer to the buffer containing the data to be encrypted.
745 @param[in] InputSize Size of the Input buffer in bytes.
746 @param[in] Ivec Pointer to initialization vector.
747 @param[out] Output Pointer to a buffer that receives the TDES encryption output.
748
749 @retval TRUE TDES encryption succeeded.
750 @retval FALSE TDES encryption failed.
751
752 **/
753 BOOLEAN
754 EFIAPI
755 TdesCbcEncrypt (
756 IN VOID *TdesContext,
757 IN CONST UINT8 *Input,
758 IN UINTN InputSize,
759 IN CONST UINT8 *Ivec,
760 OUT UINT8 *Output
761 );
762
763 /**
764 Performs TDES decryption on a data buffer of the specified size in CBC mode.
765
766 This function performs TDES decryption on data buffer pointed by Input, of specified
767 size of InputSize, in CBC mode.
768 InputSize must be multiple of block size (8 bytes). This function does not perform
769 padding. Caller must perform padding, if necessary, to ensure valid input data size.
770 Initialization vector should be one block size (8 bytes).
771 TdesContext should be already correctly initialized by TdesInit(). Behavior with
772 invalid TDES context is undefined.
773
774 If TdesContext is NULL, then ASSERT().
775 If Input is NULL, then ASSERT().
776 If InputSize is not multiple of block size (8 bytes), then ASSERT().
777 If Ivec is NULL, then ASSERT().
778 If Output is NULL, then ASSERT().
779
780 @param[in] TdesContext Pointer to the TDES context.
781 @param[in] Input Pointer to the buffer containing the data to be encrypted.
782 @param[in] InputSize Size of the Input buffer in bytes.
783 @param[in] Ivec Pointer to initialization vector.
784 @param[out] Output Pointer to a buffer that receives the TDES encryption output.
785
786 @retval TRUE TDES decryption succeeded.
787 @retval FALSE TDES decryption failed.
788
789 **/
790 BOOLEAN
791 EFIAPI
792 TdesCbcDecrypt (
793 IN VOID *TdesContext,
794 IN CONST UINT8 *Input,
795 IN UINTN InputSize,
796 IN CONST UINT8 *Ivec,
797 OUT UINT8 *Output
798 );
799
800 /**
801 Retrieves the size, in bytes, of the context buffer required for AES operations.
802
803 @return The size, in bytes, of the context buffer required for AES operations.
804
805 **/
806 UINTN
807 EFIAPI
808 AesGetContextSize (
809 VOID
810 );
811
812 /**
813 Initializes user-supplied memory as AES context for subsequent use.
814
815 This function initializes user-supplied memory pointed by AesContext as AES context.
816 In addtion, it sets up all AES key materials for subsequent encryption and decryption
817 operations.
818 There are 3 options for key length, 128 bits, 192 bits, and 256 bits.
819
820 If AesContext is NULL, then ASSERT().
821 If Key is NULL, then ASSERT().
822 If KeyLength is not valid, then ASSERT().
823
824 @param[out] AesContext Pointer to AES context being initialized.
825 @param[in] Key Pointer to the user-supplied AES key.
826 @param[in] KeyLength Length of AES key in bits.
827
828 @retval TRUE AES context initialization succeeded.
829 @retval FALSE AES context initialization failed.
830
831 **/
832 BOOLEAN
833 EFIAPI
834 AesInit (
835 OUT VOID *AesContext,
836 IN CONST UINT8 *Key,
837 IN UINTN KeyLength
838 );
839
840 /**
841 Performs AES encryption on a data buffer of the specified size in ECB mode.
842
843 This function performs AES encryption on data buffer pointed by Input, of specified
844 size of InputSize, in ECB mode.
845 InputSize must be multiple of block size (16 bytes). This function does not perform
846 padding. Caller must perform padding, if necessary, to ensure valid input data size.
847 AesContext should be already correctly initialized by AesInit(). Behavior with
848 invalid AES context is undefined.
849
850 If AesContext is NULL, then ASSERT().
851 If Input is NULL, then ASSERT().
852 If InputSize is not multiple of block size (16 bytes), then ASSERT().
853 If Output is NULL, then ASSERT().
854
855 @param[in] AesContext Pointer to the AES context.
856 @param[in] Input Pointer to the buffer containing the data to be encrypted.
857 @param[in] InputSize Size of the Input buffer in bytes.
858 @param[out] Output Pointer to a buffer that receives the AES encryption output.
859
860 @retval TRUE AES encryption succeeded.
861 @retval FALSE AES encryption failed.
862
863 **/
864 BOOLEAN
865 EFIAPI
866 AesEcbEncrypt (
867 IN VOID *AesContext,
868 IN CONST UINT8 *Input,
869 IN UINTN InputSize,
870 OUT UINT8 *Output
871 );
872
873 /**
874 Performs AES decryption on a data buffer of the specified size in ECB mode.
875
876 This function performs AES decryption on data buffer pointed by Input, of specified
877 size of InputSize, in ECB mode.
878 InputSize must be multiple of block size (16 bytes). This function does not perform
879 padding. Caller must perform padding, if necessary, to ensure valid input data size.
880 AesContext should be already correctly initialized by AesInit(). Behavior with
881 invalid AES context is undefined.
882
883 If AesContext is NULL, then ASSERT().
884 If Input is NULL, then ASSERT().
885 If InputSize is not multiple of block size (16 bytes), then ASSERT().
886 If Output is NULL, then ASSERT().
887
888 @param[in] AesContext Pointer to the AES context.
889 @param[in] Input Pointer to the buffer containing the data to be decrypted.
890 @param[in] InputSize Size of the Input buffer in bytes.
891 @param[out] Output Pointer to a buffer that receives the AES decryption output.
892
893 @retval TRUE AES decryption succeeded.
894 @retval FALSE AES decryption failed.
895
896 **/
897 BOOLEAN
898 EFIAPI
899 AesEcbDecrypt (
900 IN VOID *AesContext,
901 IN CONST UINT8 *Input,
902 IN UINTN InputSize,
903 OUT UINT8 *Output
904 );
905
906 /**
907 Performs AES encryption on a data buffer of the specified size in CBC mode.
908
909 This function performs AES encryption on data buffer pointed by Input, of specified
910 size of InputSize, in CBC mode.
911 InputSize must be multiple of block size (16 bytes). This function does not perform
912 padding. Caller must perform padding, if necessary, to ensure valid input data size.
913 Initialization vector should be one block size (16 bytes).
914 AesContext should be already correctly initialized by AesInit(). Behavior with
915 invalid AES context is undefined.
916
917 If AesContext is NULL, then ASSERT().
918 If Input is NULL, then ASSERT().
919 If InputSize is not multiple of block size (16 bytes), then ASSERT().
920 If Ivec is NULL, then ASSERT().
921 If Output is NULL, then ASSERT().
922
923 @param[in] AesContext Pointer to the AES context.
924 @param[in] Input Pointer to the buffer containing the data to be encrypted.
925 @param[in] InputSize Size of the Input buffer in bytes.
926 @param[in] Ivec Pointer to initialization vector.
927 @param[out] Output Pointer to a buffer that receives the AES encryption output.
928
929 @retval TRUE AES encryption succeeded.
930 @retval FALSE AES encryption failed.
931
932 **/
933 BOOLEAN
934 EFIAPI
935 AesCbcEncrypt (
936 IN VOID *AesContext,
937 IN CONST UINT8 *Input,
938 IN UINTN InputSize,
939 IN CONST UINT8 *Ivec,
940 OUT UINT8 *Output
941 );
942
943 /**
944 Performs AES decryption on a data buffer of the specified size in CBC mode.
945
946 This function performs AES decryption on data buffer pointed by Input, of specified
947 size of InputSize, in CBC mode.
948 InputSize must be multiple of block size (16 bytes). This function does not perform
949 padding. Caller must perform padding, if necessary, to ensure valid input data size.
950 Initialization vector should be one block size (16 bytes).
951 AesContext should be already correctly initialized by AesInit(). Behavior with
952 invalid AES context is undefined.
953
954 If AesContext is NULL, then ASSERT().
955 If Input is NULL, then ASSERT().
956 If InputSize is not multiple of block size (16 bytes), then ASSERT().
957 If Ivec is NULL, then ASSERT().
958 If Output is NULL, then ASSERT().
959
960 @param[in] AesContext Pointer to the AES context.
961 @param[in] Input Pointer to the buffer containing the data to be encrypted.
962 @param[in] InputSize Size of the Input buffer in bytes.
963 @param[in] Ivec Pointer to initialization vector.
964 @param[out] Output Pointer to a buffer that receives the AES encryption output.
965
966 @retval TRUE AES decryption succeeded.
967 @retval FALSE AES decryption failed.
968
969 **/
970 BOOLEAN
971 EFIAPI
972 AesCbcDecrypt (
973 IN VOID *AesContext,
974 IN CONST UINT8 *Input,
975 IN UINTN InputSize,
976 IN CONST UINT8 *Ivec,
977 OUT UINT8 *Output
978 );
979
980 /**
981 Retrieves the size, in bytes, of the context buffer required for ARC4 operations.
982
983 @return The size, in bytes, of the context buffer required for ARC4 operations.
984
985 **/
986 UINTN
987 EFIAPI
988 Arc4GetContextSize (
989 VOID
990 );
991
992 /**
993 Initializes user-supplied memory as ARC4 context for subsequent use.
994
995 This function initializes user-supplied memory pointed by Arc4Context as ARC4 context.
996 In addtion, it sets up all ARC4 key materials for subsequent encryption and decryption
997 operations.
998
999 If Arc4Context is NULL, then ASSERT().
1000 If Key is NULL, then ASSERT().
1001 If KeySize does not in the range of [5, 256] bytes, then ASSERT().
1002
1003 @param[out] Arc4Context Pointer to ARC4 context being initialized.
1004 @param[in] Key Pointer to the user-supplied ARC4 key.
1005 @param[in] KeySize Size of ARC4 key in bytes.
1006
1007 @retval TRUE ARC4 context initialization succeeded.
1008 @retval FALSE ARC4 context initialization failed.
1009
1010 **/
1011 BOOLEAN
1012 EFIAPI
1013 Arc4Init (
1014 OUT VOID *Arc4Context,
1015 IN CONST UINT8 *Key,
1016 IN UINTN KeySize
1017 );
1018
1019 /**
1020 Performs ARC4 encryption on a data buffer of the specified size.
1021
1022 This function performs ARC4 encryption on data buffer pointed by Input, of specified
1023 size of InputSize.
1024 Arc4Context should be already correctly initialized by Arc4Init(). Behavior with
1025 invalid ARC4 context is undefined.
1026
1027 If Arc4Context is NULL, then ASSERT().
1028 If Input is NULL, then ASSERT().
1029 If Output is NULL, then ASSERT().
1030
1031 @param[in] Arc4Context Pointer to the ARC4 context.
1032 @param[in] Input Pointer to the buffer containing the data to be encrypted.
1033 @param[in] InputSize Size of the Input buffer in bytes.
1034 @param[out] Output Pointer to a buffer that receives the ARC4 encryption output.
1035
1036 @retval TRUE ARC4 encryption succeeded.
1037 @retval FALSE ARC4 encryption failed.
1038
1039 **/
1040 BOOLEAN
1041 EFIAPI
1042 Arc4Encrypt (
1043 IN OUT VOID *Arc4Context,
1044 IN CONST UINT8 *Input,
1045 IN UINTN InputSize,
1046 OUT UINT8 *Output
1047 );
1048
1049 /**
1050 Performs ARC4 decryption on a data buffer of the specified size.
1051
1052 This function performs ARC4 decryption on data buffer pointed by Input, of specified
1053 size of InputSize.
1054 Arc4Context should be already correctly initialized by Arc4Init(). Behavior with
1055 invalid ARC4 context is undefined.
1056
1057 If Arc4Context is NULL, then ASSERT().
1058 If Input is NULL, then ASSERT().
1059 If Output is NULL, then ASSERT().
1060
1061 @param[in] Arc4Context Pointer to the ARC4 context.
1062 @param[in] Input Pointer to the buffer containing the data to be decrypted.
1063 @param[in] InputSize Size of the Input buffer in bytes.
1064 @param[out] Output Pointer to a buffer that receives the ARC4 decryption output.
1065
1066 @retval TRUE ARC4 decryption succeeded.
1067 @retval FALSE ARC4 decryption failed.
1068
1069 **/
1070 BOOLEAN
1071 EFIAPI
1072 Arc4Decrypt (
1073 IN OUT VOID *Arc4Context,
1074 IN UINT8 *Input,
1075 IN UINTN InputSize,
1076 OUT UINT8 *Output
1077 );
1078
1079 /**
1080 Resets the ARC4 context to the initial state.
1081
1082 The function resets the ARC4 context to the state it had immediately after the
1083 ARC4Init() function call.
1084 Contrary to ARC4Init(), Arc4Reset() requires no secret key as input, but ARC4 context
1085 should be already correctly initialized by ARC4Init().
1086
1087 If Arc4Context is NULL, then ASSERT().
1088
1089 @param[in, out] Arc4Context Pointer to the ARC4 context.
1090
1091 @retval TRUE ARC4 reset succeeded.
1092 @retval FALSE ARC4 reset failed.
1093
1094 **/
1095 BOOLEAN
1096 EFIAPI
1097 Arc4Reset (
1098 IN OUT VOID *Arc4Context
1099 );
1100
1101 //=====================================================================================
1102 // Asymmetric Cryptography Primitive
1103 //=====================================================================================
1104
1105 /**
1106 Allocates and initializes one RSA context for subsequent use.
1107
1108 @return Pointer to the RSA context that has been initialized.
1109 If the allocations fails, RsaNew() returns NULL.
1110
1111 **/
1112 VOID *
1113 EFIAPI
1114 RsaNew (
1115 VOID
1116 );
1117
1118 /**
1119 Release the specified RSA context.
1120
1121 If RsaContext is NULL, then ASSERT().
1122
1123 @param[in] RsaContext Pointer to the RSA context to be released.
1124
1125 **/
1126 VOID
1127 EFIAPI
1128 RsaFree (
1129 IN VOID *RsaContext
1130 );
1131
1132 /**
1133 Sets the tag-designated key component into the established RSA context.
1134
1135 This function sets the tag-designated RSA key component into the established
1136 RSA context from the user-specified non-negative integer (octet string format
1137 represented in RSA PKCS#1).
1138 If BigNumber is NULL, then the specified key componenet in RSA context is cleared.
1139
1140 If RsaContext is NULL, then ASSERT().
1141
1142 @param[in, out] RsaContext Pointer to RSA context being set.
1143 @param[in] KeyTag Tag of RSA key component being set.
1144 @param[in] BigNumber Pointer to octet integer buffer.
1145 If NULL, then the specified key componenet in RSA
1146 context is cleared.
1147 @param[in] BnSize Size of big number buffer in bytes.
1148 If BigNumber is NULL, then it is ignored.
1149
1150 @retval TRUE RSA key component was set successfully.
1151 @retval FALSE Invalid RSA key component tag.
1152
1153 **/
1154 BOOLEAN
1155 EFIAPI
1156 RsaSetKey (
1157 IN OUT VOID *RsaContext,
1158 IN RSA_KEY_TAG KeyTag,
1159 IN CONST UINT8 *BigNumber,
1160 IN UINTN BnSize
1161 );
1162
1163 /**
1164 Gets the tag-designated RSA key component from the established RSA context.
1165
1166 This function retrieves the tag-designated RSA key component from the
1167 established RSA context as a non-negative integer (octet string format
1168 represented in RSA PKCS#1).
1169 If specified key component has not been set or has been cleared, then returned
1170 BnSize is set to 0.
1171 If the BigNumber buffer is too small to hold the contents of the key, FALSE
1172 is returned and BnSize is set to the required buffer size to obtain the key.
1173
1174 If RsaContext is NULL, then ASSERT().
1175 If BnSize is NULL, then ASSERT().
1176 If BnSize is large enough but BigNumber is NULL, then ASSERT().
1177
1178 @param[in, out] RsaContext Pointer to RSA context being set.
1179 @param[in] KeyTag Tag of RSA key component being set.
1180 @param[out] BigNumber Pointer to octet integer buffer.
1181 @param[in, out] BnSize On input, the size of big number buffer in bytes.
1182 On output, the size of data returned in big number buffer in bytes.
1183
1184 @retval TRUE RSA key component was retrieved successfully.
1185 @retval FALSE Invalid RSA key component tag.
1186 @retval FALSE BnSize is too small.
1187
1188 **/
1189 BOOLEAN
1190 EFIAPI
1191 RsaGetKey (
1192 IN OUT VOID *RsaContext,
1193 IN RSA_KEY_TAG KeyTag,
1194 OUT UINT8 *BigNumber,
1195 IN OUT UINTN *BnSize
1196 );
1197
1198 /**
1199 Generates RSA key components.
1200
1201 This function generates RSA key components. It takes RSA public exponent E and
1202 length in bits of RSA modulus N as input, and generates all key components.
1203 If PublicExponent is NULL, the default RSA public exponent (0x10001) will be used.
1204
1205 Before this function can be invoked, pseudorandom number generator must be correctly
1206 initialized by RandomSeed().
1207
1208 If RsaContext is NULL, then ASSERT().
1209
1210 @param[in, out] RsaContext Pointer to RSA context being set.
1211 @param[in] ModulusLength Length of RSA modulus N in bits.
1212 @param[in] PublicExponent Pointer to RSA public exponent.
1213 @param[in] PublicExponentSize Size of RSA public exponent buffer in bytes.
1214
1215 @retval TRUE RSA key component was generated successfully.
1216 @retval FALSE Invalid RSA key component tag.
1217
1218 **/
1219 BOOLEAN
1220 EFIAPI
1221 RsaGenerateKey (
1222 IN OUT VOID *RsaContext,
1223 IN UINTN ModulusLength,
1224 IN CONST UINT8 *PublicExponent,
1225 IN UINTN PublicExponentSize
1226 );
1227
1228 /**
1229 Validates key components of RSA context.
1230
1231 This function validates key compoents of RSA context in following aspects:
1232 - Whether p is a prime
1233 - Whether q is a prime
1234 - Whether n = p * q
1235 - Whether d*e = 1 mod lcm(p-1,q-1)
1236
1237 If RsaContext is NULL, then ASSERT().
1238
1239 @param[in] RsaContext Pointer to RSA context to check.
1240
1241 @retval TRUE RSA key components are valid.
1242 @retval FALSE RSA key components are not valid.
1243
1244 **/
1245 BOOLEAN
1246 EFIAPI
1247 RsaCheckKey (
1248 IN VOID *RsaContext
1249 );
1250
1251 /**
1252 Carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme.
1253
1254 This function carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme defined in
1255 RSA PKCS#1.
1256 If the Signature buffer is too small to hold the contents of signature, FALSE
1257 is returned and SigSize is set to the required buffer size to obtain the signature.
1258
1259 If RsaContext is NULL, then ASSERT().
1260 If MessageHash is NULL, then ASSERT().
1261 If HashSize is not equal to the size of MD5, SHA-1, SHA-256, SHA-224, SHA-512 or SHA-384 digest, then ASSERT().
1262 If SigSize is large enough but Signature is NULL, then ASSERT().
1263
1264 @param[in] RsaContext Pointer to RSA context for signature generation.
1265 @param[in] MessageHash Pointer to octet message hash to be signed.
1266 @param[in] HashSize Size of the message hash in bytes.
1267 @param[out] Signature Pointer to buffer to receive RSA PKCS1-v1_5 signature.
1268 @param[in, out] SigSize On input, the size of Signature buffer in bytes.
1269 On output, the size of data returned in Signature buffer in bytes.
1270
1271 @retval TRUE Signature successfully generated in PKCS1-v1_5.
1272 @retval FALSE Signature generation failed.
1273 @retval FALSE SigSize is too small.
1274
1275 **/
1276 BOOLEAN
1277 EFIAPI
1278 RsaPkcs1Sign (
1279 IN VOID *RsaContext,
1280 IN CONST UINT8 *MessageHash,
1281 IN UINTN HashSize,
1282 OUT UINT8 *Signature,
1283 IN OUT UINTN *SigSize
1284 );
1285
1286 /**
1287 Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in
1288 RSA PKCS#1.
1289
1290 If RsaContext is NULL, then ASSERT().
1291 If MessageHash is NULL, then ASSERT().
1292 If Signature is NULL, then ASSERT().
1293 If HashSize is not equal to the size of MD5, SHA-1, SHA-256, SHA-224, SHA-512 or SHA-384 digest, then ASSERT().
1294
1295 @param[in] RsaContext Pointer to RSA context for signature verification.
1296 @param[in] MessageHash Pointer to octet message hash to be checked.
1297 @param[in] HashSize Size of the message hash in bytes.
1298 @param[in] Signature Pointer to RSA PKCS1-v1_5 signature to be verified.
1299 @param[in] SigSize Size of signature in bytes.
1300
1301 @retval TRUE Valid signature encoded in PKCS1-v1_5.
1302 @retval FALSE Invalid signature or invalid RSA context.
1303
1304 **/
1305 BOOLEAN
1306 EFIAPI
1307 RsaPkcs1Verify (
1308 IN VOID *RsaContext,
1309 IN CONST UINT8 *MessageHash,
1310 IN UINTN HashSize,
1311 IN UINT8 *Signature,
1312 IN UINTN SigSize
1313 );
1314
1315 /**
1316 Verifies the validility of a PKCS#7 signed data as described in "PKCS #7: Cryptographic
1317 Message Syntax Standard".
1318
1319 If P7Data is NULL, then ASSERT().
1320
1321 @param[in] P7Data Pointer to the PKCS#7 message to verify.
1322 @param[in] P7Size Size of the PKCS#7 message in bytes.
1323 @param[in] TrustedCert Pointer to a trusted/root certificate encoded in DER, which
1324 is used for certificate chain verification.
1325 @param[in] CertSize Size of the trusted certificate in bytes.
1326 @param[in] InData Pointer to the content to be verified.
1327 @param[in] DataSize Size of InData in bytes.
1328
1329 @retval TRUE The specified PKCS#7 signed data is valid.
1330 @retval FALSE Invalid PKCS#7 signed data.
1331
1332 **/
1333 BOOLEAN
1334 EFIAPI
1335 Pkcs7Verify (
1336 IN CONST UINT8 *P7Data,
1337 IN UINTN P7Size,
1338 IN CONST UINT8 *TrustedCert,
1339 IN UINTN CertSize,
1340 IN CONST UINT8 *InData,
1341 IN UINTN DataSize
1342 );
1343
1344 //=====================================================================================
1345 // DH Key Exchange Primitive
1346 //=====================================================================================
1347
1348 /**
1349 Allocates and Initializes one Diffie-Hellman Context for subsequent use.
1350
1351 @return Pointer to the Diffie-Hellman Context that has been initialized.
1352 If the allocations fails, DhNew() returns NULL.
1353
1354 **/
1355 VOID *
1356 EFIAPI
1357 DhNew (
1358 VOID
1359 );
1360
1361 /**
1362 Release the specified DH context.
1363
1364 If DhContext is NULL, then ASSERT().
1365
1366 @param[in] DhContext Pointer to the DH context to be released.
1367
1368 **/
1369 VOID
1370 EFIAPI
1371 DhFree (
1372 IN VOID *DhContext
1373 );
1374
1375 /**
1376 Generates DH parameter.
1377
1378 Given generator g, and length of prime number p in bits, this function generates p,
1379 and sets DH context according to value of g and p.
1380
1381 Before this function can be invoked, pseudorandom number generator must be correctly
1382 initialized by RandomSeed().
1383
1384 If DhContext is NULL, then ASSERT().
1385 If Prime is NULL, then ASSERT().
1386
1387 @param[in, out] DhContext Pointer to the DH context.
1388 @param[in] Generator Value of generator.
1389 @param[in] PrimeLength Length in bits of prime to be generated.
1390 @param[out] Prime Pointer to the buffer to receive the generated prime number.
1391
1392 @retval TRUE DH pamameter generation succeeded.
1393 @retval FALSE Value of Generator is not supported.
1394 @retval FALSE PRNG fails to generate random prime number with PrimeLength.
1395
1396 **/
1397 BOOLEAN
1398 EFIAPI
1399 DhGenerateParameter (
1400 IN OUT VOID *DhContext,
1401 IN UINTN Generator,
1402 IN UINTN PrimeLength,
1403 OUT UINT8 *Prime
1404 );
1405
1406 /**
1407 Sets generator and prime parameters for DH.
1408
1409 Given generator g, and prime number p, this function and sets DH
1410 context accordingly.
1411
1412 If DhContext is NULL, then ASSERT().
1413 If Prime is NULL, then ASSERT().
1414
1415 @param[in, out] DhContext Pointer to the DH context.
1416 @param[in] Generator Value of generator.
1417 @param[in] PrimeLength Length in bits of prime to be generated.
1418 @param[in] Prime Pointer to the prime number.
1419
1420 @retval TRUE DH pamameter setting succeeded.
1421 @retval FALSE Value of Generator is not supported.
1422 @retval FALSE Value of Generator is not suitable for the Prime.
1423 @retval FALSE Value of Prime is not a prime number.
1424 @retval FALSE Value of Prime is not a safe prime number.
1425
1426 **/
1427 BOOLEAN
1428 EFIAPI
1429 DhSetParameter (
1430 IN OUT VOID *DhContext,
1431 IN UINTN Generator,
1432 IN UINTN PrimeLength,
1433 IN CONST UINT8 *Prime
1434 );
1435
1436 /**
1437 Generates DH public key.
1438
1439 This function generates random secret exponent, and computes the public key, which is
1440 returned via parameter PublicKey and PublicKeySize. DH context is updated accordingly.
1441 If the PublicKey buffer is too small to hold the public key, FALSE is returned and
1442 PublicKeySize is set to the required buffer size to obtain the public key.
1443
1444 If DhContext is NULL, then ASSERT().
1445 If PublicKeySize is NULL, then ASSERT().
1446 If PublicKeySize is large enough but PublicKey is NULL, then ASSERT().
1447
1448 @param[in, out] DhContext Pointer to the DH context.
1449 @param[out] PublicKey Pointer to the buffer to receive generated public key.
1450 @param[in, out] PublicKeySize On input, the size of PublicKey buffer in bytes.
1451 On output, the size of data returned in PublicKey buffer in bytes.
1452
1453 @retval TRUE DH public key generation succeeded.
1454 @retval FALSE DH public key generation failed.
1455 @retval FALSE PublicKeySize is not large enough.
1456
1457 **/
1458 BOOLEAN
1459 EFIAPI
1460 DhGenerateKey (
1461 IN OUT VOID *DhContext,
1462 OUT UINT8 *PublicKey,
1463 IN OUT UINTN *PublicKeySize
1464 );
1465
1466 /**
1467 Computes exchanged common key.
1468
1469 Given peer's public key, this function computes the exchanged common key, based on its own
1470 context including value of prime modulus and random secret exponent.
1471
1472 If DhContext is NULL, then ASSERT().
1473 If PeerPublicKey is NULL, then ASSERT().
1474 If KeySize is NULL, then ASSERT().
1475 If KeySize is large enough but Key is NULL, then ASSERT().
1476
1477 @param[in, out] DhContext Pointer to the DH context.
1478 @param[in] PeerPublicKey Pointer to the peer's public key.
1479 @param[in] PeerPublicKeySize Size of peer's public key in bytes.
1480 @param[out] Key Pointer to the buffer to receive generated key.
1481 @param[in, out] KeySize On input, the size of Key buffer in bytes.
1482 On output, the size of data returned in Key buffer in bytes.
1483
1484 @retval TRUE DH exchanged key generation succeeded.
1485 @retval FALSE DH exchanged key generation failed.
1486 @retval FALSE KeySize is not large enough.
1487
1488 **/
1489 BOOLEAN
1490 EFIAPI
1491 DhComputeKey (
1492 IN OUT VOID *DhContext,
1493 IN CONST UINT8 *PeerPublicKey,
1494 IN UINTN PeerPublicKeySize,
1495 OUT UINT8 *Key,
1496 IN OUT UINTN *KeySize
1497 );
1498
1499 //=====================================================================================
1500 // Pseudo-Random Generation Primitive
1501 //=====================================================================================
1502
1503 /**
1504 Sets up the seed value for the pseudorandom number generator.
1505
1506 This function sets up the seed value for the pseudorandom number generator.
1507 If Seed is not NULL, then the seed passed in is used.
1508 If Seed is NULL, then default seed is used.
1509
1510 @param[in] Seed Pointer to seed value.
1511 If NULL, default seed is used.
1512 @param[in] SeedSize Size of seed value.
1513 If Seed is NULL, this parameter is ignored.
1514
1515 @retval TRUE Pseudorandom number generator has enough entropy for random generation.
1516 @retval FALSE Pseudorandom number generator does not have enough entropy for random generation.
1517
1518 **/
1519 BOOLEAN
1520 EFIAPI
1521 RandomSeed (
1522 IN CONST UINT8 *Seed OPTIONAL,
1523 IN UINTN SeedSize
1524 );
1525
1526 /**
1527 Generates a pseudorandom byte stream of the specified size.
1528
1529 If Output is NULL, then ASSERT().
1530
1531 @param[out] Output Pointer to buffer to receive random value.
1532 @param[in] Size Size of randome bytes to generate.
1533
1534 @retval TRUE Pseudorandom byte stream generated successfully.
1535 @retval FALSE Pseudorandom number generator fails to generate due to lack of entropy.
1536
1537 **/
1538 BOOLEAN
1539 EFIAPI
1540 RandomBytes (
1541 OUT UINT8 *Output,
1542 IN UINTN Size
1543 );
1544
1545 #endif // __BASE_CRYPT_LIB_H__
RandomBytes
BOOLEAN RandomBytes(OUT UINT8 *Output, IN UINTN Size)
Generates a pseudorandom byte stream of the specified size.
HmacMd5Init
BOOLEAN HmacMd5Init(OUT VOID *HmacMd5Context, IN CONST UINT8 *Key, IN UINTN KeySize)
Initializes user-supplied memory pointed by HmacMd5Context as HMAC-MD5 context for subsequent use...
DhComputeKey
BOOLEAN DhComputeKey(IN OUT VOID *DhContext, IN CONST UINT8 *PeerPublicKey, IN UINTN PeerPublicKeySize, OUT UINT8 *Key, IN OUT UINTN *KeySize)
Computes exchanged common key.
Sha256Update
BOOLEAN Sha256Update(IN OUT VOID *Sha256Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates SHA-256 context.
RSA_KEY_TAG
RSA_KEY_TAG
RSA Key Tags Definition used in RsaSetKey() function for key component identification.
Definition: BaseCryptLib.h:69
TdesEcbEncrypt
BOOLEAN TdesEcbEncrypt(IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs TDES encryption on a data buffer of the specified size in ECB mode.
HmacMd5Duplicate
BOOLEAN HmacMd5Duplicate(IN CONST VOID *HmacMd5Context, OUT VOID *NewHmacMd5Context)
Makes a copy of an existing HMAC-MD5 context.
Sha1Init
BOOLEAN Sha1Init(OUT VOID *Sha1Context)
Initializes user-supplied memory pointed by Sha1Context as SHA-1 hash context for subsequent use...
RsaPkcs1Sign
BOOLEAN RsaPkcs1Sign(IN VOID *RsaContext, IN CONST UINT8 *MessageHash, IN UINTN HashSize, OUT UINT8 *Signature, IN OUT UINTN *SigSize)
Carries out the RSA-SSA signature generation with EMSA-PKCS1-v1_5 encoding scheme.
RsaSetKey
BOOLEAN RsaSetKey(IN OUT VOID *RsaContext, IN RSA_KEY_TAG KeyTag, IN CONST UINT8 *BigNumber, IN UINTN BnSize)
Sets the tag-designated key component into the established RSA context.
RsaKeyQ
RSA secret prime factor of Modules (q)
Definition: BaseCryptLib.h:74
HmacMd5Update
BOOLEAN HmacMd5Update(IN OUT VOID *HmacMd5Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates HMAC-MD5 context.
Md5Init
BOOLEAN Md5Init(OUT VOID *Md5Context)
Initializes user-supplied memory pointed by Md5Context as MD5 hash context for subsequent use...
Sha256Final
BOOLEAN Sha256Final(IN OUT VOID *Sha256Context, OUT UINT8 *HashValue)
Completes computation of the SHA-256 digest value.
RsaGetKey
BOOLEAN RsaGetKey(IN OUT VOID *RsaContext, IN RSA_KEY_TAG KeyTag, OUT UINT8 *BigNumber, IN OUT UINTN *BnSize)
Gets the tag-designated RSA key component from the established RSA context.
HmacMd5Final
BOOLEAN HmacMd5Final(IN OUT VOID *HmacMd5Context, OUT UINT8 *HmacValue)
Completes computation of the HMAC-MD5 digest value.
RsaKeyQInv
The CRT coefficient (== 1/q mod p)
Definition: BaseCryptLib.h:77
HmacSha1Init
BOOLEAN HmacSha1Init(OUT VOID *HmacSha1Context, IN CONST UINT8 *Key, IN UINTN KeySize)
Initializes user-supplied memory pointed by HmacSha1Context as HMAC-SHA1 context for subsequent use...
Sha256GetContextSize
UINTN Sha256GetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for SHA-256 hash operations.
HmacMd5GetContextSize
UINTN HmacMd5GetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for HMAC-MD5 operations.
Arc4Decrypt
BOOLEAN Arc4Decrypt(IN OUT VOID *Arc4Context, IN UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs ARC4 decryption on a data buffer of the specified size.
TdesInit
BOOLEAN TdesInit(OUT VOID *TdesContext, IN CONST UINT8 *Key, IN UINTN KeyLength)
Initializes user-supplied memory as TDES context for subsequent use.
RsaKeyN
RSA public Modulus (N)
Definition: BaseCryptLib.h:70
Sha1GetContextSize
UINTN Sha1GetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for SHA-1 hash operations.
RsaPkcs1Verify
BOOLEAN RsaPkcs1Verify(IN VOID *RsaContext, IN CONST UINT8 *MessageHash, IN UINTN HashSize, IN UINT8 *Signature, IN UINTN SigSize)
Verifies the RSA-SSA signature with EMSA-PKCS1-v1_5 encoding scheme defined in RSA PKCS#1...
Sha256Duplicate
BOOLEAN Sha256Duplicate(IN CONST VOID *Sha256Context, OUT VOID *NewSha256Context)
Makes a copy of an existing SHA-256 context.
RsaKeyDp
p's CRT exponent (== d mod (p - 1))
Definition: BaseCryptLib.h:75
RsaKeyD
RSA Private exponent (d)
Definition: BaseCryptLib.h:72
Arc4GetContextSize
UINTN Arc4GetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for ARC4 operations. ...
RsaFree
VOID RsaFree(IN VOID *RsaContext)
Release the specified RSA context.
DhGenerateKey
BOOLEAN DhGenerateKey(IN OUT VOID *DhContext, OUT UINT8 *PublicKey, IN OUT UINTN *PublicKeySize)
Generates DH public key.
RsaGenerateKey
BOOLEAN RsaGenerateKey(IN OUT VOID *RsaContext, IN UINTN ModulusLength, IN CONST UINT8 *PublicExponent, IN UINTN PublicExponentSize)
Generates RSA key components.
DhGenerateParameter
BOOLEAN DhGenerateParameter(IN OUT VOID *DhContext, IN UINTN Generator, IN UINTN PrimeLength, OUT UINT8 *Prime)
Generates DH parameter.
RsaKeyDq
q's CRT exponent (== d mod (q - 1))
Definition: BaseCryptLib.h:76
AesCbcDecrypt
BOOLEAN AesCbcDecrypt(IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs AES decryption on a data buffer of the specified size in CBC mode.
Md5Final
BOOLEAN Md5Final(IN OUT VOID *Md5Context, OUT UINT8 *HashValue)
Completes computation of the MD5 digest value.
AesCbcEncrypt
BOOLEAN AesCbcEncrypt(IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs AES encryption on a data buffer of the specified size in CBC mode.
HmacSha1Final
BOOLEAN HmacSha1Final(IN OUT VOID *HmacSha1Context, OUT UINT8 *HmacValue)
Completes computation of the HMAC-SHA1 digest value.
AesGetContextSize
UINTN AesGetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for AES operations.
Sha1Update
BOOLEAN Sha1Update(IN OUT VOID *Sha1Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates SHA-1 context.
TdesGetContextSize
UINTN TdesGetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for TDES operations. ...
DhSetParameter
BOOLEAN DhSetParameter(IN OUT VOID *DhContext, IN UINTN Generator, IN UINTN PrimeLength, IN CONST UINT8 *Prime)
Sets generator and prime parameters for DH.
RsaCheckKey
BOOLEAN RsaCheckKey(IN VOID *RsaContext)
Validates key components of RSA context.
Arc4Reset
BOOLEAN Arc4Reset(IN OUT VOID *Arc4Context)
Resets the ARC4 context to the initial state.
AesEcbDecrypt
BOOLEAN AesEcbDecrypt(IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs AES decryption on a data buffer of the specified size in ECB mode.
Md5Duplicate
BOOLEAN Md5Duplicate(IN CONST VOID *Md5Context, OUT VOID *NewMd5Context)
Makes a copy of an existing MD5 context.
RsaKeyE
RSA Public exponent (e)
Definition: BaseCryptLib.h:71
AesEcbEncrypt
BOOLEAN AesEcbEncrypt(IN VOID *AesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs AES encryption on a data buffer of the specified size in ECB mode.
TdesCbcEncrypt
BOOLEAN TdesCbcEncrypt(IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs TDES encryption on a data buffer of the specified size in CBC mode.
Sha1Final
BOOLEAN Sha1Final(IN OUT VOID *Sha1Context, OUT UINT8 *HashValue)
Completes computation of the SHA-1 digest value.
Md5GetContextSize
UINTN Md5GetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for MD5 hash operations.
RandomSeed
BOOLEAN RandomSeed(IN CONST UINT8 *Seed OPTIONAL, IN UINTN SeedSize)
Sets up the seed value for the pseudorandom number generator.
DhFree
VOID DhFree(IN VOID *DhContext)
Release the specified DH context.
DhNew
VOID * DhNew(VOID)
Allocates and Initializes one Diffie-Hellman Context for subsequent use.
RsaKeyP
RSA secret prime factor of Modulus (p)
Definition: BaseCryptLib.h:73
TdesCbcDecrypt
BOOLEAN TdesCbcDecrypt(IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, IN CONST UINT8 *Ivec, OUT UINT8 *Output)
Performs TDES decryption on a data buffer of the specified size in CBC mode.
Sha256Init
BOOLEAN Sha256Init(OUT VOID *Sha256Context)
Initializes user-supplied memory pointed by Sha256Context as SHA-256 hash context for subsequent use...
Arc4Init
BOOLEAN Arc4Init(OUT VOID *Arc4Context, IN CONST UINT8 *Key, IN UINTN KeySize)
Initializes user-supplied memory as ARC4 context for subsequent use.
Md5Update
BOOLEAN Md5Update(IN OUT VOID *Md5Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates MD5 context.
RsaNew
VOID * RsaNew(VOID)
Allocates and initializes one RSA context for subsequent use.
TdesEcbDecrypt
BOOLEAN TdesEcbDecrypt(IN VOID *TdesContext, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs TDES decryption on a data buffer of the specified size in ECB mode.
HmacSha1Update
BOOLEAN HmacSha1Update(IN OUT VOID *HmacSha1Context, IN CONST VOID *Data, IN UINTN DataSize)
Digests the input data and updates HMAC-SHA1 context.
Arc4Encrypt
BOOLEAN Arc4Encrypt(IN OUT VOID *Arc4Context, IN CONST UINT8 *Input, IN UINTN InputSize, OUT UINT8 *Output)
Performs ARC4 encryption on a data buffer of the specified size.
HmacSha1Duplicate
BOOLEAN HmacSha1Duplicate(IN CONST VOID *HmacSha1Context, OUT VOID *NewHmacSha1Context)
Makes a copy of an existing HMAC-SHA1 context.
Sha1Duplicate
BOOLEAN Sha1Duplicate(IN CONST VOID *Sha1Context, OUT VOID *NewSha1Context)
Makes a copy of an existing SHA-1 context.
Pkcs7Verify
BOOLEAN Pkcs7Verify(IN CONST UINT8 *P7Data, IN UINTN P7Size, IN CONST UINT8 *TrustedCert, IN UINTN CertSize, IN CONST UINT8 *InData, IN UINTN DataSize)
Verifies the validility of a PKCS#7 signed data as described in "PKCS #7: Cryptographic Message Synta...
HmacSha1GetContextSize
UINTN HmacSha1GetContextSize(VOID)
Retrieves the size, in bytes, of the context buffer required for HMAC-SHA1 operations.
AesInit
BOOLEAN AesInit(OUT VOID *AesContext, IN CONST UINT8 *Key, IN UINTN KeyLength)
Initializes user-supplied memory as AES context for subsequent use.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: BaseEcFlashLib.h Source File

  • Library
BaseEcFlashLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _EC_FLASH_H_
35 #define _EC_FLASH_H_
36
37 #define IMAGE_SIGNATURE 0x2202L // Flash image signature (EC) offset.
38 #define IMAGE_VERSION_NUM 0x106L // Flash image version number offset.
39 #define IMAGE_SIZE_OFFSET 0x140L // Flash image size is stored here.
40 #define PLAT_SIG_OFFSET 0x142L // 8 byte platform signature stored here.
41 #define IMAGE_ECFW1_OFFSET 0x20000L // Offset of ECFW Image 1
42 #define IMAGE_ECFW2_OFFSET 0x1000L // Offset of ECFW Image 2(Recovery)
43
44 #define UPDATE_FULL 0x0 // update SPIHeader + ECFW1 + ECFW2
45 #define UPDATE_ECFW1 0x1 // update ECFW1
46 #define UPDATE_ECFW1_ECFW2 0x2 // update ECFW1 + ECFW2
47
48 #define TOTAL_BLKS 0x448 // Total number of 128 byte blocks.
49
50 #define FBLOCK_SIZE 128L // Flash line size
51 #define ECCOMMANDPORT 0x66 // Using EC ports for flashing.
52 #define ECSTATUSPORT 0x66
53 #define ECDATAPORT 0x62
54
55 //
56 // EC FLASH COMMANDS:
57 //
58 #define FLASHLOADER 0x91 // Command for FLASH reprogram mode.
59 #define NMIDISABLE 0x93 // Command for H8 NMI Disable.
60
61 #define INITERASE 0x01 // Load erase code into RAM and initialize
62 #define SETERASEBLKNUM 0x02 // Set block num for erase.
63 #define ERASEFLASHBLK 0x03 // Erase flash block.
64 #define BLANKCHECK 0x04 // Blank check the part.
65 #define INITPROGCODE 0x05 // Initialize programming code.
66 #define LOADFLASHBLK 0x06 // Load flash block for programming.
67 #define SETFLASHWRITEADDR 0x07 // Set starting address for writes.
68 #define PROGRAMFLASHBLK 0x08 // Program flash block.
69 #define VERIFYFLASHBLK 0x09 // Verify flash block.
70 #define ERASEFLASH 0x0A // Erase entire flash.
71 #define RESETEC 0x0B // Controller hard reset.
72 #define READFLASHBYTE 0x0C // Read a byte at address
73 #define READBLOCK 0x0D // Read a block at address
74
75 //
76 // EC RUNTIME COMMANDS:
77 //
78 #define READBYTE 0x01 // Read byte
79 #define WRITEBYTE 0x02 // Write byte
80 #define GETSWITCHSTATUS 0x0A // Get switch status
81 #define ENABLE_POWER_BTN 0x23 // Disable power button functionality
82 #define DISABLE_POWER_BTN 0x24 // Enable power button functionality
83 #define READECREVISION 0x90 // Read EC firmware revision number.
84 #define READECMEM 0x80 // Read the EC memory
85 #define QUERYSYSSTATUS 0x06 // Returns 1 byte of information about the system status
86 #define SYS_STATUS_FAN 0x40 // Fan status (1 = ON)
87 #define SYS_STATUS_DOCK 0x20 // Dock status (1 = Docked)
88 #define SYS_STATUS_AC 0x10 // AC power (1 = AC powered)
89 #define SYS_STATUS_THER 0x0F // CPU thermal state (0 ~ 9)
90
91 #define PLATFORM_UNKNOWN 0xFF // Unknown platform
92
93 #define m_CR 0x0D
94 #define m_LF 0x0A
95
96 #define PCIINDEX 0xCF8
97 #define PCIDATA 0xCFC
98 #define ICH_DEVNUM 0x1F
99 #define ICH_GPIO_BAR 0x58
100 #define FN0 0x00
101 #define NMIGPIO_REG 0x38
102 #define NMIGPIO_BIT 0x01
103 #define DEVINQSIZE 0x32
104 #define RMCMDSTRUCTSIZE 128+32
105 #define BBLKSIZE_OFFSET 0x50 // Offset of boot block size in image
106 #define EC_SEGMENT 8*1024L
107 #define TMKBC_SEGMENT 72*1024L
108 #define ECSEGSIZE_OFFSET 8768L // 8*1024 + 240h
109 #define PORT1 0x3F8
110 #define EC_TIME_OUT 0x50000
111 #define EC_STALL_TIME_OUT 100
112 #define EC_S_OBF BIT0
113 #define EC_S_IBF BIT1
114
115 /// Note that capacity and voltage are 16 bit values, thus you need to read them from
116 /// ACPI space with two reads (little Endian).
117 #define EC_VIRTUAL_BAT_STATUS 48 ///< Status of the virtual battery (present)
118 #define EC_VIRTUAL_BAT_PRESENT_MASK 0x10 ///< Bit 4 is the indicator
119
120 #define EC_REAL_BAT1_STATUS 50 ///< Status of the first real battery (present, charging)
121 #define EC_REAL_BAT1_REMAINING_PERCENT 52 ///< Remaining capacity in percentage
122 #define EC_REAL_BAT1_REMAINING_CAPACITY 89 ///< Remaining capacity in mWh
123 #define EC_REAL_BAT1_RESOLUTION_VOLTAGE 93 ///< Full resolution voltage in mV
124
125 #define EC_REAL_BAT2_STATUS 54 ///< Status of the second real battery (present, charging)
126 #define EC_REAL_BAT2_REMAINING_PERCENT 56 ///< Remaining capacity in percentage
127 #define EC_REAL_BAT2_REMAINING_CAPACITY 99 ///< Remaining capacity in mWh
128 #define EC_REAL_BAT2_RESOLUTION_VOLTAGE 103 ///< Full resolution voltage in mV
129
130 #define EC_REAL_BAT_PRESENT_MASK 0x8 ///< Bit 3 is the indicator
131 #define EC_REAL_BAT_CHARGING_MASK 0x1 ///< Bit 1 is the indicator
132
133 //
134 // Function prototypes
135 //
136 VOID WaitInputBufferEmpty(VOID);
137 VOID WaitOutputBufferFull(VOID);
138 UINT32 EraseFlashBlock(UINT32 BlkNum);
139 UINT32 WriteFlashBlock(UINT32 *FBufPtr);
140 UINT32 ComputeBuffChksum(UINT32 *BufPtr, UINT32 BufSize);
141 void SendEcCommand(UINT32 CmdNum);
142 void SendEcData(UINT32 Data);
143 UINT32 ReceiveEcData(void);
144 UINT32 NmiActive(void);
145 void Port80(UINT32);
146 void EcReset(void);
147 VOID ReadEcRegister(UINT8 Reg, UINT8 *RetValue);
148
149 EFI_STATUS EcFlash(UINT8* pFcntrlBin, UINT32 FcntrlBinSize, UINT8* pEcBin, UINT32 EcBinSize);
150 BOOLEAN IsEcVersionIdentical (UINT8* pEcBin);
151
152 //
153 // Globals
154 //
155 UINT32 FlashBuf[FBLOCK_SIZE];
156 UINT32 *FlashBufPtr;
157 UINT32 FBlkStartAddr;//ulong
158 UINT32 FlashBlock;
159 UINT32 ImageLen;
160 UINT32 ImageVer;
161 UINT64 FcntrlLen; //ulong
162 UINT64 FecSize;
163 UINT32 FcntrlLenLow;
164 UINT32 FcntrlLenHigh;
165 CHAR16 Buff[16];
166 CHAR16* ptBuff;
167 CHAR16 PlatformID[9];
168
169 UINT32 DevInquirySize;
170 UINT32 DevInquiryBuff[DEVINQSIZE];
171 UINT32* DevInqBuffPtr;
172 UINT32 RMDevCode[4];
173 CHAR16 RMProdName[10];
174 UINT32 RMCmdStruct[RMCMDSTRUCTSIZE];
175
176 #define EFI_PROPER_VERSION(MajorVer, MinorVer) (gBS->Hdr.Revision >= (MajorVer << 16 | MinorVer))
177
178 #endif
EcReset
EFI_STATUS EcReset(VOID)
Do EC reset.
ReceiveEcData
EFI_STATUS ReceiveEcData(OUT UINT8 *Data)
Receives data from Keyboard System Controller.
SendEcCommand
EFI_STATUS SendEcCommand(IN UINT8 Command)
Send a command to the Keyboard System Controller.
SendEcData
EFI_STATUS SendEcData(IN UINT8 Data)
Sends data to Keyboard System Controller.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: BasePlatformVariableLib.h Source File

  • Library
BasePlatformVariableLib.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35 #ifndef _BASE_PLATFORM_VARIABLE_LIB_H_
36 #define _BASE_PLATFORM_VARIABLE_LIB_H_
37
38 #include <Uefi.h>
39
40
41
42 /**
43 Check the SATA RAID mode and report its status.
44
45 @param[out] SataRaidModeEnabled The current status of SATA RAID mode.
46
47 @retval EFI_SUCESS This function always complete successfully.
48 @retval EFI_ACCESS_DENIED Cannot not retrieve PchSetup variables.
49 **/
50 EFI_STATUS
51 CheckSataRaidMode (
52 BOOLEAN *SataRaidModeEnabled
53 );
54
55 #endif
CheckSataRaidMode
EFI_STATUS CheckSataRaidMode(BOOLEAN *SataRaidModeEnabled)
Check the SATA RAID mode and report its status.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: BoardConfigLib.h Source File

  • Library
BoardConfigLib.h
Go to the documentation of this file.
1 /** @file
2 Function prototype of BoardConfigLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _BOARD_CONFIG_LIB_H_
36 #define _BOARD_CONFIG_LIB_H_
37
38 #define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field))
39
40 #define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE))
41
42 typedef struct {
43 UINTN Size;
44 UINTN Offset;
45 UINTN Data;
46 } CONFIG_PATCH_TABLE;
47
48 typedef struct {
49 CHAR16 *VarName;
50 GUID *VarGuid;
51 UINTN VarSize;
52 CONFIG_PATCH_TABLE *ConfigPatchTable;
53 UINTN ConfigPatchTableSize;
54 } CONFIG_PATCH_STRUCTURE;
55
56 //
57 // @todo Define BOARD_CONFIG
58 //
59 #define BOARD_CONFIG PLATFORM_INFO
60
61 /**
62 Procedure to detect current board HW configuration.
63
64 **/
65 VOID
66 EFIAPI
67 GetBoardConfig (
68 VOID
69 );
70
71 EFI_STATUS
72 CreateBoardDefaultVariableHob (
73 IN UINT16 DefaultId,
74 IN UINT8 OsProfile
75 );
76
77 VOID
78 PatchConfigurationDataPreMem (
79 IN CONFIG_PATCH_STRUCTURE *ConfigPatchStruct,
80 IN UINTN ConfigPatchStructSize
81 );
82
83 EFI_STATUS
84 PatchConfigurationDataInit (
85 IN CONFIG_PATCH_STRUCTURE *ConfigPatchStruct,
86 IN UINTN ConfigPatchStructSize
87 );
88
89 #endif // _BOARD_CONFIG_LIB_H_
GetBoardConfig
VOID GetBoardConfig(VOID)
Procedure to detect current board HW configuration.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: BootGuardRevocationLib.h Source File

  • Library
BootGuardRevocationLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Boot Guard revocation notification.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _BOOT_GUARD_REVOCATION_LIB_H_
37 #define _BOOT_GUARD_REVOCATION_LIB_H_
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <Library/UefiRuntimeServicesTableLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/MemoryAllocationLib.h>
45 #include <Library/DebugLib.h>
46 #include <Protocol/SimpleTextIn.h>
47
48 /**
49 Provide a hook for OEM to deal with Boot Guard revocation flow.
50 **/
51 VOID
52 EFIAPI
53 BootGuardOemRevocationHook (
54 VOID
55 );
56
57 #endif
BootGuardOemRevocationHook
VOID BootGuardOemRevocationHook(VOID)
Provide a hook for OEM to deal with Boot Guard revocation flow.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Build.h Source File

  • Library
Build.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2005 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 /* #EIS_Comment_Tag_Tool *
35 ********************************************************************************
36 **
37 ** @file build.h
38 **
39 ** @brief Contains the global version strings
40 **
41 ** @author Atar Kfir
42 **
43 ********************************************************************************
44 */
45
46 /* Sentry Header
47 *******************/
48 #ifndef _BUILD_H_
49 #define _BUILD_H_
50
51 #ifdef __cplusplus
52 extern "C" {
53 #endif
54
55 /* Global Declarations
56 **************************/
57
58 /** Build Version Number. Updated by Jamin */
59 #define VER_BUILD 1009
60 /** Build Version String. Updated by Jamin */
61 #define VER_BUILD_STR "1009"
62
63 #ifdef __cplusplus
64 }
65 #endif
66
67 #define POST_PV 1 // Set this flag to zero when are at PRE-PV and 1 when we are at POST_PV
68 // This flag will take care of including or excluding WW kill-pill check
69 // and turn on the update logic to prevent downgrade from POST_PV to PRE_PV.
70 // To update the PV value in the manifest, please modify the
71 // XML path /CseConfiguration/CseRegion/ManifestFlags value (bit 0) in the
72 // FTOOL configuration file.
73
74 /*** Global Functions
75 **************************/
76
77 #endif // _BUILD_H_
78
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: CeAta.h Source File

  • IndustryStandard
CeAta.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 /*++
36
37 Module Name:
38
39 CEATA.h
40
41 Abstract:
42
43 Header file for chipset CE-AT spec.
44
45 --*/
46
47 #ifndef _CE_ATA_H
48 #define _CE_ATA_H
49
50 #pragma pack(1)
51
52
53 #define DATA_UNIT_SIZE 512
54
55
56 #define CMD60 60
57 #define CMD61 61
58
59
60 #define RW_MULTIPLE_REGISTER CMD60
61 #define RW_MULTIPLE_BLOCK CMD61
62
63
64 #define CE_ATA_SIG_CE 0xCE
65 #define CE_ATA_SIG_AA 0xAA
66
67
68 #define Reg_Features_Exp 01
69 #define Reg_SectorCount_Exp 02
70 #define Reg_LBALow_Exp 03
71 #define Reg_LBAMid_Exp 04
72 #define Reg_LBAHigh_Exp 05
73 #define Reg_Control 06
74 #define Reg_Features_Error 09
75 #define Reg_SectorCount 10
76 #define Reg_LBALow 11
77 #define Reg_LBAMid 12
78 #define Reg_LBAHigh 13
79 #define Reg_Device_Head 14
80 #define Reg_Command_Status 15
81
82 #define Reg_scrTempC 0x80
83 #define Reg_scrTempMaxP 0x84
84 #define Reg_scrTempMinP 0x88
85 #define Reg_scrStatus 0x8C
86 #define Reg_scrReallocsA 0x90
87 #define Reg_scrERetractsA 0x94
88 #define Reg_scrCapabilities 0x98
89 #define Reg_scrControl 0xC0
90
91
92
93 typedef struct {
94 UINT8 Reserved0;
95 UINT8 Features_Exp;
96 UINT8 SectorCount_Exp;
97 UINT8 LBALow_Exp;
98 UINT8 LBAMid_Exp;
99 UINT8 LBAHigh_Exp;
100 UINT8 Control;
101 UINT8 Reserved1[2];
102 UINT8 Features_Error;
103 UINT8 SectorCount;
104 UINT8 LBALow;
105 UINT8 LBAMid;
106 UINT8 LBAHigh;
107 UINT8 Device_Head;
108 UINT8 Command_Status;
109 }TASK_FILE;
110
111
112 //
113 //Reduced ATA command set
114 //
115 #define IDENTIFY_DEVICE 0xEC
116 #define READ_DMA_EXT 0x25
117 #define WRITE_DMA_EXT 0x35
118 #define STANDBY_IMMEDIATE 0xE0
119 #define FLUSH_CACHE_EXT 0xEA
120
121
122
123 typedef struct {
124 UINT16 Reserved0[10];
125 UINT16 SerialNumber[10];
126 UINT16 Reserved1[3];
127 UINT16 FirmwareRevision[4];
128 UINT16 ModelNumber[20];
129 UINT16 Reserved2[33];
130 UINT16 MajorVersion;
131 UINT16 Reserved3[19];
132 UINT16 MaximumLBA[4];
133 UINT16 Reserved4[2];
134 UINT16 Sectorsize;
135 UINT16 Reserved5;
136 UINT16 DeviceGUID[4];
137 UINT16 Reserved6[94];
138 UINT16 Features;
139 UINT16 MaxWritesPerAddress;
140 UINT16 Reserved7[47];
141 UINT16 IntegrityWord;
142 }IDENTIFY_DEVICE_DATA;
143
144
145
146
147
148 #pragma pack()
149
150 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Common.h Source File

  • Library
Common.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2007 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33 #ifndef __COMMON_H__
34 #define __COMMON_H__
35
36 #if 0
37 //#include <stdio.h>
38
39 #ifdef EFIX64
40
41
42 //#include <atk_libc.h>
43 //#include <shell.h>
44 //#include <efilib.h>
45 //#include <efiapi.h>
46 //#include <stdio.h>
47 //#include <string.h>
48 //#include <stdlib.h>
49 //#include <unistd.h>
50 #include <efi_interface.h>
51 #include <efi.h>
52 #endif
53
54 #define bool BOOLEAN
55
56 #endif
57
58 //#ifdef _DOS
59 //#include <nal.h>
60 //#include <cudl.h>
61 //#include <dos.h>
62
63 typedef unsigned char UCHAR;
64 //typedef unsigned long DWORD;
65
66 /*#else
67 #ifndef EFIX64
68 #ifndef _LINUX
69 #ifndef IFR_PROJ
70 #include <winsock2.h>
71 #endif
72 #include <windows.h>
73 #endif //_LINUX
74 #endif
75 #endif*/
76
77
78 /*#ifdef _LINUX
79 #include "linux_types.h"
80 #endif*/
81
82 extern UINT32 g_fwuError;
83
84
85 enum errorValues {
86 FWU_ERROR_SUCCESS,
87 FWU_IME_NO_DEVICE = 8193,
88 FWU_UPD_VER_MIS = 8199,
89 FWU_VER_GET_ERR = 8204,
90 FWU_CERT_ERR = 8213,
91 FWU_REBOOT_NEEDED = 8703,
92 FWU_SKU_MISMATCH,
93 FWU_VER_MISMATCH,
94 FWU_SGN_MISMATCH,
95 FWU_GENERAL,
96 FWU_UPD_PROCESS,
97 FWU_NO_MEMORY = 8710,
98 FWU_AUTH = 8712,
99 FWU_IMG_HEADER,
100 FWU_FILE_OPEN,
101 FWU_HTTP_ERROR,
102 FWU_USAGE_ERROR,
103 FWU_HOSTNAME,
104 FWU_UPDATE_TIMEOUT,
105 FWU_LOCAL_DIS,
106 FWU_SECURE_DIS,
107 FWU_IME_UN_SUP_MESS = 8722,
108 FWU_NO_UPDATE,
109 FWU_IME_NOT_READY,
110 FWU_LAST_STATUS,
111 FWU_GET_VER_ERR = 8727,
112 FWU_IME_SMALL_BUFF,
113 FWU_WSMAN_NO = 8734,
114 FWU_UNSUPPRT_OS = 8740,
115 FWU_ERROR_FW,
116 FWU_HECI,
117 FWU_UNSUPPRT_PLAT,
118 FWU_VERIFY_OEM_ID_ERR,
119 FWU_INVALID_OEM_ID = 8745,
120 FWU_INVALID_IMG_LENGTH,
121 FWU_GLBL_BUFF_UNAVAILABLE,
122 FWU_INVALID_FW_PARAMS,
123 FWU_AMT_STATUS_INTERNAL_ERROR,
124 FWU_AMT_STATUS_NOT_READY = 8750,
125 FWU_AMT_STATUS_INVALID_AMT_MODE,
126 FWU_AMT_STATUS_INVALID_MESSAGE_LENGTH,
127 FWU_SAVE_RESTORE_POINT_ERROR,
128 FWU_FILE_WRITE,
129 FWU_GET_BLIST_ERROR = 8755,
130 FWU_CHECK_VERSION_ERROR,
131 FWU_DISPLAY_FW_VERSION,
132 FWU_IMAGE_UNDER_VCN,
133 FWU_IMAGE_VER_HIST_CHK_FAIL,
134 FWU_DOWNGRADE_VETOED = 8760,
135 FWU_FW_WRITE_FILE_FAIL,
136 FWU_FW_READ_FILE_FAIL,
137 FWU_FW_DELETE_FILE_FAIL,
138 FWU_PARTITION_LAYOUT_NOT_COMP,
139 FWU_DOWNGRADE_NOT_ALLOWED_DATA_MISMATCH = 8765,
140 FWU_UPDATE_PASSWORD_NOT_MATCHED,
141 FWU_UPDATE_PASSWORD_EXCEED_MAXIMUM_RETRY,
142 FWU_UPDATE_PASSWORD_NOT_PROVIDED,
143 FWU_UPDATE_POLLING_FAILED,
144 FWU_FILE_ALREADY_EXISTS = 8770,
145 FWU_FILE_INVALID,
146 FWU_USAGE_ERROR_B,
147 FWU_AUDIT_POLICY_FAILURE,
148 FWU_ERROR_CREATING_FT,
149 FWU_SAL_NOTIFICATION_ERROR = 8775,
150 FWU_UPD_IMG_LOADING,
151 FWU_UPD_IMG_AUTHENTICATING,
152 FWU_UPD_IMG_PROCESSING,
153 FWU_UPD_CREATING_FT,
154 FWU_UPD_UPDATING_CODE,
155 FWU_UPD_UPDATING_NFT,
156 FWU_FLASH_CODE_PARTITION_INVALID,
157 FWU_FLASH_NFT_PARTITION_INVALID,
158 FWU_ILLEGAL_IMAGE_LENGTH,
159 FWU_HOST_RESET_REQUIRED,
160 FWU_INVALID_GLUT,
161 FWU_GET_PATTRIB_ERROR,
162 FWU_GET_UPD_INFO_STATUS,
163 FWU_PID_NOT_EXPECTED,
164 FWU_UPDATE_INRECOVERY_MODE_RESTRICT_UPDATE_TO_ATTEMPTED_VERSION,
165 FWU_BUFFER_COPY_FAILED,
166 FWU_GET_ME_FWU_INFO,
167 FWU_APP_REGISTER_OS_FAILURE,
168 FWU_APP_UNREGISTER_OS_FAILURE,
169 FWU_INVALID_PARTID,
170 FWU_LIVE_PING_FAILURE,
171 FWU_SERVICE_CONNECT_FAILURE,
172 FWU_SERVICE_NOT_AVAILABLE,
173 FWU_SERVICE_BUSY,
174 FWU_USER_NOT_ADMIN,
175 FWU_WMI_FAIL,
176 FWU_CHK_BIT_LOCKER_FAIL,
177 FWU_REG_CMD_FAIL,
178 FWU_UPDATE_IMAGE_BLACKLISTED,
179 FWU_DOWNGRADE_NOT_ALLOWED_SVN_RESTRICTION,
180 FWU_INVALID_POINTER,
181 FWU_UPV_VERSION_MISMATCHED,
182 FWU_INSTID_IS_NOT_EXPECTED_ID,
183 FWU_INFO_NOT_AVAILABLE,
184 FWU_REJ_IPU_FULL_UPDATE_NEEDED,
185 FWU_IPU_NAMEID_NOT_FOUND,
186 FWU_RESTORE_POINT_INVALID,
187 FWU_RESTORE_POINT_VALID_BUT_NOT_LATEST,
188 FWU_RESTORE_POINT_OPERATION_NOT_ALLOWED,
189 FWU_DOWNGRADE_NOT_ALLOWED_VCN_RESTRICTION,
190 FWU_INVALID_SVN,
191 FWU_OUT_OF_SVN_RESOURCES,
192 FWU_REJECT_RESTORE_POINT_REQUEST_FLASH_IN_RECOVERY,
193 FWU_REJECTED_BY_UPDATE_POLICY,
194 FWU_REJECTED_INCOMPATIBLE_TOOL_USAGE,
195 FWU_REJECTED_CROSSPOINT_UPDATE_NOT_ALLOWED,
196 FWU_REJECTED_CROSSHOTFIX_UPDATE_NOT_ALLOWED,
197 FWU_REJECTED_CURRENT_FW_NOT_ELIGIBLE_FOR_UPDATE,
198 FWU_REJECTED_WRONG_UPDATE_OPERATION,
199 FWU_REJECTED_WRONG_UPDATE_IMAGE_FOUND,
200 FWU_REJECTED_IFR_UPDATE_NOT_ALLOWED,
201 FWU_FAILURE_OCCURRED_DURING_ROLLBACK,
202 FWU_RESTORE_POINT_OPERATION_FAILED,
203 FWU_ERROR_DETECT_POWER_SOURCE,
204 FWU_LAST_STATUS_CODE
205 };
206
207 typedef struct {
208 unsigned int Cse_error_code;
209 unsigned int Fwu_error_code;
210 } FwuCseErrorMap;
211
212 typedef struct {
213 unsigned int Fwu_error_code;
214 const char * Fwu_error_message;
215 } FwuCseErrorMsgMap;
216
217 typedef struct {
218 UINT32 PchVer;
219 } HW_SKU;
220
221 #define HW_SKU_DEVICE_ID_MASK 0xFFFF0000
222 #define HW_SKU_REVISION_MASK 0x000000FF
223
224 typedef struct {
225 UINT16 Major;
226 UINT16 Minor;
227 UINT16 Hotfix;
228 UINT16 Build;
229 } FWVersion;
230
231 typedef struct {
232 FWVersion code;
233 FWVersion rcvy;
234 } FlashVersion;
235
236 #ifdef __cplusplus
237 extern "C" {
238 #endif
239
240 unsigned int FromCseToFwuErrorCode(unsigned int cseer);
241 const char * FromFwuErrorCodeToErrorMsg(unsigned int fwuer);
242
243 // return < 0 if a < b
244 // 0 if a = b
245 // > 0 if a > b
246 int VersionCompare(FWVersion *a, FWVersion *b);
247
248 #ifdef __cplusplus
249 }
250 #endif
251
252
253 #ifndef EFIX64
254 #ifndef _LINUX
255 #ifndef _DOS
256 //BOOL WindowsReset( LPTSTR message );
257 #endif
258 #endif
259 #endif
260 #ifdef __cplusplus
261 }
262 #endif
263
264 #ifdef _WIN
265
266 #ifndef _LINUX
267
268 static const unsigned short DEFAULT_AMT_TCP_PORT = 16992;
269 static const unsigned short DEFAULT_AMT_TLS_PORT = 16993;
270
271 static const int MAX_LINE_LEN = 1024;
272 static const int TIMEOUT = 80;
273 static const char *DEFAULT_USERNAME = "admin";
274 static const char *DEFAULT_PASSWORD = "admin";
275
276 #endif //_LINUX
277 #endif // _WIN
278 #endif
Efi.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: CommonDefinitions.h Source File

CommonDefinitions.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _COMMON_DEFINITIONS_H_
34 #define _COMMON_DEFINITIONS_H_
35
36 //
37 // PCI CONFIGURATION MAP REGISTER OFFSETS
38 //
39 #define PCI_VID 0x0000 // Vendor ID Register
40 #define PCI_DID 0x0002 // Device ID Register
41 #define PCI_CMD 0x0004 // PCI Command Register
42 #define PCI_STS 0x0006 // PCI Status Register
43 #define PCI_RID 0x0008 // Revision ID Register
44 #define PCI_IFT 0x0009 // Interface Type
45 #define PCI_SCC 0x000A // Sub Class Code Register
46 #define PCI_BCC 0x000B // Base Class Code Register
47 #define PCI_CLS 0x000C // Cache Line Size
48 #define PCI_PMLT 0x000D // Primary Master Latency Timer
49 #define PCI_HDR 0x000E // Header Type Register
50 #define PCI_BIST 0x000F // Built in Self Test Register
51 #define PCI_BAR0 0x0010 // Base Address Register 0
52 #define PCI_BAR1 0x0014 // Base Address Register 1
53 #define PCI_BAR2 0x0018 // Base Address Register 2
54 #define PCI_PBUS 0x0018 // Primary Bus Number Register
55 #define PCI_SBUS 0x0019 // Secondary Bus Number Register
56 #define PCI_SUBUS 0x001A // Subordinate Bus Number Register
57 #define PCI_SMLT 0x001B // Secondary Master Latency Timer
58 #define PCI_BAR3 0x001C // Base Address Register 3
59 #define PCI_IOBASE 0x001C // I/O base Register
60 #define PCI_IOLIMIT 0x001D // I/O Limit Register
61 #define PCI_SECSTATUS 0x001E // Secondary Status Register
62 #define PCI_BAR4 0x0020 // Base Address Register 4
63 #define PCI_MEMBASE 0x0020 // Memory Base Register
64 #define PCI_MEMLIMIT 0x0022 // Memory Limit Register
65 #define PCI_BAR5 0x0024 // Base Address Register 5
66 #define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register
67 #define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register
68 #define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits
69 #define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits
70 #define PCI_SVID 0x002C // Subsystem Vendor ID
71 #define PCI_SID 0x002E // Subsystem ID
72 #define PCI_IOBASE_U 0x0030 // I/O base Upper Register
73 #define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register
74 #define PCI_CAPP 0x0034 // Capabilities Pointer
75 #define PCI_EROM 0x0038 // Expansion ROM Base Address
76 #define PCI_INTLINE 0x003C // Interrupt Line Register
77 #define PCI_INTPIN 0x003D // Interrupt Pin Register
78 #define PCI_MAXGNT 0x003E // Max Grant Register
79 #define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register
80 #define PCI_MAXLAT 0x003F // Max Latency Register
81
82 //
83 // Bit Difinitions
84 //
85 #ifndef BIT0
86 #define BIT0 0x0001
87 #define BIT1 0x0002
88 #define BIT2 0x0004
89 #define BIT3 0x0008
90 #define BIT4 0x0010
91 #define BIT5 0x0020
92 #define BIT6 0x0040
93 #define BIT7 0x0080
94 #define BIT8 0x0100
95 #define BIT9 0x0200
96 #ifndef BIT10
97 #define BIT10 0x0400
98 #define BIT11 0x0800
99 #define BIT12 0x1000
100 #define BIT13 0x2000
101 #define BIT14 0x4000
102 #define BIT15 0x8000
103 #define BIT16 0x00010000
104 #define BIT17 0x00020000
105 #define BIT18 0x00040000
106 #define BIT19 0x00080000
107 #define BIT20 0x00100000
108 #define BIT21 0x00200000
109 #define BIT22 0x00400000
110 #define BIT23 0x00800000
111 #define BIT24 0x01000000
112 #define BIT25 0x02000000
113 #define BIT26 0x04000000
114 #define BIT27 0x08000000
115 #define BIT28 0x10000000
116 #define BIT29 0x20000000
117 #define BIT30 0x40000000
118 #define BIT31 0x80000000
119 #ifndef BIT32
120 #define BIT32 0x100000000
121 #define BIT33 0x200000000
122 #define BIT34 0x400000000
123 #define BIT35 0x800000000
124 #define BIT36 0x1000000000
125 #define BIT37 0x2000000000
126 #define BIT38 0x4000000000
127 #define BIT39 0x8000000000
128 #define BIT40 0x10000000000
129 #define BIT41 0x20000000000
130 #define BIT42 0x40000000000
131 #define BIT43 0x80000000000
132 #define BIT44 0x100000000000
133 #define BIT45 0x200000000000
134 #define BIT46 0x400000000000
135 #define BIT47 0x800000000000
136 #define BIT48 0x1000000000000
137 #define BIT49 0x2000000000000
138 #define BIT50 0x4000000000000
139 #define BIT51 0x8000000000000
140 #define BIT52 0x10000000000000
141 #define BIT53 0x20000000000000
142 #define BIT54 0x40000000000000
143 #define BIT55 0x80000000000000
144 #define BIT56 0x100000000000000
145 #define BIT57 0x200000000000000
146 #define BIT58 0x400000000000000
147 #define BIT59 0x800000000000000
148 #define BIT60 0x1000000000000000
149 #define BIT61 0x2000000000000000
150 #define BIT62 0x4000000000000000
151 #define BIT63 0x8000000000000000
152 #endif
153 #endif
154 #endif
155
156 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: CpuPolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
CpuPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #include <CpuPolicyInitDxe.h>
35
36 DXE_CPU_POLICY_PROTOCOL mCpuPolicyData;
37
38 /**
39 Initilize Intel CPU DXE Platform Policy
40
41 @param[in] ImageHandle Image handle of this driver.
42
43 @retval EFI_SUCCESS Initialization complete.
44 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
45 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
46 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
47 **/
48 EFI_STATUS
49 EFIAPI
50 CpuPolicyInitDxe (
51 IN EFI_HANDLE ImageHandle
52 )
53 {
54 EFI_STATUS Status;
55
56 ZeroMem(&mCpuPolicyData, sizeof (DXE_CPU_POLICY_PROTOCOL));
57 mCpuPolicyData.Revision = DXE_CPU_POLICY_PROTOCOL_REVISION;
58
59 UpdateDxeSiCpuPolicy(&mCpuPolicyData);
60
61 //
62 // Install CpuInstallPolicyProtocol.
63 // While installed, RC assumes the Policy is ready and finalized. So please
64 // update and override any setting before calling this function.
65 //
66 Status = CpuInstallPolicyProtocol(ImageHandle, &mCpuPolicyData);
67 ASSERT_EFI_ERROR (Status);
68
69 return Status;
70 }
UpdateDxeSiCpuPolicy
EFI_STATUS UpdateDxeSiCpuPolicy(IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
Routine Description:
CpuInstallPolicyProtocol
EFI_STATUS CpuInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
CpuInstallPolicyProtocol installs CPU Policy.
CpuPolicyInitDxe
EFI_STATUS CpuPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Platform Policy.
Definition: CpuPolicyInitDxe.c:50
CpuPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: CpuPolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
CpuPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the SiliconPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef _CPU_POLICY_INIT_DXE_H_
36 #define _CPU_POLICY_INIT_DXE_H_
37
38 #include <Library/BaseMemoryLib.h>
39 #include <Library/MemoryAllocationLib.h>
40 #include <Library/DebugLib.h>
41 #include <Library/BaseLib.h>
42
43 #include <Protocol/CpuPolicyProtocol.h>
44 #include <Library/DxeCpuPolicyUpdateLib.h>
45
46
47 /**
48 Initilize Intel CPU DXE Policy
49
50 @param[in] ImageHandle Image handle of this driver.
51
52 @retval EFI_SUCCESS Initialization complete.
53 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
54 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
55 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
56 **/
57 EFI_STATUS
58 EFIAPI
59 CpuPolicyInitDxe (
60 IN EFI_HANDLE ImageHandle
61 );
62
63 #endif
DxeCpuPolicyUpdateLib.h
CpuPolicyInitDxe
EFI_STATUS CpuPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy.
Definition: CpuPolicyInitDxe.c:50
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: CpuSmm.h Source File

CpuSmm.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2012 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _CPUSMM_H_
34 #define _CPUSMM_H_
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 #define CPUSMM_GUID { 0x90d93e09, 0x4e91, 0x4b3d, 0x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe, 0x3c, 0x81 }
40 #define CPUSMM_SETUP_NAME L"CpuSmm"
41
42 #pragma pack(1)
43 typedef struct {
44 UINT8 CpuSmmMsrSaveStateEnable;
45 UINT8 CpuSmmCodeAccessCheckEnable;
46 UINT8 CpuSmmUseDelayIndication;
47 UINT8 CpuSmmUseBlockIndication;
48 UINT8 CpuSmmUseSmmEnableIndication;
49 UINT8 CpuSmmProcTraceEnable;
50 } CPU_SMM;
51 #pragma pack()
52
53 #define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
54 #define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8 _VerifyOffset##TYPE##Field[(OFFSET_OF(TYPE, Field) == Offset) / (OFFSET_OF(TYPE, Field) == Offset)]
55
56 //
57 // If TpmSupport/MorStae isn't in this offset, build failure (0 size array or divided by 0) will be generated.
58 // Platform DSC file maps the two field to HII PCD so the offset value is critical.
59 //
60 VERIFY_OFFSET (CPU_SMM, CpuSmmMsrSaveStateEnable, 0x0);
61 VERIFY_OFFSET (CPU_SMM, CpuSmmCodeAccessCheckEnable, 0x1);
62 VERIFY_OFFSET (CPU_SMM, CpuSmmUseDelayIndication, 0x2);
63 VERIFY_OFFSET (CPU_SMM, CpuSmmUseBlockIndication, 0x3);
64 VERIFY_OFFSET (CPU_SMM, CpuSmmUseSmmEnableIndication, 0x4);
65 VERIFY_OFFSET (CPU_SMM, CpuSmmProcTraceEnable, 0x5);
66
67 /****** DO NOT WRITE BELOW THIS LINE *******/
68 #ifdef __cplusplus
69 }
70 #endif
71 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: CustomOptionControl.h Source File

CustomOptionControl.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _CUSTOM_OPTION_CONTROL_H_
35 #define _CUSTOM_OPTION_CONTROL_H
36
37 #include <SetupVariable.h>
38 #include <Ppi/ReadOnlyVariable2.h>
39 #include <Library/DebugLib.h>
40 //#include <PchPolicyCommon.h>
41
42 extern EFI_GUID gMsftGlobalVariableGuid;
43
44
45 #pragma pack(1)
46 typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO {
47 UINT8 RevisonId; // Structure Revision ID
48 UINT8 HotkeyTriggered; // Hot key status
49 } ATTEMPT_USB_FIRST_HOTKEY_INFO;
50 #pragma pack()
51
52 #pragma pack(1)
53 typedef struct _ATTEMPT_USB_FIRST_VARIABLE {
54 UINT8 UsbBootPrior;
55 } ATTEMPT_USB_FIRST_VARIABLE;
56 #pragma pack()
57
58 //
59 // Volatile variable definition for Attempt USB first features
60 //
61 #pragma pack(1)
62 typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE {
63 UINT8 RevisonId; // Structure Revision ID
64 UINT8 UsbFirstEnable; // Attempt USB First is enabled or not
65 } ATTEMPT_USB_FIRST_RUNTIME_VARIABLE;
66 #pragma pack()
67
68 //
69 // Volatile variable definition for Enabling Flash Tools via UEFI Variable
70 //
71 #pragma pack(1)
72 typedef struct _ENABLE_FLASH_TOOLS{
73 UINT32 EnableFlashTools;
74 } ENABLE_FLASH_TOOLS;
75 #pragma pack()
76
77 //
78 // Volatile variable definition for third party Default Enabling via UEFI Variable.
79 //
80 #pragma pack(1)
81 typedef struct _ENABLE_CUSTOM_DEFAULTS{
82 UINT32 EnableCustomDefaults;
83 } ENABLE_CUSTOM_DEFAULTS;
84 #pragma pack()
85
86 #pragma pack(1)
87 typedef struct _ENABLE_CUSTOM_DEFAULTS_STATE{
88 UINT8 CurrentState;
89 } ENABLE_CUSTOM_DEFAULTS_STATE;
90 #pragma pack()
91
92 extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid;
93 extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid;
94
95 #endif // _CUSTOM_OPTION_CONTROL_H_
96
SetupVariable.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DimmInfo.h Source File

DimmInfo.h
Go to the documentation of this file.
1 /** @file
2 This header file provides Dimm info definitions used by other
3 modules for dimm info presentation.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2015 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef __DIMM_INFO_H__
37 #define __DIMM_INFO_H__
38
39 #include <Protocol/MemInfo.h>
40
41 typedef struct {
42 UINT16 MfgId;
43 CHAR8 String[16];
44 } MEMORY_MODULE_MANUFACTURER_LIST;
45
46 typedef enum {
47 DDR4,
48 DDR3,
49 LPDDR3,
50 LPDDR4,
51 NUM_DDR_TYPES
52 } DDR_TYPE;
53
54 extern CHAR8 *MemoryTypeStr[];
55 extern MEMORY_MODULE_MANUFACTURER_LIST MemoryModuleManufacturerList[];
56 extern UINT8 MemoryModuleManufacturerListSize;
57
58 #endif // __DIMM_INFO_H__
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DoxygenAcpi.h Source File

DoxygenAcpi.h
Go to the documentation of this file.
1 /** @file
2 This file contains doxygen commands definitions for creating quality platform documentation.
3
4 Copyright (c) 2013 - 2016 Intel Corporation. All rights reserved
5 This software and associated documentation (if any) is furnished
6 under a license and may only be used or copied in accordance
7 with the terms of the license. Except as permitted by the
8 license, no part of this software or documentation may be
9 reproduced, stored in a retrieval system, or transmitted in any
10 form or by any means without the express written consent of
11 Intel Corporation.
12 This file contains a 'Sample Driver' and is licensed as such
13 under the terms of your license agreement with Intel or your
14 vendor. This file may be modified by the user, subject to
15 the additional terms of the license agreement.
16 **/
17
18 /** @page PlatAcpi 2.1 - ACPI
19 @details
20 This document describes the ACPI design for platform sample code and provides detailed descriptions for all the ASL code in the package. It is a useful reference for the implementation of ACPI support for Kabylake based platforms.
21 - @subpage archoverviewacpi
22 - @subpage rationaleacpi
23 - @subpage requirementsacpi
24 - @subpage apiacpi
25 - @subpage buildflagsacpi
26 - @subpage miscacpi
27
28 **/
29
30 /** @page archoverviewacpi 2.1.1 - Architectural Overview
31 @details
32 ACPI ASL code is generally categorized into one of the modules listed below:
33 - <b>System Agent ASL Code</b>
34 This module contains the ASL files for the System Agent Host Bridge and the bridges/devices inside it. All ASL files for System Agent are included in the System Agent Reference Code package.
35 HOST_BUS.ASL: Defines various Kabylake System Agent PCI Configuration Space registers which will be used to dynamically produce all resources in the Host Bus.
36 SA.ASL: Currently defines the device objects for the PCI Express* Graphics bridge and port, and IGD.
37 INTELGFX.ASL: Defines the methods to enable/disable output switching, store display switching and LCD brightness BIOS control and return valid addresses for all display device encoders present in the system, etc.
38 IgdOpRn.ASL: Defines OperationRegions to cover the IGD PCI configuration space as described in the IGD OpRegion specification.
39 IgdOGBDA.ASL: This file contains Get BIOS Data Area function support for the IGD OpRegion/Software SCI mechanism.
40 IgdOMOBF.ASL: This file contains ASL code for handling the events, i.e. hotkeys and other system interrupts.
41 IgdOSBCB.ASL: This file contains the system BIOS call back functionality for the OpRegion/Software SCI mechanism
42
43 - <b>PCH ASL Code</b>
44 This module contains the definitions for the OperationRegions for accesses to the PCH and the methods to use it. All ASL files for the PCH are included in the PCH Reference Code package.
45 PCH.ASL: Defines the OperationRegions for the accesses to the registers inside PCH, and PCH!|s internal devices.
46 PchAudio.ASL: Defines the OperationRegion for the accesses to HDA controller.
47 PchPcie.ASL: Defines the OperationRegion for the accesses to PCI Express Root Bridge registers.
48 PchSmb.ASL: Defines the OperationRegion for the accesses to SMBus PCI Configuration Space and I/O mapped registers, and the methods to execute various SMBus transactions.
49
50 - <b>CPU ASL Code</b>
51 This module contains the tables, methods, P-state, C-state and T-state support. These will be dynamically loaded according to OS CPU driver capabilities. All CPU ASL files are included in the CPU Reference Code package.
52 Cpu0Cst.ASL/ApCst.ASL: Defines _CST method for all processors to publish C-State capability.
53 Cpu0Ist.ASL/ApIst.ASL: Defines _PPC, _PCT, _PSS method for all processors to publish P-State capabilities.
54 Cpu0Tst.ASL/ApTst.ASL: Defines _TPC, _PTC, _TSS, _TSD method for all processors to publish T-State capabilities.
55 CpuPm.ASL: Defines the methods to get the information for properly initializing tables and dynamically loading them.
56
57 - <b>Platform ASL Code</b>
58 This module contains all platform-related ACPI name spaces and methods. All Platform ASL files are in this Platform Sample package, of which most of the Differentiated System Description Table (DSDT) consists. The following sections will introduce all of ASL files in this package top-to-down in hierarchy.
59 !V DSDT.ASL:This file makes up all components into most of the DSDT, which contains information and descriptions for various system features. Additionally, this file also contains power management packages that defines system \_S0, \_S1, \_S3, \_S4 and \_S5 state mode. The ASL files listed below are included into this file to compose the whole DSDT.
60 - Amlupd.asl
61 - PlatformNvs.asl
62 - PCItree.asl
63 - Platform.asl
64 - CPU.asl
65 - Thermal.asl
66 - PCI_DRC.asl
67 - Video.asl
68 - Gpe.asl
69 - PCIEDOCK.asl
70 - Pch.asl: Not in this package. Refer to the PCH Reference Code
71 - Sa.asl: Not in this package. Refer to the SA Reference Code
72 - Note: \_S0 and \_S5 are mandatory system states.
73
74 - Globally-Used Data
75 - AmlUpd.ASL: Defines the namespaces for the support of system states.
76 - PlatformNvs.ASL: Define a Global region of ACPI NVS Region that may be used for any type of implementation. The starting offset and size will be fixed up by the System BIOS during POST.
77
78 - PciTree.ASL: This conducts the whole system bus (\_SB), starting with PCI Host Bridge Bus hierarchy (\_PCI0), incorporating all devices resident in bus 0. This may make references to others ASL files located over other reference code packages, e.g. HOST_BUS.ASL in System Agent Reference Code package. Additionally, this also defines the namespaces for the possible resources (_PRS) for LINKA/B/C/D/E/F/G/H and for routing information (_PRT)
79
80 - Cpu.ASL: The definitions of processor methods for all logical processors under \_PR
81
82 - Gpe.ASL: This ASL file contains most of General-Purpose Events methods (_Lxx).
83
84 - LpcB.asl: Defines the OperationRegions for PIRQx Routing Control Registers, I/O Decode Ranges Register, RCBA and Keyboard Controller I/O ports; declares PS/2 keyboard and mouse device. In addition, this drags in the ASL files of the devices resident in LPC bus.
85
86 - EC.ASL: Defines an EC device containing an EC Space and Query Event methods (_Qxx) for handling battery, thermal, docking system, LID, ALS and specific hotkeys; also defines an AC device, a lid switch and power button.
87
88 - Thermal.ASL: Defines two thermal zones: TZ00 and TZ01. The former is for active cooling and the later is for passive cooling. It also defines twoPowerResources: FN00 and FN01, for fan control in active cooling.
89
90 - Super I/O Controllers
91 - NAT_COM.ASL/NAT_FDC.ASL/NAT_LPT.ASL/NAT_SIO.ASL: Defines the devices and methods for the National Super I/O controller support.
92 - SMSC1000_COM.ASL/SMSC1000_LPT.ASL/SMSC1000_SIO.ASL: Defines the devices and methods for the SMSC1000 Super I/O controller support.
93 - SMSC1007_COM.ASL/SMSC1007_SIO.ASL: Defines the devices and methods for the SMSC1007 Super I/O controller support.
94 - WPCN381U_COM.asl/WPCN381U_LPT.ASL/WPCN381U_FDC.asl /WPCN381U_SIO.asl: Defines the devices and methods for the Winbond* WPCN381 SuperIO support.
95
96 - PCIEDOCK.ASL: Defines a docking station device with the related control methods, e.g. _EJ0 (a control method that ejects a device; _EJ0 means hot-ejection), _DCK (indicates that this device is a docking station and also controls the isolation logic on the docking connector for docking or undocking), _EDL (returns a packaged list of devices that are dependent on a device.
97 - Platform.ASL: Defines some standard methods, e.g. _PIC (for OS to inform the ASL code which interrupt controller is being used, 8259 or APIC), _PTS (Prepare to Sleep, is called when the OS is about to enter a sleep state.), _WAK (is called when the OS is about to wake from sleep state), _INI (is used to determine the OS) and some useful methods for other ASL code!|s use, e.g. P8XH (for port-80 display), GETB (creates then returns a smaller buffer), PNOT (performs all OS-needed notifications during a Power Switch.), TRAP (generates a Mutex protected SMI I/O Trap), NHPG (clears the PCI Express hot-plug SCI enable bits), NPME (clear PCI Express PME SCI enable bits), etc.
98 - PCI_DRC.ASL: Defines memory regions for RCRB, MCH BAR, DMI BAR, EP BAR, PCIE BAR Thermal BAR, TTT base address (for TxT), VTD Engine Memory Range, Flash Range, Local APIC Range as Motherboard Resources (PNP0C02). The _BAS, _LEN will be dynamically updated (in _CRS method) to match the real configurations.
99
100 - <b>ACPI FVI Support</b>
101 - This module creates the version information of the ACPI Reference Code, referring to the SMBIOS type 0xDD described in Firmware Version Information (FVI) Interface Specification v0.8
102 - <b>SSDT PTID ASL Code</b>
103 - PTID (Power and Temperature Instrumentation) is in an SSDT by design, which is able to dynamically loaded by <b>EFI ACPI Table Protocol</b>.
104 - Ptid.ASL: This file contains the code for Thermal Monitoring support for the PTIMon (Power and Temperature Instrumentation Monitor Utility) application to report temperature, power and Fan speed.
105 - <b>Dynamic Platform & Thermal Framework (DPTF)</b>
106 - The DPTF reference code is a Framework compliant DXE driver that consists of two main components:
107 1.DPTF device initialization
108 2.ACPI SSDT tables
109 It does all the DPTF specific initializations and loads the ACPI tables which provide the AML code to control the various thermal components.
110 DPTF is Intel!|s implementation of the ACPI 5.0 Thermal model. Following are the main features supported by the SSDT tables:
111 - Support multiple thermal device components within a single Thermal Zone
112 - Device components contain embedded temperature sensors and cooling controls (passive and/or active)
113 - Device components expose thermal trip points
114 - Device thermal interfaces exposed via device!|s driver
115 The Intel DPTF Thermal Zone has various ACPI objects:
116 - Participant device objects like CPU, Memory, Fan and on board sensors (called Generic participant devices)
117 - Thermal Objects like PATC, PATx, GTSH, _SCP
118 All these objects are described in detail in the IntelU+00AE Dynamic Platform & Thermal Framework 7.0 BIOS Writer!|s Guide Version.
119 - DPTF SSDT
120 The DPTF reference code for Kabylake is loaded in one SSDT by the DXE driver in Dptf.c.
121 All ASL files will be included in Dptf.asl, which is the SSDT file.
122
123 Participants (devices) can be exposed or hidden via the ACPI status method (_STA). Each participant is contained in its own ASL file.
124 The file name format is DeviceParticipant.asl.
125
126 Policies (methods and data structures) can be exposed or hidden by conditionally returning the GUID!|s in the IDSP method.
127 Each policy is contained in its own ASL file.
128 The file name format is DeviceNamePolicy.asl
129
130 Additionally, platforms can be customized by simply removing the unwanted include files from Dptf.asl.
131
132 - Dptf.ASL: The main ASL file with IDSP, _OSC and utility methods. All other files are included here. Customer can remove features here.
133 - Art.ASL: Active cooling table for customer modification.
134 - Ertm.ASL: Participant list for customer modification.
135 - Trt.ASL: Thermal relationship table for customer modification.
136 - Dppm.ASL: Guids for Active, Passive, Critical and Cooling mode policies.
137 - B0D4Participant.ASL: System agent device.
138 - B0D4CtdpPolicy.ASL: CTDP policy.
139 - B0D4LpmPolicy.ASL: LPM policy.
140 - B0D4DppmPolicy.ASL: DPPM policy.
141 - TcpuParticipant.ASL: CPU device for ATOM. This will not be used if B0D4 device is used.
142 - TcpuDppmPolicy.ASL: DPPM policy.
143 - TpchParticipant.ASL: PCH device.
144 - TpchDppmPolicy.ASL: DPPM policy.
145 - TAmbParticipant.ASL: Ambient sensor device.
146 - TAmbDppmPolicy.ASL: DPPM policy.
147 - TEfnParticipant.ASL: Exhaust fan device.
148 - TEfnDppmPolicy.ASL: DPPM policy.
149 - TFN1Participant.ASL: Fan 1 device.
150 - TFN2Participant.ASL: Fan 2 device.
151 - TMemParticipant.ASL: Memory device.
152 - TMemDppmPolicy.ASL: DPPM policy.
153 - TSknParticipant.ASL: Skin temperature sensor.
154 - TSknDppmPolicy.ASL: DPPM policy.
155 - T_VRParticipant.ASL: Voltage regulator temperature sensor.
156 - T_VRDppmPolicy.ASL: DPPM policy.
157
158 - <b>Miscellaneous ASL Code</b>
159
160 **/
161
162 /** @page rationaleacpi 2.1.2 - Rationale
163 @details
164 The Platform Sample code was designed with the ease of customization and integration as a primary goal. Organizing code in individual functional directories and consolidating all the chipset code in a chipset module were the approaches adopted to achieve this.
165 **/
166
167 /** @page requirementsacpi 2.1.3 - Requirements
168 @details
169 - Framework compliant
170 - ASL code build with iASL.exe vesion 20130927
171 - Build with EDKII code base with specific module revision
172 - Compliant to the UEFI 2.1 specification (where appropriate)
173 - Compliant to the Framework 0.9x specifications
174 - Compliant to VS2012 compiler
175 - Easily portable to different Framework-compliant code bases utilizing the EDK
176 - Easily portable to different platforms
177 - Able to support Client platforms (Mobile and Desktop) with the same code
178 **/
179
180 /** @page apiacpi 2.1.4 - API
181 - <b>3.1 ACPI Platform Policy Protocol</b>\n
182 _ACPI_PLATFORM_POLICY_PROTOCOL
183 @copybrief _ACPI_PLATFORM_POLICY_PROTOCOL\n\n
184 - <b>3.2 ACPI Info Protocol</b>\n
185 _ACPI_INFO_PROTOCOL
186 @copybrief _ACPI_INFO_PROTOCOL\n
187 @note This is an Output from reference Code
188 **/
189
190 /** @page buildflagsacpi 2.1.5 - Build Flags
191 @par The following build flags are used for enabling or disabling features/Configurations.
192 - MDEPKG_NDEBUG <b>TRUE</b>
193 - EFI_S3_RESUME <b>TRUE</b>
194 **/
195
196 /** @page miscacpi 2.1.6 - MiscInfo
197 **/
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DoxygenPlat.h Source File

DoxygenPlat.h
Go to the documentation of this file.
1 /** @file
2 This file contains doxygen commands definitions for creating platform sample documentation
3
4 @copyright
5 Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved
6 This software and associated documentation (if any) is furnished
7 under a license and may only be used or copied in accordance
8 with the terms of the license. Except as permitted by the
9 license, no part of this software or documentation may be
10 reproduced, stored in a retrieval system, or transmitted in any
11 form or by any means without the express written consent of
12 Intel Corporation.
13 This file contains a 'Sample Driver' and is licensed as such
14 under the terms of your license agreement with Intel or your
15 vendor. This file may be modified by the user, subject to
16 the additional terms of the license agreement.
17 **/
18
19 /** @mainpage 1 - Introduction
20 @note Platform Sample Code specifications are auto generated via doxygen
21
22 **/
23
24 /** @page Modules 2 - Platform Sample Module
25 @subpage PlatAcpi \n
26
27 **/
28
29 /** @page royalparkplatformoverride 3 - Royal Park Platform Override (RPPO)
30
31 **/
32
33 /** @page Rpintguide 4 - RoyalPark & PlatSamplePkg build Integration Guide
34 When building SiPkg/SiBinPkg with RoyalPark and PlatSamplePkg please follow below steps:\n
35 1. Restrieve RoyalPark, KabylakePlatSamplePkg and all required binary/tool files (LINK16.EXE, BpmGen, FitGem, VBIOS, Microcode and GOP...). Or you may exclude those binary files in FDF file if not required\n
36 <b>Summary of build switches in PlatformPkgConfig.dsc for optional feature/process and Binary files including/excluding as below:</b>\n
37 \#\n
38 \# PCDs consumed by DSC and FDF for optional feature\n
39 \#\n
40 <table border="1" style="width:1200px">
41 <tr>
42 <th>PCDs consumed by DSC and FDF for Optional Feature (with default setting)</th>
43 <th>DESCRIPTION</th>
44 </tr>
45 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUnitoolEnable|TRUE</td><td>Execute or not for KabylakePlatSamplePkg\\Tools\\UniTool\\UniTool.bat</td></tr>
46 <tr> <td>gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE</td><td>Enable or not for ACPI feature</td></tr>
47 <tr> <td>gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE</td><td>Enable or not for S3 feature</td></tr>
48 <tr> <td>gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE</td><td>Enable or not for SMBIOS support</td></tr>
49 <tr> <td>gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE</td><td>Enable or not for SATA ATA feature</td></tr>
50 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdGopConfigBin|TRUE</td><td>Include or exclude GopCofigBin which is for external code base to boot IGFX on RVP/CRB platforms only</td></tr>
51 </table>
52
53 \#\n
54 \# PCDs consumed by DSC or FDF for bin files. \n
55 \#\n
56 <table border="1" style="width:1200px">
57 <tr>
58 <th>PCDs consumed by DSC or FDF for BIN files (with default setting)</th>
59 <th>DESCRIPTION</th>
60 </tr>
61 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable|TRUE</td><td>\#pubkeyhash.bin</td></tr>
62 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdStartupAcmBinEnable|TRUE</td><td>\#StartupAcm.bin</td></tr>
63 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdBiosAcmBinEnable|TRUE</td><td>\#BiosAc.bin</td></tr>
64 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdBiosAcProdBinEnable|TRUE</td><td>\#BiosAcProd.bin</td></tr>
65 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdReservedFitBinEnable|TRUE</td><td>\#ReservedFIT.bin</td></tr>
66 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdCsmLegacy16BinEnable|TRUE</td><td>\#AmiLegacy16.bin</td></tr>
67 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdSredirBinEnable|TRUE</td><td>\#Sredir.bin</td></tr>
68 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdRsteOromBinEnable|TRUE</td><td>\#RsteRaidOrom.bin</td></tr>
69 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdRaidOromBinEnable|TRUE</td><td>\#RaidOrom.bin</td></tr>
70 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdAhciOromBinEnable|TRUE</td><td>\#AHCIOR.BIN</td></tr>
71 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdPxeUndiOromBinEnable|TRUE</td><td>\#PxeUndiRom.BIN</td></tr>
72 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUi13BinEnable|TRUE</td><td>\#UI13.bin</td></tr>
73 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdLegacyVideoRomBinEnable|TRUE</td><td>\#LegacyVideoRom.bin</td></tr>
74 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdStmBinEnable|TRUE</td><td>\#Stm.bin</td></tr>
75 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdVbtBinEnable|TRUE</td><td>\#Vbt.bin</td></tr>
76 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdPsmihandlerBinEnable|TRUE</td><td>\#PsmiHandler.bin</td></tr>
77 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdMeBinEnable|TRUE</td><td>\#Me.bin</td></tr>
78 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdFcntrlBinEnable|TRUE</td><td>\#Fcntrl.bin</td></tr>
79 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdEcBinEnable|TRUE</td><td>\#ksc.bin</td></tr>
80 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdEcBgUpBinEnable|TRUE</td><td>\#KscBGUP.bin</td></tr>
81 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdBgupCapsuleBinEnable|TRUE</td><td>\#BGUP_$(TARGET)_CAPSULE.bin</td></tr>
82 </table>
83 \n
84 \#\n
85 \# PCDs consumed by DSC or FDF for efi files.\n
86 \#\n
87 <table border="1" style="width:1200px">
88 <tr>
89 <th>PCDs consumed by DSC or FDF for EFI files (with default setting)</th>
90 <th>DESCRIPTION</th>
91 </tr>
92 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdSectionextractiondxeEfiEnable|TRUE</td><td>\#SectionExtractionDxe.efi</td></tr>
93 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdFwvoldxeEfiEnable|TRUE</td><td>\#FwVolDxe.efi</td></tr>
94 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdFaulttolerantwritedxeEfiEnable|TRUE</td><td>\#FaultTolerantWriteDxe.efi</td></tr>
95 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUpdateDriverDxeEfiEnable|TRUE</td><td>\#UpdateDriverDxe.efi</td></tr>
96 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdIccOverClockingBinEnable|TRUE</td><td>\#IccOverClocking.efi</td></tr>
97 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUhcdBinEnable|TRUE</td><td>\#Uhcd.efi</td></tr>
98 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUsbRtBinEnable|TRUE</td><td>\#UsbRt.efi</td></tr>
99 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUsbInt13BinEnable|TRUE</td><td>\#UsbInt13.efi</td></tr>
100 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdKbcEmulEfiEnable|TRUE</td><td>\#KbcEmul.efi & KbcEmulDxe.efi</td></tr>
101 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdLegacySredirBinEnable|TRUE</td><td>\#LegacySredir.efi</td></tr>
102 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdSmmbaseRelocateEfiEnable|TRUE</td><td>\#SmmBaseRelocate.efi</td></tr>
103 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdE0001x3EfiEnable|TRUE</td><td>\#E6023X3.EFI</td></tr>
104 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdRaidDriverEfiEnable|TRUE</td><td>\#RaidDriver.efi</td></tr>
105 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdRsteDriverEfiEnable|TRUE</td><td>\#SataDriverRste.efi</td></tr>
106 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdRstNvmeDriverEfiEnable|TRUE</td><td>\#RstNvmeDriver.efi</td></tr>
107 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdMebxEfiEnable|TRUE</td><td>\#Mebx.efi</td></tr>
108 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdMebxSetupBrowserEnable|TRUE</td><td>\#MebxSetupBrowser.efi</td></tr>
109 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdIntelGopDriverEfiEnable|TRUE</td><td>\#IntelGopDriver.efi</td></tr>
110 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUefiShellBuildSource|FALSE</td><td>\#Shell.efi</td></tr>
111 <tr> <td>gPlatformModuleTokenSpaceGuid.PcdUsbFnEnable|TRUE</td><td>\#UsbDeviceDxe.efi</td></tr>
112 </table>
113 <b>Summary the paths of all Binary as below, depends on platform design some of them may not be required:</b>\n
114 - BpCommonPkg\\Tools\\BpmGen\\*.*
115 - BpCommonPkg\\Tools\\FitGen\\*.*
116 - ClientCommonPkg\\Tools\\LINK16.EXE
117 - KabylakePlatSamplePkg\\Binaries\\Txt\\BiosAcm\\BiosAc.bin
118 - KabylakePlatSamplePkg\\Binaries\\Txt\\BiosAcm\\BiosAcProd.bin
119 - KabylakePlatSamplePkg\\Binaries\\BiosGuard\\BiosGuardModule.bin
120 - KabylakePlatSamplePkg\\Binaries\\BootGuard\\ACM\\StartupAcm.bin
121 - KabylakePlatSamplePkg\\Binaries\\Microcode\\*.*
122 - KabylakePlatSamplePkg\\Binaries\\LegacyRom\\AhciRom\\*.*
123 - KabylakePlatSamplePkg\\Binaries\\LegacyRom\\RaidRom\\*.*
124 - KabylakePlatSamplePkg\\Binaries\\LegacyRom\\VideoRom\\*.*
125 - KabylakePlatSamplePkg\\Tools\\RomImage\\*.*
126 - KabylakePlatSamplePkg\\Tools\\RomImage\\Fit\\*.*
127 - KabylakePlatSamplePkg\\Tools\\RomImage\\KabylakeLP\\*.*
128 - KabylakePlatSamplePkg\\Tools\\RomImage\\KabylakeH\\*.*
129 - KabylakePlatSamplePkg\\ToolScripts\\BpmGen\\*.*
130 - KabylakePlatSamplePkg\\ToolScripts\\FitGen\\*.*
131 - KabylakePlatSamplePkg\\ToolScripts\\SignFv\\*.* (for SignFvPlatform.bat and keys)
132 - KabylakePlatSamplePkg\\Binaries\\UefiDriver\\Gop\\*.*
133 - KabylakePlatSamplePkg\\Binaries\\UefiDriver\\Mebx\\*.*
134 - KabylakePlatSamplePkg\\Binaries\\UefiDriver\\MebxSetupBrowser\\*.*
135 - KabylakePlatSamplePkg\\Binaries\\UefiDriver\\Raid\\*.*\n
136 Note: If FitGen and BpmGen are not required, please remove the lines in KabylakePlatSamplePkg\postbuild.bat where FitGen and BpmGen called.
137 2. Generate Rsa2048Sha256 Private, public PEM key pair and name the file as privkey.pem and pubkey.pem accordingly. Also generate SHA256 hash of public key and include this as RAW file in Firmware volume. Refer pubkeyhash.bin in PlatformPkg.fdf file
138 3. Retrieve KabylakeSiliconPkg (for Source code building) and KabylakeSiliconBinPkg (For release built binary)\n
139 4. All KabylakePlatSamplePkg, KabylakeSiliconPkg and KabylakeSiliconBinPkg should be in root of RoyalPark source\n
140 5. For building with SiPkg source code, go to KabylakePlatSamplePkg and type "prep && bld" to compile the whole source code.\n
141 6. For building with SiBinPkg (Release built binary modules), ensure your code tree has KabylakeSiliconBinPkg then go to KabylakePlatSamplePkg folder and execute "BinBuild.bat r" to compile it\n
142 Note: For Binary model, BinBuild.bat actually just renames KabylakeSiliconBinPkg to KabylakeSiliconPkg (original folder will be renamed too) and then set "gPlatformModuleTokenSpaceGuid.PcdSipkgBinaryEnable|FALSE"\n
143 Refer to KabylakePlatSamplePkg\PlatformPkg.fdf for 'gPlatformModuleTokenSpaceGuid.PcdSipkgBinaryEnable' for how to switch between SiPkg source code build and binary build.\n
144 7. The Full BIOS binary (Descriptor/ME FW + BIOS ROM) generated may not boot on the system as the build steps do not cover all of the strap settings.\n
145 Please get working Descriptor/ME FW and combine with BIOS.ROM generated by this build to be a full Binary to boot the system.
146
147 Note on BootGuard:
148 BootGuard ACM authenticates IBB which includes FVRecovery, FVRecovery2 and FSP FV (only in FSP wrapper build). With this consideration, it is mandated to Sign FVRecovery3, FVMain and FVMain2.
149 SignedSection driver authenticates all signed FVs before launching it and the chain of trust will be maintained.
150
151 Based on the IBB size, BootGuard ACM with release BIOS works on 2MB LLC silicon and BootGuard ACM with both Release/Debug Bioses work on 4MB LLC silicon. This is not a recommendation and 2MB LLC silicon can boot with Debug BIOS too, if the IBB size meets the requirement.
152 Refer to BootGuard BIOS writers guide for more details.
153 **/
154
155 /** @page misc 5 - MiscInfo
156 1. PlatformInitPreMem module will install some policy functions for MRC to consume and if those functions were not in code cache region MRC will run slowly and impact both boot time and S3 resume time.\n
157 Please ensure this module will be always in code cache coverage (according to cache initialization and adjust this module in flash map)\n
158 2. The Secondary NvRam term can be used to describe CMOS as like in RVP BIOS, but it can be EMMC or some other non-volatile memory other than EFI Variable.\n
159 **/
160
161 /** @page BiosImage 6 - Bios Image
162 0. Flash Layout
163 <tr><td> @image html FlashLayout.jpg </td></tr>
164 1. FVMAIN - DXE drivers required to boot platform.\n
165 <table border="1" style="width:1500px">
166 <tr>
167 <th>Driver Name(.inf)</th>
168 <th>Build Condition</th>
169 </tr>
170 <tr><td>8259.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
171 <tr><td>ArpDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
172 <tr><td>AmtPetAlertDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
173 <tr><td>AmtSetupDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
174 <tr><td>AsfTable.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
175 <tr><td>AmtWrapperDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
176 <tr><td>AlertStandardFormatDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
177 <tr><td>ActiveManagement.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
178 <tr><td>AcpiPlatform.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
179 <tr><td>AcpiDebug.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdAcpiDebugEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
180 <tr><td>AcpiTables.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
181 <tr><td>AcpiFvi.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
182 <tr><td>AcpiTableDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
183 <tr><td>AtaBusDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
184 <tr><td>AtaAtapiPassThru.inf</td><td>gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
185 <tr><td>AmdAcpiTable.inf</td><td>gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
186 <tr><td>AmdAcpiTablePch.inf</td><td>gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
187 <tr><td>AcpiGlobalVariable.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
188 <tr><td>AcpiS3SaveDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
189 <tr><td>BootScriptExecutorDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
190 <tr><td>BootTimeDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdBootTimeEnable == TRUE</td></tr>
191 <tr><td>BdsDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
192 <tr><td>BiosExtensionLoader.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
193 <tr><td>BootManagerMenuApp.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE</td></tr>
194 <tr><td>CapsuleRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
195 <tr><td>CpuInitDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
196 <tr><td>CsmPlatformLoader.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
197 <tr><td>CpuIo2Dxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
198 <tr><td>CpuAcpiTables.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
199 <tr><td>ConPlatformDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdConSplitterEnable == TRUE</td></tr>
200 <tr><td>ConSplitterDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdConSplitterEnable == TRUE</td></tr>
201 <tr><td>CpuIoDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
202 <tr><td>DataHubDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdDataHubEnable == TRUE</td></tr>
203 <tr><td>Dhcp4Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
204 <tr><td>DpcDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
205 <tr><td>DatahubStatusCodeHandlerDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdDataHubStatusCodeEnable == TRUE</td></tr>
206 <tr><td>Dhcp6Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
207 <tr><td>DptfAcpiTables.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
208 <tr><td>DptfAcpiTablesSds.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
209 <tr><td>DisplayEngineDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE</td></tr>
210 <tr><td>Dptf.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
211 <tr><td>DxeOverClock.inf</td><td>gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE</td></tr>
212 <tr><td>DriverHealthManagerDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
213 <tr><td>DiskIoDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFatEnable == TRUE</td></tr>
214 <tr><td>EbcDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdEbcEnable == TRUE</td></tr>
215 <tr><td>EmuVariableRuntimeDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == FALSE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
216 <tr><td>E0001X3.EFI</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdE0001x3EfiEnable == TRUE</td></tr>
217 <tr><td>EnglishDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUnicodeCollectionEnable == TRUE</td></tr>
218 <tr><td>EhciDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE</td></tr>
219 <tr><td>EC.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdEcEnable == TRUE</td></tr>
220 <tr><td>EmuVariableRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == FALSE</td></tr>
221 <tr><td>FaultTolerantWriteDummy.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == FALSE</td></tr>
222 <tr><td>FaultTolerantWriteSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE</td></tr>
223 <tr><td>FaultTolerantWriteDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
224 <tr><td>Fat.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdFatEnable == TRUE</td></tr>
225 <tr><td>GopPolicy.inf</td><td>gSiPkgTokenSpaceGuid.PcdIgdEnable == TRUE</td></tr>
226 <tr><td>GopConfig.efi</td><td>gSiPkgTokenSpaceGuid.PcdIgdEnable == TRUE</td></tr>
227 <tr><td>GfxInt15Legacy.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIgdIntHookEnable == TRUE</td></tr>
228 <tr><td>GuidForwardHandlerSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
229 <tr><td>GuidForwardHandlerRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
230 <tr><td>GraphicsConsoleDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdGraphicsConsoleEnable == TRUE</td></tr>
231 <tr><td>GenericMemoryTestDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdMemoryTestEnable == TRUE</td></tr>
232 <tr><td>HddPasswordDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
233 <tr><td>HddPasswordSmm.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
234 <tr><td>HitachH8s2113.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
235 <tr><td>HpetTimerDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdUseHpetTimer == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
236 <tr><td>HiiDatabaseDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE</td></tr>
237 <tr><td>HeciInit.inf</td><td>gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
238 <tr><td>IntegratedTouch.inf</td><td>gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable == TRUE && gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
239 <tr><td>IrqBoardInfoRvpM.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
240 <tr><td>IrqBoardInfoRvpDt.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
241 <tr><td>IrqBoardInfoSvM.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
242 <tr><td>IrqBoardInfoSv.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
243 <tr><td>I2cDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdPiI2cStackEnable == TRUE</td></tr>
244 <tr><td>I2cPlatformDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdPiI2cStackEnable == TRUE</td></tr>
245 <tr><td>I2cMasterDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdPiI2cStackEnable == TRUE</td></tr>
246 <tr><td>IntelUefiRaidDiskInfo.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdIntelRaidEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
247 <tr><td>IsaIoDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
248 <tr><td>IsaSerialDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTerminalEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == FALSE</td></tr>
249 <tr><td>IntelGopDriver.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdIntelGopDriverEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdIgdEnable == TRUE</td></tr>
250 <tr><td>IccPlatformDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
251 <tr><td>IsvtCheckpointDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
252 <tr><td>IrqBoardInfo.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
253 <tr><td>IrqBoardInfoRvp.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
254 <tr><td>IsaAcpi.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
255 <tr><td>IsaBusDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
256 <tr><td>IccOverClocking.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdIccOverClockingBinEnable == TRUE && gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
257 <tr><td>Ip4Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
258 <tr><td>Ip4ConfigDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
259 <tr><td>Ip6Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
260 <tr><td>IpSecDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
261 <tr><td>IScsiDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIscsiEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
262 <tr><td>JpegDecoderDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdJpgEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE</td></tr>
263 <tr><td>JhiDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdJhiEnable == TRUE</td></tr>
264 <tr><td>KeyboardDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
265 <tr><td>LpcSmsc100x.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
266 <tr><td>MnpDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
267 <tr><td>Mebx.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdMebxEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
268 <tr><td>MebxSetupBrowser.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdMebxSetupBrowserEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
269 <tr><td>MeSsdt.inf</td><td>gSiPkgTokenSpaceGuid.PcdPttEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
270 <tr><td>Metronome.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
271 <tr><td>MonotonicCounterRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
272 <tr><td>MeUlvCheckDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
273 <tr><td>Mtftp4Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
274 <tr><td>Mtftp6Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
275 <tr><td>MeSmbiosDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE && gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
276 <tr><td>MePlatformReset.inf</td><td>gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
277 <tr><td>MeFwDowngrade.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
278 <tr><td>NvidiaAcpiTable.inf</td><td>gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
279 <tr><td>NvidiaAcpiTablePch.inf</td><td>gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
280 <tr><td>NationalPC8374L.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
281 <tr><td>NullMemoryTestDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
282 <tr><td>NullMemoryTestDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdMemoryTestEnable == FALSE</td></tr>
283 <tr><td>OpalPasswordDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdOpalPasswordEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
284 <tr><td>OpalPasswordSmm.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdOpalPasswordEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdHddPasswordEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
285 <tr><td>OverclockInterfaceACPI.inf</td><td>gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE</td></tr>
286 <tr><td>OverClockSmiHandler.inf</td><td>gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE</td></tr>
287 <tr><td>OverclockInterface.inf</td><td>gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE</td></tr>
288 <tr><td>Pcd.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
289 <tr><td>PlatformInfoDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
290 <tr><td>PchResetRuntime.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
291 <tr><td>PolicyInitDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
292 <tr><td>PlatformInitDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
293 <tr><td>PcatRealTimeClockRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
294 <tr><td>PlatformFixedPciResource.inf</td><td>gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
295 <tr><td>PciRootBridgeNoEnumeration.inf</td><td>gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
296 <tr><td>PciHostBridge.inf</td><td>gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == FALSE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
297 <tr><td>PlatformSetup.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
298 <tr><td>PchInitDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
299 <tr><td>PciPlatform.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
300 <tr><td>PciBusNoEnumeration.inf</td><td>gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
301 <tr><td>PciBusDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == FALSE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
302 <tr><td>PlatformStatusCodeHandlerSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
303 <tr><td>PlatformPort80HandlerSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
304 <tr><td>PwdCredentialProviderDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE</td></tr>
305 <tr><td>PowerMgmtDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdPpmEnable == TRUE</td></tr>
306 <tr><td>PowerMgmtSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdPpmEnable == TRUE</td></tr>
307 <tr><td>PchSmbusDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
308 <tr><td>PchSmiDispatcher.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
309 <tr><td>PchSpiRuntime.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable==FALSE</td></tr>
310 <tr><td>PchSpiSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE</td></tr>
311 <tr><td>PchInitSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
312 <tr><td>PciHotPlug.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdPciHotplugEnable == TRUE</td></tr>
313 <tr><td>PepBccdSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
314 <tr><td>PartitionDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFatEnable == TRUE</td></tr>
315 <tr><td>PlatformPrivateSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
316 <tr><td>PlatformPrivateDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
317 <tr><td>PchSvSbDxeLate.inf</td><td>gSiPkgTokenSpaceGuid.PcdSvBuild == TRUE</td></tr>
318 <tr><td>PchSvSbSmiLate.inf</td><td>gSiPkgTokenSpaceGuid.PcdSvBuild == TRUE</td></tr>
319 <tr><td>PciBusNoEnumeration.inf</td><td>gSiPkgTokenSpaceGuid.PcdFixedPciBusEnable == TRUE</td></tr>
320 <tr><td>Ps2keyboardDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
321 <tr><td>PiSmmCommunicationSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
322 <tr><td>PttHciSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdPttEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
323 <tr><td>Ps2MouseDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdMouseEnable == TRUE</td></tr>
324 <tr><td>RaidDriver.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdRaidDriverEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
325 <tr><td>RstNvmeDriver.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdNvmeEnable == TRUE</td></tr>
326 <tr><td>ReportStatusCodeRouterRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
327 <tr><td>RuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
328 <tr><td>SmmControl.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
329 <tr><td>SiInitDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
330 <tr><td>SecurityStubDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
331 <tr><td>SmmAccess.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
332 <tr><td>SaInitDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
333 <tr><td>SmmSvDispatcher.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdSmmSvDispatcherEfiEnable == TRUE</td></tr>
334 <tr><td>SecureBootConfigDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE</td></tr>
335 <tr><td>SpcrAcpiDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTerminalEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == FALSE</td></tr>
336 <tr><td>SnpDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
337 <tr><td>SaAcpiTables.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
338 <tr><td>SmbiosMiscDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE</td></tr>
339 <tr><td>SataController.inf</td><td>gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
340 <tr><td>SpiFvbServiceDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
341 <tr><td>SpiFvbServiceSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
342 <tr><td>SerialOverLan.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
343 <tr><td>SgAcpiTables.inf</td><td>gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE</td></tr>
344 <tr><td>SgAcpiTablesPch.inf</td><td>gSiPkgTokenSpaceGuid.PcdSgEnable == TRUE</td></tr>
345 <tr><td>SaveMemoryConfig.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
346 <tr><td>SavePegConfig.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
347 <tr><td>Setup.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE</td></tr>
348 <tr><td>SmmPlatform.inf</td><td>gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE</td></tr>
349 <tr><td>SmmProfileSmi.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSmmProfileEnable == TRUE</td></tr>
350 <tr><td>SmramSaveInfoHandlerSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
351 <tr><td>SimpleBootFlag.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSimpleBootFlagEnable == TRUE</td></tr>
352 <tr><td>SecureEraseDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
353 <tr><td>SmiVariable.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSmiVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
354 <tr><td>SmiVariableInt15.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSmiVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
355 <tr><td>SmiVariableInstallInt15Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSmiVariableEnable == TRUE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
356 <tr><td>SataDriverRste.efi</td><td>gPlatformModuleTokenSpaceGuid.PcdRsteDriverEfiEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE</td></tr>
357 <tr><td>SaSsdt.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
358 <tr><td>SetupBrowserDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE</td></tr>
359 <tr><td>SmbiosDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmbiosEnable == TRUE</td></tr>
360 <tr><td>ScsiBusDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdScsiEnable == TRUE</td></tr>
361 <tr><td>ScsiDiskDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdScsiEnable == TRUE</td></tr>
362 <tr><td>S3SaveStateDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
363 <tr><td>SmmS3SaveState.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
364 <tr><td>SmmLockBox.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE</td></tr>
365 <tr><td>SmmThunk.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdSmmThunkEnable == TRUE</td></tr>
366 <tr><td>TcgConfigDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
367 <tr><td>TcgMor.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
368 <tr><td>TrEEDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
369 <tr><td>TrEESmm.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
370 <tr><td>TrEEConfigDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
371 <tr><td>TrEEPlatformDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
372 <tr><td>TcgDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
373 <tr><td>TcgSmm.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
374 <tr><td>TcgSetupDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
375 <tr><td>TraceHubStatusCodeHandlerSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdTraceHubEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
376 <tr><td>TcpDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
377 <tr><td>Tcp4Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == FALSE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
378 <tr><td>TxtDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE</td></tr>
379 <tr><td>TerminalDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTerminalEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == FALSE</td></tr>
380 <tr><td>I2cTouchPanelDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdI2cTouchDriverEnable == TRUE</td></tr>
381 <tr><td>Tpm2AcpiTables.inf</td><td>gSiPkgTokenSpaceGuid.PcdPttEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
382 <tr><td>TxtSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdStmEnable == TRUE</td></tr>
383 <tr><td>TxtAcpiTables.inf</td><td>gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdStmEnable == TRUE</td></tr>
384 <tr><td>TbtDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTbtEnable == TRUE</td></tr>
385 <tr><td>TbtSmm.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTbtEnable == TRUE</td></tr>
386 <tr><td>TraceHubStatusCodeHandlerRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdTraceHubEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
387 <tr><td>UiApp.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSetupEnable == TRUE</td></tr>
388 <tr><td>UserIdentifyManagerDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE</td></tr>
389 <tr><td>UserProfileManagerDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE</td></tr>
390 <tr><td>UsbCredentialProviderDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUserIdentificationEnable == TRUE</td></tr>
391 <tr><td>Udp6Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkIp6Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
392 <tr><td>UsbTypeC.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbTypeCEnable == TRUE</td></tr>
393 <tr><td>UhciDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE</td></tr>
394 <tr><td>UsbBusDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE</td></tr>
395 <tr><td>UsbKbDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE</td></tr>
396 <tr><td>UsbMassStorageDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE</td></tr>
397 <tr><td>UsbMouseDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE</td></tr>
398 <tr><td>UsbDeviceDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbFnEnable == TRUE</td></tr>
399 <tr><td>Udp4Dxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
400 <tr><td>VariableSmmRuntimeDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE</td></tr>
401 <tr><td>VariableSmm.inf</td><td>gSiPkgTokenSpaceGuid.PcdSmmVariableEnable == TRUE</td></tr>
402 <tr><td>VlanConfigDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdNetworkVlanEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdNetworkEnable == TRUE</td></tr>
403 <tr><td>VirtualKeyboardDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdVirtualKeyboardEnable == TRUE</td></tr>
404 <tr><td>WdtAppDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
405 <tr><td>WinbondWpcn381u.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
406 <tr><td>WatchdogTimer.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
407 <tr><td>WdtDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE</td></tr>
408 <tr><td>XhciDxe.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUsbEnable == TRUE</td></tr>
409 </table>
410 2. FVMAIN2 - DXE drivers for optional features (like CSM legacy support, Overclocking etc.. this will be decompressed and dispatched only when these features are enabled to improve responsiveness.)\n
411 <table border="1" style="width:1500px">
412 <tr>
413 <th>Driver Name(.inf)</th>
414 <th>Build Condition</th>
415 </tr>
416 <tr><td>AmiLegacyBiosHook.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
417 <tr><td>AmtInt16.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
418 <tr><td>AmtInt16Csm.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE</td></tr>
419 <tr><td>BlockIoDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
420 <tr><td>GfxInt15Legacy.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIgdIntHookEnable == TRUE</td></tr>
421 <tr><td>IrqTableInfo.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
422 <tr><td>IntelRaidAtaAtapiPassThru.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIntelRaidEnable == TRUE</td></tr>
423 <tr><td>IntelRaidBiosThunk.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gSiPkgTokenSpaceGuid.PcdAtaEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdIntelRaidEnable == TRUE</td></tr>
424 <tr><td>LegacyInterrupt.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
425 <tr><td>LegacyBiosPlatform.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
426 <tr><td>LegacyBiosDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE</td></tr>
427 <tr><td>LegacyInterruptHook.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE && gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
428 <tr><td>MeUlvCheckDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdMeEnable == TRUE</td></tr>
429 <tr><td>MinUefiShell.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdUefiMiniShellEnable == TRUE</td></tr>
430 <tr><td>Shell.efi</td><td>(Build mode:DEBUG)gPlatformModuleTokenSpaceGuid.PcdUefiShellEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdUefiShellBuildSource == TRUE</td></tr>
431 <tr><td>TcgLegacy.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
432 <tr><td>TcgLegacyInstallInt1A.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
433 <tr><td>TcgLegacy16.inf</td><td>gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE</td></tr>
434 <tr><td>VideoDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
435 <tr><td>VgaClassDxe.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE || gSiPkgTokenSpaceGuid.PcdCsmEnable == TRUE</td></tr>
436 </table>
437 3. FVRECOVERY - SEC phase (keep this separate so that we can place TxtPei in the top 128K of the Flash)\n
438 <table border="1" style="width:1500px">
439 <tr>
440 <th>Driver Name(.inf)</th>
441 <th>Build Condition</th>
442 </tr>
443 <tr><td>FspWrapperReportFv.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
444 <tr><td>Pcd.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
445 <tr><td>ReportFvRecoveryPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
446 <tr><td>SecCore.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
447 <tr><td>SecCoreFsp.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
448 <tr><td>TxtPeiAp.inf</td><td>gSiPkgTokenSpaceGuid.PcdTxtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
449 </table>
450 4. FVRECOVERY2 - PeiMain/MRC/SiInit/BoardInit/PlatformInit (pre memory modules which is uncompressed)\n
451 <table border="1" style="width:1500px">
452 <tr>
453 <th>Driver Name(.inf)</th>
454 <th>Build Condition</th>
455 </tr>
456 <tr><td>AmtStatusCodePei.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
457 <tr><td>AmtStatusCodePei.inf</td><td>gSiPkgTokenSpaceGuid.PcdAmtEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
458 <tr><td>BiosInfoChecker.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE && gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
459 <tr><td>BiosInfo.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
460 <tr><td>CpuIoPei.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
461 <tr><td>CapsulePei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
462 <tr><td>CapsuleX64.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
463 <tr><td>CodeCoveragePeiBin.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdCodeCoverageEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
464 <tr><td>CmosAccessPei.inf</td><td>(Build mode:DEBUG)gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
465 <tr><td>DxeIpl.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
466 <tr><td>DebugServicePei.inf</td><td>(Build mode:DEBUG)gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
467 <tr><td>FaultTolerantWritePei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
468 <tr><td>FirmwarePerformancePei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
469 <tr><td>FpdtPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdPerformanceEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
470 <tr><td>PlatformStatusCodeHandlerPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
471 <tr><td>PlatformPort80HandlerPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
472 <tr><td>PcatSingleSegmentPciCfg2Pei.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
473 <tr><td>Pcd.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
474 <tr><td>PlatformInitPreMem.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
475 <tr><td>PhysicalPresencePei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
476 <tr><td>PeiOverClock.inf</td><td>gSiPkgTokenSpaceGuid.PcdOverclockEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
477 <tr><td>PiSmmCommunicationPei.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
478 <tr><td>SignedSectionPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
479 <tr><td>SiInitPreMem.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
480 <tr><td>S3Resume2Pei.inf</td><td>gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
481 <tr><td>TraceHubStatusCodeHandlerPei.inf</td><td>gSiPkgTokenSpaceGuid.PcdTraceHubEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
482 <tr><td>TrEEConfigPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
483 <tr><td>TrEEPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
484 <tr><td>TcgPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
485 <tr><td>VariablePei.inf</td><td>gSiPkgTokenSpaceGuid.PcdSleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
486 </table>
487 5. FVRECOVERY3 - PEI drivers which can be compressed (these are post-memory modules not in CAR range)\n
488 <table border="1" style="width:1500px">
489 <tr>
490 <th>Driver Name(.inf)</th>
491 <th>Build Condition</th>
492 </tr>
493 <tr><td>CapsulePei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
494 <tr><td>CapsuleX64.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdCapsuleEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
495 <tr><td>DxeIpl.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
496 <tr><td>FaultTolerantWritePei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
497 <tr><td>FspWrapperInit.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
498 <tr><td>FspWrapperPeim.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
499 <tr><td>IntelGraphicsPeim.efi</td><td>gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
500 <tr><td>PlatformInit.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == FALSE</td></tr>
501 <tr><td>PlatformInitPreMem.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
502 <tr><td>PhysicalPresencePei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
503 <tr><td>SignedSectionPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
504 <tr><td>TrEEConfigPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
505 <tr><td>TrEEPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpm2Enable == TRUE && gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
506 <tr><td>TcgPei.inf</td><td>gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE && gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE</td></tr>
507 </table>
508 6. BiosGuardModuleFv - Bios Guard binary module (technical this could be generic binaries FV or part of FV_Recovery2 or 3).\n
509 \# TXT ACM and BootGuard ACM will be moved out of FVRecovery2 into BiosGuardModuleFV and rename it to FV_BINARIES.\n
510 7. FvFSP - FSP binary (this can be split into three separate FVs FSP-T, FSP-M and FSP-S as these can be placed in different regions of flash part).\n
511 8. Note - \n
512 \# multiple Recovery FV design is to maintain flexibility to manage platforms with different LLC size.\n
513 \# BootGuard IBB = FVRecovery + FvFSP + FvRecovery2. To maintain the chain of trust, FvRecovery3, FvMain and FvMain2 firmware volumes need to be signed and authenticated during UEFI Bios boot.\n
514 **/
515
516 /** @page PowerButtonOverride 7 - Power Button Override
517 Both pre-OS & OS via PCH register programming are enabled 10 seconds override feature but It's not easy to observe in pre-OS phase,\n
518 because in pre-OS phase Power Button SMI will be triggered first with system shutdown before 10 seconds override timer expiration.\n
519 1) Under UEFI Shell : Upon power button press, system goes to shutdown state immediately.\n
520 2) Under OS: Upon power button press, OS will perform actions according to OS design (ex: user confirmation with a few seconds of power button pressing);\n
521 Until 10 seconds after power button keeping pressed, system goes to shutdown state.
522 **/
523
524 /** @page PostCode 8 - Post Code
525 - Post code format aligns to Silicon definition
526 Actual Post code displayed will be 16 bits(4 Bytes). Upper 4 bits will be added by Base PostCode Library(either by FSP or EDKII).\n
527 Example : Let's assume Post code as 0xWXYZ\n
528 - Update for platform code\n
529 XYZ is added by component\n
530 W indicate the phase BIOS is running. 0: SEC/PEI; 1: DXE\n
531 <BR>
532 <CENTER>
533 <STRONG>Post Code</STRONG>
534 </CENTER>
535 <table border="1" style="width:1200px">
536 <tr>
537 <th>Post Code</th>
538 <th>Progress Code</th>
539 <th>Description</th>
540 </tr>
541 <tr> <td>0x10</td> <td>PEI_CORE_STARTED</td> <td> Stared Core </td> </tr>
542 <tr> <td>0x11</td> <td>PEI_CAR_CPU_INIT</td> <td> Init Car CPU </td> </tr>
543 <tr> <td>0x1D</td> <td>PEI_MEMORY_SPD_READ</td> <td> Read SPD Memory </td> </tr>
544 <tr> <td>0x1E</td> <td>PEI_MEMORY_PRESENCE_DETECT</td> <td> Detect Memory Presence </td> </tr>
545 <tr> <td>0x1F</td> <td>PEI_MEMORY_TIMING</td> <td> Memory Timing </td> </tr>
546 <tr> <td>0x20</td> <td>PEI_MEMORY_CONFIGURING</td> <td> Memory Configuring </td> </tr>
547 <tr> <td>0x21</td> <td>PEI_MEMORY_INIT</td> <td> Init Memory </td> </tr>
548 <tr> <td>0x31</td> <td>PEI_MEMORY_INSTALLED</td> <td> Installed Memory </td> </tr>
549 <tr> <td>0x32</td> <td>PEI_CPU_INIT</td> <td> CPU Init </td> </tr>
550 <tr> <td>0x33</td> <td>PEI_CPU_CACHE_INIT</td> <td> Init CPU Cache </td> </tr>
551 <tr> <td>0x34</td> <td>PEI_CPU_BSP_SELECT</td> <td> Select CPU BSP </td> </tr>
552 <tr> <td>0x35</td> <td>PEI_CPU_AP_INIT</td> <td> Init CPU AP </td> </tr>
553 <tr> <td>0x36</td> <td>PEI_CPU_SMM_INIT</td> <td> Init CPU SMM </td> </tr>
554 <tr> <td>0x37</td> <td>PEI_MEM_NB_INIT</td> <td> Init Memory NB </td> </tr>
555 <tr> <td>0x3B</td> <td>PEI_MEM_SB_INIT</td> <td> Init Memory SB </td> </tr>
556 <tr> <td>0x4F</td> <td>PEI_DXE_IPL_STARTED</td> <td> Started PEI DXE IPL </td> </tr>
557 <tr> <td>0xF0</td> <td>PEI_RECOVERY_AUTO</td> <td> Auto Recovery </td> </tr>
558 <tr> <td>0xF1</td> <td>PEI_RECOVERY_USER</td> <td> User Recovery </td> </tr>
559 <tr> <td>0xF2</td> <td>PEI_RECOVERY_STARTED</td> <td> Started Recovery </td> </tr>
560 <tr> <td>0xF3</td> <td>PEI_RECOVERY_CAPSULE_FOUND</td> <td> Found Recovery Capsule </td> </tr>
561 <tr> <td>0xF4</td> <td>PEI_RECOVERY_CAPSULE_LOADED</td> <td> Loaded Recovery Capsule </td> </tr>
562 <tr> <td>0xE0</td> <td>PEI_S3_STARTED</td> <td> Start S3 </td> </tr>
563 <tr> <td>0xE1</td> <td>PEI_S3_BOOT_SCRIPT</td> <td> S3 Boot Script </td> </tr>
564 <tr> <td>0xE2</td> <td>PEI_S3_VIDEO_REPOST</td> <td> Repost S3 Video </td> </tr>
565 <tr> <td>0xE3</td> <td>PEI_S3_OS_WAKE</td> <td> Wake S3 OS </td> </tr>
566 <tr> <td>0x1060</td> <td>DXE_CORE_STARTED</td> <td> Started Core </td> </tr>
567 <tr> <td>0x1062</td> <td>DXE_SBRUN_INIT</td> <td> Init SBRUN </td> </tr>
568 <tr> <td>0x1068</td> <td>DXE_NB_HB_INIT</td> <td> Init NB HB </td> </tr>
569 <tr> <td>0x1069</td> <td>DXE_NB_INIT</td> <td> Init NB </td> </tr>
570 <tr> <td>0x106A</td> <td>DXE_NB_SMM_INIT</td> <td> Init NB SMM </td> </tr>
571 <tr> <td>0x1070</td> <td>DXE_SB_INIT</td> <td> SInit SB </td> </tr>
572 <tr> <td>0x1071</td> <td>DXE_SB_SMM_INIT</td> <td> Init SB SMM </td> </tr>
573 <tr> <td>0x1072</td> <td>DXE_SB_DEVICES_INIT</td> <td> Init SB Device </td> </tr>
574 <tr> <td>0x1090</td> <td>DXE_BDS_STARTED</td> <td> Started BDS </td> </tr>
575 <tr> <td>0x1092</td> <td>DXE_PCI_BUS_BEGIN</td> <td> Begin PCI BUS </td> </tr>
576 <tr> <td>0x1093</td> <td>DXE_PCI_BUS_HPC_INIT</td> <td> Init HPC BUS </td> </tr>
577 <tr> <td>0x1094</td> <td>DXE_PCI_BUS_ENUM</td> <td> Enum PCI BUS </td> </tr>
578 <tr> <td>0x1095</td> <td>DXE_PCI_BUS_REQUEST_RESOURCES</td> <td> Request PCI BUS Resources </td> </tr>
579 <tr> <td>0x1096</td> <td>DXE_PCI_BUS_ASSIGN_RESOURCES</td> <td> Assign PCI BUS Resources </td> </tr>
580 <tr> <td>0x1097</td> <td>DXE_CON_OUT_CONNECT</td> <td> CON OUT Connect </td> </tr>
581 <tr> <td>0x1098</td> <td>DXE_CON_IN_CONNECT</td> <td> CON IN Connect </td> </tr>
582 <tr> <td>0x1099</td> <td>DXE_SIO_INIT</td> <td> Init SIO </td> </tr>
583 <tr> <td>0x109A</td> <td>DXE_USB_BEGIN</td> <td> Begin USB </td> </tr>
584 <tr> <td>0x109B</td> <td>DXE_USB_RESET</td> <td> Reset USB </td> </tr>
585 <tr> <td>0x109C</td> <td>DXE_USB_DETECT</td> <td> Detect USB </td> </tr>
586 <tr> <td>0x109D</td> <td>DXE_USB_ENABLE</td> <td> Enable USB </td> </tr>
587 <tr> <td>0x10A1</td> <td>DXE_IDE_BEGIN</td> <td> Begin IDE </td> </tr>
588 <tr> <td>0x10A2</td> <td>DXE_IDE_RESET</td> <td> Reset IDE </td> </tr>
589 <tr> <td>0x10A3</td> <td>DXE_IDE_DETECT</td> <td> Detect IDE </td> </tr>
590 <tr> <td>0x10A4</td> <td>DXE_IDE_ENABLE</td> <td> Enable IDE </td> </tr>
591 <tr> <td>0x10A5</td> <td>DXE_SCSI_BEGIN</td> <td> Begin SCSI </td> </tr>
592 <tr> <td>0x10A6</td> <td>DXE_SCSI_RESET</td> <td> Reset SCSI </td> </tr>
593 <tr> <td>0x10A7</td> <td>DXE_SCSI_DETECT</td> <td> Detect SCSI </td> </tr>
594 <tr> <td>0x10A8</td> <td>DXE_SCSI_ENABLE</td> <td> Enable SCSI </td> </tr>
595 <tr> <td>0x10AB</td> <td>DXE_SETUP_START</td> <td> Start Setup </td> </tr>
596 <tr> <td>0x10AC</td> <td>DXE_SETUP_INPUT_WAIT</td> <td> Wait Setup Input </td> </tr>
597 <tr> <td>0x10AD</td> <td>DXE_READY_TO_BOOT</td> <td> Ready To Boot </td> </tr>
598 <tr> <td>0x10AE</td> <td>DXE_LEGACY_BOOT</td> <td> Legacy Boot </td> </tr>
599 <tr> <td>0x10AF</td> <td>DXE_EXIT_BOOT_SERVICES</td> <td> Exit Boot Services </td> </tr>
600 <tr> <td>0x10B0</td> <td>RT_SET_VIRTUAL_ADDRESS_MAP_BEGIN</td> <td> Begin Set RT Virtual Address Map </td> </tr>
601 <tr> <td>0x10B1</td> <td>RT_SET_VIRTUAL_ADDRESS_MAP_END</td> <td> End Set RT Virtual Address Map </td> </tr>
602 <tr> <td>0x10B2</td> <td>DXE_LEGACY_OPROM_INIT</td> <td> Init Legacy OPROM </td> </tr>
603 <tr> <td>0x10B3</td> <td>DXE_RESET_SYSTEM</td> <td> Reset System </td> </tr>
604 <tr> <td>0x10B4</td> <td>DXE_USB_HOTPLUG</td> <td> HotPlug USB </td> </tr>
605 <tr> <td>0x10B5</td> <td>DXE_PCI_BUS_HOTPLUG</td> <td> HotPlug PCI BUS </td> </tr>
606 <tr> <td>0x50</td> <td>PEI_MEMORY_INVALID_TYPE</td> <td> Invalid Memory Type</td> </tr>
607 <tr> <td>0x50</td> <td>PEI_MEMORY_INVALID_SPEED</td> <td> Invalid Memory Speed </td> </tr>
608 <tr> <td>0x51</td> <td>PEI_MEMORY_SPD_FAIL</td> <td> SPD Memory Fail </td> </tr>
609 <tr> <td>0x52</td> <td>PEI_MEMORY_INVALID_SIZE</td> <td> Invalid Memory Size </td> </tr>
610 <tr> <td>0x52</td> <td>PEI_MEMORY_MISMATCH</td> <td> Mismatch Memory </td> </tr>
611 <tr> <td>0x53</td> <td>PEI_MEMORY_NOT_DETECTED</td> <td> Not Detected Memory </td> </tr>
612 <tr> <td>0x53</td> <td>PEI_MEMORY_NONE_USEFUL</td> <td> None Useful Memory </td> </tr>
613 <tr> <td>0x54</td> <td>PEI_MEMORY_ERROR</td> <td> Memory Error </td> </tr>
614 <tr> <td>0x55</td> <td>PEI_MEMORY_NOT_INSTALLED</td> <td> Not Installed Memory </td> </tr>
615 <tr> <td>0x56</td> <td>PEI_CPU_INVALID_TYPE</td> <td> Invalid CPU Type </td> </tr>
616 <tr> <td>0x56</td> <td>PEI_CPU_INVALID_SPEED</td> <td> Invalid CPU Speed </td> </tr>
617 <tr> <td>0x57</td> <td>PEI_CPU_MISMATCH</td> <td> Mismatch CPU </td> </tr>
618 <tr> <td>0x58</td> <td>PEI_CPU_SELF_TEST_FAILED</td> <td> Self CPU Tsst Failed </td> </tr>
619 <tr> <td>0x58</td> <td>PEI_CPU_CACHE_ERROR</td> <td> CPU Cache Error </td> </tr>
620 <tr> <td>0x59</td> <td>PEI_CPU_MICROCODE_UPDATE_FAILED</td> <td> CPU Microcode Update Failed </td> </tr>
621 <tr> <td>0x59</td> <td>PEI_CPU_NO_MICROCODE</td> <td> No CPU Microcode </td> </tr>
622 <tr> <td>0x5A</td> <td>PEI_CPU_INTERNAL_ERROR</td> <td> Internal CPU Error </td> </tr>
623 <tr> <td>0x5A</td> <td>PEI_CPU_ERROR</td> <td> CPU Error </td> </tr>
624 <tr> <td>0x5B</td> <td>PEI_RESET_NOT_AVAILABLE</td> <td> Not Available Reset </td> </tr>
625 <tr> <td>0xF8</td> <td>PEI_RECOVERY_PPI_NOT_FOUND</td> <td> Not Found PPI Recovery </td> </tr>
626 <tr> <td>0xF9</td> <td>PEI_RECOVERY_NO_CAPSULE</td> <td> No Capsule Recovery </td> </tr>
627 <tr> <td>0xFA</td> <td>PEI_RECOVERY_INVALID_CAPSULE</td> <td> Invalid Capsule Recovery </td> </tr>
628 <tr> <td>0xE8</td> <td>PEI_MEMORY_S3_RESUME_FAILED</td> <td> Memory S3 Resume Failed </td> </tr>
629 <tr> <td>0xE9</td> <td>PEI_S3_RESUME_PPI_NOT_FOUND</td> <td> S3 Resume PPI Not Found </td> </tr>
630 <tr> <td>0xEA</td> <td>PEI_S3_BOOT_SCRIPT_ERROR</td> <td> S3 Boot Script Error </td> </tr>
631 <tr> <td>0xEB</td> <td>PEI_S3_OS_WAKE_ERROR</td> <td> S3 OS Wake Error </td> </tr>
632 <tr> <td>0x1058</td> <td>DXE_CPU_SELF_TEST_FAILED</td> <td> Self CPU Test Failed </td> </tr>
633 <tr> <td>0x10D1</td> <td>DXE_NB_ERROR</td> <td> NB Error </td> </tr>
634 <tr> <td>0x10D2</td> <td>DXE_SB_ERROR</td> <td> SB Error </td> </tr>
635 <tr> <td>0x10D3</td> <td>DXE_ARCH_PROTOCOL_NOT_AVAILABLE</td> <td> Not Available ARCH Protocol </td> </tr>
636 <tr> <td>0x10D4</td> <td>DXE_PCI_BUS_OUT_OF_RESOURCES</td> <td> Out of PCI BUS Resources </td> </tr>
637 <tr> <td>0x10D5</td> <td>DXE_LEGACY_OPROM_NO_SPACE</td> <td> No Legacy OPROM Space </td> </tr>
638 <tr> <td>0x10D6</td> <td>DXE_NO_CON_OUT</td> <td> NO CON OUT </td> </tr>
639 <tr> <td>0x10D7</td> <td>DXE_NO_CON_IN</td> <td> NO CON IN </td> </tr>
640 <tr> <td>0x10D8</td> <td>DXE_INVALID_PASSWORD</td> <td> Invalid Password </td> </tr>
641 <tr> <td>0x10D9</td> <td>DXE_BOOT_OPTION_LOAD_ERROR</td> <td> Boot Option Laod Error </td> </tr>
642 <tr> <td>0x10DA</td> <td>DXE_BOOT_OPTION_FAILED</td> <td> Boot Option Failed </td> </tr>
643 <tr> <td>0x10DB</td> <td>DXE_FLASH_UPDATE_FAILED</td> <td> Falsh Update Failed </td> </tr>
644 <tr> <td>0x10DC</td> <td>DXE_RESET_NOT_AVAILABLE</td> <td> Not Available Reset </td> </tr>
645 </table>
646 **/
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DoxygenRpOverride.h Source File

  • Override
DoxygenRpOverride.h
Go to the documentation of this file.
1 /** @file
2 This file contains doxygen commands definitions for creating
3 Platform override documentation
4
5 @copyright
6 Copyright (c) 2017 Intel Corporation. All rights reserved
7 This software and associated documentation (if any) is furnished
8 under a license and may only be used or copied in accordance
9 with the terms of the license. Except as permitted by such
10 license, no part of this software or documentation may be
11 reproduced, stored in a retrieval system, or transmitted in any
12 form or by any means without the express written consent of
13 Intel Corporation.
14 This file contains an 'Sample Driver' and is
15 licensed for Intel CPUs and chipsets under the terms of your
16 license agreement with Intel or your vendor. This file may
17 be modified by the user, subject to additional terms of the
18 license agreement
19 **/
20
21 /**
22 @page royalparkplatformoverride
23
24 Royal Park Platform Override tags (RPPO-XXX-XXXX) document issues that a Platform team has resolved with an override of Royal Park.
25
26 The Active RPPO table lists every issue which is currently resolved with an override. It is a catalog of all such existing overrides.
27
28 The Retired RPPO table lists issues which previously required such overrides. It is purely historical as these overrides have all been deleted (are no longer needed).
29 <BR>
30 <CENTER>
31 <STRONG>Active RPPO-ICLs</STRONG>
32 <BR>in IceLakePlatSamplePkg/Override
33 </CENTER>
34
35 <table border="1" style="width:1200px">
36 <tr>
37 <th>Tag</th>
38 <th>Client HSD</th>
39 <th>BP HSD</th>
40 <th>Status / Planned EOL</th>
41 <th>Area</th>
42 <th>Description</th>
43 </tr>
44 <tr> <td>RPPO-SKL-0002</td> <td>1205700453</td> <td></td> <td></td> <td>PLATFORM</td> <td>ASSERT if use third-party AHCI whose port number exceed 3.</td> </tr>
45 <tr> <td>RPPO-SKL-0003</td> <td>1205953088</td> <td></td> <td></td> <td>PLATFORM</td> <td>AhciMode.c spend 10ms on each un-plugged port.</td> </tr>
46 <tr> <td>RPPO-SKL-0004</td> <td>1206090050</td> <td></td> <td></td> <td>PLATFORM</td> <td>Marvell 9182 AHCI controller can't drive up in native UEFI mode.</td> </tr>
47 <tr> <td>RPPO-SKL-0015</td> <td>1206352998</td> <td></td> <td></td> <td>SECURITY</td> <td>NEWCENTURY_STS SMI causes hang in SKL Bios</td> </tr>
48 <tr> <td>RPPO-SKL-0026</td> <td>1404331317</td> <td></td> <td></td> <td>PLATFORM</td> <td>HSTI optimization platform driver is not present in SKL/KBL causing 600+ ms of extra post time</td> </tr>
49 <tr> <td>RPPO-SKL-0033</td> <td>1504083754</td> <td></td> <td></td> <td>CORE</td> <td>Override FCE tools in KBL stream to resolve long delay during build process</td> </tr>
50 <tr> <td>RPPO-KBL-0043</td> <td>1206371435</td> <td></td> <td></td> <td>CORE</td> <td>Add GCC Support to Kabylake BIOS</td> </tr>
51 <tr> <td>RPPO-CNL-0042</td> <td>1404702096</td> <td></td> <td></td> <td>PCH</td> <td>UFS command timeout is set too high in V26 BIOS</td> </tr>
52 <tr> <td>RPPO-KBL-0069</td> <td>1208882263</td> <td></td> <td></td> <td>SECURITY</td> <td>ME HFSTS resgisters change based on power source and causes inconsistent TPM measurements.</td> </tr>
53 <tr> <td>RPPO-CNL-0052</td> <td>1209012154</td> <td></td> <td></td> <td>PLATFORM</td> <td>Enable Catalog Build in one tree KBL tip</td> </tr>
54 <tr> <td>RPPO-CNL-0053</td> <td>1604228165</td> <td></td> <td></td> <td>PCH</td> <td>[CNL-Z0 RVP UFS] UFS is detecting in the BIOS, unable to boot and install OS</td> </tr>
55 <tr> <td>RPPO-CNL-0061</td> <td>1604324896</td> <td></td> <td></td> <td>PLATFORM</td> <td>[CNL U1] Adding support for USB 3.1 Gen2 device detection (superspeedplus). XHCI Spec update is needed to remove this Override.</td> </tr>
56 <tr> <td>RPPO-CNL-0062</td> <td>220151832</td> <td></td> <td></td> <td>SECURITY</td> <td>[CFL43e-CNP] - TXT fails to launch on CFL43e/CNP</td> </tr>
57 <tr> <td>RPPO-CNL-0065</td> <td>1604351459</td> <td></td> <td></td> <td>CORE</td> <td>SPI DTPM 2.0 not enumerating in TPM management console and Device manager </tr>
58 <tr> <td>RPPO-ICL-0002</td> <td>220512590</td> <td></td> <td></td> <td>CORE</td> <td>Preserve descriptors across call to PciGetBusRange</td> </tr>
59 </table>
60
61 <BR>
62 <CENTER>
63 <STRONG>Retired RPPOs</STRONG>
64 <BR>formerly in IcelakePlatSamplePkg/Override
65 </CENTER>
66
67 <table border="1" style="width:1200px">
68 <tr>
69 <th>Tag</th>
70 <th>Client HSD</th>
71 <th>BP HSD</th>
72 <th>Status / Planned EOL</th>
73 <th>Area</th>
74 <th>Description</th>
75 </tr>
76 <tr> <td>RPPO-ICL-xxxx</td> <td></td> <td></td> <td></td> <td></td> <td></td> </tr>
77 <tr> <td>RPPO-ICL-0001</td> <td>1604288624</td> <td></td> <td></td> <td>SHELL</td> <td>Reporting Incorrect data in Type 0, 2,3 and 10</td> </tr>
78 <tr> <td>RPPO-KBL-0038</td> <td>1207163253</td> <td></td> <td></td> <td>PLATFORM</td> <td>System boots to EFI after flashing new SPI image</td> </tr>
79 <tr> <td>RPPO-CNL-0063</td> <td>1405865867</td> <td></td> <td></td> <td>PCH</td> <td>UFS Should be checking for UFS_DEVICE_PATH not SCSI_DEVICE_PATH </tr>
80 <tr> <td>RPPO-CNL-0064</td> <td>220190201</td> <td></td> <td></td> <td>CORE</td> <td>[CNL]ASSERT in CNL Debug Performance Build with UDK2017 RC3 </tr>
81 </table>
82
83 **/
84
85
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DsAllocation.h Source File

DsAllocation.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DS_ALLOCATION_H_
35 #define _DS_ALLOCATION_H_
36
37
38 VOID
39 DsAllocation (
40 VOID
41 )
42 /*++
43
44 Routine Description:
45
46 Allocate NEM buffer for Data Store function and set callback for DRAM allocation in PEI phase
47
48 Arguments:
49
50 None
51
52 Returns:
53
54 None
55
56 --*/
57 ;
58
59 EFI_STATUS
60 EFIAPI
61 DsRamAllocationCallback (
62 IN EFI_PEI_SERVICES **PeiServices,
63 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
64 IN VOID *Ppi
65 )
66 /*++
67
68 Routine Description:
69
70 Internal function to allocate RAM buffer for DS function in PEI phase
71
72 Arguments:
73
74 PeiServices General purpose services available to every PEIM.
75 NotifyDescriptor The notification structure this PEIM registered on install.
76 Ppi The memory discovered PPI. Not used.
77
78 Returns:
79
80 EFI_SUCCESS The function completed successfully.
81
82 --*/
83 ;
84
85 #endif // _DS_ALLOCATION_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DsConfig.h Source File

DsConfig.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DS_CONFIG_H_
35 #define _DS_CONFIG_H_
36
37 //
38 // This is the GUID that is used to uniquely identify DS Config SWBPEs
39 // to the debugger
40 //
41 #define DS_CONFIG_SWBPE_GUID \
42 { 0x1a237f6e, 0xfa50, 0x4338, { 0xae, 0x36, 0x6c, 0x89, 0x38, 0xa7, 0xf2, 0xc2 } }
43
44 //
45 // These are the ID values for DS SWBPEs
46 //
47 typedef enum {
48 DsConfigSwbpeIdUndefined = 0,
49 DsConfigSwBpeIdCheck = 1,
50 DsConfigSwBpeIdNemStart = 2,
51 DsConfigSwBpeIdNemStop = 3,
52 DsConfigSwBpeIdDramStart = 4,
53 DsConfigSwBpeIdDramStop = 5,
54 DsConfigSwBpeIdMax = 6
55 } DS_CONFIG_SWBPE_ID;
56
57
58 //
59 // This is the DS-specific data that firmware will
60 // pass to the debugger via the DebuggerArgs field of
61 // SWBPE_MAILBOX.
62 //
63 #pragma pack (push, 1)
64 typedef struct {
65 EFI_GUID Guid;
66 UINT64 Id;
67 EFI_PHYSICAL_ADDRESS BaseAddress;
68 UINT64 Size;
69 EFI_STATUS *Status;
70 } DS_CONFIG_SWBPE_MAILBOX;
71 #pragma pack (pop)
72
73
74 VOID
75 DsBreakpointEvent (
76 IN DS_CONFIG_SWBPE_ID Id,
77 IN EFI_PHYSICAL_ADDRESS BaseAddress, OPTIONAL
78 IN UINTN Size, OPTIONAL
79 OUT EFI_STATUS *Status
80 )
81 /*++
82
83 Routine Description:
84
85 This function generates a SWBPE event. It will create a DS_CONFIG_SWBPE_MAILBOX structure
86 with the DS_CONFIG_SWBPE_GUID and the input arguments and trigger an implementation specific
87 SWBPE.
88
89 Arguments:
90
91 Id - The event being signalled to the debugger
92 BaseAddress - The address of the buffer. This is not used for some ID.
93 Size - The size of the buffer. This is not used for some ID.
94 Status - The status returned by the debugger.
95
96 Returns:
97
98 EFI_SUCCESS - The function event was intercepted by the debugger and handled successfully
99 EFI_UNSUPPORTED - The function event was not intercepted by the debugger and not handled
100
101 --*/
102 ;
103
104 #endif // _DS_CONFIG_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeAcpiGnvsInitLib.h Source File

  • Library
DxeAcpiGnvsInitLib.h
Go to the documentation of this file.
1 /** @file
2 Acpi Gnvs Init Library header file.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Base.h>
36
37
38 /**
39 @brief
40 Global NVS initialize.
41
42 @param[in] PlatformNvsAreaPtr - Pointer of global NVS area
43
44 @retval EFI_SUCCESS - Allocate Global NVS completed.
45 @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for PlatformNvsAreaProtocol.
46 **/
47 EFI_STATUS
48 EFIAPI
49 AcpiGnvsInit (
50 IN OUT VOID **PlatformNvsAreaPtr
51 );
52
AcpiGnvsInit
EFI_STATUS AcpiGnvsInit(IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeAmtPolicyUpdateLib.h Source File

  • Library
DxeAmtPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _DXE_AMT_POLICY_UPDATE_LIB_H_
34 #define _DXE_AMT_POLICY_UPDATE_LIB_H_
35
36 EFI_STATUS
37 EFIAPI
38 UpdateDxeAmtPolicy (
39 IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy
40 )
41 /*++
42
43 Routine Description:
44
45 Update DxeAmtPolicy with setup values
46
47 Arguments:
48
49 DxeAmtPolicy DXE Amt Policy
50
51 Returns:
52
53 EFI_SUCCESS Initialization complete.
54 EFI_UNSUPPORTED The chipset is unsupported by this driver.
55 EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
56 EFI_DEVICE_ERROR Device error, driver exits abnormally.
57
58 --*/
59 ;
60 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeCpuPolicyUpdateLib.h Source File

  • Library
DxeCpuPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2011 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _DXE_CPU_POLICY_UPDATE_LIB_H_
34 #define _DXE_CPU_POLICY_UPDATE_LIB_H_
35
36 #include <PiDxe.h>
37 #include <PchAccess.h>
38 #include <SetupVariable.h>
39 #include <Library/DebugLib.h>
40 #include <Library/BaseMemoryLib.h>
41 #include <Library/UefiRuntimeServicesTableLib.h>
42 #include <Library/UefiBootServicesTableLib.h>
43 #include <Protocol/CpuPolicyProtocol.h>
44
45 /**
46
47 This function prints the CPU DXE phase policy.
48
49 @param[in] DxeCpuPolicy - CPU DXE Policy protocol
50
51 **/
52 VOID
53 CpuDxePrintPolicyProtocol (
54 IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
55 );
56
57 /**
58
59 Routine Description:
60
61 This function updates Dxe Cpu Policy Protocol
62
63 Arguments:
64
65 @param[in] DxeCpuPolicy The Cpu Policy protocol instance
66
67 Returns:
68
69 @retval EFI_SUCCESS Initialization complete.
70 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
71 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
72 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
73
74 **/
75 EFI_STATUS
76 EFIAPI
77 UpdateDxeSiCpuPolicy (
78 IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
79 );
80
81 /**
82
83 CpuInstallPolicyProtocol installs CPU Policy.
84 While installed, RC assumes the Policy is ready and finalized. So please update and override
85 any setting before calling this function.
86
87 @param[in] ImageHandle Image handle of this driver.
88 @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol instance
89
90 @retval EFI_SUCCESS The policy is installed.
91 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
92
93 **/
94 EFI_STATUS
95 EFIAPI
96 CpuInstallPolicyProtocol (
97 IN EFI_HANDLE ImageHandle,
98 IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
99 );
100
101 #endif
UpdateDxeSiCpuPolicy
EFI_STATUS UpdateDxeSiCpuPolicy(IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
Routine Description:
CpuInstallPolicyProtocol
EFI_STATUS CpuInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
CpuInstallPolicyProtocol installs CPU Policy.
CpuDxePrintPolicyProtocol
VOID CpuDxePrintPolicyProtocol(IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
This function prints the CPU DXE phase policy.
SetupVariable.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeFirmwareVersionInfoLib.h Source File

  • Library
DxeFirmwareVersionInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Private data structures
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _DXE_FIRMWARE_VERSION_INFO_LIB_H_
36 #define _DXE_FIRMWARE_VERSION_INFO_LIB_H_
37
38 #define PLATFORM_FVI_STATUS_DISABLED "Disabled"
39 #define PLATFORM_FVI_STATUS_ENABLED "Enabled "
40
41 #define PLATFORM_FVI_SETUP_NAME L"PlatformFviSetupDataVar"
42
43 //
44 // Ensure proper structure formats
45 //
46 #pragma pack(1)
47
48 typedef struct {
49 UINT8 LanPhyVersion;
50 UINT16 IccMajorVersion;
51 UINT16 IccMinorVersion;
52 UINT16 IccHotfixVersion;
53 UINT16 IccBuildVersion;
54 } PLATFORM_FVI_SETUP;
55
56 #pragma pack()
57
58
59 #define SENSOR_FW_FVI_STRING "Sensor Firmware Version"
60 #define SENSOR_FW_VERSION \
61 { \
62 0xFF, 0xFF, 0xFF, 0xFFFF \
63 }
64
65 #define LAN_PHY_FVI_STRING "Lan Phy Version"
66 #define LAN_PHY_VERSION \
67 { \
68 0xFF, 0xFF, 0xFF, 0xFFFF \
69 }
70
71 #define DEBUG_MODE_STATUS "Debug Mode Status"
72 #define DEBUG_MODE_VERSION \
73 { \
74 0xFF, 0xFF, 0xFF, 0xFFFF \
75 }
76
77 #define PERFORMANCE_MODE_STATUS "Performance Mode Status"
78 #define PERFORMANCE_MODE_VERSION \
79 { \
80 0xFF, 0xFF, 0xFF, 0xFFFF \
81 }
82
83 #define DEBUG_USE_USB_STATUS "Debug Use USB(Disabled:Serial)"
84 #define DEBUG_USE_USB_VERSION \
85 { \
86 0xFF, 0xFF, 0xFF, 0xFFFF \
87 }
88
89 #define ICC_OVERLOCKING_FVI_STRING "ICC Overclocking Version"
90 #define ICC_OVERLOCKING_VERSION \
91 { \
92 0xFF, 0xFF, 0xFF, 0xFFFF \
93 }
94
95 #define UNDI_FVI_STRING "UNDI Version"
96 #define UNDI_VERSION \
97 { \
98 0xFF, 0xFF, 0xFF, 0xFFFF \
99 }
100
101 #define EC_FVI_STRING "EC FW Version"
102 #define EC_VERSION \
103 { \
104 0xFF, 0xFF, 0xFF, 0xFFFF \
105 }
106
107 #define BASE_EC_FW_FVI_STRING "Base EC FW Version"
108 #define BASE_EC_FW_VERSION \
109 { \
110 0xFF, 0xFF, 0xFF, 0xFFFF \
111 }
112
113 #define EC_2_EC_PROTOCOL_FVI_STRING "EC-EC Protocol Version"
114 #define EC_2_EC_PROTOCOL_VERSION \
115 { \
116 0xFF, 0xFF, 0xFF, 0xFFFF \
117 }
118
119 #define GOP_FVI_STRING "GOP Version"
120 #define GOP_VERSION \
121 { \
122 0xFF, 0xFF, 0xFF, 0xFFFF \
123 }
124
125 #define ROYALPARK_FVI_STRING "Royal Park Version"
126 #define ROYALPARK_VERSION \
127 { \
128 0xFF, 0xFF, 0xFF, 0xFFFF \
129 }
130
131 #define PLATFORM_FVI_STRING "Platform Version"
132 #define PLATFORM_VERSION \
133 { \
134 0xFF, 0xFF, 0xFF, 0xFFFF \
135 }
136
137 #define CLIENT_SILICON_FVI_STRING "Client Silicon Version"
138 #define CLIENT_SILICON_VERSION \
139 { \
140 0xFF, 0xFF, 0xFF, 0xFFFF \
141 }
142
143 enum {
144 LAN_PHY_VER = 0,
145 SENSOR_FW_VER,
146 DEBUG_MODE_VER,
147 PERFORMANCE_MODE_VER,
148 DEBUB_USE_USB_VER,
149 ICC_OVERLOCKING_VER,
150 UNDI_VER,
151 EC_VER,
152 GOP_VER,
153 BASE_EC_FW_VER,
154 EC_2_EC_PROTOCOL_VER,
155 ROYALPARK_VER,
156 PLATFORM_VER,
157 CLIENT_SILICON_VER,
158 } PLATFORM_FVI_INDEX;
159
160 #define SENSOR_HUB_FW_VERSION_OFFSET 0x1000
161 #define SENSOR_HUB_FW_VERSION_LENGTH 0x04
162
163 //
164 // LAN PHY Revision definitions
165 //
166 #define LAN_PHY_REV_TC 0xA0
167 #define LAN_PHY_REV_A0 0xA1
168 #define LAN_PHY_REV_A1 0xA2
169 #define LAN_PHY_REV_A2 0xA3
170 #define LAN_PHY_REV_A3 0xA4
171 #define LAN_PHY_REV_B1 0xA5
172
173
174 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeMePolicyUpdateLib.h Source File

  • Library
DxeMePolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2011 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_ME_POLICY_UPDATE_LIB_H_
35 #define _DXE_ME_POLICY_UPDATE_LIB_H_
36
37 /**
38 Update the ME Policy Library
39
40 @param[in] DxeMePolicy The pointer to get ME Policy protocol instance
41
42 @retval EFI_SUCCESS Initialization complete.
43 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
44 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
45 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
46
47 **/
48 EFI_STATUS
49 UpdateDxeMePolicy (
50 IN OUT ME_POLICY_PROTOCOL *DxeMePolicy
51 );
52
53 #endif // _DXE_ME_POLICY_UPDATE_LIB_H_
UpdateDxeMePolicy
EFI_STATUS UpdateDxeMePolicy(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
Update the ME Policy Library.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeOpromPatchLib.h Source File

  • Library
DxeOpromPatchLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2010 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_OPROM_PATCH_LIB_H_
35 #define _DXE_OPROM_PATCH_LIB_H_
36
37 #include <Protocol/PciIo.h>
38
39 VOID
40 EFIAPI
41 OpromPatchPciIo (
42 IN EFI_PCI_IO_PROTOCOL *PciIo
43 );
44
45 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxePchPolicyUpdateLib.h Source File

  • Library
DxePchPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_PCH_POLICY_UPDATE_LIB_H_
35 #define _DXE_PCH_POLICY_UPDATE_LIB_H_
36
37 /**
38 Get data for platform policy from setup options.
39
40 @param[in] PchPolicy The pointer to get PCH Policy protocol instance
41
42 @retval EFI_SUCCESS Operation success.
43
44 **/
45 EFI_STATUS
46 EFIAPI
47 UpdateDxePchPolicy (
48 IN OUT PCH_POLICY_PROTOCOL *PchPolicy
49 );
50
51 #endif
UpdateDxePchPolicy
EFI_STATUS UpdateDxePchPolicy(IN OUT PCH_POLICY_PROTOCOL *PchPolicy)
Get data for platform policy from setup options.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxePlatformBootManagerLib.h Source File

  • Library
DxePlatformBootManagerLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for DxePlatformBootManagerLib
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference
33 **/
34
35 #ifndef _DXE_PLATFORM_BOOT_MANAGER_LIB_H_
36 #define _DXE_PLATFORM_BOOT_MANAGER_LIB_H_
37
38
39 /**
40 Tries to expand the given partitions device path to start with physical HDD
41 device path
42 @param[in] LoadOption pointer to an Efi Boot Manager boot option
43 @param[out] BootDevicePath indirect pointer to retrieved device path
44
45 @retval EFI_SUCCESS Function found
46 **/
47 EFI_STATUS
48 ExpandPartitionsDevPath (
49 IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption,
50 OUT EFI_DEVICE_PATH_PROTOCOL **BootDevicePath
51 );
52
53 /**
54 Checks whenever a given load option starts with a partition device path
55
56 @param[in] LoadOption Pointer to load option to test
57
58 @retval TRUE
59 @retval FALSE
60 **/
61 BOOLEAN
62 IsItPartitionsDevicePath(
63 IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption
64 );
65
66 /**
67 This function converts an input device structure to a Unicode string.
68
69 @param DevPath A pointer to the device path structure.
70
71 @return A new allocated Unicode string that represents the device path.
72 **/
73 CHAR16 *
74 DevicePathToStr (
75 IN EFI_DEVICE_PATH_PROTOCOL *DevPath
76 );
77
78 #endif
ExpandPartitionsDevPath
EFI_STATUS ExpandPartitionsDevPath(IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption, OUT EFI_DEVICE_PATH_PROTOCOL **BootDevicePath)
Tries to expand the given partitions device path to start with physical HDD device path...
DevicePathToStr
CHAR16 * DevicePathToStr(IN EFI_DEVICE_PATH_PROTOCOL *DevPath)
This function converts an input device structure to a Unicode string.
IsItPartitionsDevicePath
BOOLEAN IsItPartitionsDevicePath(IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption)
Checks whenever a given load option starts with a partition device path.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxePolicyBoardConfigLib.h Source File

  • Library
DxePolicyBoardConfigLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for the DxePolicyBoardConfig Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _DXE_POLICY_BOARD_CONFIG_LIB_H_
35 #define _DXE_POLICY_BOARD_CONFIG_LIB_H_
36
37 #include <Protocol/AmtPolicy.h>
38 #include <Protocol/MePolicy.h>
39 #include <Protocol/SaPolicy.h>
40
41 /**
42 This function performs DXE AMT Policy update by board configuration.
43
44 @param[in, out] DxeAmtPolicy DXE AMT Policy
45
46 @retval EFI_SUCCESS The SI Policy is successfully updated.
47 @retval Others The SI Policy is not successfully updated.
48 **/
49 EFI_STATUS
50 EFIAPI
51 UpdateDxeAmtPolicyBoardConfig (
52 IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy
53 );
54
55 /**
56 This function performs DXE ME Policy update by board configuration.
57
58 @param[in, out] DxeAmtPolicy DXE ME Policy
59
60 @retval EFI_SUCCESS The SI Policy is successfully updated.
61 @retval Others The SI Policy is not successfully updated.
62 **/
63 EFI_STATUS
64 EFIAPI
65 UpdateDxeMePolicyBoardConfig (
66 IN OUT ME_POLICY_PROTOCOL *DxeMePolicy
67 );
68
69 /**
70 This function performs DXE SA Policy update by board configuration.
71
72 @param[in, out] DxeAmtPolicy DXE SA Policy
73
74 @retval EFI_SUCCESS The SI Policy is successfully updated.
75 @retval Others The SI Policy is not successfully updated.
76 **/
77 EFI_STATUS
78 EFIAPI
79 UpdateDxeSaPolicyBoardConfig (
80 IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
81 );
82
83 #endif
UpdateDxeMePolicyBoardConfig
EFI_STATUS UpdateDxeMePolicyBoardConfig(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
This function performs DXE ME Policy update by board configuration.
UpdateDxeAmtPolicyBoardConfig
EFI_STATUS UpdateDxeAmtPolicyBoardConfig(IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function performs DXE AMT Policy update by board configuration.
UpdateDxeSaPolicyBoardConfig
EFI_STATUS UpdateDxeSaPolicyBoardConfig(IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy)
This function performs DXE SA Policy update by board configuration.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxePolicyUpdateProtocol.h Source File

  • Protocol
DxePolicyUpdateProtocol.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2010 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_POLICY_UPDATE_PROTOCOL_H_
35 #define _DXE_POLICY_UPDATE_PROTOCOL_H_
36
37 //
38 // DXE Policy Update Protocol GUID
39 // {D5E1268B-F62B-4b12-BB27-CBF07AE7B8B9}
40 //
41 #define DXE_POLICY_UPDATE_PROTOCOL_GUID \
42 { \
43 0xd5e1268b, 0xf62b, 0x4b12, 0xbb, 0x27, 0xcb, 0xf0, 0x7a, 0xe7, 0xb8, 0xb9 \
44 }
45
46 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeSaPolicyUpdateLib.h Source File

  • Library
DxeSaPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2012 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_SA_POLICY_UPDATE_LIB_H_
35 #define _DXE_SA_POLICY_UPDATE_LIB_H_
36
37 /**
38 Get data for platform policy from setup options.
39
40 @param[in] SaPolicy The pointer to get SA Policy protocol instance
41
42 @retval EFI_SUCCESS Operation success.
43
44 **/
45 EFI_STATUS
46 EFIAPI
47 UpdateDxeSaPolicy (
48 IN OUT SA_POLICY_PROTOCOL *SaPolicy
49 )
50 ;
51
52 #endif
UpdateDxeSaPolicy
EFI_STATUS UpdateDxeSaPolicy(IN OUT SA_POLICY_PROTOCOL *SaPolicy)
Get data for platform policy from setup options.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeSmmAcpiCustomLib.h Source File

  • Library
DxeSmmAcpiCustomLib.h
Go to the documentation of this file.
1 /** @file
2 This header file provides platform specific definitions used by other modules
3 for platform specific initialization.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2006 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36
37 #ifndef _DXE_SMM_ACPI_CUSTOM_LIB_H_
38 #define _DXE_SMM_ACPI_CUSTOM_LIB_H_
39 //
40 // Include files
41 //
42 #include <Base.h>
43 #include <Uefi.h>
44 #include <Library/EcLib.h>
45 #include <SaAccess.h>
46 #include <Protocol/PlatformNvsArea.h>
47 #include <Protocol/SmmThunk.h>
48
49 //
50 // Platform NVS area pointer
51 //
52 extern PLATFORM_NVS_AREA *mPlatformNvsAreaPtr;
53
54 //
55 // Function declarations
56 //
57 VOID
58 PlatformSpecificAcpiEnableHook (
59 VOID
60 );
61
62 VOID
63 PlatformSpecificAcpiDisableHook (
64 VOID
65 );
66
67 #endif
PlatformNvsArea.h
This file defines the Platform NVS Area Protocol.
EcLib.h
EC library functions and definitions.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeSmmInternalGraphicDeviceLib.h Source File

  • Library
DxeSmmInternalGraphicDeviceLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_SMM_INTEL_GRAPHICS_DEVICE_LIB_H_
35 #define _DXE_SMM_INTEL_GRAPHICS_DEVICE_LIB_H_
36
37 #include <Protocol/LegacyBios.h>
38
39 #define VBIOS_SUCCESS 0x05F
40 #define VBIOS_FAILED 0x15F
41 #define NOT_NEED_ATTACHED 0x01
42 #define DEVICE_DEFAULT_ALL_BYTE 0x0F
43 #define DEVICE_DEFAULT_ALL_WORD 0x0F0F
44 #define DEVICE_SECOND_ALL_BYTE 0xF0
45 #define DEVICE_SECOND_ALL_WORD 0xF0F0
46
47 //
48 // Meaning of Bit for Device Type
49 //
50 // Bit 15 = Pipe B - LFP2
51 // Bit 14 = Pipe B - EFP2
52 // Bit 13 = Pipe B - TV2
53 // Bit 12 = Pipe B - CRT2
54 // Bit 11 = Pipe B - LFP
55 // Bit 10 = Pipe B - EFP
56 // Bit 9 = Pipe B - TV
57 // Bit 8 = Pipe B - Reserved (830M), CRT (855MG, Alviso, Calistoga)
58 // Bit 7 = Pipe A - LFP2 (830M), Reserved (855MG, Alviso, Calistoga)
59 // Bit 6 = Pipe A - EFP2
60 // Bit 5 = Pipe A - TV2
61 // Bit 4 = Pipe A - CRT2
62 // Bit 3 = Pipe A - LFP (830M), Reserved (855MG, Alviso, Calistoga)
63 // Bit 2 = Pipe A - EFP
64 // Bit 1 = Pipe A - TV
65 // Bit 0 = Pipe A - CRT
66 //
67 #define DEVICE_PIPEA_CRT 0x0001
68 #define DEVICE_PIPEA_TV 0x0002
69 #define DEVICE_PIPEA_EFP 0x0004
70 #define DEVICE_PIPEA_LFP 0x0008
71 #define DEVICE_PIPEA_CRT2 0x0010
72 #define DEVICE_PIPEA_TV2 0x0020
73 #define DEVICE_PIPEA_EFP2 0x0040
74 #define DEVICE_PIPEA_LFP2 0x0080
75 #define DEVICE_PIPEB_CRT 0x0100
76 #define DEVICE_PIPEB_TV 0x0200
77 #define DEVICE_PIPEB_EFP 0x0400
78 #define DEVICE_PIPEB_LFP 0x0800
79 #define DEVICE_PIPEB_CRT2 0x1000
80 #define DEVICE_PIPEB_TV2 0x2000
81 #define DEVICE_PIPEB_EFP2 0x4000
82 #define DEVICE_PIPEB_LFP2 0x8000
83
84 //
85 // Pop-Up states and modes
86 //
87 #define POP_UP_WINDOW_OPENED 0x01
88 #define POP_UP_WINDOW_LOADED 0x10
89
90 //
91 // Mode1 : 100b, 64 x 64 2bpp 3-color + Transparency mode
92 // Mode2 : 101b, 64 x 64 2bpp AND / XOR mode
93 // Mode3 : 110b, 64 x 64 2bpp 4-color mode
94 //
95 #define POP_UP_WINDOW_MODE_1 4
96 #define POP_UP_WINDOW_MODE_2 5
97 #define POP_UP_WINDOW_MODE_3 6
98
99 //
100 // Panel Fitting states
101 //
102 #define PANEL_FITTING_CENTERING 0x1
103 #define PANEL_FITTING_STRETCHING 0x6
104 //
105 // Global variables used in this module
106 //
107 extern EFI_PHYSICAL_ADDRESS mPopupData;
108 extern EFI_PHYSICAL_ADDRESS mPopupColor;
109 extern UINTN mPopupDataSize;
110
111 EFI_STATUS
112 LoadPopUpToVbios (
113 VOID
114 );
115 /*++
116
117 Routine Description:
118
119 Locate the pop-up buffer and pass it to the video BIOS.
120 This must call the legacy BIOS protocol, which is only available to BS code.
121 It is not SMM safe.
122
123 Arguments:
124
125 None
126
127 Returns:
128
129 EFI_SUCCESS The function completed successfully
130 EFI_UNSUPPORTED Could not locate a pop up bitmap to load
131
132 --*/
133
134 EFI_STATUS
135 GetFvImage (
136 IN EFI_GUID *NameGuid,
137 IN OUT VOID **Buffer,
138 IN OUT UINTN *Size
139 );
140 /*++
141
142 Routine Description:
143
144 This routine will take a GUIDed file name and provide a buffer of the data.
145
146 Arguments:
147
148 NameGuid Pointer to a GUID of the file name.
149 Buffer Pointer to a buffer for the file contents.
150 Size Size of the buffer, in bytes
151
152 Returns:
153
154 EFI_SUCCESS The wanted image has been found and loaded.
155 EFI_NOT_FOUND The wanted image has not been found.
156
157 --*/
158
159 EFI_STATUS
160 InitializeInternalGraphicDeviceLib (
161 VOID
162 );
163
164 VOID
165 GraphicsInt (
166 IN EFI_IA32_REGISTER_SET *Registers
167 );
168
169 VOID
170 GetCadl (
171 IN OUT EFI_IA32_REGISTER_SET *Registers
172 );
173
174 EFI_STATUS
175 GetNextState (
176 IN OUT EFI_IA32_REGISTER_SET *Registers
177 );
178
179 BOOLEAN
180 IsPrimaryDisplayDevice (
181 IN UINT32 VidDid
182 );
183
184 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: DxeTbtPolicyUpdateLib.h Source File

  • Library
DxeTbtPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_TBT_POLICY_UPDATE_LIB_H_
35 #define _DXE_TBT_POLICY_UPDATE_LIB_H_
36
37 /**
38 Get data for platform policy from setup options.
39
40 @param[in] TbtPolicy The pointer to get TBT Policy protocol instance
41
42 @retval EFI_SUCCESS Operation success.
43
44 **/
45 EFI_STATUS
46 EFIAPI
47 UpdateDxeTbtPolicy (
48 IN OUT TBT_POLICY_PROTOCOL *TbtPolicy
49 )
50 ;
51
52 #endif
UpdateDxeTbtPolicy
EFI_STATUS UpdateDxeTbtPolicy(IN OUT TBT_POLICY_PROTOCOL *TbtPolicy)
Get data for platform policy from setup options.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EcAccess.h Source File

  • Protocol
EcAccess.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2009 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef __EFI_EC_ACCESS_H___
34 #define __EFI_EC_ACCESS_H___
35
36 //typedef struct gEfiEcAccessProtocolGuid _gEfiEcAccessProtocolGuid;
37 //
38 // EC Access specification constant and types
39 //
40
41
42 //
43 // EC Access specification Data Structures
44 //
45
46
47 typedef
48 EFI_STATUS
49 (EFIAPI *EC_QUERY_COMMAND) (
50 UINT8 *Qdata
51 );
52
53 typedef
54 EFI_STATUS
55 (EFIAPI *EC_WRITE_CMD) (
56 UINT8 cmd
57 );
58
59 typedef
60 EFI_STATUS
61 (EFIAPI *EC_WRITE_DATA) (
62 UINT8 data
63 );
64
65 typedef
66 EFI_STATUS
67 (EFIAPI *EC_READ_DATA) (
68 UINT8 *data
69 );
70
71 typedef
72 EFI_STATUS
73 (EFIAPI *EC_READ_MEM) (
74 UINT8 Index,
75 UINT8 *Data
76 );
77
78 typedef
79 EFI_STATUS
80 (EFIAPI *EC_WRITE_MEM) (
81 UINT8 Index,
82 UINT8 Data
83 );
84
85 typedef
86 EFI_STATUS
87 (EFIAPI *EC_ACPI_ENABLE) (
88 VOID
89 );
90
91
92 typedef
93 EFI_STATUS
94 (EFIAPI *EC_ACPI_DISABLE) (
95 VOID
96 );
97
98 typedef
99 EFI_STATUS
100 (EFIAPI *EC_SMI_NOTIFY_ENABLE) (
101 VOID
102 );
103
104 typedef
105 EFI_STATUS
106 (EFIAPI *EC_SMI_NOTIFY_DISABLE) (
107 VOID
108 );
109
110
111 typedef
112 EFI_STATUS (EFIAPI *EC_SHUTDOWN_SYSTEM)(
113 VOID
114 );
115
116 typedef
117 EFI_STATUS (EFIAPI *EC_GET_MOTHER_BOARD_ID)(
118 UINT8 *FabID
119 );
120
121 typedef
122 EFI_STATUS (EFIAPI *EC_GET_EC_VERSION)(
123 UINT8 *Revision
124 );
125
126 typedef
127 EFI_STATUS (EFIAPI *EC_ENABLE_LAN)(
128 VOID
129 );
130
131 typedef
132 EFI_STATUS (EFIAPI *EC_DISABLE_LAN)(
133 VOID
134 );
135
136 typedef
137 EFI_STATUS (EFIAPI *EC_DEEPSX_CONFIG)(
138 UINT8 ECData
139 );
140
141 typedef
142 EFI_STATUS (EFIAPI *EC_TURBOCTRL_TESTMODE)(
143 UINT8 Enable,
144 UINT8 ACBrickCap,
145 UINT8 ECPollPeriod,
146 UINT8 ECGuardBandValue,
147 UINT8 ECAlgorithmSel
148 );
149
150 typedef
151 EFI_STATUS (EFIAPI *EC_GET_SWITCH_STATUS)(
152 UINT8 *Data
153 );
154
155 typedef
156 EFI_STATUS (EFIAPI *EC_FAIL_SAFE_FAN_CTRL)(
157 UINT8 CpuTemp,
158 UINT8 CpuFanSpeed
159 );
160 typedef struct _EFI_EC_ACCESS_PROTOCOL {
161 EFI_HANDLE Handle;
162 EC_QUERY_COMMAND QuerryCmd;
163 EC_WRITE_CMD WriteCmd;
164 EC_WRITE_DATA WriteData;
165 EC_READ_DATA ReadData;
166 EC_READ_MEM ReadMem;
167 EC_WRITE_MEM WriteMem;
168 EC_ACPI_ENABLE AcpiEnable;
169 EC_ACPI_DISABLE AcpiDisable;
170 EC_SMI_NOTIFY_ENABLE SMINotifyEnable;
171 EC_SMI_NOTIFY_DISABLE SMINotifyDisable;
172 EC_SHUTDOWN_SYSTEM ShutDownSystem;
173 EC_GET_MOTHER_BOARD_ID GetMotherBoardID;
174 EC_GET_EC_VERSION GetECVersion;
175 EC_ENABLE_LAN EnableLan;
176 EC_DISABLE_LAN DisableLan;
177 EC_DEEPSX_CONFIG DeepSxConfig;
178 EC_TURBOCTRL_TESTMODE TurboCtrlMode;
179 EC_GET_SWITCH_STATUS GetSwitchStatus;
180 EC_FAIL_SAFE_FAN_CTRL FailSafeFanCtrl;
181 } EFI_EC_ACCESS_PROTOCOL;
182
183 #endif
184
185
186
187
188
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EcCommands.h Source File

  • Library
EcCommands.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef EC_COMMANDS_H_
36 #define EC_COMMANDS_H_
37
38 //
39 // Timeout if EC command/data fails
40 //
41 #define EC_TIME_OUT 0x20000
42
43 //
44 // The EC implements an embedded controller interface at ports 0x60/0x64 and a ACPI compliant
45 // system management controller at ports 0x62/0x66. Port 0x66 is the command and status port,
46 // port 0x62 is the data port.
47 //
48 #define EC_D_PORT 0x62
49 #define EC_C_PORT 0x66
50
51 //
52 // Status Port 0x62
53 //
54 #define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold
55 #define EC_S_SMI_EVT 0x40 // SMI event is pending
56 #define EC_S_SCI_EVT 0x20 // SCI event is pending
57 #define EC_S_BURST 0x10 // EC is in burst mode or normal mode
58 #define EC_S_CMD 0x08 // Byte in data register is command/data
59 #define EC_S_IGN 0x04 // Ignored
60 #define EC_S_IBF 0x02 // Input buffer is full/empty
61 #define EC_S_OBF 0x01 // Output buffer is full/empty
62
63 //
64 // EC commands that are issued to the EC through the command port (0x66).
65 // New commands and command parameters should only be written by the host when IBF=0.
66 // Data read from the EC data port is valid only when OBF=1.
67 //
68 #define EC_C_SMI_NOTIFY_ENABLE 0x04 // Enable SMI notifications to the host
69 #define EC_C_SMI_NOTIFY_DISABLE 0x05 // SMI notifications are disabled and pending notifications cleared
70 #define EC_C_QUERY_SYS_STATUS 0x06 // Returns 1 byte of information about the system status
71 #define EC_C_QUERY_BOARD_ID_BIT 0x0A // Board Id 8 or 16 bit
72 #define EC_C_SMC_GET_MODE 0x09 // Command to detect EC
73 #define EC_C_RESET 0x0B // EC reset
74 #define EC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits
75 #define EC_C_SET_CHARGING_METHOD 0x13 // Command to specify charging method. (Normal charging or Fast charging (DFCT))
76 #define EC_C_GET_PMIC_VENDOR_ID 0x1B // Command to detect the Vendor ID of the PMIC
77 #define EC_C_SLP_S0_VOLTAGE 0x1C // Command to set/reset the bits of register V085ACNT[7:6]
78 #define EC_C_SYSTEM_POWER_OFF 0x22 // Turn off the system power
79 #define EC_C_ENABLE_POWER_BTN 0x23 // Disable power button functionality
80 #define EC_C_DISABLE_POWER_BTN 0x24 // Enable power button functionality
81 #define EC_C_LOW_POWER_ENTRY 0x2C // Enter Low Power Mode
82 #define EC_C_LOW_POWER_EXIT 0x2D // Exit Low Power Mode
83 #define EC_C_UPDATE_EC 0x2E // Update Device Power
84 #define EC_C_PMIC_VOLTAGE 0x2F // Command to set the VCC and VDDQ Voltage Levels
85 #define EC_C_LAN_ON 0x46 // Turn on the power to LAN through EC
86 #define EC_C_LAN_OFF 0x47 // Turn off the power to LAN through EC
87 #define EC_C_DIS_PCH_DTS_READ 0x4E // Disable PCH DTS reading
88 #define EC_C_SET_CTEMP 0x58 // The next byte written to the data port will be the shutdown temperature
89 #define EC_C_EN_DTEMP 0x5E // Commands EC to begin reading Thermal Diode and comparing to Critical Temperature
90 #define EC_C_DIS_DTEMP 0x5F // Commands EC to stop reading Thermal Diode
91 #define EC_C_PCH_SMBUS_EN 0x60 // EC PCH SMBus thermal monitoring Enable cmd
92 #define EC_C_PCH_SMBUS_DIS 0x61 // EC PCH SMBus thermal monitoring Disable cmd
93 #define EC_C_PCH_SMBUS_WRITE_EN 0x68 // EC PCH SMBus Write Enable cmd
94 #define EC_C_PCH_SMBUS_WRITE_DIS 0x69 // EC PCH SMBus Write Disable cmd
95 #define EC_C_TS_ON_DIMM_EN 0x6B // TS-on-DIMM thermal monitoring enable command
96 #define EC_C_TS_ON_DIMM_DIS 0x6C // TS-on-DIMM thermal monitoring disable command
97 #define EC_C_PCH_SMBUS_MSG_LENGTH 0x6D // PCH SMBus block read buffer length
98 #define EC_C_PCH_SMBUS_PEC_EN 0x6E // PCH SMBus Packet Error Checking (PEC) Enable command.
99 #define EC_C_PCH_SMBUS_PEC_DIS 0x76 // PCH SMBus Packet Error Checking (PEC) Disable command.
100 #define EC_C_SMBUS_HIGH_SPEED 0x75 // EC SMBus high speed mode command
101 #define EC_C_SMI_QUERY 0x70 // The host reads the data port to retrieve the notifications
102 #define EC_C_SMI_TIMER 0x71 // Commands the EC to generate a periodic SMI to the host
103 #define EC_C_SMI_HOTKEY 0x72 // Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
104 #define EC_C_READ_MEM 0x80 // Read the EC memory
105 #define EC_C_WRITE_MEM 0x81 // Write the EC memory
106 #define EC_C_DOCK_STATUS 0x8A // Get the dock status
107 #define EC_C_EC_REVISION 0x90 // Get the revision for the EC
108 #define EC_C_BASE_EC_FW_VERSION 0x94 // Get base EC FW version
109 #define EC_C_EC_2_EC_PROTOCOL_VERSION 0x95 // Get EC-EC protocol version
110 #define EC_C_UPDATE_PWM 0x1A // Update the FAN Speed
111 #define EC_C_ACPI_ENABLE 0xAA // Enable ACPI mode
112 #define EC_C_ACPI_DISABLE 0xAB // Disable ACPI mode
113 #define EC_C_SMI_INJECT 0xBA // The next byte written to the data port will generate an immediate SMI
114 #define EC_C_SMI_DISABLE 0xBC // SMI generation by the EC is disabled
115 #define EC_C_SMI_ENABLE 0xBD // SMI generation by the EC is enabled
116 #define EC_C_USBC_SX_ENTRY_WAIT 0xE2 // Send this command from SMM and wait for response
117 #define EC_C_USBC_SX_EXIT_WAIT 0xE3 // Send this command during boot and wait for response
118 #ifdef CPU_ICL
119 #define EC_C_USBC_IOM_READY_NOTIFY 0xE4 // Send this command during boot/resume when IOM is ready
120 #define EC_C_USBC_GET_USB_CONN_STATUS 0xE5 // Send this command during boot before USB enumeration and wait for response
121 #endif
122 #define EC_C_USBC_PD_STATUS 0xFF // Get PD status from EC RAM
123
124 //
125 // @todo Those definitions need to be reviewed and cleaned up.
126 //
127 #define EC_B_BOARD_ID 0x0F // Board ID = [3:0]
128 #define EC_B_BOARD_ID_BIT_16 0x80 // Bit7 = 1 means 16 bit implementation
129 #define EC_B_SYS_STATUS_AC 0x10 // AC power status (Bit 4 = 1, AC powered)
130 #define EC_B_SYS_STATUS_THERMAL 0x0F // CPU thermal state (0 ~ 9)
131 #define EC_B_SYS_STATUS_FAN 0x40 // Fan status (Bit 6 = 1, Fan on)
132 #define EC_B_LID_STATUS_OPEN 0x40 // Lid status (Bit 6 = 1, Lid open)
133 #define EC_B_SYS_STATUS_DOCK 0x20 // Dock status (Bit 5 = 1, Docked)
134 #define EC_B_DOCK_STATUS_ATTACH 0x01 // Dock status (Bit 0 = 1, Attach)
135
136 #define EC_D_LID_STATE 0x03 // Get Lid State (EC RAM offset 0x03 bit6)
137 #define EC_D_FORCE_RESET 0x78 // Enable/Disable ForceResetAfterAcRemoval (EC RAM offset 0x78 bit2)
138 #define EC_D_TEN_SEC_MODE 0x78 // Enable/Disable 10sec Power button Override (EC RAM offset 0x78 bit1)
139 #define EC_D_SATA2_POWER 0xC8 // Enable/Disable SATA port2 power (EC RAM offset 0xC8 bit0)
140 #define EC_D_NORMAL_CHARGING 0x01 // Select normal charging method
141 #define EC_D_FAST_CHARGING 0x02 // Select fast charging (DFCT) method
142
143 //
144 // EC commands that are only valid if the EC has ACPI mode enabled.
145 // Note that capacity and voltage are 16 bit values, thus you need to read them from
146 // ACPI space with two reads (little Endian).
147 //
148 #define EC_VIRTUAL_BAT_STATUS 48 // Status of the virtual battery (present)
149 #define EC_VIRTUAL_BAT_PRESENT_MASK 0x10 // Bit 4 is the indicator
150
151 #define EC_REAL_BAT1_STATUS 50 // Status of the first real battery (present, charging)
152 #define EC_REAL_BAT1_REMAINING_PERCENT 52 // Remaining capacity in percentage
153 #define EC_REAL_BAT1_REMAINING_CAPACITY 89 // Remaining capacity in mWh
154 #define EC_REAL_BAT1_RESOLUTION_VOLTAGE 93 // Full resolution voltage in mV
155
156 #define EC_REAL_BAT2_STATUS 54 // Status of the second real battery (present, charging)
157 #define EC_REAL_BAT2_REMAINING_PERCENT 56 // Remaining capacity in percentage
158 #define EC_REAL_BAT2_REMAINING_CAPACITY 99 // Remaining capacity in mWh
159 #define EC_REAL_BAT2_RESOLUTION_VOLTAGE 103 // Full resolution voltage in mV
160
161 #define EC_REAL_BAT_PRESENT_MASK 0x8 // Bit 3 is the indicator
162 #define EC_REAL_BAT_CHARGING_MASK 0x1 // Bit 1 is the indicator
163
164 //
165 // SMI notification code table, read through command EC_C_SMI_QUERY
166 //
167 #define EC_N_SMI_NULL 0x00 // Null marks the end of the SMI notification queue
168 #define EC_N_SMI_HOTKEY 0x20 // Hotkey pressed SMI
169 #define EC_N_SMI_ACINSERTION 0x30 // AC insertion SMI
170 #define EC_N_SMI_ACREMOVAL 0x31 // AC removal SMI
171 #define EC_N_SMI_PWRSW 0x32 // Power switch press SMI
172 #define EC_N_SMI_LID 0x33 // Lid switch change SMI
173 #define EC_N_SMI_VB 0x34 // Virtual battery switch change SMI
174 #define EC_N_SMI_THERM_0 0x60 // Thermal state 0 SMI
175 #define EC_N_SMI_THERM_1 0x61 // Thermal state 1 SMI
176 #define EC_N_SMI_THERM_2 0x62 // Thermal state 2 SMI
177 #define EC_N_SMI_THERM_3 0x63 // Thermal state 3 SMI
178 #define EC_N_SMI_THERM_4 0x64 // Thermal state 4 SMI
179 #define EC_N_SMI_THERM_5 0x65 // Thermal state 5 SMI
180 #define EC_N_SMI_THERM_6 0x66 // Thermal state 6 SMI
181 #define EC_N_SMI_THERM_7 0x67 // Thermal state 7 SMI
182 #define EC_N_SMI_THERM_8 0x68 // Thermal state 8 SMI
183 #define EC_N_SMI_DOCKED 0x70 // Dock complete SMI
184 #define EC_N_SMI_UNDOCKED 0x71 // Undock complete SMI
185 #define EC_N_SMI_UNDOCKREQUEST 0x72 // Undocking request SMI
186 #define EC_N_SMI_TIMER 0x80 // Timer wakeup SMI
187
188 //
189 // Hotkey scan code (CTRL + ALT + SHIFT + key)
190 //
191 #define EC_HK_ESC 0x01 // ESC
192 #define EC_HK_1 0x02 // 1 !
193 #define EC_HK_2 0x03 // 2 @
194 #define EC_HK_3 0x04 // 3 #
195 #define EC_HK_4 0x05 // 4 $
196 #define EC_HK_5 0x06 // 5 %
197 #define EC_HK_6 0x07 // 6 ^
198 #define EC_HK_7 0x08 // 7 &
199 #define EC_HK_8 0x09 // 8 *
200 #define EC_HK_9 0x0A // 9 (
201 #define EC_HK_0 0x0B // 0 )
202 #define EC_HK_MINUS 0x0C // - _
203 #define EC_HK_ADD 0x0D // = +
204 #define EC_HK_F1 0x3B // F1
205 #define EC_HK_F2 0x3C // F2
206 #define EC_HK_F3 0x3D // F3
207 #define EC_HK_F4 0x3E // F4
208 #define EC_HK_F5 0x3F // F5
209 #define EC_HK_F6 0x40 // F6
210 #define EC_HK_F7 0x41 // F7
211 #define EC_HK_F8 0x42 // F8
212 #define EC_HK_F9 0x43 // F9
213 #define EC_HK_F10 0x44 // F10
214 #define EC_HK_F11 0x57 // F11
215 #define EC_HK_F12 0x58 // F12
216
217 //
218 // BoardId format definition (Data came from EC_C_FAB_ID command)
219 //
220 typedef union {
221 UINT8 BoardId :5;
222 UINT8 BomId :3;
223 UINT8 Raw;
224 struct {
225 UINT8 FabId :2; // [9:8] - REV_FAB_IDx
226 UINT8 MafSafDetect :1; // [10] - MAF_SAF_N_DETECT
227 UINT8 SpdPresent :1; // [11] - SPD_PRSNT
228 UINT8 VirtualBattery :1; // [12] - VIRTUAL_BATTERY
229 UINT8 VirtualDock :1; // [13] - VIRTUAL_DOCK_DET_N
230 UINT8 RetimerBypass :1; // [14] - RETIMER_BYPASS_STRAP
231 UINT8 EspiTestCard :1; // [15] - ESPI_TESTCARD_DET
232 } RvpFields;
233 struct {
234 UINT8 FabId :3; // [10:8] - REV_FAB_IDx
235 UINT8 Reserved1 :1; // [11]
236 UINT8 VirtualBattery :1; // [12] - VIRTUAL_BATTERY
237 UINT8 Reserved2 :1; // [13]
238 UINT8 RetimerBypass :1; // [14] - RETIMER_BYPASS_STRAP
239 UINT8 Reserved3 :1; // [15]
240 } SdsFields;
241 } BOARD_ID_INFO;
242
243 #endif // EC_COMMANDS_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EcHwLib.h Source File

  • Library
EcHwLib.h
Go to the documentation of this file.
1 /** @file
2 EC hardware library functions and definitions.
3
4 This library provides basic Embedded Controller Hardware interface.
5 It is keeped simple enough and used by other BaseEc libraries to abstacrt the usage
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 2014 - 2016 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains 'Framework Code' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may not be
33 modified, except as allowed by additional terms of your license agreement.
34
35 @par Specification Reference:
36 **/
37
38
39 #ifndef _BASE_EC_HW_LIB_H_
40 #define _BASE_EC_HW_LIB_H_
41
42 #include <Base.h>
43 #include <Uefi.h>
44 #include <Library/EcCommands.h>
45
46 typedef enum {
47 LpcInterface = 0,
48 SpiInterface,
49 EspiInterface,
50 I2cInterface,
51 EcInterfaceMax
52 } EC_INTERFACE_TYPE;
53
54 typedef enum {
55 EcId0 = 0,
56 EcIdMax
57 } EC_ID;
58
59 #endif
EcCommands.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EcLib.h Source File

  • Library
EcLib.h
Go to the documentation of this file.
1 /** @file
2 EC library functions and definitions.
3
4 This library provides basic EC interface.
5
6 There may be different libraries for different environments (PEI, BS, RT, SMM).
7 Make sure you meet the requirements for the library (protocol dependencies, use
8 restrictions, etc).
9
10 @copyright
11 INTEL CONFIDENTIAL
12 Copyright 1999 - 2017 Intel Corporation.
13
14 The source code contained or described herein and all documents related to the
15 source code ("Material") are owned by Intel Corporation or its suppliers or
16 licensors. Title to the Material remains with Intel Corporation or its suppliers
17 and licensors. The Material may contain trade secrets and proprietary and
18 confidential information of Intel Corporation and its suppliers and licensors,
19 and is protected by worldwide copyright and trade secret laws and treaty
20 provisions. No part of the Material may be used, copied, reproduced, modified,
21 published, uploaded, posted, transmitted, distributed, or disclosed in any way
22 without Intel's prior express written permission.
23
24 No license under any patent, copyright, trade secret or other intellectual
25 property right is granted to or conferred upon you by disclosure or delivery
26 of the Materials, either expressly, by implication, inducement, estoppel or
27 otherwise. Any license under such intellectual property rights must be
28 express and approved by Intel in writing.
29
30 Unless otherwise agreed by Intel in writing, you may not remove or alter
31 this notice or any other notice embedded in Materials by Intel or
32 Intel's suppliers or licensors in any way.
33
34 This file contains 'Framework Code' and is licensed as such under the terms
35 of your license agreement with Intel or your vendor. This file may not be
36 modified, except as allowed by additional terms of your license agreement.
37
38 @par Specification Reference:
39 **/
40
41
42 #ifndef _BASE_EC_LIB_H_
43 #define _BASE_EC_LIB_H_
44
45 //
46 // Include files
47 //
48 #include <Base.h>
49 #include <Uefi.h>
50 #include "EcCommands.h"
51 #include <Library/EcHwLib.h>
52
53 //
54 // Function declarations
55 //
56 /**
57 Detect EC
58
59 @param[out] EcMajorRevision
60 @param[out] EcMinorRevision
61
62 @retval TRUE EC is present on the system.
63 @retval FALSE EC is NOT present on the system.
64 **/
65
66 BOOLEAN
67 DetectEc (
68 OUT UINT8 *EcMajorRevision,
69 OUT UINT8 *EcMinorRevision
70 );
71
72 /**
73
74 Initiate EC reset sequence. EC is in Normal Mode.
75
76 @retval EFI_SUCCESS Command success
77 @retval EFI_DEVICE_ERROR Command error
78 **/
79
80 EFI_STATUS
81 LpcEcResetEcInNormalMode (
82 VOID
83 );
84
85 /**
86 Send a command to the Keyboard System Controller.
87
88 @param[in] Command Command byte to send
89
90 @retval EFI_SUCCESS Command success
91 @retval EFI_TIMEOUT Command timeout
92 @retval Other Command failed
93 **/
94 EFI_STATUS
95 SendEcCommand (
96 IN UINT8 Command
97 );
98
99
100 /**
101 Sends data to Keyboard System Controller.
102
103 @param[in] Data Data byte to send
104
105 @retval EFI_SUCCESS Success
106 @retval EFI_TIMEOUT Timeout
107 @retval Other Failed
108 **/
109 EFI_STATUS
110 SendEcData (
111 IN UINT8 Data
112 );
113
114
115 /**
116 Receives data from Keyboard System Controller.
117
118 @param[out] Data Data byte received
119
120 @retval EFI_SUCCESS Read success
121 @retval EFI_TIMEOUT Read timeout
122 @retval Other Read failed
123 **/
124 EFI_STATUS
125 ReceiveEcData (
126 OUT UINT8 *Data
127 );
128
129
130 /**
131 Receives status from Keyboard System Controller.
132
133 @param[out] Status Status byte to receive
134
135 @retval EFI_SUCCESS Success
136 @retval Other Failed
137 **/
138 EFI_STATUS
139 ReceiveEcStatus (
140 OUT UINT8 *EcStatus
141 );
142
143 /**
144 Sends data to the Embedded Controler.
145 Four use-cases:
146 1.Send command to EC (DataSize and DataBuffer can be NULL)
147 2.Send command to EC and send data to EC
148 3.Send command to EC and receive data from EC
149 4.Send command to EC, send data to EC and receive data from EC
150
151 @param[in] EcId Embedded Controller identification - in case there is more then one.
152 @param[in] Interface Interface used to access the EC HW
153 @param[in] Command Command value to send to the EC
154 @param[in][out] DataSize Size of data to send to the EC.
155 If the command retuned data - size of buffer returned by the EC.
156 Be aware of the DataSize must euqal to size of DataBuffer and cannot smaller
157 than number of send data or number of receive data, whichever is the grater.
158 @param[in][out] DataBuffer Pointer to the data buffer including data to be sent to the EC.
159 If the command returned data - pointer to the buffer including the data.
160 The buffer size should be the max of receive and transmit data.
161
162 @retval EFI_SUCCESS Success
163 @retval Other Failed - EFI_TIMEOUT, EFI_INVALID_PARAMETER, EFI_UNSUPPORTED,
164 EFI_BUFFER_TOO_SMALL, etc.
165 **/
166 EFI_STATUS
167 EcInterface (
168 IN EC_ID EcId,
169 IN UINT8 Command,
170 IN OUT UINT8 *DataSize,
171 IN OUT UINT8 *DataBuffer
172 );
173
174 #endif
ReceiveEcData
EFI_STATUS ReceiveEcData(OUT UINT8 *Data)
Receives data from Keyboard System Controller.
EcHwLib.h
EC hardware library functions and definitions.
ReceiveEcStatus
EFI_STATUS ReceiveEcStatus(OUT UINT8 *EcStatus)
Receives status from Keyboard System Controller.
DetectEc
BOOLEAN DetectEc(OUT UINT8 *EcMajorRevision, OUT UINT8 *EcMinorRevision)
Detect EC.
EcInterface
EFI_STATUS EcInterface(IN EC_ID EcId, IN UINT8 Command, IN OUT UINT8 *DataSize, IN OUT UINT8 *DataBuffer)
Sends data to the Embedded Controler.
LpcEcResetEcInNormalMode
EFI_STATUS LpcEcResetEcInNormalMode(VOID)
Initiate EC reset sequence.
SendEcCommand
EFI_STATUS SendEcCommand(IN UINT8 Command)
Send a command to the Keyboard System Controller.
EcCommands.h
SendEcData
EFI_STATUS SendEcData(IN UINT8 Data)
Sends data to Keyboard System Controller.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EcMiscLib.h Source File

  • Library
EcMiscLib.h
Go to the documentation of this file.
1 /** @file
2 EC miscellaneous library functions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _BASE_EC_MISC_LIB_H_
36 #define _BASE_EC_MISC_LIB_H_
37
38 //
39 // Include files
40 //
41 #include <Base.h>
42 #include <Uefi.h>
43 #include "EcCommands.h"
44 #include <Library/EcLib.h>
45
46 ///
47 /// @todo: it should move to BaseEcAcpiLib once BaseEcAcpiLib has been created.
48 ///
49 #ifndef CPU_ICL
50 /**
51 USBC Sx Entry Wait
52
53 @param[in][out] DataBuffer
54
55 @retval EFI_SUCCESS Command success
56 @retval EFI_DEVICE_ERROR Command error
57 **/
58 EFI_STATUS
59 UsbcSxEntry (
60 IN OUT UINT8 *DataBuffer
61 );
62
63
64 /**
65 USBC Sx Exit Wait
66
67 @param[out] DataBuffer
68
69 @retval EFI_SUCCESS Command success
70 @retval EFI_DEVICE_ERROR Command error
71 **/
72 EFI_STATUS
73 UsbcSxExit (
74 OUT UINT8 *DataBuffer
75 );
76 #endif // CPU_ICL
77
78 /**
79 Send enable ACPI mode command to EC
80
81 @param[in] Enable TURE - Enable EC ACPI mode
82 FALSE - Disable EC ACPI mode
83 @retval EFI_SUCCESS Command success
84 @retval EFI_DEVICE_ERROR Command error
85 **/
86 EFI_STATUS
87 EnableEcAcpiMode (
88 IN BOOLEAN Enable
89 );
90
91
92 /**
93 Send disable SMI mode command to EC
94
95 @param EFI_SUCCESS Command success
96 @param EFI_DEVICE_ERROR Command error
97 **/
98 EFI_STATUS
99 DisableEcSmiMode (
100 VOID
101 );
102
103
104 /**
105 Set EC critical shutdown temperature
106
107 @param[in] DataBuffer Shutdown temperature
108 @retval EFI_SUCCESS Command success
109 @retval EFI_DEVICE_ERROR Command error
110 **/
111 EFI_STATUS
112 SetEcCriticalShutdownTemperature (
113 IN UINT8 DataBuffer
114 );
115
116
117 /**
118 Get power state from EC. If power state cannot be determined,
119 battery powered is assumed.
120
121 @param TRUE AC powered
122 @param FALSE Battery powered
123 **/
124 BOOLEAN
125 PowerStateIsAc (
126 VOID
127 );
128
129
130 /**
131 Do EC reset
132
133 @retval EFI_SUCCESS Command success
134 @retval EFI_DEVICE_ERROR Command error
135 **/
136 EFI_STATUS
137 EcReset (
138 VOID
139 );
140
141
142 /**
143 Initiate EC reset sequence. EC is in Normal Mode.
144
145 @retval EFI_SUCCESS Command success
146 @retval EFI_DEVICE_ERROR Command error
147 **/
148 EFI_STATUS
149 EcResetEcInNormalMode (
150 VOID
151 );
152
153 /**
154 Enable LAN power
155
156 @param[in] Enable TURE - Enable LAN power
157 FALSE - Disable LAN power
158
159 @retval EFI_SUCCESS Command success
160 @retval EFI_DEVICE_ERROR Command error
161 **/
162 EFI_STATUS
163 EnableLanPower (
164 IN BOOLEAN Enable
165 );
166
167
168 /**
169 Query SMI event
170
171 @param[out] DataBuffer SMI event
172
173 @retval EFI_SUCCESS Command success
174 @retval EFI_DEVICE_ERROR Command error
175 **/
176 EFI_STATUS
177 QuerySmiEvent (
178 OUT UINT8 *DataBuffer
179 );
180
181
182 /**
183 Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
184
185 @param[out] DataBuffer Scan code of hotkey
186
187 @retval EFI_SUCCESS Command success
188 @retval EFI_DEVICE_ERROR Command error
189 **/
190 EFI_STATUS
191 GetHotkeyScanCode (
192 OUT UINT8 *DataBuffer
193 );
194
195
196 /**
197 Get the number of battery
198
199 @param[out] DataBuffer The number of battery
200
201 @retval EFI_SUCCESS Command success
202 @retval EFI_DEVICE_ERROR Command error
203 **/
204 EFI_STATUS
205 GetBatteryNumber (
206 OUT UINT8 *DataBuffer
207 );
208
209
210 /**
211 Get PCIe dock status
212
213 @param[out] DataBuffer PCIe dock status
214
215 @retval EFI_SUCCESS Command success
216 @retval EFI_DEVICE_ERROR Command error
217 **/
218 EFI_STATUS
219 GetPcieDockStatus (
220 OUT UINT8 *DataBuffer
221 );
222
223
224 /**
225 Clear ten second power button mode
226
227 **/
228 VOID
229 ClearTenSecPwrButtonMode (
230 VOID
231 );
232
233
234 /**
235 Enable SATA port2 power
236
237 **/
238 VOID
239 EnableSataPort2Power (
240 VOID
241 );
242
243 /**
244 Set SLP_S0 Voltage
245
246 @param[in] EcDataV085ACNT
247 @retval EFI_SUCCESS Command success
248 @retval EFI_DEVICE_ERROR Command error
249 **/
250 EFI_STATUS
251 SetSlpS0Voltage (
252 IN UINT8 EcDataV085ACNT
253 );
254
255 /**
256 Detect Pmic Vendor ID
257 @param[out] DataBuffer
258
259 @retval EFI_SUCCESS Command success
260 @retval EFI_DEVICE_ERROR Command error
261 **/
262 EFI_STATUS
263 DetectPmicVendorID (
264 OUT UINT8 *DataBuffer
265 );
266
267 /**
268 Set Pmic Voltage
269
270 @param[in] EcDataVcc
271 @param[in] EcDataVddq
272
273 @retval EFI_SUCCESS Command success
274 @retval EFI_DEVICE_ERROR Command error
275 **/
276 EFI_STATUS
277 SetPmicVoltage (
278 IN UINT8 EcDataVcc,
279 IN UINT8 EcDataVddq
280 );
281
282
283 /**
284 Read data from EC RAM
285
286 @param[in][out] DataBuffer
287
288 @retval EFI_SUCCESS Command success
289 @retval EFI_DEVICE_ERROR Command error
290 **/
291 EFI_STATUS
292 ReadEcRam (
293 IN OUT UINT8 *DataBuffer
294 );
295
296
297 /**
298 Write data to EC RAM
299
300 @param[in][out] DataBuffer
301
302 @retval EFI_SUCCESS Command success
303 @retval EFI_DEVICE_ERROR Command error
304 **/
305 EFI_STATUS
306 WriteEcRam (
307 IN OUT UINT8 *DataBuffer
308 );
309
310
311 /**
312 Update Device Power
313
314 @retval EFI_SUCCESS Command success
315 @retval EFI_DEVICE_ERROR Command error
316 **/
317 EFI_STATUS
318 UpdateDevicePower (
319 VOID
320 );
321
322
323 /**
324 Query system status
325
326 @param[out] DataBuffer
327
328 @retval EFI_SUCCESS Command success
329 @retval EFI_DEVICE_ERROR Command error
330 **/
331 EFI_STATUS
332 QuerySysStatus (
333 OUT UINT8 *DataBuffer
334 );
335
336
337 /**
338 Get board fab ID
339
340 @param[out] BoardFabId
341
342 @retval EFI_SUCCESS Command success
343 @retval EFI_DEVICE_ERROR Command error
344 **/
345 EFI_STATUS
346 GetBoardInfo (
347 OUT UINT16 *BoardFabId
348 );
349
350
351 /**
352 Send Exit Low Power Mode command to EC
353
354 @retval EFI_SUCCESS Command success
355 @retval EFI_DEVICE_ERROR Command error
356 **/
357 EFI_STATUS
358 ExitLowPowerMode (
359 VOID
360 );
361
362
363 /**
364 System power off
365
366 @retval EFI_SUCCESS Command success
367 @retval EFI_DEVICE_ERROR Command error
368 **/
369 EFI_STATUS
370 SystemPowerOff (
371 VOID
372 );
373
374
375 /**
376 Detect EC revision
377
378 @param[out] DataBuffer
379
380 @retval EFI_SUCCESS Command success
381 @retval EFI_DEVICE_ERROR Command error
382 **/
383 EFI_STATUS
384 DetectEcRevision (
385 OUT UINT8 *DataBuffer
386 );
387
388
389 /**
390 Get Base EC FW version
391
392 @param[out] DataBuffer Byte 1: Base EC FW major version
393 Byte 2: Base EC FW minor version
394
395 @retval EFI_SUCCESS Command success
396 @retval EFI_DEVICE_ERROR Command error
397 **/
398 EFI_STATUS
399 GetBaseEcFwVersion (
400 OUT UINT8 *DataBuffer
401 );
402
403
404 /**
405 Get EC-EC Protocol version
406
407 @param[out] DataBuffer Byte 1: Lid EC protocol version
408 Byte 2: Base EC protocol version
409
410 @retval EFI_SUCCESS Command success
411 @retval EFI_DEVICE_ERROR Command error
412 **/
413 EFI_STATUS
414 GetEc2EcProtocolVersion (
415 OUT UINT8 *DataBuffer
416 );
417
418 /**
419 Disable PCH DTS reading on SMLink 1
420
421 @param[in] Disable 0: Enable PCH DTS reading
422 1: Disable PCH DTS reading
423
424 @retval EFI_SUCCESS Command success
425 @retval EFI_DEVICE_ERROR Command error
426 **/
427 EFI_STATUS
428 DisablePchDtsReading (
429 IN UINT8 Disable
430 );
431
432 /**
433 Wake up EC
434
435 @retval TRUE EC wake up successfully.
436 @retval FALSE Fail to wake up EC.
437 **/
438 EFI_STATUS
439 WakeUpEc (
440 VOID
441 );
442
443 /**
444 Send Update PWM command to EC
445
446 @param EFI_SUCCESS Command success
447 @param EFI_DEVICE_ERROR Command error
448 **/
449 EFI_STATUS
450 UpdatePwm (
451 VOID
452 );
453
454 /**
455 Updates the PWM to the given value and returns the Fan speed.
456 @param Pwmvalue Pwm ending value
457 @param Speed Updates the Speed
458
459 @retval EFI_SUCCESS when successfully able to get the nominal data.
460 @retval ERROR Error if anything went wrong.
461
462 **/
463 EFI_STATUS
464 GetFanSpeed(
465 IN UINT8 Pwmvalue,
466 OUT UINT16 *Speed
467 );
468
469
470 /**
471 Select charging method
472
473 @param[in] Enable TURE - Fast charging (DFCT)
474 FALSE - Normal charging
475
476 @retval EFI_SUCCESS Command success
477 @retval EFI_DEVICE_ERROR Command error
478 **/
479 EFI_STATUS
480 DfctFastChargingMode (
481 IN BOOLEAN Enable
482 );
483
484 /**
485 EcForceResetAfterAcRemoval
486
487 @param[in] ForceResetAfterAcRemovalVar 0 : Clear AC Removal reset bit in EC
488 1 : Set AC Removal reset bit in EC
489 **/
490 VOID
491 EcForceResetAfterAcRemoval (
492 IN UINT8 ForceResetAfterAcRemovalVar
493 );
494
495 #endif
DisableEcSmiMode
EFI_STATUS DisableEcSmiMode(VOID)
Send disable SMI mode command to EC.
QuerySysStatus
EFI_STATUS QuerySysStatus(OUT UINT8 *DataBuffer)
Query system status.
WakeUpEc
EFI_STATUS WakeUpEc(VOID)
Wake up EC.
DisablePchDtsReading
EFI_STATUS DisablePchDtsReading(IN UINT8 Disable)
Disable PCH DTS reading on SMLink 1.
GetEc2EcProtocolVersion
EFI_STATUS GetEc2EcProtocolVersion(OUT UINT8 *DataBuffer)
Get EC-EC Protocol version.
GetPcieDockStatus
EFI_STATUS GetPcieDockStatus(OUT UINT8 *DataBuffer)
Get PCIe dock status.
WriteEcRam
EFI_STATUS WriteEcRam(IN OUT UINT8 *DataBuffer)
Write data to EC RAM.
DetectPmicVendorID
EFI_STATUS DetectPmicVendorID(OUT UINT8 *DataBuffer)
Detect Pmic Vendor ID.
ExitLowPowerMode
EFI_STATUS ExitLowPowerMode(VOID)
Send Exit Low Power Mode command to EC.
EcReset
EFI_STATUS EcReset(VOID)
Do EC reset.
UsbcSxEntry
EFI_STATUS UsbcSxEntry(IN OUT UINT8 *DataBuffer)
USBC Sx Entry Wait.
DetectEcRevision
EFI_STATUS DetectEcRevision(OUT UINT8 *DataBuffer)
Detect EC revision.
SetPmicVoltage
EFI_STATUS SetPmicVoltage(IN UINT8 EcDataVcc, IN UINT8 EcDataVddq)
Set Pmic Voltage.
EcResetEcInNormalMode
EFI_STATUS EcResetEcInNormalMode(VOID)
Initiate EC reset sequence.
UpdatePwm
EFI_STATUS UpdatePwm(VOID)
Send Update PWM command to EC.
EnableLanPower
EFI_STATUS EnableLanPower(IN BOOLEAN Enable)
Enable LAN power.
EcForceResetAfterAcRemoval
VOID EcForceResetAfterAcRemoval(IN UINT8 ForceResetAfterAcRemovalVar)
EcForceResetAfterAcRemoval.
SystemPowerOff
EFI_STATUS SystemPowerOff(VOID)
System power off.
EnableSataPort2Power
VOID EnableSataPort2Power(VOID)
Enable SATA port2 power.
EnableEcAcpiMode
EFI_STATUS EnableEcAcpiMode(IN BOOLEAN Enable)
Send enable ACPI mode command to EC.
UsbcSxExit
EFI_STATUS UsbcSxExit(OUT UINT8 *DataBuffer)
USBC Sx Exit Wait.
GetBoardInfo
EFI_STATUS GetBoardInfo(OUT UINT16 *BoardFabId)
Get board fab ID.
SetEcCriticalShutdownTemperature
EFI_STATUS SetEcCriticalShutdownTemperature(IN UINT8 DataBuffer)
Set EC critical shutdown temperature.
UpdateDevicePower
EFI_STATUS UpdateDevicePower(VOID)
Update Device Power.
ClearTenSecPwrButtonMode
VOID ClearTenSecPwrButtonMode(VOID)
Clear ten second power button mode.
PowerStateIsAc
BOOLEAN PowerStateIsAc(VOID)
Get power state from EC.
EcCommands.h
EcLib.h
EC library functions and definitions.
GetFanSpeed
EFI_STATUS GetFanSpeed(IN UINT8 Pwmvalue, OUT UINT16 *Speed)
Updates the PWM to the given value and returns the Fan speed.
QuerySmiEvent
EFI_STATUS QuerySmiEvent(OUT UINT8 *DataBuffer)
Query SMI event.
ReadEcRam
EFI_STATUS ReadEcRam(IN OUT UINT8 *DataBuffer)
Read data from EC RAM.
GetBaseEcFwVersion
EFI_STATUS GetBaseEcFwVersion(OUT UINT8 *DataBuffer)
Get Base EC FW version.
GetHotkeyScanCode
EFI_STATUS GetHotkeyScanCode(OUT UINT8 *DataBuffer)
Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
GetBatteryNumber
EFI_STATUS GetBatteryNumber(OUT UINT8 *DataBuffer)
Get the number of battery.
SetSlpS0Voltage
EFI_STATUS SetSlpS0Voltage(IN UINT8 EcDataV085ACNT)
Set SLP_S0 Voltage.
DfctFastChargingMode
EFI_STATUS DfctFastChargingMode(IN BOOLEAN Enable)
Select charging method.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EcPlatformInitDxe.c Source File

  • PlatformInit
  • PlatformInitDxe
EcPlatformInitDxe.c
Go to the documentation of this file.
1 /** @file
2 Source code file for the Platform Init DXE module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 /**
35 Check Lid and Base EC Protocol Version
36 **/
37
38 #include "PlatformInitDxe.h"
39 #include <Include/Protocol/SimpleTextIn.h>
40 #include <Include/Library/UefiLib.h>
41
42
43 /**
44 Verifies LID base EC protocol version
45
46 **/
47 VOID
48 EFIAPI
49 CheckLidBaseEcProtocolVersion (
50 VOID
51 )
52 {
53 EFI_STATUS Status;
54 EFI_INPUT_KEY Key;
55 CHAR16 *StringBuffer1 = NULL;
56 CHAR16 *StringBuffer2 = NULL;
57 CHAR16 *StringBuffer3 = NULL;
58 CHAR16 *StringBuffer4 = NULL;
59 UINT8 Timer;
60 CHAR16 *String = NULL;
61 UINTN StringBuffSize;
62
63 if ((PcdGet8 (PcdBoardType) == BoardTypeSds) &&
64 PcdGetBool (PcdDockAttached) &&
65 (PcdGet8 (PcdEcProtocolVersion) != PcdGet8 (PcdBaseEcProtocolVersion))) {
66 if (gST->ConOut != NULL && gST->ConIn != NULL) {
67 //
68 // Popup a menu to notice user
69 //
70 gST->ConOut->ClearScreen (gST->ConOut);
71
72 String = AllocateZeroPool (2 * sizeof (CHAR16));
73 ASSERT (String != NULL);
74 if (String == NULL) {
75 goto EXIT;
76 }
77
78 StringBuffer1 = AllocateZeroPool (200 * sizeof (CHAR16));
79 ASSERT (StringBuffer1 != NULL);
80 if (StringBuffer1 == NULL) {
81 goto EXIT;
82 }
83
84 StringBuffer2 = AllocateZeroPool (200 * sizeof (CHAR16));
85 ASSERT (StringBuffer2 != NULL);
86 if (StringBuffer2 == NULL) {
87 goto EXIT;
88 }
89
90 StringBuffer3 = AllocateZeroPool (200 * sizeof (CHAR16));
91 ASSERT (StringBuffer3 != NULL);
92 if (StringBuffer3 == NULL) {
93 goto EXIT;
94 }
95
96 StringBuffer4 = AllocateZeroPool (200 * sizeof (CHAR16));
97 ASSERT (StringBuffer4 != NULL);
98 if (StringBuffer4 == NULL) {
99 goto EXIT;
100 }
101
102 StringBuffSize = (200 * sizeof (CHAR16)) / sizeof (CHAR16);
103 StrCpyS (StringBuffer1, StringBuffSize, L"!!! WARNING: Lid and Base EC Protocol version mismatch !!!");
104 StrCpyS (StringBuffer2, StringBuffSize, L"EC Protocol version: ");
105 UnicodeValueToString (String, PREFIX_ZERO | RADIX_HEX, PcdGet8 (PcdEcProtocolVersion), 2);
106 StrCatS (StringBuffer2, StringBuffSize, String);
107 StrCpyS (StringBuffer3, StringBuffSize, L"Base EC Protocol version: ");
108 UnicodeValueToString (String, PREFIX_ZERO | RADIX_HEX, PcdGet8 (PcdBaseEcProtocolVersion), 2);
109 StrCatS (StringBuffer3, StringBuffSize, String);
110 StrCpyS (StringBuffer4, StringBuffSize, L"Press <ENTER> to continue.");
111
112 CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_RED, &Key, StringBuffer1, StringBuffer2, StringBuffer3, StringBuffer4, NULL);
113
114 //
115 // Wait for a keystroke
116 //
117 Key.UnicodeChar = 0;
118 Timer = 30;
119
120 do {
121 Status = gBS->CheckEvent (gST->ConIn->WaitForKey);
122 if (!EFI_ERROR (Status)) {
123 Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
124 }
125 gBS->Stall (1000000);
126 Timer --;
127 if (Timer == 0) {
128 gST->ConOut->ClearScreen (gST->ConOut);
129 return;
130 }
131 } while (Key.UnicodeChar != CHAR_CARRIAGE_RETURN);
132
133 gST->ConOut->ClearScreen (gST->ConOut);
134 }
135 }
136
137 EXIT:
138
139 if (StringBuffer1 != NULL) {
140 FreePool (StringBuffer1);
141 }
142
143 if (StringBuffer2 != NULL) {
144 FreePool (StringBuffer2);
145 }
146
147 if (StringBuffer3 != NULL) {
148 FreePool (StringBuffer3);
149 }
150
151 if (StringBuffer4 != NULL) {
152 FreePool (StringBuffer4);
153 }
154
155 if (String != NULL) {
156 FreePool (String);
157 }
158
159 return;
160 }
CheckLidBaseEcProtocolVersion
VOID CheckLidBaseEcProtocolVersion(VOID)
Check Lid and Base EC Protocol Version.
Definition: EcPlatformInitDxe.c:49
PlatformInitDxe.h
Platform Info Driver.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EcTcssLib.h Source File

  • Library
EcTcssLib.h
Go to the documentation of this file.
1 /** @file
2 EC TCSS library functions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _BASE_EC_TCSS_LIB_H_
36 #define _BASE_EC_TSSS_LIB_H_
37
38 //
39 // Include files
40 //
41 #include <Base.h>
42 #include <Uefi.h>
43 #include <Library/EcCommands.h>
44 #include <Library/EcLib.h>
45
46 //
47 // Retry time in milli-seconds for EC-TCSS commands with Timeout
48 //
49 #define EC_TCSS_RETRY_TIME_GET_USB_CONN_STATUS 10
50 #define EC_TCSS_RETRY_TIME_SX_ENTRY_WAIT 100
51 #define EC_TCSS_RETRY_TIME_SX_EXIT_WAIT 100
52
53 //
54 // Bitmasks for USBC IOM Ready Notify message request byte
55 //
56 #define EC_TCSS_BITMASK_REPLAY_MESSAGES 0x01
57 #define EC_TCSS_BITMASK_VCCST_ON 0x02
58
59 /**
60 USBC IOM Ready Notify
61
62 @param[in][out] DataBuffer
63
64 @retval EFI_SUCCESS Command success
65 @retval EFI_DEVICE_ERROR Command error
66 **/
67 EFI_STATUS
68 UsbcIomReadyNotify (
69 IN OUT UINT8 *DataBuffer
70 );
71
72 /**
73 USBC Sx Entry Wait
74
75 @param[in][out] DataBuffer
76 @param[in] Timeout
77
78 @retval EFI_SUCCESS Command success
79 @retval EFI_DEVICE_ERROR Command error
80 **/
81 EFI_STATUS
82 UsbcGetUsbConnStatus (
83 IN OUT UINT8 *DataBuffer,
84 IN UINT32 Timeout
85 );
86
87 /**
88 Send enable ACPI mode command to EC
89
90 @param[in][out] DataBuffer
91 @param[in] Timeout
92
93 @retval EFI_SUCCESS Command success
94 @retval EFI_DEVICE_ERROR Command error
95 **/
96 EFI_STATUS
97 UsbcSxEntry (
98 IN OUT UINT8 *DataBuffer,
99 IN UINT32 Timeout
100 );
101
102 /**
103 USBC Sx Exit Wait
104
105 @param[out] DataBuffer
106 @param[in] Timeout
107
108 @retval EFI_SUCCESS Command success
109 @retval EFI_DEVICE_ERROR Command error
110 **/
111 EFI_STATUS
112 UsbcSxExit (
113 OUT UINT8 *DataBuffer,
114 IN UINT32 Timeout
115 );
116 #endif // _BASE_EC_TSSS_LIB_H_
UsbcSxEntry
EFI_STATUS UsbcSxEntry(IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
Send enable ACPI mode command to EC.
UsbcIomReadyNotify
EFI_STATUS UsbcIomReadyNotify(IN OUT UINT8 *DataBuffer)
USBC IOM Ready Notify.
UsbcGetUsbConnStatus
EFI_STATUS UsbcGetUsbConnStatus(IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Entry Wait.
UsbcSxExit
EFI_STATUS UsbcSxExit(OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Exit Wait.
EcCommands.h
EcLib.h
EC library functions and definitions.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Ecdt.h Source File

  • Acpi
  • AcpiTables
  • Ecdt
Ecdt.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Embedded Controller Boot
3 Resources Table (ECDT). All changes to the ECDT contents should be done
4 in this file.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 2016 - 2017 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _ECDT_H_
38 #define _ECDT_H_
39
40 //
41 // Statements that include other files
42 //
43
44 #include <IndustryStandard/Acpi.h>
45
46 //
47 // ECDT Definitions
48 //
49 #define EFI_ACPI_OEM_ECDT_REVISION 0x00000001
50
51 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Efi.h Source File

Efi.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _EFI_H_
35 #define _EFI_H_
36
37 #include "Tiano.h"
38
39 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EfiUsbFnIo.h Source File

  • Protocol
EfiUsbFnIo.h
Go to the documentation of this file.
1 /** @file
2 EFI USB function IO Protocol
3 This protocol supports Usb Function IO API.
4
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 2015 - 2017 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification
35 **/
36
37 #ifndef __EFI_USB_FUNC_IO_H__
38 #define __EFI_USB_FUNC_IO_H__
39
40 #include <IndustryStandard/Usb.h>
41
42 #define EFI_USBFN_IO_PROTOCOL_REVISION 0x00010001
43
44 /* //{32D2963A-FE5D-4f30-B633-6E5DC55803CC}
45 #define EFI_USBFN_IO_PROTOCOL_GUID \
46 {0x32d2963a, 0xfe5d, 0x4f30, 0xb6, 0x33, 0x6e, 0x5d, 0xc5, \
47 0x58, 0x3, 0xcc };
48 */
49
50 typedef struct _EFI_USBFN_IO_PROTOCOL EFI_USBFN_IO_PROTOCOL;
51
52 //
53 // USB standard descriptors and reqeust
54 //
55 typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST;
56 typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR;
57 typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR;
58 typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR;
59 typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR;
60
61 typedef enum _EFI_USBFN_PORT_TYPE {
62 EfiUsbUnknownPort = 0,
63 EfiUsbStandardDownstreamPort,
64 EfiUsbChargingDownstreamPort,
65 EfiUsbDedicatedChargingPort,
66 EfiUsbInvalidDedicatedChargingPort
67 } EFI_USBFN_PORT_TYPE;
68
69 /**
70 USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and
71 USB_ENDPOINT_DESCRIPTOR are already defined
72 in UEFI spec 2.3, as par USB 2.0 spec.
73 **/
74
75 typedef struct {
76 EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor;
77 EFI_USB_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable;
78 } EFI_USB_INTERFACE_INFO;
79
80 typedef struct {
81 EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor;
82 EFI_USB_INTERFACE_INFO **InterfaceInfoTable;
83 } EFI_USB_CONFIG_INFO;
84
85 typedef struct {
86 EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor;
87 EFI_USB_CONFIG_INFO **ConfigInfoTable;
88 } EFI_USB_DEVICE_INFO;
89
90
91 typedef enum _EFI_USB_ENDPOINT_TYPE {
92 UsbEndpointControl = 0x00,
93 UsbEndpointIsochronous = 0x01,
94 UsbEndpointBulk = 0x02,
95 UsbEndpointInterrupt = 0x03
96 } EFI_USB_ENDPOINT_TYPE;
97
98
99 typedef enum _EFI_USBFN_DEVICE_INFO_ID {
100 EfiUsbDeviceInfoUnknown = 0,
101 EfiUsbDeviceInfoSerialNumber,
102 EfiUsbDeviceInfoManufacturerName,
103 EfiUsbDeviceInfoProductName
104 } EFI_USBFN_DEVICE_INFO_ID;
105
106
107 typedef enum _EFI_USBFN_ENDPOINT_DIRECTION {
108 EfiUsbEndpointDirectionHostOut = 0,
109 EfiUsbEndpointDirectionHostIn,
110 EfiUsbEndpointDirectionDeviceTx = EfiUsbEndpointDirectionHostIn,
111 EfiUsbEndpointDirectionDeviceRx = EfiUsbEndpointDirectionHostOut
112 } EFI_USBFN_ENDPOINT_DIRECTION;
113
114
115 typedef enum _EFI_USBFN_MESSAGE {
116 //
117 // Nothing
118 //
119 EfiUsbMsgNone = 0,
120 //
121 // SETUP packet is received, returned Buffer contains
122 // EFI_USB_DEVICE_REQUEST struct
123 //
124 EfiUsbMsgSetupPacket,
125 //
126 // Indicates that some of the requested data has been received from the
127 // host. It is the responsibility of the class driver to determine if it
128 // needs to wait for any remaining data. Returned Buffer contains
129 // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer
130 // status and count of bytes received.
131 //
132 EfiUsbMsgEndpointStatusChangedRx,
133 //
134 // Indicates that some of the requested data has been transmitted to the
135 // host. It is the responsibility of the class driver to determine if any
136 // remaining data needs to be resent. Returned Buffer contains
137 // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer
138 // status and count of bytes sent.
139 //
140 EfiUsbMsgEndpointStatusChangedTx,
141 //
142 // DETACH bus event signaled
143 //
144 EfiUsbMsgBusEventDetach,
145 //
146 // ATTACH bus event signaled
147 //
148 EfiUsbMsgBusEventAttach,
149 //
150 // RESET bus event signaled
151 //
152 EfiUsbMsgBusEventReset,
153 //
154 // SUSPEND bus event signaled
155 //
156 EfiUsbMsgBusEventSuspend,
157 //
158 // RESUME bus event signaled
159 //
160 EfiUsbMsgBusEventResume,
161 //
162 // Bus speed updated, returned buffer indicated bus speed using
163 // following enumeration named EFI_USB_BUS_SPEED
164 //
165 EfiUsbMsgBusEventSpeed
166 } EFI_USBFN_MESSAGE;
167
168
169 typedef enum _EFI_USBFN_TRANSFER_STATUS {
170 UsbTransferStatusUnknown = 0,
171 UsbTransferStatusComplete,
172 UsbTransferStatusAborted,
173 UsbTransferStatusActive,
174 UsbTransferStatusNone
175 } EFI_USBFN_TRANSFER_STATUS;
176
177
178 typedef struct _EFI_USBFN_TRANSFER_RESULT {
179 UINTN BytesTransferred;
180 EFI_USBFN_TRANSFER_STATUS TransferStatus;
181 UINT8 EndpointIndex;
182 EFI_USBFN_ENDPOINT_DIRECTION Direction;
183 VOID *Buffer;
184 } EFI_USBFN_TRANSFER_RESULT;
185
186 typedef enum _EFI_USB_BUS_SPEED {
187 UsbBusSpeedUnknown = 0,
188 UsbBusSpeedLow,
189 UsbBusSpeedFull,
190 UsbBusSpeedHigh,
191 UsbBusSpeedSuper,
192 UsbBusSpeedMaximum = UsbBusSpeedSuper
193 } EFI_USB_BUS_SPEED;
194
195 typedef union _EFI_USBFN_MESSAGE_PAYLOAD {
196 EFI_USB_DEVICE_REQUEST udr;
197 EFI_USBFN_TRANSFER_RESULT utr;
198 EFI_USB_BUS_SPEED ubs;
199 } EFI_USBFN_MESSAGE_PAYLOAD;
200
201 typedef enum _EFI_USBFN_POLICY_TYPE {
202 EfiUsbPolicyUndefined = 0,
203 EfiUsbPolicyMaxTransactionSize,
204 EfiUsbPolicyZeroLengthTerminationSupport,
205 EfiUsbPolicyZeroLengthTermination
206 } EFI_USBFN_POLICY_TYPE;
207
208
209 /**
210
211 Allocates transfer buffer of the specified size that satisfies
212 controller requirements.
213
214 The AllocateTransferBuffer function allocates a memory region of Size bytes and
215 returns the address of the allocated memory that satisfies underlying
216 controller requirements in the location referenced by Buffer.
217
218 **/
219 typedef
220 EFI_STATUS
221 (EFIAPI * EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (
222 IN EFI_USBFN_IO_PROTOCOL *This,
223 IN UINTN Size,
224 OUT VOID **Buffer
225 );
226
227 /**
228
229 Deallocates the memory allocated for the transfer buffer by AllocateTransferBuffer function.
230
231 **/
232 typedef
233 EFI_STATUS
234 (EFIAPI * EFI_USBFN_IO_FREE_TRANSFER_BUFFER) (
235 IN EFI_USBFN_IO_PROTOCOL *This,
236 IN VOID *Buffer
237 );
238
239 /**
240 Returns information about what type of device was attached.
241
242 **/
243 typedef
244 EFI_STATUS
245 (EFIAPI * EFI_USBFN_IO_DETECT_PORT) (
246 IN EFI_USBFN_IO_PROTOCOL *This,
247 OUT EFI_USBFN_PORT_TYPE *PortType
248 );
249
250 /**
251 Configure endpoints based on supplied device and configuration descriptors.
252 **/
253 typedef
254 EFI_STATUS
255 (EFIAPI * EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) (
256 IN EFI_USBFN_IO_PROTOCOL *This,
257 IN EFI_USB_DEVICE_INFO *DeviceInfo
258 );
259
260
261 /**
262 Returns the maximum packet size of the specified endpoint type for the supplied bus speed.
263 **/
264 typedef
265 EFI_STATUS
266 (EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) (
267 IN EFI_USBFN_IO_PROTOCOL *This,
268 IN EFI_USB_ENDPOINT_TYPE EndpointType,
269 IN EFI_USB_BUS_SPEED BusSpeed,
270 OUT UINT16 *MaxPacketSize
271 );
272
273 /**
274 Returns the maximum supported transfer size.
275 **/
276 typedef
277 EFI_STATUS
278 (EFIAPI * EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) (
279 IN EFI_USBFN_IO_PROTOCOL *This,
280 OUT UINTN *MaxTransferSize
281 );
282
283 /**
284 Returns device specific information based on the supplied identifier as a
285 Unicode string.
286 **/
287 typedef
288 EFI_STATUS
289 (EFIAPI * EFI_USBFN_IO_GET_DEVICE_INFO) (
290 IN EFI_USBFN_IO_PROTOCOL *This,
291 IN EFI_USBFN_DEVICE_INFO_ID Id,
292 IN OUT UINTN *BufferSize,
293 OUT VOID *Buffer OPTIONAL
294 );
295
296 /**
297 Returns vendor-id and product-id of the device.
298 **/
299 typedef
300 EFI_STATUS
301 (EFIAPI * EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) (
302 IN EFI_USBFN_IO_PROTOCOL *This,
303 OUT UINT16 *Vid,
304 OUT UINT16 *Pid
305 );
306
307 /**
308 Aborts transfer on the specified endpoint.
309 **/
310 typedef
311 EFI_STATUS
312 (EFIAPI * EFI_USBFN_IO_ABORT_TRANSFER) (
313 IN EFI_USBFN_IO_PROTOCOL *This,
314 IN UINT8 EndpointIndex,
315 IN EFI_USBFN_ENDPOINT_DIRECTION Direction
316 );
317
318 /**
319 Returns the stall state on the specified endpoint.
320 **/
321 typedef
322 EFI_STATUS
323 (EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) (
324 IN EFI_USBFN_IO_PROTOCOL *This,
325 IN UINT8 EndpointIndex,
326 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
327 IN OUT BOOLEAN *State
328 );
329
330 /**
331 Sets or clears the stall state on the specified endpoint.
332 **/
333 typedef
334 EFI_STATUS
335 (EFIAPI * EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) (
336 IN EFI_USBFN_IO_PROTOCOL *This,
337 IN UINT8 EndpointIndex,
338 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
339 IN BOOLEAN State
340 );
341
342
343 /**
344 This function is called repeatedly to receive updates on USB bus states,
345 receive, transmit status changes on endpoints and setup packet on endpoint 0.
346 **/
347 typedef
348 EFI_STATUS
349 (EFIAPI * EFI_USBFN_IO_EVENTHANDLER) (
350 IN EFI_USBFN_IO_PROTOCOL *This,
351 OUT EFI_USBFN_MESSAGE *Message,
352 IN OUT UINTN *PayloadSize,
353 OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload
354 );
355
356 /**
357 Primary function to handle transfer in either direction based on specified
358 direction and on the specified endpoint.
359 **/
360 typedef
361 EFI_STATUS
362 (EFIAPI *EFI_USBFN_IO_TRANSFER) (
363 IN EFI_USBFN_IO_PROTOCOL *This,
364 IN UINT8 EndpointIndex,
365 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
366 IN OUT UINTN *BufferSize,
367 IN OUT VOID *Buffer
368 );
369
370 /**
371 This function supplies power to the USB controller if needed,
372 initialize hardware and internal data structures, and then return.
373
374 The port must not be activated by this function.
375 **/
376 typedef
377 EFI_STATUS
378 (EFIAPI * EFI_USBFN_IO_START_CONTROLLER) (
379 IN EFI_USBFN_IO_PROTOCOL *This
380 );
381
382 /**
383 This function disables the hardware device by resetting the run/stop bit and
384 power off the USB controller if needed.
385 **/
386 typedef
387 EFI_STATUS
388 (EFIAPI * EFI_USBFN_IO_STOP_CONTROLLER) (
389 IN EFI_USBFN_IO_PROTOCOL *This
390 );
391
392 /**
393 This function sets the configuration policy for the specified non-control endpoint.
394
395 Refer to the description for calling restrictions.
396 **/
397 typedef
398 EFI_STATUS
399 (EFIAPI * EFI_USBFN_IO_SET_ENDPOINT_POLICY) (
400 IN EFI_USBFN_IO_PROTOCOL *This,
401 IN UINT8 EndpointIndex,
402 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
403 IN EFI_USBFN_POLICY_TYPE PolicyType,
404 IN UINTN BufferSize,
405 IN VOID *Buffer
406 );
407
408 /**
409 This function retrieves the configuration policy for the specified non-control endpoint.
410
411 There are no associated calling restrictions for this function.
412 **/
413 typedef
414 EFI_STATUS
415 (EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_POLICY) (
416 IN EFI_USBFN_IO_PROTOCOL *This,
417 IN UINT8 EndpointIndex,
418 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
419 IN EFI_USBFN_POLICY_TYPE PolicyType,
420 IN OUT UINTN *BufferSize,
421 IN OUT VOID *Buffer
422 );
423
424
425 struct _EFI_USBFN_IO_PROTOCOL {
426 UINT32 Revision;
427 EFI_USBFN_IO_DETECT_PORT DetectPort;
428 EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS ConfigureEnableEndpoints;
429 EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE GetEndpointMaxPacketSize;
430 EFI_USBFN_IO_GET_DEVICE_INFO GetDeviceInfo;
431 EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID GetVendorIdProductId;
432 EFI_USBFN_IO_ABORT_TRANSFER AbortTransfer;
433 EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE GetEndpointStallState;
434 EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE SetEndpointStallState;
435 EFI_USBFN_IO_EVENTHANDLER EventHandler;
436 EFI_USBFN_IO_TRANSFER Transfer;
437 EFI_USBFN_IO_GET_MAXTRANSFER_SIZE GetMaxTransferSize;
438 EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER AllocateTransferBuffer;
439 EFI_USBFN_IO_FREE_TRANSFER_BUFFER FreeTransferBuffer;
440
441 /// Valid for version EFI_USBFN_IO_PROTOCOL_REVISION2 and above
442 EFI_USBFN_IO_START_CONTROLLER StartController;
443 EFI_USBFN_IO_STOP_CONTROLLER StopController;
444 EFI_USBFN_IO_SET_ENDPOINT_POLICY SetEndpointPolicy;
445 EFI_USBFN_IO_GET_ENDPOINT_POLICY GetEndpointPolicy;
446 };
447
448 #endif
EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE
EFI_STATUS(* EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE)(IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_ENDPOINT_TYPE EndpointType, IN EFI_USB_BUS_SPEED BusSpeed, OUT UINT16 *MaxPacketSize)
Returns the maximum packet size of the specified endpoint type for the supplied bus speed...
Definition: EfiUsbFnIo.h:266
EFI_USBFN_IO_FREE_TRANSFER_BUFFER
EFI_STATUS(* EFI_USBFN_IO_FREE_TRANSFER_BUFFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN VOID *Buffer)
Deallocates the memory allocated for the transfer buffer by AllocateTransferBuffer function...
Definition: EfiUsbFnIo.h:234
EFI_USBFN_IO_GET_ENDPOINT_POLICY
EFI_STATUS(* EFI_USBFN_IO_GET_ENDPOINT_POLICY)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
This function retrieves the configuration policy for the specified non-control endpoint.
Definition: EfiUsbFnIo.h:415
EFI_USBFN_IO_SET_ENDPOINT_POLICY
EFI_STATUS(* EFI_USBFN_IO_SET_ENDPOINT_POLICY)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN UINTN BufferSize, IN VOID *Buffer)
This function sets the configuration policy for the specified non-control endpoint.
Definition: EfiUsbFnIo.h:399
EFI_USBFN_IO_ABORT_TRANSFER
EFI_STATUS(* EFI_USBFN_IO_ABORT_TRANSFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction)
Aborts transfer on the specified endpoint.
Definition: EfiUsbFnIo.h:312
EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID
EFI_STATUS(* EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID)(IN EFI_USBFN_IO_PROTOCOL *This, OUT UINT16 *Vid, OUT UINT16 *Pid)
Returns vendor-id and product-id of the device.
Definition: EfiUsbFnIo.h:301
EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER
EFI_STATUS(* EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINTN Size, OUT VOID **Buffer)
Allocates transfer buffer of the specified size that satisfies controller requirements.
Definition: EfiUsbFnIo.h:221
EFI_USBFN_IO_GET_MAXTRANSFER_SIZE
EFI_STATUS(* EFI_USBFN_IO_GET_MAXTRANSFER_SIZE)(IN EFI_USBFN_IO_PROTOCOL *This, OUT UINTN *MaxTransferSize)
Returns the maximum supported transfer size.
Definition: EfiUsbFnIo.h:278
EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS
EFI_STATUS(* EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS)(IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_DEVICE_INFO *DeviceInfo)
Configure endpoints based on supplied device and configuration descriptors.
Definition: EfiUsbFnIo.h:255
EFI_USBFN_IO_EVENTHANDLER
EFI_STATUS(* EFI_USBFN_IO_EVENTHANDLER)(IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_MESSAGE *Message, IN OUT UINTN *PayloadSize, OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload)
This function is called repeatedly to receive updates on USB bus states, receive, transmit status cha...
Definition: EfiUsbFnIo.h:349
EFI_USB_INTERFACE_INFO
USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR a...
Definition: EfiUsbFnIo.h:75
EFI_USBFN_IO_TRANSFER
EFI_STATUS(* EFI_USBFN_IO_TRANSFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
Primary function to handle transfer in either direction based on specified direction and on the speci...
Definition: EfiUsbFnIo.h:362
EFI_USBFN_IO_DETECT_PORT
EFI_STATUS(* EFI_USBFN_IO_DETECT_PORT)(IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_PORT_TYPE *PortType)
Returns information about what type of device was attached.
Definition: EfiUsbFnIo.h:245
EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE
EFI_STATUS(* EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN BOOLEAN State)
Sets or clears the stall state on the specified endpoint.
Definition: EfiUsbFnIo.h:335
EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE
EFI_STATUS(* EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT BOOLEAN *State)
Returns the stall state on the specified endpoint.
Definition: EfiUsbFnIo.h:323
EFI_USBFN_IO_STOP_CONTROLLER
EFI_STATUS(* EFI_USBFN_IO_STOP_CONTROLLER)(IN EFI_USBFN_IO_PROTOCOL *This)
This function disables the hardware device by resetting the run/stop bit and power off the USB contro...
Definition: EfiUsbFnIo.h:388
EFI_USBFN_IO_START_CONTROLLER
EFI_STATUS(* EFI_USBFN_IO_START_CONTROLLER)(IN EFI_USBFN_IO_PROTOCOL *This)
This function supplies power to the USB controller if needed, initialize hardware and internal data s...
Definition: EfiUsbFnIo.h:378
EFI_USBFN_IO_GET_DEVICE_INFO
EFI_STATUS(* EFI_USBFN_IO_GET_DEVICE_INFO)(IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USBFN_DEVICE_INFO_ID Id, IN OUT UINTN *BufferSize, OUT VOID *Buffer OPTIONAL)
Returns device specific information based on the supplied identifier as a Unicode string...
Definition: EfiUsbFnIo.h:289
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: EmmcCardInfoProtocol.h Source File

  • Protocol
EmmcCardInfoProtocol.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2013 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _EMMC_CARD_INFO_H_
35 #define _EMMC_CARD_INFO_H_
36
37 typedef struct _EFI_EMMC_CARD_INFO_PROTOCOL EFI_EMMC_CARD_INFO_PROTOCOL;
38
39
40 //
41 // EMMC Card info Structures
42 //
43 struct _EFI_EMMC_CARD_INFO_PROTOCOL{
44 CARD_DATA *CardData;
45 };
46
47 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: FWUpdateLib.h Source File

  • Library
FWUpdateLib.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2009 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _EFI_FW_UPDATE_LIB_H_
35 #define _EFI_FW_UPDATE_LIB_H_
36
37 #define SUCCESS 0
38 #define INVALID_DATA_FORMAT_VERSION 0
39 #define INVALID_MANIFEST_DATA 1
40 #define NO_FPT_IMAGE 2
41 #define MANIFEST_BUFFER 0x1000
42 #define FPT_PARTITION_NAME_FPT 0x54504624
43 #define INVALID_PARTITION_START 0
44
45 // below structure is defiend by the fw team
46 // in fwucommon.h file
47 typedef struct _UPDATE_FLAGS_LIB
48 {
49 unsigned int RestorePoint:1; // If set indicate restore point
50 unsigned int RestartOperation:1; // If set indicate restart operation, like lost hard drive etc...
51 unsigned int UserRollback:1; // indicates user has initiated a rollback
52 unsigned int Reserve:29; //
53 }UPDATE_FLAGS_LIB;
54
55 // Used by the tool to perform FULL FW update
56 typedef enum _UPDATE_TYPE
57 {
58 DOWNGRADE_SUCCESS = 0,
59 DOWNGRADE_FAILURE,
60 SAMEVERSION_SUCCESS,
61 SAMEVERSION_FAILURE,
62 UPGRADE_SUCCESS,
63 UPGRADE_PROMPT
64 }UPDATE_TYPE;
65
66 //Image type to validate the binary sent to update
67 //For Full Update - only FULL image type is valid
68 //For Partial Update - only FULL and PARTIAL image type is valid
69 //FULL Image => Image with Flash Partition Table, FTPR, and NFTPR
70 //PARTIAL Image => Image with no Flash Partition Table or FTPR or NFTPR,
71 // only WCOD or LOCL
72 typedef enum _IMAGE_TYPE
73 {
74 FULL = 0,
75 PARTIAL,
76 RESTORE,
77 INVALID
78 }IMAGE_TYPE;
79
80 typedef enum _SKU_TYPE {
81 SKU_1_5_MB = 0,
82 SKU_5_MB,
83 SKU_INVALID
84 }SKU_TYPE;
85
86 //Used by the tool to retrieve FW version information
87 typedef struct {
88 unsigned short Major;
89 unsigned short Minor;
90 unsigned short Hotfix;
91 unsigned short Build;
92 } VersionLib;
93
94 typedef enum _FWUPD_POWER_SOURCE
95 {
96 FWUPD_POWER_SOURCE_AC = 1, ///< AC Power source
97 FWUPD_POWER_SOURCE_DC = 2, ///< DC Power source
98 FWUPD_POWER_SOURCE_UNKOWN ///< Unable to determine power source
99 } FWUPD_POWER_SOURCE;
100
101 //Should be used by both tool and UNS to retrieve the Updated UPV version
102 typedef struct _IPU_UPDATED_INFO
103 {
104 unsigned int UpdatedUpvVer;//Version from the update image file that is for updating IPU
105 unsigned int Reserved[4];
106 }IPU_UPDATED_INFO;
107
108 // disable the "zero-sized array" warning
109 #pragma warning(disable:4200)
110 typedef enum _FWU_STATUS {
111 FWU_STATUS_SUCCESS = 0,
112 FWU_STATUS_NO_MEMORY = 1,
113 FWU_STATUS_NOT_READY = 2,
114 FWU_STATUS_ILLEGAL_LENGTH = 3,
115 FWU_STATUS_AUTHENTICATION_FAILED = 4,
116 FWU_STATUS_INTERNAL_ERROR = 5,
117 FWU_STATUS_SKU_FAILURE = 6,
118 FWU_STATUS_VERSION_FAILURE = 7
119 }FWU_STATUS;
120
121 // From FWU_if.h
122
123 #pragma pack(1)
124
125 /**
126 * FWU_GET_INFO_MESSAGE - get version
127 *
128 * @MessageType: FWU_MESSAGE_TYPE_GET_INFO
129 */
130 typedef struct {
131 UINT32 MessageType;
132 } FWU_GET_INFO_MESSAGE;
133
134 /**
135 * FWU_DATA_MESSAGE - data fragment of the image
136 *
137 * @MessageType: FWU_MESSAGE_TYPE_DATA
138 * @Length: The length of the data field, in Little Endian
139 * @Reserved: Reserved, must be 0
140 * @Data: The data of the image fragment
141 */
142 typedef struct {
143 UINT32 MessageType;
144 UINT32 Length;
145 UINT8 Reserved[3];
146 #ifndef _DOS
147 UINT8 Data[0];
148 #endif
149 } FWU_DATA_MESSAGE;
150
151 #pragma pack()
152
153 bool
154 IsUpdateStatusPending (
155 IN UINT32 status
156 )
157 /*++
158
159 Routine Description:
160
161 Checks if ME FW Update client is ready to accept an update
162
163 Arguments:
164
165
166 Returns:
167
168 true if ready
169
170 --*/
171 ;
172
173 UINT32
174 CheckPolicyBuffer (
175 IN char* buffer,
176 IN int bufferLength,
177 IN int AllowSV,
178 IN UPDATE_TYPE *Upd_Type,
179 IN VersionLib *ver
180 )
181 /*++
182
183 Routine Description:
184
185 This routine determines if the update is allowed given the ME Upgrade/downgrade/same version policy
186
187 Arguments:
188
189 Returns:
190
191 FWU_ERROR_SUCCESS if operation allowed
192
193 --*/
194 ;
195
196 UINT32
197 FwUpdateFullBuffer (
198 IN char *buffer,
199 IN UINT32 bufferLength,
200 IN char *_pwd,
201 IN int _forceResetLib,
202 IN UINT32 UpdateEnvironment,
203 IN _UUID OemID,
204 IN UPDATE_FLAGS_LIB update_flags,
205 IN void(*func)(float, float)
206 )
207 /*++
208
209 Routine Description:
210
211 This routine sends the buffer to the ME FW Update Client
212
213 Arguments:
214
215 Returns:
216
217 FWU_ERROR_SUCCESS if operation allowed
218
219 --*/
220 ;
221
222 UINT32
223 FwUpdatePartialBuffer (
224 IN char *buffer,
225 IN UINT32 bufferLength,
226 IN UINT32 PartitionID,
227 IN UINT32 Flags,
228 IN IPU_UPDATED_INFO *IpuUpdatedInfo,
229 IN char *_pwd,
230 //IN int _forceResetLib,
231 IN UINT32 UpdateEnvironment,
232 IN _UUID OemID,
233 IN UPDATE_FLAGS_LIB update_flags,
234 IN void(*func)(float, float)
235 );
236
237 UINT32
238 FWUpdate_QueryStatus_Get_Response (
239 IN UINT32 *UpdateStatus,
240 IN UINT32 *TotalStages,
241 IN UINT32 *PercentWritten,
242 IN UINT32 *LastUpdateStatus,
243 IN UINT32 *LastResetType
244 )
245 /*++
246
247 Routine Description:
248
249 This routine queries the ME Kernel for the update status
250
251 Arguments:
252
253 Returns:
254
255 FWU_ERROR_SUCCESS if operation allowed
256
257 --*/
258 ;
259
260 bool
261 VerifyOemId(
262 IN _UUID id
263 )
264 /*++
265
266 Routine Description:
267
268 The ME FW when created has an OEM ID embedded in it. For security
269 reasons, we need to verify that the OEM ID of the application (mOemID)
270 matches the OEM ID of the ME FW.
271
272 NOTE: A connection to the client is required before this routine is
273 executed.
274
275 Arguments:
276
277 UUID to check
278
279
280 Returns:
281
282 true or false indicating if the match was succesfull
283
284 --*/
285 ;
286
287 EFI_STATUS
288 GetLastStatus(
289 OUT UINT32 *LastFwUpdateStatus
290 )
291 /*++
292
293 Routine Description:
294
295 Get the last status of the FW Update Client - this is used to determine if a previous update
296 requires a reboot
297
298 Arguments:
299
300 UINT32 pointer for results of previous update.
301
302
303 Returns:
304
305 EFI Error code
306
307 --*/
308 ;
309
310 EFI_STATUS
311 GetLastUpdateResetType (
312 OUT UINT32 *LastResetType
313 )/*++
314
315 Routine Description:
316
317 Get the last status of the FW Update Client - this is used to determine if a previous update
318 requires a reboot
319
320 Arguments:
321
322 UINT32 pointer for results of previous update.
323
324
325 Returns:
326
327 EFI Error code
328
329 --*/
330 ;
331
332 EFI_STATUS
333 GetInterfaces (
334 OUT UINT16 *interfaces
335 )
336 ;
337
338 EFI_STATUS
339 CheckVersion(
340 IN UINT8 *FileBuffer,
341 IN BOOLEAN AllowSV,
342 OUT FlashVersion *FlashVersion,
343 OUT UINT32 *LastFwUpdateStatus
344 )
345 /*++
346
347 Routine Description:
348
349 Policy routine to verify if the current FW version is older
350 than the version in the image.
351
352 The routine will return the result of a previous ME FW Update. If a reset is required
353 before an update can occur, the return value will indicate it
354
355 NOTE: A connection to the client is required before this routine is
356 executed.
357
358 Arguments:
359
360 UINT8 pointer to update image
361 BOOLEAN indicating TRUE for same version update
362 FlashVersion pointer for return version numbers of FW Update image
363 UINT32 pointer for results of previous update.
364
365
366 Returns:
367
368 EFI_UNSUPPORTED if version is of update image is not supported
369
370 --*/
371 ;
372
373 EFI_STATUS
374 StartUpdate(
375 IN UINT8 *FileBuffer,
376 IN UINT32 FileLength,
377 IN CHAR *Password,
378 IN VOID (*DataProgressProc)(VOID),
379 IN UINT32 DataProgessSteps,
380 OUT STATUS *FWU_Status
381 )
382 /*++
383
384 Routine Description:
385
386 Start the update process by asking the ME FW Update client
387 to allocate a buffer for the image. Note that the ME does not update the flash until
388 the FWU_END message is received.
389
390 If the current ME Flash image is password protected, then that password is required to unlock
391 the update process
392
393 Because the process of downloading the image is time consuming, a callback is provided for each
394 chunk of data sent to the ME FW Update client. If desired, the caller can specify the number of steps
395 that the total data send will have (e.g. 100 means a total of 100 callbacks for the entire duration). The
396 number of steps supplied will be divided by the total result of (FileLength / Chunksize) + 1.
397
398 Arguments:
399
400 UINT8 pointer to FW Update Image
401 UINT32 FW Update image length
402 CHAR16 pointer to password (if no password then NULL)
403 VOID pointer to callback function (if no callback then NULL)
404 UINT32 callback steps (1 means each packet sent will trigger a callback)
405 UINT32 pointer to ME FW Update Client return status
406
407 Returns:
408
409 EFI_STATUS
410
411 --*/
412 ;
413
414 EFI_STATUS
415 EndUpdate (
416 IN VOID (*EndProgressProc)(VOID),
417 IN UINT32 EndProgressSteps,
418 OUT STATUS *FWU_Status
419 )
420 /*++
421
422 Routine Description:
423
424 Send the FWU_END message to the ME after a successful data download.
425 This operation will request the ME to validate the image and update the
426 flash. Depending on flash speed, the operation may take serveral minutes
427 to finish. Be patient...
428
429 Because the process of updating the image is time consuming, a callback is provided each delay (5 seconds)
430 that occurs waiting for the ME FW Update client to respond. If desired, the caller can specify a number of timeouts before
431 a callback (e.g. 1 means send wait 5 seconds then invoke the callback routine).
432
433 Arguments:
434
435 VOID pointer to callback function (if no callback then NULL)
436 UINT32 callback ratio (1 means wait 5 seconds and then trigger a callback)
437 UINT32 pointer to ME FW Update Client return status
438
439 Returns:
440
441 EFI_STATUS
442
443 --*/
444 ;
445
446 EFI_STATUS
447 GetFwFlashVersion(
448 IN FWVersion *fwVersion
449 )
450 /*++
451
452 Routine Description:
453
454 Get the FW version of the currently running ME FW
455
456 NOTE: A connection to the client is required before this routine is
457 executed.
458
459 Arguments:
460
461 FWVersion pointer to FW Flash version
462
463 Returns:
464
465 EFI_STATUS
466
467 --*/
468 ;
469 unsigned int FwUpdateCheckPowerSource(
470 FWUPD_POWER_SOURCE* PowerState);
471
472 UINT32 GetExtendedIpuPartitionAttributes(
473 FWU_GET_IPU_PT_ATTRB_MSG_REPLY* FwuGetIpuAttrbMsgInfo,
474 UINT32 updateOp);
475
476 UINT32 GetIpuPartitionAttributes(FWU_GET_IPU_PT_ATTRB_MSG_REPLY* FwuGetIpuAttrbMsgInfo);
477
478 #endif
479
_FWUPD_POWER_SOURCE
_FWUPD_POWER_SOURCE
Definition: FWUpdateLib.h:94
FWUPD_POWER_SOURCE_DC
DC Power source.
Definition: FWUpdateLib.h:97
FWU_DATA_MESSAGE
FWU_DATA_MESSAGE - data fragment of the image.
Definition: FWUpdateLib.h:142
FWU_GET_INFO_MESSAGE
FWU_GET_INFO_MESSAGE - get version.
Definition: FWUpdateLib.h:130
FWUPD_POWER_SOURCE_AC
AC Power source.
Definition: FWUpdateLib.h:96
FWUPD_POWER_SOURCE_UNKOWN
Unable to determine power source.
Definition: FWUpdateLib.h:98
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Facs.h Source File

  • Acpi
  • AcpiTables
  • Facs
Facs.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Firmware ACPI Control
3 Structure (FACS). All changes to the FACS contents should be done
4 in this file.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 1999 - 2017 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _FACS_H_
38 #define _FACS_H_
39
40 //
41 // Statements that include other files
42 //
43
44 #include <IndustryStandard/Acpi.h>
45
46 //
47 // FACS Definitions
48 //
49
50 #define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000
51 #define EFI_ACPI_GLOBAL_LOCK 0x00000000
52
53 //
54 // Firmware Control Structure Feature Flags are defined in AcpiX.0.h
55 //
56 #define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000
57
58 #define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000
59
60 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Fadt6.1.h Source File

  • Acpi
  • AcpiTables
  • Fadt
Fadt6.1.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Fixed ACPI Description Table
3 (FADT). All changes to the FADT contents should be done in this file.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2017 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _FADT_H_
37 #define _FADT_H_
38
39 //
40 // Statements that include other files
41 //
42
43 #include <IndustryStandard/Acpi.h>
44
45 #include "Register/PchRegsPmcCnl.h"
46
47 //
48 // FADT Definitions
49 //
50 #ifndef EFI_ACPI_OEM_FADT_REVISION
51 #define EFI_ACPI_OEM_FADT_REVISION 0x00000000
52 #endif
53
54 //
55 // For ACPI 1.0 support
56 //
57 #define EFI_ACPI_INT_MODEL 0x00
58 /*
59 1 Desktop
60 2 Mobile
61 3 Workstation
62 4 Enterprise Server
63 5 SOHO Server
64 6 Appliance PC
65 7 Performance Server
66 */
67 #define EFI_ACPI_PREFERRED_PM_PROFILE 0x02
68 #define EFI_ACPI_SCI_INT 0x0009
69 #define EFI_ACPI_SMI_CMD 0x000000B2
70 #define EFI_ACPI_S4_BIOS_REQ 0xF2
71 #define EFI_ACPI_PSTATE_CNT 0x00
72 #define EFI_ACPI_GPE1_BASE 0x10
73 #define EFI_ACPI_CST_CNT 0x0
74 #define EFI_ACPI_P_LVL2_LAT 101
75 #define EFI_ACPI_P_LVL3_LAT 1001
76 #define EFI_ACPI_FLUSH_SIZE 0x0000
77 #define EFI_ACPI_FLUSH_STRIDE 0x0000
78 #define EFI_ACPI_DUTY_OFFSET 0x01
79 #define EFI_ACPI_DUTY_WIDTH 0x03
80 #define EFI_ACPI_DAY_ALRM 0x0D
81 #define EFI_ACPI_MON_ALRM 0x00
82 #define EFI_ACPI_CENTURY 0x32
83
84 //
85 // IA-PC Boot Architecture Flags, see ACPI 6.1 table specification and Acpi61.h
86 // We should not use EFI_ACPI_6_1_8042 for legacy free platform, or XP reset fail. No impact to mobile.
87 //
88 #define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_1_LEGACY_DEVICES)
89
90 //
91 // Fixed Feature Flags, see ACPI 2.0 table specification and Acpi2_0.h
92 //
93 #define EFI_ACPI_FIXED_FEATURE_FLAGS (\
94 EFI_ACPI_6_1_USE_PLATFORM_CLOCK | \
95 EFI_ACPI_6_1_WBINVD | \
96 EFI_ACPI_6_1_DCK_CAP | \
97 EFI_ACPI_6_1_RTC_S4 | \
98 EFI_ACPI_6_1_SLP_BUTTON | \
99 EFI_ACPI_6_1_PROC_C1 | \
100 EFI_ACPI_6_1_RESET_REG_SUP \
101 )
102
103 //
104 // PM1A Event Register Block Generic Address Information
105 //
106 #define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
107 #define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
108 #define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
109 #define EFI_ACPI_PM1A_EVT_BLK_ADDRESS FixedPcdGet16 (PcdAcpiBaseAddress)
110
111 //
112 // PM1B Event Register Block Generic Address Information
113 //
114 #define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
115 #define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
116 #define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
117 #define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x0000000000000000
118
119 //
120 // PM1A Control Register Block Generic Address Information
121 //
122 #define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
123 #define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
124 #define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
125 #define EFI_ACPI_PM1A_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
126
127 //
128 // PM1B Control Register Block Generic Address Information
129 //
130 #define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
131 #define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
132 #define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
133 #define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x0000000000000000
134
135 //
136 // PM2 Control Register Block Generic Address Information
137 //
138 #define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
139 #define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
140 #define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
141 #define EFI_ACPI_PM2_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50)
142
143 //
144 // Power Management Timer Control Register Block Generic Address
145 // Information
146 //
147 #define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
148 #define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
149 #define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
150 #define EFI_ACPI_PM_TMR_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
151
152 //
153 // General Purpose Event 0 Register Block Generic Address
154 // Information
155 //
156 #define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
157 #define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0x100
158 #define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
159 #define EFI_ACPI_GPE0_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + R_CNL_PCH_ACPI_IO_GPE0_STS_31_0)
160
161 //
162 // General Purpose Event 1 Register Block Generic Address
163 // Information
164 //
165 #define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
166 #define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x00
167 #define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x00
168 #define EFI_ACPI_GPE1_BLK_ADDRESS 0x0000000000000000
169
170 //
171 // Reset Register Generic Address Information
172 //
173 #define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_1_SYSTEM_IO
174 #define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
175 #define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
176 #define EFI_ACPI_RESET_REG_ADDRESS 0x0000000000000CF9
177 #define EFI_ACPI_RESET_VALUE 0x06
178
179 //
180 // Number of bytes decoded by PM1 event blocks (a and b)
181 //
182 #define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
183
184 //
185 // Number of bytes decoded by PM1 control blocks (a and b)
186 //
187 #define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
188
189 //
190 // Number of bytes decoded by PM2 control block
191 //
192 #define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)
193
194 //
195 // Number of bytes decoded by PM timer block
196 //
197 #define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
198
199 //
200 // Number of bytes decoded by GPE0 block
201 //
202 #define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)
203
204 //
205 // Number of bytes decoded by GPE1 block
206 //
207 #define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)
208
209 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: FirwmareConfigurations.h Source File

FirwmareConfigurations.h
Go to the documentation of this file.
1 /** @file
2 This header file provides definitions of firmware configuration.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _FIRMWARE_CONFIGURATION_H_
36 #define _FIRMWARE_CONFIGURATION_H_
37
38 typedef enum {
39 FwConfigDefault = 0,
40 FwConfigProduction,
41 FwConfigTest,
42 FwConfigMax
43 } FW_CONFIG;
44
45 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: FspPolicyInitLib.h Source File

  • Library
FspPolicyInitLib.h
Go to the documentation of this file.
1 /** @file
2 Function prototype of FspPolicyInitLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _FSP_POLICY_INIT_LIB_H_
36 #define _FSP_POLICY_INIT_LIB_H_
37
38 #include <FspEas.h>
39 #include <FspmUpd.h>
40 #include <FspsUpd.h>
41
42 VOID
43 EFIAPI
44 FspPolicyInitPreMem (
45 IN FSPM_UPD *FspmUpdDataPtr
46 );
47
48 VOID
49 EFIAPI
50 FspPolicyInit (
51 IN OUT FSPS_UPD *FspsUpd
52 );
53
54 #endif // _FSP_POLICY_INIT_LIB_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Fwu_Common.h Source File

  • Library
Fwu_Common.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2005 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _FWU_COMMON_H
35 #define _FWU_COMMON_H
36
37 #include "ver.h"
38 #include "mkhi_hdrs.h"
39
40 typedef unsigned int STATUS;
41
42 //#define FW_UPDATE_STATUS unsigned int
43
44 #define BLACK_LIST_ENTRY_MAX 10
45 #define FWU_PWD_MAX_SIZE 32
46 #define MAXIMUM_IPU_SUPPORTED 4
47 #define ACTUAL_IPU_SUPPORTED 3
48 #define HASH_SHA256_LEN 32
49
50 #define FPT_PARTITION_NAME_UPDT 0x54445055
51 #define FPT_PARTITION_NAME_ISHC 0x43485349
52
53 // Safe Update States
54 #define SU_STATE0_NO_UPDATE 0
55 #define SU_STATE1_COPY_FT_TO_NFTP_BEGIN 1
56 #define SU_STATE1_COPY_FT_TO_NFTP_END 2
57 #define SU_STATE2_COPY_ALL_BEGIN 3
58 #define SU_STATE2_COPY_ALL_END 4
59 #define SU_STATE3_CONFIRM_LIVE_PING_BEGIN 5
60 #define SU_STATE3_CONFIRM_LIVE_PING_END 6
61 #define SU_ROLLBACK1_RECOVER_NFT_BEGIN 7
62 #define SU_ROLLBACK1_RECOVER_NFT_END 0 // Back to NO_UPDATE
63 #define SU_ROLLBACK2_RECOVER_ALL_BEGIN 8
64 //#define SU_FORCE_ROLLBACK2_RECOVER_ALL 9
65 #define SU_ROLLBACK2_RECOVER_ALL_END 0 // Back to NO_UPDATE
66
67 // From FwuHeciMsgs.h
68 /* HMRFPO_GETSTATUS_CMD_STATUS and HMRFPOState Values*/
69 // These are already included in KabyLakeSiliconPkg\Me\include\Mkhi_msgs.h
70 //#define HMRFPO_DISABLED 0
71 //#define HMRFPO_LOCKED 1
72 //#define HMRFPO_ENABLED 2
73
74 /** \addtogroup fwupdate
75 <b>HMRFPO_ENABLE</b> Data structure:
76 \li \ref _FWUPDATE_HMRFPO_ENABLE_DATA
77 \li \ref _FWUPDATE_HMRFPO_ENABLE
78 \li \ref _FWUPDATE_HMRFPO_ENABLE_ACK_DATA
79 \li \ref _FWUPDATE_HMRFPO_ENABLE_ACK
80 */
81
82 // ***************************************
83 /* HMRFPO Related Enums */
84 // ***************************************
85 /** \addtogroup fwupdate
86 HMRFPO_ENABLE_CMD_ACK_STATUS codes:
87 \code
88 #define HMRFPO_ENABLE_SUCCESS 0
89 #define HMRFPO_LOCKED 1
90 #define HMRFPO_NVAR_FAILURE 2
91 #define HMRFPO_TDT_FAILURE 3
92 #define HMRFPO_EOP_FAILURE 4
93 #define HMRFPO_ENABLE_UNKNOWNFAIL 5
94 \endcode
95 */
96
97 /* HMRFPO_ENABLE_CMD_ACK_STATUS */
98 //#define HMRFPO_ENABLE_SUCCESS 0
99 //#define HMRFPO_LOCKED 1
100 //#define HMRFPO_NVAR_FAILURE 2
101 #define HMRFPO_TDT_FAILURE 3
102 #define HMRFPO_EOP_FAILURE 4
103 //#define HMRFPO_ENABLE_UNKNOWNFAIL 5
104
105
106 /** \addtogroup fwupdate
107 <b>HMRFPO_LOCK</b> Data structure:
108 \li \ref _FWUPDATE_HMRFPO_LOCK
109 \li \ref _FWUPDATE_HMRFPO_LOCK_ACK_DATA
110 \li \ref _FWUPDATE_HMRFPO_LOCK_ACK
111 */
112
113 /** \addtogroup fwupdate
114 HMRFPO_LOCK_CMD_ACK_STATUS codes:
115 \code
116 #define HMRFPO_LOCK_SUCCESS 0
117 #define HMRFPO_LOCK_MANUF_MODE_FAIL 1
118 \endcode
119 */
120
121 /* HMRFPO_LOCK_CMD_ACK_STATUS */
122 //#define HMRFPO_LOCK_SUCCESS 0
123 #define HMRFPO_LOCK_MANUF_MODE_FAIL 1
124
125 #if 1
126 /**
127 * @brief The operation completed successfully.
128 */
129 #define STATUS_SUCCESS 0x0
130
131 //
132 //STATUS_SIZE_ERROR
133 // The size of the specified object (memory pool, stack, message queue,
134 // etc.) is invalid.
135 //
136 #define STATUS_SIZE_ERROR 0x5
137
138 //
139 //STATUS_NOT_AVAILABLE
140 // An attempt to remove a mutex on which a thread is suspended has been
141 // attempted.
142 //
143 #define STATUS_NOT_AVAILABLE 0x1D
144
145 //
146 //STATUS_NOT_FOUND
147 // The requested item could not be found.
148 //
149 #define STATUS_NOT_FOUND 0x81
150
151 //
152 //STATUS_INVALID_HANDLE
153 // The provided handle does not exist.
154 //
155 #define STATUS_INVALID_HANDLE 0x83
156
157 //
158 //STATUS_INVALID_ACCESS
159 // An attempt was made to access an inaccessible or unavailable object.
160 //
161 #define STATUS_INVALID_ACCESS 0x84
162
163 //
164 //STATUS_INVALID_PARAMS
165 // One or more parameters are invalid.
166 //
167 #define STATUS_INVALID_PARAMS 0x85
168
169 //
170 //STATUS_NOT_READY
171 // The h/w device is not ready.
172 //
173 #define STATUS_NOT_READY 0x88
174
175 //
176 //STATUS_NOT_SUPPORTED
177 // The function, message or request is not recognized or supported.
178 //
179 #define STATUS_NOT_SUPPORTED 0x89
180
181 //
182 //STATUS_DEVICE_ERROR
183 // The h/w device reported an error while attempting the operation.
184 //
185 #define STATUS_DEVICE_ERROR 0x8B
186
187 //
188 //STATUS_INVALID_ADDRESS
189 // The address provided in invalid.
190 //
191 #define STATUS_INVALID_ADDRESS 0x8C
192
193 //
194 //STATUS_INVALID_COMMAND
195 // The requested command is unrecognized or invalid.
196 //
197 #define STATUS_INVALID_COMMAND 0x8D
198
199 //
200 //STATUS_STACK_OVERFLOW
201 // The request caused a stack overflow.
202 //
203 #define STATUS_STACK_OVER_FLOW 0x8E
204
205 //
206 //STATUS_BUFFER_TOO_SMALL
207 // The provided buffer is too small to hold the requested data.
208 //
209 #define STATUS_BUFFER_TOO_SMALL 0x8F
210
211 //
212 //STATUS_INVALID_BUFFER
213 // The buffer was not the proper size for the request.
214 //
215 #define STATUS_INVALID_BUFFER 0x91
216
217 //
218 //STATUS_NO_RESPONSE
219 // No response was received from the requested target.
220 //
221 #define STATUS_NO_RESPONSE 0x92
222
223 //
224 //STATUS_TIMED_OUT
225 // The device or object timed out and was unable to complete the request.
226 //
227 #define STATUS_TIMED_OUT 0x93
228
229 //
230 //STATUS_NOT_STARTED
231 // The requested operation could not be started. For protocols, this
232 // error indicates the protocol has not been started.
233 //
234 #define STATUS_NOT_STARTED 0x94
235
236 //
237 //STATUS_ALREADY_STARTED
238 // The requested operation has already been started.
239 // - For protocols, this error
240 // indicates the protocol has already been started.
241 // - For Policy Manager this error means
242 // that the MKHI group ID is already registered.
243 // For FW update, we only allow one process to do the update at a time, this means error
244 // case where FW update is already in progress, the current process will have to try later.
245 //
246 #define STATUS_ALREADY_STARTED 0x95
247
248 //
249 //STATUS_OUT_OF_RESOURCES
250 // Insufficient resources to perform the request. Used by components operating
251 // in non-blocking mode. A caller will be returned this error when a component
252 // does not have enough resources like command buffers, PRDs etc... to entertain
253 // a new request.
254 //
255 #define STATUS_OUT_OF_RESOURCES 0x9D
256
257 //
258 //STATUS_FAILURE
259 // A unknown error encountered while performing a requested transaction.
260 //
261 #define STATUS_FAILURE 0x9E
262
263 //
264 //STATUS_IMAGE_INVALID
265 // The FW Update image content is invalid.
266 #define STATUS_IMAGE_INVALID 0xA5
267
268 // STATUS_UPDATE_MISMATCH_HW_SKU
269 // Indicates that there is a mismatch between the current HW SKU and the
270 // one in the new image.
271 #define STATUS_UPDATE_MISMATCH_HW_SKU 0xB6
272
273 // STATUS_UPDATE_MISMATCH_FW_SKU
274 // Indicates that there is a mismatch between the current FW SKU and the
275 // one in the new image.
276 #define STATUS_UPDATE_MISMATCH_FW_SKU 0xB7
277
278 // STATUS_UPDATE_MISMATCH_VERSION
279 // Indicates that there is a mismatch between the current FW version and the
280 // one in the new image.
281 #define STATUS_UPDATE_MISMATCH_VERSION 0xB8
282
283 //
284 //STATUS_OUT_OF_MEMORY
285 // This error can be returned for the following reasons:
286 // 1.Attempt to allocate memory and no memory is available
287 // 2.Attempt to free a memory block on which a thread is suspended
288 // NOTE: This value is the same a as STATUS_START_ERROR.
289 //
290 #define STATUS_OUT_OF_MEMORY 0xBE
291
292 // STATUS for FWU kernel between 0x200 to 0x2FF
293 #define FW_UPDATE_STATUS UINT32
294
295 #define NO_UPDATE 0
296 #define STATUS_UPDATE_SUCCESS 0x0 // Zero for sucess anything else is consider failures
297 #define STATUS_UPDATE_IMAGE_INVALID 0x201
298 #define STATUS_UPDATE_INTEGRITY_FAILURE 0x202
299 #define STATUS_UPDATE_SKU_MISMATCH 0x203
300 #define STATUS_UPDATE_FW_VERSION_MISMATCH 0x204
301 #define STATUS_UPDATE_GENERAL_FAILURE 0x205
302 #define STATUS_UPDATE_OUT_OF_RESOURCES 0x206
303 #define STATUS_UPDATE_AUDIT_POLICY_FAILURE 0x207
304 #define STATUS_UPDATE_ERROR_CREATING_FT 0x208
305 #define STATUS_UPDATE_SAL_NOTIFICATION_ERROR 0x209
306 #define STATUS_UPDATE_IMG_LOADING 0x20A
307 #define STATUS_UPDATE_IMG_AUTHENTICATING 0x20B
308 #define STATUS_UPDATE_IMG_PROCESSING 0x20C
309 #define STATUS_UPDATE_CREATING_FT 0x20D
310 #define STATUS_UPDATE_UPDATING_CODE 0x20E
311 #define STATUS_UPDATE_UPDATING_NFT 0x20F
312 #define STATUS_UPDATE_FLASH_CODE_PARTITION_INVALID 0x210
313 #define STATUS_UPDATE_FLASH_NFT_PARTITION_INVALID 0x211
314 #define STATUS_UPDATE_ILLEGAL_IMAGE_LENGTH 0x212
315 #define STATUS_UPDATE_NOT_READY 0x213
316
317 #define STATUS_UPDATE_HOST_RESET_REQUIRED 0x214
318 #define STATUS_INVALID_GLUT 0x215
319 #define STATUS_INVALID_OEM_ID 0x216
320
321 // New for CPT add below here
322 #define STATUS_UPDATE_IMAGE_BLACKLISTED 0x217 //New SPT
323 #define STATUS_UPDATE_IMAGE_VERSION_HISTORY_CHECK_FAILURE 0x218 //New SPT
324 #define STATUS_UPDATE_DOWNGRADE_VETOED 0x219
325 #define STATUS_UPDATE_WRITE_FILE_FAILURE 0x22A
326 #define STATUS_UPDATE_READ_FILE_FAILURE 0x22B
327 #define STATUS_UPDATE_DELETE_FILE_FAILURE 0x22C
328 #define STATUS_UPDATE_PARTITION_LAYOUT_NOT_COMPATIBLE 0x22D // FW Update is not possible due to partition move //New SPT - partition sizes
329 #define STATUS_DOWNGRADE_NOT_ALLOWED_DATA_MISMATCHED 0x22E
330 #define STATUS_UPDATE_FW_UPDATE_IS_DISABLED 0x22F
331 #define STATUS_UPDATE_PASSWORD_NOT_MATCHED 0x230
332 #define STATUS_UPDATE_PASSWORD_EXCEED_MAXIMUM_RETRY 0x231
333 #define STATUS_UPDATE_INRECOVERY_MODE_RESTRICT_UPDATE_TO_ATTEMPTED_VERSION 0x232 // They have to update with the same image that they started with.
334
335
336 // New for Partial FW update
337 #define STATUS_UPDATE_UPV_VERSION_MISMATCHED 0x233 // UPV version mismatched update is not allow
338 #define STATUS_UPDATE_INSTID_IS_NOT_EXPECTED_ID 0x234 // Reject update, instance ID sent is not one of expected ID
339 #define STATUS_UPDATE_INFO_NOT_AVAILABLE 0x235 // While in the middle of update IPU attrib info will bot be available
340 #define STATUS_UPDATE_REJ_IPU_FULL_UPDATE_NEEDED 0x236 // Can't do IPU update while we are in Full recovery mode.
341 #define STATUS_UPDATE_IPU_NAMEID_NOT_FOUND 0x237 // IPU name not found when compare with UPV extension
342
343 #define STATUS_UPDATE_RESTORE_POINT_INVALID 0x238
344 #define STATUS_UPDATE_RESTORE_POINT_VALID_BUT_NOT_LATEST 0x239
345 #define STATUS_UPDATE_RESTORE_POINT_OPERATION_NOT_ALLOWED 0x23A
346 #define STATUS_DOWNGRADE_NOT_ALLOWED_SVN_RESTRICTION 0x23B
347 #define STATUS_DOWNGRADE_NOT_ALLOWED_VCN_RESTRICTION 0x23C
348 #define STATUS_INVALID_SVN 0x23D
349 #define STATUS_UPDATE_OUT_OF_SVN_RESOURCES 0x23E
350 #define STATUS_UPDATE_REJECT_RESTORE_POINT_REQUEST_FLASH_IN_RECOVERY 0x23F
351 #define STATUS_UPDATE_REJECTED_BY_UPDATE_POLICY 0x240
352 #define STATUS_UPDATE_REJECTED_INCOMPATIBLE_TOOL_USAGE 0x241
353 #define STATUS_UPDATE_REJECTED_CROSSPOINT_UPDATE_NOT_ALLOWED 0x242
354 #define STATUS_UPDATE_REJECTED_CROSSHOTFIX_UPDATE_NOT_ALLOWED 0x243
355 #define STATUS_UPDATE_REJECTED_CURRENT_FW_NOT_ELIGIBLE_FOR_UPDATE 0x244
356 #define STATUS_UPDATE_REJECTED_WRONG_UPDATE_OPERATION 0x245
357 #define STATUS_UPDATE_REJECTED_WRONG_UPDATE_IMAGE_FOUND 0x246
358 #define STATUS_UPDATE_REJECTED_IFR_UPDATE_NOT_ALLOWED 0x247
359 #define STATUS_UPDATE_FAILURE_OCCURRED_DURING_ROLLBACK 0x248
360
361 // New for SPT add below here
362 #define STATUS_UPDATE_FW_ENGINEERING_VERSION_NOT_ALLOWED 0x249
363 #define STATUS_UPDATE_FW_ENGINEERING_VERSION_REQUIRED 0x24A
364 #define STATUS_UPDATE_FW_RESTORE_HISTORY_NOT_FOUND 0x24B
365 #define STATUS_UPDATE_API_VERSION_MISMATCH 0x24C
366
367
368 //.........................................................................
369 //......................................................................... // Reserve for FWU usage
370 #define STATUS_UPDATE_LAST_STATUS_CODE 0x2FF
371
372 // means internal FW operation errors
373 //#define STATUS_UPDATE_UNKNOWN = 0xFFFFFFFF
374
375
376 #endif
377
378
379 #pragma pack(1)
380 // From FwuHeciMsgs.h
381 // MKHI CMD Defs
382 typedef enum
383 {
384 FWUPDATE_HMRFPO_ENABLE_CMD = 0x01,
385 FWUPDATE_HMRFPO_LOCK_CMD,
386 FWUPDATE_HMRFPO_GETSTATUS_CMD,
387 FWUPDATE_HMRFPO_DISABLE_CMD,
388
389 FWUPDATE_HMRFPO_ENABLE_CMD_ACK = 0x81,
390 FWUPDATE_HMRFPO_LOCK_CMD_ACK,
391 FWUPDATE_HMRFPO_GETSTATUS_CMD_ACK,
392 FWUPDATE_HMRFPO_DISABLE_CMD_ACK,
393
394 } FWUPDATE_HMRFPO_MKHI_COMMANDS;
395
396 // ***************************************
397 /* Fixed address MKHI FWUPDATE messaging commands Group ID 0x06 for FW update*/
398 // ***************************************
399 typedef enum
400 {
401 FWUPDATE_RESUME_CMD = 0x01,
402 FWUPDATE_QUERY_STATUS_CMD,
403 FWUPDATE_FORCE_SAFE_BOOT_CMD,
404
405 FWUPDATE_RESUME_CMD_ACK = 0x81,
406 FWUPDATE_QUERY_STATUSCMD_ACK,
407 FWUPDATE_FORCE_SAFE_BOOT_ACK,
408
409 } FWUPDATE_MKHI_COMMANDS;
410
411 // From MeTypes.h
412 // Enums for the FLASH image possible states and Update states.
413 //
414 typedef enum _FLASH_IMAGE_STATUS
415 {
416 IMAGE_VALID = 0,
417 IMAGE_CODE_INVALID,
418 IMAGE_NFT_INVALID,
419 IMAGE_CREATING_FT, // Make backup of FT, or copy FT to NFTP partition for IFR
420 IMAGE_UPDATING_CODE,
421 IMAGE_UPDATING_NFT,
422
423 IMAGE_STATUS_UNKNOWN = 0xFFFFFFFF
424
425 } FLASH_IMAGE_STATUS;
426
427 typedef enum _FWU_HECI_MSG_STATUS{
428 FWU_NOT_READY,
429 FWU_ILLEGAL_LENGTH, //allocate image buffer
430 } FWU_HECI_MSG_STATUS;
431
432 typedef enum _BLACK_LIST_EXPRESSION_TYPES
433 {
434 BLE_EMPTY = 0,
435 BLE_EQ,
436 BLE_LTE,
437 BLE_GTE,
438 BLE_RANGE
439 }BLACK_LIST_EXPRESSION_TYPES;
440
441 typedef enum _FWU_OPERATION
442 {
443 FWU_FULL_UPDATE_OPERATION = 0,
444 FWU_IPU_UPDATE_OPERATION
445 }FWU_OPERATION;
446
447 typedef enum _FWU_ENVIRONMENT
448 {
449 FWU_ENV_MANUFACTURING = 0, // Manufacturing update
450 FWU_ENV_IFU, // Independent Firmware update
451 }FWU_ENVIRONMENT;
452
453 typedef enum _FWU_ROLLBACK_MODE
454 {
455 FWU_ROLLBACK_NONE = 0, // No rollback
456 FWU_ROLLBACK_1, // Rollback 1 procedure
457 FWU_ROLLBACK_2, // Rollback 2 procedure
458 }FWU_ROLLBACK_MODE;
459
460 typedef struct _FWU_INFO_FLAGS
461 {
462 unsigned int RecoveryMode:2; // 0 = No recovery; 1 = Full Recovery Mode,2 = Partial Recovery Mode
463 unsigned int IpuNeeded:1; // IPU_NEEDED bit, if set we are in IPU_NEEDED state.
464 unsigned int FwInitDone:1; // If set indicate FW is done initialized
465 unsigned int FwuInProgress:1; // If set FWU is in progress, this will be set for IFU update as well
466 unsigned int SuInprogress:1; // If set IFU Safe FW update is in progress.
467 unsigned int NewFtTestS:1; // If set indicate that the new FT image is in Test Needed state (Stage 2 Boot)
468 unsigned int SafeBootCnt:4; // Boot count before the operation is success
469 unsigned int FsbFlag:1; // Force Safe Boot Flag, when this bit is set, we'll boot kernel only and go into recovery mode
470
471 //////////////////////////////////////////////////////
472 // These fields below are important for FWU tool.
473 //////////////////////////////////////////////////////
474 unsigned int LivePingNeeded:1; // Use for IFU only, See Below
475 // FWU tool needs to send Live-Ping or perform querying to confirm update successful.
476 // With the current implementation when LivePingNeeded is set,
477 // Kernel had already confirmed it. No action from the tool is needed.
478 unsigned int ResumeUpdateNeeded:1; // Use for IFU only, If set FWU tool needs to resend update image
479 unsigned int RollbackNeededMode:2; // FWU_ROLLBACK_NONE = 0, FWU_ROLLBACK_1, FWU_ROLLBACK_2
480 // If not FWU_ROLLBACK_NONE, FWU tool needs to send restore_point image.
481 unsigned int ResetNeeded:2; // When this field is set to ME_RESET_REQUIRED, FW Kernel will
482 // perform ME_RESET after this message. No action from the tool is needed.
483 unsigned int SuState:4; // See possible values below
484 unsigned int RecoveryCause:2; // IMAGE_CODE_INVALID = 1; IMAGE_NFT_INVALID = 2;
485 unsigned int Reserve:8;
486 }FWU_INFO_FLAGS;
487
488
489 typedef struct _BLACK_LIST_ENTRY
490 {
491 unsigned short ExpressionType;
492 unsigned short MinorVer;
493 unsigned short HotfixVer1;
494 unsigned short BuildVer1;
495 unsigned short HotfixVer2;
496 unsigned short BuildVer2;
497 }BLACK_LIST_ENTRY;
498
499
500 //Data
501 typedef struct _FWU_HECI_MESSAGE_DATA
502 {
503 unsigned int Length;
504 unsigned char Reserved[3];
505 unsigned char Data[1];
506 } FWU_HECI_MESSAGE_DATA;
507
508
509 typedef struct _PT_ATTRB
510 {
511 unsigned int PtNameId; // HW_COMP_HDR_STRUCTID_WCOD 0x244f4357 OR
512 // HW_COMP_HDR_STRUCTID_LOCL 0x4C434F4C OR
513 // HW_COMP_HDR_STRUCTID_MDMV 0x564D444D
514 unsigned int LoadAddress; // Load Address of the IPU
515 VERSION FwVer; // FW version from IUP Manifest
516 unsigned int CurrentInstId; // Current Inst ID from flash, 0 indicate invalid ID
517 unsigned int CurrentUpvVer; // Upper sig 16 bits are Major Version.
518 unsigned int ExpectedInstId;// Expected Inst ID that need to be updated to
519 unsigned int ExpectedUpvVer;// Upper sig 16 bits are Major Version.
520 unsigned int Resv[4];
521 }PT_ATTRB;
522 C_ASSERT(sizeof(PT_ATTRB) == 48);
523
524
525 typedef struct _RESTORE_POINT_IPU_ATTR
526 {
527 unsigned int PartitionId; // WCOD, LOCL, MDMV
528 VERSION FwVer; // FW version from IUP Manifest
529 unsigned int CurrentInstId; // Current Inst ID from flash, 0 indicate invalid ID
530 unsigned int CurrentUpvVer; // Upper sig 16 bits are Major Version.
531 }RESTORE_POINT_IPU_ATTR;
532 C_ASSERT(sizeof(RESTORE_POINT_IPU_ATTR) == 20);
533
534
535 typedef struct _OEM_UUID
536 {
537 unsigned int Data1;
538 unsigned short Data2;
539 unsigned short Data3;
540 unsigned char Data4 [ 8 ];
541 } OEM_UUID;
542
543
544 typedef struct _FWU_RESTORE_POINT_INFO
545 {
546 unsigned char HashCalculated[HASH_SHA256_LEN];
547 VERSION FwVer; // FT Firmware version
548 RESTORE_POINT_IPU_ATTR RestAttr[ACTUAL_IPU_SUPPORTED];
549 unsigned int RESERVE;
550 }FWU_RESTORE_POINT_INFO;
551 C_ASSERT(sizeof(FWU_RESTORE_POINT_INFO) == 104);
552
553
554 typedef struct _UPDATE_VERSION_INFO
555 {
556 VERSION Version;
557 unsigned char History[4];
558 unsigned int CriticalHotfixDescriptor;
559
560 }UPDATE_VERSION_INFO;
561
562
563 typedef struct _UPDATE_FLAGS
564 {
565 unsigned int RestorePoint:1; // If set indicate restore point
566 unsigned int RestartOperation:1; // If set indicate restart operation, like lost hard drive etc...
567 unsigned int UserRollback:1; // indicates user has initiated a rollback
568 unsigned int Reserve:29; //
569 }UPDATE_FLAGS;
570
571
572 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////
573 ///////////////////// ME FWU related Information that will be provided by discovery DLL /////////////////////////
574 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////
575
576 // ME_FWU_INFO General information related to FW update
577 // Few basic rules:
578 // Do not delete member, allow add new member only to the end of this struct.
579 // The producer(Kernel) will only copy up to the size of the consumer StructSize. Consumer must set the StructSize.
580 // TBD each field need to initialize to invalid pattern? In the case that we could not get
581 // the information.
582 typedef struct _ME_FWU_INFO
583 {
584 unsigned int StructSize; // SizeOfThisStruct
585 unsigned int ApiVer; // Version of this API Major in upper 16 bits
586 VERSION FtpVer; // QWORD Major(15:0), Minor(31:16), HotFix(47:32),
587 // Build#(63:48)
588 VERSION NftpVer; // QWORD Major(15:0), Minor(31:16), HotFix(47:32),
589 // Build#(63:48)
590 unsigned int ChipsetVer; // PCH version
591 unsigned int GlobalChipId; // Global chip identification
592 unsigned char SystemManufacturer[32]; // Ascii of char string
593
594 unsigned int MebxFwuConfig; // 0= Disable, 1 = enable , 2 = PW protected
595 unsigned int HwSku; // MEFWCAPS_SKU HW feature set or not
596 unsigned int FwSku; // MEFWCAPS_SKU FW feature set from
597 // SkuTable fuse or not fuse
598 unsigned int LastFwUpdateStatus; // Last FW update status
599 unsigned int DataFormatVer; // Data format version Major(31:16), Minor (15:0). Only Major is used
600 unsigned int SvnVer; // Security version number
601 unsigned int VcnVer; // Version Control Number
602 // This field is currently not used
603 /* Warning *********************************************************************/
604 // Do not delete member, allow add new member only to the end of this struct.
605 /* Warning *********************************************************************/
606 VERSION MebxVer; // MEBX version
607 FWU_INFO_FLAGS FwuInfoFlags; // FWU information flags
608 unsigned int PlatformAttributes; // ME_PLATFORM_TYPE Contains Platform Attributes:
609 // CpuType,platform type, superSku,etc. See ME_PLATFORM_TYPE
610 OEM_UUID OemId; // Famous OEM_ID
611 unsigned short MeFwSize; // Size of FW image in multiple of .5MB
612 unsigned char History[4]; // Keep track of version tree history
613 // Minor0Predecessor, Minor1Predecessor, Minor2Predecessor, Minor3Predecessor
614 // FWU will check to see if the update image has the same predecessor with the
615 // one that is already in the flash before allow the update.
616 unsigned int CriticalHotfixDescriptor; // Each bit signify a particular Critical Hot Fix
617 unsigned int FwuIFRAllowedRule; // 1 Aloowed, 0 Disallowed
618 FWU_RESTORE_POINT_INFO LastRestorePointInfo; //Replace old unsigned int Reserved[29];
619 unsigned int FwStatus1; // Firmware status register 1, use for debugging
620 unsigned int FwStatus2; // Firmware status register 2, use for debugging
621 unsigned int Reserve1; // //
622 unsigned short NumSupportedIup; // Number of IPUs actually supported, use this number to traverse IupEntry
623 PT_ATTRB IupEntry [MAXIMUM_IPU_SUPPORTED];
624
625 }ME_FWU_INFO;
626 C_ASSERT(sizeof(ME_FWU_INFO) == 448);
627
628
629 // Typedef for the commands serviced by the Fw Update service
630 typedef enum _FWU_HECI_MESSAGE_TYPE
631 {
632 FWU_GET_VERSION = 0,
633 FWU_GET_VERSION_REPLY,
634 FWU_START,
635 FWU_START_REPLY,
636 FWU_DATA,
637 FWU_DATA_REPLY,
638 FWU_END,
639 FWU_END_REPLY,
640 FWU_GET_INFO,
641 FWU_GET_INFO_REPLY,
642 FWU_GET_FEATURE_STATE,
643 FWU_GET_FEATURE_STATE_REPLY,
644 FWU_GET_FEATURE_CAPABILITY,
645 FWU_GET_FEATURE_CAPABILITY_REPLY,
646 FWU_GET_PLATFORM_TYPE,
647 FWU_GET_PLATFORM_TYPE_REPLY,
648 FWU_VERIFY_OEMID,
649 FWU_VERIFY_OEMID_REPLY,
650 FWU_GET_OEMID,
651 FWU_GET_OEMID_REPLY,
652 FWU_IMAGE_COMPATABILITY_CHECK,
653 FWU_IMAGE_COMPATABILITY_CHECK_REPLY,
654 FWU_GET_UPDATE_DATA_EXTENSION,
655 FWU_GET_UPDATE_DATA_EXTENSION_REPLY,
656 FWU_GET_RESTORE_POINT_IMAGE,
657 FWU_GET_RESTORE_POINT_IMAGE_REPLY,
658 //FWU_GET_RECOVERY_MODE,
659 //FWU_GET_RECOVERY_MODE_REPLY,
660 FWU_GET_IPU_PT_ATTRB,
661 FWU_GET_IPU_PT_ATTRB_REPLY,
662 FWU_GET_FWU_INFO_STATUS,
663 FWU_GET_FWU_INFO_STATUS_REPLY,
664 GET_ME_FWU_INFO,
665 GET_ME_FWU_INFO_REPLY,
666 FWU_CONFIRM_LIVE_PING,
667 FWU_CONFIRM_LIVE_PING_REPLY,
668 FWU_VERIFY_PWD,
669 FWU_VERIFY_PWD_REPLY,
670 FWU_GET_RESTORE_POINT_IMAGE_DATA,
671 FWU_GET_RESTORE_POINT_IMAGE_DATA_REPLY,
672 FWU_INVALID_REPLY = 0xFF
673 } FWU_HECI_MESSAGE_TYPE;
674
675
676 /**
677 * FWU_FLASH_IMAGE_START_MSG - start the update process
678 *
679 * @MessageType: FWU_FLASH_IMAGE_START_MSG
680 */
681 typedef struct _FWU_FLASH_IMAGE_START_MSG_REPLY
682 {
683 STATUS Status;
684 unsigned int Resv[4];
685 }FWU_FLASH_IMAGE_START_MSG_REPLY;
686
687
688 /**
689 * FWU_GET_VERSION_MSG - start the update process
690 *
691 * @MessageType: FWU_GET_VERSION_MSG
692 */
693 // Struct definition below here //
694 typedef struct _FWU_GET_VERSION_MSG_REPLY
695 {
696 unsigned int MessageType;
697 unsigned int Status;
698 unsigned int Sku;
699 unsigned int PCHVer;
700 unsigned int Vendor;
701 unsigned int LastFwUpdateStatus;
702 unsigned int HwSku;
703 VERSION CodeVersion;
704 VERSION AMTVersion;
705 unsigned short EnabledUpdateInterfaces; // local, remote (LMS/LME) and secure update
706 unsigned short SvnInFlash; // Security version of image that is already in flash
707 unsigned int DataFormatVersion; // Upper 16 sig bits for Major version lower 16's for Minor Version
708 unsigned int LastUpdateResetType; // Last successfull update partition reset type prior to reboot. After reboot, it should be zero
709 } FWU_GET_VERSION_MSG_REPLY;
710
711
712 /**
713 * FWU_START_MSG - start the update process
714 *
715 * @MessageType: FWU_START_MSG
716 */
717 typedef struct _FWU_START_MSG
718 {
719 unsigned int MessageType;
720 unsigned int Length; // Length of update image
721 unsigned int UpdtLength; // Length of preupdate partition
722 unsigned char UpdateType; // 0 Full update, 1 partial IPU pdate
723 unsigned char PassWordLength; // Length of password not include NULL
724 unsigned char PassWordData[FWU_PWD_MAX_SIZE]; // Password data not include NULL byte
725 unsigned int IpuIdTobeUpdated; // Only for Partial FWU
726 unsigned int UpdateEnvironment;// 0 default to normal manufacturing use
727 // 1 is for Emergency IFU update
728 UPDATE_FLAGS UpdateFlags;
729 OEM_UUID OemId;
730 unsigned int Resv[4];
731 } FWU_START_MSG;
732
733
734 typedef struct _FWU_START_MSG_REPLY
735 {
736 unsigned int MessageType;
737 STATUS Status;
738 unsigned int Resv[4];
739
740 }FWU_START_MSG_REPLY;
741
742
743 /**
744 * FWU_DATA_MSG - send data during the update process
745 *
746 * @MessageType: FWU_DATA_MSG
747 */
748 typedef struct _FWU_DATA_MSG
749 {
750 unsigned int MessageType;
751 unsigned int Length;
752 unsigned char Reserved[3];
753 unsigned char Data[1];
754 } FWU_DATA_MSG;
755
756
757 typedef struct _FWU_DATA_MSG_REPLY
758 {
759 unsigned int MessageType;
760 STATUS Status;
761 }FWU_DATA_MSG_REPLY;
762
763
764 /**
765 * FWU_END_MSG - end the update process
766 *
767 * @MessageType: FWU_END_MSG
768 */
769 typedef struct _FWU_END_MESSAGE
770 {
771 unsigned int MessageType;
772 } FWU_END_MESSAGE;
773
774 typedef struct _FWU_END_MSG_REPLY
775 {
776 unsigned int MessageType;
777 STATUS Status; // 0 indicate success, else failure
778 unsigned int ResetType;
779 unsigned int Resv[4];
780
781 }FWU_END_MSG_REPLY;
782
783
784 /**
785 * FWU_GET_INFO_MSG - get info
786 *
787 * @MessageType: FWU_GET_INFO_MSG
788 */
789 typedef struct _FWU_GET_INFO_MSG
790 {
791 unsigned int MessageType;
792 } FWU_GET_INFO_MSG;
793
794 // Contains the data to be returned for GET_VERSION command
795 typedef struct _FWU_GET_INFO_MSG_REPLY{
796 unsigned int MessageType;
797 unsigned int Status;
798 VERSION MEBxVersion;
799 unsigned int FlashOverridePolicy;
800 unsigned int MangeabilityMode;
801 unsigned int BiosBootState;
802 struct {
803 unsigned int CryptoFuse :1;
804 unsigned int FlashProtection:1; // read from SPI driver
805 unsigned int Obsolete_FwOverrideQualifier:2;
806 unsigned int MeResetReason:2; // Reset.h
807 unsigned int Obsolete_FwOverrideCounter:8; //TO DO: change this in MeTypes.h to unsigned char
808 unsigned int reserved:18;
809 }Fields;
810 unsigned char BiosVersion[20];
811
812 }FWU_GET_INFO_MSG_REPLY;
813
814
815 /**
816 * FWU_GET_FEATURE_STATE_MSG - get info
817 *
818 * @MessageType: FWU_GET_FEATURE_STATE_MSG
819 */
820 typedef struct _FWU_GET_FEATURE_STATE_MSG_REPLY
821 {
822 unsigned int MessageType;
823 unsigned int Status;
824 unsigned int FeatureState;
825 } FWU_GET_FEATURE_STATE_MSG_REPLY;
826
827
828 /**
829 * FWU_GET_PLATFORM_TYPE_MSG - get plat type
830 *
831 * @MessageType: FWU_GET_PLATFORM_TYPE_MSG
832 */
833 typedef struct _FWU_GET_PLATFORM_TYPE_MSG_REPLY
834 {
835 unsigned int MessageType;
836 unsigned int Status;
837 unsigned int PlatformType;
838 } FWU_GET_PLATFORM_TYPE_MSG_REPLY;
839
840
841 /**
842 * FWU_VERIFY_OEMID_MSG - verify OEMID
843 *
844 * @MessageType: FWU_VERIFY_OEMID_MSG
845 */
846 typedef struct _FWU_VERIFY_OEMID_MSG
847 {
848 unsigned int MessageType;
849 OEM_UUID OemId;
850 } FWU_VERIFY_OEMID_MSG;
851
852 typedef struct _FWU_VERIFY_OEMID_MSG_REPLY
853 {
854 unsigned int MessageType;
855 unsigned int Status;
856 }FWU_VERIFY_OEMID_MSG_REPLY;
857
858
859 /**
860 * FWU_GET_OEMID_MSG - verify OEMID
861 *
862 * @MessageType: FWU_GET_OEMID_MSG
863 */
864 typedef struct _FWU_GET_OEMID_MSG_REPLY
865 {
866 unsigned int MessageType;
867 STATUS Status;
868 OEM_UUID OemId;
869 } FWU_GET_OEMID_MSG_REPLY;
870
871
872 /**
873 * FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability
874 *
875 * @MessageType: FWU_IMAGE_COMPATABILITY_CHECK_MSG
876 */
877 typedef struct _FWU_IMAGE_COMPATABILITY_CHECK_MSG
878 {
879 unsigned int MessageType;
880 unsigned int ManifestLength; // Manifest Len
881 unsigned char Reserved[3];
882 unsigned char ManifestBuffer[1]; // At least one element
883 // otherwise compiling error when use WATCOM compiler
884 }FWU_IMAGE_COMPATABILITY_CHECK_MSG;
885
886
887
888 typedef struct _FWU_IMAGE_COMPATABILITY_CHECK_MSG_REPLY
889 {
890 unsigned int MessageType;
891 STATUS Status; // 0 is OK for update, else failures
892 // Possible error code
893 // STATUS_UPDATE_READ_FILE_FAILURE
894 // STATUS_UPDATE_FW_VERSION_MISMATCH
895 // STATUS_UPDATE_IMAGE_INVALID
896 // STATUS_UPDATE_FLASH_CODE_PARTITION_INVALID
897 // STATUS_UPDATE_IMAGE_VERSION_HISTORY_CHECK_FAILURE
898 // STATUS_UPDATE_IMAGE_BLACKLISTED
899 }FWU_IMAGE_COMPATABILITY_CHECK_MSG_REPLY;
900
901
902 /**
903 * FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability
904 *
905 * @MessageType: FWU_GET_UPDATE_DATA_EXTENSION_MSG
906 */
907 typedef struct _FWU_GET_UPDATE_DATA_EXTENSION_MSG
908 {
909 unsigned int MessageType;
910 } FWU_GET_UPDATE_DATA_EXTENSION_MSG;
911
912 typedef struct _FWU_GET_UPDATE_DATA_EXTENSION_MSG_REPLY
913 {
914 unsigned int MessageType;
915 STATUS Status; // 0 for success, other failure and the info is invalid
916 unsigned char History[4]; // Minor0Predecessor, Minor1Predecessor, Minor2Predecessor, Minor3Predecessor
917 unsigned int CriticalHotfixDescriptor;
918 BLACK_LIST_ENTRY BlackList[BLACK_LIST_ENTRY_MAX];
919 }FWU_GET_UPDATE_DATA_EXTENSION_MSG_REPLY;
920
921
922 /**
923 * FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image
924 *
925 * @MessageType: FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
926 */
927 typedef struct _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
928 {
929 unsigned int MessageType;
930 } FWU_GET_RESTORE_POINT_IMAGE_MESSAGE;
931
932 typedef struct _FWU_GET_RESTORE_POINT_IMAGE_MSG_REPLY
933 {
934 unsigned int MessageType;
935 STATUS Status;
936 unsigned int RestorePointImageSize; // Size of image is in Bytes
937 unsigned int RestorePointImage[1];
938 }FWU_GET_RESTORE_POINT_IMAGE_MSG_REPLY;
939
940
941 /**
942 * FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image
943 *
944 * @MessageType: FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
945 */
946 typedef struct _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE
947 {
948 unsigned int MessageType;
949 } FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE;
950
951 typedef struct _FWU_GET_RESTORE_POINT_IMAGE_DATA_MSG_REPLY
952 {
953 unsigned int MessageType;
954 STATUS Status;
955 unsigned int RestorePointImageOffset;
956 unsigned int RestorePointImageDataLength; // Size of image is in Bytes
957 unsigned int RestorePointImage[1];
958 }FWU_GET_RESTORE_POINT_IMAGE_DATA_MSG_REPLY;
959
960
961 /**
962 * FWU_GET_IPU_PT_ATTRB_MSG - get info status
963 *
964 * @MessageType: FWU_GET_IPU_PT_ATTRB_MSG
965 */
966 typedef struct _FWU_GET_IPU_PT_ATTRB_MSG
967 {
968 unsigned int MessageType;
969 unsigned int UpdateType;
970 } FWU_GET_IPU_PT_ATTRB_MSG;
971
972 typedef struct _FWU_GET_IPU_PT_ATTRB_MSG_REPLY
973 {
974 unsigned int MessageType; // Internal FWU tool use only
975 STATUS Status; // Internal FWU tool use only
976 VERSION FtpFwVer; // FW version in Fault Tolerance Partition.
977 // This might be used for diagnostic or debug.
978 unsigned int SizeoOfPtAttrib; // Size in bytes. Simply is the sizeof (PT_ATTRB structure)
979 unsigned int NumOfPartition; // Number of partition actually return in this reply message
980 PT_ATTRB PtAttribute[MAXIMUM_IPU_SUPPORTED];
981 unsigned int Resv[4];
982 }FWU_GET_IPU_PT_ATTRB_MSG_REPLY;
983
984
985 /**
986 * FWU_GET_FWU_INFO_STATUS_MSG - get info status
987 *
988 * @MessageType: FWU_GET_FWU_INFO_STATUS_MSG
989 */
990 typedef struct _FWU_GET_FWU_INFO_STATUS_MSG
991 {
992 unsigned int MessageType;
993 unsigned int InfoParm; // Not used
994 unsigned int Resv[4];
995 }FWU_GET_FWU_INFO_STATUS_MSG;
996
997 typedef struct _FWU_GET_FWU_INFO_STATUS_MSG_REPLY
998 {
999 unsigned int MessageType;
1000 STATUS Status;
1001 FWU_INFO_FLAGS Flags;
1002 unsigned int Resv[4];
1003 }FWU_GET_FWU_INFO_STATUS_MSG_REPLY;
1004
1005
1006 /**
1007 * ME_FWU_INFO_MSG - get ME firmware update info message
1008 *
1009 * @MessageType: ME_FWU_INFO_MSG
1010 */
1011 typedef struct _ME_FWU_INFO_MSG
1012 {
1013 unsigned int MessageType;
1014 unsigned int MessageParams[2]; //Currently not used
1015 }ME_FWU_INFO_MSG;
1016
1017 typedef struct _ME_FWU_INFO_MSG_REPLY
1018 {
1019 unsigned int MessageType;
1020 unsigned int Status; // 0 = success, else failure
1021 ME_FWU_INFO MeFwuInfo;
1022 }ME_FWU_INFO_MSG_REPLY;
1023
1024 /**
1025 * FWU_CONFIRM_LIVE_PING_MSG - confirm live ping
1026 *
1027 * @MessageType: FWU_CONFIRM_LIVE_PING_MSG
1028 */
1029 typedef struct _FWU_CONFIRM_LIVE_PING_MSG
1030 {
1031 unsigned int MessageType;
1032 unsigned int Reserve[4];
1033 } FWU_CONFIRM_LIVE_PING_MSG;
1034
1035 typedef struct _FWU_CONFIRM_LIVE_PING_MSG_REPLY
1036 {
1037 unsigned int MessageType;
1038 unsigned int Status; // Always STATUS_SUCCESS = 0
1039 unsigned int Reserve[4];
1040 }FWU_CONFIRM_LIVE_PING_MSG_REPLY;
1041
1042
1043 /**
1044 * FWU_VERIFY_PWD_MSG - confirm live ping
1045 *
1046 * @MessageType: FWU_VERIFY_PWD_MSG
1047 */
1048 typedef struct _FWU_VERIFY_PWD_MSG
1049 {
1050 unsigned int MessageType;
1051 unsigned char PasswordLength;
1052 unsigned char PasswordData[FWU_PWD_MAX_SIZE];
1053 }FWU_VERIFY_PWD_MSG;
1054
1055 typedef struct _FWU_VERIFY_PWD_MSG_REPLY
1056 {
1057 unsigned int MessageType;
1058 unsigned int Status;
1059 }FWU_VERIFY_PWD_MSG_REPLY;
1060
1061
1062 /**
1063 * FWU_INVALID_MSG - confirm live ping
1064 *
1065 * @MessageType: FWU_INVALID_MSG
1066 */
1067 typedef struct _FWU_INVALID_MSG_REPLY
1068 {
1069 unsigned int MessageType;
1070 STATUS Status;
1071 }FWU_INVALID_MSG_REPLY;
1072
1073
1074 //NOTE: WE ARE VERY CLOSE TO MAXIMUM HECI MESSAGE BUFFER SIZE
1075 typedef struct _FWU_HECI_MSG
1076 {
1077 union{
1078 unsigned int MessageType;
1079
1080 FWU_GET_VERSION_MSG_REPLY VersionReply;
1081 FWU_START_MSG Start;
1082 FWU_START_MSG_REPLY StartReply;
1083 FWU_DATA_MSG Data;
1084 FWU_DATA_MSG_REPLY DataReply;
1085 FWU_END_MSG_REPLY EndReply;
1086 FWU_GET_INFO_MSG_REPLY InfoReply;
1087 FWU_GET_FEATURE_STATE_MSG_REPLY FeatureStateReply;
1088 FWU_GET_PLATFORM_TYPE_MSG_REPLY PlatformTypeReply;
1089 FWU_VERIFY_OEMID_MSG VerifyOemId;
1090 FWU_VERIFY_OEMID_MSG_REPLY VerifyOemIdReply;
1091 FWU_GET_OEMID_MSG_REPLY GetOemIdReply;
1092 FWU_IMAGE_COMPATABILITY_CHECK_MSG ImageCheck;
1093 FWU_IMAGE_COMPATABILITY_CHECK_MSG_REPLY ImageCheckReply;
1094 FWU_GET_UPDATE_DATA_EXTENSION_MSG_REPLY GetUpdateDataExtReply;
1095 FWU_GET_RESTORE_POINT_IMAGE_MSG_REPLY GetRestorePointImageReply;
1096 FWU_GET_RESTORE_POINT_IMAGE_DATA_MSG_REPLY GetRestorePointImageDataReply;
1097 //FWU_GET_RECOVERY_MODE_MSG GetRecoveryMode;
1098 //FWU_GET_RECOVERY_MODE_MSG_REPLY GetRecoveryModeReply;
1099 FWU_GET_IPU_PT_ATTRB_MSG GetIpuPtAttrb;
1100 FWU_GET_IPU_PT_ATTRB_MSG_REPLY GetIpuPtAttrbReply;
1101 FWU_GET_FWU_INFO_STATUS_MSG GetFwuInfoStatusMsg;
1102 FWU_GET_FWU_INFO_STATUS_MSG_REPLY GetFwuInfoStatusMsgReply;
1103 ME_FWU_INFO_MSG_REPLY GetMeInfoMsgReply;
1104 FWU_CONFIRM_LIVE_PING_MSG ConfirmLivePingMsg;
1105 FWU_CONFIRM_LIVE_PING_MSG_REPLY ConfirmLivePingMsgReply;
1106 FWU_VERIFY_PWD_MSG VerifyPwd;
1107 FWU_VERIFY_PWD_MSG_REPLY VerifyPwdReply;
1108 FWU_INVALID_MSG_REPLY InvalidMsgReply;
1109
1110 }MessageData;
1111 }FWU_HECI_MSG;
1112
1113 // ***************************************
1114 /* HMRFPO Message Data Structures */
1115 // ***************************************
1116
1117 //HMRFPO ENABLE REQ
1118 typedef struct _FWUPDATE_HMRFPO_ENABLE_DATA //unlock
1119 {
1120 unsigned long long Nonce; //For minisku/BIOS message compatibility
1121 } FWUPDATE_HMRFPO_ENABLE_DATA;
1122
1123 typedef struct _FWUPDATE_HMRFPO_ENABLE
1124 {
1125 mkhi_message_header_t Header;
1126 FWUPDATE_HMRFPO_ENABLE_DATA Data; //For minisku/BIOS message compatibility
1127 } FWUPDATE_HMRFPO_ENABLE;
1128
1129
1130 //HMRFPO ENABLE ACK
1131 typedef struct _FWUPDATE_HMRFPO_ENABLE_ACK_DATA
1132 {
1133 unsigned int FactoryDefaultBase; //For minisku/BIOS message compatibility
1134 unsigned int FactoryDefaultLimit; //For minisku/BIOS message compatibility
1135 unsigned char HMRFPO_EN_Status;
1136 unsigned char Rsvd[3];
1137 } FWUPDATE_HMRFPO_ENABLE_ACK_DATA;
1138
1139 typedef struct _FWUPDATE_HMRFPO_ENABLE_ACK
1140 {
1141 mkhi_message_header_t Header;
1142 FWUPDATE_HMRFPO_ENABLE_ACK_DATA Data;
1143 } FWUPDATE_HMRFPO_ENABLE_ACK;
1144
1145
1146 //HMRFPO LOCK REQ
1147 typedef struct _FWUPDATE_HMRFPO_LOCK
1148 {
1149 mkhi_message_header_t Header;
1150 } FWUPDATE_HMRFPO_LOCK;
1151
1152
1153 //HMRFPO LOCK ACK
1154 typedef struct _FWUPDATE_HMRFPO_LOCK_ACK_DATA
1155 {
1156 unsigned long long Nonce;
1157 unsigned int FactoryDefaultBase; //For minisku/BIOS message compatibility
1158 unsigned int FactoryDefaultLimit; //For minisku/BIOS message compatibility
1159 unsigned char HMRFPO_LOCK_Status;
1160 unsigned char Rsvd[3];
1161 } FWUPDATE_HMRFPO_LOCK_ACK_DATA;
1162
1163 typedef struct _FWUPDATE_HMRFPO_LOCK_ACK
1164 {
1165 mkhi_message_header_t Header;
1166 FWUPDATE_HMRFPO_LOCK_ACK_DATA Data;
1167 } FWUPDATE_HMRFPO_LOCK_ACK;
1168
1169 //HMRFPO GETSTATUS REQ
1170 typedef struct _FWUPDATE_HMRFPO_GETSTATUS
1171 {
1172 mkhi_message_header_t Header;
1173 } FWUPDATE_HMRFPO_GETSTATUS;
1174
1175
1176 //HMRFPO GETSTATUS ACK
1177 typedef struct _FWUPDATE_HMRFPO_GETSTATUS_ACK_DATA
1178 {
1179 unsigned char HMRFPO_State;
1180 unsigned char Rsvd[3];
1181 } FWUPDATE_HMRFPO_GETSTATUS_ACK_DATA;
1182
1183 typedef struct _FWUPDATE_HMRFPO_GETSTATUS_ACK
1184 {
1185 mkhi_message_header_t Header;
1186 FWUPDATE_HMRFPO_GETSTATUS_ACK_DATA Data;
1187 } FWUPDATE_HMRFPO_GETSTATUS_ACK;
1188
1189 /*
1190 //HMRFPO DISABLE REQ
1191 typedef struct _FWUPDATE_HMRFPO_DISABLE
1192 {
1193 mkhi_message_header_t Header;
1194 } FWUPDATE_HMRFPO_DISABLE;
1195
1196 typedef struct _MKHI_FWUPDATE_HMRFPO_DISABLE
1197 {
1198 HECI_MESSAGE_HEADER Header;
1199 FWUPDATE_HMRFPO_DISABLE Msg;
1200 } MKHI_FWUPDATE_HMRFPO_DISABLE;
1201
1202 //HMRFPO DISABLE ACK
1203 typedef struct _FWUPDATE_HMRFPO_DISABLE_ACK_DATA
1204 {
1205 unsigned char HMRFPO_DIS_Status;
1206 unsigned char Reserved[3]; //To conform to CBM_TEMPLATE in BUP
1207 //so sizeof(FWUPDATE_HMRFPO_DISABLE_ACK_DATA) == UINT32
1208 } FWUPDATE_HMRFPO_DISABLE_ACK_DATA;
1209
1210 typedef struct _FWUPDATE_HMRFPO_DISABLE_ACK
1211 {
1212 mkhi_message_header_t Header;
1213 FWUPDATE_HMRFPO_DISABLE_ACK_DATA Data;
1214 } FWUPDATE_HMRFPO_DISABLE_ACK;
1215
1216 // FWUPDATE_QUERY_UPDATE_STATUS
1217 typedef struct _FWUPDATE_QUERY_UPDATE_STATUS
1218 {
1219 mkhi_message_header_t Header;
1220 } FWUPDATE_QUERY_UPDATE_STATUS;
1221
1222
1223 //FWUPDATE_QUERY_UPDATE_STATUS_ACK
1224 typedef struct _FWUPDATE_QUERY_UPDATE_STATUS_ACK_DATA
1225 {
1226 unsigned int PercentComplete;
1227 unsigned int CurrentStage; // Current update Stage
1228 unsigned int TotalStages; // Total number of update stages
1229 unsigned int LastUpdateStatus; // Last FW update status
1230 } FWUPDATE_QUERY_UPDATE_STATUS_ACK_DATA;
1231
1232 typedef struct _FWUPDATE_QUERY_UPDATE_STATUS_ACK
1233 {
1234 mkhi_message_header_t Header; // Header.Result = 0 indicate in progress
1235 // Header.Result = 1 Complete the update
1236 // Header.Result = 2 Error during the update
1237 FWUPDATE_QUERY_UPDATE_STATUS_ACK_DATA QueryAckData;
1238 unsigned int ResetType; // Partition reset type
1239 FWU_INFO_FLAGS Flags; // See FWU_INFO_FLAGS
1240 } FWUPDATE_QUERY_UPDATE_STATUS_ACK;
1241 */
1242
1243 // FWUPDATE_FORCE_SAFE_BOOT_CMD
1244 typedef struct _FWUPDATE_FORCE_SAFE_BOOT_MSG
1245 {
1246 mkhi_message_header_t Header;
1247 } FWUPDATE_FORCE_SAFE_BOOT_MSG;
1248
1249 typedef struct _FWUPDATE_FORCE_SAFE_BOOT_MSG_ACK
1250 {
1251 mkhi_message_header_t Header; // Header.Result = 0 indicate success else failure
1252 unsigned int Data;
1253 } FWUPDATE_FORCE_SAFE_BOOT_MSG_ACK;
1254 #pragma pack()
1255
1256
1257 #endif // _FWU_COMMON_H
1258
1259
1260
_FWU_VERIFY_PWD_MSG
FWU_VERIFY_PWD_MSG - confirm live ping.
Definition: Fwu_Common.h:1048
_FWU_IMAGE_COMPATABILITY_CHECK_MSG
FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability.
Definition: Fwu_Common.h:877
_FWU_END_MESSAGE
FWU_END_MSG - end the update process.
Definition: Fwu_Common.h:769
FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE
struct _FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.
FWU_GET_FEATURE_STATE_MSG_REPLY
struct _FWU_GET_FEATURE_STATE_MSG_REPLY FWU_GET_FEATURE_STATE_MSG_REPLY
FWU_GET_FEATURE_STATE_MSG - get info.
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
struct _FWU_GET_RESTORE_POINT_IMAGE_MESSAGE FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.
FWU_GET_OEMID_MSG_REPLY
struct _FWU_GET_OEMID_MSG_REPLY FWU_GET_OEMID_MSG_REPLY
FWU_GET_OEMID_MSG - verify OEMID.
_FWU_VERIFY_OEMID_MSG
FWU_VERIFY_OEMID_MSG - verify OEMID.
Definition: Fwu_Common.h:846
_FWU_GET_RESTORE_POINT_IMAGE_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.
Definition: Fwu_Common.h:927
FWU_GET_INFO_MSG
struct _FWU_GET_INFO_MSG FWU_GET_INFO_MSG
FWU_GET_INFO_MSG - get info.
_FWU_GET_IPU_PT_ATTRB_MSG
FWU_GET_IPU_PT_ATTRB_MSG - get info status.
Definition: Fwu_Common.h:966
FWU_GET_PLATFORM_TYPE_MSG_REPLY
struct _FWU_GET_PLATFORM_TYPE_MSG_REPLY FWU_GET_PLATFORM_TYPE_MSG_REPLY
FWU_GET_PLATFORM_TYPE_MSG - get plat type.
_FWU_GET_INFO_MSG
FWU_GET_INFO_MSG - get info.
Definition: Fwu_Common.h:789
FWU_FLASH_IMAGE_START_MSG_REPLY
struct _FWU_FLASH_IMAGE_START_MSG_REPLY FWU_FLASH_IMAGE_START_MSG_REPLY
FWU_FLASH_IMAGE_START_MSG - start the update process.
_FWU_GET_VERSION_MSG_REPLY
FWU_GET_VERSION_MSG - start the update process.
Definition: Fwu_Common.h:694
_FWU_GET_OEMID_MSG_REPLY
FWU_GET_OEMID_MSG - verify OEMID.
Definition: Fwu_Common.h:864
_FWU_GET_PLATFORM_TYPE_MSG_REPLY
FWU_GET_PLATFORM_TYPE_MSG - get plat type.
Definition: Fwu_Common.h:833
FWU_END_MESSAGE
struct _FWU_END_MESSAGE FWU_END_MESSAGE
FWU_END_MSG - end the update process.
FWU_INVALID_MSG_REPLY
struct _FWU_INVALID_MSG_REPLY FWU_INVALID_MSG_REPLY
FWU_INVALID_MSG - confirm live ping.
mkhi_hdrs.h
FWU_GET_UPDATE_DATA_EXTENSION_MSG
struct _FWU_GET_UPDATE_DATA_EXTENSION_MSG FWU_GET_UPDATE_DATA_EXTENSION_MSG
FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability.
_FWU_GET_UPDATE_DATA_EXTENSION_MSG
FWU_GET_UPDATE_DATA_EXTENSION_MSG - verify image compatability.
Definition: Fwu_Common.h:907
FWU_CONFIRM_LIVE_PING_MSG
struct _FWU_CONFIRM_LIVE_PING_MSG FWU_CONFIRM_LIVE_PING_MSG
FWU_CONFIRM_LIVE_PING_MSG - confirm live ping.
_FWU_DATA_MSG
FWU_DATA_MSG - send data during the update process.
Definition: Fwu_Common.h:748
ver.h
Contains definitions of the MAJOR, MINOR, & HOTFIX versions used throughout the code.
_FWU_GET_FEATURE_STATE_MSG_REPLY
FWU_GET_FEATURE_STATE_MSG - get info.
Definition: Fwu_Common.h:820
ME_FWU_INFO_MSG
struct _ME_FWU_INFO_MSG ME_FWU_INFO_MSG
ME_FWU_INFO_MSG - get ME firmware update info message.
_FWU_CONFIRM_LIVE_PING_MSG
FWU_CONFIRM_LIVE_PING_MSG - confirm live ping.
Definition: Fwu_Common.h:1029
_FWU_INVALID_MSG_REPLY
FWU_INVALID_MSG - confirm live ping.
Definition: Fwu_Common.h:1067
FWU_START_MSG
struct _FWU_START_MSG FWU_START_MSG
FWU_START_MSG - start the update process.
FWU_VERIFY_OEMID_MSG
struct _FWU_VERIFY_OEMID_MSG FWU_VERIFY_OEMID_MSG
FWU_VERIFY_OEMID_MSG - verify OEMID.
_FWU_FLASH_IMAGE_START_MSG_REPLY
FWU_FLASH_IMAGE_START_MSG - start the update process.
Definition: Fwu_Common.h:681
FWU_GET_VERSION_MSG_REPLY
struct _FWU_GET_VERSION_MSG_REPLY FWU_GET_VERSION_MSG_REPLY
FWU_GET_VERSION_MSG - start the update process.
_VERSION
Defines a generic version structure used in the software build process.
Definition: ver.h:83
FWU_DATA_MSG
struct _FWU_DATA_MSG FWU_DATA_MSG
FWU_DATA_MSG - send data during the update process.
_FWU_START_MSG
FWU_START_MSG - start the update process.
Definition: Fwu_Common.h:717
FWU_VERIFY_PWD_MSG
struct _FWU_VERIFY_PWD_MSG FWU_VERIFY_PWD_MSG
FWU_VERIFY_PWD_MSG - confirm live ping.
_ME_FWU_INFO_MSG
ME_FWU_INFO_MSG - get ME firmware update info message.
Definition: Fwu_Common.h:1011
_FWU_GET_RESTORE_POINT_IMAGE_DATA_MESSAGE
FWU_GET_RESTORE_POINT_IMAGE_MESSAGE - get restore point image.
Definition: Fwu_Common.h:946
_FWU_GET_FWU_INFO_STATUS_MSG
FWU_GET_FWU_INFO_STATUS_MSG - get info status.
Definition: Fwu_Common.h:990
FWU_GET_IPU_PT_ATTRB_MSG
struct _FWU_GET_IPU_PT_ATTRB_MSG FWU_GET_IPU_PT_ATTRB_MSG
FWU_GET_IPU_PT_ATTRB_MSG - get info status.
FWU_GET_FWU_INFO_STATUS_MSG
struct _FWU_GET_FWU_INFO_STATUS_MSG FWU_GET_FWU_INFO_STATUS_MSG
FWU_GET_FWU_INFO_STATUS_MSG - get info status.
FWU_IMAGE_COMPATABILITY_CHECK_MSG
struct _FWU_IMAGE_COMPATABILITY_CHECK_MSG FWU_IMAGE_COMPATABILITY_CHECK_MSG
FWU_IMAGE_COMPATABILITY_CHECK_MSG - verify image compatability.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: GfxInt15Interface.c Source File

  • PlatformInit
  • PlatformInitDxe
GfxInt15Interface.c
Go to the documentation of this file.
1 /** @file
2 This is a driver to produce Int15 hook.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 //
36 // Module specific Includes
37 //
38 #include "PlatformInitDxe.h"
39 #include <Uefi/UefiBaseType.h>
40 #include <Protocol/LegacyInterruptHandler.h>
41 #include <Protocol/FirmwareVolume2.h>
42
43 GLOBAL_REMOVE_IF_UNREFERENCED EFI_LEGACY_INTERRUPT_HANDLER_PROTOCOL mLegacyInterruptHandler;
44
45 /**
46 Loads real mode file form the FV
47
48 @param[in] Guid
49 @param[in] Buffer
50 @param[in] BufferSize
51
52 @retval EFI_SUCCESS Function has completed successfully.
53 **/
54 EFI_STATUS
55 LoadRealModeFile (
56 EFI_GUID *Guid,
57 VOID **Buffer,
58 UINTN *BufferSize
59 )
60 {
61 EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
62 UINT32 Authentication;
63 EFI_STATUS Status;
64 UINTN NumHandles;
65 EFI_HANDLE *HandleBuffer;
66 UINTN Index;
67
68 *Buffer = NULL;
69 *BufferSize = 0;
70 Fv = NULL;
71
72 Status = gBS->LocateHandleBuffer (
73 ByProtocol,
74 &gEfiFirmwareVolume2ProtocolGuid,
75 NULL,
76 &NumHandles,
77 &HandleBuffer
78 );
79 if (EFI_ERROR(Status)) return Status;
80
81 for (Index = 0; Index < NumHandles; ++Index) {
82 Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiFirmwareVolume2ProtocolGuid, (VOID **) &Fv);
83 if (EFI_ERROR(Status)) continue;
84
85 Status = Fv->ReadSection(Fv,
86 Guid,
87 EFI_SECTION_RAW,
88 0, //Instance
89 Buffer,
90 BufferSize,
91 &Authentication);
92
93 if (Status == EFI_SUCCESS) break;
94 }
95
96 (gBS->FreePool)(HandleBuffer);
97 return Status;
98 }
99
100 /**
101 Inititialize Interrupt 15.
102
103 **/
104 VOID
105 InitializeGfxInt15 (
106 VOID
107 )
108 {
109 EFI_STATUS Status;
110 EFI_HANDLE Handle;
111
112
113 mLegacyInterruptHandler.Number = 0x15;
114 Status = LoadRealModeFile (&gRealModeFileGuid, (VOID **) &mLegacyInterruptHandler.Handler, &mLegacyInterruptHandler.Length);
115 ASSERT_EFI_ERROR (Status);
116
117 Handle = NULL;
118 Status = gBS->InstallMultipleProtocolInterfaces (
119 &Handle,
120 &gEfiLegacyInterruptHandlerProtocolGuid,
121 &mLegacyInterruptHandler,
122 NULL
123 );
124 ASSERT_EFI_ERROR (Status);
125 }
LoadRealModeFile
EFI_STATUS LoadRealModeFile(EFI_GUID *Guid, VOID **Buffer, UINTN *BufferSize)
Loads real mode file form the FV.
Definition: GfxInt15Interface.c:55
PlatformInitDxe.h
Platform Info Driver.
InitializeGfxInt15
VOID InitializeGfxInt15(VOID)
Inititialize Interrupt 15.
Definition: GfxInt15Interface.c:105
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: GopPolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
GopPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file initialises and Installs GopPolicy Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include "GopPolicyInitDxe.h"
36 #include <Protocol/GopPolicy.h>
37
38 GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;
39 GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0;
40 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0;
41
42 //
43 // Function implementations
44 //
45
46 /**
47
48 @param[out] CurrentLidStatus
49
50 @retval EFI_SUCCESS
51 @retval EFI_UNSUPPORTED
52 **/
53 EFI_STATUS
54 EFIAPI
55 GetPlatformLidStatus (
56 OUT LID_STATUS *CurrentLidStatus
57 )
58 {
59 EFI_STATUS Status;
60 UINT8 PortDataOut;
61 UINT8 DataBuffer[1];
62
63 //
64 // If the platform does not support a lid, the function must return EFI_UNSUPPORTED
65 //
66 if (PcdGet8 (PcdPlatformType) == TypeTrad && PcdGet8 (PcdPlatformFlavor) == FlavorDesktop) {
67 DEBUG ((DEBUG_INFO, "Returning Lid status as unsupported to GOP for DT/AIO board\n"));
68 return EFI_UNSUPPORTED;
69 }
70 if (PcdGetBool (PcdEcPresent)) {
71 DataBuffer[0] = EC_D_LID_STATE;
72 Status = ReadEcRam (DataBuffer);
73 if (Status == EFI_SUCCESS) {
74 PortDataOut = DataBuffer[0];
75 if ((PortDataOut & EC_B_LID_STATUS_OPEN) == EC_B_LID_STATUS_OPEN) {
76 *CurrentLidStatus = LidOpen;
77 } else {
78 *CurrentLidStatus = LidClosed;
79 }
80 return EFI_SUCCESS;
81 }
82 }
83
84 return EFI_UNSUPPORTED;
85 }
86 /**
87
88 @param[out] CurrentDockStatus
89
90 @retval EFI_SUCCESS
91 @retval EFI_UNSUPPORTED
92 **/
93 EFI_STATUS
94 EFIAPI
95 GetPlatformDockStatus (
96 OUT DOCK_STATUS CurrentDockStatus
97 )
98 {
99 return EFI_UNSUPPORTED;
100 }
101
102
103 /**
104
105 @param[out] VbtAddress
106 @param[out] VbtSize
107
108 @retval EFI_SUCCESS
109 @retval EFI_NOT_FOUND
110 **/
111 EFI_STATUS
112 EFIAPI
113 GetVbtData (
114 OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
115 OUT UINT32 *VbtSize
116 )
117 {
118 EFI_STATUS Status;
119 UINTN FvProtocolCount;
120 EFI_HANDLE *FvHandles;
121 EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
122 UINTN Index;
123 UINT32 AuthenticationStatus;
124 UINT8 *Buffer;
125 UINTN VbtBufferSize;
126 UINTN VariableSize;
127 SETUP_DATA SetupData;
128
129
130 Status = EFI_NOT_FOUND;
131 if ( mVbtAddress == 0) {
132 Fv = NULL;
133 VariableSize = sizeof (SETUP_DATA);
134 //
135 // Get setup variable
136 //
137 Status = gRT->GetVariable (
138 L"Setup",
139 &gSetupVariableGuid,
140 NULL,
141 &VariableSize,
142 &SetupData
143 );
144
145 Buffer = 0;
146 FvHandles = NULL;
147 Status = gBS->LocateHandleBuffer (
148 ByProtocol,
149 &gEfiFirmwareVolume2ProtocolGuid,
150 NULL,
151 &FvProtocolCount,
152 &FvHandles
153 );
154 if (!EFI_ERROR (Status)) {
155 for (Index = 0; Index < FvProtocolCount; Index++) {
156 Status = gBS->HandleProtocol (
157 FvHandles[Index],
158 &gEfiFirmwareVolume2ProtocolGuid,
159 (VOID **) &Fv
160 );
161 VbtBufferSize = 0;
162 Status = Fv->ReadSection (
163 Fv,
164 PcdGetPtr(PcdIntelGraphicsVbtFileGuid),
165 EFI_SECTION_RAW,
166 0,
167 (VOID **) &Buffer,
168 &VbtBufferSize,
169 &AuthenticationStatus
170 );
171 if (!EFI_ERROR (Status)) {
172 *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer;
173 *VbtSize = (UINT32)VbtBufferSize;
174 mVbtAddress = *VbtAddress;
175 mVbtSize = *VbtSize;
176 Status = EFI_SUCCESS;
177 break;
178 }
179 }
180 } else {
181 Status = EFI_NOT_FOUND;
182 }
183
184 if (FvHandles != NULL) {
185 FreePool (FvHandles);
186 FvHandles = NULL;
187 }
188 } else {
189 *VbtAddress = mVbtAddress;
190 *VbtSize = mVbtSize;
191 Status = EFI_SUCCESS;
192 }
193
194 return Status;
195 }
196
197 /**
198 Initialize GOP DXE Policy
199
200 @param[in] ImageHandle Image handle of this driver.
201
202 @retval EFI_SUCCESS Initialization complete.
203 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
204 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
205 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
206 **/
207
208 EFI_STATUS
209 EFIAPI
210 GopPolicyInitDxe (
211 IN EFI_HANDLE ImageHandle
212 )
213 {
214 EFI_STATUS Status;
215
216 //
217 // Initialize the EFI Driver Library
218 //
219 SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
220
221 mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03;
222 mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus;
223 mGOPPolicy.GetVbtData = GetVbtData;
224 mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus;
225
226 //
227 // Install protocol to allow access to this Policy.
228 //
229 Status = gBS->InstallMultipleProtocolInterfaces (
230 &ImageHandle,
231 &gGopPolicyProtocolGuid,
232 &mGOPPolicy,
233 NULL
234 );
235
236 return Status;
237 }
GetPlatformLidStatus
EFI_STATUS GetPlatformLidStatus(OUT LID_STATUS *CurrentLidStatus)
Definition: GopPolicyInitDxe.c:55
GetPlatformDockStatus
EFI_STATUS GetPlatformDockStatus(OUT DOCK_STATUS CurrentDockStatus)
Definition: GopPolicyInitDxe.c:95
GopPolicyInitDxe
EFI_STATUS GopPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy.
Definition: GopPolicyInitDxe.c:210
GopPolicyInitDxe.h
Header file for the GopPolicyInitDxe Driver.
ReadEcRam
EFI_STATUS ReadEcRam(IN OUT UINT8 *DataBuffer)
Read data from EC RAM.
GetVbtData
EFI_STATUS GetVbtData(OUT EFI_PHYSICAL_ADDRESS *VbtAddress, OUT UINT32 *VbtSize)
Definition: GopPolicyInitDxe.c:113
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: GopPolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
GopPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the GopPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _GOP_POLICY_INIT_DXE_H_
35 #define _GOP_POLICY_INIT_DXE_H_
36
37 #include <Protocol/FirmwareVolume2.h>
38 #include <SetupVariable.h>
39 #include <Library/UefiLib.h>
40 #include <Library/BaseLib.h>
41 #include <Library/MemoryAllocationLib.h>
42 #include <Library/DxeServicesTableLib.h>
43 #include <Library/UefiBootServicesTableLib.h>
44 #include <Library/UefiRuntimeServicesTableLib.h>
45 #include <Library/BaseMemoryLib.h>
46 #include <Library/DebugLib.h>
47 #include <Library/EcMiscLib.h>
48 #include <PlatformBoardId.h>
49 #include <Library/PcdLib.h>
50
51 /**
52 Initialize GOP DXE Policy
53
54 @param[in] ImageHandle Image handle of this driver.
55
56 @retval EFI_SUCCESS Initialization complete.
57 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
58 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
59 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
60 **/
61 EFI_STATUS
62 EFIAPI
63 GopPolicyInitDxe(
64 IN EFI_HANDLE ImageHandle
65 );
66
67 #endif
GopPolicyInitDxe
EFI_STATUS GopPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy.
Definition: GopPolicyInitDxe.c:210
PlatformBoardId.h
Defines Platform BoardIds.
EcMiscLib.h
EC miscellaneous library functions.
SetupVariable.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: GpioExpanderLib.h Source File

  • Library
GpioExpanderLib.h
Go to the documentation of this file.
1 /** @file
2 Support for IO expander TCA6424.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Uefi.h>
36 #include <Library/DebugLib.h>
37 #include <Library/TimerLib.h>
38 #include <Library/IoLib.h>
39 #include <Library/UefiLib.h>
40 #include <PchAccess.h>
41 #include <Library/PchSerialIoLib.h>
42
43 /**
44 Set the Direction value for the given Expander Gpio pin.
45
46 This function is to Set the direction value for the GPIO
47 Pin within the giving Expander.
48
49 @param[in] Expander Expander Value with in the Contoller
50 @param[in] Pin Pin with in the Expnader Value
51 @param[in] Value none
52 **/
53 VOID
54 GpioExpSetDirection (
55 IN UINT8 Expander,
56 IN UINT8 Pin,
57 IN UINT8 Direction
58 );
59 /**
60 Set the input value for the given Expander Gpio pin.
61
62 This function is to get the input value for the GPIO
63 Pin within the giving Expander.
64
65 @param[in] Expander Expander Value with in the Contoller
66 @param[in] Pin Pin with in the Expnader Value
67 @param[in] Value none
68
69 **/
70 VOID
71 GpioExpSetPolarity (
72 IN UINT8 Expander,
73 IN UINT8 Pin,
74 IN UINT8 Polarity
75 );
76 /**
77 Set the Output value for the given Expander Gpio pin.
78
79 This function is to Set the Output value for the GPIO
80 Pin within the giving Expander.
81
82 @param[in] Expander Expander Value with in the Contoller
83 @param[in] Pin Pin with in the Expnader Value
84 @param[in] Value none
85
86 **/
87 VOID
88 GpioExpSetOutput (
89 IN UINT8 Expander,
90 IN UINT8 Pin,
91 IN UINT8 Value
92 );
93 /**
94 Returns the data from register value giving in the input.
95
96 This function is to get the data from the Expander
97 Registers by following the I2C Protocol communication
98
99
100 @param[in] Bar0 Bar address of the SerialIo Controller
101 @param[in] Address Expander Value with in the Contoller
102 @param[in] Register Address of Input/Output/Configure/Polarity
103 registers with in the Expander
104
105 @retval UINT8 Value returned from the register
106 **/
107 UINT8
108 GpioExpGetInput (
109 IN UINT8 Expander,
110 IN UINT8 Pin
111 );
112
113 /**
114 Configures all registers of a single IO Expander in one go.
115
116 @param[in] Expander Expander number (0/1)
117 @param[in] Direction Bit-encoded direction values. BIT0 is for pin0, etc. 0=output, 1=input
118 @param[in] Polarity Bit-encoded input inversion values. BIT0 is for pin0, etc. 0=normal, 1=inversion
119 @param[in] Output Bit-encoded output state, ignores polarity, only applicable if direction=INPUT. BIT0 is for pin0, etc. 0=low, 1=high
120
121 **/
122 VOID
123 GpioExpBulkConfig (
124 IN UINT8 Expander,
125 IN UINT32 Direction,
126 IN UINT32 Polarity,
127 IN UINT32 Output
128 );
129
130 /**
131 Returns the Controller on which GPIO expander is present.
132
133 This function returns the Controller value
134
135 @param[out] Controller Pointer to a Controller value on
136 which I2C expander is configured.
137
138 @retval EFI_SUCCESS non.
139 **/
140 EFI_STATUS
141 GpioExpGetController (
142 OUT UINT8 *Controller
143 );
144
145
GpioExpSetOutput
VOID GpioExpSetOutput(IN UINT8 Expander, IN UINT8 Pin, IN UINT8 Value)
Set the Output value for the given Expander Gpio pin.
GpioExpSetDirection
VOID GpioExpSetDirection(IN UINT8 Expander, IN UINT8 Pin, IN UINT8 Direction)
Set the Direction value for the given Expander Gpio pin.
GpioExpBulkConfig
VOID GpioExpBulkConfig(IN UINT8 Expander, IN UINT32 Direction, IN UINT32 Polarity, IN UINT32 Output)
Configures all registers of a single IO Expander in one go.
GpioExpGetController
EFI_STATUS GpioExpGetController(OUT UINT8 *Controller)
Returns the Controller on which GPIO expander is present.
GpioExpSetPolarity
VOID GpioExpSetPolarity(IN UINT8 Expander, IN UINT8 Pin, IN UINT8 Polarity)
Set the input value for the given Expander Gpio pin.
GpioExpGetInput
UINT8 GpioExpGetInput(IN UINT8 Expander, IN UINT8 Pin)
Returns the data from register value giving in the input.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: HidI2cPlatformSupportLib.h Source File

  • Library
HidI2cPlatformSupportLib.h
Go to the documentation of this file.
1 /** @file
2 Support for IO expander TCA6424.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Uefi.h>
36
37 //
38 // There's no decision yet if the 3 functions below should be a lib or protocol
39 //
40
41 EFI_STATUS EFIAPI HidI2cInitialize ( IN EFI_HANDLE Handle);
42 BOOLEAN EFIAPI HidI2cCheckInterrupt ( IN EFI_HANDLE Handle);
43 UINT16 EFIAPI HidI2cGetHidRegisterAddress ( IN EFI_HANDLE Handle);
44
45 typedef
46 UINT16
47 (EFIAPI *HID_I2C_GET_HID_REGISTER_ADDRESS)(
48 IN EFI_HANDLE Device
49 );
50 typedef
51 BOOLEAN
52 (EFIAPI *HID_I2C_CHECK_INTERRUPT)(
53 IN EFI_HANDLE Device
54 );
55 typedef
56 EFI_STATUS
57 (EFIAPI *HID_I2C_INITIALIZE)(
58 IN EFI_HANDLE Device
59 );
60
61 typedef struct {
62 HID_I2C_GET_HID_REGISTER_ADDRESS GetHidRegisterAddress;
63 HID_I2C_CHECK_INTERRUPT CheckInterrupt;
64 HID_I2C_INITIALIZE Initialize;
65 } HID_I2C_PLATFORM_SUPPORT;
66
67
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Hpet.h Source File

  • Acpi
  • AcpiTables
  • Hpet
Hpet.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI High Precision Event Timer Description Table
3 (HPET). All changes to the HPET contents should be done in this file.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 1999 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _HPET_H_
37 #define _HPET_H_
38
39 //
40 // Statements that include other files
41 //
42
43 #include <IndustryStandard/Acpi30.h>
44 #include <IndustryStandard/HighPrecisionEventTimerTable.h>
45
46 //
47 // HPET Definitions
48 //
49
50 #define EFI_ACPI_OEM_HPET_REVISION 0x00000001
51
52 #define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201
53
54 //
55 // Event Timer Block Base Address Information
56 //
57 #define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_3_0_SYSTEM_MEMORY
58 #define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x40
59 #define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00
60 #define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00
61 #define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS 0x00000000FED00000
62
63 #define EFI_ACPI_HPET_NUMBER 0x00
64
65 #define EFI_ACPI_MIN_CLOCK_TICK 0x0080
66
67 #define EFI_ACPI_HPET_ATTRIBUTES 0x00
68
69 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: HstiIbvFeatureBit.h Source File

HstiIbvFeatureBit.h
Go to the documentation of this file.
1 /** @file
2 This file contains various definitions for IHV HSTI implementation
3 including error string definitions
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2015 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification
34 **/
35
36 #ifndef __HSTI_FEATURE_BIT_H__
37 #define __HSTI_FEATURE_BIT_H__
38
39 #define HSTI_IMPLEMENTATION_ID_BROADWELL L"Intel(R) 9-Series v1"
40
41 #define HSTI_SECURITY_FEATURE_SIZE 3
42
43 #define HSTI_ERROR L"Error "
44 #define HSTI_PLATFORM_SECURITY_SPECIFICATION L" Platform Security Specification"
45
46 #define HSTI_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH L" - Firmware Trust Continuation Crypto Strength - "
47 #define HSTI_NO_TEST_KEY_VERIFICATION L" - No Test Key Verification - "
48 #define HSTI_FIRMWARE_VERSION_ROLLBACK_PROTECTION L" - Firmware Version Rollback Protection - "
49 #define HSTI_SECUREBOOT_BYPASS_CHECKING L" - SecureBoot Bypass Checking - "
50 #define HSTI_EXTERNAL_DEVICE_DMA_PROTECTION L" - External Device DMA Protection - "
51 #define HSTI_MOR_SUPPORT L" - MOR Support - "
52
53 #define HSTI_BYTE2_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH BIT0
54 #define HSTI_BYTE2_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH_ERROR_CODE_1 L"0x00100001"
55 #define HSTI_BYTE2_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH_ERROR_STRING_1 L"SHA1\r\n"
56
57 #define HSTI_BYTE2_NO_TEST_KEY_VERIFICATION BIT1
58 #define HSTI_BYTE2_NO_TEST_KEY_VERIFICATION_ERROR_CODE_1 L"0x00110001"
59 #define HSTI_BYTE2_NO_TEST_KEY_VERIFICATION_ERROR_STRING_1 L"fail\r\n"
60
61 #define HSTI_BYTE2_FIRMWARE_VERSION_ROLLBACK_PROTECTION BIT2
62 #define HSTI_BYTE2_FIRMWARE_VERSION_ROLLBACK_PROTECTION_ERROR_CODE_1 L"0x00120001"
63 #define HSTI_BYTE2_FIRMWARE_VERSION_ROLLBACK_PROTECTION_ERROR_STRING_1 L"fail\r\n"
64
65 #define HSTI_BYTE2_SECUREBOOT_BYPASS_CHECKING BIT3
66 #define HSTI_BYTE2_SECUREBOOT_BYPASS_CHECKING_ERROR_CODE_1 L"0x00130001"
67 #define HSTI_BYTE2_SECUREBOOT_BYPASS_CHECKING_ERROR_STRING_1 L"fail\r\n"
68
69
70 #define HSTI_BYTE2_EXTERNAL_DEVICE_DMA_PROTECTION BIT4
71 #define HSTI_BYTE2_EXTERNAL_DEVICE_DMA_PROTECTION_ERROR_CODE_1 L"0x00140001"
72 #define HSTI_BYTE2_EXTERNAL_DEVICE_DMA_PROTECTION_ERROR_STRING_1 L"unsupported\r\n"
73
74
75 #define HSTI_BYTE2_MOR_SUPPORT BIT5
76 #define HSTI_BYTE2_MOR_SUPPORT_ERROR_CODE_1 L"0x00150001"
77 #define HSTI_BYTE2_MOR_SUPPORT_ERROR_STRING_1 L"unsupported\r\n"
78
79
80 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: I2cAccessLib.h Source File

  • Library
I2cAccessLib.h
Go to the documentation of this file.
1 /** @file
2 Support for IO expander TCA6424.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Uefi.h>
36 #include <Library/DebugLib.h>
37 #include <Library/TimerLib.h>
38 #include <Library/IoLib.h>
39 #include <Library/UefiLib.h>
40 #include <PchAccess.h>
41 #include <Library/PchSerialIoLib.h>
42
43 #define WAIT_1_SECOND 1600000000 //1.6 * 10^9
44 #define MAX_DATA_COUNT 6
45 #define BLOCK_COMMAND_WAIT 0
46 #define BLOCK_COMMAND_I2C_READ 1
47 #define BLOCK_COMMAND_I2C_WRITE 2
48
49 EFI_STATUS
50 I2cWriteRead (
51 IN UINTN MmioBase,
52 IN UINT8 SlaveAddress,
53 IN UINT8 WriteLength,
54 IN UINT8 *WriteBuffer,
55 IN UINT8 ReadLength,
56 IN UINT8 *ReadBuffer,
57 IN UINT64 TimeBudget
58 );
59
60 EFI_STATUS
61 I2cBlockWriteRead(
62 IN PCH_SERIAL_IO_CONTROLLER,
63 IN UINT8 SlaveAddress,
64 IN UINT8 *I2cCommandBlock,
65 IN UINT32 BlockSize
66 );
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: I2cBusConfigurationManagement.h Source File

  • Protocol
I2cBusConfigurationManagement.h
Go to the documentation of this file.
1 /** @file
2 I2C bus configuration management interface
3
4 The I2C host driver uses this API to configure the
5 switches and multiplexers in the I2C bus to gain access
6 to the desired I2C device at its maximum clock frequency.
7
8 @copyright
9 INTEL CONFIDENTIAL
10 Copyright 2012 - 2016 Intel Corporation.
11
12 The source code contained or described herein and all documents related to the
13 source code ("Material") are owned by Intel Corporation or its suppliers or
14 licensors. Title to the Material remains with Intel Corporation or its suppliers
15 and licensors. The Material may contain trade secrets and proprietary and
16 confidential information of Intel Corporation and its suppliers and licensors,
17 and is protected by worldwide copyright and trade secret laws and treaty
18 provisions. No part of the Material may be used, copied, reproduced, modified,
19 published, uploaded, posted, transmitted, distributed, or disclosed in any way
20 without Intel's prior express written permission.
21
22 No license under any patent, copyright, trade secret or other intellectual
23 property right is granted to or conferred upon you by disclosure or delivery
24 of the Materials, either expressly, by implication, inducement, estoppel or
25 otherwise. Any license under such intellectual property rights must be
26 express and approved by Intel in writing.
27
28 Unless otherwise agreed by Intel in writing, you may not remove or alter
29 this notice or any other notice embedded in Materials by Intel or
30 Intel's suppliers or licensors in any way.
31
32 This file contains a 'Sample Driver' and is licensed as such under the terms
33 of your license agreement with Intel or your vendor. This file may be modified
34 by the user, subject to the additional terms of the license agreement.
35
36 @par Specification Reference:
37
38 **/
39
40 #ifndef __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
41 #define __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
42
43 #include <Protocol/I2cMaster.h>
44
45 ///
46 /// I2C bus configuration management protocol
47 ///
48 /// The I2C driver stack uses the concept of an I2C bus configuration
49 /// as a way to describe a particular state of the switches and
50 /// multiplexers in the I2C bus.
51 ///
52 /// A simple I2C bus does not have any multiplexers or switches is
53 /// described to the I2C driver stack with a single I2C bus configuration.
54 ///
55 /// An I2C bus with switches and multiplexers use an I2C bus configuration
56 /// to describe each of the unique settings for the switches and multiplexers.
57 /// However the I2C platform driver only needs to define the I2C bus
58 /// configurations that the software uses, which is a subset of the
59 /// total.
60 ///
61 /// The I2C bus configuration description includes a list of I2C devices
62 /// which may be accessed when this I2C bus configuration is enabled.
63 /// I2C devices before a switch or multiplexer should be included in one
64 /// I2C bus configuration while I2C devices after a switch or multiplexer
65 /// should be on another I2C bus configuration.
66 ///
67 /// The I2C bus configuration management protocol is an optional
68 /// protocol provided by the I2C platform driver. When the I2C bus
69 /// configuration protocol is not defined the host driver assumes a
70 /// single I2C bus configuration and operates the I2C bus at 100 KHz.
71 /// When the I2C bus configuration protocol is available, the I2C host
72 /// driver uses the I2C bus configuration protocol to call into the
73 /// I2C platform driver to set the switches and multiplexers and set
74 /// the maximum I2C bus frequency.
75 ///
76 /// The platform designers determine the maximum I2C bus frequency by
77 /// selecting a frequency which supports all of the I2C devices on the
78 /// I2C bus for the setting of switches and multiplexers. The platform
79 /// designers must validate this against the I2C device data sheets and
80 /// any limits of the I2C controller or bus length.
81 ///
82 /// The I2C host driver uses an index into a list or array of I2C bus
83 /// configurations to keep the platform implementation hidden from the
84 /// rest of the I2C stack. The protocol exposes BusConfigurationCount
85 /// to enable the I2C host driver to perform bounds checking on the I2C
86 /// bus configuration value supplied by the upper layers. The I2C bus
87 /// layer also is told during the I2C device enumeration which I2C bus
88 /// configuration is in use for each of the I2C devices. While this
89 /// is hidden from the upper layers the I2C bus configuration is
90 /// provided to the I2C host driver when performing I2C requests.
91 ///
92 /// When the I2C bus configuration protocol is available, the I2C host
93 /// driver calls EnableBusConfiguration to enable access to the necessary
94 /// I2C bus configuration. This host driver may optimize calls to
95 /// EnableBusConfiguration by only calling the routine only when the I2C
96 /// bus configuration value changes between I2C requests.
97 ///
98 /// When I2C operations are necessary on the same I2C bus to change I2C
99 /// GPIO devices, multiplexers or switches, the I2C platform layer uses
100 /// the I2C master protocol to perform the necessary I2C operations.
101 ///
102 /// It is up to the I2C platform driver to choose the proper I2C bus
103 /// configuration when ExitBootServices is called.
104 ///
105 typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL;
106
107
108 /**
109 Enable access to an I2C bus configuration.
110
111 This routine must be called at or below TPL_NOTIFY. For synchronous
112 requests this routine must be called at or below TPL_CALLBACK.
113
114 Reconfigure the switches and multiplexers in the I2C bus to enable
115 access to a specific I2C bus configuration. Also select the maximum
116 clock frequency for this I2C bus configuration.
117
118 This routine uses the I2cMaster protocol when the platform routine
119 needs to perform I2C operations on the local bus. This eliminates
120 any recursion in the I2C stack for configuration operations on the
121 local bus. This works because the local I2C bus is idle while the
122 I2C bus configuration is being enabled.
123
124 The platform layer must perform I2C operations on other I2C busses
125 by using the EFI_I2C_HOST_PROTOCOL or third party driver interface
126 for the specific device. This requirement is because the I2C host
127 driver controls the flow of requests to the I2C conroller. Use the
128 EFI_I2C_HOST_PROTOCOL when the device is not defined in the platform's
129 ACPI tables. Use the third party driver when it is available or
130 EFI_I2C_BUS_PROTOCOL when the thrid party driver is not available
131 but the device is defined in the platform's ACPI tables.
132
133 @param[in] This Address of an EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
134 structure
135 @param[in] I2cBusConfiguration Index into a list or array of I2C bus
136 configurations.
137 @param[in] I2cMaster Address of an EFI_I2C_MASTER_PROTOCOL
138 structure. This protocol may only be used
139 for this specific operation and should not
140 be referenced after this operation completes!
141 @param[in] Event Event to set when the operation is
142 complete.
143 @param[out] Status Buffer to receive the operation
144 status.
145
146 @retval EFI_SUCCESS The operation completed successfully.
147 @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.
148 This could indicate the slave device is not present.
149 @retval EFI_INVALID_PARAMETER I2cMaster is NULL
150 @retval EFI_INVALID_PARAMETER TPL is too high
151 @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value
152 @retval EFI_NO_RESPONSE The I2C device is not responding to the
153 slave address. EFI_DEVICE_ERROR may also be
154 returned if the controller can not distinguish
155 when the NACK occurred.
156 @retval EFI_NOT_FOUND I2C slave address exceeds maximum address
157 @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
158 the event and then read status.
159 @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
160 @retval EFI_TIMEOUT The transaction did not complete within an internally
161 specified timeout period.
162
163 **/
164 typedef
165 EFI_STATUS
166 (EFIAPI *EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION) (
167 IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This,
168 IN UINTN I2cBusConfiguration,
169 IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster,
170 IN EFI_EVENT Event OPTIONAL,
171 IN EFI_STATUS *Status OPTIONAL
172 );
173
174
175 ///
176 /// I2C bus configuration management protocol
177 ///
178 struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL {
179 ///
180 /// Enable an I2C bus configuration for use
181 ///
182 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration;
183
184 ///
185 /// Number of switch and multiplexer configurations for this
186 /// I2C bus.
187 ///
188 UINTN I2cBusConfigurationCount;
189 };
190
191 #endif // __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
_EFI_I2C_MASTER_PROTOCOL
I2C master mode protocol.
Definition: I2cMaster.h:511
I2cMaster.h
I2C Master interface.
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL::EnableI2cBusConfiguration
EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration
Enable an I2C bus configuration for use.
Definition: I2cBusConfigurationManagement.h:182
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2C bus configuration management protocol.
Definition: I2cBusConfigurationManagement.h:178
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL::I2cBusConfigurationCount
UINTN I2cBusConfigurationCount
Number of switch and multiplexer configurations for this I2C bus.
Definition: I2cBusConfigurationManagement.h:188
EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION
EFI_STATUS(* EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION)(IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, IN UINTN I2cBusConfiguration, IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster, IN EFI_EVENT Event OPTIONAL, IN EFI_STATUS *Status OPTIONAL)
Enable access to an I2C bus configuration.
Definition: I2cBusConfigurationManagement.h:166
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: I2cMaster.h Source File

  • Protocol
I2cMaster.h
Go to the documentation of this file.
1 /** @file
2 I2C Master interface
3
4 A driver or application uses the I2C master protocol to
5 manage the master mode of an I2C controller. Note that
6 access is restricted to the current configuration of the I2C
7 bus.
8
9 \section I2cDriverStack I2C Driver Stack
10
11 The following is a representation of the I<sup>2</sup>C (I2C)
12 driver stack and an I2C bus layout.
13
14 <code><pre>
15 +-----------------+
16 | Application |
17 +-----------------+
18 |
19 | Third Party or UEFI
20 |
21 V
22 +--------+ +-----------------+
23 | Slave | | Third Party |
24 | Driver | | I2C Device |
25 | | | Driver |
26 +--------+ +-----------------+
27 | |
28 | BUS |
29 | |
30 | V
31 | +-----------------+
32 | | I2C Bus Driver |------------------.
33 | +-----------------+ |
34 | | |
35 | HOST | BUS |
36 | | CONFIGURATION |
37 SLAVE | V MANAGEMENT | ACPI
38 | +-----------------+ |
39 | | I2C Host Driver |----------. |
40 | +-----------------+ | |
41 | | | |
42 | MASTER | V V
43 | | +-------=-------------+
44 | V | I2C Platform Driver |
45 | +-----------------+ +---------------------+
46 `------>| I2C Port Driver | | |
47 +-----------------+ | |
48 | | |
49 Software | | |
50 --------------------------------------------------
51 Hardware | | |
52 | | |
53 V | |
54 +-----------------+ | |
55 | I2C Controller | | |
56 +-----------------+ | |
57 | | |
58 ----------------------- | |
59 I2C Bus | | |
60 | +------------+ | |
61 +----| High speed | | |
62 | | I2C device | | |
63 | | 0x01 | | |
64 | +------------+ | |
65 | | |
66 +---------+ 0 | |
67 | Switch |<------------------` |
68 +---------+ 1 |
69 | |
70 | +------------+ |
71 +----| Fast speed | |
72 | | I2C device | |
73 | | 0x02 | |
74 | +------------+ |
75 | |
76 +-------------+ |
77 | Multiplexer |<-----------------------`
78 +-------------+
79 0 | | 1
80 | |
81 | |
82 | | +-------------+
83 | +----| Third Party |
84 | | | I2C Device |
85 | | | 0x03, 0x04 |
86 | | +-------------+
87 | |
88 |
89 | +-------------+
90 +------------| Third Party |
91 | | I2C Device |
92 | | 0x03, 0x04 |
93 | +-------------+
94 |
95 </pre></code>
96
97 The platform hardware designer chooses the bus layout based upon
98 the platform, I2C chip and software requirements. The design uses
99 switches to truncate the bus to enable higher speed operation for a
100 subset of devices which are placed closer to the controller. When the
101 switch is on, the extended bus must operate at a lower speed. The
102 design uses multiplexer to create separate address spaces enabling
103 the use of multiple devices which would otherwise have conflicting
104 addresses. See the
105 <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup>2</sup>C
106 Specification</a> for more details.
107
108 N.B. Some operating systems may prohibit the changing of switches
109 and multiplexers in the I2C bus. In this case the platform hardware
110 and software designers must select a single I2C bus configuration
111 consisting of constant input values for the switches and multiplexers.
112 The platform software designer must then ensure that this I2C bus
113 configuration is enabled prior to passing control to the operating
114 system.
115
116 The platform hardware designer needs to provide the platform software
117 designer the following data for each I2C bus:
118
119 1. Which controller controls this bus
120
121 2. A list of logic blocks contained in one or more I2C devices:
122
123 a. I2C device which contains this logic block
124
125 b. Logic block slave address
126
127 c. Logic block name
128
129 3. For each configuration of the switches and multiplexer
130
131 a. What is the maximum speed of operation
132
133 b. What devices are accessible
134
135 4. The settings for the switches and multiplexers when control is
136 given to the operating system.
137
138 \section ThirdPartyI2cDrivers Third Party I2C Drivers
139
140 This layer is I2C chip specific but platform and host controller
141 independent.
142
143 Third party I2C driver writers, typically silicon vendors, need
144 to provide:
145
146 1. The device path node data that is used to select their
147 driver.
148
149 2. The order for the blocks of logic that get referenced
150 by the entries in the slave address array.
151
152 3. The hardware version of the I2C device, this value is passed
153 to the third party I2C driver to enable it to perform work
154 arounds for the specific hardware version. This value should
155 match the value in the ACPI _HRV tag.
156
157 The third party I2C driver uses relative addressing to abstract
158 the platform specific details of the I2C device. Using an
159 example I2C device containing an accelerometer and a magnetometer
160 which consumes two slave addresses, one for each logic block. The
161 third party I2C driver writer may choose to write two drivers, one
162 for each block of logic, in which case each driver refers to the
163 single I2C slave address using the relative value of zero (0).
164 However if the third party I2C driver writer chooses to write a
165 single driver which consumes multiple slave addresses then the
166 third party I2C driver writer needs to convey the order of the
167 I2C slave address entries in the slave address array to the
168 platform software designer. For the example:
169
170 0: Accelerometer
171
172 1: Magnetometer
173
174 The platform hardware designer picks the actual slave addresses
175 from the I2C device's data sheet and provides this information
176 to the platform software designer. The platform software designer
177 then places the slave addresses into the slave address array in the
178 order specified by the third party I2C driver writer. The third
179 party driver I2C writer then indirectly references this array by
180 specifying the index value as the relative slave address. The
181 relative value always starts at zero (0) and its maximum value is
182 the number of entries in slave address array minus one.
183
184 The slave address is specified as a 32-bit integer to allow room
185 for future slave address expansion. Only the port driver knows
186 the maximum slave address value. All other drivers and
187 applications must look for the EFI_NOT_FOUND status for the
188 indication that the maximum slave address was exceeded.
189
190 \section I2cBusDriver I2C Bus Driver
191
192 This layer is platform, host controller, and I2C chip independent.
193
194 The I2C bus driver creates a handle for each of the I2C devices
195 described within the platform driver. The I2C controller's device
196 path is extended with the device path node provided by the platform
197 driver and attached to the handle. The third party I2C device driver
198 uses the device path to determine if it may connect. For ACPI nodes,
199 the third party I2C driver should use the CID or CidString value.
200
201 The I2C bus driver validates the relative address for the I2C device
202 and then converts the relative value to an actual I2C slave address.
203 The request is then passed to the I2C host driver.
204
205 \section I2cHostDriver I2C Host Driver
206
207 This layer is platform, host controller, and I2C chip independent.
208
209 N.B. For proper operation of the I2C bus, only the I2C bus driver
210 and the I2C test application should connect to the I2C host driver
211 via the EFI_I2C_HOST_DRIVER_PROTOCOL.
212
213 The I2C host driver may access any device on the I2C bus. The I2C
214 host driver has the following responsibilities:
215
216 1. Limits the number of requests to the I2C port driver to one.
217 The I2C host driver holds on to additional requests until the
218 I2C port driver is available to process the request. The I2C
219 requests are issued in FIFO order to the I2C port driver.
220
221 2. Enable the proper I2C bus configuration before starting the
222 I2C request on the I2C port driver
223
224 I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress.
225 I2C bus configuration zero (0) is the portion of the I2C bus that
226 connects to the host controller. The bus configuration specifies
227 the control values for the switches and multiplexers in the I2C bus.
228 After the switches and multiplexers are properly configured, the I2C
229 controller uses the slave address to access the requested I2C device.
230
231 Since the I2C driver stack supports asynchronous operations this
232 layer maintains a queue of I2C requests until the I2C controller
233 is available them. When a request reaches the head of the queue
234 the necessary bus configuration is enabled and then the request
235 is sent to the I2C port driver.
236
237 \section I2cPortDriver I2C Port Driver
238
239 This layer is I2C controller specific but platform independent.
240
241 This layer manipulates the I2C controller to perform an operation
242 on the I2C bus. This layer does not configure the I2C bus so it
243 is up to the caller to ensure that the I2C bus is in the proper
244 configuration before issuing the I2C request.
245
246 This layer typically needs the following information:
247
248 1. Host controller address
249 2. Controller's input clock frequency
250
251 Depending upon the I2C controller, more data may be necessary.
252 This layer may use any method to get these values: hard coded
253 values, PCD values, or may choose to communicate with the platform
254 layer using an undefined mechanism to get these values.
255
256 If the I2C port driver requires data from the platform driver then
257 the I2C port driver writer needs to provide the platform interface
258 details to the platform software designer.
259
260 \section I2cPlatformDriver I2C Platform Driver
261
262 When enabling access to I2C devices within UEFI, this driver
263 installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device
264 descriptions to the I2C bus driver using the EFI_I2C_DEVICE
265 structure. These descriptions include the bus configuration
266 number required for the I2C device, the slave address array
267 and the device path.
268
269 The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional.
270 This protocol needs to be specified under the following conditions:
271
272 1. The I2C bus must operate at a frequency greater than 100 KHz
273 2. The I2C bus contains switches or multiplexers.
274
275 The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the
276 I2C host driver to call into the I2C platform driver to enable
277 a specific I2C bus configuration and set its maximum clock speed.
278
279 The platform software designer collects the data requirements
280 from third party I2C driver writers, the I2C controller
281 driver writer, the EFI_I2C_ACPI_PROTOCOL and
282 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL. The platform
283 software designer gets the necessary data from the platform
284 hardware designer. The platform software designer then builds
285 the data structures and implements the necessary routines to
286 construct the I2C platform driver.
287
288 \section I2cSwitches Switches and Multiplexers
289
290 There are some I2C switches and I2C multiplexers where the control
291 is done via I2C commands. When the control inputs come via the
292 same I2C bus that is being configured then the platform driver must
293 use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform
294 driver. While the I2C host driver makes the call to the I2C
295 platform driver to configure the bus, the host driver keeps the
296 I2C port driver idle, to allow the I2C platform driver preform
297 the necessary configuration operations.
298
299 If however the configuration control is done via and I2C device
300 connected to a different I2C bus (host controller), then it is
301 possible for the platform software designer may choose between
302 the following:
303
304 1. Call into a third party I2C driver to manipulate the I2C
305 bus control device.
306 2. Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C
307 driver exists for the I2C bus control device
308 3. Call into the EFI_I2C_HOST_PROTOCOL if the platform does
309 not expose the I2C bus control device.
310
311 @copyright
312 INTEL CONFIDENTIAL
313 Copyright 2012 - 2016 Intel Corporation.
314
315 The source code contained or described herein and all documents related to the
316 source code ("Material") are owned by Intel Corporation or its suppliers or
317 licensors. Title to the Material remains with Intel Corporation or its suppliers
318 and licensors. The Material may contain trade secrets and proprietary and
319 confidential information of Intel Corporation and its suppliers and licensors,
320 and is protected by worldwide copyright and trade secret laws and treaty
321 provisions. No part of the Material may be used, copied, reproduced, modified,
322 published, uploaded, posted, transmitted, distributed, or disclosed in any way
323 without Intel's prior express written permission.
324
325 No license under any patent, copyright, trade secret or other intellectual
326 property right is granted to or conferred upon you by disclosure or delivery
327 of the Materials, either expressly, by implication, inducement, estoppel or
328 otherwise. Any license under such intellectual property rights must be
329 express and approved by Intel in writing.
330
331 Unless otherwise agreed by Intel in writing, you may not remove or alter
332 this notice or any other notice embedded in Materials by Intel or
333 Intel's suppliers or licensors in any way.
334
335 This file contains a 'Sample Driver' and is licensed as such under the terms
336 of your license agreement with Intel or your vendor. This file may be modified
337 by the user, subject to the additional terms of the license agreement.
338
339 @par Specification Reference:
340
341 **/
342
343 #ifndef __I2C_MASTER_H__
344 #define __I2C_MASTER_H__
345
346 // @todo: do the integration with the I2cMaster.h from MdePkg.
347
348 /**
349 Declare the forward references
350
351 **/
352 typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL; ///< I2C master protocol
353
354 ///
355 /// I2C device operation
356 ///
357 /// This structure provides the information necessary for an operation
358 /// on an I2C device
359 ///
360 typedef struct {
361 ///
362 /// Number of bytes to send to the I2C device
363 ///
364 UINT32 WriteBytes;
365
366 ///
367 /// Number of bytes to read, set to zero for write only operations
368 ///
369 UINT32 ReadBytes;
370
371 ///
372 /// Address of the buffer containing the data to send to the I2C device.
373 /// The WriteBuffer must be at least WriteBytes in length.
374 ///
375 UINT8 *WriteBuffer;
376
377 ///
378 /// Address of the buffer to receive data from the I2C device. Use NULL
379 /// for write only operations. The ReadBuffer must be at least ReadBytes
380 /// in length.
381 ///
382 UINT8 *ReadBuffer;
383
384 ///
385 /// Timeout for the I2C operation in 100 ns units
386 ///
387 UINT32 Timeout;
388 } EFI_I2C_REQUEST_PACKET;
389
390
391 /**
392 Set the I2C controller bus clock frequency.
393
394 This routine must be called at or below TPL_NOTIFY.
395
396 The software and controller do a best case effort of using the specified
397 frequency for the I2C bus. If the frequency does not match exactly then
398 the controller will use a slightly lower frequency to avoid
399 exceeding the operating conditions for any of the I2C devices on the bus.
400 For example if 400 KHz was specified and the controller's divide network
401 only supports 402 KHz or 398 KHz then the controller would be set to 398
402 KHz. However if the desired frequency is 400 KHz and the controller only
403 supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTED.
404
405 @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
406 structure
407 @param[in] BusClockHertz New I2C bus clock frequency in Hertz
408
409 @retval EFI_SUCCESS The bus frequency was set successfully.
410 @retval EFI_UNSUPPORTED The controller does not support this frequency.
411
412 **/
413 typedef
414 EFI_STATUS
415 (EFIAPI *EFI_I2C_MASTER_BUS_FREQUENCY_SET) (
416 IN CONST EFI_I2C_MASTER_PROTOCOL *This,
417 IN UINTN BusClockHertz
418 );
419
420 /**
421 Reset the I2C controller and configure it for use
422
423 This routine must be called at or below TPL_NOTIFY.
424
425 The I2C controller is reset and the I2C bus frequency is set to 100 KHz.
426
427 @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
428 structure
429
430 **/
431 typedef
432 VOID
433 (EFIAPI *EFI_I2C_MASTER_RESET) (
434 IN CONST EFI_I2C_MASTER_PROTOCOL *This
435 );
436
437 /**
438 Start an I2C operation on the host controller
439
440 This routine must be called at or below TPL_NOTIFY. For synchronous
441 requests this routine must be called at or below TPL_CALLBACK.
442
443 This function initiates an I2C operation on the controller.
444
445 The operation is performed by selecting the I2C device with its slave
446 address and then sending all write data to the I2C device. If read data
447 is requested, a restart is sent followed by the slave address and then
448 the read data is clocked into the I2C controller and placed in the read
449 buffer. When the operation completes, the status value is returned and
450 then the event is set.
451
452 N.B. The typical consumer of this API is the I2C host driver.
453 Extreme care must be taken by other consumers of this API to
454 prevent confusing the third party I2C drivers due to a state
455 change at the I2C device which the third party I2C drivers did
456 not initiate. I2C platform drivers may use this API within
457 these guidelines.
458
459 N.B. This API supports only one operation, no queuing support
460 exists at this layer. This API assumes that the I2C bus is in
461 the correct configuration for the I2C request.
462
463 @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
464 structure
465 @param[in] SlaveAddress Address of the device on the I2C bus.
466 @param[in] Event Event to set for asynchronous operations,
467 NULL for synchronous operations
468 @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
469 structure describing the I2C operation
470 @param[out] I2cStatus Optional buffer to receive the I2C operation
471 completion status
472
473 @retval EFI_SUCCESS The operation completed successfully.
474 @retval EFI_ABORTED The request did not complete because the driver
475 was shutdown.
476 @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.
477 @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.
478 This could indicate the slave device is not present.
479 @retval EFI_INVALID_PARAMETER RequestPacket is NULL
480 @retval EFI_INVALID_PARAMETER TPL is too high
481 @retval EFI_NOT_FOUND SlaveAddress exceeds maximum address
482 @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
483 the event and then read status pointed to by
484 the request packet.
485 @retval EFI_NO_RESPONSE The I2C device is not responding to the
486 slave address. EFI_DEVICE_ERROR may also be
487 returned if the controller cannot distinguish
488 when the NACK occurred.
489 @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
490 @retval EFI_TIMEOUT The transaction did not complete within an internally
491 specified timeout period.
492
493 **/
494 typedef
495 EFI_STATUS
496 (EFIAPI *EFI_I2C_MASTER_START_REQUEST) (
497 IN CONST EFI_I2C_MASTER_PROTOCOL *This,
498 IN UINTN SlaveAddress,
499 IN EFI_EVENT Event OPTIONAL,
500 IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
501 OUT EFI_STATUS *I2cStatus OPTIONAL
502 );
503
504 ///
505 /// I2C master mode protocol
506 ///
507 /// This protocol manipulates the I2C host controller to perform transactions as a
508 /// master on the I2C bus using the current state of any switches or multiplexers
509 /// in the I2C bus.
510 ///
511 struct _EFI_I2C_MASTER_PROTOCOL {
512 ///
513 /// Set the clock frequency for the I2C bus
514 ///
515 EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet;
516
517 ///
518 /// Reset the I2C host controller
519 ///
520 EFI_I2C_MASTER_RESET Reset;
521
522 ///
523 /// Start an I2C transaction in master mode on the host controller
524 ///
525 EFI_I2C_MASTER_START_REQUEST StartRequest;
526
527 ///
528 /// The maximum number of bytes the I2C host controller
529 /// is able to receive from the I2C bus.
530 ///
531 UINT32 MaximumReceiveBytes;
532
533 ///
534 /// The maximum number of bytes the I2C host controller
535 /// is able to send on the I2C bus.
536 ///
537 UINT32 MaximumTransmitBytes;
538
539 ///
540 /// The maximum number of bytes in the I2C bus transaction.
541 ///
542 UINT32 MaximumTotalBytes;
543 };
544
545 #endif // __I2C_MASTER_H__
_EFI_I2C_MASTER_PROTOCOL
I2C master mode protocol.
Definition: I2cMaster.h:511
EFI_I2C_REQUEST_PACKET::ReadBytes
UINT32 ReadBytes
Number of bytes to read, set to zero for write only operations.
Definition: I2cMaster.h:369
_EFI_I2C_MASTER_PROTOCOL::Reset
EFI_I2C_MASTER_RESET Reset
Reset the I2C host controller.
Definition: I2cMaster.h:520
_EFI_I2C_MASTER_PROTOCOL::StartRequest
EFI_I2C_MASTER_START_REQUEST StartRequest
Start an I2C transaction in master mode on the host controller.
Definition: I2cMaster.h:525
_EFI_I2C_MASTER_PROTOCOL::BusFrequencySet
EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet
Set the clock frequency for the I2C bus.
Definition: I2cMaster.h:515
EFI_I2C_REQUEST_PACKET::WriteBytes
UINT32 WriteBytes
Number of bytes to send to the I2C device.
Definition: I2cMaster.h:364
_EFI_I2C_MASTER_PROTOCOL::MaximumReceiveBytes
UINT32 MaximumReceiveBytes
The maximum number of bytes the I2C host controller is able to receive from the I2C bus...
Definition: I2cMaster.h:531
_EFI_I2C_MASTER_PROTOCOL::MaximumTransmitBytes
UINT32 MaximumTransmitBytes
The maximum number of bytes the I2C host controller is able to send on the I2C bus.
Definition: I2cMaster.h:537
EFI_I2C_REQUEST_PACKET
I2C device operation.
Definition: I2cMaster.h:360
_EFI_I2C_MASTER_PROTOCOL::MaximumTotalBytes
UINT32 MaximumTotalBytes
The maximum number of bytes in the I2C bus transaction.
Definition: I2cMaster.h:542
EFI_I2C_REQUEST_PACKET::ReadBuffer
UINT8 * ReadBuffer
Address of the buffer to receive data from the I2C device.
Definition: I2cMaster.h:382
EFI_I2C_MASTER_BUS_FREQUENCY_SET
EFI_STATUS(* EFI_I2C_MASTER_BUS_FREQUENCY_SET)(IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN BusClockHertz)
Set the I2C controller bus clock frequency.
Definition: I2cMaster.h:415
EFI_I2C_REQUEST_PACKET::Timeout
UINT32 Timeout
Timeout for the I2C operation in 100 ns units.
Definition: I2cMaster.h:387
EFI_I2C_MASTER_START_REQUEST
EFI_STATUS(* EFI_I2C_MASTER_START_REQUEST)(IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN SlaveAddress, IN EFI_EVENT Event OPTIONAL, IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, OUT EFI_STATUS *I2cStatus OPTIONAL)
Start an I2C operation on the host controller.
Definition: I2cMaster.h:496
EFI_I2C_REQUEST_PACKET::WriteBuffer
UINT8 * WriteBuffer
Address of the buffer containing the data to send to the I2C device.
Definition: I2cMaster.h:375
EFI_I2C_MASTER_RESET
VOID(* EFI_I2C_MASTER_RESET)(IN CONST EFI_I2C_MASTER_PROTOCOL *This)
Reset the I2C controller and configure it for use.
Definition: I2cMaster.h:433
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: I2cMmioConfigLib.h Source File

  • Library
I2cMmioConfigLib.h
Go to the documentation of this file.
1 /** @file
2 Memory mapped I/O specific configuration declarations
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _I2C_MMIO_CONFIG_LIB_H_
37 #define _I2C_MMIO_CONFIG_LIB_H_
38
39 #include <Protocol/MmioDevice.h>
40
41 ///
42 /// Declare the memory mapped I/O devices assocaited with the
43 /// board.
44 ///
45 extern CONST EFI_MMIO_DEVICE_PROTOCOL gMmioDeviceList [ ];
46 extern CONST UINTN gMmioDeviceCount;
47
48 #endif // _I2C_MMIO_CONFIG_LIB_H_
gMmioDeviceList
CONST EFI_MMIO_DEVICE_PROTOCOL gMmioDeviceList[]
Declare the memory mapped I/O devices assocaited with the board.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: IccOverClocking.h Source File

  • Protocol
IccOverClocking.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2010 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _ICC_OVERCLOCKING_H_
36 #define _ICC_OVERCLOCKING_H_
37
38 /* Types used by ICC LIB */
39
40 typedef enum _ICC_LIB_STATUS
41 {
42 ICC_LIB_STATUS_SUCCESS,
43 ICC_LIB_STATUS_INVALID_PARAMS,
44 ICC_LIB_STATUS_INVALID_CLOCK_NUMBER,
45 ICC_LIB_STATUS_CLOCK_NOT_FOUND,
46 ICC_LIB_STATUS_INVALID_FREQ_VALUE,
47 ICC_LIB_STATUS_FREQ_TOO_LOW,
48 ICC_LIB_STATUS_FREQ_TOO_HIGH,
49 ICC_LIB_STATUS_FREQ_MUST_HAVE_ZERO_SSC,
50 ICC_LIB_STATUS_SSC_CHANGE_NOT_ALLOWED,
51 ICC_LIB_STATUS_INVALID_SSC_MODE,
52 ICC_LIB_STATUS_SSC_MODE_NOT_SUPPORTED,
53 ICC_LIB_STATUS_SSC_OUT_OF_RANGE,
54 ICC_LIB_STATUS_SSC_TOO_HIGH,
55 ICC_LIB_STATUS_SSC_TOO_LOW,
56 ICC_LIB_STATUS_SSC_CHANGE_NOT_ALLOWED_SSC_DISABLED,
57 ICC_LIB_STATUS_DYNAMIC_CHANGE_NOT_ALLOWED,
58 ICC_LIB_STATUS_INVALID_DMI_PEG_RATIO,
59 ICC_LIB_STATUS_REGISTER_IS_LOCKED,
60 ICC_LIB_STATUS_MEI_INITIALIZATION_FAILED,
61 ICC_LIB_STATUS_MEI_CONNECTION_FAILED,
62 ICC_LIB_STATUS_UNEXPECTED_FW_ERROR,
63 ICC_LIB_STATUS_UNSUPPORTED_HW,
64 ICC_LIB_STATUS_CLOCK_DISABLED_FAILED_PROGRAMMING,
65 ICC_LIB_STATUS_FREQ_AND_SSC_NOT_MATCH,
66 ICC_LIB_STATUS_WAITING_FOR_WARM_RESET,
67 ICC_LIB_STATUS_NOT_ALLOWED_IN_USER_MODE,
68 ICC_LIB_STATUS_TOO_MANY_CONNECTIONS,
69 ICC_LIB_STATUS_INVALID_COOKIE,
70 ICC_LIB_STATUS_DMI_PEG_RATIO_CHANGE_NOT_ALLOWED,
71 ICC_LIB_STATUS_NO_USAGE_DEFINED_FOR_THE_CLOCK,
72 ICC_LIB_STATUS_DATA_NOT_AVAILABLE,
73
74 ICC_LIB_STATUS_UNSPECIFIED_ERROR = 0xFFFF
75 } ICC_LIB_STATUS;
76
77 typedef enum _ICC_CLOCK_USAGE
78 {
79 ICC_CLOCK_USAGE_BCLK = 0,
80 ICC_CLOCK_USAGE_DMI,
81 ICC_CLOCK_USAGE_PEG,
82 ICC_CLOCK_USAGE_PCIE,
83 ICC_CLOCK_USAGE_PCI33,
84 ICC_CLOCK_USAGE_RESERVED,
85 ICC_CLOCK_USAGE_SATA,
86 ICC_CLOCK_USAGE_USB3,
87 ICC_CLOCK_USAGE_DISPLAY,
88 ICC_CLOCK_USAGE_DISPLAY_NON_SPREAD,
89 ICC_CLOCK_USAGE_27MHZ_DOWN_GFX,
90 ICC_CLOCK_USAGE_DISPLAY_VGA,
91 ICC_CLOCK_USAGE_USB_LEGACY,
92 ICC_CLOCK_USAGE_14_31818_MHZ
93 } ICC_CLOCK_USAGE;
94
95 // @brief Defines a generic version structure used in the software build process.
96 typedef struct _ICC_LIB_VERSION
97 {
98 UINT16 Major;
99 UINT16 Minor;
100 UINT16 Hotfix;
101 UINT16 Build;
102 } ICC_LIB_VERSION;
103
104 typedef UINT32 ICC_CLOCK_FREQUENCY;
105
106 typedef UINT16 ICC_CLOCK_USAGE_MASK;
107
108 typedef struct _ICC_CLOCK_RANGES
109 {
110 ICC_CLOCK_FREQUENCY FrequencyMin;
111 ICC_CLOCK_FREQUENCY FrequencyMax;
112 UINT8 SscChangeAllowed;
113 UINT8 SscUpAllowed;
114 UINT8 SscCenterAllowed;
115 UINT8 SscDownAllowed;
116 UINT8 SscPercentMax;
117 // that field is actually still a bit mask, but usually applications will never use it.
118 ICC_CLOCK_USAGE_MASK UsageMask;
119 UINT8 SscHaltAllowed;
120 } ICC_CLOCK_RANGES;
121
122 typedef UINT8 ICC_CLOCK_ID;
123
124 typedef UINT32 ICC_CLOCK_ID_MASK;
125
126 typedef enum _ICC_RECORD_INVALIDATION_REASON
127 {
128 ICC_LIB_RIR_RECORD_VALID = 0,
129 ICC_LIB_RIR_AC_POWER_LOSS,
130 ICC_LIB_RIR_BOOT_WITH_DEFAULT,
131 ICC_LIB_RIR_PLATFORM_BOOT_TIMEOUT,
132 ICC_LIB_RIR_WDT_EXPIRED,
133 ICC_LIB_RIR_RESERVED,
134 ICC_LIB_RIR_INVALIDATE_BY_REQUEST,
135 ICC_LIB_RIR_FW_BUG
136 } ICC_RECORD_INVALIDATION_REASON;
137
138 #endif /* _ICC_OVERCLOCKING_H_ */
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: IccSetupData.h Source File

IccSetupData.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __ICC_SETUP_DATA_H__
35 #define __ICC_SETUP_DATA_H__
36
37 #define MAX_UI_CLOCKS 2
38
39 #define CLOCK1 1
40
41 #define INTEL_ICC_GUID \
42 {0x64192dca, 0xd034, 0x49d2, 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}
43
44 #define DONT_DISPLAY 0
45 #define DISPLAY 1
46
47 #define OPTION_DISABLED 0
48 #define OPTION_ENABLED 1
49
50 #define OPTION_LOCK_DEFAULT 0
51 #define OPTION_LOCK_ALL 1
52 #define OPTION_UNLOCK_ALL 2
53
54 #define ICC_SSC_NONE 0
55 #define ICC_SSC_UP 1
56 #define ICC_SSC_CENTER 2
57 #define ICC_SSC_DOWN 4
58
59 #define ICC_BCLK_REAL_TIME 0
60 #define ICC_BCLK_PERM_NO_WR 1
61
62 #define ICC_SETUP_DATA_C_NAME L"IccAdvancedSetupDataVar"
63
64 //
65 // Ensure proper structure formats
66 //
67 #pragma pack(1)
68
69 typedef struct _ICC_SETUP_DATA {
70 UINT16 Frequency;
71 UINT8 Spread;
72 UINT8 ShowFrequency;
73 UINT8 ShowSpread;
74 UINT8 ShowProfile;
75 UINT8 Profile;
76 UINT8 AllowAdvancedOptions;
77 } ICC_SETUP_DATA;
78
79 #pragma pack()
80
81 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Madt.h Source File

  • Acpi
  • AcpiTables
  • Madt
Madt.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Multiple APIC Description
3 Table (MADT).
4 To make changes to the MADT, it is necessary to update the count for the
5 APIC structure being updated, and to modify table found in Madt.c.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 1999 - 2017 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37
38 #ifndef _MADT_H_
39 #define _MADT_H_
40
41 //
42 // Statements that include other files
43 //
44
45 #include <IndustryStandard/Acpi.h>
46
47 //
48 // MADT Definitions
49 //
50
51 #define EFI_ACPI_OEM_MADT_REVISION 0x00000001
52
53
54 //
55 // Multiple APIC Flags are defined in AcpiX.0.h
56 //
57 #define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)
58 #define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT)
59
60 //
61 // Define the number of each table type.
62 // This is where the table layout is modified.
63 //
64
65 #define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 16
66 #define EFI_ACPI_IO_APIC_COUNT 1
67 #define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2
68 #define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0
69 #define EFI_ACPI_LOCAL_APIC_NMI_COUNT 16
70 #define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0
71 #define EFI_ACPI_IO_SAPIC_COUNT 0
72 #define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0
73 #define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0
74
75 //
76 // MADT structure
77 //
78
79 //
80 // Ensure proper structure formats
81 //
82 #pragma pack (1)
83
84 //
85 // ACPI 1.0 Table structure
86 //
87 typedef struct {
88 EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
89
90 #if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
91 EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
92 #endif
93
94 #if EFI_ACPI_IO_APIC_COUNT > 0
95 EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
96 #endif
97
98 #if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
99 EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
100 #endif
101
102 #if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
103 EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
104 #endif
105
106 #if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
107 EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
108 #endif
109
110 #if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
111 EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
112 #endif
113
114 } EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
115
116 //
117 // ACPI 2.0 Table structure
118 //
119 typedef struct {
120 EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
121
122 #if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
123 EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
124 #endif
125
126 #if EFI_ACPI_IO_APIC_COUNT > 0
127 EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
128 #endif
129
130 #if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
131 EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
132 #endif
133
134 #if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
135 EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
136 #endif
137
138 #if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
139 EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
140 #endif
141
142 #if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
143 EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
144 #endif
145
146 #if EFI_ACPI_IO_SAPIC_COUNT > 0
147 EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
148 #endif
149
150 #if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0
151 EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
152 #endif
153
154 #if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0
155 EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
156 #endif
157
158 } EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
159
160 #pragma pack ()
161
162 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Mcfg.h Source File

  • Acpi
  • AcpiTables
  • Mcfg
Mcfg.h
Go to the documentation of this file.
1 /** @file
2 This file describes the contents of the ACPI Memory Mapped Configuration
3 Space Access Table (MCFG).
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2004 - 2017 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _MCFG_H_
37 #define _MCFG_H_
38
39 //
40 // Statements that include other files
41 //
42
43 #include <IndustryStandard/Acpi30.h>
44 #include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
45
46 //
47 // MCFG Definitions
48 //
49
50 #define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
51
52 //
53 // Define the number of allocation structures so that we can build the table structure.
54 //
55 #define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 2
56
57 //
58 // MCFG structure
59 //
60
61 //
62 // Ensure proper structure formats
63 //
64 #pragma pack (1)
65
66 //
67 // MCFG Table structure
68 //
69 typedef struct {
70 EFI_ACPI_DESCRIPTION_HEADER Header;
71 UINT64 Reserved;
72 #if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0
73 EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT];
74 #endif
75 } EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
76
77 #pragma pack ()
78
79 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: MePolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
MePolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel ME DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "MePolicyInitDxe.h"
35
36 /**
37 Initialize ME DXE Policy
38
39 @param[in] ImageHandle Image handle of this driver.
40
41 @retval EFI_SUCCESS Initialization complete.
42 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
43 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
44 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
45 **/
46 EFI_STATUS
47 EFIAPI
48 MePolicyInitDxe (
49 IN EFI_HANDLE ImageHandle
50 )
51 {
52 EFI_STATUS Status;
53 ME_POLICY_PROTOCOL *MePolicyProtocol;
54
55 DEBUG ((DEBUG_INFO, "MePolicyInitDxe\n"));
56 //
57 // Call MeCreatePolicyDefaults to initialize platform policy structure
58 // and get all default policy settings.
59 //
60 Status = MeCreatePolicyDefaults (&MePolicyProtocol);
61 ASSERT_EFI_ERROR (Status);
62 if (EFI_ERROR (Status)) {
63 return Status;
64 }
65
66 UpdateDxeMePolicyBoardConfig (MePolicyProtocol);
67
68 if (mFirmwareConfiguration != FwConfigDefault) {
69 UpdateDxeMePolicy (MePolicyProtocol);
70 }
71 //
72 // Install MeInstallPolicyProtocol.
73 // While installed, RC assumes the Policy is ready and finalized. So please
74 // update and override any setting before calling this function.
75 //
76 Status = MeInstallPolicyProtocol (ImageHandle, MePolicyProtocol);
77 ASSERT_EFI_ERROR (Status);
78
79 return Status;
80 }
81
UpdateDxeMePolicy
EFI_STATUS UpdateDxeMePolicy(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
Update the ME Policy Library.
UpdateDxeMePolicyBoardConfig
EFI_STATUS UpdateDxeMePolicyBoardConfig(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
This function performs DXE ME Policy update by board configuration.
MePolicyInitDxe
EFI_STATUS MePolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy.
Definition: MePolicyInitDxe.c:48
MePolicyInitDxe.h
Header file for the MePolicyInitDxe Driver.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: MePolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
MePolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the MePolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _ME_POLICY_INIT_DXE_H_
35 #define _ME_POLICY_INIT_DXE_H_
36
37 #include <Library/IoLib.h>
38 #include <Library/PcdLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42
43 #include <PchAccess.h>
44 #include <Protocol/MePolicy.h>
45 #include <Library/DxeMePolicyLib.h>
46 #include <Library/DxePolicyBoardConfigLib.h>
47 #include <Library/DxeMePolicyUpdateLib.h>
48
49 extern UINT8 mFirmwareConfiguration;
50
51 /**
52 Initialize ME DXE Policy
53
54 @param[in] ImageHandle Image handle of this driver.
55
56 @retval EFI_SUCCESS Initialization complete.
57 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
58 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
59 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
60 **/
61 EFI_STATUS
62 EFIAPI
63 MePolicyInitDxe (
64 IN EFI_HANDLE ImageHandle
65 )
66 ;
67
68 /**
69 Checkes the HECI protocol and send MEI message
70
71 @param[in] Event Event objext
72 @param[in] *Context VOID Pointer
73
74 **/
75 VOID
76 EFIAPI
77 HeciPlatformDebugCapabilityMsgCallback (
78 IN EFI_EVENT Event,
79 IN VOID *Context
80 )
81 ;
82 #endif
DxePolicyBoardConfigLib.h
Header file for the DxePolicyBoardConfig Library.
DxeMePolicyUpdateLib.h
MePolicyInitDxe
EFI_STATUS MePolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy.
Definition: MePolicyInitDxe.c:48
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
HeciPlatformDebugCapabilityMsgCallback
VOID HeciPlatformDebugCapabilityMsgCallback(IN EFI_EVENT Event, IN VOID *Context)
Checkes the HECI protocol and send MEI message.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Mmc.h Source File

  • IndustryStandard
Mmc.h
Go to the documentation of this file.
1 /** @file
2 Header file for Industry MMC 4.2 spec.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _MMC_H
35 #define _MMC_H
36
37 #pragma pack(1)
38
39 //
40 // Command definition
41 //
42 #define CMD0 0
43 #define CMD1 1
44 #define CMD2 2
45 #define CMD3 3
46 #define CMD4 4
47 #define CMD6 6
48 #define CMD7 7
49 #define CMD8 8
50 #define CMD9 9
51 #define CMD10 10
52 #define CMD11 11
53 #define CMD12 12
54 #define CMD13 13
55 #define CMD14 14
56 #define CMD15 15
57 #define CMD16 16
58 #define CMD17 17
59 #define CMD18 18
60 #define CMD19 19
61 #define CMD20 20
62 #define CMD21 21
63 #define CMD23 23
64 #define CMD24 24
65 #define CMD25 25
66 #define CMD26 26
67 #define CMD27 27
68 #define CMD28 28
69 #define CMD29 29
70 #define CMD30 30
71 #define CMD31 31
72 #define CMD35 35
73 #define CMD36 36
74 #define CMD38 38
75 #define CMD39 39
76 #define CMD40 40
77 #define CMD42 42
78 #define CMD55 55
79 #define CMD56 56
80
81 #define GO_IDLE_STATE CMD0
82 #define SEND_OP_COND CMD1
83 #define ALL_SEND_CID CMD2
84 #define SET_RELATIVE_ADDR CMD3
85 #define SET_DSR CMD4
86 #define SWITCH CMD6
87 #define SELECT_DESELECT_CARD CMD7
88 #define SEND_EXT_CSD CMD8
89 #define SEND_CSD CMD9
90 #define SEND_CID CMD10
91 #define READ_DAT_UNTIL_STOP CMD11
92 #define STOP_TRANSMISSION CMD12
93 #define SEND_STATUS CMD13
94 #define BUSTEST_R CMD14
95 #define GO_INACTIVE_STATE CMD15
96 #define SET_BLOCKLEN CMD16
97 #define READ_SINGLE_BLOCK CMD17
98 #define READ_MULTIPLE_BLOCK CMD18
99 #define BUSTEST_W CMD19
100 #define WRITE_DAT_UNTIL_STOP CMD20
101 #define SEND_TUNING_BLOCK CMD21
102 #define SET_BLOCK_COUNT CMD23
103 #define WRITE_BLOCK CMD24
104 #define WRITE_MULTIPLE_BLOCK CMD25
105 #define PROGRAM_CID CMD26
106 #define PROGRAM_CSD CMD27
107 #define SET_WRITE_PROT CMD28
108 #define CLR_WRITE_PROT CMD29
109 #define SEND_WRITE_PROT CMD30
110 #define SEND_WRITE_PROT_TYPE CMD31
111 #define ERASE_GROUP_START CMD35
112 #define ERASE_GROUP_END CMD36
113 #define ERASE CMD38
114 #define FAST_IO CMD39
115 #define GO_IRQ_STATE CMD40
116 #define LOCK_UNLOCK CMD42
117 #define APP_CMD CMD55
118 #define GEN_CMD CMD56
119
120 #define B_PERM_WP_DIS 0x10
121 #define B_PWR_WP_EN 0x01
122 #define US_PERM_WP_DIS 0x10
123 #define US_PWR_WP_EN 0x01
124
125 #define FREQUENCY_OD (400 * 1000)
126 #define FREQUENCY_MMC_DEFAULT (25 * 1000 * 1000)
127 #define FREQUENCY_MMC_PP (26 * 1000 * 1000)
128 #define FREQUENCY_MMC_PP_HIGH (52 * 1000 * 1000)
129 #define FREQUENCY_MMC_HS (200 * 1000 * 1000)
130
131 #define DEFAULT_DSR_VALUE 0x404
132
133 //
134 // Registers definition
135 //
136 typedef struct {
137 UINT32 Reserved0: 7; // 0
138 UINT32 V170_V195: 1; // 1.70V - 1.95V
139 UINT32 V200_V260: 7; // 2.00V - 2.60V
140 UINT32 V270_V360: 9; // 2.70V - 3.60V
141 UINT32 Reserved1: 5; // 0
142 UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
143 UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
144 } OCR;
145
146 typedef struct {
147 UINT8 NotUsed: 1; // 1
148 UINT8 CRC: 7; // CRC7 checksum
149 UINT8 MDT; // Manufacturing date
150 UINT32 PSN; // Product serial number
151 UINT8 PRV; // Product revision
152 UINT8 PNM[6]; // Product name
153 UINT16 OID; // OEM/Application ID
154 UINT8 MID; // Manufacturer ID
155 } CID;
156
157
158 typedef struct {
159 UINT8 NotUsed: 1; // 1 [0:0]
160 UINT8 CRC: 7; // CRC [7:1]
161 UINT8 ECC: 2; // ECC code [9:8]
162 UINT8 FILE_FORMAT: 2; // File format [11:10]
163 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
164 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
165 UINT8 COPY: 1; // Copy flag (OTP) [14:14]
166 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
167 UINT16 CONTENT_PROT_APP: 1; // Content protection application [16:16]
168 UINT16 Reserved0: 4; // 0 [20:17]
169 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
170 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
171 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
172 UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
173 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
174 UINT32 WP_GRP_SIZE: 5; // Write protect group size [36:32]
175 UINT32 ERASE_GRP_MULT: 5; // Erase group size multiplier [41:37]
176 UINT32 ERASE_GRP_SIZE: 5; // Erase group size [46:42]
177 UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
178 UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
179 UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
180 UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
181 UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
182 UINT32 C_SIZELow2: 2;// Device size [73:62]
183 UINT32 C_SIZEHigh10: 10;// Device size [73:62]
184 UINT32 Reserved1: 2; // 0 [75:74]
185 UINT32 DSR_IMP: 1; // DSR implemented [76:76]
186 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
187 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
188 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
189 UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
190 UINT32 CCC: 12;// Card command classes [95:84]
191 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
192 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
193 UINT8 TAAC ; // Data read access-time 1 [119:112]
194 UINT8 Reserved2: 2; // 0 [121:120]
195 UINT8 SPEC_VERS: 4; // System specification version [125:122]
196 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
197 } CSD;
198
199 typedef struct {
200 UINT8 Reserved133_0[134]; // [133:0] 0
201 UINT8 SEC_BAD_BLOCK_MGMNT; // [134] Bad Block Management mode
202 UINT8 Reserved135; // [135] 0
203 UINT8 ENH_START_ADDR[4]; // [139:136] Enhanced User Data Start Address
204 UINT8 ENH_SIZE_MULT[3]; // [142:140] Enhanced User Data Start Size
205 UINT8 GP_SIZE_MULT_1[3]; // [145:143] GPP1 Size
206 UINT8 GP_SIZE_MULT_2[3]; // [148:146] GPP2 Size
207 UINT8 GP_SIZE_MULT_3[3]; // [151:149] GPP3 Size
208 UINT8 GP_SIZE_MULT_4[3]; // [154:152] GPP4 Size
209 UINT8 PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting
210 UINT8 PARTITIONS_ATTRIBUTES; // [156] Partitions attributes
211 UINT8 MAX_ENH_SIZE_MULT[3]; // [159:157] GPP4 Start Size
212 UINT8 PARTITIONING_SUPPORT; // [160] Partitioning Support
213 UINT8 HPI_MGMT; // [161] HPI management
214 UINT8 RST_n_FUNCTION; // [162] H/W reset function
215 UINT8 BKOPS_EN; // [163] Enable background operations handshake
216 UINT8 BKOPS_START; // [164] Manually start background operations
217 UINT8 Reserved165; // [165] 0
218 UINT8 WR_REL_PARAM; // [166] Write reliability parameter register
219 UINT8 WR_REL_SET; // [167] Write reliability setting register
220 UINT8 RPMB_SIZE_MULT; // [168] RPMB Size
221 UINT8 FW_CONFIG; // [169] FW configuration
222 UINT8 Reserved170; // [170] 0
223 UINT8 USER_WP; // [171] User area write protection
224 UINT8 Reserved172; // [172] 0
225 UINT8 BOOT_WP; // [173] Boot area write protection
226 UINT8 Reserved174; // [174] 0
227 UINT8 ERASE_GROUP_DEF; // [175] High density erase group definition
228 UINT8 Reserved176; // [176] 0
229 UINT8 BOOT_BUS_WIDTH; // [177] Boot bus width
230 UINT8 BOOT_CONFIG_PROT; // [178] Boot config protection
231 UINT8 PARTITION_CONFIG; // [179] Partition config
232 UINT8 Reserved180; // [180] 0
233 UINT8 ERASED_MEM_CONT; // [181] Erased Memory Content
234 UINT8 Reserved182; // [182] 0
235 UINT8 BUS_WIDTH; // [183] Bus Width Mode
236 UINT8 Reserved184; // [184] 0
237 UINT8 HS_TIMING; // [185] High Speed Interface Timing
238 UINT8 Reserved186; // [186] 0
239 UINT8 POWER_CLASS; // [187] Power Class
240 UINT8 Reserved188; // [188] 0
241 UINT8 CMD_SET_REV; // [189] Command Set Revision
242 UINT8 Reserved190; // [190] 0
243 UINT8 CMD_SET; // [191] Command Set
244 UINT8 EXT_CSD_REV; // [192] Extended CSD Revision
245 UINT8 Reserved193; // [193] 0
246 UINT8 CSD_STRUCTURE; // [194] CSD Structure Version
247 UINT8 Reserved195; // [195] 0
248 UINT8 CARD_TYPE; // [196] Card Type
249 UINT8 DRIVER_STRENGTH; // [197] Driver Strength
250 UINT8 OUT_OF_INTERRUPT_TIME; // [198] Out-of-interrupt busy timing
251 UINT8 PARTITION_SWITCH_TIME; // [199] Partition switching timing
252 UINT8 PWR_CL_52_195; // [200] Power Class for 52MHz @ 1.95V
253 UINT8 PWR_CL_26_195; // [201] Power Class for 26MHz @ 1.95V
254 UINT8 PWR_CL_52_360; // [202] Power Class for 52MHz @ 3.6V
255 UINT8 PWR_CL_26_360; // [203] Power Class for 26MHz @ 3.6V
256 UINT8 Reserved204; // [204] 0
257 UINT8 MIN_PERF_R_4_26; // [205] Minimum Read Performance for 4bit @26MHz
258 UINT8 MIN_PERF_W_4_26; // [206] Minimum Write Performance for 4bit @26MHz
259 UINT8 MIN_PERF_R_8_26_4_52; // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz
260 UINT8 MIN_PERF_W_8_26_4_52; // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz
261 UINT8 MIN_PERF_R_8_52; // [209] Minimum Read Performance for 8bit @52MHz
262 UINT8 MIN_PERF_W_8_52; // [210] Minimum Write Performance for 8bit @52MHz
263 UINT8 Reserved211; // [211] 0
264 UINT8 SEC_COUNT[4]; // [215:212] Sector Count
265 UINT8 Reserved216; // [216] 0
266 UINT8 S_A_TIMEOUT; // [217] Sleep/awake timeout
267 UINT8 Reserved218; // [218] 0
268 UINT8 S_C_VCCQ; // [219] Sleep current (VCCQ)
269 UINT8 S_C_VCC; // [220] Sleep current (VCC)
270 UINT8 HC_WP_GRP_SIZE; // [221] High-capacity write protect group size
271 UINT8 REL_WR_SEC_C; // [222] Reliable write sector count
272 UINT8 ERASE_TIMEOUT_MULT; // [223] High-capacity erase timeout
273 UINT8 HC_ERASE_GRP_SIZE; // [224] High-capacity erase unit size
274 UINT8 ACC_SIZE; // [225] Access size
275 UINT8 BOOT_SIZE_MULTI; // [226] Boot partition size
276 UINT8 Reserved227; // [227] 0
277 UINT8 BOOT_INFO; // [228] Boot information
278 UINT8 SEC_TRIM_MULT; // [229] Secure TRIM Multiplier
279 UINT8 SEC_ERASE_MULT; // [230] Secure Erase Multiplier
280 UINT8 SEC_FEATURE_SUPPORT; // [231] Secure Feature support
281 UINT8 TRIM_MULT; // [232] TRIM Multiplier
282 UINT8 Reserved233; // [233] 0
283 UINT8 MIN_PERF_DDR_R_8_52; // [234] Min Read Performance for 8-bit @ 52MHz
284 UINT8 MIN_PERF_DDR_W_8_52; // [235] Min Write Performance for 8-bit @ 52MHz
285 UINT8 Reserved237_236[2]; // [237:236] 0
286 UINT8 PWR_CL_DDR_52_195; // [238] Power class for 52MHz, DDR at 1.95V
287 UINT8 PWR_CL_DDR_52_360; // [239] Power class for 52MHz, DDR at 3.6V
288 UINT8 Reserved240; // [240] 0
289 UINT8 INI_TIMEOUT_AP; // [241] 1st initialization time after partitioning
290 UINT8 CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors
291 UINT8 BKOPS_STATUS; // [246] Background operations status
292 UINT8 Reserved501_247[255]; // [501:247] 0
293 UINT8 BKOPS_SUPPORT; // [502] Background operations support
294 UINT8 HPI_FEATURES; // [503] HPI features
295 UINT8 S_CMD_SET; // [504] Sector Count
296 UINT8 Reserved511_505[7]; // [511:505] Sector Count
297 } EXT_CSD;
298
299
300 //
301 //Card Status definition
302 //
303 typedef struct {
304 UINT32 Reserved0: 2; //Reserved for Manufacturer Test Mode
305 UINT32 Reserved1: 2; //Reserved for Application Specific commands
306 UINT32 Reserved2: 1; //
307 UINT32 SAPP_CMD: 1; //
308 UINT32 Reserved3: 1; //Reserved
309 UINT32 SWITCH_ERROR: 1; //
310 UINT32 READY_FOR_DATA: 1; //
311 UINT32 CURRENT_STATE: 4; //
312 UINT32 ERASE_RESET: 1; //
313 UINT32 Reserved4: 1; //Reserved
314 UINT32 WP_ERASE_SKIP: 1; //
315 UINT32 CID_CSD_OVERWRITE: 1; //
316 UINT32 OVERRUN: 1; //
317 UINT32 UNDERRUN: 1; //
318 UINT32 ERROR: 1; //
319 UINT32 CC_ERROR: 1; //
320 UINT32 CARD_ECC_FAILED: 1; //
321 UINT32 ILLEGAL_COMMAND: 1; //
322 UINT32 COM_CRC_ERROR: 1; //
323 UINT32 LOCK_UNLOCK_FAILED: 1; //
324 UINT32 CARD_IS_LOCKED: 1; //
325 UINT32 WP_VIOLATION: 1; //
326 UINT32 ERASE_PARAM: 1; //
327 UINT32 ERASE_SEQ_ERROR: 1; //
328 UINT32 BLOCK_LEN_ERROR: 1; //
329 UINT32 ADDRESS_MISALIGN: 1; //
330 UINT32 ADDRESS_OUT_OF_RANGE:1; //
331 } CARD_STATUS;
332
333 typedef struct {
334 UINT32 CmdSet: 3;
335 UINT32 Reserved0: 5;
336 UINT32 Value: 8;
337 UINT32 Index: 8;
338 UINT32 Access: 2;
339 UINT32 Reserved1: 6;
340 } SWITCH_ARGUMENT;
341
342 #define CommandSet_Mode 0
343 #define SetBits_Mode 1
344 #define ClearBits_Mode 2
345 #define WriteByte_Mode 3
346
347 #define Idle_STATE 0
348 #define Ready_STATE 1
349 #define Ident_STATE 2
350 #define Stby_STATE 3
351 #define Tran_STATE 4
352 #define Data_STATE 5
353 #define Rcv_STATE 6
354 #define Prg_STATE 7
355 #define Dis_STATE 8
356 #define Btst_STATE 9
357
358 #pragma pack()
359 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: MultiPlatSupport.h Source File

MultiPlatSupport.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2013 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __MULTI_PLATFORM_SUPPORT_H__
35 #define __MULTI_PLATFORM_SUPPORT_H__
36
37 ///
38 /// Alignment of variable name and data, according to the architecture:
39 /// * For IA-32 and Intel(R) 64 architectures: 1.
40 /// * For IA-64 architecture: 8.
41 ///
42 #if defined (MDE_CPU_IPF)
43 #define ALIGNMENT 8
44 #else
45 #define ALIGNMENT 1
46 #endif
47
48 //
49 // GET_PAD_SIZE calculates the miminal pad bytes needed to make the current pad size satisfy the alignment requirement.
50 //
51 #if (ALIGNMENT == 1)
52 #define GET_PAD_SIZE(a) (0)
53 #else
54 #define GET_PAD_SIZE(a) (((~a) + 1) & (ALIGNMENT - 1))
55 #endif
56
57 ///
58 /// Alignment of Variable Data Header in Variable Store region.
59 ///
60 #define HEADER_ALIGNMENT 4
61 #define HEADER_ALIGN(Header) (((UINTN) (Header) + HEADER_ALIGNMENT - 1) & (~(HEADER_ALIGNMENT - 1)))
62
63 ///
64 /// Status of Variable Store Region.
65 ///
66 typedef enum {
67 EfiRaw,
68 EfiValid,
69 EfiInvalid,
70 EfiUnknown
71 } VARIABLE_STORE_STATUS;
72
73 #pragma pack(1)
74
75 ///
76 /// Variable Store Header Format and State.
77 ///
78 #define VARIABLE_STORE_FORMATTED 0x5a
79 #define VARIABLE_STORE_HEALTHY 0xfe
80
81 ///
82 /// Variable Store region header.
83 ///
84 typedef struct {
85 ///
86 /// Variable store region signature.
87 ///
88 EFI_GUID Signature;
89 ///
90 /// Size of entire variable store,
91 /// including size of variable store header but not including the size of FvHeader.
92 ///
93 UINT32 Size;
94 ///
95 /// Variable region format state.
96 ///
97 UINT8 Format;
98 ///
99 /// Variable region healthy state.
100 ///
101 UINT8 State;
102 UINT16 Reserved;
103 UINT32 Reserved1;
104 } VARIABLE_STORE_HEADER;
105
106 ///
107 /// Variable data start flag.
108 ///
109 #define VARIABLE_DATA 0x55AA
110
111 ///
112 /// Variable State flags.
113 ///
114 #define VAR_IN_DELETED_TRANSITION 0xfe ///< Variable is in obsolete transition.
115 #define VAR_DELETED 0xfd ///< Variable is obsolete.
116 #define VAR_HEADER_VALID_ONLY 0x7f ///< Variable header has been valid.
117 #define VAR_ADDED 0x3f ///< Variable has been completely added.
118
119 ///
120 /// Single Variable Data Header Structure.
121 ///
122 typedef struct {
123 ///
124 /// Variable Data Start Flag.
125 ///
126 UINT16 StartId;
127 ///
128 /// Variable State defined above.
129 ///
130 UINT8 State;
131 UINT8 Reserved;
132 ///
133 /// Attributes of variable defined in UEFI specification.
134 ///
135 UINT32 Attributes;
136 ///
137 /// Size of variable null-terminated Unicode string name.
138 ///
139 UINT32 NameSize;
140 ///
141 /// Size of the variable data without this header.
142 ///
143 UINT32 DataSize;
144 ///
145 /// A unique identifier for the vendor that produces and consumes this varaible.
146 ///
147 EFI_GUID VendorGuid;
148 } VARIABLE_HEADER;
149
150 ///
151 /// Single Variable Data Header Structure for Auth variable.
152 ///
153 typedef struct {
154 ///
155 /// Variable Data Start Flag.
156 ///
157 UINT16 StartId;
158 ///
159 /// Variable State defined above.
160 ///
161 UINT8 State;
162 UINT8 Reserved;
163 ///
164 /// Attributes of variable defined in UEFI specification.
165 ///
166 UINT32 Attributes;
167 ///
168 /// Associated monotonic count value against replay attack.
169 ///
170 UINT64 MonotonicCount;
171 ///
172 /// Associated TimeStamp value against replay attack.
173 ///
174 EFI_TIME TimeStamp;
175 ///
176 /// Index of associated public key in database.
177 ///
178 UINT32 PubKeyIndex;
179 ///
180 /// Size of variable null-terminated Unicode string name.
181 ///
182 UINT32 NameSize;
183 ///
184 /// Size of the variable data without this header.
185 ///
186 UINT32 DataSize;
187 ///
188 /// A unique identifier for the vendor that produces and consumes this varaible.
189 ///
190 EFI_GUID VendorGuid;
191 } AUTHENTICATED_VARIABLE_HEADER;
192
193 typedef struct {
194 UINT16 DefaultId;
195 UINT16 BoardId;
196 } DEFAULT_INFO;
197
198 typedef struct {
199 UINT16 Offset;
200 UINT8 Value;
201 } DATA_DELTA;
202
203 typedef struct {
204 //
205 // HeaderSize includes HeaderSize fields and DefaultInfo arrays
206 //
207 UINT16 HeaderSize;
208 //
209 // DefaultInfo arrays those have the same default setting.
210 //
211 DEFAULT_INFO DefaultInfo[1];
212 //
213 // Default data is stored as variable storage or the array of DATA_DELTA.
214 //
215 } DEFAULT_DATA;
216
217 #pragma pack()
218
219 #endif
VARIABLE_STORE_STATUS
VARIABLE_STORE_STATUS
Status of Variable Store Region.
Definition: MultiPlatSupport.h:66
VARIABLE_HEADER::Attributes
UINT32 Attributes
Attributes of variable defined in UEFI specification.
Definition: MultiPlatSupport.h:135
VARIABLE_STORE_HEADER::Format
UINT8 Format
Variable region format state.
Definition: MultiPlatSupport.h:97
VARIABLE_HEADER::DataSize
UINT32 DataSize
Size of the variable data without this header.
Definition: MultiPlatSupport.h:143
AUTHENTICATED_VARIABLE_HEADER::PubKeyIndex
UINT32 PubKeyIndex
Index of associated public key in database.
Definition: MultiPlatSupport.h:178
VARIABLE_HEADER
Single Variable Data Header Structure.
Definition: MultiPlatSupport.h:122
AUTHENTICATED_VARIABLE_HEADER::NameSize
UINT32 NameSize
Size of variable null-terminated Unicode string name.
Definition: MultiPlatSupport.h:182
AUTHENTICATED_VARIABLE_HEADER::DataSize
UINT32 DataSize
Size of the variable data without this header.
Definition: MultiPlatSupport.h:186
AUTHENTICATED_VARIABLE_HEADER::MonotonicCount
UINT64 MonotonicCount
Associated monotonic count value against replay attack.
Definition: MultiPlatSupport.h:170
VARIABLE_HEADER::NameSize
UINT32 NameSize
Size of variable null-terminated Unicode string name.
Definition: MultiPlatSupport.h:139
AUTHENTICATED_VARIABLE_HEADER::State
UINT8 State
Variable State defined above.
Definition: MultiPlatSupport.h:161
AUTHENTICATED_VARIABLE_HEADER::TimeStamp
EFI_TIME TimeStamp
Associated TimeStamp value against replay attack.
Definition: MultiPlatSupport.h:174
VARIABLE_HEADER::VendorGuid
EFI_GUID VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.
Definition: MultiPlatSupport.h:147
AUTHENTICATED_VARIABLE_HEADER::StartId
UINT16 StartId
Variable Data Start Flag.
Definition: MultiPlatSupport.h:157
VARIABLE_STORE_HEADER::Size
UINT32 Size
Size of entire variable store, including size of variable store header but not including the size of ...
Definition: MultiPlatSupport.h:93
VARIABLE_STORE_HEADER::State
UINT8 State
Variable region healthy state.
Definition: MultiPlatSupport.h:101
AUTHENTICATED_VARIABLE_HEADER::Attributes
UINT32 Attributes
Attributes of variable defined in UEFI specification.
Definition: MultiPlatSupport.h:166
VARIABLE_HEADER::StartId
UINT16 StartId
Variable Data Start Flag.
Definition: MultiPlatSupport.h:126
VARIABLE_STORE_HEADER::Signature
EFI_GUID Signature
Variable store region signature.
Definition: MultiPlatSupport.h:88
VARIABLE_STORE_HEADER
Variable Store region header.
Definition: MultiPlatSupport.h:84
AUTHENTICATED_VARIABLE_HEADER::VendorGuid
EFI_GUID VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.
Definition: MultiPlatSupport.h:190
AUTHENTICATED_VARIABLE_HEADER
Single Variable Data Header Structure for Auth variable.
Definition: MultiPlatSupport.h:153
VARIABLE_HEADER::State
UINT8 State
Variable State defined above.
Definition: MultiPlatSupport.h:130
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: MultiPlatSupportLib.h Source File

  • Library
MultiPlatSupportLib.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2012 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _MULTI_PLATFORM_SUPPORT_LIB_H_
35 #define _MULTI_PLATFORM_SUPPORT_LIB_H_
36
37 /**
38 Get variable from default variable HOB.
39
40 @param[in] VariableName A Null-terminated string that is the name of the vendor's
41 variable.
42 @param[in] VendorGuid A unique identifier for the vendor.
43 @param[out] Attributes If not NULL, a pointer to the memory location to return the
44 attributes bitmask for the variable.
45 @param[in, out] DataSize On input, the size in bytes of the return Data buffer.
46 On output the size of data returned in Data.
47 @param[out] Data The buffer to return the contents of the variable.
48
49 @retval EFI_SUCCESS The function completed successfully.
50 @retval EFI_NOT_FOUND The variable was not found.
51 @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result.
52 @retval EFI_INVALID_PARAMETER VariableName is NULL.
53 @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
54 @retval EFI_INVALID_PARAMETER DataSize is NULL.
55 @retval EFI_INVALID_PARAMETER The DataSize is not too small and Data is NULL.
56
57 **/
58 EFI_STATUS
59 EFIAPI
60 GetVariableFromHob (
61 IN CHAR16 *VariableName,
62 IN EFI_GUID *VendorGuid,
63 OUT UINT32 *Attributes, OPTIONAL
64 IN OUT UINTN *DataSize,
65 OUT VOID *Data
66 );
67
68 /**
69 Set variable to default variable HOB.
70
71 @param[in] VariableName A Null-terminated string that is the name of the vendor's
72 variable.
73 @param[in] VendorGuid A unique identifier for the vendor.
74 @param[in] Attributes If not NULL, a pointer to the memory location to set the
75 attributes bitmask for the variable.
76 @param[in] DataSize On input, the size in bytes of the return Data buffer.
77 On output the size of data returned in Data.
78 @param[in] Data The buffer to return the contents of the variable.
79
80 @retval EFI_SUCCESS The function completed successfully.
81 @retval EFI_NOT_FOUND The variable was not found.
82 @retval EFI_INVALID_PARAMETER VariableName is NULL.
83 @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
84 @retval EFI_INVALID_PARAMETER Attributes is not NULL, but attributes value is 0.
85 @retval EFI_INVALID_PARAMETER DataSize is not equal to the variable data size.
86 @retval EFI_INVALID_PARAMETER The DataSize is equal to the variable data size, but Data is NULL.
87
88 **/
89 EFI_STATUS
90 EFIAPI
91 SetVariableToHob (
92 IN CHAR16 *VariableName,
93 IN EFI_GUID *VendorGuid,
94 IN UINT32 *Attributes, OPTIONAL
95 IN UINTN DataSize,
96 IN VOID *Data
97 );
98
99 /**
100 This function finds the matched default data and create GUID hob for it.
101
102 @param[in] DefaultId - Specifies the type of defaults to retrieve.
103
104 @return EFI_SUCCESS - The matched default data is found.
105 @return EFI_NOT_FOUND - The matched default data is not found.
106 @return EFI_OUT_OF_RESOURCES - No enough resource to create HOB.
107
108 **/
109 EFI_STATUS
110 EFIAPI
111 CreateDefaultVariableHob (
112 IN UINT16 DefaultId
113 );
114
115 #endif
SetVariableToHob
EFI_STATUS SetVariableToHob(IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, IN UINT32 *Attributes, OPTIONAL IN UINTN DataSize, IN VOID *Data)
Set variable to default variable HOB.
CreateDefaultVariableHob
EFI_STATUS CreateDefaultVariableHob(IN UINT16 DefaultId)
This function finds the matched default data and create GUID hob for it.
GetVariableFromHob
EFI_STATUS GetVariableFromHob(IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, OUT UINT32 *Attributes, OPTIONAL IN OUT UINTN *DataSize, OUT VOID *Data)
Get variable from default variable HOB.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: OcSetupVariable.h Source File

OcSetupVariable.h
Go to the documentation of this file.
1 /** @file
2 Variable definition for overclocking support
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _OC_SETUP_VARIABLE_H_
35 #define _OC_SETUP_VARIABLE_H_
36
37 #pragma pack(1)
38 typedef struct{
39 UINT8 OcInterfaceRtUpdated; // New added, used to indicate OC variable has been updated during RT.
40 //
41 // Sa setup
42 //
43 UINT8 tCL;
44 UINT8 tRCDtRP;
45 UINT16 tRAS;
46 UINT8 tWR;
47 UINT16 tRFC;
48 UINT8 tRRD;
49 UINT8 tWTR;
50 UINT8 tRTP;
51 UINT16 tFAW;
52 UINT8 tWRDefault;
53 UINT8 NModeSupport;
54 UINT8 DdrRatioDefault;
55 UINT8 DdrRatio;
56 UINT16 MemoryVoltage;
57 UINT8 BclkOverride;
58 UINT32 BclkFrequency;
59 UINT8 GtMaxOcRatio;
60 UINT8 SpdProfileSelected;
61 UINT8 DdrRefClk;
62 UINT8 GtVoltageMode;
63 UINT16 GtVoltageOffset;
64 UINT8 GtVoltageOffsetPrefix;
65 UINT16 GtVoltageOverride;
66 UINT16 GtExtraTurboVoltage;
67 UINT16 UncoreVoltageOffset;
68 UINT8 UncoreVoltageOffsetPrefix;
69
70 //
71 // CPU Setup
72 //
73 UINT8 OverclockingSupport;
74 UINT8 EnableGv;
75 UINT8 CpuRatio;
76 UINT8 CpuRatioOverride;
77 UINT8 CoreMaxOcRatio;
78 UINT8 CoreVoltageMode;
79 UINT16 CoreVoltageOverride;
80 UINT16 CoreExtraTurboVoltage;
81 UINT16 CoreVoltageOffset;
82 UINT8 CoreVoltageOffsetPrefix;
83 UINT8 RingMaxOcRatio;
84 UINT8 RingVoltageMode;
85 UINT16 RingVoltageOverride;
86 UINT16 RingExtraTurboVoltage;
87 UINT16 RingVoltageOffset;
88 UINT8 RingVoltageOffsetPrefix;
89 UINT8 PowerLimit1Time;
90 UINT8 TurboMode;
91 UINT8 RatioLimit1;
92 UINT8 RatioLimit2;
93 UINT8 RatioLimit3;
94 UINT8 RatioLimit4;
95 UINT8 RatioLimit5;
96 UINT8 RatioLimit6;
97 UINT8 RatioLimit7;
98 UINT8 RatioLimit8;
99 UINT8 TurboPowerLimitLock;
100 UINT32 PowerLimit1;
101 UINT32 PowerLimit1Default;
102 UINT8 PowerLimit2;
103 UINT32 PowerLimit2Power;
104 UINT32 PowerLimit2Default;
105 UINT8 OverclockingLock;
106 UINT8 LongDurationPwrLimitOverride;
107 UINT8 WDTSupportforNextOSBoot;
108 UINT16 TimeforNextOSBoot;
109
110 //
111 // Setup
112 //
113 UINT8 PlatformUnstable;
114
115 //
116 // IccMax and AVX Retio Control
117 //
118 UINT16 IccMax[5];
119 UINT8 Avx2RatioOffset;
120 UINT8 Avx3RatioOffset;
121
122 //
123 // GT Unsliced
124 //
125 UINT8 GtusMaxOcRatio;
126 UINT8 GtusVoltageMode;
127 UINT16 GtusVoltageOffset;
128 UINT8 GtusVoltageOffsetPrefix;
129 UINT16 GtusVoltageOverride;
130 UINT16 GtusExtraTurboVoltage;
131 } OC_SETUP_DATA;
132
133 #pragma pack()
134 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: OemSetup.h Source File

OemSetup.h
Go to the documentation of this file.
1 /** @file
2 OEM Specific Setup Variables and Structures
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _OEMSETUP_H_
36 #define _OEMSETUP_H_
37
38 #include <PchLimits.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 // OS profile
45 #define OS_PROFILE_GUID \
46 { 0xE59376D7, 0x2DD9, 0x42A3, 0x9E, 0xC8, 0x1D, 0x71, 0xD5, 0xE3, 0xC1, 0xEC }
47
48 // Currently enumerated OSes
49 #define OsNone 0x00
50 #define OsAndroid 0x01
51 #define OsWinCs 0x02
52 #define OsWinNonCs 0x03
53 #define OsMax 0x04
54
55 //
56 // From PchInfoLib.h
57 //
58 #define SKL_PCH 1
59 #define KBL_PCH 2
60 #define CNL_PCH 3
61 #ifdef PCH_ICL
62 #define ICL_PCH 4
63 #endif
64 #define PCH_UNKNOWN_GENERATION 0xFF
65
66 #define PCH_MOBILE_SKU 0
67 #define PCH_DESKTOP_SKU 1
68 #define PCH_SERVER_SKU 2
69
70 #define PCH_RP_AVAILABLE 0
71 #define PCH_RP_FUSED_OFF 1
72 #define PCH_RP_MERGED 2
73 #define PCH_RP_DIFFERENT_BUS 3
74 #define PCH_RP_ETHERNET 4
75 #define PCH_RP_NOT_IMPLEMENTED 5
76
77 #pragma pack(1)
78
79 typedef struct _SETUP_VOLATILE_DATA
80 {
81 UINT8 FabId;
82 UINT8 BoardBomId;
83 UINT16 PlatId;
84 UINT8 PlatformFlavor;
85 UINT8 PlatformType;
86 UINT8 BoardType;
87 UINT8 VTdAvailable;
88 UINT8 PchGeneration;
89 UINT8 GbeSupportByPch; // Gbe is supported on current PCH
90 UINT8 GbeAvailable; // Gbe is configured and usable
91 UINT8 DimmPresent[4];
92 UINT8 PciePortCfg[PCH_MAX_PCIE_ROOT_PORTS];
93 UINT8 EnableDebugSerialIoUartNumber;
94 UINT8 EmmcSupported;
95 UINT8 SdCardSupported;
96 UINT8 UfsSupported;
97 UINT32 AcpiDebugAddress;
98 UINT8 PegPresent[4];
99 UINT8 RstAvailable;
100 UINT8 RsteAvailable;
101 UINT8 SataMpsPresent[8];
102 UINT8 DockAttached;
103 UINT8 PcieStorageMap[PCH_MAX_PCIE_ROOT_PORTS];
104 UINT8 PcieStorageProgrammingInterface[PCH_MAX_PCIE_ROOT_PORTS];
105 UINT8 CycleRouterMap[PCH_MAX_PCIE_ROOT_PORTS];
106 UINT8 AudioLinkSupported[13];
107 UINT8 PchCridSupport;
108 } SETUP_VOLATILE_DATA;
109
110 //This structure is used for setup.
111 typedef struct {
112 UINT8 XDBitAvailable;
113 UINT8 TurboModeAvailable;
114 UINT8 XETdcTdpLimitAvailable;
115 UINT8 CoreRatioLimitAvailable;
116 UINT8 HTAvailable;
117 UINT8 MultiCoreAvailable;
118 UINT8 VTAvailable;
119 UINT8 AESAvailable;
120 UINT8 TXTAvailable;
121 UINT8 CxAvailable;
122 UINT8 C1Available;
123 UINT8 C1EAvailable;
124 UINT8 C3Available;
125 UINT8 C6Available;
126 UINT8 C7Available;
127 UINT8 C8Available;
128 UINT8 C9Available;
129 UINT8 C10Available;
130 UINT8 EISTAvailable;
131 UINT8 HwpAvailable;
132 UINT8 ItbmAvailable;
133 UINT8 NumCores;
134 UINT8 MultiSocketAvailable;
135 UINT8 MultiSocketPopulated;
136 UINT8 LocalX2ApicAvailable;
137 UINT8 EnergyEfficientTurboAvailable;
138 UINT8 SgxSupported;
139 UINT8 C6DramSupported;
140 UINT8 ApicIdFlag;
141 UINT8 ConfigTdpAvailable;
142 UINT8 LpmAvailable;
143 UINT8 TimedMwaitSupported;
144 UINT8 DebugInterfaceSupported;
145 UINT8 ProcTraceSupported;
146 UINT8 SmmEnhancementSupported;
147 UINT8 SmmTargetedSmiAvailable;
148 UINT8 SmmCpuSvrstrAvailable;
149 UINT8 SmmCodeAccessAvailable;
150 UINT8 SmmLongFlowAvailable;
151 UINT8 HdcSupported;
152 UINT8 HwpInterruptSupported;
153 UINT8 CtdpDownSupported;
154 UINT8 CtdpUpSupported;
155 UINT8 FivrSupported;
156 UINT8 McivrSupported;
157 UINT8 FclkSupported;
158 } SETUP_CPU_FEATURES;
159
160 typedef struct {
161 UINT8 OsProfile;
162 UINT8 PrevOs;
163 } OS_PROFILE;
164
165 #pragma pack()
166
167 /****** DO NOT WRITE BELOW THIS LINE *******/
168 #ifdef __cplusplus
169 }
170 #endif
171 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: OverClockPpi.h Source File

  • Ppi
OverClockPpi.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2010 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _PEI_OVERCLOCKING_PPI_H
35 #define _PEI_OVERCLOCKING_PPI_H
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #ifdef __cplusplus
41 }
42 #endif
43 #endif
44
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PcdInitDxe.c Source File

  • PlatformInit
  • PcdInitDxe
PcdInitDxe.c
Go to the documentation of this file.
1 /** @file
2 Driver for initializing platform dynamic PCDs.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #include <Uefi.h>
37 #include <Library/BaseLib.h>
38 #include <Library/BaseMemoryLib.h>
39 #include <Library/PcdLib.h>
40 #include <Library/DebugLib.h>
41 #include <Library/UefiRuntimeServicesTableLib.h>
42 #include <Library/UefiBootServicesTableLib.h>
43 #include <Library/PchInfoLib.h>
44 #include <Library/SataLib.h>
45 #include <SetupVariable.h>
46 #include <BootTime.h>
47
48
49 EFI_STATUS
50 EFIAPI
51 PlatformPcdInitEntryPoint (
52 IN EFI_HANDLE ImageHandle,
53 IN EFI_SYSTEM_TABLE *SystemTable
54 )
55 {
56 UINTN VarSize;
57 EFI_STATUS Status;
58 CPU_SETUP CpuSetup;
59 SETUP_DATA SetupData;
60 BOOTTIME_SETUP BootTimeSetup;
61
62 VarSize = sizeof (SETUP_DATA);
63 Status = gRT->GetVariable (
64 L"Setup",
65 &gSetupVariableGuid,
66 NULL,
67 &VarSize,
68 &SetupData
69 );
70 if (EFI_ERROR (Status)) {
71 DEBUG((DEBUG_ERROR, "Failed to get setup variable\n"));
72 return Status;
73 }
74
75 VarSize = sizeof (CPU_SETUP);
76 Status = gRT->GetVariable (
77 L"CpuSetup",
78 &gCpuSetupVariableGuid,
79 NULL,
80 &VarSize,
81 &CpuSetup
82 );
83 if (EFI_ERROR (Status)) {
84 DEBUG((DEBUG_ERROR, "Failed to get CPU Setup variable\n"));
85 return Status;
86 }
87
88 if (SetupData.FastBoot) {
89 //
90 // Disable MdeModulePkg core PcdAtaSmartEnable to skip HDD SMART enabling
91 //
92 PcdSetBoolS (PcdAtaSmartEnable, FALSE);
93 //
94 // Enable gEfiMdeModulePkgTokenSpaceGuid PcdFastPS2Detection to enable quick PS2 device detection
95 //
96 PcdSetBoolS (PcdFastPS2Detection, TRUE);
97 }
98
99 //
100 // Change PcdAcpiDebugEnable PCD to TRUE if ACPI DEBUG is enabled in Setup menu
101 //
102 if (SetupData.AcpiDebug) {
103 PcdSetBoolS (PcdAcpiDebugEnable, TRUE);
104 } else {
105 PcdSetBoolS (PcdAcpiDebugEnable, FALSE);
106 }
107
108 //
109 // Change PcdOverclockEnable PCD to TRUE if Over-clocking Support is enabled in Setup menu
110 //
111 if (CpuSetup.OverclockingSupport) {
112 PcdSetBoolS (PcdOverclockEnable, TRUE);
113 } else {
114 PcdSetBoolS (PcdOverclockEnable, FALSE);
115 }
116
117 //
118 // Update AHCI max ports
119 //
120 PcdSet8S (PcdAhciMaxPorts, GetPchMaxSataPortNum (0));
121
122 //
123 // Change PcdBootTime PCD to TRUE if BootTimeLog is enabled in Setup menu
124 //
125 VarSize = sizeof (BOOTTIME_SETUP);
126 Status = gRT->GetVariable (
127 L"BootTime",
128 &gSetupVariableGuid,
129 NULL,
130 &VarSize,
131 &BootTimeSetup
132 );
133
134 if (!EFI_ERROR (Status)) {
135 (BootTimeSetup.BootTime == 1) ? PcdSetBoolS(PcdBootTime, TRUE) : PcdSetBoolS(PcdBootTime, FALSE);
136 }
137
138 return EFI_SUCCESS;
139 }
SetupVariable.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PchPolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
PchPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for PCH DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "PchPolicyInitDxe.h"
35
36 //
37 // Function implementations
38 //
39
40 /**
41 Initialize PCH DXE Policy
42
43 @param[in] ImageHandle Image handle of this driver.
44
45 @retval EFI_SUCCESS Initialization complete.
46 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
47 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
48 **/
49 EFI_STATUS
50 EFIAPI
51 PchPolicyInitDxe (
52 IN EFI_HANDLE ImageHandle
53 )
54 {
55 EFI_STATUS Status;
56 PCH_POLICY_PROTOCOL *PchPolicy;
57
58 //
59 // Call CreatePchDxeConfigBlocks to create & initialize platform policy structure
60 // and get all Intel default policy settings.
61 //
62 Status = CreatePchDxeConfigBlocks (&PchPolicy);
63 DEBUG((DEBUG_INFO, "PchPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", PchPolicy->TableHeader.NumberOfBlocks));
64 ASSERT_EFI_ERROR (Status);
65
66 if (mFirmwareConfiguration != FwConfigDefault) {
67 UpdateDxePchPolicy (PchPolicy);
68 }
69
70 //
71 // Install PchInstallPolicyProtocol.
72 // While installed, RC assumes the Policy is ready and finalized. So please
73 // update and override any setting before calling this function.
74 //
75 Status = PchInstallPolicyProtocol (ImageHandle, PchPolicy);
76 ASSERT_EFI_ERROR (Status);
77
78 return Status;
79 }
UpdateDxePchPolicy
EFI_STATUS UpdateDxePchPolicy(IN OUT PCH_POLICY_PROTOCOL *PchPolicy)
Get data for platform policy from setup options.
PchPolicyInitDxe.h
Header file for the PchPolicyInitDxe Driver.
PchPolicyInitDxe
EFI_STATUS PchPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize PCH DXE Policy.
Definition: PchPolicyInitDxe.c:51
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PchPolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
PchPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PchPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PCH_POLICY_INIT_DXE_H_
35 #define _PCH_POLICY_INIT_DXE_H_
36
37 #include <Library/BaseMemoryLib.h>
38 #include <Library/MemoryAllocationLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42 #include <Protocol/PchPolicy.h>
43 #include <Library/DxePchPolicyLib.h>
44 #include <Library/DxePchPolicyUpdateLib.h>
45
46 extern UINT8 mFirmwareConfiguration;
47
48 /**
49 <b>PCH DXE Policy Driver Entry Point</b> \n
50 - <b>Introduction</b> \n
51 Pch DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
52 Platform policy Protocol is initialized with default settings in this funciton.
53 This policy Protocol has to be initialized prior to PCH initialization DXE drivers execution.
54
55 - @pre
56 - Runtime variable service should be ready if policy initialization required.
57
58 - @result
59 PCH_POLICY_PROTOCOL will be installed successfully and ready for Pch reference code use.
60
61 - <b>Porting Recommendations</b> \n
62 Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
63
64 @param[in] ImageHandle - Image handle of this driver.
65
66 @retval EFI_SUCCESS Initialization complete.
67 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
68 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
69 **/
70 EFI_STATUS
71 EFIAPI
72 PchPolicyInitDxe (
73 IN EFI_HANDLE ImageHandle
74 );
75
76 #endif
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
DxePchPolicyUpdateLib.h
PchPolicyInitDxe
EFI_STATUS PchPolicyInitDxe(IN EFI_HANDLE ImageHandle)
PCH DXE Policy Driver Entry Point
Definition: PchPolicyInitDxe.c:51
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PdtUpdateLib.h Source File

  • Library
PdtUpdateLib.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _PDT_UPDATE_LIB_H_
35 #define _PDT_UPDATE_LIB_H_
36
37 #include <Uefi.h>
38 #include <PiDxe.h>
39 #include <Library/UefiLib.h>
40 #include <Library/DebugLib.h>
41 #include <Library/MemoryAllocationLib.h>
42 #include <Library/BaseLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/IoLib.h>
45 #include <Library/UefiBootServicesTableLib.h>
46 #include <Library/UefiRuntimeServicesTableLib.h>
47 #include <Library/DxeMeLib.h>
48
49 /**
50 API to Update new PDT file by sending it to ME
51
52 @param[in] PlatformId Platform ID to be matched to in MultiPDT package
53 @param[in] FileBuffer The pointer to MultiPdt file
54 @param[in] MultiPdtSize MultiPDT file size
55
56 @retval EFI_SUCCESS Bios2Ish file send complete.
57
58 **/
59
60 EFI_STATUS
61 PdtUpdate (
62 IN UINT32 PlatformId,
63 IN UINT8 *FileBuffer,
64 IN UINT32 MultiPdtSize
65 );
66
67 #endif
PdtUpdate
EFI_STATUS PdtUpdate(IN UINT32 PlatformId, IN UINT8 *FileBuffer, IN UINT32 MultiPdtSize)
API to Update new PDT file by sending it to ME.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiBootGuardEventLogLib.h Source File

  • Library
PeiBootGuardEventLogLib.h
Go to the documentation of this file.
1 /** @file
2 This file contains functions for creating TPM Event Log
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 /**
36 Create various events in the event log as required for Bootguard Enabled Boot
37
38 @retval EFI_SUCCES Events created successfully
39 @retval Others Bootguard not supported
40 **/
41 EFI_STATUS
42 EFIAPI
43 CreateBootguardEventLogEntries (
44 IN BOOT_GUARD_INFO *BootGuardInfo
45 );
CreateBootguardEventLogEntries
EFI_STATUS CreateBootguardEventLogEntries(IN BOOT_GUARD_INFO *BootGuardInfo)
Create various events in the event log as required for Bootguard Enabled Boot.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiCpuPolicyDebugLib.h Source File

  • Library
PeiCpuPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel CPU PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_CPU_POLICY_DEBUG_LIB_H_
35 #define _PEI_CPU_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs CPU PEI Debug Policy initialization.
40
41 @param[in] SiPreMemPolicyPpi The SI PreMem Policy PPI instance
42
43 @retval EFI_SUCCESS The PPI is installed and initialized.
44 @retval EFI ERRORS The PPI is not successfully installed.
45 **/
46 EFI_STATUS
47 EFIAPI
48 UpdatePeiCpuPolicyDebugPreMem (
49 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
50 );
51
52
53 /**
54 This function performs CPU PEI Debug Policy initialization.
55
56 @param[in] SiPolicyPpi The SI Policy PPI instance
57
58 @retval EFI_SUCCESS The PPI is installed and initialized.
59 @retval EFI ERRORS The PPI is not successfully installed.
60 **/
61 EFI_STATUS
62 EFIAPI
63 UpdatePeiCpuPolicyDebug (
64 IN OUT SI_POLICY_PPI *SiPolicyPpi
65 );
66 #endif
UpdatePeiCpuPolicyDebug
EFI_STATUS UpdatePeiCpuPolicyDebug(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs CPU PEI Debug Policy initialization.
UpdatePeiCpuPolicyDebugPreMem
EFI_STATUS UpdatePeiCpuPolicyDebugPreMem(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs CPU PEI Debug Policy initialization.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiDxeBoardIdsLib.h Source File

  • Library
PeiDxeBoardIdsLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Board Information boot time changes.
3
4 @par Revision Reference:
5 SMBIOS Specification version 2.8.0 from DMTF: http://www.dmtf.org/standards/smbios
6 Intel Framework Specifications, all available at: http://www.intel.com/technology/framework/spec.htm
7 - SMBUS Host Controller Protocol Specification
8 Unified Extensible Firmware Interface (UEFI) Specifications: http://www.uefi.org/specs/
9
10 @copyright
11 INTEL CONFIDENTIAL
12 Copyright 2015 - 2016 Intel Corporation.
13
14 The source code contained or described herein and all documents related to the
15 source code ("Material") are owned by Intel Corporation or its suppliers or
16 licensors. Title to the Material remains with Intel Corporation or its suppliers
17 and licensors. The Material may contain trade secrets and proprietary and
18 confidential information of Intel Corporation and its suppliers and licensors,
19 and is protected by worldwide copyright and trade secret laws and treaty
20 provisions. No part of the Material may be used, copied, reproduced, modified,
21 published, uploaded, posted, transmitted, distributed, or disclosed in any way
22 without Intel's prior express written permission.
23
24 No license under any patent, copyright, trade secret or other intellectual
25 property right is granted to or conferred upon you by disclosure or delivery
26 of the Materials, either expressly, by implication, inducement, estoppel or
27 otherwise. Any license under such intellectual property rights must be
28 express and approved by Intel in writing.
29
30 Unless otherwise agreed by Intel in writing, you may not remove or alter
31 this notice or any other notice embedded in Materials by Intel or
32 Intel's suppliers or licensors in any way.
33
34 This file contains a 'Sample Driver' and is licensed as such under the terms
35 of your license agreement with Intel or your vendor. This file may be modified
36 by the user, subject to the additional terms of the license agreement.
37
38 @par Specification Reference:
39 **/
40
41 #ifndef _BOARDIDS__LIB_H_
42 #define _BOARDIDS_LIB_H_
43
44 extern CHAR16 *mBoardIdIndex[];
45
46 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiPchPolicyDebugLib.h Source File

  • Library
PeiPchPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel PCH PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_PCH_POLICY_DEBUG_LIB_H_
35 #define _PEI_PCH_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs PCH PEI Debug Policy initialization.
40
41 @param[in, out] SiPolicy The SI Policy PPI instance
42
43 @retval EFI_SUCCESS The PPI is installed and initialized.
44 @retval EFI ERRORS The PPI is not successfully installed.
45 **/
46 EFI_STATUS
47 EFIAPI
48 UpdatePeiPchPolicyDebug (
49 IN OUT SI_POLICY_PPI *SiPolicy
50 );
51
52 /**
53 This function performs PCH PEI Debug Policy initialization.
54
55 @param[in] PchPreMemPolicy The PCH PreMem Policy PPI instance
56
57 @retval EFI_SUCCESS The PPI is installed and initialized.
58 @retval EFI ERRORS The PPI is not successfully installed.
59 **/
60 EFI_STATUS
61 EFIAPI
62 UpdatePeiPchPolicyDebugPreMem (
63 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
64 );
65 #endif
UpdatePeiPchPolicyDebug
EFI_STATUS UpdatePeiPchPolicyDebug(IN OUT SI_POLICY_PPI *SiPolicy)
This function performs PCH PEI Debug Policy initialization.
UpdatePeiPchPolicyDebugPreMem
EFI_STATUS UpdatePeiPchPolicyDebugPreMem(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy)
This function performs PCH PEI Debug Policy initialization.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiPlatformLib.h Source File

  • Library
PeiPlatformLib.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_PLATFORM_LIB_H_
35 #define _PEI_PLATFORM_LIB_H_
36
37
38
39 #define PEI_DEVICE_DISABLED 0
40 #define PEI_DEVICE_ENABLED 1
41
42 typedef struct {
43 UINT8 Register;
44 UINT32 Value;
45 } PCH_GPIO_DEV;
46
47 //
48 // GPIO Initialization Data Structure
49 //
50 typedef struct{
51 PCH_GPIO_DEV Use_Sel;
52 PCH_GPIO_DEV Use_Sel2;
53 PCH_GPIO_DEV Use_Sel3;
54 PCH_GPIO_DEV Io_Sel;
55 PCH_GPIO_DEV Io_Sel2;
56 PCH_GPIO_DEV Io_Sel3;
57 PCH_GPIO_DEV Lvl;
58 PCH_GPIO_DEV Lvl2;
59 PCH_GPIO_DEV Lvl3;
60 PCH_GPIO_DEV Inv;
61 PCH_GPIO_DEV Blink;
62 PCH_GPIO_DEV Rst_Sel;
63 PCH_GPIO_DEV Rst_Sel2;
64 } GPIO_INIT_STRUCT;
65
66 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiPlatformRecoveryLib.h Source File

  • Library
PeiPlatformRecoveryLib.h
Go to the documentation of this file.
1 /** @file
2 This library provides platform recovery module.
3
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 1999 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_PLATFORM_RECOVERY_LIB_H_
37 #define _PEI_PLATFORM_RECOVERY_LIB_H_
38
39
40 /**
41 Provide the functionality of the recovery module.
42
43 @retval EFI_SUCCESS The function completed successfully.
44 **/
45 EFI_STATUS
46 EFIAPI
47 InitializeRecovery (
48 VOID
49 );
50 #endif
InitializeRecovery
EFI_STATUS InitializeRecovery(VOID)
Provide the functionality of the recovery module.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiPolicyBoardConfigLib.h Source File

  • Library
PeiPolicyBoardConfigLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PeiPolicyBoardConfig Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_
35 #define _PEI_POLICY_BOARD_CONFIG_LIB_H_
36
37 #include <Ppi/SiPolicy.h>
38
39 /**
40 This function performs PEI CPU Pre-Memory Policy update by board configuration.
41
42 @param[in, out] SiPolicy The SI PreMem Policy PPI instance
43
44 @retval EFI_SUCCESS The SI Policy is successfully updated.
45 @retval Others The SI Policy is not successfully updated.
46 **/
47 EFI_STATUS
48 EFIAPI
49 UpdatePeiCpuPolicyBoardConfigPreMem (
50 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
51 );
52
53 /**
54 This function performs PEI ME Pre-Memory Policy update by board configuration.
55
56 @param[in, out] SiPolicy The SI PreMem Policy PPI instance
57
58 @retval EFI_SUCCESS The SI Policy is successfully updated.
59 @retval Others The SI Policy is not successfully updated.
60 **/
61 EFI_STATUS
62 EFIAPI
63 UpdatePeiMePolicyBoardConfigPreMem (
64 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
65 );
66
67 /**
68 This function performs PEI PCH Pre-Memory Policy update by board configuration.
69
70 @param[in, out] SiPolicy The SI PreMem Policy PPI instance
71
72 @retval EFI_SUCCESS The SI Policy is successfully updated.
73 @retval Others The SI Policy is not successfully updated.
74 **/
75 EFI_STATUS
76 EFIAPI
77 UpdatePeiPchPolicyBoardConfigPreMem (
78 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
79 );
80
81 /**
82 This function performs PEI SA Pre-Memory Policy update by board configuration.
83
84 @param[in, out] SiPolicy The SI PreMem Policy PPI instance
85
86 @retval EFI_SUCCESS The SI Policy is successfully updated.
87 @retval Others The SI Policy is not successfully updated.
88 **/
89 EFI_STATUS
90 EFIAPI
91 UpdatePeiSaPolicyBoardConfigPreMem (
92 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
93 );
94
95 /**
96 This function performs PEI AMT Policy update by board configuration.
97
98 @param[in, out] SiPolicy The SI Policy PPI instance
99
100 @retval EFI_SUCCESS The SI Policy is successfully updated.
101 @retval Others The SI Policy is not successfully updated.
102 **/
103 EFI_STATUS
104 EFIAPI
105 UpdatePeiAmtPolicyBoardConfig (
106 IN OUT SI_POLICY_PPI *SiPolicyPpi
107 );
108
109 /**
110 This function performs PEI CPU Policy update by board configuration.
111
112 @param[in, out] SiPolicy The SI Policy PPI instance
113
114 @retval EFI_SUCCESS The SI Policy is successfully updated.
115 @retval Others The SI Policy is not successfully updated.
116 **/
117 EFI_STATUS
118 EFIAPI
119 UpdatePeiCpuPolicyBoardConfig (
120 IN OUT SI_POLICY_PPI *SiPolicyPpi
121 );
122
123 /**
124 This function performs PEI ME Policy update by board configuration.
125
126 @param[in, out] SiPolicy The SI Policy PPI instance
127
128 @retval EFI_SUCCESS The SI Policy is successfully updated.
129 @retval Others The SI Policy is not successfully updated.
130 **/
131 EFI_STATUS
132 EFIAPI
133 UpdatePeiMePolicyBoardConfig (
134 IN OUT SI_POLICY_PPI *SiPolicyPpi
135 );
136
137 /**
138 This function performs PEI PCH Policy update by board configuration.
139
140 @param[in, out] SiPolicy The SI Policy PPI instance
141
142 @retval EFI_SUCCESS The SI Policy is successfully updated.
143 @retval Others The SI Policy is not successfully updated.
144 **/
145 EFI_STATUS
146 EFIAPI
147 UpdatePeiPchPolicyBoardConfig (
148 IN OUT SI_POLICY_PPI *SiPolicyPpi
149 );
150
151 /**
152 This function performs PEI SA Policy update by board configuration.
153
154 @param[in, out] SiPolicy The SI Policy PPI instance
155
156 @retval EFI_SUCCESS The SI Policy is successfully updated.
157 @retval Others The SI Policy is not successfully updated.
158 **/
159 EFI_STATUS
160 EFIAPI
161 UpdatePeiSaPolicyBoardConfig (
162 IN OUT SI_POLICY_PPI *SiPolicyPpi
163 );
164
165 /**
166 This function performs PEI TBT Policy update by board configuration.
167
168 @param[in, out] SiPolicy The SI Policy PPI instance
169
170 @retval EFI_SUCCESS The SI Policy is successfully updated.
171 @retval Others The SI Policy is not successfully updated.
172 **/
173 EFI_STATUS
174 EFIAPI
175 UpdatePeiTbtPolicyBoardConfig (
176 IN OUT SI_POLICY_PPI *SiPolicyPpi
177 );
178
179 /**
180 This function performs PEI SI Policy update by board configuration.
181
182 @param[in, out] SiPolicy The SI Policy PPI instance
183
184 @retval EFI_SUCCESS The SI Policy is successfully updated.
185 @retval Others The SI Policy is not successfully updated.
186 **/
187 EFI_STATUS
188 EFIAPI
189 UpdatePeiSiPolicyBoardConfig (
190 IN OUT SI_POLICY_PPI *SiPolicyPpi
191 );
192
193 #endif
UpdatePeiCpuPolicyBoardConfig
EFI_STATUS UpdatePeiCpuPolicyBoardConfig(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI CPU Policy update by board configuration.
UpdatePeiSaPolicyBoardConfig
EFI_STATUS UpdatePeiSaPolicyBoardConfig(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI SA Policy update by board configuration.
UpdatePeiPchPolicyBoardConfigPreMem
EFI_STATUS UpdatePeiPchPolicyBoardConfigPreMem(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI PCH Pre-Memory Policy update by board configuration.
UpdatePeiPchPolicyBoardConfig
EFI_STATUS UpdatePeiPchPolicyBoardConfig(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI PCH Policy update by board configuration.
UpdatePeiCpuPolicyBoardConfigPreMem
EFI_STATUS UpdatePeiCpuPolicyBoardConfigPreMem(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI CPU Pre-Memory Policy update by board configuration.
UpdatePeiSiPolicyBoardConfig
EFI_STATUS UpdatePeiSiPolicyBoardConfig(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI SI Policy update by board configuration.
UpdatePeiAmtPolicyBoardConfig
EFI_STATUS UpdatePeiAmtPolicyBoardConfig(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI AMT Policy update by board configuration.
UpdatePeiSaPolicyBoardConfigPreMem
EFI_STATUS UpdatePeiSaPolicyBoardConfigPreMem(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI SA Pre-Memory Policy update by board configuration.
UpdatePeiMePolicyBoardConfigPreMem
EFI_STATUS UpdatePeiMePolicyBoardConfigPreMem(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs PEI ME Pre-Memory Policy update by board configuration.
UpdatePeiMePolicyBoardConfig
EFI_STATUS UpdatePeiMePolicyBoardConfig(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI ME Policy update by board configuration.
UpdatePeiTbtPolicyBoardConfig
EFI_STATUS UpdatePeiTbtPolicyBoardConfig(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs PEI TBT Policy update by board configuration.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiPolicyInitLib.h Source File

  • Library
PeiPolicyInitLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PolicyInitPei Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _POLICY_INIT_PEI_LIB_H_
35 #define _POLICY_INIT_PEI_LIB_H_
36
37 /**
38 Initialize Intel PEI Platform Policy
39
40 @param[in] FirmwareConfiguration It uses to skip specific policy init that depends
41 on the 'FirmwareConfiguration' varaible.
42 **/
43 VOID
44 EFIAPI
45 PeiPolicyInitPreMem (
46 IN UINT8 FirmwareConfiguration
47 );
48
49 /**
50 Initialize Intel PEI Platform Policy
51
52 @param[in] PeiServices General purpose services available to every PEIM.
53 @param[in] FirmwareConfiguration It uses to skip specific policy init that depends
54 on the 'FirmwareConfiguration' varaible.
55 **/
56 VOID
57 EFIAPI
58 PeiPolicyInit (
59 IN CONST EFI_PEI_SERVICES **PeiServices,
60 IN UINT8 FirmwareConfiguration
61 );
62 #endif
PeiPolicyInitPreMem
VOID PeiPolicyInitPreMem(IN UINT8 FirmwareConfiguration)
Initialize Intel PEI Platform Policy.
PeiPolicyInit
VOID PeiPolicyInit(IN CONST EFI_PEI_SERVICES **PeiServices, IN UINT8 FirmwareConfiguration)
Initialize Intel PEI Platform Policy.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiReadWriteVariableLib.h Source File

  • Library
PeiReadWriteVariableLib.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_READ_WRITE_VARIABLE_LIB_H_
35 #define _PEI_READ_WRITE_VARIABLE_LIB_H_
36
37 /**
38 Initialize PEI read write Variable PPI.
39
40 @retval Status
41 **/
42 EFI_STATUS
43 PeiReadWriteVariableInit (
44 VOID
45 );
46
47 #endif
PeiReadWriteVariableInit
EFI_STATUS PeiReadWriteVariableInit(VOID)
Initialize PEI read write Variable PPI.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiSaPolicyDebugLib.h Source File

  • Library
PeiSaPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel SA PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_SA_POLICY_DEBUG_LIB_H_
35 #define _PEI_SA_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs SA PEI Debug PreMem Policy initialization.
40
41 @param[in] SiPreMemPolicyPpi The SA PreMem Policy PPI instance
42
43 @retval EFI_SUCCESS The PPI is installed and initialized.
44 @retval EFI ERRORS The PPI is not successfully installed.
45 **/
46 EFI_STATUS
47 EFIAPI
48 UpdatePeiSaPolicyDebugPreMem (
49 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
50 );
51
52 /**
53 This function performs SA PEI Debug Policy initialization.
54
55 @param[in] SiPolicyPpi The SA Policy PPI instance
56
57 @retval EFI_SUCCESS The PPI is installed and initialized.
58 @retval EFI ERRORS The PPI is not successfully installed.
59 **/
60 EFI_STATUS
61 EFIAPI
62 UpdatePeiSaPolicyDebug (
63 IN OUT SI_POLICY_PPI *SiPolicyPpi
64 );
65 #endif
UpdatePeiSaPolicyDebug
EFI_STATUS UpdatePeiSaPolicyDebug(IN OUT SI_POLICY_PPI *SiPolicyPpi)
This function performs SA PEI Debug Policy initialization.
UpdatePeiSaPolicyDebugPreMem
EFI_STATUS UpdatePeiSaPolicyDebugPreMem(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
This function performs SA PEI Debug PreMem Policy initialization.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiSiPolicyDebugLib.h Source File

  • Library
PeiSiPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel SI PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_SI_POLICY_DEBUG_LIB_H_
35 #define _PEI_SI_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs SI PEI Debug Policy initialization.
40
41 @param[in, out] SiPolicy The SI Policy PPI instance
42
43 @retval EFI_SUCCESS The PPI is installed and initialized.
44 @retval EFI ERRORS The PPI is not successfully installed.
45 **/
46 EFI_STATUS
47 UpdatePeiSiPolicyDebug (
48 IN OUT SI_POLICY_PPI *SiPolicy
49 );
50
51 #endif
UpdatePeiSiPolicyDebug
EFI_STATUS UpdatePeiSiPolicyDebug(IN OUT SI_POLICY_PPI *SiPolicy)
This function performs SI PEI Debug Policy initialization.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiSwbpeLib.h Source File

  • Library
PeiSwbpeLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _PEI_SWBPE_LIB_H_
36 #define _PEI_SWBPE_LIB_H_
37
38 #include <DsAllocation.h>
39 #include <DsConfig.h>
40 #include <Swbpe.h>
41
42 #endif
DsAllocation.h
Swbpe.h
DsConfig.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PeiWdtAppLib.h Source File

  • Library
PeiWdtAppLib.h
Go to the documentation of this file.
1 /** @file
2 PEI WDT App library definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PEI_WDT_APP_LIB_H_
36 #define _PEI_WDT_APP_LIB_H_
37
38 #include <Base.h>
39 #include <Uefi.h>
40 #include <Ppi/Wdt.h>
41 #include <Library/DebugLib.h>
42 #include <Ppi/ReadOnlyVariable2.h>
43 #include <Library/PeiServicesLib.h>
44 #include <WdtAppVariable.h>
45
46
47 /**
48 turns on WDT during PEI phase according to requests made by
49 OS overclocking application (through WDT status) and BIOS modules (through flash variable)
50
51 @param[in] WdtPei
52
53 @retval EFI_SUCCESS
54 **/
55 EFI_STATUS
56 PeiWdtApp (
57 IN WDT_PPI *WdtPei
58 );
59
60 #endif
PeiWdtApp
EFI_STATUS PeiWdtApp(IN WDT_PPI *WdtPei)
turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT ...
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Platform.h Source File

Platform.h
Go to the documentation of this file.
1 /** @file
2 This header file provides platform specific definitions used
3 by other modules for platform specific initialization.
4 This is not suitable for consumption by ASL or VRF files.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 2004 - 2016 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _PLATFORM_H_
38 #define _PLATFORM_H_
39
40 #include "CommonDefinitions.h"
41 #include "PchAccess.h"
42 #include "SaAccess.h"
43
44 //
45 // Need minimum of 48MB during PEI phase for IAG and some buffer for boot.
46 //
47 #ifdef PCH_ICL
48 #define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
49 #define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
50 #else
51 #define PEI_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) // 80MB + 256MB
52 #define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) // 80MB + 256MB
53 #endif
54
55 #define FLASH_BLOCK_SIZE 0x10000
56
57 #define CPU_EXTERNAL_CLOCK_FREQ 0x64
58 #define CPU_FREQUENCY_MODE_100 0x64
59 #define FREQUENCY_RESOLUTION_3182 0xc6e
60 #define NDIVIDER_BASE_VALUE 0x19d
61 #define MDIVIDER_VALUE_13 0xd
62
63 #endif
CommonDefinitions.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformBoardConfig.h Source File

PlatformBoardConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for Platform Boards Configurations.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_BOARD_CONFIG_H
36 #define _PLATFORM_BOARD_CONFIG_H
37
38 #include <ConfigBlock.h>
39 #include <PchPolicyCommon.h>
40 #include <ConfigBlock/MemoryConfig.h>
41 #include <GpioConfig.h>
42
43 #define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
44 #define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) & 0xFFF0))
45
46 #define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001
47 #define BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001
48 #define BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001
49 #define BOARD_NO_BATTERY_SUPPORT 0
50 #define BOARD_REAL_BATTERY_SUPPORTED BIT0
51 #define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
52
53 //
54 // ACPI table information used to update tables thru PCD
55 //
56 #define ACPI_OEM_TABLE_ID_ICL_ULT 0x544C552D4C4349 // ICL-ULT
57
58 #pragma pack(1)
59
60 typedef struct {
61 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
62 } BOARD_CONFIG_BLOCK;
63
64 typedef struct {
65 UINT8 GpioSupport;
66 UINT32 WakeGpioNo;
67 UINT8 HoldRstExpanderNo;
68 UINT32 HoldRstGpioNo;
69 BOOLEAN HoldRstActive;
70 UINT8 PwrEnableExpanderNo;
71 UINT32 PwrEnableGpioNo;
72 BOOLEAN PwrEnableActive;
73 } SWITCH_GRAPHIC_GPIO;
74
75 typedef struct {
76 UINT8 ClkReqNumber : 4;
77 UINT8 ClkReqSupported : 1;
78 UINT8 DeviceResetPadActiveHigh : 1;
79 UINT32 DeviceResetPad;
80 } ROOT_PORT_CLK_INFO;
81
82 typedef struct {
83 UINT8 Section;
84 UINT8 Pin;
85 } EXPANDER_GPIO_CONFIG;
86
87 typedef enum {
88 BoardGpioTypePch,
89 BoardGpioTypeExpander,
90 BoardGpioTypeNotSupported = 0xFF
91 } BOARD_GPIO_TYPE;
92
93 typedef struct {
94 UINT8 Type;
95 UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
96 union {
97 UINT32 Pin;
98 EXPANDER_GPIO_CONFIG Expander;
99 } u;
100 } BOARD_GPIO_CONFIG;
101
102 // Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
103 #define NOT_USED 0xFF
104 #define FREE_RUNNING 0x80
105 #define LAN_CLOCK 0x70
106 #define PCIE_PEG 0x40
107 #define PCIE_PCH 0x00
108
109 typedef struct {
110 UINT32 ClockUsage;
111 UINT32 ClkReqSupported;
112 } PCIE_CLOCK_CONFIG;
113
114 typedef union {
115 UINT64 Blob;
116 BOARD_GPIO_CONFIG BoardGpioConfig;
117 ROOT_PORT_CLK_INFO Info;
118 PCIE_CLOCK_CONFIG PcieClock;
119 } PCD64_BLOB;
120
121 typedef union {
122 UINT32 Blob;
123 USB20_AFE Info;
124 } PCD32_BLOB;
125
126 #ifndef IO_EXPANDER_DISABLED
127 #define IO_EXPANDER_DISABLED 0xFF
128 #endif
129
130 #define SPD_DATA_SIZE 512
131
132 #pragma pack()
133
134 #endif // _PLATFORM_BOARD_CONFIG_H
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformBoardId.h Source File

PlatformBoardId.h
Go to the documentation of this file.
1 /** @file
2 Defines Platform BoardIds
3
4 @copyright
5 "INTEL CONFIDENTIAL
6 Copyright 2011 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way."
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_BOARD_ID_H_
36 #define _PLATFORM_BOARD_ID_H_
37
38 #define FlavorUnknown 0x0
39 #define FlavorMobile 0x1
40 #define FlavorDesktop 0x2
41 #define FlavorWorkstation 0x3
42 #define FlavorUpServer 0x4
43 #define FlavorEmbedded 0x5
44 #define FlavorPlatformMax 0x6
45
46 #define TypeUnknown 0x0
47 #define TypeTrad 0x1
48 #define TypeUltUlx 0x2
49
50 //
51 // CannonLake Board Id 0x00 - 0xF
52 //
53 //#define BoardIdCannonlakeX0Lpddr4 0x00
54 #define BoardIdCannonlakeUDdr4Rvp 0x01
55 #define BoardIdCannonlakeULpddr4Rvp 0x02
56 #define BoardIdCannonlakeULpdimmDvp 0x03
57 //#define BoardIdSkylakeA0Rvp3 0x04
58 #define BoardIdCannonlakeUSds 0x05
59 #define BoardIdCannonLakeYLpddr3 0x06
60 #define BoardIdCannonLakeYLpddr4 0x07
61 //#define BoardIdCannonLakeLpdimmDoe 0x08
62 //#define BoardIdCannonLakeIdv1 0x09
63 #define BoardIdCannonLakeHDdr4 0x0B
64 #define BoardIdCannonLakeHLpddr4 0x0D
65 //#define BoardIdCannonlakeULpddr3Rvp5 0x0E
66
67 //
68 // Simics Boards
69 //
70 #define BoardIdIclSimicsDdr4Rvp2 0x02
71
72
73 //
74 // CoffeeLake Board Id's 0x10 - 0x1F
75 //
76 #define BoardIdCoffeeLakeULpddr3CpuBrd 0x10 // This is KC PnP skew and has two board's one for CPU and one for Companion Card
77 #define BoardIdCoffeeLakeULpddr3CompBrd 0x11 // Companion Card PnP board Id
78 #define BoardIdCoffeeLakeUDdr4 0x12 // PI/merged power plane board
79 //0x13 reserved for U
80 //0x14 reserved for U
81 //0x15 reserved for U
82 #define BoardIdCoffeeLakeHDdr4 0x16
83 //0x17 reserved for H
84 #define BoardIdCoffeeLakeSUdimm 0x18 // PI/merged power plane board
85 #define BoardIdCoffeeLakeSSodimm 0x19 // PnP board
86 #define BoardIdCoffeeLakeOCUdimm 0x1A // CFL-S OC board
87 //0x1B reserved for S
88 //0x1C reserved for Generic use
89 //0x1D reserved for Generic use
90 //0x1E reserved for Generic use
91 //0x1F reserved for Generic use
92
93 #define BoardIdUnknown1 0xffff
94
95 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformClock.h Source File

PlatformClock.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _PLATFORM_DEFINITIONS_CLOCK_H_
35 #define _PLATFORM_DEFINITIONS_CLOCK_H_
36
37 //
38 // Clock controller SMBUS address
39 //
40 #define CLOCK_CONTROLLER_SMBUS_ADDRESS 0xD2
41
42 //
43 // Redfort platform CK505 configuration bytes 0~12
44 // (Reference: Table 21, CK505 Clock Synthesizer Specification Revision 1.0
45 // October 2006 Intel)
46 //
47 // BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
48 // =================================================================================
49 // Byte 0
50 // ------
51 // FSC(r) FSB(r) FSA(r) MT_EN Reserved SRC_MAIN SATA_SEL PD_RESTORE
52 // _SEL
53 // 0 0 0 0 0 1 0 1
54 //
55 // Byte 1
56 // ------
57 // SRC0_SEL PLL1_SSC PLL3_SSC PLL3_CFB3 PLL3_CFB2 PLL3_CFB1 PLL3_CFB0 PCI_SEL
58 // _DC _DC
59 // 1 0 0 0 0 0 1 1
60 //
61 // Byte 2
62 // ------
63 // REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE
64 // 1 0 0 0 0 0 0 0
65 //
66 // Byte 3
67 // ------
68 // SRC11_OE SRC10_OE SRC9_OE SRC8/ITP SRC7_OE SRC6_OE SRC5_OE SRC4_OE
69 // _OE
70 // 0 0 0 0 0 0 0 0
71 //
72 // Byte 4
73 // ------
74 // SRC3_OE SATA/SRC2 SRC1_OE SRC0 CPU1_OE CPU0_OE PLL1_SSC PLL3_SSC_EN
75 // _OE /DOT96_OE _EN
76 // 0 1 1 1 0 1 0 0
77 //
78 // Byte 5
79 // ------
80 // CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL
81 // 0 0 0 0 0 0 0 0
82 //
83 // Byte 6
84 // ------
85 // CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP SRC_STP_CRTL
86 // _CRTL
87 // 0 0 0 0 0 0 0 0
88 //
89 // Byte 7
90 // ------
91 // RC Bit3(r) RC Bit2(r) RC Bit1(r) RC Bit0(r) VID Bit3(r)VID Bit2(r)VID Bit1(r)VID Bit0(r)
92 // 0 0 0 0 0 0 0 0
93 //
94 // Byte 8
95 // ------
96 // DID3(r) DID2(r) DID1(r) DID0(r) Reserved Reserved SE1_OE SE2_OE
97 // 0 0 0 0 0 0 0 0
98 //
99 // Byte 9
100 // ------
101 // PCIF5_STP TME_STRAP REF_DRIVE TEST_MODE TEST_MODE IO_VOUT2 IO_VOUT1 IO_VOUT0
102 // _CTRL (r) _SEL _ENTRY
103 // 0 0 1 0 0 1 0 1
104 //
105 // Byte 10
106 // -------
107 // SRC5_EN PLL3_EN PLL2_EN SRC_DIV_EN PCI_DIV_EN CPU_DIV_EN CPU1_STOP CPU0_STOP
108 // _STRAP(r) _EN _EN
109 // 1 1 1 0 0 0 0 0
110 //
111 // Byte 11
112 // -------
113 // PCI3_CFG1 PCI3_CFG0 25MHZ_EN PLL4_EN CPU2_AMT CPU1_AMT PCI-E_GEN2 CPU2_STOP
114 // (r) (r) _SE1 _EN _EN (r) _EN
115 // 0 1 0 1 0 0 1 0
116 //
117 // Byte 12
118 // -------
119 // Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0
120 // 0 0 0 0 1 1 0 1
121 //
122
123 #define MOBILE_CLOCK_CONTROLLER_SETTINGS {0x05, 0x83, 0x80, 0, 0x77, 0x00, 0x0, 0x00, 0, 0x25, 0xe0, 0x52, 0xd}
124 #define DESKTOP_CLOCK_CONTROLLER_SETTINGS {0x35, 0x83, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x26, 0x03, 0x25, 0xFD, 0x56}
125
126 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformConfigurationChangeVariable.h Source File

PlatformConfigurationChangeVariable.h
Go to the documentation of this file.
1 /** @file
2 Platform configuration change variable definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PLATFORM_CONFIGURATION_CHANGE_VARIABLE_H__
36 #define __PLATFORM_CONFIGURATION_CHANGE_VARIABLE_H__
37
38 #define EFI_TREE_PHYSICAL_PRESENCE_DATA_GUID \
39 { \
40 0xe3cacf62, 0x3062, 0x4e1d, { 0x97, 0x8e, 0x46, 0x80, 0x7a, 0xb9, 0x74, 0x7d }\
41 }
42
43 #define PLATFORM_CONFIGURATION_CHANGE L"PlatformConfigurationChange"
44
45 #define NO_CONFIG_CHANGE 0x00000000
46 #define FIRST_BOOT 0x00000001
47 #define SETUP_OPTION_CHANGE 0x00000002
48
49 typedef struct {
50 UINT32 ConfigChangeType; /// Significant change from previous boot
51 } CONFIGURATION_CHANGE;
52
53 #endif
54
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformEmmcHs400Info.h Source File

  • Guid
PlatformEmmcHs400Info.h
Go to the documentation of this file.
1 /** @file
2 GUID used for Platform Emmc Hs400 Tuning Info NVRAM Data
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PLATFORM_EMMC_HS400_TUNING_INFO_GUID_H_
35 #define _PLATFORM_EMMC_HS400_TUNING_INFO_GUID_H_
36
37 #define HS400_TUNING_DATA_VAR L"Hs400TuningData"
38
39 /**
40 This structure describes the variable to be set with the returned EMMC_TUNING_DATA
41 from EMMC_TUNE protocol.
42 **/
43 typedef struct _PLATFORM_EMMC_TUNING_DATA {
44 /**
45 eMMC HS400 Data Validation Status
46 0: HS400 Data is invalid, 1: HS400 Data is valid
47 **/
48 UINT8 Hs400DataValid;
49 UINT8 Hs400RxStrobe1Dll; ///< Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)
50 UINT8 Hs400TxDataDll; ///< Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)
51 } PLATFORM_EMMC_TUNING_DATA;
52
53
54 #endif
_PLATFORM_EMMC_TUNING_DATA::Hs400TxDataDll
UINT8 Hs400TxDataDll
Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)
Definition: PlatformEmmcHs400Info.h:50
_PLATFORM_EMMC_TUNING_DATA::Hs400RxStrobe1Dll
UINT8 Hs400RxStrobe1Dll
Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)
Definition: PlatformEmmcHs400Info.h:49
_PLATFORM_EMMC_TUNING_DATA::Hs400DataValid
UINT8 Hs400DataValid
eMMC HS400 Data Validation Status 0: HS400 Data is invalid, 1: HS400 Data is valid ...
Definition: PlatformEmmcHs400Info.h:48
_PLATFORM_EMMC_TUNING_DATA
This structure describes the variable to be set with the returned EMMC_TUNING_DATA from EMMC_TUNE pro...
Definition: PlatformEmmcHs400Info.h:43
PLATFORM_EMMC_TUNING_DATA
struct _PLATFORM_EMMC_TUNING_DATA PLATFORM_EMMC_TUNING_DATA
This structure describes the variable to be set with the returned EMMC_TUNING_DATA from EMMC_TUNE pro...
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformGlobalVariable.h Source File

  • Guid
PlatformGlobalVariable.h
Go to the documentation of this file.
1 /** @file
2 GUID for Platform (NVRAM) Variables.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PLATFORM_GLOBAL_VARIABLE_GUID_H__
36 #define __PLATFORM_GLOBAL_VARIABLE_GUID_H__
37
38 #define PLATFORM_GLOBAL_VARIABLE \
39 { \
40 0xa5dabcf0, 0xc7a1, 0x4370, { 0x8c, 0x21, 0xfa, 0x50, 0xd3, 0x22, 0xa4, 0x3e } \
41 }
42
43 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformInfo.h Source File

PlatformInfo.h
Go to the documentation of this file.
1 /** @file
2 GUID used for Platform Info Data entries in the HOB list.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _PLATFORM_INFO_H_
37 #define _PLATFORM_INFO_H_
38
39 #include <PlatformBoardType.h>
40
41 #pragma pack(1)
42
43 ///
44 /// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h
45 ///
46 typedef UINT32 PCH_GPIO_PAD; //Copied from GpioConfig.h (need to change it based on include)
47
48 typedef struct {
49 UINT8 Expander;
50 UINT8 Pin;
51 UINT16 Reserved; // Reserved for future use
52 } IO_EXPANDER_PAD;
53
54 typedef union {
55 PCH_GPIO_PAD PchGpio;
56 IO_EXPANDER_PAD IoExpGpio;
57 } GPIO_PAD_CONFIG;
58
59 typedef struct {
60 UINT8 GpioType; // 0: Disabled (no GPIO support), 1: PCH, 2: I/O Expander
61 UINT8 Reserved[3]; // Reserved for future use
62 GPIO_PAD_CONFIG GpioData;
63 } PACKED_GPIO_CONFIG;
64
65 typedef union {
66 PACKED_GPIO_CONFIG PackedGpio;
67 UINT64 Data64;
68 } COMMON_GPIO_CONFIG;
69
70 #pragma pack()
71
72 #endif
PCH_GPIO_PAD
UINT32 PCH_GPIO_PAD
PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h.
Definition: PlatformInfo.h:46
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformInit.c Source File

  • PlatformInit
  • PlatformInitPei
PlatformInit.c
Go to the documentation of this file.
1 /** @file
2 Source code file for Platform Init PEI module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Register/Msr.h>
36 #include <CpuRegs.h>
37 #include <PchAccess.h>
38 #include <MeChipset.h>
39 #include <SetupVariable.h>
40 #include <Library/IoLib.h>
41 #include <Library/HobLib.h>
42 #include <Library/DebugLib.h>
43 #include <Library/PchInfoLib.h>
44 #include <Library/BaseMemoryLib.h>
45 #include <Library/PeiServicesLib.h>
46 #include <Library/PciSegmentLib.h>
47 #include <IndustryStandard/Pci30.h>
48 #include <Library/PchCycleDecodingLib.h>
49 #include <Library/PmcLib.h>
50 #include <Library/GpioLib.h>
51 #include <Library/PeiPolicyInitLib.h>
52 #include <Ppi/EndOfPeiPhase.h>
53 #include <Library/MtrrLib.h>
54 #include <Ppi/ReadOnlyVariable2.h>
55 #include <Guid/SmramMemoryReserve.h>
56 #include <Library/PeiReadWriteVariableLib.h>
57 #include <Library/ConfigBlockLib.h>
58 #include <Ppi/SiPolicy.h>
59 #include <SaPolicyCommon.h>
60 #include <Library/SiPolicyLib.h>
61 #include <Board/Include/PeiPlatformHookLib.h>
62
63 #include <Guid/FirmwareFileSystem2.h>
64 #include <Protocol/FirmwareVolumeBlock.h>
65 #include <Guid/SystemNvDataGuid.h>
66
67 #include <AttemptUsbFirst.h>
68
69 #include <Library/BoardConfigLib.h>
70 #include <Board/Include/BoardHook.h>
71
72 #include <Ppi/I2cMaster.h>
73 #include <Library/TimerLib.h>
74 #include "PlatformBoardId.h"
75 #include <Library/EcLib.h>
76 #include <Library/PostCodeLib.h>
77 #include <PlatformPostCode.h>
78 #include <Library/EcTcssLib.h>
79 #include <SaTcssHob.h>
80 #include <Library/ItbtPcieRpLib.h>
81
82 #define I2C_SAR_ADDRESS_SDS 0x28
83 #define I2C_WRITE 0
84
85 EFI_STATUS
86 EFIAPI
87 PlatformInitEndOfPei (
88 IN CONST EFI_PEI_SERVICES **PeiServices,
89 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
90 IN VOID *Ppi
91 );
92
93 static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
94 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
95 &gEfiEndOfPeiSignalPpiGuid,
96 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitEndOfPei
97 };
98
99 /**
100 Update MTRR setting and set write back as default memory attribute.
101
102 @retval EFI_SUCCESS The function completes successfully.
103 @retval Others Some error occurs.
104 **/
105 EFI_STATUS
106 EFIAPI
107 SetCacheMtrrAfterEndOfPei (
108 VOID
109 )
110 {
111 EFI_STATUS Status;
112 MTRR_SETTINGS MtrrSetting;
113 EFI_PEI_HOB_POINTERS Hob;
114 UINT64 MemoryBase;
115 UINT64 MemoryLength;
116 UINT64 Power2Length;
117 EFI_BOOT_MODE BootMode;
118 UINTN Index;
119 UINT64 SmramSize;
120 UINT64 SmramBase;
121 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
122 SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
123 SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
124 UINT32 IedSize;
125 SI_POLICY_PPI *SiPolicy;
126 SI_CONFIG *SiConfig;
127 UINT32 TraceHubMemSize;
128
129 Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicy);
130 ASSERT_EFI_ERROR(Status);
131
132 Status = GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &SiConfig);
133 ASSERT_EFI_ERROR (Status);
134
135 Status = PeiServicesGetBootMode (&BootMode);
136 ASSERT_EFI_ERROR (Status);
137
138 if (BootMode == BOOT_ON_S3_RESUME) {
139 return EFI_SUCCESS;
140 }
141
142 IedSize = 0;
143 MiscPeiPreMemConfig = NULL;
144 //
145 // Obtain SA policy settings.
146 //
147 Status = PeiServicesLocatePpi (
148 &gSiPreMemPolicyPpiGuid,
149 0,
150 NULL,
151 (VOID **) &SiPreMemPolicyPpi
152 );
153 ASSERT_EFI_ERROR (Status);
154 if (!EFI_ERROR(Status)) {
155 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
156 ASSERT_EFI_ERROR (Status);
157 if (MiscPeiPreMemConfig != NULL) {
158 IedSize = MiscPeiPreMemConfig->IedSize;
159 }
160 }
161
162 //
163 // Clear the CAR Settings
164 //
165 ZeroMem (&MtrrSetting, sizeof (MTRR_SETTINGS));
166
167 //
168 // Default Cachable attribute will be set to WB to support large memory size/hot plug memory
169 //
170 MtrrSetting.MtrrDefType &= ~((UINT64)(0xFF));
171 MtrrSetting.MtrrDefType |= (UINT64) CacheWriteBack;
172
173 //
174 // Set fixed cache for memory range below 1MB
175 //
176 Status = MtrrSetMemoryAttributeInMtrrSettings (
177 &MtrrSetting,
178 0x0,
179 0xA0000,
180 CacheWriteBack
181 );
182 ASSERT_EFI_ERROR (Status);
183
184 Status = MtrrSetMemoryAttributeInMtrrSettings (
185 &MtrrSetting,
186 0xA0000,
187 0x20000,
188 CacheUncacheable
189 );
190 ASSERT_EFI_ERROR (Status);
191
192 Status = MtrrSetMemoryAttributeInMtrrSettings (
193 &MtrrSetting,
194 0xC0000,
195 0x40000,
196 CacheWriteProtected
197 );
198 ASSERT_EFI_ERROR ( Status);
199
200 //
201 // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
202 // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
203 //
204 SmramSize = 0;
205 SmramBase = 0;
206 Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
207 while (!END_OF_HOB_LIST (Hob)) {
208 if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
209 if (CompareGuid (&Hob.Guid->Name, &gEfiSmmPeiSmramMemoryReserveGuid)) {
210 SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
211 for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
212 if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
213 SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
214 if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
215 SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
216 }
217 }
218 }
219 break;
220 }
221 }
222 Hob.Raw = GET_NEXT_HOB (Hob);
223 }
224
225 //
226 // Set non system memory as UC
227 //
228 MemoryBase = 0x100000000;
229
230 //
231 // Add IED size to set whole SMRAM as WB to save MTRR count
232 //
233 SmramSize += IedSize;
234 MemoryLength = MemoryBase - (SmramBase + SmramSize);
235 while (MemoryLength != 0) {
236 Power2Length = GetPowerOfTwo64 (MemoryLength);
237 MemoryBase -= Power2Length;
238 Status = MtrrSetMemoryAttributeInMtrrSettings (
239 &MtrrSetting,
240 MemoryBase,
241 Power2Length,
242 CacheUncacheable
243 );
244 ASSERT_EFI_ERROR (Status);
245 MemoryLength -= Power2Length;
246 }
247
248 //
249 // Get Trace Hub memory base and size
250 //
251 TraceHubMemSize = TraceHubCalculateTotalBufferSize (SiPreMemPolicyPpi);
252 if (TraceHubMemSize > 0) {
253 DEBUG ((DEBUG_INFO, "PlatformInit Set MTRR UC for Trace hub\n"));
254 DEBUG ((DEBUG_INFO, "Trace Hub Mem Size = 0x%08x\n", TraceHubMemSize));
255 DEBUG ((DEBUG_INFO, "Trace Hub Mem Base = 0x%08x\n", SiConfig->TraceHubMemBase));
256 Status = MtrrSetMemoryAttributeInMtrrSettings (
257 &MtrrSetting,
258 SiConfig->TraceHubMemBase,
259 TraceHubMemSize,
260 CacheUncacheable
261 );
262 ASSERT_EFI_ERROR (Status);
263 }
264
265
266 //
267 // Update MTRR setting from MTRR buffer
268 //
269 MtrrSetAllMtrrs (&MtrrSetting);
270
271 return Status;
272 }
273
274 /**
275 Reset the SAR Sensor to ensure the SAR sensor can trigger an edge to the WWAN module on SKL SDS for FCC compliance.
276
277 @retval EFI_SUCCESS The function completes successfully.
278 @retval Others Some error occurs.
279 **/
280 EFI_STATUS
281 EFIAPI
282 ResetSarSensorSklSds (
283 VOID
284 )
285 {
286 EFI_STATUS Status;
287 UINTN Speed;
288 EFI_I2C_REQUEST_PACKET Packet;
289 UINT8 Buffer[2];
290 UINTN Instance;
291 EFI_PEI_I2C_MASTER_PPI *MasterPpi;
292 UINT64 Ticker;
293 UINT64 TimeNanoSeconds;
294 UINT64 DelayFromReset;
295 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
296 SETUP_DATA SystemConfiguration;
297 UINTN VariableSize;
298
299 Status = PeiServicesLocatePpi (
300 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
301 0, // INSTANCE
302 NULL, // EFI_PEI_PPI_DESCRIPTOR
303 (VOID **) &VariableServices // PPI
304 );
305 if (EFI_ERROR(Status)) {
306 DEBUG ((DEBUG_ERROR, "ResetSarSensorSklSds: Failed to find PEI Read Variable support. Status = %r\n", Status));
307 }
308 ASSERT_EFI_ERROR (Status);
309
310 VariableSize = sizeof (SETUP_DATA);
311 Status = VariableServices->GetVariable (
312 VariableServices,
313 PLATFORM_SETUP_VARIABLE_NAME,
314 &gSetupVariableGuid,
315 NULL,
316 &VariableSize,
317 &SystemConfiguration
318 );
319
320 //
321 // If WWAN is diabled skip SAR Reset Delay, else get the reset delay from the BIOS menu option
322 //
323 if (EFI_ERROR(Status) || !SystemConfiguration.WWANEnable) {
324 DEBUG ((DEBUG_ERROR, "ResetSarSensorSklSds: Either GetVariable failed or WWAN is disabled. Status = %r\n", Status));
325 return (Status);
326 }
327 DelayFromReset = SystemConfiguration.I2cSarResetDelay;
328 DEBUG ((DEBUG_INFO, "ResetSarSensorSklSds: Specified delay is %d seconds.\n", DelayFromReset));
329
330 //
331 // Wait for the reset delay (number of seconds after reset until SAR Sensor reset can be issued)
332 //
333 Ticker = GetPerformanceCounter();
334 TimeNanoSeconds = GetTimeInNanoSecond (Ticker);
335
336 while (TimeNanoSeconds < MultU64x32(DelayFromReset, 1000000000)) {
337 MicroSecondDelay(200);
338 Ticker = GetPerformanceCounter();
339 TimeNanoSeconds = GetTimeInNanoSecond (Ticker);
340 }
341
342 //
343 // Issue SAR Sensor Reset to trigger edge to WWAN module
344 //
345 Speed = 0;
346 Instance = 0;
347 Status = EFI_SUCCESS;
348 while(TRUE) {
349 Status = PeiServicesLocatePpi (&gEfiPeiI2cMasterPpiGuid, Instance, NULL, (VOID **) &MasterPpi);
350 if (EFI_ERROR (Status)) {
351 break;
352 }
353 if (CompareGuid (&(MasterPpi->Identifier), &gI2c0MasterGuid)) { // We know that the I2C device is I2C0 for SKL SDS
354 break;
355 }
356 Instance++;
357 }
358 if (EFI_ERROR (Status)) {
359 DEBUG ((DEBUG_ERROR, "ResetSarSensorSklSds: Fail to Locate I2C PPI! Status = %r\n", Status));
360 } else {
361 Speed = (UINTN)(100000);
362 Status = MasterPpi->SetBusFrequency(MasterPpi,&Speed);
363
364 if (EFI_ERROR(Status)) {
365 DEBUG ((DEBUG_ERROR, "ResetSarSensorSklSds: SetBusFrequency Failed. Status = %r\n", Status));
366 return (Status);
367 }
368
369 Packet.OperationCount = 1;
370 Packet.Operation[0].Flags = I2C_WRITE;
371 Packet.Operation[0].LengthInBytes = 2;
372 Packet.Operation[0].Buffer = Buffer;
373 Buffer[0] = 0x7f;
374 Buffer[1] = 0xde;
375 Status = MasterPpi->StartRequest(MasterPpi, I2C_SAR_ADDRESS_SDS, &Packet); //SAR Sensor I2C address is 0x28 on SKL SDS
376 if (EFI_ERROR(Status)) {
377 DEBUG ((DEBUG_ERROR, "ResetSarSensorSklSds: StartRequest Failed. Status = %r\n", Status));
378 return (Status);
379 }
380
381 DEBUG ((DEBUG_INFO, "Finished I2C 0x28 write to SAR sensor\n"));
382 }
383
384 return (Status);
385 }
386
387 /**
388 This function sends IOM Ready Notify message to EC
389
390 @retval EFI_SUCCESS The function completed successfully
391 @retval EFI_NOT_READY IomReady bit is not set
392 @retval others Some error occurred
393 **/
394 EFI_STATUS
395 IOMReadyNotifyToEC (
396 VOID
397 )
398 {
399 EFI_STATUS Status;
400 SA_SETUP SaSetup;
401 SETUP_DATA SystemConfiguration;
402 UINTN VariableSize;
403 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
404 UINT8 EcDataBuffer;
405 UINT8 ReplayMsgBitMask;
406 UINT8 VccstBitMask;
407 EFI_BOOT_MODE BootMode;
408 SA_TCSS_HOB *TcssHob;
409
410 TcssHob = NULL;
411 ///
412 /// Locate HOB for TCSS Data and read IOM ready state
413 ///
414 TcssHob = (SA_TCSS_HOB *) GetFirstGuidHob (&gSaTcssHobGuid);
415 if (TcssHob == NULL) {
416 return EFI_NOT_READY;
417 }
418 if (!TcssHob->TcssData.IOMReady) {
419 DEBUG ((DEBUG_ERROR, "IOMReadyNotifyToEC: IOMReady bit not set in TcssHob.\n"));
420 return EFI_NOT_READY;
421 }
422
423 Status = PeiServicesLocatePpi (
424 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
425 0, // INSTANCE
426 NULL, // EFI_PEI_PPI_DESCRIPTOR
427 (VOID **) &VariableServices // PPI
428 );
429 if (EFI_ERROR(Status)) {
430 DEBUG ((DEBUG_ERROR, "IOMReadyNotifyToEC: Failed to find PEI Read Variable support. Status = %r\n", Status));
431 }
432 else {
433 VariableSize = sizeof (SETUP_DATA);
434 Status = VariableServices->GetVariable (
435 VariableServices,
436 PLATFORM_SETUP_VARIABLE_NAME,
437 &gSetupVariableGuid,
438 NULL,
439 &VariableSize,
440 &SystemConfiguration
441 );
442 ASSERT_EFI_ERROR (Status);
443 //
444 // Send IOMReadyNotify only if EC Handshake is enabled in BIOS setup
445 //
446 if (!EFI_ERROR(Status) && SystemConfiguration.UsbcBiosTcssHandshake == 1) {
447 PeiServicesGetBootMode (&BootMode);
448 VariableSize = sizeof (SA_SETUP);
449 Status = VariableServices->GetVariable (
450 VariableServices,
451 L"SaSetup",
452 &gSetupVariableGuid,
453 NULL,
454 &VariableSize,
455 &SaSetup
456 );
457 // Todo: add other condition (boot mode) checks here.
458
459 EcDataBuffer = 0x00;
460 ReplayMsgBitMask = EC_TCSS_BITMASK_REPLAY_MESSAGES;
461
462 if (!EFI_ERROR (Status)) {
463 VccstBitMask = SaSetup.TcssVccstStatus;
464 //
465 // S4 and S5 flow
466 //
467 if ((BootMode == BOOT_ON_S4_RESUME) || (BootMode == BOOT_ON_S5_RESUME)) {
468 if (SaSetup.TcssVccstStatus == 1) {
469 //
470 // Clear ReplayMsgBitMask after checking VccstStatus policy.
471 //
472 ReplayMsgBitMask = 0x00;
473 }
474 } else if (BootMode == BOOT_ON_S3_RESUME) {
475 //
476 // For S3 resume, clear replay bit always as Platform EC doesn't support replay in S3
477 //
478 ReplayMsgBitMask = 0x00;
479 }
480 }
481 EcDataBuffer = ReplayMsgBitMask | VccstBitMask;
482 Status = UsbcIomReadyNotify(&EcDataBuffer);
483 // Todo: Add error condition check if Status is not success
484 }
485 }
486 return Status;
487 }
488
489
490 /**
491 This function handles PlatformInit task at the end of PEI
492
493 @param[in] PeiServices Pointer to PEI Services Table.
494 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
495 caused this function to execute.
496 @param[in] Ppi Pointer to the PPI data associated with this function.
497
498 @retval EFI_SUCCESS The function completes successfully
499 @retval others
500 **/
501 EFI_STATUS
502 EFIAPI
503 PlatformInitEndOfPei (
504 IN CONST EFI_PEI_SERVICES **PeiServices,
505 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
506 IN VOID *Ppi
507 )
508 {
509 EFI_STATUS Status;
510
511 Status = SetCacheMtrrAfterEndOfPei ();
512 ASSERT_EFI_ERROR (Status);
513
514 #ifdef FSP_WRAPPER_FLAG
515 //
516 // Update the TBT Device Info into Internal Structure for Wrapper side.
517 //
518 InitializeItbtDevInfo ();
519 #endif
520
521 //
522 // Send IOM Ready Notify message to EC
523 //
524 Status = IOMReadyNotifyToEC ();
525
526 //
527 //Function to enable VM in case HD Audio is Disabled
528 //
529 PremiumPmicEnableSlpS0Voltage();
530
531 return Status;
532 }
533
534 //@todo Review this functionality and if it is required for SKL SDS
535 /**
536 Create the HOB for hotkey status for 'Attempt USB First' feature
537
538 @retval EFI_SUCCESS HOB Creating successful.
539 @retval Others HOB Creating failed.
540 **/
541 EFI_STATUS
542 CreateAttemptUsbFirstHotkeyInfoHob (
543 VOID
544 )
545 {
546 EFI_STATUS Status;
547 ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
548 VOID *Hob;
549
550 Status = EFI_SUCCESS;
551
552 ZeroMem (
553 &AttemptUsbFirstHotkeyInfo,
554 sizeof (AttemptUsbFirstHotkeyInfo)
555 );
556
557 AttemptUsbFirstHotkeyInfo.RevisonId = 0;
558 AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE;
559
560 ///
561 /// Build HOB for Attempt USB First feature
562 ///
563 Hob = BuildGuidDataHob (
564 &gAttemptUsbFirstHotkeyInfoHobGuid,
565 &(AttemptUsbFirstHotkeyInfo),
566 sizeof (ATTEMPT_USB_FIRST_HOTKEY_INFO)
567 );
568
569 return Status;
570 }
571
572 /**
573 Get the BIOS Guard Module pointer.
574
575 @param[in, out] ModulePtr - Input is a NULL pointer,
576 and output points BIOS Guard module address if found.
577
578 @retval EFI_SUCCESS - BIOS Guard Module found.
579 @retval EFI_NOT_FOUND - BIOS Guard Module not found.
580 **/
581 EFI_STATUS
582 UpdateBiosGuardModulePtr (
583 IN OUT EFI_PHYSICAL_ADDRESS *ModulePtr
584 )
585 {
586 EFI_STATUS Status;
587 EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
588 EFI_FFS_FILE_HEADER *FfsFile;
589 EFI_GUID *BiosGuardModuleGuidPtr;
590 UINT32 ModuleAddr;
591
592 BiosGuardModuleGuidPtr = &gBiosGuardModuleGuid;
593 FfsFile = NULL;
594 Status = EFI_SUCCESS;
595
596 ModuleAddr = 0;
597 ///
598 /// Locate Firmware Volume header
599 ///
600 FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashFirmwareBinariesFvBase);
601
602 ///
603 /// Locate Firmware File System file within Firmware Volume
604 ///
605 Status = PeiServicesFfsFindFileByName (BiosGuardModuleGuidPtr, FvHeader, (VOID **)&FfsFile);
606 if (EFI_ERROR (Status)) {
607 return EFI_NOT_FOUND;
608 }
609 ModuleAddr = (UINT32)((UINT8 *) FfsFile + sizeof (EFI_FFS_FILE_HEADER));
610 DEBUG(( DEBUG_INFO, "BIOS Guard Module Location: %x\n", ModuleAddr));
611 *ModulePtr = (EFI_PHYSICAL_ADDRESS) ModuleAddr;
612
613 return Status;
614 }
615
616 /**
617 Create and initialize BIOS Guard HOB
618
619 @param[in] CpuSecurityPreMemConfig Pointer to a CPU_SECURITY_PREMEM_CONFIG
620
621 @retval EFI_SUCCESS HOB Creating successful.
622 @retval Others HOB Creating failed.
623 **/
624 EFI_STATUS
625 BiosGuardHobInit (
626 IN CONST CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig
627 )
628 {
629 EFI_STATUS Status;
630 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
631 UINTN VariableSize;
632 CPU_SETUP CpuSetupBuffer;
633 CPU_SETUP *CpuSetup;
634 BIOSGUARD_HOB *BiosGuardHobPtr;
635 UINT64 SpiBaseAddress;
636 UINTN PchSpiBase;
637 UINT32 FlashBase = 0;
638 UINT8 BgpdtPkeySlot0[] = { 0x6a, 0x94, 0x81, 0x87, 0xfd, 0x8c, 0x51, 0x0a, 0x2a, 0x74, 0x9c, 0x7b, 0xe3, 0xf7, 0x5c, 0x3a, 0xbf, 0xce, 0x60, 0x4f, 0x68, 0xeb, 0xc6, 0x8f, 0x69, 0x98, 0x8c, 0xc5, 0xdb, 0xe3, 0x29, 0x70 };
639 UINT8 BgpdtPkeySlot1[] = { 0x1c, 0x51, 0x3a, 0xc5, 0x1c, 0x3d, 0x63, 0x10, 0xef, 0xed, 0xfe, 0xc5, 0xf3, 0x4b, 0xf2, 0xe0, 0x9b, 0x22, 0xe8, 0x06, 0xab, 0xd3, 0x19, 0x2e, 0xfa, 0xfb, 0x6e, 0xd9, 0x36, 0x0d, 0x68, 0x18 };
640 UINT8 BgpdtPkeySlot2[] = { 0x19, 0x0b, 0x33, 0xf8, 0xde, 0x3a, 0xa7, 0x9b, 0x57, 0xad, 0xb2, 0x45, 0x86, 0x0e, 0x7f, 0x0e, 0x40, 0x62, 0x80, 0x22, 0x8f, 0x04, 0x92, 0xec, 0x87, 0x44, 0x81, 0xd9, 0xef, 0xed, 0x9f, 0xa3 };
641 UINT8 EcStatus;
642 UINT8 PlatIdStr[] = "ICELAKE";
643
644 //
645 // Make sure ReadOnlyVariablePpi is available
646 //
647 Status = PeiServicesLocatePpi (
648 &gEfiPeiReadOnlyVariable2PpiGuid,
649 0,
650 NULL,
651 (VOID **) &VariableServices
652 );
653 ASSERT_EFI_ERROR (Status);
654
655 VariableSize = sizeof (CPU_SETUP);
656 Status = VariableServices->GetVariable (
657 VariableServices,
658 L"CpuSetup",
659 &gCpuSetupVariableGuid,
660 NULL,
661 &VariableSize,
662 &CpuSetupBuffer
663 );
664 ASSERT_EFI_ERROR (Status);
665 CpuSetup = &CpuSetupBuffer;
666
667 // @todo. Move below code to find flash size to PCH library
668 SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
669 DEFAULT_PCI_SEGMENT_NUMBER_PCH,
670 DEFAULT_PCI_BUS_NUMBER_PCH,
671 PCI_DEVICE_NUMBER_PCH_SPI,
672 PCI_FUNCTION_NUMBER_PCH_SPI,
673 0
674 );
675
676 PchSpiBase = PciSegmentRead32(SpiBaseAddress + R_SPI_CFG_BAR0) & ~B_SPI_CFG_BAR0_MASK;
677 if (PchSpiBase != 0) {
678 FlashBase = (UINT32) LShiftU64 ((*(UINT16*)(UINTN) PchSpiBase), 12);
679 }
680
681 Status = PeiServicesCreateHob(EFI_HOB_TYPE_GUID_EXTENSION, sizeof (BIOSGUARD_HOB), (VOID **)&BiosGuardHobPtr);
682 ASSERT_EFI_ERROR(Status);
683
684 ZeroMem(&(BiosGuardHobPtr->Bgpdt), (sizeof (BIOSGUARD_HOB) - sizeof (EFI_HOB_GUID_TYPE)));
685 BiosGuardHobPtr->EfiHobGuidType.Name = gBiosGuardHobGuid;
686
687 BiosGuardHobPtr->Bgpdt.BgpdtMajVer = BGPDT_MAJOR_VERSION;
688 BiosGuardHobPtr->Bgpdt.BgpdtMinVer = BGPDT_MINOR_VERSION;
689 BiosGuardHobPtr->Bgpdt.BgModSvn = BIOSGUARD_SVN;
690 BiosGuardHobPtr->Bgpdt.BiosSvn = 0x00540000;
691
692 BiosGuardHobPtr->Bgpdt.LastSfam = 4;
693 BiosGuardHobPtr->Bgpdt.SfamData[0].FirstByte = FlashBase + FixedPcdGet32 (PcdFlashFvMain2Offset);
694 BiosGuardHobPtr->Bgpdt.SfamData[0].LastByte = FlashBase + FixedPcdGet32 (PcdFlashFvMain2Offset) + FixedPcdGet32 (PcdFlashFvMain2Size) - 1;
695 BiosGuardHobPtr->Bgpdt.SfamData[1].FirstByte = FlashBase + FixedPcdGet32 (PcdFlashFvMainOffset);
696 BiosGuardHobPtr->Bgpdt.SfamData[1].LastByte = FlashBase + FixedPcdGet32 (PcdFlashFvMainOffset) + FixedPcdGet32 (PcdFlashFvMainSize) - 1;
697 BiosGuardHobPtr->Bgpdt.SfamData[2].FirstByte = FlashBase + FixedPcdGet32 (PcdFlashFvRecovery3Offset);
698 BiosGuardHobPtr->Bgpdt.SfamData[2].LastByte = FlashBase + FixedPcdGet32 (PcdFlashFvRecovery3Offset) + FixedPcdGet32 (PcdFlashFvRecovery3Size) + FixedPcdGet32 (PcdFlashFvFspsSize) - 1;
699 BiosGuardHobPtr->Bgpdt.SfamData[3].FirstByte = FlashBase + FixedPcdGet32 (PcdFlashFvRecovery2Offset);
700 BiosGuardHobPtr->Bgpdt.SfamData[3].LastByte = FlashBase + FixedPcdGet32 (PcdFlashFvRecovery2Offset) + FixedPcdGet32 (PcdFlashFvRecovery2Size) + FixedPcdGet32 (PcdFlashFvFspmtSize) - 1;
701 BiosGuardHobPtr->Bgpdt.SfamData[4].FirstByte = FlashBase + FixedPcdGet32 (PcdFlashFvRecoveryOffset);
702 BiosGuardHobPtr->Bgpdt.SfamData[4].LastByte = FlashBase + FixedPcdGet32 (PcdFlashFvRecoveryOffset) + FixedPcdGet32 (PcdFlashFvRecoverySize) - 1;
703 CopyMem (&BiosGuardHobPtr->Bgpdt.PkeySlot0[0], &BgpdtPkeySlot0[0], sizeof (BgpdtPkeySlot0));
704 CopyMem (&BiosGuardHobPtr->Bgpdt.PkeySlot1[0], &BgpdtPkeySlot1[0], sizeof (BgpdtPkeySlot1));
705 CopyMem (&BiosGuardHobPtr->Bgpdt.PkeySlot2[0], &BgpdtPkeySlot2[0], sizeof (BgpdtPkeySlot2));
706 BiosGuardHobPtr->BiosGuardLog.LastPage = MAX_BIOSGUARD_LOG_PAGE - 1;
707 BiosGuardHobPtr->BiosGuardLog.LoggingOptions = BIOSGUARD_LOG_OPT_DEBUG | BIOSGUARD_LOG_OPT_FLASH_ERROR | BIOSGUARD_LOG_OPT_FLASH_ERASE | BIOSGUARD_LOG_OPT_FLASH_WRITE | BIOSGUARD_LOG_OPT_BRANCH_TRACE | BIOSGUARD_LOG_OPT_STEP_TRACE;
708 BiosGuardHobPtr->BiosGuardLog.Version = BIOSGUARD_LOG_VERSION;
709
710 if (PcdGetBool (PcdEcPresent)) {
711 DEBUG ((DEBUG_INFO, "EC is Present\n"));
712 BiosGuardHobPtr->Bgpdt.BiosGuardAttr |= EnumEcPresent;
713 BiosGuardHobPtr->Bgpdt.EcCmd = EC_C_PORT;
714 BiosGuardHobPtr->Bgpdt.EcData = EC_D_PORT;
715 Status = SendEcCommand(0xB0);
716 if (Status == EFI_SUCCESS) {
717 Status = ReceiveEcData (&EcStatus);
718 if (((EcStatus & 0xF8) == 0) && (EcStatus & BIT0)) {
719 if (((EcStatus & (BIT2 | BIT1)) == (BIT2 | BIT1)) || (((EcStatus & (BIT2 | BIT1)) == 0))) {
720 DEBUG ((DEBUG_INFO, "EC FW supports BiosGuard\n"));
721 BiosGuardHobPtr->Bgpdt.BiosGuardAttr |= EnumEcBiosGuardProtected;
722 BiosGuardHobPtr->Bgpdt.EcCmdGetSvn = 0xB3;
723 BiosGuardHobPtr->Bgpdt.EcCmdOpen = 0xB4;
724 BiosGuardHobPtr->Bgpdt.EcCmdClose = 0xB5;
725 BiosGuardHobPtr->Bgpdt.EcCmdPortTest = 0xB6;
726 BiosGuardHobPtr->BgupHeader.EcSvn = 0x00010000;
727 } else {
728 DEBUG ((DEBUG_ERROR, "EC FW Error\n"));
729 }
730 } else {
731 DEBUG ((DEBUG_WARN, "EC FW do not support BiosGuard\n"));
732 }
733 } else {
734 DEBUG ((DEBUG_ERROR, "SendEcCommand(EcCmdDiscovery) Failed\n"));
735 }
736 }
737 BiosGuardHobPtr->Bgpdt.BiosGuardAttr |= EnumFlashwearoutProtection;
738 BiosGuardHobPtr->Bgpdt.BiosGuardAttr |= EnumFtuEnable;
739
740 Status = UpdateBiosGuardModulePtr(&BiosGuardHobPtr->BiosGuardModulePtr);
741 ASSERT_EFI_ERROR (Status);
742 BiosGuardHobPtr->Bgpdt.BgpdtSize = (sizeof (BGPDT) - sizeof (BiosGuardHobPtr->Bgpdt.SfamData) + ((BiosGuardHobPtr->Bgpdt.LastSfam + 1) * sizeof (SFAM_DATA)));
743 CopyMem (&BiosGuardHobPtr->Bgpdt.PlatId[0], &PlatIdStr[0], sizeof (PlatIdStr));
744
745 BiosGuardHobPtr->BgupHeader.Version = BGUP_HDR_VERSION;
746 CopyMem(&BiosGuardHobPtr->BgupHeader.PlatId[0], &PlatIdStr[0], sizeof (PlatIdStr));
747 BiosGuardHobPtr->BgupHeader.PkgAttributes = 0;
748 BiosGuardHobPtr->BgupHeader.PslMajorVer = PSL_MAJOR_VERSION;
749 BiosGuardHobPtr->BgupHeader.PslMinorVer = PSL_MINOR_VERSION;
750 BiosGuardHobPtr->BgupHeader.BiosSvn = BiosGuardHobPtr->Bgpdt.BiosSvn;
751 BiosGuardHobPtr->BgupHeader.VendorSpecific = 0x808655AA;
752
753 return EFI_SUCCESS;
754 }
755
756 /**
757 Program SpiEiss and LE bit for Variable Write service.
758
759 **/
760 VOID
761 DisableBiosLockForPeiWriteVariable (
762 VOID
763 )
764 {
765 UINT64 SpiBaseAddress;
766
767 SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
768 DEFAULT_PCI_SEGMENT_NUMBER_PCH,
769 DEFAULT_PCI_BUS_NUMBER_PCH,
770 PCI_DEVICE_NUMBER_PCH_SPI,
771 PCI_FUNCTION_NUMBER_PCH_SPI,
772 0
773 );
774
775 PciSegmentAnd8 (SpiBaseAddress + R_SPI_CFG_BC, (UINT8) ~(B_SPI_CFG_BC_EISS | B_SPI_CFG_BC_LE));
776 return;
777 }
778
779 VOID
780 CrashLogCollectDataFromPmcSSRAM (
781 VOID
782 )
783 {
784 EFI_STATUS Status;
785 PMC_IPC_DISCOVERY_BUF DiscoveryBuffer;
786 UINT64 PmcSsramBaseAddress;
787 UINT32 PmcSsramBar0;
788 UINT32 CrashLogAddr;
789 EFI_PHYSICAL_ADDRESS AllocateAddress;
790 UINT32 *Destination = NULL;
791 UINT32 PmcLogSize;
792 UINT32 PunitLogSize;
793 UINT32 CpuLogSize;
794 UINT32 CrashLogSize = 0;
795 UINT32 CopiedSize = 0;
796
797 DEBUG ((DEBUG_INFO, "CrashLogCollectDataFromPmcSSRAM - start\n"));
798
799 //
800 // Check for the availability of CrashLog feature
801 //
802 ZeroMem (&DiscoveryBuffer, sizeof (PMC_IPC_DISCOVERY_BUF));
803
804 Status = PmcCrashLogDiscovery (&DiscoveryBuffer);
805
806 if (EFI_ERROR (Status) || (DiscoveryBuffer.Bits.Avail != 1) || (DiscoveryBuffer.Bits.Dis == 1)) {
807 DEBUG ((DEBUG_INFO, "PCH CrashLog feature is not supported\n"));
808 return;
809 }
810
811 //
812 // Start to access PMC SSARM MMIO
813 //
814 PmcSsramBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
815 DEFAULT_PCI_SEGMENT_NUMBER_PCH,
816 DEFAULT_PCI_BUS_NUMBER_PCH,
817 PCI_DEVICE_NUMBER_PCH_PMC_SSRAM,
818 PCI_FUNCTION_NUMBER_PCH_PMC_SSRAM,
819 0
820 );
821
822 if (PciSegmentRead16 (PmcSsramBaseAddress + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
823 DEBUG ((DEBUG_ERROR, "PMC SSRAM PCI device is disabled\n"));
824 return;
825 }
826
827 //
828 // Program BAR 0 and enable command register memory space decoding
829 //
830 PmcSsramBar0 = PcdGet32 (PcdSiliconInitTempMemBaseAddr);
831 PciSegmentWrite32 (PmcSsramBaseAddress + PCI_BASE_ADDRESSREG_OFFSET, PmcSsramBar0);
832 PciSegmentOr16 (PmcSsramBaseAddress + PCI_COMMAND_OFFSET, (UINT16) (EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER));
833
834 //
835 // Check for the presence of CrashLog data
836 //
837 CrashLogAddr = PmcSsramBar0 + DiscoveryBuffer.Bits.BaseOffset;
838 DEBUG ((DEBUG_INFO, "Value at CrashLogAddress 0x%x = 0x%x \n ", CrashLogAddr, MmioRead32 (CrashLogAddr)));
839 DEBUG ((DEBUG_INFO, "Value at CrashLogAddress 0x%x = 0x%x \n ", CrashLogAddr + 4, MmioRead32 (CrashLogAddr + 4)));
840
841 if ((MmioRead32 (CrashLogAddr) != 0) && ((MmioRead32 (CrashLogAddr + 4) & 0x0F) != 0)) {
842 DEBUG ((DEBUG_INFO, "Pmc CrashLog is present\n"));
843 } else {
844 DEBUG ((DEBUG_INFO, "Pmc CrashLog is not present\n"));
845 goto Exit;
846 }
847
848 //
849 // Allocate memory buffer for CrashLog data
850 //
851 PmcSsramGetCrashLogSize (&PmcLogSize, &PunitLogSize, &CpuLogSize);
852 CrashLogSize = PmcLogSize + PunitLogSize + CpuLogSize;
853
854 Status = PeiServicesAllocatePages (
855 EfiBootServicesData,
856 EFI_SIZE_TO_PAGES (CrashLogSize),
857 &AllocateAddress
858 );
859
860 if (EFI_ERROR (Status)) {
861 DEBUG ((DEBUG_ERROR, "Memory out of resource\n"));
862 goto Exit;
863 }
864
865 //
866 // Set PCD to pass this memory buffer to CrashLogDxe driver
867 //
868 PcdSet64S (PcdCrashLogDataBuffer, (UINT64) AllocateAddress);
869 DEBUG ((DEBUG_INFO, "PcdCrashLogDataBuffer = 0x%x\n", AllocateAddress));
870
871 ZeroMem ((VOID *) (UINTN) AllocateAddress, EFI_SIZE_TO_PAGES (CrashLogSize) * EFI_PAGE_SIZE);
872
873 //
874 // Copy CrashLog data from SSRAM to allocated memory buffer
875 //
876 Destination = (UINT32 *)(UINTN) AllocateAddress;
877 CopiedSize = 0;
878 while (CopiedSize < CrashLogSize) {
879 *Destination = MmioRead32 (CrashLogAddr); // Byte access is not allowed to PMC SSRAM, hence copying DW by DW
880 Destination++;
881 CrashLogAddr += 4;
882 CopiedSize += 4;
883 }
884
885 //
886 // Clear the SSRAM region after copying the error log
887 //
888 Status = PmcCrashLogClear ();
889 DEBUG ((DEBUG_INFO, " Clear CrashLog Status = %r\n", Status));
890
891 Exit:
892 //
893 // Disable PMC SSRAM MMIO
894 //
895 PciSegmentAnd16 (PmcSsramBaseAddress + PCI_COMMAND_OFFSET, (UINT16) ~(EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE));
896 PciSegmentWrite32 (PmcSsramBaseAddress + PCI_BASE_ADDRESSREG_OFFSET, 0);
897 DEBUG ((DEBUG_INFO, "CrashLogCollectDataFromPmcSSRAM - end\n"));
898
899 return;
900 }
901 /**
902 Platform Init PEI module entry point
903
904 @param[in] FileHandle Not used.
905 @param[in] PeiServices General purpose services available to every PEIM.
906
907 @retval EFI_SUCCESS The function completes successfully
908 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
909 **/
910 EFI_STATUS
911 EFIAPI
912 PlatformInitEntryPoint (
913 IN EFI_PEI_FILE_HANDLE FileHandle,
914 IN CONST EFI_PEI_SERVICES **PeiServices
915 )
916 {
917 EFI_STATUS Status;
918 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
919 SETUP_DATA SystemConfiguration;
920 UINTN VariableSize;
921 UINT8 FwConfig;
922 SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
923 CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
924 PEI_BOARD_CONFIG_PCD_INIT BoardConfigPcdInit;
925
926 PostCode(PLATFORM_INIT_POSTMEM_ENTRY);
927 Status = PeiServicesLocatePpi (
928 &gSiPreMemPolicyPpiGuid,
929 0,
930 NULL,
931 (VOID **) &SiPreMemPolicyPpi
932 );
933 ASSERT_EFI_ERROR (Status);
934
935 Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
936 ASSERT_EFI_ERROR (Status);
937
938 //
939 // Init Board Config Pcd.
940 //
941 BoardConfigPcdInit = (PEI_BOARD_CONFIG_PCD_INIT) (UINTN) PcdGet64 (PcdFuncBoardConfigInit);
942 ASSERT (BoardConfigPcdInit != NULL);
943
944 if (BoardConfigPcdInit != NULL) {
945 Status = BoardConfigPcdInit (NULL);
946 ASSERT_EFI_ERROR (Status);
947 }
948
949 ///
950 /// Configure GPIO and SIO
951 ///
952 Status = BoardInit ();
953 ASSERT_EFI_ERROR (Status);
954
955 if (PcdGetBool (PcdPeiWriteVariableEnable)) {
956 DisableBiosLockForPeiWriteVariable ();
957 }
958
959 Status = PeiReadWriteVariableInit ();
960
961 Status = PeiServicesLocatePpi (
962 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
963 0, // INSTANCE
964 NULL, // EFI_PEI_PPI_DESCRIPTOR
965 (VOID **) &VariableServices // PPI
966 );
967 ASSERT_EFI_ERROR (Status);
968
969 VariableSize = sizeof (SETUP_DATA);
970 Status = VariableServices->GetVariable (
971 VariableServices,
972 PLATFORM_SETUP_VARIABLE_NAME,
973 &gSetupVariableGuid,
974 NULL,
975 &VariableSize,
976 &SystemConfiguration
977 );
978 if (EFI_ERROR (Status)) {
979 DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
980 FwConfig = 0;
981 } else {
982 FwConfig = SystemConfiguration.FirmwareConfiguration;
983 }
984
985 if (CpuSecurityPreMemConfig->BiosGuard == TRUE) {
986 Status = BiosGuardHobInit(CpuSecurityPreMemConfig);
987 ASSERT_EFI_ERROR (Status);
988 }
989
990 //
991 // BIOS shall extract Crash records from PMC SSRAM after memory init
992 // and before enabling the Energy Reporting feature
993 //
994 CrashLogCollectDataFromPmcSSRAM ();
995
996 PeiPolicyInit (PeiServices, FwConfig);
997
998 //
999 // Create USB Boot First hotkey information HOB
1000 //
1001 CreateAttemptUsbFirstHotkeyInfoHob ();
1002
1003 //
1004 // Initializing Platform Specific Programming
1005 //
1006 Status = PlatformSpecificInit();
1007 ASSERT_EFI_ERROR (Status);
1008
1009 //
1010 // Performing PlatformInitEndOfPei after EndOfPei PPI produced
1011 //
1012 Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList);
1013
1014 PostCode(PLATFORM_INIT_POSTMEM_EXIT);
1015
1016 return Status;
1017 }
EcTcssLib.h
EC TCSS library functions.
IOMReadyNotifyToEC
EFI_STATUS IOMReadyNotifyToEC(VOID)
This function sends IOM Ready Notify message to EC.
Definition: PlatformInit.c:395
SystemNvDataGuid.h
BoardConfigLib.h
Function prototype of BoardConfigLib.
UsbcIomReadyNotify
EFI_STATUS UsbcIomReadyNotify(IN OUT UINT8 *DataBuffer)
USBC IOM Ready Notify.
PeiReadWriteVariableInit
EFI_STATUS PeiReadWriteVariableInit(VOID)
Initialize PEI read write Variable PPI.
BiosGuardHobInit
EFI_STATUS BiosGuardHobInit(IN CONST CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig)
Create and initialize BIOS Guard HOB.
Definition: PlatformInit.c:625
ReceiveEcData
EFI_STATUS ReceiveEcData(OUT UINT8 *Data)
Receives data from Keyboard System Controller.
PeiPolicyInitLib.h
Header file for the PolicyInitPei Library.
UpdateBiosGuardModulePtr
EFI_STATUS UpdateBiosGuardModulePtr(IN OUT EFI_PHYSICAL_ADDRESS *ModulePtr)
Get the BIOS Guard Module pointer.
Definition: PlatformInit.c:582
EFI_I2C_REQUEST_PACKET
I2C device operation.
Definition: I2cMaster.h:360
PeiReadWriteVariableLib.h
SetCacheMtrrAfterEndOfPei
EFI_STATUS SetCacheMtrrAfterEndOfPei(VOID)
Update MTRR setting and set write back as default memory attribute.
Definition: PlatformInit.c:107
PlatformInitEntryPoint
EFI_STATUS PlatformInitEntryPoint(IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init PEI module entry point.
Definition: PlatformInit.c:912
PlatformBoardId.h
Defines Platform BoardIds.
CreateAttemptUsbFirstHotkeyInfoHob
EFI_STATUS CreateAttemptUsbFirstHotkeyInfoHob(VOID)
Create the HOB for hotkey status for 'Attempt USB First' feature.
Definition: PlatformInit.c:542
DisableBiosLockForPeiWriteVariable
VOID DisableBiosLockForPeiWriteVariable(VOID)
Program SpiEiss and LE bit for Variable Write service.
Definition: PlatformInit.c:761
SendEcCommand
EFI_STATUS SendEcCommand(IN UINT8 Command)
Send a command to the Keyboard System Controller.
PeiPolicyInit
VOID PeiPolicyInit(IN CONST EFI_PEI_SERVICES **PeiServices, IN UINT8 FirmwareConfiguration)
Initialize Intel PEI Platform Policy.
EcLib.h
EC library functions and definitions.
PlatformInitEndOfPei
EFI_STATUS PlatformInitEndOfPei(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task at the end of PEI.
Definition: PlatformInit.c:503
PlatformPostCode.h
AttemptUsbFirst.h
ResetSarSensorSklSds
EFI_STATUS ResetSarSensorSklSds(VOID)
Reset the SAR Sensor to ensure the SAR sensor can trigger an edge to the WWAN module on SKL SDS for F...
Definition: PlatformInit.c:282
SetupVariable.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformInitDxe.c Source File

  • PlatformInit
  • PlatformInitDxe
PlatformInitDxe.c
Go to the documentation of this file.
1 /** @file
2 Source code file for the Platform Init DXE module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "PlatformInitDxe.h"
35 #include <CpuRegs.h>
36 #include <Guid/EventGroup.h>
37 #include <Library/BootGuardLib.h>
38 #include <Protocol/CpuInfo.h>
39 #include <Protocol/PlatformNvsArea.h>
40 #include <Protocol/VariableLock.h>
41 #include <Protocol/S3SaveState.h>
42 #include <SoftwareGuardSetupData.h>
43 #include <MeBiosPayloadHob.h>
44 #include <Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h>
45 #include <Library/CpuPlatformLib.h>
46 #include <Library/GpioLib.h>
47 #include <Library/PchPcrLib.h>
48 #include <Board/Include/BoardHook.h>
49 #include <Library/SmbiosProcessorLib.h>
50 #include <Protocol/PchReset.h>
51 #include <Guid/TpmInstance.h>
52 #include <Library/Tpm2CommandLib.h>
53 #include <Library/DxeSmbiosFirmwareVersionInfoLib.h>
54 #include <Library/PostCodeLib.h>
55 #include <PlatformPostCode.h>
56 #include <Private/CpuInitDataHob.h>
57
58 GLOBAL_REMOVE_IF_UNREFERENCED EFI_EVENT EndOfDxeEvent;
59 GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL mPlatformNvsAreaProtocol;
60
61 ///
62 /// SGX EPC definitions
63 ///
64 #define EPC_FRACTION_NUMERATOR 381
65 #define EPC_FRACTION_DENOMINATOR 512
66 #define EPC_SUBTRACT_MB SIZE_2MB
67 #define PRM_BOTTOM_LIMIT 4
68
69 EFI_STATUS
70 EFIAPI
71 PlatformPchResetCallback (
72 IN EFI_RESET_TYPE ResetType,
73 IN EFI_GUID *ResetTypeGuid
74 );
75
76 GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_CALLBACK_PROTOCOL mPchResetCallbackProtocol = { PlatformPchResetCallback };
77
78 /**
79 This function handles PlatformInit task at the end of DXE
80
81 @param[in] Event The Event this notify function registered to.
82 @param[in] Context Pointer to the context data registered to the
83 Event.
84 **/
85 VOID
86 EFIAPI
87 EndofDxeCallback (
88 IN EFI_EVENT Event,
89 IN VOID *Context
90 )
91 {
92 static BOOLEAN S3DataSaved = FALSE;
93 UINT16 ABase;
94 UINT32 SmiEn;
95 UINT16 Pm1Sts;
96
97 gBS->CloseEvent (Event);
98
99 //
100 // @todo: It should be moved to other place.
101 //
102 CheckLidBaseEcProtocolVersion ();
103
104 if (S3DataSaved) {
105 return ;
106 }
107
108 ABase = PmcGetAcpiBase ();
109 SmiEn = IoRead32 (ABase + R_ACPI_IO_SMI_EN);
110 //
111 // Disabled Legacy USB Logic that generates SMI, during S3 Resume.
112 //
113 SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB | B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_PERIODIC | B_ACPI_IO_SMI_EN_SWSMI_TMR);
114
115 S3BootScriptSaveIoWrite (
116 S3BootScriptWidthUint32,
117 (UINTN) (ABase + R_ACPI_IO_SMI_EN),
118 1,
119 &SmiEn
120 );
121 //
122 // Clear bust master status bit on S3 resume
123 //
124 Pm1Sts = B_ACPI_IO_PM1_STS_BM;
125
126 S3BootScriptSaveIoWrite (
127 S3BootScriptWidthUint16,
128 (UINTN) (ABase + R_ACPI_IO_PM1_STS),
129 1,
130 &Pm1Sts
131 );
132
133 S3DataSaved = TRUE;
134
135
136 ///
137 /// Verify if Boot Guard is supported
138 ///
139 if (IsBootGuardSupported()){
140 ///
141 /// Identify if Revocation is requested by Boot Guard ACM
142 ///
143 if (AsmReadMsr64 (MSR_BOOT_GUARD_SACM_INFO) & BIT7) {
144 BootGuardOemRevocationHook();
145 }
146 }
147
148 }
149
150 /**
151 Registers callback for.PlatformInitEndOfDxe
152
153 **/
154 VOID
155 RegisterEndOfDxeCallbacks(
156 VOID
157 )
158 {
159 EFI_STATUS Status;
160
161 ///
162 /// Performing PlatformInitEndOfDxe after the gEfiEndOfDxeEventGroup is signaled.
163 ///
164 Status = gBS->CreateEventEx (
165 EVT_NOTIFY_SIGNAL,
166 TPL_CALLBACK,
167 EndofDxeCallback,
168 NULL,
169 &gEfiEndOfDxeEventGroupGuid,
170 &EndOfDxeEvent
171 );
172 ASSERT_EFI_ERROR (Status);
173
174 }
175
176 /**
177 This function handles PlatformInitDxe task at the ready to boot
178
179 @param[in] Event The Event this notify function registered to.
180 @param[in] Context Pointer to the context data registered to the
181 Event.
182 **/
183 VOID
184 EFIAPI
185 PlatformDxeReadyToBootCallback (
186 IN EFI_EVENT Event,
187 IN VOID *Context
188 )
189 {
190 gBS->CloseEvent (Event);
191
192 return;
193 }
194
195 /**
196 Registers callback for PlatformDxeReadyToBoot
197
198 **/
199 VOID
200 RegisterReadyToBootCallback (
201 VOID
202 )
203 {
204 EFI_STATUS Status;
205 EFI_EVENT Event;
206
207 Status = EfiCreateEventReadyToBootEx (
208 TPL_CALLBACK,
209 PlatformDxeReadyToBootCallback,
210 NULL,
211 &Event
212 );
213
214 ASSERT_EFI_ERROR (Status);
215 }
216
217 /**
218 Call back function for Pch Reset.
219
220 @param[in] ResetType Reset Types which includes GlobalReset.
221 @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the Reset Type Guid.
222
223 @retval EFI_SUCCESS The function completed successfully
224 @retval Others All other error conditions encountered result in an ASSERT.
225 **/
226 EFI_STATUS
227 EFIAPI
228 PlatformPchResetCallback (
229 IN EFI_RESET_TYPE ResetType,
230 IN EFI_GUID *ResetTypeGuid
231 )
232 {
233 EFI_STATUS Status;
234
235 DEBUG ((DEBUG_INFO, "PlatformPchResetCallback\n"));
236
237 Status = Tpm2Shutdown (TPM_SU_CLEAR);
238 if (EFI_ERROR (Status)) {
239 DEBUG ((DEBUG_ERROR, "Tpm2Shutdown (TPM_SU_CLEAR) failed: %r\n", Status));
240 }
241
242 return EFI_SUCCESS;
243 }
244
245 /**
246 Creates a UEFI variable for OS with all data regarding SGX EPC
247
248 @retval EPC_BIOS_CONFIG Pointer to BIOS EPC variable structure
249 **/
250 EPC_BIOS_CONFIG *
251 CreateSgxInfoForOs (
252 VOID
253 )
254 {
255 UINT64 SupportedPrmBins;
256 UINT64 PrmSize;
257 UINT64 MaxPrmSize;
258 UINT8 Index;
259 UINT8 BinVal;
260 UINT64 C6DramSub;
261 EFI_CPUID_REGISTER Cpuid;
262 EPC_BIOS_CONFIG *EpcBios;
263 VOID *Hob;
264 CPU_INIT_DATA_HOB *CpuInitDataHob;
265 CPU_CONFIG_DATA *CpuConfigData;
266
267 EpcBios = (EPC_BIOS_CONFIG*) AllocateRuntimePool (sizeof (EPC_BIOS_CONFIG));
268 C6DramSub = 0;
269
270 if (EpcBios == NULL) {
271 DEBUG ((DEBUG_ERROR, "CreateSgxInfoForOs: Memory allocation for EPC structure failed"));
272 return NULL;
273 }
274
275 ///
276 /// Presence of SGX feature is detectable by reading CPUID.(EAX=0x12, ECX=0):EAX[0]
277 ///
278 AsmCpuidEx (CPUID_SGX_ENABLED, 0, &Cpuid.RegEax, 0, 0, 0);
279
280 ///
281 /// If SGX was not activated
282 ///
283 if (Cpuid.RegEax == 0) {
284 DEBUG ((DEBUG_INFO, "CreateSgxInfoForOs: SGX feature is not present, setting AllocatedEpcSize = 0\n"));
285 EpcBios->AllocatedEpcSize = 0;
286 } else {
287
288 //
289 // Read CPUID(12,0x2) to get EPC Base and size
290 //
291 AsmCpuidEx (CPUID_SGX_ENABLED, 0x2, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
292
293 //
294 // Check if the first sub-leaf is a valid EPC section
295 //
296 if ((Cpuid.RegEax & 0xF) != 0x1) {
297 EpcBios->AllocatedEpcSize = 0;
298 } else {
299
300 ///
301 /// If SGX was enabled, this variable will hold the EPC length as it was read from CPUID SGX sub-leaf
302 /// Else this variable will hold the value 0
303 ///
304 EpcBios->AllocatedEpcSize = (UINT32) (UINTN) (LShiftU64 ((UINT64) (Cpuid.RegEdx & 0xFFFFF), 32) + (UINT64) (Cpuid.RegEcx & 0xFFFFF000));
305 }
306 }
307
308 ///
309 /// Get CPU Init Data Hob
310 ///
311 Hob = GetFirstGuidHob (&gCpuInitDataHobGuid);
312 if (Hob == NULL) {
313 DEBUG ((DEBUG_ERROR, "CPU Data HOB not available\n"));
314 ASSERT(Hob == NULL);
315 }
316 CpuInitDataHob = (CPU_INIT_DATA_HOB *) ((UINTN) Hob + sizeof (EFI_HOB_GUID_TYPE));
317 CpuConfigData = (CPU_CONFIG_DATA *)(UINTN)CpuInitDataHob->CpuConfigData;
318
319 ///
320 /// If C6DRAM is supported, then PRMRR size of 1MB will be supported. Reduce 0.5 MB from reported EPC size
321 ///
322 SupportedPrmBins = AsmReadMsr64 (MSR_PRMRR_VALID_CONFIG);
323
324 if (((SupportedPrmBins & BIT0) != 0) && CpuConfigData->EnableC6Dram && (IsC6dramSupported (CpuConfigData->EnableC6Dram))) {
325 C6DramSub = SIZE_512KB;
326 }
327
328 EpcBios->SupportedPrmBins = (UINT32) (UINTN) SupportedPrmBins;
329 DEBUG ((DEBUG_INFO, "CreateSgxInfoForOs: SupportedPrmBins = 0x%ll016X\n", SupportedPrmBins));
330
331 MaxPrmSize = 0;
332 ///
333 /// Traverse over all SupportedPrmBins, skip the ones, that are lower or equal to 2 MB
334 ///
335 for (Index = 0, PrmSize = 1; Index < sizeof(EpcBios->EpcMap) / sizeof(EpcBios->EpcMap[0]); Index++) {
336
337 EpcBios->EpcMap[Index] = 0;
338
339 ///
340 /// No More supported PRM size
341 ///
342 if (SupportedPrmBins == 0) {
343 continue;
344 }
345 BinVal = SupportedPrmBins & BIT0;
346 if (Index != 0) {
347
348 ///
349 /// Current PRM size in MB
350 ///
351 PrmSize = LShiftU64(PrmSize,1);
352 }
353 SupportedPrmBins = RShiftU64(SupportedPrmBins, 1);
354
355 ///
356 /// Don't include PRM sizes that are lower than 4MB
357 ///
358 if (BinVal == 0 || PrmSize < PRM_BOTTOM_LIMIT) {
359 continue;
360 } else {
361
362 ///
363 /// Calculate the supported EPC size: PRM_SIZE * (191/256) - 2MB - (0.5MB, if C6 DRAM is supported)
364 ///
365 DEBUG ((DEBUG_INFO, "CreateSgxInfoForOs: Supported PRM size = %d MB\n", PrmSize));
366 EpcBios->EpcMap[Index] = (UINT32)(DivU64x32(MultU64x32(PrmSize * SIZE_1MB, EPC_FRACTION_NUMERATOR), EPC_FRACTION_DENOMINATOR) - EPC_SUBTRACT_MB - C6DramSub);
367 DEBUG ((DEBUG_INFO, "CreateSgxInfoForOs: EpcBios->EpcMap[%d] = 0x%ll016X MB\n", Index, EpcBios->EpcMap[Index]));
368 EpcBios->MaxEpcSize = EpcBios->EpcMap[Index];
369 MaxPrmSize = PrmSize;
370 }
371 }
372
373 DEBUG ((DEBUG_INFO, "CreateSgxInfoForOs: Final MaxEpcSize = 0x%ll016X MB\n", EpcBios->MaxEpcSize));
374 DEBUG ((DEBUG_INFO, "CreateSgxInfoForOs end\n"));
375
376 return EpcBios;
377 }
378
379 /**
380 Update BIOS and OS EPC UEFI variables
381 **/
382 VOID
383 UpdateEpcVariables (
384 VOID
385 )
386 {
387 EFI_STATUS Status;
388 EFI_STATUS EpcBiosStatus;
389 EFI_STATUS EpcOsStatus;
390 UINTN EpcBiosConfigurationSize;
391 EPC_BIOS_CONFIG EpcBiosConfiguration;
392 UINTN EpcOsConfigurationSize;
393 EPC_OS_CONFIG EpcOsConfiguration;
394 CPU_INFO_PROTOCOL *CpuInfo;
395 EPC_BIOS_CONFIG *EpcBios;
396 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock;
397 UINTN VariableSize;
398 UINT32 VariableAttr;
399 CPU_SETUP CpuSetup;
400
401 VariableSize = sizeof (CPU_SETUP);
402 Status = gRT->GetVariable (
403 L"CpuSetup",
404 &gCpuSetupVariableGuid,
405 &VariableAttr,
406 &VariableSize,
407 &CpuSetup
408 );
409 ASSERT_EFI_ERROR (Status);
410
411 ///
412 /// Reading EPC_BIOS UEFI variable
413 ///
414 EpcBiosConfigurationSize = sizeof (EPC_BIOS_CONFIG);
415 EpcBiosStatus = gRT->GetVariable (
416 EPC_BIOS,
417 &gEpcBiosDataGuid,
418 NULL,
419 &EpcBiosConfigurationSize,
420 &EpcBiosConfiguration
421 );
422 ///
423 /// Reading EPC_OS_CTRL UEFI variable
424 ///
425 EpcOsConfigurationSize = sizeof (EPC_OS_CONFIG);
426 EpcOsStatus = gRT->GetVariable (
427 EPC_OS_CTRL,
428 &gEpcOsDataGuid,
429 NULL,
430 &EpcOsConfigurationSize,
431 &EpcOsConfiguration
432 );
433
434 if (!EFI_ERROR(EpcBiosStatus)) {
435 DEBUG ((DEBUG_INFO, "Old MaxEpcSize from GetVariable = 0x%X\n", EpcBiosConfiguration.MaxEpcSize));
436 DEBUG ((DEBUG_INFO, "Old SupportedPrmBins from GetVariable = 0x%X\n", EpcBiosConfiguration.SupportedPrmBins));
437 DEBUG ((DEBUG_INFO, "Old EpcSize from GetVariable = 0x%X\n", EpcBiosConfiguration.AllocatedEpcSize));
438 }
439
440 if (!EFI_ERROR(EpcOsStatus)) {
441 DEBUG ((DEBUG_INFO, "Old RequestedEpcSize from GetVariable = 0x%X\n", EpcOsConfiguration.RequestedEpcSize));
442 }
443
444 ///
445 /// If SGX is not in 'Software Control' mode, delete EPC_BIOS (if found) & delete EPC_OS_CTRL variable (if found).
446 ///
447 if (CpuSetup.EnableSgx != SGX_SOFTWARE_CONTROL) {
448
449 if (EpcBiosStatus != EFI_NOT_FOUND) {
450 ///
451 /// SGX is not in 'Software Control' mode and EPC_BIOS variable is found. Hence, deleting EPC_BIOS variable.
452 ///
453 DEBUG ((DEBUG_INFO, "SGX is not in 'Software Control' mode and EPC_BIOS variable is found, deleting EPC_BIOS variable \n"));
454 ZeroMem (&EpcBiosConfiguration, EpcBiosConfigurationSize);
455
456 Status = gRT->SetVariable (
457 EPC_BIOS,
458 &gEpcBiosDataGuid,
459 0,
460 0,
461 NULL
462 );
463 }
464
465 if (EpcOsStatus != EFI_NOT_FOUND) {
466 ///
467 /// SGX is not in 'Software Control' mode and EPC_OS_CTRL variable is found. Hence, deleting EPC_OS_CTRL variable.
468 ///
469 DEBUG ((DEBUG_INFO, "SGX is not in 'Software Control' mode and EPC_OS_CTRL variable is found, deleting EPC_OS_CTRL variable \n"));
470 ZeroMem (&EpcOsConfiguration, EpcOsConfigurationSize);
471
472 Status = gRT->SetVariable (
473 EPC_OS_CTRL,
474 &gEpcOsDataGuid,
475 0,
476 0,
477 NULL
478 );
479 }
480 return;
481 }
482
483 ///
484 /// Get the CPU platform setup policy.
485 ///
486 Status = gBS->LocateProtocol (&gCpuInfoProtocolGuid, NULL, (VOID **) &CpuInfo);
487 if (EFI_ERROR (Status)) {
488 DEBUG ((DEBUG_ERROR, "Located CpuInfo Protocol Status = %r\n", Status));
489 return;
490 }
491 EpcBios = CreateSgxInfoForOs ();
492
493 ///
494 /// If BIOS EPC UEFI variable initialization fails
495 ///
496 if (EpcBios == NULL) {
497 return;
498 }
499
500 DEBUG ((DEBUG_INFO, "Saving UEFI variable EPC_BIOS\n"));
501 DEBUG ((DEBUG_INFO, "New MaxEpcSize from HOB = 0x%X\n", EpcBios->MaxEpcSize));
502 DEBUG ((DEBUG_INFO, "New SupportedPrmBins from HOB = 0x%X\n", EpcBios->SupportedPrmBins));
503 DEBUG ((DEBUG_INFO, "New AllocatedEpcSize from HOB = 0x%X\n", EpcBios->AllocatedEpcSize));
504
505 ///
506 /// SGX is in 'Software Control' mode, need to update EPC_BIOS variable
507 ///
508 DEBUG ((DEBUG_INFO, "SGX is in 'Software Control' mode, updating EPC_BIOS variable \n"));
509 Status = gRT->SetVariable (
510 EPC_BIOS,
511 &gEpcBiosDataGuid,
512 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
513 sizeof (EPC_BIOS_CONFIG),
514 EpcBios
515 );
516 ASSERT_EFI_ERROR(Status);
517
518 ///
519 /// Locking EPC_BIOS variable, setting it to be read only
520 ///
521 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
522 if (!EFI_ERROR (Status)) {
523 Status = VariableLock->RequestToLock (VariableLock, EPC_BIOS, &gEpcBiosDataGuid);
524 if (EFI_ERROR (Status)) {
525 DEBUG ((DEBUG_INFO, "BIOS was unable to lock EpcBios Variable\n"));
526 }
527 }
528
529 ///
530 /// If SGX was enabled and SGX setup option is set to auto
531 ///
532 if ((EpcBios->AllocatedEpcSize != 0) && (CpuSetup.EnableSgx == SGX_SOFTWARE_CONTROL)) {
533
534 ///
535 /// Updating PRMRR size setup option, to be compatible with current PRMRR size
536 ///
537 CpuSetup.PrmrrSize = SIZE_32MB;
538 if (EpcBios->AllocatedEpcSize > SIZE_32MB) {
539 CpuSetup.PrmrrSize = SIZE_64MB;
540 }
541 if (EpcBios->AllocatedEpcSize > SIZE_64MB) {
542 CpuSetup.PrmrrSize = SIZE_128MB;
543 }
544 if (EpcBios->AllocatedEpcSize > SIZE_128MB) {
545 CpuSetup.PrmrrSize = SIZE_256MB;
546 }
547 DEBUG ((DEBUG_INFO, "PRMRR size in setup options was changed to 0x%ll016X \n", CpuSetup.PrmrrSize));
548 }
549
550 Status = gRT->SetVariable (
551 L"CpuSetup",
552 &gCpuSetupVariableGuid,
553 VariableAttr,
554 sizeof (CPU_SETUP),
555 &CpuSetup
556 );
557 ASSERT_EFI_ERROR(Status);
558 }
559
560 VOID
561 UpdateSgxSvnVariable(
562 VOID
563 )
564 {
565 EFI_STATUS Status;
566 CPU_INFO_PROTOCOL *CpuInfo;
567 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock;
568 UINT64 MaskValue;
569 UINT64 Svn;
570 MaskValue = BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16;
571 ///
572 /// Locate CPU Info Protocol.
573 ///
574 Status = gBS->LocateProtocol (&gCpuInfoProtocolGuid, NULL, (VOID **) &CpuInfo);
575 if (EFI_ERROR (Status)) {
576 DEBUG ((DEBUG_ERROR, "Located CpuInfo Protocol Status = %r\n", Status));
577 return;
578 }
579
580 Svn = CpuInfo->SgxInfo->SgxSinitNvsData;
581 Svn &= MaskValue;
582 Svn >>= 16;
583 DEBUG ((DEBUG_INFO, "SINIT SE SVN:: Read the SgxSinitNvsData value = 0x%X \n", CpuInfo->SgxInfo->SgxSinitNvsData));
584 DEBUG ((DEBUG_INFO, "SINIT SE SVN:: Programming NV Variable with the Svn value = 0x%X \n", Svn));
585 Status = gRT->SetVariable (
586 SINIT_SVN_VARIABLE_NAME,
587 &gSinitSvnGuid,
588 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
589 sizeof (SINIT_SVN),
590 &Svn
591 );
592
593 ASSERT_EFI_ERROR(Status);
594
595 ///
596 /// Locking SINIT_SVN_VARIABLE_NAME variable, setting it to be read only
597 ///
598 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
599 if (!EFI_ERROR (Status)) {
600 Status = VariableLock->RequestToLock (VariableLock, SINIT_SVN_VARIABLE_NAME, &gSinitSvnGuid);
601 if (EFI_ERROR (Status)) {
602 DEBUG ((DEBUG_INFO, "BIOS was unable to lock SinitSvn Variable\n"));
603 }
604 }
605 }
606
607 /**
608 Creates a UEFI variable for reporting platform SGX status information
609 **/
610 VOID
611 UpdateSgxPolicyStatusVariable (
612 VOID
613 )
614 {
615 EFI_STATUS Status;
616 EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock;
617 UINTN VariableSize;
618 UINT32 VariableAttr;
619 CPU_SETUP CpuSetup;
620 SOFTWARE_GUARD_STATUS SgxPolicyStatus;
621
622 VariableSize = sizeof (CPU_SETUP);
623 Status = gRT->GetVariable (
624 L"CpuSetup",
625 &gCpuSetupVariableGuid,
626 &VariableAttr,
627 &VariableSize,
628 &CpuSetup
629 );
630 ASSERT_EFI_ERROR (Status);
631
632 ///
633 /// Update SGX Status variables
634 /// Initialize variables if CPU Setup data not found
635 ///
636 if (EFI_ERROR(Status)){
637 DEBUG ((DEBUG_ERROR, "CPU Setup data was not found. Initalizing SGX variables.\n"));
638 SgxPolicyStatus.SgxStatus = 0;
639 } else {
640 SgxPolicyStatus.SgxStatus = CpuSetup.EnableSgx;
641 }
642
643 ///
644 /// Set SGX Status UEFI variable with updated values
645 ///
646 Status = gRT->SetVariable (
647 SGX_POLICY,
648 &gSgxPolicyStatusGuid,
649 EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
650 sizeof (SOFTWARE_GUARD_STATUS),
651 &SgxPolicyStatus
652 );
653 ASSERT_EFI_ERROR (Status);
654
655 ///
656 /// Locking SOFTWARE_GUARD_STATUS variable, setting it to be read only
657 ///
658 Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
659 if (!EFI_ERROR (Status)) {
660 Status = VariableLock->RequestToLock (VariableLock, SGX_POLICY, &gSgxPolicyStatusGuid);
661 if (EFI_ERROR (Status)) {
662 DEBUG ((DEBUG_INFO, "BIOS was unable to lock SgxPolicyStatus variable.\n"));
663 } else {
664 DEBUG ((DEBUG_INFO, "BIOS locked SgxPolicyStatus variable.\n"));
665 }
666 }
667 ASSERT_EFI_ERROR (Status);
668 }
669
670 /**
671 Updates Platform information to the setup data
672
673 **/
674 VOID
675 UpdatePlatformInfo(
676 VOID
677 )
678 {
679 EFI_STATUS Status;
680 SETUP_VOLATILE_DATA SetupVolatileData;
681 UINT32 SetupVolAttributes;
682 UINTN VariableSize;
683 UINT64 HbPciD0F0RegBase;
684 BOARD_HOOK_PLATFORM_SETUP_OVERRIDE BoardHookPlatformSetupOverride;
685
686 SetMem(&SetupVolatileData,sizeof(SETUP_VOLATILE_DATA),0);
687
688 VariableSize = sizeof (SETUP_VOLATILE_DATA);
689 Status = gRT->GetVariable (
690 L"SetupVolatileData",
691 &gSetupVariableGuid,
692 &SetupVolAttributes,
693 &VariableSize,
694 &SetupVolatileData
695 );
696 ASSERT_EFI_ERROR (Status);
697 //
698 // Get VTd status
699 //
700 HbPciD0F0RegBase = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, 0);
701 SetupVolatileData.VTdAvailable = (PciSegmentRead32 (HbPciD0F0RegBase + 0xe4) & BIT23) ? 0 : 1;
702
703 SetupVolatileData.PlatformFlavor = PcdGet8 (PcdPlatformFlavor);
704 SetupVolatileData.FabId = PcdGet8 (PcdBoardRev);
705 SetupVolatileData.BoardBomId = PcdGet8 (PcdBoardBomId);
706 SetupVolatileData.PlatformType = PcdGet8 (PcdPlatformType);
707 SetupVolatileData.BoardType = PcdGet8 (PcdBoardType);
708
709 BoardHookPlatformSetupOverride = (BOARD_HOOK_PLATFORM_SETUP_OVERRIDE) (UINTN) PcdGet64 (PcdFuncBoardHookPlatformSetupOverride);
710 ASSERT (BoardHookPlatformSetupOverride != NULL);
711 if (BoardHookPlatformSetupOverride) {
712 Status = BoardHookPlatformSetupOverride ((VOID *) &SetupVolatileData);
713 }
714
715 Status = gRT->SetVariable (
716 L"SetupVolatileData",
717 &gSetupVariableGuid,
718 SetupVolAttributes,
719 sizeof (SETUP_VOLATILE_DATA),
720 &SetupVolatileData
721 );
722 ASSERT_EFI_ERROR (Status);
723 }
724
725 /**
726 Entry point for the driver.
727
728 @param[in] ImageHandle Image Handle.
729 @param[in] SystemTable EFI System Table.
730
731 @retval EFI_SUCCESS Function has completed successfully.
732 @retval Others All other error conditions encountered result in an ASSERT.
733 **/
734 EFI_STATUS
735 EFIAPI
736 PlatformInitDxe (
737 IN EFI_HANDLE ImageHandle,
738 IN EFI_SYSTEM_TABLE *SystemTable
739 )
740 {
741 EFI_STATUS Status;
742 SETUP_DATA SetupData;
743 UINTN VariableSize;
744 UINT32 VariableAttr;
745 UINT8 *SecureBootState;
746
747 PostCode(PLATFORM_INIT_DXE_ENTRY);
748 Status = EFI_SUCCESS;
749
750 #ifdef SINITBIN_FLAG
751 Status = TxtSinitAcmLoad ();
752 if (Status == EFI_SUCCESS) {
753 DEBUG((DEBUG_INFO, "TXTDXE: Found SINIT ACM In FV\n"));
754 } else {
755 DEBUG((DEBUG_INFO, "TXTDXE: Error finding SINIT binary in FVs\n"));
756 }
757 #endif
758
759 Status = InstallSmbiosFviOemType(); // todo: remove it once Bios Guard convert the HOB generation.
760 ASSERT_EFI_ERROR (Status);
761
762 if (IsSgxSupported () && PcdGetBool (PcdSoftwareGuardEnable)) {
763 UpdateEpcVariables ();
764 UpdateSgxSvnVariable ();
765 UpdateSgxPolicyStatusVariable ();
766 }
767
768 SecureBootState = NULL;
769 GetVariable2 (L"SecureBootEnable", &gEfiSecureBootEnableDisableGuid, (VOID**)&SecureBootState, NULL);
770
771 //
772 // Set CsmControl Setup variable reflecting Secure boot status. Whenever Secure boot is enabled, CSM must be turned off.
773 //
774 if ((SecureBootState != NULL) && (*SecureBootState)) {
775 VariableSize = sizeof (SETUP_DATA);
776 Status = gRT->GetVariable (
777 L"Setup",
778 &gSetupVariableGuid,
779 &VariableAttr,
780 &VariableSize,
781 &SetupData
782 );
783 ASSERT_EFI_ERROR (Status);
784
785 if (!EFI_ERROR (Status)) {
786 SetupData.CsmControl = EFI_CSM_CONTROL_ALWAYS_OFF;
787 SetupData.OpRomPost = OPROM_EFI;
788 Status = gRT->SetVariable (
789 L"Setup",
790 &gSetupVariableGuid,
791 VariableAttr,
792 VariableSize,
793 &SetupData
794 );
795 ASSERT_EFI_ERROR (Status);
796 }
797 }
798
799 if (SecureBootState != NULL) {
800 FreePool (SecureBootState);
801 }
802
803 #ifdef CSM_FLAG
804 if (PcdGetBool (PcdCsmEnable)) {
805 InitializeGfxInt15();
806 }
807 #endif
808
809 //
810 // Initialize System Agent platform settings
811 //
812 SaPlatformInitDxe();
813
814 //
815 // Update Platform information to the setup data
816 //
817 UpdatePlatformInfo();
818
819 #ifdef CSM_FLAG
820 //
821 // Save the SA settings related to Display while CSM is enabled
822 //
823 if(PcdGetBool (PcdCsmEnable)) {
824 UpdateSaDisplayRegisters ();
825 }
826 #endif
827
828 //
829 // Update DIMM funtionalities for desktop and server boards
830 //
831 UpdateDimmPopulation();
832
833 RegisterEndOfDxeCallbacks();
834 RegisterReadyToBootCallback ();
835
836 //
837 // Add Smbios type 4 and type 7 table.
838 //
839 AddSmbiosProcessorAndCacheTables ();
840
841 //
842 // Check if TPM2.0 exist.
843 //
844 if (CompareGuid (PcdGetPtr(PcdTpmInstanceGuid), &gEfiTpmDeviceInstanceNoneGuid)) {
845 } else if (CompareGuid (PcdGetPtr(PcdTpmInstanceGuid), &gEfiTpmDeviceInstanceTpm12Guid)) {
846 } else {
847 //
848 // Register Pch reset callback to shutdown TPM
849 //
850 Status = gBS->InstallProtocolInterface (
851 &ImageHandle,
852 &gPchResetCallbackProtocolGuid,
853 EFI_NATIVE_INTERFACE,
854 &mPchResetCallbackProtocol
855 );
856 ASSERT_EFI_ERROR (Status);
857 }
858
859 PostCode(PLATFORM_INIT_DXE_EXIT);
860
861 return Status;
862 }
863
864 #ifdef SINITBIN_FLAG
865 /**
866
867 This function looks for SINIT ACM in FVs and updates TXT HOB
868 with SINIT ACM Base and Size.
869
870 @retval EFI_SUCCESS - SINIT ACM found and copied.
871 @retval EFI_NOT_FOUND - If TxtInfoHob is not found
872 @retval EFI_UNSUPPORTED - TXT Device memory not available.
873
874 **/
875 EFI_STATUS
876 TxtSinitAcmLoad (
877 VOID
878 )
879 {
880 EFI_STATUS Status;
881 TXT_INFO_HOB *HobList;
882 TXT_INFO_DATA *TxtInfoData;
883 EFI_HANDLE *HandleBuffer;
884 UINTN NumberOfHandles;
885 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
886 UINTN Size;
887 EFI_FV_FILETYPE FileType;
888 UINT32 FvStatus;
889 EFI_FV_FILE_ATTRIBUTES Attributes;
890 UINT64 TxtHeapMemoryBase;
891 UINT64 TxtSinitMemoryBase;
892 UINT64 *Ptr64;
893 EFI_PHYSICAL_ADDRESS TopAddr;
894 BIOS_OS_DATA_REGION *BiosOsDataRegion;
895
896 HandleBuffer = NULL;
897 NumberOfHandles = 0;
898 FwVol = NULL;
899 FileType = 0;
900 Attributes = 0;
901 BiosOsDataRegion = NULL;
902
903 ///
904 /// Find TXT HOB
905 ///
906 HobList = (TXT_INFO_HOB *) GetFirstGuidHob (&gTxtInfoHobGuid);
907 if (HobList == NULL) {
908 return EFI_NOT_FOUND;
909 }
910
911 TxtInfoData = &HobList->Data;
912 ///
913 /// Check TXT mode
914 ///
915 if (TxtInfoData->TxtMode == 0){
916 return EFI_UNSUPPORTED;
917 }
918
919 if ((TxtInfoData == 0) ||
920 (TxtInfoData->TxtDprMemoryBase == 0) ||
921 (TxtInfoData->TxtDprMemorySize == 0) ||
922 (TxtInfoData->TxtHeapMemorySize == 0) ||
923 (TxtInfoData->SinitMemorySize == 0)
924 ) {
925 return EFI_UNSUPPORTED;
926 } else {
927 ///
928 /// Use address passed from PEI
929 ///
930 TopAddr = TxtInfoData->TxtDprMemoryBase + TxtInfoData->TxtDprMemorySize;
931
932 TxtHeapMemoryBase = (UINT64) (TopAddr - TxtInfoData->TxtHeapMemorySize);
933
934 TxtSinitMemoryBase = TxtHeapMemoryBase - TxtInfoData->SinitMemorySize;
935 }
936 ///
937 /// Start looking for SINIT ACM in FVs
938 ///
939 DEBUG((DEBUG_INFO, "TXTDXE: Looking for SINIT ACM in FVs\n"));
940
941 Status = gBS->LocateHandleBuffer(
942 ByProtocol,
943 &gEfiFirmwareVolume2ProtocolGuid,
944 NULL,
945 &NumberOfHandles,
946 &HandleBuffer
947 );
948 ASSERT_EFI_ERROR(Status);
949 ///
950 /// Looking for FV with SinitAC binary
951 ///
952 for (UINTN i = 0; i < NumberOfHandles; i++) {
953 ///
954 /// Get the protocol on this handle
955 ///
956 Status = gBS->HandleProtocol(
957 HandleBuffer[i],
958 &gEfiFirmwareVolume2ProtocolGuid,
959 &FwVol
960 );
961 ASSERT_EFI_ERROR(Status);
962 ///
963 /// See if it has the SinitACM file
964 ///
965 Size = 0;
966 FvStatus = 0;
967 Status = FwVol->ReadFile(
968 FwVol,
969 &gSinitModuleGuid,
970 NULL,
971 &Size,
972 &FileType,
973 &Attributes,
974 &FvStatus
975 );
976 ///
977 /// If the binary was located, then break
978 ///
979 if (Status == EFI_SUCCESS) {
980 DEBUG((DEBUG_INFO, "TXTDXE: Found SINIT ACM In FV\n"));
981 break;
982 }
983 }
984 FreePool(HandleBuffer);
985 ///
986 /// Sanity check
987 ///
988 if ( !(FwVol == NULL || Status != EFI_SUCCESS || Size >= TxtInfoData->SinitMemorySize ) ) {
989 ///
990 /// Read Sinit ACM from the storage file.
991 ///
992 Ptr64 = (UINT64 *)TxtSinitMemoryBase;
993 Status = FwVol->ReadFile(
994 FwVol,
995 &gSinitModuleGuid,
996 &Ptr64,
997 &Size,
998 &FileType,
999 &Attributes,
1000 &FvStatus
1001 );
1002 ASSERT_EFI_ERROR(Status);
1003 TxtInfoData->SinitAcmSize = (UINT64) Size;
1004
1005 Ptr64 = (UINT64 *) TxtHeapMemoryBase;
1006 ///
1007 /// BiosOsDataSize plus size of data size field itself
1008 ///
1009 BiosOsDataRegion = (BIOS_OS_DATA_REGION *) (Ptr64 + 1);
1010 BiosOsDataRegion->BiosSinitSize = (UINT32) TxtInfoData->SinitAcmSize;
1011 DEBUG((DEBUG_INFO, "TXTDXE: Copy SINIT ACM Done\n"));
1012 }
1013 return Status;
1014 }
1015 #endif
UpdateSgxPolicyStatusVariable
VOID UpdateSgxPolicyStatusVariable(VOID)
Creates a UEFI variable for reporting platform SGX status information.
Definition: PlatformInitDxe.c:611
EndofDxeCallback
VOID EndofDxeCallback(IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInit task at the end of DXE.
Definition: PlatformInitDxe.c:87
RegisterEndOfDxeCallbacks
VOID RegisterEndOfDxeCallbacks(VOID)
Registers callback for.PlatformInitEndOfDxe.
Definition: PlatformInitDxe.c:155
UpdateSgxSvnVariable
VOID UpdateSgxSvnVariable(VOID)
Definition: PlatformInitDxe.c:561
EPC_OS_CONFIG::RequestedEpcSize
UINT32 RequestedEpcSize
Requested EPC size in MB.
Definition: SoftwareGuardSetupData.h:48
EPC_OS_CONFIG
EPC data structure for OS Variable.
Definition: SoftwareGuardSetupData.h:47
_EPC_BIOS_CONFIG
EPC data structure for BIOS Variable.
Definition: SoftwareGuardSetupData.h:54
BootGuardOemRevocationHook
VOID BootGuardOemRevocationHook(VOID)
Provide a hook for OEM to deal with Boot Guard revocation flow.
SoftwareGuardSetupData.h
Software Guard Setup Variables and Structures.
PlatformInitDxe
EFI_STATUS PlatformInitDxe(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point for the driver.
Definition: PlatformInitDxe.c:736
CheckLidBaseEcProtocolVersion
VOID CheckLidBaseEcProtocolVersion(VOID)
Check Lid and Base EC Protocol Version.
Definition: EcPlatformInitDxe.c:49
PlatformInitDxe.h
Platform Info Driver.
SaPlatformInitDxe
VOID SaPlatformInitDxe(VOID)
System Agent platform Initialization.
Definition: SaPlatformInitDxe.c:406
EPC_BIOS_CONFIG
struct _EPC_BIOS_CONFIG EPC_BIOS_CONFIG
EPC data structure for BIOS Variable.
PlatformDxeReadyToBootCallback
VOID PlatformDxeReadyToBootCallback(IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInitDxe task at the ready to boot.
Definition: PlatformInitDxe.c:185
_EPC_BIOS_CONFIG::EpcMap
UINT32 EpcMap[32]
Mapping of PRM size to corresponding EPC size.
Definition: SoftwareGuardSetupData.h:58
UpdateEpcVariables
VOID UpdateEpcVariables(VOID)
Update BIOS and OS EPC UEFI variables.
Definition: PlatformInitDxe.c:383
SOFTWARE_GUARD_STATUS::SgxStatus
UINT8 SgxStatus
Bitmap of SGX Policy setting.
Definition: SoftwareGuardSetupData.h:76
PlatformNvsArea.h
This file defines the Platform NVS Area Protocol.
_EPC_BIOS_CONFIG::AllocatedEpcSize
UINT32 AllocatedEpcSize
Allocated EPC size in MB.
Definition: SoftwareGuardSetupData.h:57
RegisterReadyToBootCallback
VOID RegisterReadyToBootCallback(VOID)
Registers callback for PlatformDxeReadyToBoot.
Definition: PlatformInitDxe.c:200
EPC_FRACTION_NUMERATOR
#define EPC_FRACTION_NUMERATOR
SGX EPC definitions.
Definition: PlatformInitDxe.c:64
_EPC_BIOS_CONFIG::SupportedPrmBins
UINT32 SupportedPrmBins
supported EPC bins; Bit 0- Support for 1 MB, 1- Support for 2 MB, 2- Support for 4 MB...
Definition: SoftwareGuardSetupData.h:55
SOFTWARE_GUARD_STATUS
Data structure for SGX Policy Status The presence of this variable implies that SGX is supported For ...
Definition: SoftwareGuardSetupData.h:67
UpdatePlatformInfo
VOID UpdatePlatformInfo(VOID)
Updates Platform information to the setup data.
Definition: PlatformInitDxe.c:675
_EPC_BIOS_CONFIG::MaxEpcSize
UINT32 MaxEpcSize
Maximum EPC size supported by platform in MB.
Definition: SoftwareGuardSetupData.h:56
PlatformPchResetCallback
EFI_STATUS PlatformPchResetCallback(IN EFI_RESET_TYPE ResetType, IN EFI_GUID *ResetTypeGuid)
Call back function for Pch Reset.
Definition: PlatformInitDxe.c:228
UpdateDimmPopulation
VOID UpdateDimmPopulation(VOID)
Updates DIMM slots status for Desktop,server and workstation boards.
Definition: SaPlatformInitDxe.c:252
PlatformPostCode.h
CreateSgxInfoForOs
EPC_BIOS_CONFIG * CreateSgxInfoForOs(VOID)
Creates a UEFI variable for OS with all data regarding SGX EPC.
Definition: PlatformInitDxe.c:251
InitializeGfxInt15
VOID InitializeGfxInt15(VOID)
Inititialize Interrupt 15.
Definition: GfxInt15Interface.c:105
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformInitDxe.h Source File

  • PlatformInit
  • PlatformInitDxe
PlatformInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Platform Info Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_INIT_DXE_H_
36 #define _PLATFORM_INIT_DXE_H_
37
38 #include <Library/IoLib.h>
39 #include <Library/PcdLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <Library/UefiRuntimeServicesTableLib.h>
42 #include <PchAccess.h>
43 #include <SaAccess.h>
44 #include <Library/HobLib.h>
45 #include <SetupVariable.h>
46 #include <Library/DebugLib.h>
47 #include <Library/S3BootScriptLib.h>
48 #include <Library/BootGuardRevocationLib.h>
49 #include <Library/BaseMemoryLib.h>
50 #include <Library/MemoryAllocationLib.h>
51 #include <Library/PrintLib.h>
52 #include <Library/UefiLib.h>
53 #include <Uefi/UefiBaseType.h>
54 #include <Library/HobLib.h>
55 #include <OemSetup.h>
56 #include <Protocol/MemInfo.h>
57 #include <MemInfoHob.h>
58 #include <Library/PmcLib.h>
59 #include <Base.h>
60 #include "PlatformBoardId.h"
61 #include <PlatformBoardConfig.h>
62 #include <PlatformBoardType.h>
63 #include <Library/PciSegmentLib.h>
64 #ifdef SINITBIN_FLAG
65 #include <TxtInfoHob.h>
66 #include <Txt.h>
67 #include <Protocol/FirmwareVolume2.h>
68 #endif
69
70 //----------------------------------------------------------------------------
71 // VT-d Engine Configuration Register Details
72 //----------------------------------------------------------------------------
73 #define SA_VTD_RMRR_USB_LENGTH 0x20000
74
75 VOID
76 SaPlatformInitDxe (
77 VOID
78 );
79
80 VOID
81 EFIAPI
82 CheckLidBaseEcProtocolVersion (
83 VOID
84 );
85
86 VOID
87 UpdateDimmPopulation(
88 VOID
89 );
90
91 #ifdef CSM_FLAG
92 VOID
93 InitializeGfxInt15 (
94 VOID
95 );
96
97 VOID
98 UpdateSaDisplayRegisters(
99 VOID
100 );
101 #endif
102
103 #ifdef SINITBIN_FLAG
104 /**
105
106 This function looks for SINIT ACM in FVs and updates TXT HOB
107 with SINIT ACM Base and Size.
108
109 @retval EFI_SUCCESS - SINIT ACM found and copied.
110 @retval EFI_NOT_FOUND - If TxtInfoHob is not found
111 @retval EFI_UNSUPPORTED - TXT Device memory not available.
112
113 **/
114 EFI_STATUS
115 TxtSinitAcmLoad (
116 VOID
117 );
118 #endif
119
120 #endif
CheckLidBaseEcProtocolVersion
VOID CheckLidBaseEcProtocolVersion(VOID)
Check Lid and Base EC Protocol Version.
Definition: EcPlatformInitDxe.c:49
SaPlatformInitDxe
VOID SaPlatformInitDxe(VOID)
System Agent platform Initialization.
Definition: SaPlatformInitDxe.c:406
BootGuardRevocationLib.h
Header file for Boot Guard revocation notification.
OemSetup.h
OEM Specific Setup Variables and Structures.
PlatformBoardConfig.h
Header file for Platform Boards Configurations.
PlatformBoardId.h
Defines Platform BoardIds.
UpdateDimmPopulation
VOID UpdateDimmPopulation(VOID)
Updates DIMM slots status for Desktop,server and workstation boards.
Definition: SaPlatformInitDxe.c:252
SetupVariable.h
InitializeGfxInt15
VOID InitializeGfxInt15(VOID)
Inititialize Interrupt 15.
Definition: GfxInt15Interface.c:105
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformInitLib.h Source File

  • Library
PlatformInitLib.h
Go to the documentation of this file.
1 /** @file
2 Function prototype of PlatformInitLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_INIT_LIB_H_
36 #define _PLATFORM_INIT_LIB_H_
37
38 VOID
39 PlatformLateInit (
40 VOID
41 );
42
43 VOID
44 InitSerialPort (
45 VOID
46 );
47
48 #endif // _PLATFORM_INIT_LIB_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformInitPreMem.c Source File

  • PlatformInit
  • PlatformInitPei
PlatformInitPreMem.c
Go to the documentation of this file.
1 /** @file
2 Source code file for Platform Init Pre-Memory PEI module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #include <Base.h>
37 #include <OemSetup.h>
38 #include <PchAccess.h>
39 #include <SetupVariable.h>
40 #include <PlatformBoardId.h>
41 #include <SaPolicyCommon.h>
42 #include <CpuAccess.h>
43 #include <Platform.h>
44 #include <MeChipset.h>
45 #include <IndustryStandard/Pci30.h>
46 #include <Library/IoLib.h>
47 #include <PlatformNvRamHookLib.h>
48 #include <Library/DebugLib.h>
49 #include <Library/HobLib.h>
50 #include <Library/PcdLib.h>
51 #include <Library/TimerLib.h>
52 #include <Library/EcMiscLib.h>
53 #include <Library/EcCommands.h>
54 #include <Library/PciSegmentLib.h>
55 #include <Library/CpuPlatformLib.h>
56 #include <Library/BaseMemoryLib.h>
57 #include <Library/PeiServicesLib.h>
58 #include <Board/Include/PeiPlatformHookLib.h>
59 #include <Library/PchCycleDecodingLib.h>
60 #include <Library/PchPcrLib.h>
61 #include <Library/MultiPlatSupportLib.h>
62 #include <Library/PeiPlatformRecoveryLib.h>
63 #include <Library/PeiPolicyInitLib.h>
64 #include <Library/MemoryAllocationLib.h>
65 #include <Library/MtrrLib.h>
66 #include <Ppi/Smbus2.h>
67 #include <Ppi/ReadOnlyVariable2.h>
68 #include <Ppi/MemoryDiscovered.h>
69 #include <Ppi/FirmwareVolumeInfo.h>
70 #include <Ppi/Capsule.h>
71 #include <Ppi/BootInRecoveryMode.h>
72 #include <Ppi/MasterBootMode.h>
73 #include <Ppi/Reset.h>
74 #include <BootState.h>
75 #include <SimpleBootFlag.h>
76 #include <Guid/GlobalVariable.h>
77 #include <Guid/FirmwareFileSystem2.h>
78 #include <FastBootExceptionInfoHob.h>
79 #include <FastBootFunctionEnabledHob.h>
80 #include <Guid/TcoWdtHob.h>
81 #include <Guid/MemoryTypeInformation.h>
82 #include <Uefi/UefiInternalFormRepresentation.h>
83 #include <Library/PeiPlatformLib.h>
84 #include <Library/PeiWdtAppLib.h>
85 #include <Library/BiosIdLib.h>
86 #include <Include/Library/ConfigBlockLib.h>
87 #include <Library/PeiServicesTablePointerLib.h>
88 #include <Library/PchSerialIoLib.h>
89 #include <Library/SetupDataCacheLib.h>
90 #include <IndustryStandard/SmBios.h>
91 #include <FirwmareConfigurations.h>
92 #include <Library/BoardConfigLib.h>
93 #include <PlatformBoardConfig.h>
94 #include <Board/Include/BoardHook.h>
95 #include <Library/PmcLib.h>
96 #include <FastBootDataDef.h>
97 #include <Setup.h>
98 #include <Library/PostCodeLib.h>
99 #include <PlatformPostCode.h>
100 #include <Library/StallPpiLib.h>
101 #include <SaDataHob.h>
102 #include <Guid/ImageAuthentication.h>
103
104 ///
105 /// If the debugger branch trace/data store debug feature is enabled
106 /// This is an optional debug feature as enabling it will introduce
107 /// significant changes in performance and system resources
108 ///
109 #include "DsAllocation.h" //must be include for release build
110 ///
111
112 typedef struct {
113 EFI_PHYSICAL_ADDRESS BaseAddress;
114 UINT64 Length;
115 } MEMORY_MAP;
116
117 #ifndef STALL_ONE_MICRO_SECOND
118 #define STALL_ONE_MICRO_SECOND 1
119 #endif
120 #ifndef STALL_ONE_MILLI_SECOND
121 #define STALL_ONE_MILLI_SECOND 1000
122 #endif
123
124 #define FAST_BOOT_OR_MASK 0x01
125 #define BOOT_SPECIAL_MASK 0x80
126
127 ///
128 /// Reset Generator I/O Port
129 ///
130 #define RESET_GENERATOR_PORT 0xCF9
131
132 ///
133 /// Wake Event Types
134 ///
135
136 #define EC_GETWAKE_STATUS 0x35
137 #define EC_CLEARWAKE_STATUS 0x36
138
139 ///
140 /// Priority of our boot modes, highest priority first
141 ///
142 GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE mBootModePriority[] = {
143 BOOT_IN_RECOVERY_MODE,
144 BOOT_WITH_DEFAULT_SETTINGS,
145 BOOT_ON_FLASH_UPDATE,
146 BOOT_ON_S2_RESUME,
147 BOOT_ON_S3_RESUME,
148 BOOT_ON_S4_RESUME,
149 BOOT_WITH_MINIMAL_CONFIGURATION,
150 BOOT_ASSUMING_NO_CONFIGURATION_CHANGES,
151 BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS,
152 BOOT_WITH_FULL_CONFIGURATION,
153 BOOT_ON_S5_RESUME,
154 BOOT_SPECIAL_MASK
155 };
156
157 GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap [] = {
158 {FixedPcdGet64 (PcdApicLocalAddress), FixedPcdGet32 (PcdApicLocalMmioSize)},
159 {FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32 (PcdMchMmioSize)},
160 {FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32 (PcdDmiMmioSize)},
161 {FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32 (PcdEpMmioSize)},
162 #ifdef CPU_CFL
163 {FixedPcdGet64 (PcdGdxcBaseAddress), FixedPcdGet32 (PcdGdxcMmioSize)}
164 #endif
165 };
166
167 EFI_STATUS
168 EFIAPI
169 PlatformInitPreMem (
170 IN CONST EFI_PEI_SERVICES **PeiServices,
171 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
172 IN VOID *Ppi
173 );
174
175 EFI_STATUS
176 EFIAPI
177 Smbus2IsReadyCallback (
178 IN CONST EFI_PEI_SERVICES **PeiServices,
179 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
180 IN VOID *Ppi
181 );
182
183 EFI_STATUS
184 EFIAPI
185 MemoryDiscoveredPpiNotifyCallback (
186 IN CONST EFI_PEI_SERVICES **PeiServices,
187 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
188 IN VOID *Ppi
189 );
190
191 EFI_STATUS
192 EFIAPI
193 SiPreMemPolicyPpiNotifyCallback (
194 IN CONST EFI_PEI_SERVICES **PeiServices,
195 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
196 IN VOID *Ppi
197 );
198
199 EFI_STATUS
200 EFIAPI
201 WdtAppPpiNotifyCallback (
202 IN CONST EFI_PEI_SERVICES **PeiServices,
203 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
204 IN VOID *Ppi
205 );
206
207 EFI_STATUS
208 EFIAPI
209 PlatformInitPreMemUpdateBootMode (
210 IN CONST EFI_PEI_SERVICES **PeiServices,
211 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
212 IN VOID *Interface
213 );
214
215 EFI_STATUS
216 EFIAPI
217 PchReset (
218 IN CONST EFI_PEI_SERVICES **PeiServices
219 );
220
221 static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
222 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
223 &gEfiPeiReadOnlyVariable2PpiGuid,
224 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitPreMem
225 };
226
227 static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
228 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
229 &gEfiPeiMemoryDiscoveredPpiGuid,
230 (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
231 };
232
233 static EFI_PEI_NOTIFY_DESCRIPTOR mSiPreMemPolicyNotifyList = {
234 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
235 &gSiPreMemPolicyPpiGuid,
236 (EFI_PEIM_NOTIFY_ENTRY_POINT) SiPreMemPolicyPpiNotifyCallback
237 };
238
239 static EFI_PEI_NOTIFY_DESCRIPTOR mWdtPpiNotifyList = {
240 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
241 &gWdtPpiGuid,
242 (EFI_PEIM_NOTIFY_ENTRY_POINT) WdtAppPpiNotifyCallback
243 };
244
245 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListNonS3BootMode = {
246 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
247 &gEfiPeiBootInNonS3ModePpiGuid,
248 NULL
249 };
250
251 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
252 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
253 &gEfiPeiBootInRecoveryModePpiGuid,
254 NULL
255 };
256
257 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode = {
258 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
259 &gEfiPeiMasterBootModePpiGuid,
260 NULL
261 };
262
263 #ifdef CAPSULE_FLAG
264 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_NOTIFY_DESCRIPTOR mBootModeNotifyList = {
265 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
266 &gPeiCapsulePpiGuid,
267 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitPreMemUpdateBootMode
268 };
269 #endif // CAPSULE_FLAG
270
271 static EFI_PEI_RESET_PPI mResetPpi = {
272 PchReset
273 };
274
275 static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
276 {
277 (EFI_PEI_PPI_DESCRIPTOR_PPI| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
278 &gEfiPeiResetPpiGuid,
279 &mResetPpi
280 }
281 };
282
283 static EFI_PEI_PPI_DESCRIPTOR mPatchConfigurationDataPreMemPpi[] = {
284 {
285 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
286 &gPatchConfigurationDataPreMemPpiGuid,
287 NULL
288 }
289 };
290
291 EFI_STATUS
292 EFIAPI
293 PeiGuidForward (
294 VOID
295 );
296
297 VOID
298 PrintVariableData (
299 IN UINT8 *Data8,
300 IN UINTN DataSize
301 )
302 {
303 UINTN Index;
304
305 for (Index = 0; Index < DataSize; Index++) {
306 if (Index % 0x10 == 0) {
307 DEBUG ((DEBUG_INFO, "\n%08X:", Index));
308 }
309 DEBUG ((DEBUG_INFO, " %02X", *Data8++));
310 }
311 DEBUG ((DEBUG_INFO, "\n"));
312 }
313
314 /**
315 Perform the default variable initializations after variable service is ready.
316
317 @param[in] PeiServices Pointer to PEI Services Table.
318 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
319 caused this function to execute.
320 @param[in] Interface Pointer to the PPI data associated with this function.
321
322 @retval EFI_SUCCESS The function completes successfully
323 @retval others
324 **/
325 EFI_STATUS
326 EFIAPI
327 PlatformVariableInit (
328 IN CONST EFI_PEI_SERVICES **PeiServices,
329 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
330 IN VOID *Interface
331 )
332 {
333 EFI_STATUS Status;
334 EFI_STATUS Status2;
335 EFI_STATUS Status3;
336 EFI_STATUS Status4;
337 EFI_STATUS Status5;
338 SA_SETUP SaSetup;
339 ME_SETUP MeSetup;
340 CPU_SETUP CpuSetup;
341 PCH_SETUP PchSetup;
342 SETUP_DATA Setup;
343 UINTN DataSize;
344 UINTN SaDataSize;
345 UINTN MeDataSize;
346 UINTN CpuDataSize;
347 UINTN PchDataSize;
348 OS_PROFILE OsProfileData;
349 UINTN OsProfileSize;
350 UINT8 OsProfile;
351 UINT8 PrevOs;
352 UINT32 Attributes = 0;
353 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
354 EFI_BOOT_MODE BootMode;
355
356 VariableServices = (EFI_PEI_READ_ONLY_VARIABLE2_PPI *) Interface;
357
358 ///
359 /// Check whether OS defaults need to be loaded
360 ///
361 DEBUG ((DEBUG_INFO, "Check if OsDefaults need to be loaded \n"));
362
363 OsProfileSize = sizeof (OS_PROFILE);
364 Status = VariableServices->GetVariable (
365 VariableServices,
366 L"OsProfile",
367 &gOsProfileGuid,
368 &Attributes,
369 &OsProfileSize,
370 &OsProfileData
371 );
372
373 DEBUG ((DEBUG_INFO, "Get OsProfile variable, Status = %r, Attributes = %X \n", Status, Attributes));
374
375 if (EFI_ERROR (Status)) {
376 DEBUG ((DEBUG_INFO, "OS_PROFILE not available yet, do nothing \n" ));
377 OsProfile = 0;
378 PrevOs = 0;
379 } else {
380 OsProfile = OsProfileData.OsProfile;
381 PrevOs = OsProfileData.PrevOs;
382 DEBUG ((DEBUG_INFO, "OsProfile = %X, PrevOs = %X \n", OsProfile, PrevOs));
383 }
384
385 ///
386 /// To verify if secondary NvRam corrupted and see if resetting to default variable is required or not.
387 ///
388 if (NeedResetBoardDefaultVariableHob()) {
389 return CreateBoardDefaultVariableHob (EFI_HII_DEFAULT_CLASS_STANDARD, OsProfile);
390 }
391
392 ///
393 /// Check BootMode on Recovery boot or Boot with Default settings.
394 ///
395 Status = PeiServicesGetBootMode (&BootMode);
396 ASSERT_EFI_ERROR (Status);
397 if (BootMode == BOOT_IN_RECOVERY_MODE || BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
398 return CreateBoardDefaultVariableHob (EFI_HII_DEFAULT_CLASS_STANDARD, OsProfile);
399 }
400
401 ///
402 /// Check whether Setup Variable does exist to know the first boot or not.
403 ///
404 DataSize = sizeof (SETUP_DATA);
405 Status = VariableServices->GetVariable (VariableServices, L"Setup", &gSetupVariableGuid, NULL, &DataSize, &Setup);
406
407 SaDataSize = sizeof (SA_SETUP);
408 Status2 = VariableServices->GetVariable (VariableServices, L"SaSetup", &gSaSetupVariableGuid, NULL, &SaDataSize, &SaSetup);
409
410 MeDataSize = sizeof (ME_SETUP);
411 Status3 = VariableServices->GetVariable (VariableServices, L"MeSetup", &gMeSetupVariableGuid, NULL, &MeDataSize, &MeSetup);
412
413 CpuDataSize = sizeof (CPU_SETUP);
414 Status4 = VariableServices->GetVariable (VariableServices, L"CpuSetup", &gCpuSetupVariableGuid, NULL, &CpuDataSize, &CpuSetup);
415
416 PchDataSize = sizeof (PCH_SETUP);
417 Status5 = VariableServices->GetVariable (VariableServices, L"PchSetup", &gPchSetupVariableGuid, NULL, &PchDataSize, &PchSetup);
418
419 ///
420 /// Setup variable is not found. So, set the default setting.
421 ///
422 if (Status == EFI_NOT_FOUND || Status2 == EFI_NOT_FOUND || Status3 == EFI_NOT_FOUND || Status4 == EFI_NOT_FOUND || Status5 == EFI_NOT_FOUND || (OsProfile != PrevOs)) {
423 Status = CreateBoardDefaultVariableHob (EFI_HII_DEFAULT_CLASS_STANDARD, OsProfile);
424 if (EFI_ERROR (Status)) {
425 return Status;
426 }
427
428 Status = VariableServices->GetVariable (VariableServices, L"Setup", &gSetupVariableGuid, NULL, &DataSize, &Setup);
429 ASSERT_EFI_ERROR (Status);
430
431 Status = VariableServices->GetVariable (VariableServices, L"SaSetup", &gSaSetupVariableGuid, NULL, &SaDataSize, &SaSetup);
432 ASSERT_EFI_ERROR (Status);
433
434 Status = VariableServices->GetVariable (VariableServices, L"MeSetup", &gMeSetupVariableGuid, NULL, &MeDataSize, &MeSetup);
435 ASSERT_EFI_ERROR (Status);
436
437 Status = VariableServices->GetVariable (VariableServices, L"CpuSetup", &gCpuSetupVariableGuid, NULL, &CpuDataSize, &CpuSetup);
438 ASSERT_EFI_ERROR (Status);
439
440 Status = VariableServices->GetVariable (VariableServices, L"PchSetup", &gPchSetupVariableGuid, NULL, &PchDataSize, &PchSetup);
441 ASSERT_EFI_ERROR (Status);
442
443 DEBUG_CODE_BEGIN();
444 ///
445 /// Print default Setup variable.
446 ///
447 DEBUG ((DEBUG_INFO, "\nDumping SETUP_DATA:"));
448 PrintVariableData ((UINT8 *) &Setup, DataSize);
449
450 DEBUG ((DEBUG_INFO, "\nDumping SA_SETUP:"));
451 PrintVariableData ((UINT8 *) &SaSetup, SaDataSize);
452
453 DEBUG ((DEBUG_INFO, "\nDumping CPU_SETUP:"));
454 PrintVariableData ((UINT8 *) &CpuSetup, CpuDataSize);
455
456 DEBUG ((DEBUG_INFO, "\nDumping ME_SETUP:"));
457 PrintVariableData ((UINT8 *) &MeSetup, MeDataSize);
458
459 DEBUG ((DEBUG_INFO, "\nDumping PCH_SETUP:"));
460 PrintVariableData ((UINT8 *) &PchSetup, PchDataSize);
461 DEBUG_CODE_END();
462 }
463
464 return EFI_SUCCESS;
465 }
466
467
468 /**
469 Set Cache Mtrr.
470 **/
471 VOID
472 SetCacheMtrr (
473 VOID
474 )
475 {
476 EFI_STATUS Status;
477 EFI_PEI_HOB_POINTERS Hob;
478 MTRR_SETTINGS MtrrSetting;
479 UINT64 MemoryBase;
480 UINT64 MemoryLength;
481 UINT64 LowMemoryLength;
482 UINT64 HighMemoryLength;
483 EFI_BOOT_MODE BootMode;
484 EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
485 UINT64 CacheMemoryLength;
486
487 ///
488 /// Reset all MTRR setting.
489 ///
490 ZeroMem (&MtrrSetting, sizeof (MTRR_SETTINGS));
491
492 ///
493 /// Cache the Flash area as WP to boost performance
494 /// Set WP cache size to fixed at 16MB for saving MTRR usage.
495 ///
496 Status = MtrrSetMemoryAttributeInMtrrSettings (
497 &MtrrSetting,
498 0xff000000,
499 0x01000000,
500 CacheWriteProtected
501 );
502 ASSERT_EFI_ERROR (Status);
503
504 ///
505 /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
506 ///
507 MtrrSetAllMtrrs (&MtrrSetting);
508
509 ///
510 /// Set low to 1 MB. Since 1MB cacheability will always be set
511 /// until override by CSM.
512 /// Initialize high memory to 0.
513 ///
514 LowMemoryLength = 0x100000;
515 HighMemoryLength = 0;
516 ResourceAttribute = (
517 EFI_RESOURCE_ATTRIBUTE_PRESENT |
518 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
519 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
520 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
521 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
522 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
523 );
524
525 Status = PeiServicesGetBootMode (&BootMode);
526 ASSERT_EFI_ERROR (Status);
527
528 if (BootMode != BOOT_ON_S3_RESUME) {
529 ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
530 }
531
532 Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
533 while (!END_OF_HOB_LIST (Hob)) {
534 if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
535 if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
536 ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
537 (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
538 ) {
539 if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
540 HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
541 } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
542 LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
543 }
544 }
545 }
546
547 Hob.Raw = GET_NEXT_HOB (Hob);
548 }
549
550 DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
551 DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
552
553 ///
554 /// Assume size of main memory is multiple of 256MB
555 ///
556 MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
557 MemoryBase = 0;
558
559 CacheMemoryLength = MemoryLength;
560 ///
561 /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
562 ///
563 if (MemoryLength > 0xDC000000) {
564 CacheMemoryLength = 0xC0000000;
565 Status = MtrrSetMemoryAttributeInMtrrSettings (
566 &MtrrSetting,
567 MemoryBase,
568 CacheMemoryLength,
569 CacheWriteBack
570 );
571 ASSERT_EFI_ERROR (Status);
572
573 MemoryBase = 0xC0000000;
574 CacheMemoryLength = MemoryLength - 0xC0000000;
575 if (MemoryLength > 0xE0000000) {
576 CacheMemoryLength = 0x20000000;
577 Status = MtrrSetMemoryAttributeInMtrrSettings (
578 &MtrrSetting,
579 MemoryBase,
580 CacheMemoryLength,
581 CacheWriteBack
582 );
583 ASSERT_EFI_ERROR (Status);
584
585 MemoryBase = 0xE0000000;
586 CacheMemoryLength = MemoryLength - 0xE0000000;
587 }
588 }
589
590 Status = MtrrSetMemoryAttributeInMtrrSettings (
591 &MtrrSetting,
592 MemoryBase,
593 CacheMemoryLength,
594 CacheWriteBack
595 );
596 ASSERT_EFI_ERROR (Status);
597
598 if (LowMemoryLength != MemoryLength) {
599 MemoryBase = LowMemoryLength;
600 MemoryLength -= LowMemoryLength;
601 Status = MtrrSetMemoryAttributeInMtrrSettings (
602 &MtrrSetting,
603 MemoryBase,
604 MemoryLength,
605 CacheUncacheable
606 );
607 ASSERT_EFI_ERROR (Status);
608 }
609
610 ///
611 /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
612 ///
613 Status = MtrrSetMemoryAttributeInMtrrSettings (
614 &MtrrSetting,
615 0xA0000,
616 0x20000,
617 CacheUncacheable
618 );
619 ASSERT_EFI_ERROR (Status);
620
621 Status = MtrrSetMemoryAttributeInMtrrSettings (
622 &MtrrSetting,
623 0xC0000,
624 0x40000,
625 CacheWriteProtected
626 );
627 ASSERT_EFI_ERROR ( Status);
628 ///
629 /// Update MTRR setting from MTRR buffer
630 ///
631 MtrrSetAllMtrrs (&MtrrSetting);
632
633 return;
634 }
635
636 /**
637 figure out the CSM configuration and post it to PcdCsmEnable.
638
639 @param[in] Event Event whose notification function is being invoked.
640 @param[in] Context Pointer to the notification function's context.
641 **/
642 VOID
643 EFIAPI
644 GetCsmControlStatus (
645 VOID
646 )
647 {
648 UINT8 SecureBoot;
649 EFI_STATUS Status;
650 SA_DATA_HOB *SaDataHob;
651 UINTN VariableSize;
652 SETUP_DATA mSetupData;
653 BOOLEAN CsmEnabled;
654 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
655 #ifdef FSP_WRAPPER_FLAG
656 VOID **FspHobListPtr;
657 EFI_PEI_HOB_POINTERS Hob;
658 #endif
659
660 ///
661 /// Read EFI variable
662 ///
663 Status = PeiServicesLocatePpi (
664 &gEfiPeiReadOnlyVariable2PpiGuid,
665 0,
666 NULL,
667 (VOID **) &PeiVar
668 );
669 ASSERT_EFI_ERROR (Status);
670 VariableSize = sizeof (SecureBoot);
671 Status = PeiVar->GetVariable (
672 PeiVar,
673 EFI_SECURE_BOOT_MODE_NAME,
674 &gEfiGlobalVariableGuid,
675 NULL,
676 &VariableSize,
677 &SecureBoot
678 );
679
680 if (!EFI_ERROR (Status) && (SecureBoot == SECURE_BOOT_MODE_ENABLE)) {
681 CsmEnabled = FALSE;
682 } else {
683 VariableSize = sizeof (SETUP_DATA);
684 Status = PeiVar->GetVariable (
685 PeiVar,
686 L"Setup",
687 &gSetupVariableGuid,
688 NULL,
689 &VariableSize,
690 &mSetupData
691 );
692
693 if (EFI_ERROR (Status)) {
694 mSetupData.CsmControl = EFI_CSM_CONTROL_DETECT_LEGACY_VGA;
695 }
696 switch (mSetupData.CsmControl) {
697 case EFI_CSM_CONTROL_ALWAYS_OFF:
698 CsmEnabled = FALSE;
699 break;
700
701 case EFI_CSM_CONTROL_ALWAYS_ON:
702 CsmEnabled = TRUE;
703 break;
704
705 case EFI_CSM_CONTROL_DETECT_LEGACY_VGA:
706 SaDataHob = NULL;
707 #ifndef FSP_WRAPPER_FLAG
708 SaDataHob = (SA_DATA_HOB *) GetFirstGuidHob (&gSaDataHobGuid);
709 #else
710 Hob.Raw = GetFirstGuidHob (&gFspHobGuid);
711 if (Hob.Raw != NULL) {
712 FspHobListPtr = GET_GUID_HOB_DATA(Hob.Raw);
713 SaDataHob = GetNextGuidHob(&gSaDataHobGuid, *FspHobListPtr);
714 }
715 #endif
716 if (SaDataHob != NULL) {
717 if (SaDataHob->LegacyOnlyVgaOpRomDetected) {
718 CsmEnabled = TRUE;
719 } else {
720 CsmEnabled = FALSE;
721 }
722 } else {
723 CsmEnabled = FALSE;
724 }
725 break;
726
727 default:
728 ASSERT (FALSE);
729 CsmEnabled = FALSE;
730 break;
731 }
732 }
733
734 PcdSetBoolS (PcdCsmEnable, CsmEnabled);
735 }
736
737 /**
738 Install Firmware Volume Hob's once there is main memory
739
740 @param[in] PeiServices General purpose services available to every PEIM.
741 @param[in] NotifyDescriptor Notify that this module published.
742 @param[in] Ppi PPI that was installed.
743
744 @retval EFI_SUCCESS The function completed successfully.
745 **/
746 EFI_STATUS
747 EFIAPI
748 MemoryDiscoveredPpiNotifyCallback (
749 IN CONST EFI_PEI_SERVICES **PeiServices,
750 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
751 IN VOID *Ppi
752 )
753 {
754 EFI_STATUS Status;
755 EFI_BOOT_MODE BootMode;
756 UINTN Index;
757 UINT8 PhysicalAddressBits;
758 UINT32 RegEax;
759 MEMORY_MAP PcieMmioMap;
760
761 Index = 0;
762
763 Status = PeiServicesGetBootMode (&BootMode);
764 ASSERT_EFI_ERROR (Status);
765
766 SetCacheMtrr ();
767
768 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
769 if (RegEax >= 0x80000008) {
770 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
771 PhysicalAddressBits = (UINT8) RegEax;
772 } else {
773 PhysicalAddressBits = 36;
774 }
775
776 ///
777 /// Create a CPU hand-off information
778 ///
779 BuildCpuHob (PhysicalAddressBits, 16);
780
781 GetCsmControlStatus ();
782
783 ///
784 /// If S3 resume, then we are done
785 ///
786 if (BootMode == BOOT_ON_S3_RESUME) {
787 return EFI_SUCCESS;
788 }
789 ///
790 /// Build HOB for DXE
791 ///
792 if (BootMode == BOOT_IN_RECOVERY_MODE) {
793 ///
794 /// Prepare the recovery service
795 ///
796 Status = InitializeRecovery ();
797 ASSERT_EFI_ERROR (Status);
798 } else {
799
800 PeiServicesInstallFvInfo2Ppi (
801 &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashFvMainBase))->FileSystemGuid),
802 (VOID *) (UINTN) FixedPcdGet32 (PcdFlashFvMainBase),
803 FixedPcdGet32 (PcdFlashFvMainSize),
804 NULL,
805 NULL,
806 0
807 );
808
809 }
810
811 ///
812 /// Build Memory Mapped IO Resource which is used to build E820 Table in LegacyBios.
813 ///
814 PcieMmioMap.BaseAddress = FixedPcdGet64 (PcdPciExpressBaseAddress);
815 PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
816
817 BuildResourceDescriptorHob (
818 EFI_RESOURCE_MEMORY_MAPPED_IO,
819 (EFI_RESOURCE_ATTRIBUTE_PRESENT |
820 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
821 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
822 PcieMmioMap.BaseAddress,
823 PcieMmioMap.Length
824 );
825 BuildMemoryAllocationHob (
826 PcieMmioMap.BaseAddress,
827 PcieMmioMap.Length,
828 EfiMemoryMappedIO
829 );
830 for (Index = 0; Index < sizeof (MmioMap) / (sizeof (MEMORY_MAP)); Index++) {
831 BuildResourceDescriptorHob (
832 EFI_RESOURCE_MEMORY_MAPPED_IO,
833 (EFI_RESOURCE_ATTRIBUTE_PRESENT |
834 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
835 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
836 MmioMap[Index].BaseAddress,
837 MmioMap[Index].Length
838 );
839 BuildMemoryAllocationHob (
840 MmioMap[Index].BaseAddress,
841 MmioMap[Index].Length,
842 EfiMemoryMappedIO
843 );
844 }
845
846 //
847 // Report resource HOB for flash FV
848 //
849 BuildResourceDescriptorHob (
850 EFI_RESOURCE_MEMORY_MAPPED_IO,
851 (EFI_RESOURCE_ATTRIBUTE_PRESENT |
852 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
853 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
854 (UINTN) FixedPcdGet32 (PcdBiosAreaBaseAddress),
855 (UINTN) FixedPcdGet32 (PcdBiosSize)
856 );
857 BuildMemoryAllocationHob (
858 (UINTN) FixedPcdGet32 (PcdBiosAreaBaseAddress),
859 (UINTN) FixedPcdGet32 (PcdBiosSize),
860 EfiMemoryMappedIO
861 );
862
863 BuildFvHob (
864 (UINTN) FixedPcdGet32 (PcdBiosAreaBaseAddress),
865 (UINTN) FixedPcdGet32 (PcdBiosSize)
866 );
867
868 return Status;
869 }
870
871 /**
872 Check fast boot is enabled or not
873
874 @retval FastBootEnabledStatus TRUE means fast boot is enabled
875 FALSE means fast boot is disabled
876 **/
877 BOOLEAN
878 EFIAPI
879 IsFastBootEnabled (
880 VOID
881 )
882 {
883 EFI_STATUS Status;
884 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
885 UINTN VarSize;
886 SETUP_DATA SystemConfiguration;
887 BOOLEAN FastBootEnabledStatus;
888
889 FastBootEnabledStatus = FALSE;
890 Status = PeiServicesLocatePpi (
891 &gEfiPeiReadOnlyVariable2PpiGuid,
892 0,
893 NULL,
894 (VOID **) &PeiReadOnlyVarPpi
895 );
896 if (Status == EFI_SUCCESS) {
897 VarSize = sizeof (SETUP_DATA);
898 Status = PeiReadOnlyVarPpi->GetVariable (
899 PeiReadOnlyVarPpi,
900 L"Setup",
901 &gSetupVariableGuid,
902 NULL,
903 &VarSize,
904 &SystemConfiguration
905 );
906 if (Status == EFI_SUCCESS) {
907 if (SystemConfiguration.FastBoot != 0) {
908 FastBootEnabledStatus = TRUE;
909 }
910 }
911 }
912
913 return FastBootEnabledStatus;
914 }
915
916
917 /**
918 Check Fast Boot 30-second WDT (TCO Timer) timeout has occurred
919
920 @retval TRUE Timeout has occurred
921 @retval FALSE Timeout didnt occur
922 **/
923 BOOLEAN
924 IsTimeOutOccurred (
925 VOID
926 )
927 {
928 if (IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TWDS) == FAST_BOOT_WDT_RESET_SIGNATURE) {
929 IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TWDS, 0);
930 DEBUG ((DEBUG_INFO, "WDT occurred in previous boot\n"));
931 return TRUE;
932 }
933
934 DEBUG ((DEBUG_INFO, "WDT did not occur in previous boot\n"));
935 return FALSE;
936 }
937
938
939 /**
940 Check if this system boot is due to 4sec power button override has occurred
941
942 @retval TRUE Power Button Override occurred in last system boot
943 @retval FALSE Power Button Override didnt occur
944 **/
945 BOOLEAN
946 IsPowerButtonOverride (
947 VOID
948 )
949 {
950 if (PmcIsPowerButtonOverrideDetected ()) {
951 DEBUG ((DEBUG_INFO, "Power Button Override occurred in last system boot\n"));
952 return TRUE;
953 }
954
955 DEBUG ((DEBUG_INFO, "Power Button Override did not occur\n"));
956 return FALSE;
957 }
958
959
960 #ifdef _MSC_VER
961 #pragma warning (push)
962 #pragma warning (disable : 4090)
963 #endif
964
965 /**
966 Check Boot Flag Status to determine if previous boot was successful
967
968 @retval TRUE Previous Boot was success
969 @retval FALSE Previous Boot wasn't success
970 **/
971 BOOLEAN
972 IsPreviousBootSuccessful (
973 VOID
974 )
975 {
976 EFI_STATUS Status;
977 UINT8 PreviousBootCompletionFlag;
978 BOOLEAN BootState;
979 UINTN DataSize;
980 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
981
982 Status = PeiServicesLocatePpi (
983 &gEfiPeiReadOnlyVariable2PpiGuid,
984 0,
985 NULL,
986 (VOID **) &PeiVar
987 );
988 ASSERT_EFI_ERROR (Status);
989
990 ///
991 /// Get last Boot State Variable to confirm that it is not a first boot.
992 ///
993 DataSize = sizeof (BOOLEAN);
994 Status = PeiVar->GetVariable (
995 PeiVar,
996 BOOT_STATE_VARIABLE_NAME,
997 &gBootStateGuid,
998 NULL,
999 &DataSize,
1000 &BootState
1001 );
1002 if (EFI_ERROR (Status)) {
1003 return FALSE;
1004 }
1005 PreviousBootCompletionFlag = 0;
1006
1007 PreviousBootCompletionFlag = GetBootFlagStatus();
1008 PreviousBootCompletionFlag &= FAST_BOOT_OR_MASK;
1009
1010 if(PreviousBootCompletionFlag){
1011 DEBUG ((DEBUG_INFO, "Previous Boot was not successful to boot to OS\n"));
1012 return FALSE;
1013 }
1014 DEBUG ((DEBUG_INFO, "Previous boot cycle successfully completed handover to OS\n"));
1015 return TRUE;
1016 }
1017
1018 #ifdef _MSC_VER
1019 #pragma warning (pop)
1020 #endif
1021
1022
1023 /**
1024 Query PCH to determine if Intrusion Detection set
1025
1026 @retval TRUE No Change
1027 @retavl FALSE Change
1028 **/
1029 BOOLEAN
1030 IsBootWithNoChange (
1031 VOID
1032 )
1033 {
1034 EFI_STATUS Status;
1035 UINT16 TcoBase;
1036 UINT16 Tco2Status;
1037 BOOLEAN BoxOpen;
1038 BOOLEAN BootState;
1039 UINTN DataSize;
1040 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
1041
1042 Status = PeiServicesLocatePpi (
1043 &gEfiPeiReadOnlyVariable2PpiGuid,
1044 0,
1045 NULL,
1046 (VOID **) &PeiVar
1047 );
1048 ASSERT_EFI_ERROR (Status);
1049
1050 ///
1051 /// Get last Boot State Variable From NVRAM
1052 ///
1053 DataSize = sizeof (BOOLEAN);
1054 Status = PeiVar->GetVariable (
1055 PeiVar,
1056 BOOT_STATE_VARIABLE_NAME,
1057 &gBootStateGuid,
1058 NULL,
1059 &DataSize,
1060 &BootState
1061 );
1062 if (EFI_ERROR (Status)) {
1063 // If there's no variable, just report the state of the hardware
1064 BootState = TRUE;
1065 }
1066
1067 ///
1068 /// Read the TCO registers
1069 ///
1070 TcoBase = (UINT16)PcdGet16 (PcdTcoBaseAddress);
1071 Tco2Status = IoRead16 (TcoBase + R_TCO_IO_TCO2_STS);
1072
1073 ///
1074 /// This is the state of the hardware
1075 ///
1076 BoxOpen = (BOOLEAN) (Tco2Status & B_TCO_IO_TCO2_STS_INTRD_DET);
1077 if (BoxOpen) {
1078 ///
1079 /// Clear the bit for next boot.
1080 ///
1081 Tco2Status |= B_TCO_IO_TCO2_STS_INTRD_DET;
1082 IoWrite16 (TcoBase + R_TCO_IO_TCO2_STS, Tco2Status);
1083
1084 ///
1085 /// Since it was OPEN, return that it cannot be in "no config. change boot"
1086 ///
1087 DEBUG ((DEBUG_INFO, "Boot with Full configuration\n"));
1088 return FALSE;
1089 } else {
1090 ///
1091 /// Since it was CLOSED, return that can be "no config. change boot"
1092 /// Need variable to know that memory was tested AT LEAST one time!
1093 ///
1094 if (!BootState) {
1095 DEBUG ((DEBUG_INFO, "Boot assuming no configuration changes\n"));
1096 return TRUE;
1097 } else {
1098 DEBUG ((DEBUG_INFO, "Boot with Full configuration\n"));
1099 return FALSE;
1100 }
1101 }
1102 }
1103
1104
1105 /**
1106 Given the current boot mode, and a proposed new boot mode, determine
1107 which has priority. If the new boot mode has higher priority, then
1108 make it the current boot mode.
1109
1110 @param[in][out] CurrentBootMode pointer to current planned boot mode
1111 @param[in][out] NewBootMode proposed boot mode
1112
1113 @retval EFI_NOT_FOUND if either boot mode is not recognized
1114 @retval EFI_SUCCESS if both boot mode values were
1115 recognized and were processed.
1116 **/
1117 EFI_STATUS
1118 PrioritizeBootMode (
1119 IN OUT EFI_BOOT_MODE *CurrentBootMode,
1120 IN EFI_BOOT_MODE NewBootMode
1121 )
1122 {
1123 UINT32 CurrentIndex;
1124 UINT32 NewIndex;
1125
1126 ///
1127 /// Find the position of the current boot mode in our priority array
1128 ///
1129 for ( CurrentIndex = 0;
1130 CurrentIndex < sizeof (mBootModePriority) / sizeof (mBootModePriority[0]);
1131 CurrentIndex++) {
1132 if (mBootModePriority[CurrentIndex] == *CurrentBootMode) {
1133 break;
1134 }
1135 }
1136 if (CurrentIndex >= sizeof (mBootModePriority) / sizeof (mBootModePriority[0])) {
1137 return EFI_NOT_FOUND;
1138 }
1139 ///
1140 /// Find the position of the new boot mode in our priority array
1141 ///
1142 for ( NewIndex = 0;
1143 NewIndex < sizeof (mBootModePriority) / sizeof (mBootModePriority[0]);
1144 NewIndex++) {
1145 if (mBootModePriority[NewIndex] == NewBootMode) {
1146 ///
1147 /// If this new boot mode occurs before the current boot mode in the
1148 /// priority array, then take it.
1149 ///
1150 if (NewIndex < CurrentIndex) {
1151 *CurrentBootMode = NewBootMode;
1152 }
1153 return EFI_SUCCESS;
1154 }
1155 }
1156 return EFI_NOT_FOUND;
1157 }
1158
1159
1160 /**
1161 Check if the value is of ODD parity.
1162
1163 @param[in] Value the 8 bits value
1164
1165 @retval TRUE the value is of ODD parity
1166 @retval FALSE the value is not of ODD parity
1167 **/
1168 BOOLEAN
1169 CheckOddParity (
1170 IN UINT8 Value
1171 )
1172 {
1173 UINT8 OddNum;
1174 UINT8 Index;
1175
1176 OddNum = 0;
1177
1178 for (Index = 0; Index < 8; Index++) {
1179 if (Value & (1 << Index)) {
1180 OddNum++;
1181 }
1182 }
1183
1184 return (BOOLEAN) (OddNum % 2 != 0);
1185 }
1186
1187
1188 /**
1189 Get simple boot flag
1190
1191 @retval LegacyValue
1192 @retval EfiValue
1193 **/
1194 UINT8
1195 GetSimpleBootFlag (
1196 VOID
1197 )
1198 {
1199 EFI_STATUS Status;
1200 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;
1201 UINTN BufferSize;
1202 UINT8 EfiValue;
1203 UINT8 LegacyValue;
1204
1205 ///
1206 /// Read EFI variable
1207 ///
1208 Status = PeiServicesLocatePpi (
1209 &gEfiPeiReadOnlyVariable2PpiGuid,
1210 0,
1211 NULL,
1212 (VOID **) &PeiVar
1213 );
1214 ASSERT_EFI_ERROR (Status);
1215 EfiValue = 0;
1216 BufferSize = sizeof (EfiValue);
1217 Status = PeiVar->GetVariable (
1218 PeiVar,
1219 SIMPLE_BOOT_FLAG_VARIABLE_NAME,
1220 &gEfiGlobalVariableGuid,
1221 NULL,
1222 &BufferSize,
1223 &EfiValue
1224 );
1225
1226 if (!EFI_ERROR (Status)) {
1227 if (!CheckOddParity (EfiValue)) {
1228 EfiValue = 0;
1229 }
1230 }
1231
1232 ///
1233 /// Read legacy simple boot flag
1234 ///
1235 ///
1236 ///
1237 LegacyValue = GetRtc3Address();
1238
1239 if (!CheckOddParity (LegacyValue)) {
1240 LegacyValue = 0;
1241 }
1242
1243 return (LegacyValue != 0) ? LegacyValue : EfiValue;
1244 }
1245
1246 #ifdef _MSC_VER
1247 #pragma warning (push)
1248 #pragma warning (disable : 4090)
1249 #endif
1250
1251 EFI_STATUS
1252 EFIAPI
1253 PlatformInitPreMemUpdateBootMode (
1254 IN CONST EFI_PEI_SERVICES **PeiServices,
1255 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
1256 IN VOID *Interface
1257 )
1258 {
1259 EFI_STATUS Status;
1260 PEI_CAPSULE_PPI *Capsule;
1261 EFI_SIMPLE_BOOT_FLAG SimpleBootFlag;
1262 EFI_BOOT_MODE BootMode;
1263 UINT8 FastBootRegData;
1264 FAST_BOOT_EXCEPTION_INFO_HOB *FastBootExceptionInfoHob;
1265 FAST_BOOT_EXCEPTION_TYPE ExceptionType;
1266 FAST_BOOT_EXCEPTION_CATEGORY ExceptionCategory;
1267 BOOLEAN IsFastBootEnable;
1268 ExceptionType = NoException;
1269 ExceptionCategory = NoExceptionCategory;
1270 FastBootRegData = 0;
1271
1272 PeiServicesGetBootMode (&BootMode);
1273 IsFastBootEnable = IsFastBootEnabled ();
1274 ///
1275 /// Check Simple Boot Flag
1276 ///
1277 SimpleBootFlag.Uint8 = GetSimpleBootFlag ();
1278 if ((SimpleBootFlag.Bits.Booting != 0) || (SimpleBootFlag.Bits.Diag != 0)) {
1279 ///
1280 /// Don't set Diagnostics boot it will significantly impact boot performance. e.g.: MRC extensive memory test
1281 /// Current platform boot flow is very complex and it may reset before booting to OS.
1282 /// Need to design a hook machanism: bios calls PreReset() before resetting system when the BOOTING bit gets cleared.
1283 ///
1284 /// PrioritizeBootMode (&BootMode, BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS);
1285 }
1286
1287 ///
1288 /// Determine if we're in capsule update mode
1289 ///
1290 Status = PeiServicesLocatePpi (
1291 &gPeiCapsulePpiGuid,
1292 0,
1293 NULL,
1294 (VOID **)&Capsule
1295 );
1296 if (Status == EFI_SUCCESS) {
1297 Status = Capsule->CheckCapsuleUpdate ((EFI_PEI_SERVICES **) PeiServices);
1298 if (Status == EFI_SUCCESS) {
1299 PrioritizeBootMode (&BootMode, BOOT_ON_FLASH_UPDATE);
1300 }
1301 }
1302
1303 if ((BootMode != BOOT_ON_S5_RESUME) && IsBootWithNoChange ()) {
1304 PrioritizeBootMode (&BootMode, BOOT_ASSUMING_NO_CONFIGURATION_CHANGES);
1305 } else {
1306 PrioritizeBootMode (&BootMode, BOOT_WITH_FULL_CONFIGURATION);
1307 }
1308
1309 ///
1310 /// if Fast Boot is enabled, check other excption conditions before
1311 /// prioritizing BootMode to BOOT_WITH_MINIMAL_CONFIGURATION
1312 ///
1313 if (IsFastBootEnable) {
1314 if(IsPreviousBootSuccessful () && !IsTimeOutOccurred () && !IsPowerButtonOverride ()) {
1315 DEBUG ((DEBUG_INFO, "Prioritizing Boot mode to BOOT_WITH_MINIMAL_CONFIGURATION\n"));
1316 PrioritizeBootMode (&BootMode, BOOT_WITH_MINIMAL_CONFIGURATION);
1317 } else {
1318 Status = PeiServicesCreateHob (
1319 EFI_HOB_TYPE_GUID_EXTENSION,
1320 sizeof (FAST_BOOT_EXCEPTION_INFO_HOB),
1321 (VOID **) &FastBootExceptionInfoHob
1322 );
1323 if (!EFI_ERROR (Status)) {
1324 FastBootExceptionInfoHob->Header.Name = gFastBootExceptionInfoHobGuid;
1325 FastBootExceptionInfoHob->FbExceptionType = ExceptionType2;
1326 FastBootExceptionInfoHob->FbExceptionCategory = BootFailure;
1327 }
1328
1329 DEBUG ((DEBUG_INFO, "Exception has occurred. Prioritizing Boot mode to BOOT_WITH_FULL_CONFIGURATION\n"));
1330 PrioritizeBootMode (&BootMode, BOOT_WITH_FULL_CONFIGURATION);
1331 }
1332 }
1333
1334 Status = PeiServicesSetBootMode (BootMode);
1335 ASSERT_EFI_ERROR (Status);
1336 /*
1337 if (*BootMode == BOOT_ON_S3_RESUME) {
1338 Status = (**PeiServices).InstallPpi (PeiServices, &mPpiListSStateBootMode);
1339 ASSERT_EFI_ERROR (Status);
1340 }
1341 */
1342
1343 ///
1344 /// FastBoot - set boot progress bit to indicate boot is in progress
1345 /// bit will be cleared before booting to OS
1346 ///
1347 if (IsFastBootEnable) {
1348 if (BootMode != BOOT_ON_S3_RESUME) {
1349 FastBootRegData = GetBootFlagStatus();
1350 FastBootRegData |= FAST_BOOT_OR_MASK;
1351 UpdateBootFlagStatus(FastBootRegData);
1352 }
1353 }
1354
1355 ///
1356 /// Signal possible dependent modules that there has been a
1357 /// final boot mode determination, it is used to build BIST
1358 /// Hob for Dxe use.
1359 ///
1360 Status = PeiServicesInstallPpi (&mPpiBootMode);
1361 ASSERT_EFI_ERROR (Status);
1362
1363 if (BootMode != BOOT_ON_S3_RESUME) {
1364 ///
1365 /// If not in S3 mode, signal it.
1366 ///
1367 Status = PeiServicesInstallPpi (&mPpiListNonS3BootMode);
1368 ASSERT_EFI_ERROR (Status);
1369 }
1370
1371 return EFI_SUCCESS;
1372 }
1373
1374 #ifdef _MSC_VER
1375 #pragma warning (pop)
1376 #endif
1377
1378
1379 /**
1380 Detect boot mode
1381 **/
1382 VOID
1383 DetectBootMode (
1384 VOID
1385 )
1386 {
1387 EFI_STATUS Status;
1388 PMC_SLEEP_STATE SleepType;
1389 EFI_BOOT_MODE BootMode;
1390
1391 PeiServicesGetBootMode (&BootMode);
1392
1393 Status = IsRecoveryMode ();
1394 if (Status == EFI_SUCCESS) {
1395 BootMode = BOOT_IN_RECOVERY_MODE;
1396 Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
1397 ASSERT_EFI_ERROR (Status);
1398 } else {
1399 if (Status == EFI_UNSUPPORTED) {
1400 BootMode = BOOT_WITH_DEFAULT_SETTINGS;
1401 }
1402
1403 SleepType = PmcGetSleepTypeAfterWake ();
1404 if (SleepType != PmcNotASleepState) {
1405 if (!PmcIsPowerFailureDetected () &&
1406 PmcIsRtcBatteryGood ()) {
1407 switch (SleepType) {
1408 case PmcS3SleepState:
1409 BootMode = BOOT_ON_S3_RESUME;
1410 break;
1411 case PmcS4SleepState:
1412 BootMode = BOOT_ON_S4_RESUME;
1413 break;
1414 case PmcS5SleepState:
1415 BootMode = BOOT_ON_S5_RESUME;
1416 break;
1417 default:
1418 break;
1419 }
1420 } else {
1421 ///
1422 /// Clear Wake Status and Sleep Type
1423 ///
1424 PmcClearWakeStatus ();
1425 PmcSetSleepState (PmcInS0State);
1426 }
1427 }
1428
1429 DEBUG ((DEBUG_INFO, "Check Cmos Battery Status\n"));
1430 if (!PmcIsRtcBatteryGood()) {
1431 ///
1432 /// Report RTC battery failure
1433 ///
1434 DEBUG ((DEBUG_ERROR, "RTC Power failure !! Could be due to a weak or missing battery.\n"));
1435
1436 DEBUG ((DEBUG_ERROR, "BootMode is set to BOOT_WITH_DEFAULT_SETTINGS\n"));
1437
1438 BootMode = BOOT_WITH_DEFAULT_SETTINGS;
1439 }
1440 }
1441 PeiServicesSetBootMode (BootMode);
1442
1443 #ifdef CAPSULE_FLAG
1444 ///
1445 /// Register notify to update BootMode later
1446 ///
1447 Status = PeiServicesNotifyPpi (&mBootModeNotifyList);
1448 #else
1449 Status = PlatformInitPreMemUpdateBootMode (GetPeiServicesTablePointer (), NULL, NULL);
1450 #endif
1451 ASSERT_EFI_ERROR (Status);
1452
1453 return ;
1454 }
1455
1456
1457 /**
1458 Check to see the overclocking is enabled or not
1459
1460 @retval OverclockingEnabledStatus TRUE means overclocking is enabled
1461 FALSE means overclocking is disabled
1462 **/
1463 BOOLEAN
1464 IsOverclockingEnabled (
1465 VOID
1466 )
1467 {
1468 EFI_STATUS Status;
1469 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
1470 UINTN VarSize;
1471 CPU_SETUP CpuSetup;
1472 BOOLEAN OverclockingEnabledStatus;
1473
1474 OverclockingEnabledStatus = FALSE;
1475
1476 Status = PeiServicesLocatePpi (
1477 &gEfiPeiReadOnlyVariable2PpiGuid,
1478 0,
1479 NULL,
1480 (VOID **) &PeiReadOnlyVarPpi
1481 );
1482 if (Status == EFI_SUCCESS) {
1483 VarSize = sizeof (CPU_SETUP);
1484 Status = PeiReadOnlyVarPpi->GetVariable (
1485 PeiReadOnlyVarPpi,
1486 L"CpuSetup",
1487 &gCpuSetupVariableGuid,
1488 NULL,
1489 &VarSize,
1490 &CpuSetup
1491 );
1492 if (Status == EFI_SUCCESS) {
1493 if (CpuSetup.OverclockingSupport != 0) {
1494 OverclockingEnabledStatus = TRUE;
1495 }
1496 }
1497 }
1498
1499 return OverclockingEnabledStatus;
1500 }
1501
1502
1503 /**
1504 Create Fast Boot HOB
1505
1506 @param[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
1507
1508 @retval EFI_SUCCESS The function completes successfully
1509 @retval others
1510 **/
1511 EFI_STATUS
1512 EFIAPI
1513 CreateFastBootHob (
1514 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices
1515 )
1516 {
1517 EFI_STATUS Status;
1518 UINTN VarSize;
1519 EFI_BOOT_MODE BootMode;
1520 FAST_BOOT_FUNCTION_ENABLED_HOB *FastBootFunctionEnabledHob;
1521 FAST_BOOT_EXCEPTION_INFO_HOB *FastBootExceptionInfoHob;
1522
1523 if (IsFastBootEnabled ()) {
1524 ///
1525 /// If Fast Boot is enabled, create the FAST_BOOT_FUNCTION_ENABLED_HOB for other modules' reference.
1526 ///
1527 Status = PeiServicesCreateHob (
1528 EFI_HOB_TYPE_GUID_EXTENSION,
1529 sizeof (FAST_BOOT_FUNCTION_ENABLED_HOB),
1530 (VOID **) &FastBootFunctionEnabledHob
1531 );
1532 if (!EFI_ERROR (Status)) {
1533 FastBootFunctionEnabledHob->Header.Name = gFastBootFunctionEnabledHobGuid;
1534 FastBootFunctionEnabledHob->FastBootEnabled = TRUE;
1535 } else {
1536 return Status;
1537 }
1538 ///
1539 /// When RTC battery is drained (RTC power loss) or Secondary NvRam content is cleared (via jumper short), this bit will get set.
1540 /// This is the Fast Boot Exception Type 2.
1541 ///
1542 if (!PmcIsRtcBatteryGood ()) {
1543 Status = PeiServicesCreateHob (
1544 EFI_HOB_TYPE_GUID_EXTENSION,
1545 sizeof (FAST_BOOT_EXCEPTION_INFO_HOB),
1546 (VOID **) &FastBootExceptionInfoHob
1547 );
1548 if (!EFI_ERROR (Status)) {
1549 FastBootExceptionInfoHob->Header.Name = gFastBootExceptionInfoHobGuid;
1550 FastBootExceptionInfoHob->FbExceptionType = ExceptionType2;
1551 FastBootExceptionInfoHob->FbExceptionCategory = ContentLost;
1552 } else {
1553 return Status;
1554 }
1555 }
1556 ///
1557 /// Check the EFI Globally-Defined variable which is nonexistent right after updating BIOS, to determine if BIOS was just updated.
1558 ///
1559 Status = VariableServices->GetVariable (
1560 VariableServices,
1561 L"ConOut",
1562 &gEfiGlobalVariableGuid,
1563 NULL,
1564 &VarSize,
1565 NULL
1566 );
1567 if (Status == EFI_NOT_FOUND) {
1568 PeiServicesGetBootMode (&BootMode);
1569 Status = PrioritizeBootMode (&BootMode, BOOT_WITH_FULL_CONFIGURATION);
1570 if (!EFI_ERROR (Status)) {
1571 Status = PeiServicesSetBootMode (BootMode);
1572 }
1573 Status = PeiServicesCreateHob (
1574 EFI_HOB_TYPE_GUID_EXTENSION,
1575 sizeof (FAST_BOOT_EXCEPTION_INFO_HOB),
1576 (VOID **) &FastBootExceptionInfoHob
1577 );
1578 if (!EFI_ERROR (Status)) {
1579 FastBootExceptionInfoHob->Header.Name = gFastBootExceptionInfoHobGuid;
1580 FastBootExceptionInfoHob->FbExceptionType = ExceptionType2;
1581 FastBootExceptionInfoHob->FbExceptionCategory = FirmwareUpdate;
1582 } else {
1583 return Status;
1584 }
1585 }
1586 ///
1587 /// If overclocking is enabled, then BIOS shall switch back to Full Boot mode
1588 ///
1589 if (IsOverclockingEnabled ()) {
1590 Status = PeiServicesCreateHob (
1591 EFI_HOB_TYPE_GUID_EXTENSION,
1592 sizeof (FAST_BOOT_EXCEPTION_INFO_HOB),
1593 (VOID **) &FastBootExceptionInfoHob
1594 );
1595 if (!EFI_ERROR (Status)) {
1596 FastBootExceptionInfoHob->Header.Name = gFastBootExceptionInfoHobGuid;
1597 FastBootExceptionInfoHob->FbExceptionType = ExceptionType2;
1598 FastBootExceptionInfoHob->FbExceptionCategory = SpecialBoot;
1599 } else {
1600 return Status;
1601 }
1602 }
1603 }
1604 return EFI_SUCCESS;
1605 }
1606
1607
1608 /**
1609 Parse the status registers for figuring out the wake-up event and save it into
1610 an GUID HOB which will be referenced later.
1611
1612 @param[out] WakeUpType Updates the wakeuptype based on the status registers
1613 **/
1614 VOID
1615 GetWakeupEventAndSaveToHob (
1616 OUT UINT8 *WakeUpType
1617 )
1618 {
1619 UINT16 Pm1Sts;
1620 UINTN Gpe0Sts;
1621 UINTN Gpe0PmeSts;
1622 UINTN Gpe0RiSts;
1623 UINT16 AcpiBase;
1624
1625 DEBUG ((DEBUG_INFO, "GetWakeupEventAndSaveToHob ()\n"));
1626
1627 Gpe0Sts = 0;
1628 Gpe0RiSts = 0;
1629 Gpe0PmeSts = 0;
1630 AcpiBase = PmcGetAcpiBase ();
1631
1632 ///
1633 /// Read the ACPI registers
1634 ///
1635 Pm1Sts = IoRead16 (AcpiBase + R_ACPI_IO_PM1_STS);
1636 Gpe0Sts = IoRead32 (AcpiBase + R_CNL_PCH_ACPI_IO_GPE0_STS_127_96);
1637 Gpe0RiSts = Gpe0Sts & B_ACPI_IO_GPE0_STS_127_96_RI;
1638 Gpe0PmeSts = Gpe0Sts & B_ACPI_IO_GPE0_STS_127_96_PME;
1639
1640 DEBUG ((DEBUG_INFO, "Gpe0Sts is: %02x\n", Gpe0Sts));
1641 DEBUG ((DEBUG_INFO, "ACPI Wake Status Register: %04x\n", Pm1Sts));
1642
1643 ///
1644 /// Figure out the wake-up event
1645 ///
1646 if ((Pm1Sts & B_ACPI_IO_PM1_EN_PWRBTN) != 0 ) {
1647 *WakeUpType = SystemWakeupTypePowerSwitch;
1648 } else if ((Pm1Sts & B_ACPI_IO_PM1_STS_WAK) != 0) {
1649 if (Gpe0PmeSts != 0) {
1650 *WakeUpType = SystemWakeupTypePciPme;
1651 } else if (Gpe0RiSts != 0) {
1652 *WakeUpType = SystemWakeupTypeModemRing;
1653 } else if (Gpe0Sts != 0) {
1654 *WakeUpType = SystemWakeupTypeOther;
1655 } else {
1656 *WakeUpType = SystemWakeupTypeOther;
1657 }
1658 } else if ((Pm1Sts & B_ACPI_IO_PM1_STS_RTC) != 0) {
1659 *WakeUpType = SystemWakeupTypeApmTimer;
1660 } else {
1661 *WakeUpType = SystemWakeupTypeOther;
1662 }
1663
1664
1665 DEBUG ((DEBUG_INFO, "GetWakeupEventAndSaveToHob : WakeUpType %x\n", *WakeUpType));
1666 }
1667
1668
1669
1670
1671 //@todo it should be performed in Si Pkg.
1672 /**
1673 Provide hard reset PPI service.
1674 To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
1675
1676 @param[in] PeiServices General purpose services available to every PEIM.
1677
1678 @retval Not return System reset occured.
1679 @retval EFI_DEVICE_ERROR Device error, could not reset the system.
1680 **/
1681 EFI_STATUS
1682 EFIAPI
1683 PchReset(
1684 IN CONST EFI_PEI_SERVICES **PeiServices
1685 )
1686 {
1687 DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
1688 IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
1689
1690 CpuDeadLoop ();
1691
1692 ///
1693 /// System reset occured, should never reach at this line.
1694 ///
1695 ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
1696
1697 return EFI_DEVICE_ERROR;
1698 }
1699
1700 //@todo it should be moved to Si Pkg.
1701 /**
1702 Early Platform PCH initialization
1703 **/
1704 VOID
1705 EarlyPlatformPchInit (
1706 VOID
1707 )
1708 {
1709 UINT8 Data8;
1710 UINT8 TcoRebootHappened;
1711 TCO_WDT_HOB *TcoWdtHobPtr;
1712 EFI_STATUS Status;
1713
1714 ///
1715 /// Read the Second TO status bit
1716 ///
1717 Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
1718 if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
1719 TcoRebootHappened = 1;
1720 DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
1721 } else {
1722 TcoRebootHappened = 0;
1723 }
1724
1725 ///
1726 /// Create HOB
1727 ///
1728 Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof (TCO_WDT_HOB), (VOID **) &TcoWdtHobPtr);
1729 if (!EFI_ERROR (Status)) {
1730 TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
1731 TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
1732 }
1733
1734 ///
1735 /// Clear the Second TO status bit
1736 ///
1737 IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);
1738 }
1739
1740 /**
1741 Set the state to go after G3
1742
1743 @dot
1744 digraph G {
1745 subgraph cluster_c0 {
1746 node [shape = box];
1747 b1[label="EcForceResetAfterAcRemoval ()" fontsize=12 style=filled color=lightblue];
1748 b2[label="Force S5" fontsize=12 style=filled color=lightblue];
1749 b3[label="Force S0" fontsize=12 style=filled color=lightblue];
1750
1751 node [shape = ellipse];
1752 e1[label="Start" fontsize=12 style=filled color=lightblue];
1753 e2[label="End" fontsize=12 style=filled color=lightblue];
1754
1755 node [shape = diamond,style=filled,color=lightblue];
1756 d1[label="GetVariable\nFroceResetAfterAcRemoval" fontsize=12];
1757 d2[label="EcPresent" fontsize=12];
1758 d3[label="ForceResetAfterAcRemoval" fontsize=12];
1759 d4[label="GetVariable\nStateAfterG3" fontsize=12];
1760 d5[label="StateAfterG3" fontsize=12];
1761
1762 label = "SetTheStateToGoAfterG3 Flow"; fontsize=15; fontcolor=black; color=lightblue;
1763 e1 -> d1
1764 d1 -> d2 [label="Success" fontsize=9]
1765 d1 -> d4 [label="Fail" fontsize=9]
1766 d2 -> b1 [label="Yes" fontsize=9]
1767 b1 -> d3
1768 d2 -> d3 [label="No" fontsize=9]
1769 d3 -> b3 [label="Yes" fontsize=9]
1770 d3 -> d4 [label="No" fontsize=9]
1771 d4 -> d5 [label="Success" fontsize=9]
1772 d4 -> b3 [label="Fail" fontsize=9]
1773 d5 -> b2 [label="Set" fontsize=9]
1774 d5 -> b3 [label="Clear" fontsize=9]
1775 b3 -> e2
1776 }
1777 }
1778 @enddot
1779
1780 @param[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
1781 **/
1782 VOID
1783 SetTheStateToGoAfterG3 (
1784 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices
1785 )
1786 {
1787 EFI_STATUS Status;
1788 UINTN VariableSize;
1789 UINT8 ForceResetAfterAcRemovalVar;
1790 UINT8 StateAfterG3;
1791 PCH_SETUP PchSetup;
1792
1793 ForceResetAfterAcRemovalVar = 0;
1794 StateAfterG3 = 0;
1795
1796
1797 VariableSize = sizeof (PCH_SETUP);
1798 Status = VariableServices->GetVariable (
1799 VariableServices,
1800 L"PchSetup",
1801 &gPchSetupVariableGuid,
1802 NULL,
1803 &VariableSize,
1804 &PchSetup
1805 );
1806 if (!EFI_ERROR(Status)) {
1807 StateAfterG3 = PchSetup.StateAfterG3;
1808 }
1809
1810 if ((StateAfterG3 == 1) && (ForceResetAfterAcRemovalVar == 0)) {
1811 PmcSetPlatformStateAfterPowerFailure (1); // AfterG3 = S5
1812 } else {
1813 PmcSetPlatformStateAfterPowerFailure (0); // AfterG3 = S0
1814 }
1815 }
1816
1817
1818 // @todo: It should be moved Policy Init.
1819 /**
1820 Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
1821
1822 @param[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
1823 **/
1824 VOID
1825 PlatformPchInit (
1826 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices
1827 )
1828 {
1829
1830 ///
1831 /// Enable the LPC I/O decoding for 0x6A0~0x6A7 as EC's extra I/O port, where 0x6A0 is the Data port
1832 /// and 0x6A4 is the Command/Status port.
1833 ///
1834 if (PcdGetBool (PcdEcPresent)) {
1835 PchLpcGenIoRangeSet (PcdGet16 (PcdEcExtraIoBase), 0x10); //PTLMOD+
1836 }
1837 #ifdef SIO_NCT667F
1838 else {
1839 /// Added Nuvoton HW monitor IO address.
1840 PchLpcGenIoRangeSet (PcdGet16 (PcdNct6776fHwMonBase), 0x10);
1841 }
1842 #endif //SIO_NCT667F
1843
1844 }
1845
1846
1847 /**
1848 Run this function after SaPolicy PPI to be installed.
1849
1850 @param[in] PeiServices General purpose services available to every PEIM.
1851 @param[in] NotifyDescriptor Notify that this module published.
1852 @param[in] Ppi PPI that was installed.
1853
1854 @retval EFI_SUCCESS The function completed successfully.
1855 **/
1856 EFI_STATUS
1857 EFIAPI
1858 SiPreMemPolicyPpiNotifyCallback (
1859 IN CONST EFI_PEI_SERVICES **PeiServices,
1860 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
1861 IN VOID *Ppi
1862 )
1863 {
1864 EFI_STATUS Status;
1865
1866 ///
1867 /// Platform specific programming. It may have Chipset, EC or some platform specific
1868 /// programming here.
1869 ///
1870 Status = PlatformSpecificInitPreMem ();
1871 ASSERT_EFI_ERROR (Status);
1872
1873 return Status;
1874 }
1875
1876
1877 /**
1878 Run this function after Wdt PPI to be installed.
1879
1880 @param[in] PeiServices General purpose services available to every PEIM.
1881 @param[in] NotifyDescriptor Notify that this module published.
1882 @param[in] Ppi PPI that was installed.
1883
1884 @retval EFI_SUCCESS The function completed successfully.
1885 **/
1886 EFI_STATUS
1887 EFIAPI
1888 WdtAppPpiNotifyCallback (
1889 IN CONST EFI_PEI_SERVICES **PeiServices,
1890 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
1891 IN VOID *Ppi
1892 )
1893 {
1894 EFI_STATUS Status;
1895 WDT_PPI *WdtPei;
1896
1897 WdtPei = (WDT_PPI *) Ppi;
1898
1899 Status = PeiWdtApp (WdtPei);
1900 ASSERT_EFI_ERROR (Status);
1901
1902 return Status;
1903 }
1904
1905
1906 /**
1907 Build a HOB for debug configure data.
1908
1909 The DebugConfigHob is built by platform code and consumed by PeiDxeSmmDebugPrintErrorLevelLib and
1910 PeiDxeSmmSerialPortParameterLib library instances.
1911
1912 @param[in] DebugConfigData A pointer to the DEBUG_CONFIG_DATA.
1913
1914 **/
1915 VOID
1916 BuildDebugConfigDataHob (
1917 IN DEBUG_CONFIG_DATA *DebugConfigData
1918 )
1919 {
1920 DEBUG_CONFIG_DATA_HOB *DebugConfigDataHob;
1921
1922 DebugConfigDataHob = BuildGuidHob (&gDebugConfigHobGuid, sizeof (DEBUG_CONFIG_DATA_HOB));
1923 ASSERT (DebugConfigDataHob != NULL);
1924 if (DebugConfigDataHob == NULL) {
1925 DEBUG ((DEBUG_ERROR, "Build Debug Config Hob failed!\n"));
1926 return;
1927 }
1928
1929 DebugConfigDataHob->SerialDebug = DebugConfigData->SerialDebug;
1930 DebugConfigDataHob->SerialDebugBaudRate = DebugConfigData->SerialDebugBaudRate;
1931 DebugConfigDataHob->RamDebugInterface = (DebugConfigData->RamDebugInterface == 1 && FeaturePcdGet (PcdRamDebugEnable)) ? 1 : 0;
1932 DebugConfigDataHob->UartDebugInterface = (DebugConfigData->UartDebugInterface == 1 && FeaturePcdGet (PcdSerialPortEnable)) ? 1 : 0;
1933 DebugConfigDataHob->Usb3DebugInterface = (DebugConfigData->Usb3DebugInterface == 1 && FeaturePcdGet (PcdUsb3SerialStatusCodeEnable)) ? 1 : 0;
1934 DebugConfigDataHob->SerialIoDebugInterface = (DebugConfigData->SerialIoDebugInterface == 1 && FeaturePcdGet (PcdSerialIoUartEnable)) ? 1 : 0;
1935 DebugConfigDataHob->TraceHubDebugInterface = (DebugConfigData->TraceHubDebugInterface == 1 && FeaturePcdGet (PcdTraceHubEnable)) ? 1 : 0;
1936 }
1937
1938 /**
1939 This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
1940
1941 @dot
1942 digraph G {
1943 subgraph cluster_c0 {
1944 node [shape = box];
1945 b1[label="FlashMapInit ()" fontsize=12 style=filled color=lightblue];
1946 b2[label="ConfigurePlatformClocks ()" fontsize=12 style=filled color=lightblue];
1947 b3[label="Notify Smbus2 PPI" fontsize=12 style=filled color=lightblue];
1948 b4[label="BuildGuidDataHob ()" fontsize=12 style=filled color=lightblue];
1949 b5[label="PlatformVariableInit ()" fontsize=12 style=filled color=lightblue];
1950 b6[label="DetectWakeReason ()" fontsize=12 style=filled color=lightblue];
1951 b7[label="DetectBootMode ()" fontsize=12 style=filled color=lightblue];
1952 b8[label="Get SystemConfiguration variable" fontsize=12 style=filled color=lightblue];
1953 b9[label="Set the system configuration\n to FirmwareConfiguration" fontsize=12 style=filled color=lightblue];
1954 b10[label="Set the system configuration\n to production mode" fontsize=12 style=filled color=lightblue];
1955 b11[label="PeiPolicyInitPreMem ()" fontsize=12 style=filled color=lightblue];
1956 b12[label="BoardInit ()\n to configure GPIO and SIO" fontsize=12 style=filled color=lightblue];
1957 b13[label="CreateFastBootHob ()" fontsize=12 style=filled color=lightblue];
1958 b14[label="GetWakeupEventAndSaveToHob ()" fontsize=12 style=filled color=lightblue];
1959 b15[label="CreateAttemptUsbFirstHotkeyInfoHob ()" fontsize=12 style=filled color=lightblue];
1960 b16[label="Notify Wdt PPI" fontsize=12 style=filled color=lightblue];
1961 b17[label="Notify gSiPreMemPolicyPpiGuid PPI" fontsize=12 style=filled color=lightblue];
1962 b18[label="PlatformPchInit ()" fontsize=12 style=filled color=lightblue];
1963 b19[label="SetTheStateToGoAfterG3 ()" fontsize=12 style=filled color=lightblue];
1964 b20[label="Clear all pending SMI" fontsize=12 style=filled color=lightblue];
1965 b21[label="Install Pre Memory PPIs" fontsize=12 style=filled color=lightblue];
1966
1967 node [shape = ellipse];
1968 e1[label="Start" fontsize=12 style=filled color=lightblue];
1969 e2[label="End" fontsize=12 style=filled color=lightblue];
1970
1971 node [shape = diamond,style=filled,color=lightblue];
1972 d1[label="Locate Smbus2 PPI" fontsize=12];
1973 d2[label="Is status success?" fontsize=12];
1974
1975 label = "PlatformInitPreMem Flow"; fontsize=15; fontcolor=black; color=lightblue;
1976 e1 -> b1
1977 b1 -> d1
1978 d1 -> b2 [label="Success" fontsize=9]
1979 d1 -> b3 [label="Fail" fontsize=9]
1980 d5 -> b4 [label="Present" fontsize=9]
1981 b4 -> b5
1982 b5 -> b6
1983 b6 -> b7
1984 b7 -> b8
1985 b8 -> d2
1986 d2 -> b9 [label="Yes" fontsize=9]
1987 d2 -> b10 [label="No" fontsize=9]
1988 b9 -> b11
1989 b10 -> b11
1990 b11 -> b12
1991 b12 -> b13
1992 b13 -> b14
1993 b14 -> b15
1994 b15 -> b16
1995 b16 -> b17
1996 b17 -> b18
1997 b18 -> b19
1998 b19 -> b20
1999 b20 -> b21
2000 b21 -> e2
2001 }
2002 }
2003 @enddot
2004
2005 @param[in] PeiServices Pointer to PEI Services Table.
2006 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
2007 caused this function to execute.
2008 @param[in] Ppi Pointer to the PPI data associated with this function.
2009
2010 @retval EFI_SUCCESS The function completes successfully
2011 @retval others
2012 **/
2013 EFI_STATUS
2014 EFIAPI
2015 PlatformInitPreMem (
2016 IN CONST EFI_PEI_SERVICES **PeiServices,
2017 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
2018 IN VOID *Ppi
2019 )
2020 {
2021 EFI_STATUS Status;
2022 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
2023 EFI_BOOT_MODE BootMode;
2024 UINT64 McD0BaseAddress;
2025 UINT16 ABase;
2026 SETUP_DATA SystemConfiguration;
2027 UINTN VariableSize;
2028 UINT8 FwConfig;
2029 CHAR16 BiosVersion[40];
2030 CHAR16 ReleaseDate[20];
2031 CHAR16 ReleaseTime[20];
2032 UINT8 WakeupType;
2033 UINTN Size;
2034 PEI_BOARD_CONFIG_PCD_INIT BoardConfigPcdInitPreMem;
2035 UINT8 SynchDelay;
2036 DEBUG_CONFIG_DATA DebugConfigData;
2037 BOOLEAN IsFirstBoot = FALSE;
2038 UINT32 InitSetupVolVarAttr;
2039 UINT8 InitSetupFlag;
2040
2041 PostCode(PLATFORM_INIT_PREMEM_ENTRY);
2042
2043 if (PcdGetBool (PcdPlatformInitPreMem)) {
2044 return EFI_SUCCESS;
2045 }
2046
2047 VariableServices = (EFI_PEI_READ_ONLY_VARIABLE2_PPI *) Ppi;
2048
2049 Status = GetBiosVersionDateTime (BiosVersion, ReleaseDate, ReleaseTime);
2050 Size = sizeof (BiosVersion);
2051 PcdSetPtrS (PcdBiosVersion, &Size, &BiosVersion);
2052 Size = sizeof (ReleaseDate);
2053 PcdSetPtrS (PcdBiosVersion, &Size, &ReleaseDate);
2054 Size = sizeof (ReleaseTime);
2055 PcdSetPtrS (PcdBiosVersion, &Size, &ReleaseTime);
2056 //
2057 // Updates the wakeupType which will be used to update the same in Smbios table 01
2058 //
2059 GetWakeupEventAndSaveToHob (&WakeupType);
2060 PcdSet8S (PcdWakeupType, WakeupType);
2061
2062 Status = PcdSetBoolS (PcdPlatformInitPreMem, TRUE);
2063 ASSERT_EFI_ERROR (Status);
2064
2065 //
2066 // Init Board Config Pcd.
2067 //
2068 BoardConfigPcdInitPreMem = (PEI_BOARD_CONFIG_PCD_INIT) (UINTN) PcdGet32 (PcdFuncBoardConfigInitPreMem);
2069 ASSERT (BoardConfigPcdInitPreMem != NULL);
2070
2071 if (BoardConfigPcdInitPreMem != NULL) {
2072 Status = BoardConfigPcdInitPreMem (NULL);
2073 ASSERT_EFI_ERROR (Status);
2074 }
2075
2076 DetectBootMode ();
2077 PeiServicesGetBootMode (&BootMode);
2078 //
2079 // Make sure the Variable "Setup" and "(RC)Setup" have been initialized in boot modes where it may not be.
2080 //
2081 if ((BootMode != BOOT_WITH_MINIMAL_CONFIGURATION) &&
2082 (BootMode != BOOT_ASSUMING_NO_CONFIGURATION_CHANGES) &&
2083 (BootMode != BOOT_ON_S5_RESUME) &&
2084 (BootMode != BOOT_ON_S4_RESUME) &&
2085 (BootMode != BOOT_ON_S3_RESUME)) {
2086 Status = PlatformVariableInit (PeiServices, NotifyDescriptor, Ppi);
2087 ASSERT_EFI_ERROR (Status);
2088 }
2089
2090 //
2091 // PatchConfigurationDataPreMem
2092 //
2093 Status = VariableServices->GetVariable (
2094 VariableServices,
2095 L"InitSetupVariable",
2096 &gSetupVariableGuid,
2097 &InitSetupVolVarAttr,
2098 &VariableSize,
2099 &InitSetupFlag
2100 );
2101 if (Status == EFI_NOT_FOUND) {
2102 IsFirstBoot = TRUE;
2103 }
2104
2105 if ((IsFirstBoot) || (BootMode == BOOT_WITH_DEFAULT_SETTINGS)) {
2106 Status = PeiServicesInstallPpi (mPatchConfigurationDataPreMemPpi);
2107 ASSERT_EFI_ERROR (Status);
2108 }
2109
2110 //
2111 // After PlatformVariableInit, the Variable "Setup" has been initialized.
2112 // Cache the Variable "Setup" here to boost performance.
2113 //
2114 Status = SetupDataCacheInit ();
2115
2116 VariableSize = sizeof (SETUP_DATA);
2117 Status = VariableServices->GetVariable (
2118 VariableServices,
2119 L"Setup",
2120 &gSetupVariableGuid,
2121 NULL,
2122 &VariableSize,
2123 &SystemConfiguration
2124 );
2125 if (EFI_ERROR (Status)) {
2126 DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
2127 FwConfig = 0;
2128 SynchDelay = 0;
2129 } else {
2130 FwConfig = SystemConfiguration.FirmwareConfiguration;
2131 SynchDelay = SystemConfiguration.AlternateModeSynchDelay;
2132 }
2133
2134
2135 DEBUG_CODE_BEGIN();
2136 VariableSize = sizeof (DEBUG_CONFIG_DATA);
2137 Status = VariableServices->GetVariable (
2138 VariableServices,
2139 L"DebugConfigData",
2140 &gDebugConfigVariableGuid,
2141 NULL,
2142 &VariableSize,
2143 &DebugConfigData
2144 );
2145 if (EFI_ERROR (Status)) {
2146 DEBUG ((DEBUG_ERROR, "Failed to get Debug Configuration data variable!\n"));
2147 } else {
2148 BuildDebugConfigDataHob (&DebugConfigData);
2149 }
2150 DEBUG_CODE_END();
2151
2152 if (SystemConfiguration.FastBoot == 0) {
2153 if (SynchDelay != 0) {
2154 MicroSecondDelay (SynchDelay * STALL_ONE_MILLI_SECOND * 100); // SynchDelay * 0.1s
2155 }
2156 }
2157 if ((PcdGetBool (PcdUsbcEcPdNegotiation)) && ((BootMode == BOOT_ON_S5_RESUME) |
2158 (BootMode == BOOT_ON_S4_RESUME) |
2159 (BootMode == BOOT_ON_S3_RESUME))) {
2160 }
2161 ///
2162 ///
2163 ///
2164 ///
2165
2166 //
2167 // Initialize Intel PEI Platform Policy
2168 //
2169 PeiPolicyInitPreMem (FwConfig);
2170
2171 ///
2172 /// Configure GPIO and SIO
2173 ///
2174 Status = BoardInitPreMem ();
2175 ASSERT_EFI_ERROR (Status);
2176
2177 Status = CreateFastBootHob (VariableServices);
2178 ASSERT_EFI_ERROR (Status);
2179
2180 Status = PeiServicesNotifyPpi (&mWdtPpiNotifyList);
2181 ASSERT_EFI_ERROR (Status);
2182
2183 Status = PeiServicesNotifyPpi (&mSiPreMemPolicyNotifyList);
2184 ASSERT_EFI_ERROR (Status);
2185
2186 ///
2187 /// Do basic PCH init
2188 ///
2189 PlatformPchInit (VariableServices);
2190
2191 ///
2192 /// Set what state (S0/S5) to go to when power is re-applied after a power failure (G3 state)
2193 ///
2194 SetTheStateToGoAfterG3 (VariableServices);
2195
2196 ABase = PmcGetAcpiBase ();
2197
2198 ///
2199 /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
2200 ///
2201 IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
2202 IoWrite32 (ABase + R_CNL_PCH_ACPI_IO_GPE0_EN_127_96, 0);
2203 ///----------------------------------------------------------------------------------
2204 ///
2205 /// BIOS should check the wake status before memory initialization to determine
2206 /// if ME has reset the system while the host was in a sleep state. If platform was not in a sleep state,
2207 /// BIOS should ensure a non-sleep exit path is taken by forcing an s5 exit.
2208 ///
2209 if (PmcGetSleepTypeAfterWake () == PmcNotASleepState) {
2210 PmcSetSleepState (PmcS5SleepState);
2211 }
2212
2213 Status = PeiServicesGetBootMode (&BootMode);
2214 ASSERT_EFI_ERROR (Status);
2215 if (BootMode == BOOT_ON_S3_RESUME) {
2216 //
2217 // A platform PEIM should enable R/W access to E/F segment in the S3 boot path
2218 // otherwise, this AP wakeup buffer can't be accessed during CPU S3 operation.
2219 //
2220 McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, 0);
2221 PciSegmentWrite8 (McD0BaseAddress + R_SA_PAM0, 0x30);
2222 PciSegmentWrite8 (McD0BaseAddress + R_SA_PAM5, 0x33);
2223 PciSegmentWrite8 (McD0BaseAddress + R_SA_PAM6, 0x33);
2224 }
2225
2226 ///
2227 /// Install Pre Memory PPIs
2228 ///
2229 Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
2230 ASSERT_EFI_ERROR (Status);
2231
2232 PostCode(PLATFORM_INIT_PREMEM_EXIT);
2233
2234 return Status;
2235 }
2236
2237
2238 /**
2239 Platform Init before memory PEI module entry point
2240
2241 @param[in] FileHandle Not used.
2242 @param[in] PeiServices General purpose services available to every PEIM.
2243
2244 @retval EFI_SUCCESS The function completes successfully
2245 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
2246 **/
2247 EFI_STATUS
2248 EFIAPI
2249 PlatformInitPreMemEntryPoint (
2250 IN EFI_PEI_FILE_HANDLE FileHandle,
2251 IN CONST EFI_PEI_SERVICES **PeiServices
2252 )
2253 {
2254 EFI_STATUS Status;
2255 BIOS_ID_IMAGE BiosIdImage;
2256
2257 ///@todo this functionality should be moved to Si Pkg.
2258 ///
2259 /// Allocate an initial buffer from heap for debugger use
2260 ///
2261 DEBUG_CODE(DsAllocation (););
2262
2263 Status = GetBiosId (&BiosIdImage);
2264
2265 if (Status == EFI_SUCCESS) {
2266 DEBUG ((DEBUG_INFO, "+==================================================+\n"));
2267 DEBUG ((DEBUG_INFO, "| BIOS version [%s] |\n", &BiosIdImage.BiosIdString));
2268 DEBUG ((DEBUG_INFO, "+==================================================+\n"));
2269 }
2270
2271 //
2272 // Initialize Nvram to default when checksum computation is failed
2273 //
2274 SecondaryNvRamInit ();
2275 ///
2276 /// Install Stall PPI
2277 ///
2278 Status = InstallStallPpi();
2279 ASSERT_EFI_ERROR (Status);
2280
2281 ///@todo it should be moved to Si Pkg.
2282 ///
2283 /// Do Early PCH init
2284 ///
2285 EarlyPlatformPchInit ();
2286
2287 ///
2288 /// Performing PlatformInitPreMem after PeiReadOnlyVariable2 PPI produced
2289 ///
2290 Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
2291
2292 ///
2293 /// After code reorangized, memorycallback will run because the PPI is already
2294 /// installed when code run to here, it is supposed that the InstallEfiMemory is
2295 /// done before.
2296 ///
2297 Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
2298
2299 return Status;
2300 }
DetectBootMode
VOID DetectBootMode(VOID)
Detect boot mode.
Definition: PlatformInitPreMem.c:1383
PeiPlatformRecoveryLib.h
This library provides platform recovery module.
SetTheStateToGoAfterG3
VOID SetTheStateToGoAfterG3(IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Set the state to go after G3.
Definition: PlatformInitPreMem.c:1783
MemoryDiscoveredPpiNotifyCallback
EFI_STATUS MemoryDiscoveredPpiNotifyCallback(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Install Firmware Volume Hob's once there is main memory.
Definition: PlatformInitPreMem.c:748
SiPreMemPolicyPpiNotifyCallback
EFI_STATUS SiPreMemPolicyPpiNotifyCallback(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after SaPolicy PPI to be installed.
Definition: PlatformInitPreMem.c:1858
IsOverclockingEnabled
BOOLEAN IsOverclockingEnabled(VOID)
Check to see the overclocking is enabled or not.
Definition: PlatformInitPreMem.c:1464
GetCsmControlStatus
VOID GetCsmControlStatus(VOID)
figure out the CSM configuration and post it to PcdCsmEnable.
Definition: PlatformInitPreMem.c:644
InitializeRecovery
EFI_STATUS InitializeRecovery(VOID)
Provide the functionality of the recovery module.
GetRtc3Address
UINT8 GetRtc3Address(VOID)
Get RTC 3 Address.
NeedResetBoardDefaultVariableHob
BOOLEAN NeedResetBoardDefaultVariableHob(VOID)
Check to reset setup variable and Clear CMOS 0E when CMOS content is bad.
PlatformInitPreMemUpdateBootMode
EFI_STATUS PlatformInitPreMemUpdateBootMode(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Interface)
Definition: PlatformInitPreMem.c:1253
BoardConfigLib.h
Function prototype of BoardConfigLib.
IsTimeOutOccurred
BOOLEAN IsTimeOutOccurred(VOID)
Check Fast Boot 30-second WDT (TCO Timer) timeout has occurred.
Definition: PlatformInitPreMem.c:924
mBootModePriority
GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE mBootModePriority[]
Priority of our boot modes, highest priority first.
Definition: PlatformInitPreMem.c:142
PlatformNvRamHookLib.h
Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NV...
PlatformInitPreMemEntryPoint
EFI_STATUS PlatformInitPreMemEntryPoint(IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init before memory PEI module entry point.
Definition: PlatformInitPreMem.c:2249
CheckOddParity
BOOLEAN CheckOddParity(IN UINT8 Value)
Check if the value is of ODD parity.
Definition: PlatformInitPreMem.c:1169
EarlyPlatformPchInit
VOID EarlyPlatformPchInit(VOID)
Early Platform PCH initialization.
Definition: PlatformInitPreMem.c:1705
IsPreviousBootSuccessful
BOOLEAN IsPreviousBootSuccessful(VOID)
Check Boot Flag Status to determine if previous boot was successful.
Definition: PlatformInitPreMem.c:972
PchReset
EFI_STATUS PchReset(IN CONST EFI_PEI_SERVICES **PeiServices)
Provide hard reset PPI service.
Definition: PlatformInitPreMem.c:1683
IsFastBootEnabled
BOOLEAN IsFastBootEnabled(VOID)
Check fast boot is enabled or not.
Definition: PlatformInitPreMem.c:879
PlatformInitPreMem
EFI_STATUS PlatformInitPreMem(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced.
Definition: PlatformInitPreMem.c:2015
Platform.h
This header file provides platform specific definitions used by other modules for platform specific i...
PeiPolicyInitLib.h
Header file for the PolicyInitPei Library.
IsPowerButtonOverride
BOOLEAN IsPowerButtonOverride(VOID)
Check if this system boot is due to 4sec power button override has occurred.
Definition: PlatformInitPreMem.c:946
OemSetup.h
OEM Specific Setup Variables and Structures.
GetBootFlagStatus
UINT8 GetBootFlagStatus(VOID)
Get Boot Flag Status.
PlatformPchInit
VOID PlatformPchInit(IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers.
Definition: PlatformInitPreMem.c:1825
WdtAppPpiNotifyCallback
EFI_STATUS WdtAppPpiNotifyCallback(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after Wdt PPI to be installed.
Definition: PlatformInitPreMem.c:1888
SecondaryNvRamInit
VOID SecondaryNvRamInit(VOID)
Load CMOS default on RTC battery failure.
DsAllocation.h
RESET_GENERATOR_PORT
#define RESET_GENERATOR_PORT
Reset Generator I/O Port.
Definition: PlatformInitPreMem.c:130
GetSimpleBootFlag
UINT8 GetSimpleBootFlag(VOID)
Get simple boot flag.
Definition: PlatformInitPreMem.c:1195
UpdateBootFlagStatus
VOID UpdateBootFlagStatus(UINT8 BootStatus)
Update Boot Flag Status.
CreateFastBootHob
EFI_STATUS CreateFastBootHob(IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Create Fast Boot HOB.
Definition: PlatformInitPreMem.c:1513
SetCacheMtrr
VOID SetCacheMtrr(VOID)
Set Cache Mtrr.
Definition: PlatformInitPreMem.c:472
PeiPlatformLib.h
PlatformBoardConfig.h
Header file for Platform Boards Configurations.
PlatformBoardId.h
Defines Platform BoardIds.
EcMiscLib.h
EC miscellaneous library functions.
Setup.h
IsBootWithNoChange
BOOLEAN IsBootWithNoChange(VOID)
Query PCH to determine if Intrusion Detection set.
Definition: PlatformInitPreMem.c:1030
MultiPlatSupportLib.h
PeiPolicyInitPreMem
VOID PeiPolicyInitPreMem(IN UINT8 FirmwareConfiguration)
Initialize Intel PEI Platform Policy.
PeiWdtApp
EFI_STATUS PeiWdtApp(IN WDT_PPI *WdtPei)
turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT ...
BuildDebugConfigDataHob
VOID BuildDebugConfigDataHob(IN DEBUG_CONFIG_DATA *DebugConfigData)
Build a HOB for debug configure data.
Definition: PlatformInitPreMem.c:1916
EcCommands.h
PlatformVariableInit
EFI_STATUS PlatformVariableInit(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Interface)
Perform the default variable initializations after variable service is ready.
Definition: PlatformInitPreMem.c:327
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
MEMORY_MAP
If the debugger branch trace/data store debug feature is enabled This is an optional debug feature as...
Definition: PlatformInitPreMem.c:112
PlatformPostCode.h
GetWakeupEventAndSaveToHob
VOID GetWakeupEventAndSaveToHob(OUT UINT8 *WakeUpType)
Parse the status registers for figuring out the wake-up event and save it into an GUID HOB which will...
Definition: PlatformInitPreMem.c:1615
SetupVariable.h
TcoWdtHob.h
PrioritizeBootMode
EFI_STATUS PrioritizeBootMode(IN OUT EFI_BOOT_MODE *CurrentBootMode, IN EFI_BOOT_MODE NewBootMode)
Given the current boot mode, and a proposed new boot mode, determine which has priority.
Definition: PlatformInitPreMem.c:1118
PeiWdtAppLib.h
PEI WDT App library definitions.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformNvRamHookLib.h Source File

PlatformNvRamHookLib.h
Go to the documentation of this file.
1 /** @file
2
3 Platform Nv RAM Hook Library Header Definition which will oprovide the absraction
4 to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright (c) 2017 Intel Corporation. All rights reserved
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _PLATFORM_NVRAM_HOOK_LIB_H_
38 #define _PLATFORM_NVRAM_HOOK_LIB_H_
39
40 #ifndef DEFAULT_VALUE
41 #define DEFAULT_VALUE 0
42 #endif
43
44 /**
45 Test to see if Checksum is bad.
46
47 @retval TRUE - Checksum content is bad
48 FALSE - Checksum content is good
49 **/
50 BOOLEAN
51 IsChecksumBad (
52 VOID
53 );
54
55 /**
56 Clear Diagnostic Status.
57 **/
58 VOID
59 ClearDiagnosticStatus (
60 VOID
61 );
62
63 /**
64 Check to reset setup variable and Clear CMOS 0E when CMOS content is bad
65
66 @retval Flag to Reset Setup variable : TRUE - When CMOS content is bad
67 FALSE - Otherwise
68 **/
69 BOOLEAN
70 NeedResetBoardDefaultVariableHob(
71 VOID
72 );
73
74 /**
75 Load CMOS default on RTC battery failure.
76 **/
77 VOID
78 SecondaryNvRamInit(
79 VOID
80 );
81
82 /**
83 Get Boot Flag Status.
84
85 @retval Value of current boot status
86 **/
87 UINT8
88 GetBootFlagStatus(
89 VOID
90 );
91
92 /**
93 Update Boot Flag Status.
94
95 @param [in] BootStatus Current Boot value which to be updated.
96 **/
97 VOID
98 UpdateBootFlagStatus(
99 UINT8 BootStatus
100 );
101
102 /**
103 Get RTC 3 Address.
104
105 @retval Current value of RTC 3 Address
106 **/
107 UINT8
108 GetRtc3Address(
109 VOID
110 );
111 /**
112 Get Post Code Break for Port 80 and 81
113
114 @param [out] *Port80 Pointer to return value of post code 80
115
116 @param [out] *Port81 Pointer to return value of post code 81
117 **/
118 VOID
119 GetPostCodeBreak(
120 UINT8 *Port80,
121 UINT8 *Port81
122 );
123
124 /**
125 Get TXT Alias Check Request and Reset it.
126
127 @retval TXT Alias Check Request
128 **/
129 UINT8
130 GetTxtAliasCheckAndReset(
131 VOID
132 );
133
134 /**
135 Save the TXT Alias Check Request.
136
137 @param [in] ACheckRequest Request of TXT Alias Check.
138 **/
139 VOID
140 SaveTxtAliasCheck(
141 UINT8 ACheckRequest
142 );
143
144 /**
145 Save the CPU Ratio.
146
147 @param [in] CpuRatio The Cpu ratio value to be saved.
148 **/
149 VOID
150 SaveCpuRatio(
151 UINT8 CpuRatio
152 );
153
154 /**
155 Set the BCLK Ramp Flag.
156
157 @param [in] BclkRampFlag The BCLK Ramp Flag to be set.
158 **/
159 VOID
160 SetBclkRampFlag(
161 UINT8 BclkRampFlag
162 );
163
164 /**
165 Save the SA settings related to Display
166
167 @param [in] SaSetup Display related SA data to be saved
168 @param [in] DDISelection DDI Selection
169 **/
170 VOID
171 SaveSaDisplayRegisters(
172 VOID *SaSetupData,
173 UINT8 DDISelection
174 );
175
176 /**
177 Get TBT Host Router Status.
178
179 CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)
180
181 @retval Current value of TBT Host Router Status
182 **/
183 UINT8
184 GetTbtHostRouterStatus(
185 VOID
186 );
187
188 /**
189 Save TBT Host Router Status.
190
191 CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)
192
193 @param [in] TbtHrStatus The TBT Host Router Status to be udpated.
194 **/
195 VOID
196 SaveTbtHostRouterStatus(
197 UINT8 TbtHrStatus
198 );
199 #endif // _PLATFORM_NVRAM_HOOK_LIB_H_
SaveTxtAliasCheck
VOID SaveTxtAliasCheck(UINT8 ACheckRequest)
Save the TXT Alias Check Request.
GetRtc3Address
UINT8 GetRtc3Address(VOID)
Get RTC 3 Address.
NeedResetBoardDefaultVariableHob
BOOLEAN NeedResetBoardDefaultVariableHob(VOID)
Check to reset setup variable and Clear CMOS 0E when CMOS content is bad.
GetPostCodeBreak
VOID GetPostCodeBreak(UINT8 *Port80, UINT8 *Port81)
Get Post Code Break for Port 80 and 81.
GetTxtAliasCheckAndReset
UINT8 GetTxtAliasCheckAndReset(VOID)
Get TXT Alias Check Request and Reset it.
GetBootFlagStatus
UINT8 GetBootFlagStatus(VOID)
Get Boot Flag Status.
SecondaryNvRamInit
VOID SecondaryNvRamInit(VOID)
Load CMOS default on RTC battery failure.
ClearDiagnosticStatus
VOID ClearDiagnosticStatus(VOID)
Clear Diagnostic Status.
UpdateBootFlagStatus
VOID UpdateBootFlagStatus(UINT8 BootStatus)
Update Boot Flag Status.
SaveTbtHostRouterStatus
VOID SaveTbtHostRouterStatus(UINT8 TbtHrStatus)
Save TBT Host Router Status.
SaveCpuRatio
VOID SaveCpuRatio(UINT8 CpuRatio)
Save the CPU Ratio.
IsChecksumBad
BOOLEAN IsChecksumBad(VOID)
Test to see if Checksum is bad.
SaveSaDisplayRegisters
VOID SaveSaDisplayRegisters(VOID *SaSetupData, UINT8 DDISelection)
Save the SA settings related to Display.
SetBclkRampFlag
VOID SetBclkRampFlag(UINT8 BclkRampFlag)
Set the BCLK Ramp Flag.
GetTbtHostRouterStatus
UINT8 GetTbtHostRouterStatus(VOID)
Get TBT Host Router Status.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformNvsArea.h Source File

  • Protocol
PlatformNvsArea.h
Go to the documentation of this file.
1 /** @file
2 This file defines the Platform NVS Area Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_NVS_AREA_H_
36 #define _PLATFORM_NVS_AREA_H_
37
38 //
39 // Platform NVS Area definition
40 //
41 #include <PlatformNvsAreaDef.h>
42
43 //
44 // Includes
45 //
46 #define PLATFORM_NVS_DEVICE_ENABLE 1
47 #define PLATFORM_NVS_DEVICE_DISABLE 0
48
49 //
50 // Forward reference for pure ANSI compatibility
51 //
52 typedef struct _PLATFORM_NVS_AREA_PROTOCOL PLATFORM_NVS_AREA_PROTOCOL;
53
54 //
55 // Platform NVS Area Protocol GUID
56 //
57 #define PLATFORM_NVS_AREA_PROTOCOL_GUID \
58 { 0xc77ae556,0x40a3, 0x41c0, 0xac, 0xe6, 0x71, 0x43, 0x8c, 0x60, 0xf8, 0x71 }
59
60 #define PLATFORM_NVS_AREA_REVISION_1 1
61
62 //
63 // Platform NVS Area Protocol
64 //
65 typedef struct _PLATFORM_NVS_AREA_PROTOCOL {
66 PLATFORM_NVS_AREA *Area;
67 } PLATFORM_NVS_AREA_PROTOCOL;
68
69 #endif // _PLATFORM_NVS_AREA_H_
PlatformNvsAreaDef.h
ACPI DSDT table.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformNvsAreaDef.h Source File

PlatformNvsAreaDef.h
Go to the documentation of this file.
1 //
2 // Automatically generated by GenNvs ver 2.4.2
3 // Please DO NOT modify !!!
4 //
5
6
7 /** @file
8 ACPI DSDT table
9
10 @copyright
11 INTEL CONFIDENTIAL
12 Copyright 2011 - 2017 Intel Corporation.
13
14 The source code contained or described herein and all documents related to the
15 source code ("Material") are owned by Intel Corporation or its suppliers or
16 licensors. Title to the Material remains with Intel Corporation or its suppliers
17 and licensors. The Material may contain trade secrets and proprietary and
18 confidential information of Intel Corporation and its suppliers and licensors,
19 and is protected by worldwide copyright and trade secret laws and treaty
20 provisions. No part of the Material may be used, copied, reproduced, modified,
21 published, uploaded, posted, transmitted, distributed, or disclosed in any way
22 without Intel's prior express written permission.
23
24 No license under any patent, copyright, trade secret or other intellectual
25 property right is granted to or conferred upon you by disclosure or delivery
26 of the Materials, either expressly, by implication, inducement, estoppel or
27 otherwise. Any license under such intellectual property rights must be
28 express and approved by Intel in writing.
29
30 Unless otherwise agreed by Intel in writing, you may not remove or alter
31 this notice or any other notice embedded in Materials by Intel or
32 Intel's suppliers or licensors in any way.
33
34 This file contains a 'Sample Driver' and is licensed as such under the terms
35 of your license agreement with Intel or your vendor. This file may be modified
36 by the user, subject to the additional terms of the license agreement.
37
38 @par Specification
39 **/
40
41 // Define a Global region of ACPI NVS Region that may be used for any
42 // type of implementation. The starting offset and size will be fixed
43 // up by the System BIOS during POST. Note that the Size must be a word
44 // in size to be fixed up correctly.
45
46
47 #ifndef _PLATFORM_NVS_AREA_DEF_H_
48 #define _PLATFORM_NVS_AREA_DEF_H_
49
50 #pragma pack (push,1)
51 typedef struct {
52 //
53 // Miscellaneous Dynamic Registers:
54 //
55 UINT16 OperatingSystem; ///< Offset 0 Operating System
56 UINT8 SmiFunction; ///< Offset 2 SMI Function Call (ASL to SMI via I/O Trap)
57 UINT8 SmiParameter0; ///< Offset 3 SMIF - Parameter 0
58 UINT8 SmiParameter1; ///< Offset 4 SMIF - Parameter 1
59 UINT8 SciFunction; ///< Offset 5 SCI Function Call (SMI to ASL via _L00)
60 UINT8 SciParameter0; ///< Offset 6 SCIF - Parameter 0
61 UINT8 SciParameter1; ///< Offset 7 SCIF - Parameter 1
62 UINT8 GlobalLock; ///< Offset 8 Global Lock Function Call (EC Communication)
63 UINT8 LockParameter0; ///< Offset 9 LCKF - Parameter 0
64 UINT8 LockParameter1; ///< Offset 10 LCKF - Parameter 1
65 UINT32 Port80DebugValue; ///< Offset 11 Port 80 Debug Port Value
66 UINT8 PowerState; ///< Offset 15 Power State (AC Mode = 1)
67 UINT8 DebugState; ///< Offset 16 Debug State
68 //
69 // Thermal Policy Registers:
70 //
71 UINT8 EnableThermalKSC; ///< Offset 17 Enable Thermal Offset for KSC
72 UINT8 Ac1TripPoint; ///< Offset 18 Active Trip Point 1
73 UINT8 Ac0TripPoint; ///< Offset 19 Active Trip Point
74 UINT8 PassiveThermalTripPoint; ///< Offset 20 Passive Trip Point
75 UINT8 PassiveTc1Value; ///< Offset 21 Passive Trip Point TC1 Value
76 UINT8 PassiveTc2Value; ///< Offset 22 Passive Trip Point TC2 Value
77 UINT8 PassiveTspValue; ///< Offset 23 Passive Trip Point TSP Value
78 UINT8 CriticalThermalTripPoint; ///< Offset 24 Critical Trip Point
79 UINT8 EnableDigitalThermalSensor; ///< Offset 25 Digital Thermal Sensor Enable
80 UINT8 BspDigitalThermalSensorTemperature; ///< Offset 26 Digital Thermal Sensor 1 Reading
81 UINT8 ApDigitalThermalSensorTemperature; ///< Offset 27 Digital Thermal Sensor 2 Reading
82 UINT8 DigitalThermalSensorSmiFunction; ///< Offset 28 DTS SMI Function Call
83 //
84 // Revision Field:
85 //
86 UINT8 Revision; ///< Offset 29 Revison of GlobalNvsArea
87 //
88 // CPU Identification Registers:
89 //
90 UINT8 ApicEnable; ///< Offset 30 APIC Enabled by SBIOS (APIC Enabled = 1)
91 UINT8 ThreadCount; ///< Offset 31 Number of Enabled Threads
92 UINT8 CurentPdcState0; ///< Offset 32 PDC Settings, Processor 0
93 UINT8 CurentPdcState1; ///< Offset 33 PDC Settings, Processor 1
94 UINT8 MaximumPpcState; ///< Offset 34 Maximum PPC state
95 UINT32 PpmFlags; ///< Offset 35 PPM Flags (Same as CFGD)
96 UINT8 C6C7Latency; ///< Offset 39 C6/C7 Entry/Exit latency
97 //
98 // SIO Configuration Registers:
99 //
100 UINT8 DockedSioPresent; ///< Offset 40 National SIO Present
101 UINT8 DockComA; ///< Offset 41 COM A Port
102 UINT8 DockComB; ///< Offset 42 COM B Port
103 UINT8 DockLpt; ///< Offset 43 LPT Port
104 UINT8 DockFdc; ///< Offset 44 FDC Port
105 UINT8 OnboardCom; ///< Offset 45 SMSC Com Port
106 UINT8 OnboardComCir; ///< Offset 46 SMSC Com CIR Port
107 UINT8 SMSC1007; ///< Offset 47 SMSC1007 SIO Present
108 UINT8 WPCN381U; ///< Offset 48 WPCN381U SIO Present
109 UINT8 SMSC1000; ///< Offset 49 SMSC1000 SIO Present
110 //
111 // Extended Mobile Access Values
112 //
113 UINT8 EmaEnable; ///< Offset 50 EMA Enable
114 UINT16 EmaPointer; ///< Offset 51 EMA Pointer
115 UINT16 EmaLength; ///< Offset 53 EMA Length
116 //
117 // MEF Registers:
118 //
119 UINT8 MefEnable; ///< Offset 55 MEF Enable
120 //
121 // PCIe Dock Status:
122 //
123 UINT8 PcieDockStatus; ///< Offset 56 PCIe Dock Status
124 //
125 // TPM Registers
126 //
127 UINT8 MorData; ///< Offset 57 Memory Overwrite Request Data
128 UINT8 TcgParamter; ///< Offset 58 Used for save the Mor and/or physical presence paramter
129 UINT32 PPResponse; ///< Offset 59 Physical Presence request operation response
130 UINT8 PPRequest; ///< Offset 63 Physical Presence request operation
131 UINT8 LastPPRequest; ///< Offset 64 Last Physical Presence request operation
132 //
133 // SATA Registers:
134 //
135 UINT8 IdeMode; ///< Offset 65 IDE Mode (Compatible\Enhanced)
136 //
137 // Board Id
138 //
139 UINT8 PlatformId; ///< Offset 66 Platform id
140 UINT8 BoardType; ///< Offset 67 Board Type
141 //
142 // PCIe Hot Plug
143 //
144 UINT8 PcieOSCControl; ///< Offset 68 PCIE OSC Control
145 UINT8 NativePCIESupport; ///< Offset 69 Native PCIE Setup Value
146 //
147 // USB Sideband Deferring Support
148 //
149 UINT8 HostAlertVector1; ///< Offset 70 USB Sideband Deferring GPE Vector (HOST_ALERT#1)
150 UINT8 HostAlertVector2; ///< Offset 71 USB Sideband Deferring GPE Vector (HOST_ALERT#2)
151 //
152 // Embedded Controller Availability Flag.
153 //
154 UINT8 EcAvailable; ///< Offset 72 Embedded Controller Availability Flag.
155 //
156 // Global Variables
157 //
158 UINT8 DisplaySupportFlag; ///< Offset 73 _DOS Display Support Flag.
159 UINT8 InterruptModeFlag; ///< Offset 74 Global IOAPIC/8259 Interrupt Mode Flag.
160 UINT8 CoolingTypeFlag; ///< Offset 75 Global Cooling Type Flag.
161 UINT8 L01Counter; ///< Offset 76 Global L01 Counter.
162 UINT8 VirtualFan0Status; ///< Offset 77 Virtual Fan0 Status.
163 UINT8 VirtualFan1Status; ///< Offset 78 Virtual Fan1 Status.
164 UINT8 VirtualFan2Status; ///< Offset 79 Virtual Fan2 Status.
165 UINT8 VirtualFan3Status; ///< Offset 80 Virtual Fan3 Status.
166 UINT8 VirtualFan4Status; ///< Offset 81 Virtual Fan4 Status.
167 UINT8 VirtualFan5Status; ///< Offset 82 Virtual Fan5 Status.
168 UINT8 VirtualFan6Status; ///< Offset 83 Virtual Fan6 Status.
169 UINT8 VirtualFan7Status; ///< Offset 84 Virtual Fan7 Status.
170 UINT8 VirtualFan8Status; ///< Offset 85 Virtual Fan8 Status.
171 UINT8 VirtualFan9Status; ///< Offset 86 Virtual Fan9 Status.
172 //
173 // Thermal
174 //
175 UINT8 ActiveThermalTripPointSA; ///< Offset 87 Active Trip Point for MCH
176 UINT8 PassiveThermalTripPointSA; ///< Offset 88 Passive Trip Point for MCH
177 UINT32 PlatformCpuId; ///< Offset 89 CPUID Feature Information [EAX]
178 UINT32 TBARB; ///< Offset 93 Reserved for Thermal Base Low Address for BIOS
179 UINT32 TBARBH; ///< Offset 97 Reserved for Thermal Base High Address for BIOS
180 UINT8 RunTimeInterface; ///< Offset 101 Run Time Interface for Intelligent Power Savings
181 UINT8 TsOnDimmEnabled; ///< Offset 102 TS-on-DIMM is chosen in SETUP and present on the DIMM
182 //
183 // Board info
184 //
185 UINT8 PlatformFlavor; ///< Offset 103 Platform Flavor
186 UINT8 BoardRev; ///< Offset 104 Board Rev
187 //
188 // Package temperature
189 //
190 UINT8 PackageDTSTemperature; ///< Offset 105 Package Temperature
191 UINT8 IsPackageTempMSRAvailable; ///< Offset 106 Package Temperature MSR available
192 UINT8 PeciAccessMethod; ///< Offset 107 Peci Access Method
193 UINT8 Ac0FanSpeed; ///< Offset 108 _AC0 Fan Speed
194 UINT8 Ac1FanSpeed; ///< Offset 109 _AC1 Fan Speed
195 UINT8 Ap2DigitalThermalSensorTemperature; ///< Offset 110 Digital Thermal Sensor 3 Reading
196 UINT8 Ap3DigitalThermalSensorTemperature; ///< Offset 111 Digital Thermal Sensor 4 Reading
197 //
198 // XTU 3.0 Specification
199 //
200 UINT32 XTUBaseAddress; ///< Offset 112 XTU Continous structure Base Address
201 UINT32 XTUSize; ///< Offset 116 XMP Size
202 UINT32 XMPBaseAddress; ///< Offset 120 XMP Base Address
203 UINT8 DDRReferenceFreq; ///< Offset 124 DDR Reference Frequency
204 UINT8 Rtd3Support; ///< Offset 125 Runtime D3 support.
205 UINT8 Rtd3P0dl; ///< Offset 126 User selctable Delay for Device D0 transition.
206 UINT8 Rtd3P3dl; ///< Offset 127 User selctable Delay for Device D3 transition.
207 //
208 // DPTF Devices and trip points
209 //
210 UINT8 EnableDptf; ///< Offset 128 EnableDptf
211 UINT16 EnableDCFG; ///< Offset 129 EnableDCFG
212 UINT8 EnableSaDevice; ///< Offset 131 EnableSaDevice
213 UINT8 CriticalThermalTripPointSA; ///< Offset 132 CriticalThermalTripPointSa
214 UINT8 HotThermalTripPointSA; ///< Offset 133 HotThermalTripPointSa
215 UINT8 ThermalSamplingPeriodSA; ///< Offset 134 ThermalSamplingPeriodSA
216 //
217 // DPTF Policies
218 //
219 UINT8 EnableCtdpPolicy; ///< Offset 135 EnableCtdpPolicy
220 //
221 // DPPM Devices and trip points
222 //
223 UINT8 EnableFan1Device; ///< Offset 136 EnableFan1Device
224 UINT8 EnableAmbientDevice; ///< Offset 137 EnableAmbientDevice
225 UINT8 ActiveThermalTripPointAmbient; ///< Offset 138 ActiveThermalTripPointAmbient
226 UINT8 PassiveThermalTripPointAmbient; ///< Offset 139 PassiveThermalTripPointAmbient
227 UINT8 CriticalThermalTripPointAmbient; ///< Offset 140 CriticalThermalTripPointAmbient
228 UINT8 HotThermalTripPointAmbient; ///< Offset 141 HotThermalTripPointAmbient
229 UINT8 EnableSkinDevice; ///< Offset 142 EnableSkinDevice
230 UINT8 ActiveThermalTripPointSkin; ///< Offset 143 ActiveThermalTripPointSkin
231 UINT8 PassiveThermalTripPointSkin; ///< Offset 144 PassiveThermalTripPointSkin
232 UINT8 CriticalThermalTripPointSkin; ///< Offset 145 CriticalThermalTripPointSkin
233 UINT8 HotThermalTripPointSkin; ///< Offset 146 HotThermalTripPointSkin
234 UINT8 EnableExhaustFanDevice; ///< Offset 147 EnableExhaustFanDevice
235 UINT8 ActiveThermalTripPointExhaustFan; ///< Offset 148 ActiveThermalTripPointExhaustFan
236 UINT8 PassiveThermalTripPointExhaustFan; ///< Offset 149 PassiveThermalTripPointExhaustFan
237 UINT8 CriticalThermalTripPointExhaustFan; ///< Offset 150 CriticalThermalTripPointExhaustFan
238 UINT8 HotThermalTripPointExhaustFan; ///< Offset 151 HotThermalTripPointExhaustFan
239 UINT8 EnableVRDevice; ///< Offset 152 EnableVRDevice
240 UINT8 ActiveThermalTripPointVR; ///< Offset 153 ActiveThermalTripPointVR
241 UINT8 PassiveThermalTripPointVR; ///< Offset 154 PassiveThermalTripPointVR
242 UINT8 CriticalThermalTripPointVR; ///< Offset 155 CriticalThermalTripPointVR
243 UINT8 HotThermalTripPointVR; ///< Offset 156 HotThermalTripPointVR
244 //
245 // DPPM Policies
246 //
247 UINT8 EnableActivePolicy; ///< Offset 157 EnableActivePolicy
248 UINT8 EnablePassivePolicy; ///< Offset 158 EnablePassivePolicy
249 UINT8 EnableCriticalPolicy; ///< Offset 159 EnableCriticalPolicy
250 UINT8 EnablePIDPolicy; ///< Offset 160 EnablePIDPolicy
251 UINT8 TrtRevision; ///< Offset 161 TrtRevision
252 //
253 // CLPO (Current Logical Processor Off lining Setting)
254 //
255 UINT8 LPOEnable; ///< Offset 162 LPOEnable
256 UINT8 LPOStartPState; ///< Offset 163 LPOStartPState
257 UINT8 LPOStepSize; ///< Offset 164 LPOStepSize
258 UINT8 LPOPowerControlSetting; ///< Offset 165 LPOPowerControlSetting
259 UINT8 LPOPerformanceControlSetting; ///< Offset 166 LPOPerformanceControlSetting
260 //
261 // Miscellaneous DPTF
262 //
263 UINT32 PpccStepSize; ///< Offset 167 PPCC Step Size
264 UINT8 EnableDisplayParticipant; ///< Offset 171 EnableDisplayParticipant
265 //
266 // BIOS Guard
267 //
268 UINT64 BiosGuardMemAddress; ///< Offset 172 BIOS Guard Memory Address for Tool Interface
269 UINT8 BiosGuardMemSize; ///< Offset 180 BIOS Guard Memory Size for Tool Interface
270 UINT16 BiosGuardIoTrapAddress; ///< Offset 181 BIOS Guard IoTrap Address for Tool Interface
271 //
272 // Never Sleep Technology
273 //
274 UINT8 IrmtCfg; ///< Offset 183 Irmt Configuration
275 //
276 // Comms Hub
277 //
278 UINT8 CommsHubEnable; ///< Offset 184 Comms Hub Enable/Disable
279 UINT8 LowPowerS0Idle; ///< Offset 185 Low Power S0 Idle Enable
280 //
281 // BIOS only version of Config TDP
282 //
283 UINT8 ConfigTdpBios; ///< Offset 186 enable/disable BIOS only version of Config TDP
284 UINT8 DockSmi; ///< Offset 187 Dock SMI number
285 //
286 // LPC SIO configuration
287 //
288 UINT16 LpcSioPort1; ///< Offset 188 SIO config port 1
289 UINT16 LpcSioPort2; ///< Offset 190 SIO config port 2
290 UINT16 LpcSioPmeBar; ///< Offset 192 SIO PME Base Address
291 UINT8 Reserved0[306]; ///< Offset 194:499
292 UINT8 EnableWrlsParticipant; ///< Offset 500 EnableWrlsParticipant
293 UINT8 ActiveThermalTripPointWrls; ///< Offset 501 ActiveThermalTripPointWrls
294 UINT8 PassiveThermalTripPointWrls; ///< Offset 502 PassiveThermalTripPointWrls
295 UINT8 CriticalThermalTripPointWrls; ///< Offset 503 CriticalThermalTripPointWrls
296 UINT8 HotThermalTripPointWrls; ///< Offset 504 HotThermalTripPointWrls
297 UINT8 EnablePowerParticipant; ///< Offset 505 EnablePowerParticipant
298 UINT16 DPTFRsvd0; ///< Offset 506 DPTFRsvd0
299 UINT16 PowerParticipantPollingRate; ///< Offset 508 PowerParticipantPollingRate
300 UINT8 EnablePowerBossPolicy; ///< Offset 510 EnablePowerBossPolicy
301 UINT8 EnableVSPolicy; ///< Offset 511 EnableVSPolicy
302 UINT8 EnableRFIMPolicy; ///< Offset 512 RFI Mitigation
303 UINT8 Reserved1[2]; ///< Offset 513:514
304 UINT8 UsbPowerResourceTest; ///< Offset 515 RTD3 USB Power Resource config
305 UINT8 Rtd3I2C0SensorHub; ///< Offset 516 RTD3 support for I2C0 SH
306 UINT8 VirtualGpioButtonSxBitmask; ///< Offset 517 Virtual GPIO button Notify Sleep State Change
307 UINT8 IuerButtonEnable; ///< Offset 518 IUER Button Enable
308 UINT8 IuerConvertibleEnable; ///< Offset 519 IUER Convertible Enable
309 UINT8 IuerDockEnable; ///< Offset 520 IUER Dock Enable
310 UINT8 CSNotifyEC; ///< Offset 521 EC Notification of Low Power S0 Idle State
311 UINT16 Rtd3AudioDelay; ///< Offset 522 RTD3 Audio Codec device delay
312 UINT16 Rtd3SensorHub; ///< Offset 524 RTD3 SensorHub delay time after applying power to device
313 UINT16 Rtd3TouchPanelDelay; ///< Offset 526 RTD3 TouchPanel delay time after applying power to device
314 UINT16 Rtd3TouchPadDelay; ///< Offset 528 RTD3 TouchPad delay time after applying power to device
315 UINT16 VRRampUpDelay; ///< Offset 530 VR Ramp up delay
316 UINT8 PstateCapping; ///< Offset 532 P-state Capping
317 UINT16 Rtd3I2C0ControllerPS0Delay; ///< Offset 533 Delay in _PS0 after powering up I2C0 Controller
318 UINT16 Rtd3I2C1ControllerPS0Delay; ///< Offset 535 Delay in _PS0 after powering up I2C1 Controller
319 UINT16 Rtd3Config0; ///< Offset 537 RTD3 Config Setting0(BIT0:ZPODD, BIT1:Reserved, BIT2:PCIe NVMe, Bit4:SKL SDS SIP I2C Touch, BIT6:Card Reader, BIT7:WWAN)
320 UINT16 Rtd3Config1; ///< Offset 539 RTD3 Config Setting1(BIT0:Sata Port0, BIT1:Sata Port1, BIT2:Sata Port2, BIT3:Sata Port3)
321 UINT8 CSDebugLightEC; ///< Offset 541 EC Debug Light (CAPS LOCK) for when in Low Power S0 Idle State
322 UINT8 Ps2MouseEnable; ///< Offset 542 Ps2 Mouse Enable
323 UINT8 Ps2KbMsEnable; ///< Offset 543 Ps2 Keyboard and Mouse Enable
324 UINT8 DiscreteWifiRtd3ColdSupport; ///< Offset 544 Enable RTD3 Cold Support for Wifi
325 UINT8 DiscreteWigigRtd3ColdSupport; ///< Offset 545 Enable RTD3 Cold Support for Wigig
326 UINT8 DiscreteWwanRtd3ColdSupport; ///< Offset 546 Enable RTD3 Cold Support for WWAN
327 UINT16 SSH0; ///< Offset 547 SSCN-HIGH for I2C0
328 UINT16 SSL0; ///< Offset 549 SSCN-LOW for I2C0
329 UINT16 SSD0; ///< Offset 551 SSCN-HOLD for I2C0
330 UINT16 FMH0; ///< Offset 553 FMCN-HIGH for I2C0
331 UINT16 FML0; ///< Offset 555 FMCN-LOW for I2C0
332 UINT16 FMD0; ///< Offset 557 FMCN-HOLD for I2C0
333 UINT16 FPH0; ///< Offset 559 FPCN-HIGH for I2C0
334 UINT16 FPL0; ///< Offset 561 FPCN-LOW for I2C0
335 UINT16 FPD0; ///< Offset 563 FPCN-HOLD for I2C0
336 UINT16 HMH0; ///< Offset 565 HMCN-HIGH for I2C0
337 UINT16 HML0; ///< Offset 567 HMCN-LOW for I2C0
338 UINT16 HMD0; ///< Offset 569 HMCN-HOLD for I2C0
339 UINT8 Reserved2[2]; ///< Offset 571:572
340 UINT16 SSH1; ///< Offset 573 SSCN-HIGH for I2C1
341 UINT16 SSL1; ///< Offset 575 SSCN-LOW for I2C1
342 UINT16 SSD1; ///< Offset 577 SSCN-HOLD for I2C1
343 UINT16 FMH1; ///< Offset 579 FMCN-HIGH for I2C1
344 UINT16 FML1; ///< Offset 581 FMCN-LOW for I2C1
345 UINT16 FMD1; ///< Offset 583 FMCN-HOLD for I2C1
346 UINT16 FPH1; ///< Offset 585 FPCN-HIGH for I2C1
347 UINT16 FPL1; ///< Offset 587 FPCN-LOW for I2C1
348 UINT16 FPD1; ///< Offset 589 FPCN-HOLD for I2C1
349 UINT16 HMH1; ///< Offset 591 HMCN-HIGH for I2C1
350 UINT16 HML1; ///< Offset 593 HMCN-LOW for I2C1
351 UINT16 HMD1; ///< Offset 595 HMCN-HOLD for I2C1
352 UINT8 Reserved3[1]; ///< Offset 597:597
353 UINT16 SSH2; ///< Offset 598 SSCN-HIGH for I2C2
354 UINT16 SSL2; ///< Offset 600 SSCN-LOW for I2C2
355 UINT16 SSD2; ///< Offset 602 SSCN-HOLD for I2C2
356 UINT16 FMH2; ///< Offset 604 FMCN-HIGH for I2C2
357 UINT16 FML2; ///< Offset 606 FMCN-LOW for I2C2
358 UINT16 FMD2; ///< Offset 608 FMCN-HOLD for I2C2
359 UINT16 FPH2; ///< Offset 610 FPCN-HIGH for I2C2
360 UINT16 FPL2; ///< Offset 612 FPCN-LOW for I2C2
361 UINT16 FPD2; ///< Offset 614 FPCN-HOLD for I2C2
362 UINT16 HMH2; ///< Offset 616 HMCN-HIGH for I2C2
363 UINT16 HML2; ///< Offset 618 HMCN-LOW for I2C2
364 UINT16 HMD2; ///< Offset 620 HMCN-HOLD for I2C2
365 UINT8 Reserved4[1]; ///< Offset 622:622
366 UINT16 SSH3; ///< Offset 623 SSCN-HIGH for I2C3
367 UINT16 SSL3; ///< Offset 625 SSCN-LOW for I2C3
368 UINT16 SSD3; ///< Offset 627 SSCN-HOLD for I2C3
369 UINT16 FMH3; ///< Offset 629 FMCN-HIGH for I2C3
370 UINT16 FML3; ///< Offset 631 FMCN-LOW for I2C3
371 UINT16 FMD3; ///< Offset 633 FMCN-HOLD for I2C3
372 UINT16 FPH3; ///< Offset 635 FPCN-HIGH for I2C3
373 UINT16 FPL3; ///< Offset 637 FPCN-LOW for I2C3
374 UINT16 FPD3; ///< Offset 639 FPCN-HOLD for I2C3
375 UINT16 HMH3; ///< Offset 641 HMCN-HIGH for I2C3
376 UINT16 HML3; ///< Offset 643 HMCN-LOW for I2C3
377 UINT16 HMD3; ///< Offset 645 HMCN-HOLD for I2C3
378 UINT8 Reserved5[1]; ///< Offset 647:647
379 UINT16 SSH4; ///< Offset 648 SSCN-HIGH for I2C4
380 UINT16 SSL4; ///< Offset 650 SSCN-LOW for I2C4
381 UINT16 SSD4; ///< Offset 652 SSCN-HOLD for I2C4
382 UINT16 FMH4; ///< Offset 654 FMCN-HIGH for I2C4
383 UINT16 FML4; ///< Offset 656 FMCN-LOW for I2C4
384 UINT16 FMD4; ///< Offset 658 FMCN-HOLD for I2C4
385 UINT16 FPH4; ///< Offset 660 FPCN-HIGH for I2C4
386 UINT16 FPL4; ///< Offset 662 FPCN-LOW for I2C4
387 UINT16 FPD4; ///< Offset 664 FPCN-HOLD for I2C4
388 UINT16 HMH4; ///< Offset 666 HMCN-HIGH for I2C4
389 UINT16 HML4; ///< Offset 668 HMCN-LOW for I2C4
390 UINT16 HMD4; ///< Offset 670 HMCN-HOLD for I2C4
391 UINT8 Reserved6[1]; ///< Offset 672:672
392 UINT16 SSH5; ///< Offset 673 SSCN-HIGH for I2C5
393 UINT16 SSL5; ///< Offset 675 SSCN-LOW for I2C5
394 UINT16 SSD5; ///< Offset 677 SSCN-HOLD for I2C5
395 UINT16 FMH5; ///< Offset 679 FMCN-HIGH for I2C5
396 UINT16 FML5; ///< Offset 681 FMCN-LOW for I2C5
397 UINT16 FMD5; ///< Offset 683 FMCN-HOLD for I2C5
398 UINT16 FPH5; ///< Offset 685 FPCN-HIGH for I2C5
399 UINT16 FPL5; ///< Offset 687 FPCN-LOW for I2C5
400 UINT16 FPD5; ///< Offset 689 FPCN-HOLD for I2C5
401 UINT16 HMH5; ///< Offset 691 HMCN-HIGH for I2C5
402 UINT16 HML5; ///< Offset 693 HMCN-LOW for I2C5
403 UINT16 HMD5; ///< Offset 695 HMCN-HOLD for I2C5
404 UINT8 Reserved7[1]; ///< Offset 697:697
405 UINT16 M0C0; ///< Offset 698 M0D3 for I2C0
406 UINT16 M1C0; ///< Offset 700 M1D3 for I2C0
407 UINT16 M0C1; ///< Offset 702 M0D3 for I2C1
408 UINT16 M1C1; ///< Offset 704 M1D3 for I2C1
409 UINT16 M0C2; ///< Offset 706 M0D3 for I2C2
410 UINT16 M1C2; ///< Offset 708 M1D3 for I2C2
411 UINT16 M0C3; ///< Offset 710 M0D3 for I2C3
412 UINT16 M1C3; ///< Offset 712 M1D3 for I2C3
413 UINT16 M0C4; ///< Offset 714 M0D3 for I2C4
414 UINT16 M1C4; ///< Offset 716 M1D3 for I2C4
415 UINT16 M0C5; ///< Offset 718 M0D3 for I2C5
416 UINT16 M1C5; ///< Offset 720 M1D3 for I2C5
417 UINT16 M0C6; ///< Offset 722 M0D3 for SPI0
418 UINT16 M1C6; ///< Offset 724 M1D3 for SPI0
419 UINT16 M0C7; ///< Offset 726 M0D3 for SPI1
420 UINT16 M1C7; ///< Offset 728 M1D3 for SPI1
421 UINT16 M0C8; ///< Offset 730 M0D3 for SPI2
422 UINT16 M1C8; ///< Offset 732 M1D3 for SPI2
423 UINT8 Reserved8[1]; ///< Offset 734:734
424 UINT16 M0C9; ///< Offset 735 M0D3 for UART0
425 UINT16 M1C9; ///< Offset 737 M1D3 for UART0
426 UINT16 M0CA; ///< Offset 739 M0D3 for UART1
427 UINT16 M1CA; ///< Offset 741 M1D3 for UART1
428 UINT16 M0CB; ///< Offset 743 M0D3 for UART2
429 UINT16 M1CB; ///< Offset 745 M1D3 for UART2
430 UINT8 Reserved9[1]; ///< Offset 747:747
431 //
432 // Driver Mode
433 //
434 UINT32 GpioIrqRoute; ///< Offset 748 GPIO IRQ
435 UINT8 DriverModeTouchPanel; ///< Offset 752 PIRQS 34,50(GPIO)
436 UINT8 DriverModeTouchPad; ///< Offset 753 PIRQX 39,55(GPIO)
437 UINT8 DriverModeSensorHub; ///< Offset 754 PIRQM 28,14(GPIO)
438 UINT8 SensorStandby; ///< Offset 755 Sensor Standby mode
439 UINT8 PL1LimitCS; ///< Offset 756 set PL1 limit when entering CS
440 UINT16 PL1LimitCSValue; ///< Offset 757 PL1 limit value
441 UINT8 EnableWwanTempSensorDevice; ///< Offset 759 EnableWwanTempSensorDevice
442 UINT8 EnableCpuVrTempSensorDevice; ///< Offset 760 EnableCpuVrTempSensorDevice
443 UINT8 EnableSsdTempSensorDevice; ///< Offset 761 EnableSsdTempSensorDevice
444 UINT8 EnableInletFanTempSensorDevice; ///< Offset 762 EnableInletFanTempSensorDevice
445 UINT8 ActiveThermalTripPointInletFan; ///< Offset 763 ActiveThermalTripPointInletFan
446 UINT8 PassiveThermalTripPointInletFan; ///< Offset 764 PassiveThermalTripPointInletFan
447 UINT8 CriticalThermalTripPointInletFan; ///< Offset 765 CriticalThermalTripPointInletFan
448 UINT8 HotThermalTripPointInletFan; ///< Offset 766 HotThermalTripPointInletFan
449 UINT8 UsbSensorHub; ///< Offset 767 Sensor Hub Type - (0)None, (1)USB, (2)I2C Intel, (3)I2C STM
450 UINT8 BCV4; ///< Offset 768 Broadcom's Bluetooth adapter's revision
451 UINT8 WTV0; ///< Offset 769 I2C0/WITT devices version
452 UINT8 WTV1; ///< Offset 770 I2C1/WITT devices version
453 UINT8 AtmelPanelFwUpdate; ///< Offset 771 Atmel panel FW update Enable/Disable
454 UINT8 Reserved10[6]; ///< Offset 772:777
455 UINT32 LowPowerS0IdleConstraint; ///< Offset 778 PEP Constraints
456 // Bit[1:0] - Storage (0:None, 1:Storage Controller, 2:Raid)
457 // Bit[2] - En/Dis UART0
458 // Bit[3] - En/Dis UART1
459 // Bit[4] - Unused
460 // Bit[5] - En/Dis I2C0
461 // Bit[6] - En/Dis I2C1
462 // Bit[7] - En/Dis XHCI
463 // Bit[8] - En/Dis HD Audio (includes ADSP)
464 // Bit[9] - En/Dis Gfx
465 // Bit[10] - En/Dis CPU
466 // Bit[11] - En/Dis EMMC
467 // Bit[12] - En/Dis SDXC
468 // Bit[13] - En/Dis I2C2
469 // Bit[14] - En/Dis I2C3
470 // Bit[15] - En/Dis I2C4
471 // Bit[16] - En/Dis I2C5
472 // Bit[17] - En/Dis UART2
473 // Bit[18] - En/Dis SPI0
474 // Bit[19] - En/Dis SPI1
475 // Bit[20] - [CNL] En/Dis SPI2
476 // Bit[21] - En/Dis IPU0
477 // Bit[22] - En/Dis CSME
478 UINT16 VRStaggeringDelay; ///< Offset 782 VR Staggering delay
479 UINT8 TenSecondPowerButtonEnable; ///< Offset 784 10sec Power button support
480 // Bit0: 10 sec P-button Enable/Disable
481 // Bit1: Internal Flag
482 // Bit2: Rotation Lock flag, 0:unlock, 1:lock
483 // Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop
484 // Bit4: Undock / Dock Flag, 0: Undock, 1: Dock
485 // Bit5: VBDL Flag. 0: VBDL is not called, 1: VBDL is called, Virtual Button Driver is loaded.
486 // Bit6: Reserved for future use.
487 // Bit7: EC 10sec PB Override state for S3/S4 wake up.
488 //
489 // Generation Id(Tock/Tick)
490 //
491 UINT8 GenerationId; ///< Offset 785 Generation Id(0=Shark bay, 1=Crescent Bay)
492 //
493 // DPTF
494 //
495 UINT8 EnableWWANParticipant; ///< Offset 786 EnableWWANParticipant
496 UINT8 ActiveThermalTripPointWWAN; ///< Offset 787 ActiveThermalTripPointWWAN
497 UINT8 PassiveThermalTripPointWWAN; ///< Offset 788 PassiveThermalTripPointWWAN
498 UINT8 CriticalThermalTripPointWWAN; ///< Offset 789 CriticalThermalTripPointWWAN
499 UINT8 HotThermalTripPointWWAN; ///< Offset 790 HotThermalTripPointWWAN
500 UINT8 Reserved11[16]; ///< Offset 791:806
501 UINT16 MinPowerLimit0; ///< Offset 807 Minimum Power Limit 0 for DPTF use via PPCC Object
502 UINT8 EnableChargerParticipant; ///< Offset 809 EnableChargerParticipant
503 UINT8 CriticalThermalTripPointSaS3; ///< Offset 810 CriticalThermalTripPointSaS3
504 UINT8 CriticalThermalTripPointAmbientS3; ///< Offset 811 CriticalThermalTripPointAmbientS3
505 UINT8 CriticalThermalTripPointSkinS3; ///< Offset 812 CriticalThermalTripPointSkinS3
506 UINT8 CriticalThermalTripPointExhaustFanS3; ///< Offset 813 CriticalThermalTripPointExhaustFanS3
507 UINT8 CriticalThermalTripPointVrS3; ///< Offset 814 CriticalThermalTripPointVRS3
508 UINT8 CriticalThermalTripPointWrlsS3; ///< Offset 815 CriticalThermalTripPointWrlsS3
509 UINT8 CriticalThermalTripPointInletFanS3; ///< Offset 816 CriticalThermalTripPointInletFanS3
510 UINT8 CriticalThermalTripPointWwanS3; ///< Offset 817 CriticalThermalTripPointWWANS3
511 UINT8 CriticalThermalTripPointWGigS3; ///< Offset 818 CriticalThermalTripPointWGigS3
512 UINT8 SataPortState; ///< Offset 819 SATA port state, Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3
513 //
514 // DPTF
515 //
516 UINT8 Enable2DCameraParticipant; ///< Offset 820 Enable2DCameraParticipant
517 UINT8 EcLowPowerMode; ///< Offset 821 EC Low Power Mode: 1 - Enabled, 0 - Disabled
518 UINT8 SensorSamplingPeriodSen1; ///< Offset 822 SensorSamplingPeriodSen1
519 UINT8 SensorSamplingPeriodSen2; ///< Offset 823 SensorSamplingPeriodSen2
520 UINT8 SensorSamplingPeriodSen3; ///< Offset 824 SensorSamplingPeriodSen3
521 UINT8 SensorSamplingPeriodSen4; ///< Offset 825 SensorSamplingPeriodSen4
522 UINT8 SensorSamplingPeriodSen5; ///< Offset 826 SensorSamplingPeriodSen5
523 UINT8 ThermalSamplingPeriodTMEM; ///< Offset 827 ThermalSamplingPeriodTMEM @deprecated. Memory Participant is not POR for DPTF
524 UINT8 EnableStorageParticipantST1; ///< Offset 828 EnableStorageParticipantST1
525 UINT8 ActiveThermalTripPointST1; ///< Offset 829 ActiveThermalTripPointST1
526 UINT8 PassiveThermalTripPointST1; ///< Offset 830 PassiveThermalTripPointST1
527 UINT8 CriticalThermalTripPointST1; ///< Offset 831 CriticalThermalTripPointST1
528 UINT8 CriticalThermalTripPointS3ST1; ///< Offset 832 CriticalThermalTripPointS3ST1
529 UINT8 HotThermalTripPointST1; ///< Offset 833 HotThermalTripPointST1
530 UINT8 EnableStorageParticipantST2; ///< Offset 834 EnableStorageParticipantST2
531 UINT8 ActiveThermalTripPointST2; ///< Offset 835 ActiveThermalTripPointST2
532 UINT8 PassiveThermalTripPointST2; ///< Offset 836 PassiveThermalTripPointST2
533 UINT8 CriticalThermalTripPointST2; ///< Offset 837 CriticalThermalTripPointST2
534 UINT8 CriticalThermalTripPointS3ST2; ///< Offset 838 CriticalThermalTripPointS3ST2
535 UINT8 HotThermalTripPointST2; ///< Offset 839 HotThermalTripPointST2
536 UINT8 EnableVS1Participant; ///< Offset 840 EnableVS1Participant
537 UINT8 ActiveThermalTripPointVS1; ///< Offset 841 ActiveThermalTripPointVS1
538 UINT8 PassiveThermalTripPointVS1; ///< Offset 842 PassiveThermalTripPointVS1
539 UINT8 CriticalThermalTripPointVS1; ///< Offset 843 CriticalThermalTripPointVS1
540 UINT8 CriticalThermalTripPointVS1S3; ///< Offset 844 CriticalThermalTripPointVS1S3
541 UINT8 HotThermalTripPointVS1; ///< Offset 845 HotThermalTripPointVS1
542 UINT8 EnableVS2Participant; ///< Offset 846 EnableVS2Participant
543 UINT8 ActiveThermalTripPointVS2; ///< Offset 847 ActiveThermalTripPointVS2
544 UINT8 PassiveThermalTripPointVS2; ///< Offset 848 PassiveThermalTripPointVS2
545 UINT8 CriticalThermalTripPointVS2; ///< Offset 849 CriticalThermalTripPointVS2
546 UINT8 CriticalThermalTripPointVS2S3; ///< Offset 850 CriticalThermalTripPointVS2S3
547 UINT8 HotThermalTripPointVS2; ///< Offset 851 HotThermalTripPointVS2
548 UINT8 EnableSen1Participant; ///< Offset 852 EnableSen1Participant
549 UINT8 ActiveThermalTripPointSen1; ///< Offset 853 ActiveThermalTripPointSen1
550 UINT8 PassiveThermalTripPointSen1; ///< Offset 854 PassiveThermalTripPointSen1
551 UINT8 CriticalThermalTripPointSen1; ///< Offset 855 CriticalThermalTripPointSen1
552 UINT8 HotThermalTripPointSen1; ///< Offset 856 HotThermalTripPointSen1
553 UINT8 EnableSen2Participant; ///< Offset 857 EnableSen2Participant
554 UINT8 ActiveThermalTripPointSen2; ///< Offset 858 ActiveThermalTripPointSen2
555 UINT8 PassiveThermalTripPointSen2; ///< Offset 859 PassiveThermalTripPointSen2
556 UINT8 CriticalThermalTripPointSen2; ///< Offset 860 CriticalThermalTripPointSen2
557 UINT8 HotThermalTripPointSen2; ///< Offset 861 HotThermalTripPointSen2
558 UINT8 EnableSen3Participant; ///< Offset 862 EnableSen3Participant
559 UINT8 ActiveThermalTripPointSen3; ///< Offset 863 ActiveThermalTripPointSen3
560 UINT8 PassiveThermalTripPointSen3; ///< Offset 864 PassiveThermalTripPointSen3
561 UINT8 CriticalThermalTripPointSen3; ///< Offset 865 CriticalThermalTripPointSen3
562 UINT8 HotThermalTripPointSen3; ///< Offset 866 HotThermalTripPointSen3
563 UINT8 EnableSen4Participant; ///< Offset 867 EnableSen4Participant
564 UINT8 ActiveThermalTripPointSen4; ///< Offset 868 ActiveThermalTripPointSen4
565 UINT8 PassiveThermalTripPointSen4; ///< Offset 869 PassiveThermalTripPointSen4
566 UINT8 CriticalThermalTripPointSen4; ///< Offset 870 CriticalThermalTripPointSen4
567 UINT8 HotThermalTripPointSen4; ///< Offset 871 HotThermalTripPointSen4
568 UINT8 EnableSen5Participant; ///< Offset 872 EnableSen5Participant
569 UINT8 ActiveThermalTripPointSen5; ///< Offset 873 ActiveThermalTripPointSen5
570 UINT8 PassiveThermalTripPointSen5; ///< Offset 874 PassiveThermalTripPointSen5
571 UINT8 CriticalThermalTripPointSen5; ///< Offset 875 CriticalThermalTripPointSen5
572 UINT8 HotThermalTripPointSen5; ///< Offset 876 HotThermalTripPointSen5
573 UINT8 CriticalThermalTripPointSen1S3; ///< Offset 877 CriticalThermalTripPointSen1S3
574 UINT8 CriticalThermalTripPointSen2S3; ///< Offset 878 CriticalThermalTripPointSen2S3
575 UINT8 CriticalThermalTripPointSen3S3; ///< Offset 879 CriticalThermalTripPointSen3S3
576 UINT8 CriticalThermalTripPointSen4S3; ///< Offset 880 CriticalThermalTripPointSen4S3
577 UINT8 CriticalThermalTripPointSen5S3; ///< Offset 881 CriticalThermalTripPointSen5S3
578 UINT8 PowerSharingManagerEnable; ///< Offset 882 PowerSharingManagerEnable
579 UINT8 PsmSplcDomainType1; ///< Offset 883 PsmSplcDomainType1
580 UINT32 PsmSplcPowerLimit1; ///< Offset 884 PsmSplcPowerLimit1
581 UINT32 PsmSplcTimeWindow1; ///< Offset 888 PsmSplcTimeWindow1
582 UINT8 PsmSplcDomainType2; ///< Offset 892 PsmSplcDomainType2
583 UINT32 PsmSplcPowerLimit2; ///< Offset 893 PsmSplcPowerLimit2
584 UINT32 PsmSplcTimeWindow2; ///< Offset 897 PsmSplcTimeWindow2
585 UINT8 PsmDplcDomainType1; ///< Offset 901 PsmDplcDomainType1
586 UINT8 PsmDplcDomainPreference1; ///< Offset 902 PsmDplcDomainPreference1
587 UINT16 PsmDplcPowerLimitIndex1; ///< Offset 903 PsmDplcPowerLimitIndex1
588 UINT16 PsmDplcDefaultPowerLimit1; ///< Offset 905 PsmDplcDefaultPowerLimit1
589 UINT32 PsmDplcDefaultTimeWindow1; ///< Offset 907 PsmDplcDefaultTimeWindow1
590 UINT16 PsmDplcMinimumPowerLimit1; ///< Offset 911 PsmDplcMinimumPowerLimit1
591 UINT16 PsmDplcMaximumPowerLimit1; ///< Offset 913 PsmDplcMaximumPowerLimit1
592 UINT16 PsmDplcMaximumTimeWindow1; ///< Offset 915 PsmDplcMaximumTimeWindow1
593 UINT8 PsmDplcDomainType2; ///< Offset 917 PsmDplcDomainType2
594 UINT8 PsmDplcDomainPreference2; ///< Offset 918 PsmDplcDomainPreference2
595 UINT16 PsmDplcPowerLimitIndex2; ///< Offset 919 PsmDplcPowerLimitIndex2
596 UINT16 PsmDplcDefaultPowerLimit2; ///< Offset 921 PsmDplcDefaultPowerLimit2
597 UINT32 PsmDplcDefaultTimeWindow2; ///< Offset 923 PsmDplcDefaultTimeWindow2
598 UINT16 PsmDplcMinimumPowerLimit2; ///< Offset 927 PsmDplcMinimumPowerLimit2
599 UINT16 PsmDplcMaximumPowerLimit2; ///< Offset 929 PsmDplcMaximumPowerLimit2
600 UINT16 PsmDplcMaximumTimeWindow2; ///< Offset 931 PsmDplcMaximumTimeWindow2
601 UINT8 WifiEnable; ///< Offset 933 WifiEnable
602 UINT8 WifiDomainType1; ///< Offset 934 WifiDomainType1
603 UINT16 WifiPowerLimit1; ///< Offset 935 WifiPowerLimit1
604 UINT32 WifiTimeWindow1; ///< Offset 937 WifiTimeWindow1
605 UINT8 WifiDomainType2; ///< Offset 941 WifiDomainType2
606 UINT16 WifiPowerLimit2; ///< Offset 942 WifiPowerLimit2
607 UINT32 WifiTimeWindow2; ///< Offset 944 WifiTimeWindow2
608 UINT8 WifiDomainType3; ///< Offset 948 WifiDomainType3
609 UINT16 WifiPowerLimit3; ///< Offset 949 WifiPowerLimit3
610 UINT32 WifiTimeWindow3; ///< Offset 951 WifiTimeWindow3
611 UINT8 TRxDelay0; ///< Offset 955 TRxDelay0
612 UINT8 TRxCableLength0; ///< Offset 956 TRxCableLength0
613 UINT8 TRxDelay1; ///< Offset 957 TRxDelay1
614 UINT8 TRxCableLength1; ///< Offset 958 TRxCableLength1
615 UINT8 WrddDomainType1; ///< Offset 959 WrddDomainType1
616 UINT16 WrddCountryIndentifier1; ///< Offset 960 WrddCountryIndentifier1
617 UINT8 WrddDomainType2; ///< Offset 962 WrddDomainType2
618 UINT16 WrddCountryIndentifier2; ///< Offset 963 WrddCountryIndentifier2
619 UINT8 Reserved12[53]; ///< Offset 965:1017
620 UINT8 EnableAPPolicy; ///< Offset 1018 Adaptive Performance Policy
621 UINT16 MinPowerLimit1; ///< Offset 1019 Minimum Power Limit 1 for DPTF use via PPCC Object
622 UINT16 MinPowerLimit2; ///< Offset 1021 Minimum Power Limit 2 for DPTF use via PPCC Object
623 //
624 // Intel Serial(R) IO Sensor Device Selection
625 //
626 UINT8 SDS0; ///< Offset 1023 SerialIo Devices for controller0
627 UINT8 SDS1; ///< Offset 1024 SerialIo Devices for controller1
628 UINT8 SDS2; ///< Offset 1025 SerialIo Devices for controller2
629 UINT8 SDS3; ///< Offset 1026 SerialIo Devices for controller3
630 UINT8 SDS4; ///< Offset 1027 SerialIo Devices for controller4
631 UINT8 SDS5; ///< Offset 1028 SerialIo Devices for controller5
632 UINT8 SDS6; ///< Offset 1029 SerialIo Devices for controller6
633 UINT8 SDS7; ///< Offset 1030 SerialIo Devices for controller7
634 UINT8 SDS8; ///< Offset 1031 SerialIo Devices for controller8
635 UINT8 SDS9; ///< Offset 1032 SerialIo Devices for controller9
636 UINT8 SDSA; ///< Offset 1033 SerialIo Devices for controller10
637 UINT8 TPLB; ///< Offset 1034 custom touchpanel's bus address
638 UINT16 TPLH; ///< Offset 1035 custom touchpanel's HID address
639 UINT8 WTVX; ///< Offset 1037 WITT test devices' version
640 UINT8 WITX; ///< Offset 1038 WITT test devices' connection point
641 UINT8 GPTD; ///< Offset 1039 GPIO test devices
642 UINT16 GDBT; ///< Offset 1040 GPIO test devices' debounce value,
643 UINT8 UTKX; ///< Offset 1042 UTK test devices' connection point
644 UINT8 SPTD; ///< Offset 1043 SerialIo additional test devices
645 UINT8 Reserved13[22]; ///< Offset 1044:1065
646 UINT32 TableLoadBuffer; ///< Offset 1066 Buffer for runtime ACPI Table loading
647 UINT8 SDM0; ///< Offset 1070 interrupt mode for controller0 devices
648 UINT8 SDM1; ///< Offset 1071 interrupt mode for controller1 devices
649 UINT8 SDM2; ///< Offset 1072 interrupt mode for controller2 devices
650 UINT8 SDM3; ///< Offset 1073 interrupt mode for controller3 devices
651 UINT8 SDM4; ///< Offset 1074 interrupt mode for controller4 devices
652 UINT8 SDM5; ///< Offset 1075 interrupt mode for controller5 devices
653 UINT8 SDM6; ///< Offset 1076 interrupt mode for controller6 devices
654 UINT8 SDM7; ///< Offset 1077 interrupt mode for controller7 devices
655 UINT8 SDM8; ///< Offset 1078 interrupt mode for controller8 devices
656 UINT8 SDM9; ///< Offset 1079 interrupt mode for controller9 devices
657 UINT8 SDMA; ///< Offset 1080 interrupt mode for controller10 devices
658 UINT8 SDMB; ///< Offset 1081 interrupt mode for controller11 devices
659 UINT8 Reserved14[1]; ///< Offset 1082:1082
660 UINT8 USTP; ///< Offset 1083 use SerialIo timing parameters
661 UINT8 Reserved15[41]; ///< Offset 1084:1124
662 UINT32 FingerPrintSleepGpio; ///< Offset 1125 Gpio for fingerprint sleep
663 UINT32 FingerPrintIrqGpio; ///< Offset 1129 Gpio for fingerprint irq
664 UINT8 DiscreteGnssModule; ///< Offset 1133 GNSS module and its interface, 0=disabled, 1=CG2000 over SerialIo Uart, 2=CG2000 over ISH Uart
665 UINT32 DiscreteGnssModuleResetGpio; ///< Offset 1134 Gpio for GNSS reset
666 UINT32 DiscreteBtModuleRfKillGpio; ///< Offset 1138 Gpio for Bluetooth RfKill
667 UINT32 DiscreteBtModuleIrqGpio; ///< Offset 1142 Gpio for Bluetooth interrupt
668 UINT32 TouchpadIrqGpio; ///< Offset 1146 Gpio for touchPaD Interrupt
669 UINT32 TouchpanelIrqGpio; ///< Offset 1150 Gpio for touchPaneL Interrupt
670 UINT8 DiscreteBtUartSupport; ///< Offset 1154 Switch to enable BT UART Support
671 UINT8 DiscreteGnssSupport; ///< Offset 1155 Switch to enable GNSS Support
672 //
673 // MipiCam specific
674 //
675 UINT8 MipiCamControlLogic0; ///< Offset 1156
676 UINT8 MipiCamControlLogic1; ///< Offset 1157
677 UINT8 MipiCamControlLogic2; ///< Offset 1158
678 UINT8 MipiCamControlLogic3; ///< Offset 1159
679 UINT8 MipiCamLink0Enabled; ///< Offset 1160
680 UINT8 MipiCamLink1Enabled; ///< Offset 1161
681 UINT8 MipiCamLink2Enabled; ///< Offset 1162
682 UINT8 MipiCamLink3Enabled; ///< Offset 1163
683 UINT8 MipiCamLanesClkDiv; ///< Offset 1164
684 // Control Logic 0 options
685 UINT8 MipiCamCtrlLogic0_Version; ///< Offset 1165 Version of CLDB structure
686 UINT8 MipiCamCtrlLogic0_Type; ///< Offset 1166 Type
687 UINT8 MipiCamCtrlLogic0_CrdVersion; ///< Offset 1167 Version of CRD
688 UINT32 MipiCamCtrlLogic0_InputClock; ///< Offset 1168 Input Clock
689 UINT8 MipiCamCtrlLogic0_GpioPinsEnabled; ///< Offset 1172 Number of GPIO Pins enabled
690 UINT8 MipiCamCtrlLogic0_I2cBus; ///< Offset 1173 I2C Serial Bus Number
691 UINT16 MipiCamCtrlLogic0_I2cAddress; ///< Offset 1174 I2C Address
692 UINT8 MipiCamCtrlLogic0_GpioGroupPadNumber[4]; ///< Offset 1176 GPIO Group Pad Number
693 UINT8 MipiCamCtrlLogic0_GpioGroupNumber[4]; ///< Offset 1180 GPIO Group Number
694 UINT8 MipiCamCtrlLogic0_GpioFunction[4]; ///< Offset 1184 GPIO Function
695 UINT8 MipiCamCtrlLogic0_GpioActiveValue[4]; ///< Offset 1188 GPIO Active Value
696 UINT8 MipiCamCtrlLogic0_GpioInitialValue[4]; ///< Offset 1192 GPIO Initial Value
697 UINT8 MipiCamCtrlLogic0_Pld; ///< Offset 1196 Camera Position
698 UINT8 MipiCamCtrlLogic0_Wled1FlashMaxCurrent; ///< Offset 1197 WLED1 Flash Max Current
699 UINT8 MipiCamCtrlLogic0_Wled1TorchMaxCurrent; ///< Offset 1198 WLED1 Torch Max Current
700 UINT8 MipiCamCtrlLogic0_Wled2FlashMaxCurrent; ///< Offset 1199 WLED2 Flash Max Current
701 UINT8 MipiCamCtrlLogic0_Wled2TorchMaxCurrent; ///< Offset 1200 WLED2 Torch Max Current
702 UINT8 MipiCamCtrlLogic0_SubPlatformId; ///< Offset 1201 Sub Platform Id
703 UINT8 MipiCamCtrlLogic0_Wled1Type; ///< Offset 1202 WLED1 Type
704 UINT8 MipiCamCtrlLogic0_Wled2Type; ///< Offset 1203 WLED2 Type
705 UINT8 MipiCamCtrlLogic0_PchClockSource; ///< Offset 1204 PCH Clock source
706 // Control Logic 1 options
707 UINT8 MipiCamCtrlLogic1_Version; ///< Offset 1205 Version of CLDB structure
708 UINT8 MipiCamCtrlLogic1_Type; ///< Offset 1206 Type
709 UINT8 MipiCamCtrlLogic1_CrdVersion; ///< Offset 1207 Version of CRD
710 UINT32 MipiCamCtrlLogic1_InputClock; ///< Offset 1208 Input Clock
711 UINT8 MipiCamCtrlLogic1_GpioPinsEnabled; ///< Offset 1212 Number of GPIO Pins enabled
712 UINT8 MipiCamCtrlLogic1_I2cBus; ///< Offset 1213 I2C Serial Bus Number
713 UINT16 MipiCamCtrlLogic1_I2cAddress; ///< Offset 1214 I2C Address
714 UINT8 MipiCamCtrlLogic1_GpioGroupPadNumber[4]; ///< Offset 1216 GPIO Group Pad Number
715 UINT8 MipiCamCtrlLogic1_GpioGroupNumber[4]; ///< Offset 1220 GPIO Group Number
716 UINT8 MipiCamCtrlLogic1_GpioFunction[4]; ///< Offset 1224 GPIO Function
717 UINT8 MipiCamCtrlLogic1_GpioActiveValue[4]; ///< Offset 1228 GPIO Active Value
718 UINT8 MipiCamCtrlLogic1_GpioInitialValue[4]; ///< Offset 1232 GPIO Initial Value
719 UINT8 MipiCamCtrlLogic1_Pld; ///< Offset 1236 Camera Position
720 UINT8 MipiCamCtrlLogic1_Wled1FlashMaxCurrent; ///< Offset 1237 WLED1 Flash Max Current
721 UINT8 MipiCamCtrlLogic1_Wled1TorchMaxCurrent; ///< Offset 1238 WLED1 Torch Max Current
722 UINT8 MipiCamCtrlLogic1_Wled2FlashMaxCurrent; ///< Offset 1239 WLED2 Flash Max Current
723 UINT8 MipiCamCtrlLogic1_Wled2TorchMaxCurrent; ///< Offset 1240 WLED2 Torch Max Current
724 UINT8 MipiCamCtrlLogic1_SubPlatformId; ///< Offset 1241 Sub Platform Id
725 UINT8 MipiCamCtrlLogic1_Wled1Type; ///< Offset 1242 WLED1 Type
726 UINT8 MipiCamCtrlLogic1_Wled2Type; ///< Offset 1243 WLED2 Type
727 UINT8 MipiCamCtrlLogic1_PchClockSource; ///< Offset 1244 PCH Clock source
728 // Control Logic 2 options
729 UINT8 MipiCamCtrlLogic2_Version; ///< Offset 1245 Version of CLDB structure
730 UINT8 MipiCamCtrlLogic2_Type; ///< Offset 1246 Type
731 UINT8 MipiCamCtrlLogic2_CrdVersion; ///< Offset 1247 Version of CRD
732 UINT32 MipiCamCtrlLogic2_InputClock; ///< Offset 1248 Input Clock
733 UINT8 MipiCamCtrlLogic2_GpioPinsEnabled; ///< Offset 1252 Number of GPIO Pins enabled
734 UINT8 MipiCamCtrlLogic2_I2cBus; ///< Offset 1253 I2C Serial Bus Number
735 UINT16 MipiCamCtrlLogic2_I2cAddress; ///< Offset 1254 I2C Address
736 UINT8 MipiCamCtrlLogic2_GpioGroupPadNumber[4]; ///< Offset 1256 GPIO Group Pad Number
737 UINT8 MipiCamCtrlLogic2_GpioGroupNumber[4]; ///< Offset 1260 GPIO Group Number
738 UINT8 MipiCamCtrlLogic2_GpioFunction[4]; ///< Offset 1264 GPIO Function
739 UINT8 MipiCamCtrlLogic2_GpioActiveValue[4]; ///< Offset 1268 GPIO Active Value
740 UINT8 MipiCamCtrlLogic2_GpioInitialValue[4]; ///< Offset 1272 GPIO Initial Value
741 UINT8 MipiCamCtrlLogic2_Pld; ///< Offset 1276 Camera Position
742 UINT8 MipiCamCtrlLogic2_Wled1FlashMaxCurrent; ///< Offset 1277 WLED1 Flash Max Current
743 UINT8 MipiCamCtrlLogic2_Wled1TorchMaxCurrent; ///< Offset 1278 WLED1 Torch Max Current
744 UINT8 MipiCamCtrlLogic2_Wled2FlashMaxCurrent; ///< Offset 1279 WLED2 Flash Max Current
745 UINT8 MipiCamCtrlLogic2_Wled2TorchMaxCurrent; ///< Offset 1280 WLED2 Torch Max Current
746 UINT8 MipiCamCtrlLogic2_SubPlatformId; ///< Offset 1281 Sub Platform Id
747 UINT8 MipiCamCtrlLogic2_Wled1Type; ///< Offset 1282 WLED1 Type
748 UINT8 MipiCamCtrlLogic2_Wled2Type; ///< Offset 1283 WLED2 Type
749 UINT8 MipiCamCtrlLogic2_PchClockSource; ///< Offset 1284 PCH Clock source
750 // Control Logic 3 options
751 UINT8 MipiCamCtrlLogic3_Version; ///< Offset 1285 Version of CLDB structure
752 UINT8 MipiCamCtrlLogic3_Type; ///< Offset 1286 Type
753 UINT8 MipiCamCtrlLogic3_CrdVersion; ///< Offset 1287 Version of CRD
754 UINT32 MipiCamCtrlLogic3_InputClock; ///< Offset 1288 Input Clock
755 UINT8 MipiCamCtrlLogic3_GpioPinsEnabled; ///< Offset 1292 Number of GPIO Pins enabled
756 UINT8 MipiCamCtrlLogic3_I2cBus; ///< Offset 1293 I2C Serial Bus Number
757 UINT16 MipiCamCtrlLogic3_I2cAddress; ///< Offset 1294 I2C Address
758 UINT8 MipiCamCtrlLogic3_GpioGroupPadNumber[4]; ///< Offset 1296 GPIO Group Pad Number
759 UINT8 MipiCamCtrlLogic3_GpioGroupNumber[4]; ///< Offset 1300 GPIO Group Number
760 UINT8 MipiCamCtrlLogic3_GpioFunction[4]; ///< Offset 1304 GPIO Function
761 UINT8 MipiCamCtrlLogic3_GpioActiveValue[4]; ///< Offset 1308 GPIO Active Value
762 UINT8 MipiCamCtrlLogic3_GpioInitialValue[4]; ///< Offset 1312 GPIO Initial Value
763 UINT8 MipiCamCtrlLogic3_Pld; ///< Offset 1316 Camera Position
764 UINT8 MipiCamCtrlLogic3_Wled1FlashMaxCurrent; ///< Offset 1317 WLED1 Flash Max Current
765 UINT8 MipiCamCtrlLogic3_Wled1TorchMaxCurrent; ///< Offset 1318 WLED1 Torch Max Current
766 UINT8 MipiCamCtrlLogic3_Wled2FlashMaxCurrent; ///< Offset 1319 WLED2 Flash Max Current
767 UINT8 MipiCamCtrlLogic3_Wled2TorchMaxCurrent; ///< Offset 1320 WLED2 Torch Max Current
768 UINT8 MipiCamCtrlLogic3_SubPlatformId; ///< Offset 1321 Sub Platform Id
769 UINT8 MipiCamCtrlLogic3_Wled1Type; ///< Offset 1322 WLED1 Type
770 UINT8 MipiCamCtrlLogic3_Wled2Type; ///< Offset 1323 WLED2 Type
771 UINT8 MipiCamCtrlLogic3_PchClockSource; ///< Offset 1324 PCH Clock source
772 // Mipi Cam Link0 options
773 UINT8 MipiCamLink0SensorModel; ///< Offset 1325 Sensor Model
774 UINT8 MipiCamLink0UserHid[9]; ///< Offset 1326 User defined HID ASCII character 0
775 ///< Offset 1334 User defined HID ASCII character 8
776 UINT8 MipiCamLink0Pld; ///< Offset 1335 Camera Position
777 UINT8 MipiCamLink0ModuleName[16]; ///< Offset 1336 Camera Module Name ASCII character 0
778 ///< Offset 1351 Camera Module Name ASCII character 15
779 UINT8 MipiCamLink0I2cDevicesEnabled; ///< Offset 1352 Number of I2C devices
780 UINT8 MipiCamLink0I2cBus; ///< Offset 1353 I2C Serial Bus number
781 UINT16 MipiCamLink0I2cAddrDev[12]; ///< Offset 1354 Address of I2C Device0 on Link0
782 ///< Offset 1356 Address of I2C Device1 on Link0
783 ///< Offset 1358 Address of I2C Device2 on Link0
784 ///< Offset 1360 Address of I2C Device3 on Link0
785 ///< Offset 1362 Address of I2C Device4 on Link0
786 ///< Offset 1364 Address of I2C Device5 on Link0
787 ///< Offset 1366 Address of I2C Device6 on Link0
788 ///< Offset 1368 Address of I2C Device7 on Link0
789 ///< Offset 1370 Address of I2C Device8 on Link0
790 ///< Offset 1372 Address of I2C Device9 on Link0
791 ///< Offset 1374 Address of I2C Device10 on Link0
792 ///< Offset 1376 Address of I2C Device11 on Link0
793 UINT8 MipiCamLink0I2cDeviceType[12]; ///< Offset 1378 Type of I2C Device0 on Link0
794 ///< Offset 1379 Type of I2C Device1 on Link0
795 ///< Offset 1380 Type of I2C Device2 on Link0
796 ///< Offset 1381 Type of I2C Device3 on Link0
797 ///< Offset 1382 Type of I2C Device4 on Link0
798 ///< Offset 1383 Type of I2C Device5 on Link0
799 ///< Offset 1384 Type of I2C Device6 on Link0
800 ///< Offset 1385 Type of I2C Device7 on Link0
801 ///< Offset 1386 Type of I2C Device8 on Link0
802 ///< Offset 1387 Type of I2C Device9 on Link0
803 ///< Offset 1388 Type of I2C Device10 on Link0
804 ///< Offset 1389 Type of I2C Device11 on Link0
805 UINT8 MipiCamLink0DD_Version; ///< Offset 1390 Version of SSDB structure
806 UINT8 MipiCamLink0DD_CrdVersion; ///< Offset 1391 Version of CRD
807 UINT8 MipiCamLink0DD_LinkUsed; ///< Offset 1392 CSI2 Link used
808 UINT8 MipiCamLink0DD_LaneUsed; ///< Offset 1393 MIPI-CSI2 Data Lane
809 UINT8 MipiCamLink0DD_EepromType; ///< Offset 1394 EEPROM Type
810 UINT8 MipiCamLink0DD_VcmType; ///< Offset 1395 VCM Type
811 UINT8 MipiCamLink0DD_FlashSupport; ///< Offset 1396 Flash Support
812 UINT8 MipiCamLink0DD_PrivacyLed; ///< Offset 1397 Privacy LED
813 UINT8 MipiCamLink0DD_Degree; ///< Offset 1398 Degree
814 UINT32 MipiCamLink0DD_Mclk; ///< Offset 1399 MCLK
815 UINT8 MipiCamLink0DD_ControlLogic; ///< Offset 1403 Control Logic
816 UINT8 MipiCamLink0DD_PmicPosition; ///< Offset 1404 PMIC Position
817 UINT8 MipiCamLink0DD_VoltageRail; ///< Offset 1405 Voltage Rail
818 // Mipi Cam Link1 options
819 UINT8 MipiCamLink1SensorModel; ///< Offset 1406 Sensor Model
820 UINT8 MipiCamLink1UserHid[9]; ///< Offset 1407 User defined HID ASCII character 0
821 ///< Offset 1415 User defined HID ASCII character 8
822 UINT8 MipiCamLink1Pld; ///< Offset 1416 Camera Position
823 UINT8 MipiCamLink1ModuleName[16]; ///< Offset 1417 Camera Module Name ASCII character 0
824 ///< Offset 1432 Camera Module Name ASCII character 15
825 UINT8 MipiCamLink1I2cDevicesEnabled; ///< Offset 1433 Number of I2C devices
826 UINT8 MipiCamLink1I2cBus; ///< Offset 1434 I2C Serial Bus number
827 UINT16 MipiCamLink1I2cAddrDev[12]; ///< Offset 1435 Address of I2C Device0 on Link1
828 ///< Offset 1437 Address of I2C Device1 on Link1
829 ///< Offset 1439 Address of I2C Device2 on Link1
830 ///< Offset 1441 Address of I2C Device3 on Link1
831 ///< Offset 1443 Address of I2C Device4 on Link1
832 ///< Offset 1445 Address of I2C Device5 on Link1
833 ///< Offset 1447 Address of I2C Device6 on Link1
834 ///< Offset 1449 Address of I2C Device7 on Link1
835 ///< Offset 1451 Address of I2C Device8 on Link1
836 ///< Offset 1453 Address of I2C Device9 on Link1
837 ///< Offset 1455 Address of I2C Device10 on Link1
838 ///< Offset 1457 Address of I2C Device11 on Link1
839 UINT8 MipiCamLink1I2cDeviceType[12]; ///< Offset 1459 Type of I2C Device0 on Link1
840 ///< Offset 1460 Type of I2C Device1 on Link1
841 ///< Offset 1461 Type of I2C Device2 on Link1
842 ///< Offset 1462 Type of I2C Device3 on Link1
843 ///< Offset 1463 Type of I2C Device4 on Link1
844 ///< Offset 1464 Type of I2C Device5 on Link1
845 ///< Offset 1465 Type of I2C Device6 on Link1
846 ///< Offset 1466 Type of I2C Device7 on Link1
847 ///< Offset 1467 Type of I2C Device8 on Link1
848 ///< Offset 1468 Type of I2C Device9 on Link1
849 ///< Offset 1469 Type of I2C Device10 on Link1
850 ///< Offset 1470 Type of I2C Device11 on Link1
851 UINT8 MipiCamLink1DD_Version; ///< Offset 1471 Version of SSDB structure
852 UINT8 MipiCamLink1DD_CrdVersion; ///< Offset 1472 Version of CRD
853 UINT8 MipiCamLink1DD_LinkUsed; ///< Offset 1473 CSI2 Link used
854 UINT8 MipiCamLink1DD_LaneUsed; ///< Offset 1474 MIPI-CSI2 Data Lane
855 UINT8 MipiCamLink1DD_EepromType; ///< Offset 1475 EEPROM Type
856 UINT8 MipiCamLink1DD_VcmType; ///< Offset 1476 VCM Type
857 UINT8 MipiCamLink1DD_FlashSupport; ///< Offset 1477 Flash Support
858 UINT8 MipiCamLink1DD_PrivacyLed; ///< Offset 1478 Privacy LED
859 UINT8 MipiCamLink1DD_Degree; ///< Offset 1479 Degree
860 UINT32 MipiCamLink1DD_Mclk; ///< Offset 1480 MCLK
861 UINT8 MipiCamLink1DD_ControlLogic; ///< Offset 1484 Control Logic
862 UINT8 MipiCamLink1DD_PmicPosition; ///< Offset 1485 PMIC Position
863 UINT8 MipiCamLink1DD_VoltageRail; ///< Offset 1486 Voltage Rail
864 // Mipi Cam Link2 options
865 UINT8 MipiCamLink2SensorModel; ///< Offset 1487 Sensor Model
866 UINT8 MipiCamLink2UserHid[9]; ///< Offset 1488 User defined HID ASCII character 0
867 ///< Offset 1496 User defined HID ASCII character 8
868 UINT8 MipiCamLink2Pld; ///< Offset 1497 Camera Position
869 UINT8 MipiCamLink2ModuleName[16]; ///< Offset 1498 Camera Module Name ASCII character 0
870 ///< Offset 1513 Camera Module Name ASCII character 15
871 UINT8 MipiCamLink2I2cDevicesEnabled; ///< Offset 1514 Number of I2C devices
872 UINT8 MipiCamLink2I2cBus; ///< Offset 1515 I2C Serial Bus number
873 UINT16 MipiCamLink2I2cAddrDev[12]; ///< Offset 1516 Address of I2C Device0 on Link2
874 ///< Offset 1518 Address of I2C Device1 on Link2
875 ///< Offset 1520 Address of I2C Device2 on Link2
876 ///< Offset 1522 Address of I2C Device3 on Link2
877 ///< Offset 1524 Address of I2C Device4 on Link2
878 ///< Offset 1526 Address of I2C Device5 on Link2
879 ///< Offset 1528 Address of I2C Device6 on Link2
880 ///< Offset 1530 Address of I2C Device7 on Link2
881 ///< Offset 1532 Address of I2C Device8 on Link2
882 ///< Offset 1534 Address of I2C Device9 on Link2
883 ///< Offset 1536 Address of I2C Device10 on Link2
884 ///< Offset 1538 Address of I2C Device11 on Link2
885 UINT8 MipiCamLink2I2cDeviceType[12]; ///< Offset 1540 Type of I2C Device0 on Link2
886 ///< Offset 1541 Type of I2C Device1 on Link2
887 ///< Offset 1542 Type of I2C Device2 on Link2
888 ///< Offset 1543 Type of I2C Device3 on Link2
889 ///< Offset 1544 Type of I2C Device4 on Link2
890 ///< Offset 1545 Type of I2C Device5 on Link2
891 ///< Offset 1546 Type of I2C Device6 on Link2
892 ///< Offset 1547 Type of I2C Device7 on Link2
893 ///< Offset 1548 Type of I2C Device8 on Link2
894 ///< Offset 1549 Type of I2C Device9 on Link2
895 ///< Offset 1550 Type of I2C Device10 on Link2
896 ///< Offset 1551 Type of I2C Device11 on Link2
897 UINT8 MipiCamLink2DD_Version; ///< Offset 1552 Version of SSDB structure
898 UINT8 MipiCamLink2DD_CrdVersion; ///< Offset 1553 Version of CRD
899 UINT8 MipiCamLink2DD_LinkUsed; ///< Offset 1554 CSI2 Link used
900 UINT8 MipiCamLink2DD_LaneUsed; ///< Offset 1555 MIPI-CSI2 Data Lane
901 UINT8 MipiCamLink2DD_EepromType; ///< Offset 1556 EEPROM Type
902 UINT8 MipiCamLink2DD_VcmType; ///< Offset 1557 VCM Type
903 UINT8 MipiCamLink2DD_FlashSupport; ///< Offset 1558 Flash Support
904 UINT8 MipiCamLink2DD_PrivacyLed; ///< Offset 1559 Privacy LED
905 UINT8 MipiCamLink2DD_Degree; ///< Offset 1560 Degree
906 UINT32 MipiCamLink2DD_Mclk; ///< Offset 1561 MCLK
907 UINT8 MipiCamLink2DD_ControlLogic; ///< Offset 1565 Control Logic
908 UINT8 MipiCamLink2DD_PmicPosition; ///< Offset 1566 PMIC Position
909 UINT8 MipiCamLink2DD_VoltageRail; ///< Offset 1567 Voltage Rail
910 // Mipi Cam Link3 options
911 UINT8 MipiCamLink3SensorModel; ///< Offset 1568 Sensor Model
912 UINT8 MipiCamLink3UserHid[9]; ///< Offset 1569 User defined HID ASCII character 0
913 ///< Offset 1577 User defined HID ASCII character 8
914 UINT8 MipiCamLink3Pld; ///< Offset 1578 Camera Position
915 UINT8 MipiCamLink3ModuleName[16]; ///< Offset 1579 Camera Module Name ASCII character 0
916 ///< Offset 1594 Camera Module Name ASCII character 15
917 UINT8 MipiCamLink3I2cDevicesEnabled; ///< Offset 1595 Number of I2C devices
918 UINT8 MipiCamLink3I2cBus; ///< Offset 1596 I2C Serial Bus number
919 UINT16 MipiCamLink3I2cAddrDev[12]; ///< Offset 1597 Address of I2C Device0 on Link3
920 ///< Offset 1599 Address of I2C Device1 on Link3
921 ///< Offset 1601 Address of I2C Device2 on Link3
922 ///< Offset 1603 Address of I2C Device3 on Link3
923 ///< Offset 1605 Address of I2C Device4 on Link3
924 ///< Offset 1607 Address of I2C Device5 on Link3
925 ///< Offset 1609 Address of I2C Device6 on Link3
926 ///< Offset 1611 Address of I2C Device7 on Link3
927 ///< Offset 1613 Address of I2C Device8 on Link3
928 ///< Offset 1615 Address of I2C Device9 on Link3
929 ///< Offset 1617 Address of I2C Device10 on Link3
930 ///< Offset 1619 Address of I2C Device11 on Link3
931 UINT8 MipiCamLink3I2cDeviceType[12]; ///< Offset 1621 Type of I2C Device0 on Link3
932 ///< Offset 1622 Type of I2C Device1 on Link3
933 ///< Offset 1623 Type of I2C Device2 on Link3
934 ///< Offset 1624 Type of I2C Device3 on Link3
935 ///< Offset 1625 Type of I2C Device4 on Link3
936 ///< Offset 1626 Type of I2C Device5 on Link3
937 ///< Offset 1627 Type of I2C Device6 on Link3
938 ///< Offset 1628 Type of I2C Device7 on Link3
939 ///< Offset 1629 Type of I2C Device8 on Link3
940 ///< Offset 1630 Type of I2C Device9 on Link3
941 ///< Offset 1631 Type of I2C Device10 on Link3
942 ///< Offset 1632 Type of I2C Device11 on Link3
943 UINT8 MipiCamLink3DD_Version; ///< Offset 1633 Version of SSDB structure
944 UINT8 MipiCamLink3DD_CrdVersion; ///< Offset 1634 Version of CRD
945 UINT8 MipiCamLink3DD_LinkUsed; ///< Offset 1635 CSI2 Link used
946 UINT8 MipiCamLink3DD_LaneUsed; ///< Offset 1636 MIPI-CSI2 Data Lane
947 UINT8 MipiCamLink3DD_EepromType; ///< Offset 1637 EEPROM Type
948 UINT8 MipiCamLink3DD_VcmType; ///< Offset 1638 VCM Type
949 UINT8 MipiCamLink3DD_FlashSupport; ///< Offset 1639 Flash Support
950 UINT8 MipiCamLink3DD_PrivacyLed; ///< Offset 1640 Privacy LED
951 UINT8 MipiCamLink3DD_Degree; ///< Offset 1641 Degree
952 UINT32 MipiCamLink3DD_Mclk; ///< Offset 1642 MCLK
953 UINT8 MipiCamLink3DD_ControlLogic; ///< Offset 1646 Control Logic
954 UINT8 MipiCamLink3DD_PmicPosition; ///< Offset 1647 PMIC Position
955 UINT8 MipiCamLink3DD_VoltageRail; ///< Offset 1648 Voltage Rail
956 UINT8 Reserved16[6]; ///< Offset 1649:1654
957 UINT8 PciDelayOptimizationEcr; ///< Offset 1655
958 UINT8 I2SC; ///< Offset 1656 HD Audio I2S Codec Selection
959 UINT32 I2SI; ///< Offset 1657 HD Audio I2S Codec Interrupt Pin
960 UINT8 OemDesignVariable0; ///< Offset 1661 DPTF Oem Design Variables
961 UINT8 OemDesignVariable1; ///< Offset 1662 DPTF Oem Design Variables
962 UINT8 OemDesignVariable2; ///< Offset 1663 DPTF Oem Design Variables
963 UINT8 OemDesignVariable3; ///< Offset 1664 DPTF Oem Design Variables
964 UINT8 OemDesignVariable4; ///< Offset 1665 DPTF Oem Design Variables
965 UINT8 OemDesignVariable5; ///< Offset 1666 DPTF Oem Design Variables
966 UINT32 UsbTypeCOpBaseAddr; ///< Offset 1667 USB Type C Opregion base address
967 UINT8 Reserved17[1]; ///< Offset 1671:1671
968 UINT8 WirelessCharging; ///< Offset 1672 WirelessCharging
969 // RTD3 Settings
970 UINT8 Reserved19[7]; ///< Offset 1673:1679
971 UINT8 TPLS; ///< Offset 1680 custom touchpanel's bus speed
972 UINT8 TPDB; ///< Offset 1681 custom touchpad's bus address
973 UINT16 TPDH; ///< Offset 1682 custom touchpad's HID address
974 UINT8 TPDS; ///< Offset 1684 custom touchpad's bus speed
975 UINT32 HdaDspPpModuleMask; ///< Offset 1685 HD-Audio DSP Post-Processing Module Mask
976 UINT64 HdaDspPpModCustomGuid1Low; ///< Offset 1689 HDA PP module custom GUID 1 - first 64bit [0-63]
977 UINT64 HdaDspPpModCustomGuid1High; ///< Offset 1697 HDA PP module custom GUID 1 - second 64bit [64-127]
978 UINT64 HdaDspPpModCustomGuid2Low; ///< Offset 1705 HDA PP module custom GUID 2 - first 64bit [0-63]
979 UINT64 HdaDspPpModCustomGuid2High; ///< Offset 1713 HDA PP module custom GUID 2 - second 64bit [64-127]
980 UINT64 HdaDspPpModCustomGuid3Low; ///< Offset 1721 HDA PP module custom GUID 3 - first 64bit [0-63]
981 UINT64 HdaDspPpModCustomGuid3High; ///< Offset 1729 HDA PP module custom GUID 3 - second 64bit [64-127]
982 UINT8 HidEventFilterEnable; ///< Offset 1737 HID Event Filter Driver enable
983 UINT8 XdciFnEnable; ///< Offset 1738 XDCI Enable/Disable status
984 UINT8 WrdsWiFiSarEnable; ///< Offset 1739 WrdsWiFiSarEnable
985 UINT8 WrdsWiFiSarTxPowerSet1Limit1; ///< Offset 1740 WrdsWiFiSarTxPowerSet1Limit1
986 UINT8 WrdsWiFiSarTxPowerSet1Limit2; ///< Offset 1741 WrdsWiFiSarTxPowerSet1Limit2
987 UINT8 WrdsWiFiSarTxPowerSet1Limit3; ///< Offset 1742 WrdsWiFiSarTxPowerSet1Limit3
988 UINT8 WrdsWiFiSarTxPowerSet1Limit4; ///< Offset 1743 WrdsWiFiSarTxPowerSet1Limit4
989 UINT8 WrdsWiFiSarTxPowerSet1Limit5; ///< Offset 1744 WrdsWiFiSarTxPowerSet1Limit5
990 UINT8 WrdsWiFiSarTxPowerSet1Limit6; ///< Offset 1745 WrdsWiFiSarTxPowerSet1Limit6
991 UINT8 WrdsWiFiSarTxPowerSet1Limit7; ///< Offset 1746 WrdsWiFiSarTxPowerSet1Limit7
992 UINT8 WrdsWiFiSarTxPowerSet1Limit8; ///< Offset 1747 WrdsWiFiSarTxPowerSet1Limit8
993 UINT8 WrdsWiFiSarTxPowerSet1Limit9; ///< Offset 1748 WrdsWiFiSarTxPowerSet1Limit9
994 UINT8 WrdsWiFiSarTxPowerSet1Limit10; ///< Offset 1749 WrdsWiFiSarTxPowerSet1Limit10
995 UINT8 EnableVoltageMargining; ///< Offset 1750 Enable Voltage Margining
996 UINT16 DStateHSPort; ///< Offset 1751 D-State for xHCI HS port(BIT0:USB HS Port0 ~ BIT15:USB HS Port15)
997 UINT16 DStateSSPort; ///< Offset 1753 D-State for xHCI SS port(BIT0:USB SS Port0 ~ BIT15:USB SS Port15)
998 UINT8 DStateSataPort; ///< Offset 1755 D-State for SATA port(BIT0:SATA Port0 ~ BIT7:SATA Port7)
999 UINT8 WigigRfe; ///< Offset 1756 WigigRfe
1000 UINT8 WiGigRfeCh1; ///< Offset 1757 WiGigRfeCh1
1001 UINT8 WiGigRfeCh2; ///< Offset 1758 WiGigRfeCh2
1002 UINT8 WiGigRfeCh3; ///< Offset 1759 WiGigRfeCh3
1003 UINT8 WiGigRfeCh4; ///< Offset 1760 WiGigRfeCh4
1004 UINT32 AwvClassIndex; ///< Offset 1761 AwvClassIndex
1005 UINT8 EwrdWiFiDynamicSarEnable; ///< Offset 1765 EwrdWiFiDynamicSarEnable
1006 UINT8 EwrdWiFiDynamicSarRangeSets; ///< Offset 1766 EwrdWiFiDynamicSarRangeSets
1007 UINT8 EwrdWiFiSarTxPowerSet2Limit1; ///< Offset 1767 EwrdWiFiSarTxPowerSet2Limit1
1008 UINT8 EwrdWiFiSarTxPowerSet2Limit2; ///< Offset 1768 EwrdWiFiSarTxPowerSet2Limit2
1009 UINT8 EwrdWiFiSarTxPowerSet2Limit3; ///< Offset 1769 EwrdWiFiSarTxPowerSet2Limit3
1010 UINT8 EwrdWiFiSarTxPowerSet2Limit4; ///< Offset 1770 EwrdWiFiSarTxPowerSet2Limit4
1011 UINT8 EwrdWiFiSarTxPowerSet2Limit5; ///< Offset 1771 EwrdWiFiSarTxPowerSet2Limit5
1012 UINT8 EwrdWiFiSarTxPowerSet2Limit6; ///< Offset 1772 EwrdWiFiSarTxPowerSet2Limit6
1013 UINT8 EwrdWiFiSarTxPowerSet2Limit7; ///< Offset 1773 EwrdWiFiSarTxPowerSet2Limit7
1014 UINT8 EwrdWiFiSarTxPowerSet2Limit8; ///< Offset 1774 EwrdWiFiSarTxPowerSet2Limit8
1015 UINT8 EwrdWiFiSarTxPowerSet2Limit9; ///< Offset 1775 EwrdWiFiSarTxPowerSet2Limit9
1016 UINT8 EwrdWiFiSarTxPowerSet2Limit10; ///< Offset 1776 EwrdWiFiSarTxPowerSet2Limit10
1017 UINT8 EwrdWiFiSarTxPowerSet3Limit1; ///< Offset 1777 EwrdWiFiSarTxPowerSet3Limit1
1018 UINT8 EwrdWiFiSarTxPowerSet3Limit2; ///< Offset 1778 EwrdWiFiSarTxPowerSet3Limit2
1019 UINT8 EwrdWiFiSarTxPowerSet3Limit3; ///< Offset 1779 EwrdWiFiSarTxPowerSet3Limit3
1020 UINT8 EwrdWiFiSarTxPowerSet3Limit4; ///< Offset 1780 EwrdWiFiSarTxPowerSet3Limit4
1021 UINT8 EwrdWiFiSarTxPowerSet3Limit5; ///< Offset 1781 EwrdWiFiSarTxPowerSet3Limit5
1022 UINT8 EwrdWiFiSarTxPowerSet3Limit6; ///< Offset 1782 EwrdWiFiSarTxPowerSet3Limit6
1023 UINT8 EwrdWiFiSarTxPowerSet3Limit7; ///< Offset 1783 EwrdWiFiSarTxPowerSet3Limit7
1024 UINT8 EwrdWiFiSarTxPowerSet3Limit8; ///< Offset 1784 EwrdWiFiSarTxPowerSet3Limit8
1025 UINT8 EwrdWiFiSarTxPowerSet3Limit9; ///< Offset 1785 EwrdWiFiSarTxPowerSet3Limit9
1026 UINT8 EwrdWiFiSarTxPowerSet3Limit10; ///< Offset 1786 EwrdWiFiSarTxPowerSet3Limit10
1027 UINT8 EwrdWiFiSarTxPowerSet4Limit1; ///< Offset 1787 EwrdWiFiSarTxPowerSet4Limit1
1028 UINT8 EwrdWiFiSarTxPowerSet4Limit2; ///< Offset 1788 EwrdWiFiSarTxPowerSet4Limit2
1029 UINT8 EwrdWiFiSarTxPowerSet4Limit3; ///< Offset 1789 EwrdWiFiSarTxPowerSet4Limit3
1030 UINT8 EwrdWiFiSarTxPowerSet4Limit4; ///< Offset 1790 EwrdWiFiSarTxPowerSet4Limit4
1031 UINT8 EwrdWiFiSarTxPowerSet4Limit5; ///< Offset 1791 EwrdWiFiSarTxPowerSet4Limit5
1032 UINT8 EwrdWiFiSarTxPowerSet4Limit6; ///< Offset 1792 EwrdWiFiSarTxPowerSet4Limit6
1033 UINT8 EwrdWiFiSarTxPowerSet4Limit7; ///< Offset 1793 EwrdWiFiSarTxPowerSet4Limit7
1034 UINT8 EwrdWiFiSarTxPowerSet4Limit8; ///< Offset 1794 EwrdWiFiSarTxPowerSet4Limit8
1035 UINT8 EwrdWiFiSarTxPowerSet4Limit9; ///< Offset 1795 EwrdWiFiSarTxPowerSet4Limit9
1036 UINT8 EwrdWiFiSarTxPowerSet4Limit10; ///< Offset 1796 EwrdWiFiSarTxPowerSet4Limit10
1037 UINT8 WgdsWiFiSarDeltaGroup1PowerMax1; ///< Offset 1797 WgdsWiFiSarDeltaGroup1PowerMax1
1038 UINT8 WgdsWiFiSarDeltaGroup1PowerChainA1; ///< Offset 1798 WgdsWiFiSarDeltaGroup1PowerChainA1
1039 UINT8 WgdsWiFiSarDeltaGroup1PowerChainB1; ///< Offset 1799 WgdsWiFiSarDeltaGroup1PowerChainB1
1040 UINT8 WgdsWiFiSarDeltaGroup1PowerMax2; ///< Offset 1800 WgdsWiFiSarDeltaGroup1PowerMax2
1041 UINT8 WgdsWiFiSarDeltaGroup1PowerChainA2; ///< Offset 1801 WgdsWiFiSarDeltaGroup1PowerChainA2
1042 UINT8 WgdsWiFiSarDeltaGroup1PowerChainB2; ///< Offset 1802 WgdsWiFiSarDeltaGroup1PowerChainB2
1043 UINT8 WgdsWiFiSarDeltaGroup2PowerMax1; ///< Offset 1803 WgdsWiFiSarDeltaGroup2PowerMax1
1044 UINT8 WgdsWiFiSarDeltaGroup2PowerChainA1; ///< Offset 1804 WgdsWiFiSarDeltaGroup2PowerChainA1
1045 UINT8 WgdsWiFiSarDeltaGroup2PowerChainB1; ///< Offset 1805 WgdsWiFiSarDeltaGroup2PowerChainB1
1046 UINT8 WgdsWiFiSarDeltaGroup2PowerMax2; ///< Offset 1806 WgdsWiFiSarDeltaGroup2PowerMax2
1047 UINT8 WgdsWiFiSarDeltaGroup2PowerChainA2; ///< Offset 1807 WgdsWiFiSarDeltaGroup2PowerChainA2
1048 UINT8 WgdsWiFiSarDeltaGroup2PowerChainB2; ///< Offset 1808 WgdsWiFiSarDeltaGroup2PowerChainB2
1049 UINT8 WgdsWiFiSarDeltaGroup3PowerMax1; ///< Offset 1809 WgdsWiFiSarDeltaGroup3PowerMax1
1050 UINT8 WgdsWiFiSarDeltaGroup3PowerChainA1; ///< Offset 1810 WgdsWiFiSarDeltaGroup3PowerChainA1
1051 UINT8 WgdsWiFiSarDeltaGroup3PowerChainB1; ///< Offset 1811 WgdsWiFiSarDeltaGroup3PowerChainB1
1052 UINT8 WgdsWiFiSarDeltaGroup3PowerMax2; ///< Offset 1812 WgdsWiFiSarDeltaGroup3PowerMax2
1053 UINT8 WgdsWiFiSarDeltaGroup3PowerChainA2; ///< Offset 1813 WgdsWiFiSarDeltaGroup3PowerChainA2
1054 UINT8 WgdsWiFiSarDeltaGroup3PowerChainB2; ///< Offset 1814 WgdsWiFiSarDeltaGroup3PowerChainB2
1055 UINT8 Reserved20[27]; ///< Offset 1815:1841
1056 // Reserved for Groups 4 to 9, each needs 6 bytes and total 36 bytes reserved
1057 UINT8 WiFiDynamicSarAntennaACurrentSet; ///< Offset 1842 WiFiDynamicSarAntennaACurrentSet
1058 UINT8 WiFiDynamicSarAntennaBCurrentSet; ///< Offset 1843 WiFiDynamicSarAntennaBCurrentSet
1059 UINT8 BluetoothSar; ///< Offset 1844 BluetoothSar
1060 UINT8 BluetoothSarBr; ///< Offset 1845 BluetoothSarBr
1061 UINT8 BluetoothSarEdr2; ///< Offset 1846 BluetoothSarEdr2
1062 UINT8 BluetoothSarEdr3; ///< Offset 1847 BluetoothSarEdr3
1063 UINT8 BluetoothSarLe; ///< Offset 1848 BluetoothSarLe
1064 UINT8 Reserved21[4]; ///< Offset 1849:1852
1065 // Reserved for Bluetooth Sar future use
1066 UINT8 CoExistenceManager; ///< Offset 1853 CoExistenceManager
1067 UINT8 RunTimeVmControl; ///< Offset 1854 RunTime VM Control
1068 //
1069 //Feature Specific Data Bits
1070 //
1071 UINT8 UsbTypeCSupport; ///< Offset 1855 USB Type C Supported
1072 UINT32 HebcValue; ///< Offset 1856 HebcValue
1073 UINT8 PcdBatteryPresent; ///< Offset 1860 Battery Present - Bit0: Real Battery is supported on this platform. Bit1: Virtual Battery is supported on this platform.
1074 UINT8 PcdTsOnDimmTemperature; ///< Offset 1861 TS-on-DIMM temperature
1075 UINT8 Reserved22[3]; ///< Offset 1862:1864
1076 UINT8 PcdRealBattery1Control; ///< Offset 1865 Real Battery 1 Control
1077 UINT8 PcdRealBattery2Control; ///< Offset 1866 Real Battery 2 Control
1078 UINT8 PcdMipiCamSensor; ///< Offset 1867 Mipi Camera Sensor
1079 UINT8 PcdNCT6776FCOM; ///< Offset 1868 NCT6776F COM
1080 UINT8 PcdNCT6776FSIO; ///< Offset 1869 NCT6776F SIO
1081 UINT8 PcdNCT6776FHWMON; ///< Offset 1870 NCT6776F HWMON
1082 UINT8 PcdH8S2113SIO; ///< Offset 1871 H8S2113 SIO
1083 UINT8 PcdPowerParticipant; ///< Offset 1872 Power Participant
1084 UINT8 PcdZPoddConfig; ///< Offset 1873 ZPODD
1085 UINT8 PcdRGBCameraAdr; ///< Offset 1874 RGB Camera Address
1086 UINT8 PcdDepthCameraAdr; ///< Offset 1875 Depth Camera Addresy
1087 UINT32 PcdSmcRuntimeSciPin; ///< Offset 1876 SMC Runtime Sci Pin
1088 UINT8 PcdConvertableDockSupport; ///< Offset 1880 Convertable Dock Support
1089 UINT8 PcdEcHotKeyF3Support; ///< Offset 1881 Ec Hotkey F3 Support
1090 UINT8 PcdEcHotKeyF4Support; ///< Offset 1882 Ec Hotkey F4 Support
1091 UINT8 PcdEcHotKeyF5Support; ///< Offset 1883 Ec Hotkey F5 Support
1092 UINT8 PcdEcHotKeyF6Support; ///< Offset 1884 Ec Hotkey F6 Support
1093 UINT8 PcdEcHotKeyF7Support; ///< Offset 1885 Ec Hotkey F7 Support
1094 UINT8 PcdEcHotKeyF8Support; ///< Offset 1886 Ec Hotkey F8 Support
1095 UINT8 PcdVirtualButtonVolumeUpSupport; ///< Offset 1887 Virtual Button Volume Up Support
1096 UINT8 PcdVirtualButtonVolumeDownSupport; ///< Offset 1888 Virtual Button Volume Down Support
1097 UINT8 PcdVirtualButtonHomeButtonSupport; ///< Offset 1889 Virtual Button Home Button Support
1098 UINT8 PcdVirtualButtonRotationLockSupport; ///< Offset 1890 Virtual Button Rotation Lock Support
1099 UINT8 PcdSlateModeSwitchSupport; ///< Offset 1891 Slate Mode Switch Support
1100 UINT8 PcdVirtualGpioButtonSupport; ///< Offset 1892 Virtual Button Support
1101 UINT8 PcdAcDcAutoSwitchSupport; ///< Offset 1893 Ac Dc Auto Switch Support
1102 UINT32 PcdPmPowerButtonGpioPin; ///< Offset 1894 Pm Power Button Gpio Pin
1103 UINT8 PcdAcpiEnableAllButtonSupport; ///< Offset 1898 Acpi Enable All Button Support
1104 UINT8 PcdAcpiHidDriverButtonSupport; ///< Offset 1899 Acpi Hid Driver Button Support
1105 UINT8 DisplayDepthLowerLimit; ///< Offset 1900 DPTF Display Depth Lower Limit in percent
1106 UINT8 DisplayDepthUpperLimit; ///< Offset 1901 DPTF Display Depth Upper Limit in percent
1107 UINT8 PepWiGigF1; ///< Offset 1902 PEP F1 constraints for WiGig device
1108 UINT8 ThermalSamplingPeriodWrls; ///< Offset 1903 ThermalSamplingPeriodWrls
1109 UINT32 EcLowPowerModeGpioPin; ///< Offset 1904 EcLowPowerModeGpioPin
1110 UINT32 EcSmiGpioPin; ///< Offset 1908 EcSmiGpioPin
1111 UINT8 WakeOnWiGigSupport; ///< Offset 1912 Wake on S3-S4 WiGig Docking Support
1112 //
1113 // UCMC setup option, GPIO Pad
1114 //
1115 UINT8 UCSI; ///< Offset 1913 Option to Enable/Disable UCSI/UCMC device
1116 UINT32 UcmcPort1Gpio; ///< Offset 1914 Gpio for UCMC Port 1 Interrupt
1117 UINT32 UcmcPort2Gpio; ///< Offset 1918 Gpio for UCMC Port 2 Interrupt
1118 UINT8 Reserved23[23]; ///< Offset 1922:1944
1119 UINT8 EnablePchFivrParticipant; ///< Offset 1945 EnablePchFivrParticipant
1120 UINT8 Reserved24[5]; ///< Offset 1946:1950
1121 UINT8 SerialPortAcpiDebug; ///< Offset 1951 Serial Port ACPI debug
1122 UINT8 Ufp2DfpGlobalFlag; ///< Offset 1952 Upstream Facing port or Downstream Facing port Global Flag from LPC EC
1123 UINT8 Ufp2DfpUsbPort; ///< Offset 1953 Upstream Facing port or Downstream Facing port number from LPC EC
1124 UINT8 DbcGlobalFlag; ///< Offset 1954 Debug Mode Global Flag from LPC EC
1125 UINT8 DbcUsbPort; ///< Offset 1955 Debug Mode USB Port Number from LPC EC
1126 } PLATFORM_NVS_AREA;
1127
1128 #pragma pack(pop)
1129 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformPostCode.h Source File

PlatformPostCode.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright (c) 2016-2017 Intel Corporation. All rights reserved
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _PLATFORMPOSTCODE_H_
34 #define _PLATFORMPOSTCODE_H_
35
36 //
37 // GENERAL USAGE GUIDELINES
38 //
39
40 /**
41 [definition]
42 PostCode = XYZZ
43 X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE
44 Y - "6"=platform driver, "5"=board driver
45 ZZ - "00"=entry, "7F"=exit
46 - 1 - board init premem: entry/exit (0xD500/0xD57F)
47 - 2 - platform init premem: entry/exit (0xD600/0xD67F)
48 - 3 - board init postmem: entry/exit (0x9500/0x957F)
49 - 4 - platform init postmem: entry/exit (0x9600/0x967F)
50 - 5 - board init DXE: entry/exit (0x7500/0x757F)
51 - 6 - platform init DXE: entry/exit (0x7600/0x767F)
52 - 7 - platform SMM init: entry/exit (0x8600/0x867F)
53 - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC
54 - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC
55 - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with ACPI _PTS PC
56 */
57
58 #define BOARD_INIT_PREMEM_ENTRY 0xD500
59 #define BOARD_INIT_PREMEM_EXIT 0xD57F
60 #define PLATFORM_INIT_PREMEM_ENTRY 0xD600
61 #define PLATFORM_INIT_PREMEM_EXIT 0xD67F
62 #define BOARD_INIT_POSTMEM_ENTRY 0x9500
63 #define BOARD_INIT_POSTMEM_EXIT 0x957F
64 #define PLATFORM_INIT_POSTMEM_ENTRY 0x9600
65 #define PLATFORM_INIT_POSTMEM_EXIT 0x967F
66 #define BOARD_INIT_DXE_ENTRY 0x7500
67 #define BOARD_INIT_DXE_EXIT 0x757F
68 #define PLATFORM_INIT_DXE_ENTRY 0x7600
69 #define PLATFORM_INIT_DXE_EXIT 0x767F
70 #define PLATFORM_SMM_INIT_ENTRY 0x8600
71 #define PLATFORM_SMM_INIT_EXIT 0x867F
72 #define BIOS_S3_ENTRY 0xB503
73 #define BIOS_S4_ENTRY 0xB504
74 #define BIOS_S5_ENTRY 0xB505
75
76 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformSecureLib.h Source File

  • Library
PlatformSecureLib.h
Go to the documentation of this file.
1 /** @file
2 Provides a secure platform-specific method to detect physically present user.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PLATFORM_SECURE_LIB_H__
36 #define __PLATFORM_SECURE_LIB_H__
37
38
39 /**
40 Constructor function for Platform Security library.
41
42 @param[in] ImageHandle The firmware allocated handle for the EFI image.
43 @param[in] SystemTable A pointer to the EFI System Table.
44
45 @retval EFI_SUCCESS When this function completed.
46
47 **/
48 EFI_STATUS
49 EFIAPI
50 PlatformSecureLibTestConstructor (
51 IN EFI_HANDLE ImageHandle,
52 IN EFI_SYSTEM_TABLE *SystemTable
53 )
54
55
56 /**
57
58 This function provides a platform-specific method to detect whether the platform
59 is operating by a physically present user.
60
61 Programmatic changing of platform security policy (such as disable Secure Boot,
62 or switch between Standard/Custom Secure Boot mode) MUST NOT be possible during
63 Boot Services or after exiting EFI Boot Services. Only a physically present user
64 is allowed to perform these operations.
65
66 NOTE THAT: This function cannot depend on any EFI Variable Service since they are
67 not available when this function is called in AuthenticateVariable driver.
68
69 @retval TRUE The platform is operated by a physically present user.
70 @retval FALSE The platform is NOT operated by a physically present user.
71
72 **/
73 BOOLEAN
74 EFIAPI
75 UserPhysicalPresent (
76 VOID
77 );
78
79 #endif
PlatformSecureLibTestConstructor
EFI_STATUS PlatformSecureLibTestConstructor(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) BOOLEAN UserPhysicalPresent(VOID)
Constructor function for Platform Security library.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PlatformSmmIoLib.h Source File

  • Library
PlatformSmmIoLib.h
Go to the documentation of this file.
1 /** @file
2 This library provides SMM functions for IO and PCI IO access.
3 These can be used to save size and simplify code.
4 All contents must be runtime and SMM safe.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 1999 - 2017 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35
36 **/
37
38 #ifndef _PLATFORM_SMM_IO_LIB_H_
39 #define _PLATFORM_SMM_IO_LIB_H_
40
41 #include <Uefi/UefiBaseType.h>
42 #include <Uefi/UefiMultiPhase.h>
43 #include <Uefi/UefiSpec.h>
44 #include <Library/DebugLib.h>
45 #include <Library/ReportStatusCodeLib.h>
46 #include <Pi/PiDxeCis.h>
47 #include <Library/SmmServicesTableLib.h>
48 #include <IndustryStandard/Pci22.h>
49
50
51
52 ///
53 /// Global variables that must be defined and initialized to use this library
54 ///
55
56 ///
57 /// Definitions
58 ///
59 #define ICH_ACPI_TIMER_MAX_VALUE 0x1000000 ///< The timer is 24 bit overflow
60 ///
61 /// Pci I/O related data structure deifinition
62 ///
63 typedef enum {
64 SmmPciWidthUint8 = 0,
65 SmmPciWidthUint16 = 1,
66 SmmPciWidthUint32 = 2,
67 SmmPciWidthUint64 = 3,
68 SmmPciWidthMaximum
69 } SMM_PCI_IO_WIDTH;
70
71 #define SMM_PCI_ADDRESS(bus, dev, func, reg) \
72 ((UINT64) ((((UINT32) bus) << 24) + (((UINT32) dev) << 16) + (((UINT32) func) << 8) + ((UINT32) reg)))
73
74 typedef struct {
75 UINT8 Register;
76 UINT8 Function;
77 UINT8 Device;
78 UINT8 Bus;
79 UINT32 ExtendedRegister;
80 } SMM_PCI_IO_ADDRESS;
81
82 ///
83 /// CPU I/O Access Functions
84 ///
85 /**
86 Do a one byte IO read
87
88 @param[in] Address - IO address to read
89
90 @retval Data read
91 **/
92 UINT8
93 SmmIoRead8 (
94 IN UINT16 Address
95 );
96
97 /**
98 Do a one byte IO write
99
100 @param[in] Address - IO address to write
101 @param[in] Data - Data to write
102 **/
103 VOID
104 SmmIoWrite8 (
105 IN UINT16 Address,
106 IN UINT8 Data
107 );
108
109 /**
110 Do a two byte IO read
111
112 @param[in] Address - IO address to read
113
114 @retval Data read
115 **/
116 UINT16
117 SmmIoRead16 (
118 IN UINT16 Address
119 );
120
121 /**
122 Do a two byte IO write
123
124 @param[in] Address - IO address to write
125 @param[in] Data - Data to write
126 **/
127 VOID
128 SmmIoWrite16 (
129 IN UINT16 Address,
130 IN UINT16 Data
131 );
132
133 /**
134 Do a four byte IO read
135
136 @param[in] Address - IO address to read
137
138 @retval Data read
139 **/
140 UINT32
141 SmmIoRead32 (
142 IN UINT16 Address
143 );
144
145 /**
146 Do a four byte IO write
147
148 @param[in] Address - IO address to write
149 @param[in] Data - Data to write
150 **/
151 VOID
152 SmmIoWrite32 (
153 IN UINT16 Address,
154 IN UINT32 Data
155 );
156
157 /**
158 Do a one byte Memory write
159
160 @param[in] Dest - Memory address to write
161 @param[in] Data - Data to write
162 **/
163 VOID
164 SmmMemWrite8 (
165 IN UINT64 Dest,
166 IN UINT8 Data
167 );
168
169 /**
170 Do a one byte Memory read
171
172 @param[in] Dest - Memory address to read
173
174 @retval Data read
175 **/
176 UINT8
177 SmmMemRead8 (
178 IN UINT64 Dest
179 );
180
181 /**
182 Do a two bytes Memory write
183
184 @param[in] Dest - Memory address to write
185 @param[in] Data - Data to write
186 **/
187 VOID
188 SmmMemWrite16 (
189 IN UINT64 Dest,
190 IN UINT16 Data
191 );
192
193 /**
194 Do a two bytes Memory read
195
196 @param[in] Dest - Memory address to read
197
198 @retval Data read
199 **/
200 UINT16
201 SmmMemRead16 (
202 IN UINT64 Dest
203 );
204
205 /**
206 Do a four bytes Memory write
207
208 @param[in] Dest - Memory address to write
209 @param[in] Data - Data to write
210 **/
211 VOID
212 SmmMemWrite32 (
213 IN UINT64 Dest,
214 IN UINT32 Data
215 );
216
217 /**
218 Do a four bytes Memory read
219
220 @param[in] Dest - Memory address to read
221
222 @retval Data read
223 **/
224 UINT32
225 SmmMemRead32 (
226 IN UINT64 Dest
227 );
228
229 /**
230 Do a four bytes Memory read, then AND with Data, then write back to the same address
231
232 @param[in] Dest - Memory address to write
233 @param[in] Data - Data to do AND
234 **/
235 VOID
236 SmmMemAnd32 (
237 IN UINT64 Dest,
238 IN UINT32 Data
239 );
240 ///
241 /// Pci Configuration Space access functions definition
242 ///
243 /**
244 Read value from the specified PCI config space register
245
246 @param[in] Width - The width (8, 16 or 32 bits) of accessed pci config space register
247 @param[in] Address - The address of the accessed pci register (bus, dev, func, offset)
248 @param[in] Buffer - The returned value
249
250 @retval EFI_SUCCESS - All operations successfully
251 @retval EFI_INVALID_PARAMETER - Width is not valid or dosn't match register address
252 @retval Other error code - If any error occured when calling libiary functions
253 **/
254 EFI_STATUS
255 SmmPciCfgRead (
256 IN SMM_PCI_IO_WIDTH Width,
257 IN SMM_PCI_IO_ADDRESS *Address,
258 IN OUT VOID *Buffer
259 );
260 /**
261 Write value into the specified PCI config space register
262
263 @param[in] Width - The width (8, 16 or 32 bits) of accessed pci config space register
264 @param[in] Address - The address of the accessed pci register (bus, dev, func, offset)
265 @param[in] Buffer - The returned value
266
267 @retval EFI_SUCCESS - All operations successfully
268 @retval EFI_INVALID_PARAMETER - Width is not valid or dosn't match register address
269 @retval Other error code - If any error occured when calling libiary functions
270 **/
271 EFI_STATUS
272 SmmPciCfgWrite (
273 IN SMM_PCI_IO_WIDTH Width,
274 IN SMM_PCI_IO_ADDRESS *Address,
275 IN OUT VOID *Buffer
276 );
277 #endif
SmmIoWrite8
VOID SmmIoWrite8(IN UINT16 Address, IN UINT8 Data)
Do a one byte IO write.
SmmMemWrite16
VOID SmmMemWrite16(IN UINT64 Dest, IN UINT16 Data)
Do a two bytes Memory write.
SmmMemWrite8
VOID SmmMemWrite8(IN UINT64 Dest, IN UINT8 Data)
Do a one byte Memory write.
SmmMemAnd32
VOID SmmMemAnd32(IN UINT64 Dest, IN UINT32 Data)
Do a four bytes Memory read, then AND with Data, then write back to the same address.
SmmMemRead8
UINT8 SmmMemRead8(IN UINT64 Dest)
Do a one byte Memory read.
SmmIoRead16
UINT16 SmmIoRead16(IN UINT16 Address)
Do a two byte IO read.
SmmMemWrite32
VOID SmmMemWrite32(IN UINT64 Dest, IN UINT32 Data)
Do a four bytes Memory write.
SmmPciCfgWrite
EFI_STATUS SmmPciCfgWrite(IN SMM_PCI_IO_WIDTH Width, IN SMM_PCI_IO_ADDRESS *Address, IN OUT VOID *Buffer)
Write value into the specified PCI config space register.
SmmIoRead8
UINT8 SmmIoRead8(IN UINT16 Address)
CPU I/O Access Functions.
SmmIoWrite32
VOID SmmIoWrite32(IN UINT16 Address, IN UINT32 Data)
Do a four byte IO write.
SmmMemRead16
UINT16 SmmMemRead16(IN UINT64 Dest)
Do a two bytes Memory read.
SMM_PCI_IO_WIDTH
SMM_PCI_IO_WIDTH
Pci I/O related data structure deifinition.
Definition: PlatformSmmIoLib.h:63
SmmIoWrite16
VOID SmmIoWrite16(IN UINT16 Address, IN UINT16 Data)
Do a two byte IO write.
SmmPciCfgRead
EFI_STATUS SmmPciCfgRead(IN SMM_PCI_IO_WIDTH Width, IN SMM_PCI_IO_ADDRESS *Address, IN OUT VOID *Buffer)
Pci Configuration Space access functions definition.
SmmIoRead32
UINT32 SmmIoRead32(IN UINT16 Address)
Do a four byte IO read.
SmmMemRead32
UINT32 SmmMemRead32(IN UINT64 Dest)
Do a four bytes Memory read.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
PolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is a wrapper for Platform Policy driver. Get Setup
3 Value to initialize Intel DXE Platform Policy.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2013 - 2017 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #include "PolicyInitDxe.h"
37
38 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFirmwareConfiguration = 0;
39
40 /**
41 Initialize DXE Platform Policy
42
43 @param[in] ImageHandle Image handle of this driver.
44 @param[in] SystemTable Global system service table.
45
46 @retval EFI_SUCCESS Initialization complete.
47 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
48 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
49 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
50 **/
51 EFI_STATUS
52 EFIAPI
53 PolicyInitDxeEntryPoint (
54 IN EFI_HANDLE ImageHandle,
55 IN EFI_SYSTEM_TABLE *SystemTable
56 )
57 {
58 EFI_STATUS Status;
59 UINTN VarDataSize;
60 SETUP_DATA *SystemConfiguration = NULL;
61
62 VarDataSize = sizeof (SETUP_DATA);
63
64 SystemConfiguration = (SETUP_DATA *)AllocateZeroPool (VarDataSize);
65
66 mFirmwareConfiguration = 0;
67 if (SystemConfiguration == NULL) {
68 DEBUG ((DEBUG_ERROR, "Fail to allocate memory to get System Configuration!\n"));
69 } else {
70 Status = gRT->GetVariable (
71 L"Setup",
72 &gSetupVariableGuid,
73 NULL,
74 &VarDataSize,
75 SystemConfiguration
76 );
77
78 if (EFI_ERROR (Status)) {
79 DEBUG ((DEBUG_ERROR, "Fail to get System Configuration to identify the initial policy mode!\n"));
80 } else {
81 mFirmwareConfiguration = SystemConfiguration->FirmwareConfiguration;
82 }
83 }
84
85 //
86 // SystemAgent Dxe Platform Policy Initialization
87 //
88 Status = SaPolicyInitDxe (ImageHandle);
89 DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization done\n"));
90 ASSERT_EFI_ERROR (Status);
91
92 //
93 // PCH Dxe Platform Policy Initialization
94 //
95 Status = PchPolicyInitDxe (ImageHandle);
96 DEBUG ((DEBUG_INFO, "PCH Dxe Platform Policy Initialization done\n"));
97 ASSERT_EFI_ERROR (Status);
98
99 //
100 // ME DXE Policy Initialization
101 //
102 Status = MePolicyInitDxe (ImageHandle);
103 DEBUG ((DEBUG_INFO, "ME DXE Policy Initialization done\n"));
104 ASSERT_EFI_ERROR (Status);
105
106 //
107 // AMT DXE Policy Initialization
108 //
109 #ifdef AMT_SUPPORT
110 Status = AmtPolicyInitDxe (ImageHandle);
111 DEBUG ((DEBUG_INFO, "AMT DXE Policy Initialization done\n"));
112 #endif
113
114 //
115 // Silicon Dxe Platform Policy Initialization
116 //
117 Status = SiliconPolicyInitDxe (ImageHandle);
118 DEBUG ((DEBUG_INFO, "Silicon Dxe Platform Policy Initialization done\n"));
119 ASSERT_EFI_ERROR (Status);
120
121 //
122 // CPU DXE Platform Policy Initialization
123 //
124 Status = CpuPolicyInitDxe (ImageHandle);
125 DEBUG ((DEBUG_INFO, "Cpu Dxe Platform Policy Initialization done\n"));
126 ASSERT_EFI_ERROR (Status);
127
128
129 if (PcdGetBool(PcdIntelGopEnable)) {
130 //
131 // GOP Dxe Policy Initialization
132 //
133 Status = GopPolicyInitDxe(ImageHandle);
134 DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
135 ASSERT_EFI_ERROR(Status);
136 }
137
138 //
139 // TBT Dxe Platform Policy Initialization
140 //
141 Status = TbtPolicyInitDxe (ImageHandle);
142 DEBUG ((DEBUG_INFO, "TBT Dxe Platform Policy Initialization done\n"));
143 ASSERT_EFI_ERROR (Status);
144
145 return Status;
146
147 }
PolicyInitDxe.h
Header file for the PolicyInitDxe Driver.
MePolicyInitDxe
EFI_STATUS MePolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy.
Definition: MePolicyInitDxe.c:48
TbtPolicyInitDxe
EFI_STATUS TbtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize TBT DXE Policy.
Definition: TbtPolicyInitDxe.c:53
GopPolicyInitDxe
EFI_STATUS GopPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy.
Definition: GopPolicyInitDxe.c:210
CpuPolicyInitDxe
EFI_STATUS CpuPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Platform Policy.
Definition: CpuPolicyInitDxe.c:50
SaPolicyInitDxe
EFI_STATUS SaPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize SA DXE Policy.
Definition: SaPolicyInitDxe.c:53
AmtPolicyInitDxe
EFI_STATUS AmtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy.
Definition: AmtPolicyInitDxe.c:48
PchPolicyInitDxe
EFI_STATUS PchPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize PCH DXE Policy.
Definition: PchPolicyInitDxe.c:51
PolicyInitDxeEntryPoint
EFI_STATUS PolicyInitDxeEntryPoint(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy.
Definition: PolicyInitDxe.c:53
SiliconPolicyInitDxe
EFI_STATUS SiliconPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel Cpu DXE Platform Policy.
Definition: SiliconPolicyInitDxe.c:51
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
PolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _POLICY_INIT_DXE_H_
35 #define _POLICY_INIT_DXE_H_
36
37
38 #include <Library/BaseMemoryLib.h>
39 #include <Library/UefiBootServicesTableLib.h>
40 #include <Library/UefiRuntimeServicesTableLib.h>
41 #include <Library/DebugLib.h>
42 #include <SetupVariable.h>
43
44 #include "AmtPolicyInitDxe.h"
45 #include "MePolicyInitDxe.h"
46 #include "SaPolicyInitDxe.h"
47 #include "PchPolicyInitDxe.h"
48 #include "SiliconPolicyInitDxe.h"
49 #include "GopPolicyInitDxe.h"
50 #include "CpuPolicyInitDxe.h"
51 #include "TbtPolicyInitDxe.h"
52
53 #include <Library/DxeTbtPolicyLib.h>
54 /**
55 Initialize DXE Platform Policy
56
57 @param[in] ImageHandle - Image handle of this driver.
58 @param[in] SystemTable - Global system service table.
59
60 @retval EFI_SUCCESS Initialization complete.
61 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
62 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
63 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
64 **/
65
66 EFI_STATUS
67 EFIAPI
68 PolicyInitDxeEntryPoint (
69 IN EFI_HANDLE ImageHandle,
70 IN EFI_SYSTEM_TABLE *SystemTable
71 );
72
73 #endif
AmtPolicyInitDxe.h
Header file for the AmtPolicyInitDxe Driver.
MePolicyInitDxe.h
Header file for the MePolicyInitDxe Driver.
SiliconPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
GopPolicyInitDxe.h
Header file for the GopPolicyInitDxe Driver.
PchPolicyInitDxe.h
Header file for the PchPolicyInitDxe Driver.
TbtPolicyInitDxe.h
Header file for the TbtPolicyInitDxe Driver.
SaPolicyInitDxe.h
Header file for the SaPolicyInitDxe Driver.
CpuPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
SetupVariable.h
PolicyInitDxeEntryPoint
EFI_STATUS PolicyInitDxeEntryPoint(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy.
Definition: PolicyInitDxe.c:53
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PttInstance.h Source File

  • Guid
PttInstance.h
Go to the documentation of this file.
1 /** @file
2 GUID definition for the PTT device instance
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef __PTT_INSTANCE_GUID_H__
36 #define __PTT_INSTANCE_GUID_H__
37
38 #define TPM_DEVICE_INTERFACE_TPM20_PTT \
39 { 0x72cd3a7b, 0xfea5, 0x4f5e, { 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13 } }
40
41 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: PttPTPInstanceGuid.h Source File

  • Guid
PttPTPInstanceGuid.h
Go to the documentation of this file.
1 /** @file
2 GUID definition for the PTT device instance
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PTT_PTP_INSTANCE_GUID_H__
36 #define __PTT_PTP_INSTANCE_GUID_H__
37
38 #define TPM_DEVICE_INTERFACE_TPM20_PTT_PTP \
39 { 0x93d66f66, 0x55da, 0x4f03, { 0x9b, 0x5f, 0x32, 0xcf, 0x9e, 0x54, 0x3b, 0x3a } }
40
41 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: S3MemoryVariable.h Source File

  • Guid
S3MemoryVariable.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32
33 **/
34
35
36 #ifndef _S3_MEMORY_VARIABLE_H_
37 #define _S3_MEMORY_VARIABLE_H_
38 #define S3_MEMORY_VARIABLE_NAME L"S3MemoryVariable"
39
40 typedef struct {
41 EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase;
42 UINT32 AcpiReservedMemorySize;
43 UINT64 SystemMemoryLength;
44 } S3_MEMORY_VARIABLE;
45
46 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SaPlatformInitDxe.c Source File

  • PlatformInit
  • PlatformInitDxe
SaPlatformInitDxe.c
Go to the documentation of this file.
1 /** @file
2 Source code file for the Platform Init DXE module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "PlatformInitDxe.h"
35 #include <Protocol/BlockIo.h>
36 #include <Protocol/GopPolicy.h>
37 #include <LegacyUsb/Protocol/UsbController.h>
38 #include <Protocol/SaPolicy.h>
39 #include <Library/DebugLib.h>
40 #include <Protocol/Cpu.h>
41 #include <Protocol/PciEnumerationComplete.h>
42 #include <PlatformNvRamHookLib.h>
43 #include <TbtBoardInfo.h>
44
45 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddress;
46 GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize;
47
48 #define EFI_MAX_ADDRESS 0xFFFFFFFF
49
50
51 EFI_STATUS
52 EFIAPI
53 RegisterDisplayDimmPopulationErrMsg (
54 VOID
55 );
56
57 VOID
58 EFIAPI
59 DisplayDimmPopulationErrMsg (
60 IN EFI_EVENT Event,
61 IN VOID *Context
62 );
63
64 VOID
65 UpdateGmAdrRegionToWriteCombine (
66 VOID
67 );
68
69 VOID
70 EFIAPI
71 PciEnumCompleteCallback (
72 IN EFI_EVENT Event,
73 IN VOID *Context
74 );
75
76
77 /**
78 Update RMRR Base and Limit Address for USB.
79
80 **/
81 VOID
82 UpdateRmrrUsbAddress (
83 VOID
84 )
85 {
86 EFI_STATUS Status;
87 SA_POLICY_PROTOCOL *SaPolicy;
88 MISC_DXE_CONFIG *MiscDxeConfig;
89 UINTN VariableSize;
90 SA_SETUP SaSetup;
91
92 VariableSize = sizeof(SA_SETUP);
93 Status = gRT->GetVariable(
94 L"SaSetup",
95 &gSaSetupVariableGuid,
96 NULL,
97 &VariableSize,
98 &SaSetup
99 );
100 ASSERT_EFI_ERROR(Status);
101
102 Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) &SaPolicy);
103 if (EFI_ERROR (Status)) {
104 return;
105 }
106
107 Status = GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
108 ASSERT_EFI_ERROR (Status);
109
110 if (SaSetup.EnableVtd == 1) {
111 mSize = EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);
112 mAddress = EFI_MAX_ADDRESS;
113
114 Status = (gBS->AllocatePages) (
115 AllocateMaxAddress,
116 EfiReservedMemoryType,
117 mSize,
118 &mAddress
119 );
120 ASSERT_EFI_ERROR (Status);
121
122 MiscDxeConfig->RmrrUsbBaseAddress[0] = mAddress;
123 MiscDxeConfig->RmrrUsbBaseAddress[1] = mAddress + SA_VTD_RMRR_USB_LENGTH - 1;
124 }
125 }
126
127 /**
128 Update SaPolicyGopVbtPointer and Size
129
130 **/
131 EFI_STATUS
132 UpdateSaPolicyGopVbtPointer (
133 VOID
134 )
135 {
136 EFI_STATUS Status;
137 SA_POLICY_PROTOCOL *SaPolicy;
138 GOP_POLICY_PROTOCOL *GopPolicy;
139 EFI_PHYSICAL_ADDRESS VbtAddress;
140 UINT32 Size;
141 GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
142
143 Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) &SaPolicy);
144 if (EFI_ERROR (Status)) {
145 return Status;
146 }
147
148 Status = GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
149 ASSERT_EFI_ERROR (Status);
150
151 DEBUG ((DEBUG_INFO, "Locate GopPolicy and GetVbtData\n"));
152 ///
153 /// Locate the GOP Policy Protocol.
154 ///
155 GopPolicy = NULL;
156 Status = gBS->LocateProtocol (
157 &gGopPolicyProtocolGuid,
158 NULL,
159 (VOID **) &GopPolicy
160 );
161 ASSERT (GopPolicy != NULL);
162 if (EFI_ERROR (Status) || (GopPolicy == NULL)) {
163 return Status;
164 }
165
166 ///
167 /// Get VBT data
168 ///
169 VbtAddress = 0;
170 Size = 0;
171 DEBUG ((DEBUG_INFO, "GetVbtData\n"));
172 Status = GopPolicy->GetVbtData (&VbtAddress, &Size);
173 if (EFI_ERROR (Status)) {
174 return Status;
175 }
176 GraphicsDxeConfig->VbtAddress = VbtAddress;
177 GraphicsDxeConfig->Size = Size;
178
179 return Status;
180 }
181
182 /**
183 Update Setup variable for keep DMA UUID
184 **/
185 VOID
186 UpdateItbtDmaUuidVariable (
187 VOID
188 )
189 {
190 UINTN VarSize;
191 UINT32 VariableAttr;
192 TBT_INFO_HOB *TbtInfoHobPtr;
193 SETUP_DATA SystemConfiguration;
194 EFI_STATUS Status;
195
196 DEBUG ((DEBUG_INFO, "UpdateItbtDmaUuidVariable - Start\n"));
197 //
198 // Get Setup Data for update ITBT DMA UUID
199 //
200 VarSize = sizeof (SETUP_DATA);
201 Status = gRT->GetVariable (
202 PLATFORM_SETUP_VARIABLE_NAME,
203 &gSetupVariableGuid,
204 &VariableAttr,
205 &VarSize,
206 &SystemConfiguration
207 );
208 ASSERT_EFI_ERROR (Status);
209
210 if (EFI_ERROR(Status)){
211 DEBUG ((DEBUG_ERROR, "Platform Setup data was not found.\n"));
212 return;
213 }
214
215 ///
216 /// Get ITBT DMA UUID value from HOB of gSaTcssHobGuid
217 ///
218 TbtInfoHobPtr = (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid);
219
220 if (TbtInfoHobPtr == NULL) {
221 DEBUG ((DEBUG_ERROR, "TcssHobPtr is NULL.\n"));
222 return;
223 }
224
225 //
226 // Update UUID to Setup Data from Hob
227 //
228 SystemConfiguration.ITbtDmaUuid[0] = TbtInfoHobPtr->ITbtDmaUuid[0];
229 SystemConfiguration.ITbtDmaUuid[1] = TbtInfoHobPtr->ITbtDmaUuid[1];
230 SystemConfiguration.ITbtDmaUuid[2] = TbtInfoHobPtr->ITbtDmaUuid[2];
231
232 ///
233 /// Set ITBT DMA UUID to Setup Data variable with updated values
234 ///
235 Status = gRT->SetVariable (
236 PLATFORM_SETUP_VARIABLE_NAME,
237 &gSetupVariableGuid,
238 VariableAttr,
239 VarSize,
240 &SystemConfiguration
241 );
242 ASSERT_EFI_ERROR (Status);
243 DEBUG ((DEBUG_INFO, "UpdateItbtDmaUuidVariable - End\n"));
244 }
245
246
247 /**
248 Updates DIMM slots status for Desktop,server and workstation boards
249
250 **/
251 VOID
252 UpdateDimmPopulation(
253 VOID
254 )
255 {
256
257 if (PcdGetBool (PcdDisplayDimmPopulationError) && PcdGetBool (PcdDimmPopulationError)) {
258 RegisterDisplayDimmPopulationErrMsg ();
259 }
260 }
261
262 /**
263 Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation.
264
265 @param[in] SystemTable Pointer to the System Table
266
267 @retval EFI_SUCCESS return EFI_STATUS as success
268 **/
269 EFI_STATUS
270 EFIAPI
271 RegisterDisplayDimmPopulationErrMsg (
272 VOID
273 )
274 {
275 EFI_EVENT DimmPopultionErrMsgEvent;
276 VOID *Registration;
277
278 DimmPopultionErrMsgEvent = NULL;
279
280 //
281 // Create event for SimpleInProtocol Callback notification
282 //
283 gBS->CreateEvent (
284 EVT_NOTIFY_SIGNAL,
285 TPL_CALLBACK,
286 DisplayDimmPopulationErrMsg,
287 NULL,
288 &DimmPopultionErrMsgEvent
289 );
290 gBS->RegisterProtocolNotify (
291 &gBdsAllDriversConnectedProtocolGuid,
292 DimmPopultionErrMsgEvent,
293 &Registration
294 );
295
296 return EFI_SUCCESS;
297 }
298
299 /**
300 Display DIMM population error message, while Wrong DIMM Population is found.
301
302 @param[in] Event A pointer to the Event that triggered the callback
303 @param[in] Context A pointer to private data registered with the callback function.
304
305 @retval EFI_SUCCESS If Successfully exectuted else returns the error status
306 **/
307 VOID
308 EFIAPI
309 DisplayDimmPopulationErrMsg (
310 IN EFI_EVENT Event,
311 IN VOID *Context
312 )
313 {
314 EFI_STATUS Status;
315 EFI_INPUT_KEY Key;
316
317 DEBUG ((DEBUG_ERROR, "\n DIMMPopulation Error msg\n"));
318
319 if (gST->ConOut != NULL && gST->ConIn != NULL) {
320 if (Event != NULL) {
321 gBS->CloseEvent (Event);
322 }
323 //
324 // Display the Error Message
325 //
326 gST->ConOut->OutputString (gST->ConOut, L"");
327
328 gST->ConOut->OutputString (gST->ConOut, L"Error...! Invalid DIMM Population.");
329
330 gST->ConOut->OutputString (gST->ConOut, L"Slot 0 can't be populated when Slot 1 is not populated on the same channel");
331
332 gST->ConOut->OutputString (gST->ConOut, L"Press <Y> to Continue. <N> to Shutdown");
333
334 //
335 // Wait for User Input
336 //
337 do {
338 Status = gBS->CheckEvent (gST->ConIn->WaitForKey);
339 if (!EFI_ERROR (Status)) {
340 Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
341 if (Key.UnicodeChar == L'Y' || Key.UnicodeChar == L'y') {
342 DEBUG ((DEBUG_INFO, " Boot Continue\n"));
343 break;
344 } else if (Key.UnicodeChar == L'N' || Key.UnicodeChar == L'n') {
345 DEBUG ((DEBUG_ERROR, " System shutdown\n"));
346 gRT->ResetSystem (EfiResetShutdown, EFI_SUCCESS, 0, NULL);
347 }
348 }
349 } while (1);
350 }
351 }
352
353 #ifdef CSM_FLAG
354 /**
355 Updates System Agent registers related to display
356
357 **/
358 VOID
359 UpdateSaDisplayRegisters(
360 VOID
361 )
362 {
363 EFI_STATUS Status;
364 UINTN SaSetupSize;
365 UINT8 DDISelection;
366 SA_SETUP SaSetup;
367
368 SaSetupSize = sizeof (SA_SETUP);
369 Status = gRT->GetVariable (
370 L"SaSetup",
371 &gSaSetupVariableGuid,
372 NULL,
373 &SaSetupSize,
374 &SaSetup
375 );
376
377 if (EFI_ERROR(Status)) {
378 SaSetup.LcdPanelType = 0;
379 SaSetup.LcdPanelScaling = 0;
380 SaSetup.IgdBootType = 0;
381 SaSetup.DisplayPipeB = 0;
382 SaSetup.IgdLcdBlc = 0;
383 SaSetup.ActiveLFP = 0;
384 SaSetup.LfpColorDepth = 0;
385 SaSetup.PrimaryDisplay = 0;
386 SaSetup.VbiosBrightness = 0;
387 }
388
389 DDISelection = PcdGet8 (PcdDDISelection);
390
391 //
392 // Save the SA settings related to Display
393 //
394 SaveSaDisplayRegisters (
395 &SaSetup,
396 DDISelection
397 );
398 }
399 #endif
400
401 /**
402 System Agent platform Initialization
403
404 **/
405 VOID
406 SaPlatformInitDxe (
407 VOID
408 )
409 {
410
411 //
412 // Update RMRR Base and Limit Address for USB
413 //
414 UpdateRmrrUsbAddress();
415
416 //
417 // Update GOP VBT Address and Size from FV
418 //
419 UpdateSaPolicyGopVbtPointer();
420
421 //
422 // Update GT Aperture region memory type as Write Combine.
423 //
424 UpdateGmAdrRegionToWriteCombine();
425
426 //
427 // Save Itbt Dma UUID Data
428 //
429 UpdateItbtDmaUuidVariable();
430 }
431
432 /**
433 This function will update the GT Aperture Region to Write Combining.
434
435 **/
436 VOID
437 UpdateGmAdrRegionToWriteCombine (
438 VOID
439 )
440 {
441 VOID *Registration;
442
443 DEBUG ((DEBUG_INFO, "Call backs to update GmAdr region as write combine\n"));
444
445 ///
446 /// Create PCI Enumeration Completed callback
447 ///
448 EfiCreateProtocolNotifyEvent (
449 &gEfiPciEnumerationCompleteProtocolGuid,
450 TPL_NOTIFY,
451 PciEnumCompleteCallback,
452 NULL,
453 &Registration
454 );
455 }
456
457 /**
458 This function gets registered as a callback to perform SA functions after PCI enumeration completes.
459
460 @param[in] Event - A pointer to the Event that triggered the callback.
461 @param[in] Context - A pointer to private data registered with the callback function.
462 **/
463 VOID
464 EFIAPI
465 PciEnumCompleteCallback (
466 IN EFI_EVENT Event,
467 IN VOID *Context
468 )
469 {
470 EFI_STATUS Status;
471 VOID *ProtocolPointer;
472 UINT32 Msac;
473 UINT64 McD2BaseAddress;
474 UINT64 GtApertureSize;
475 UINT64 GtApertureAdr;
476 EFI_CPU_ARCH_PROTOCOL *CpuArch;
477 SA_POLICY_PROTOCOL *SaPolicy;
478 MISC_DXE_CONFIG *MiscDxeConfig;
479
480 DEBUG ((DEBUG_INFO, "SA Platform PciEnumCompleteCallback Start\n"));
481
482 Msac = 0;
483 GtApertureAdr = 0;
484 GtApertureSize = 0;
485
486 ///
487 /// Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
488 /// if it is, we will skip it until real event is triggered
489 ///
490 Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, NULL, (VOID **) &ProtocolPointer);
491 if (EFI_SUCCESS != Status) {
492 return;
493 }
494
495 gBS->CloseEvent (Event);
496
497 McD2BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0, 0);
498 ///
499 /// If device 0:2:0 (Internal Graphics Device, or GT) is not present, skip it.
500 ///
501 if ((PciSegmentRead16 (McD2BaseAddress + R_SA_IGD_VID) != 0xFFFF)) {
502 Msac = PciSegmentRead32 (McD2BaseAddress + R_SA_IGD_MSAC_OFFSET);
503 GtApertureSize = ((((Msac & (BIT20 | BIT19 | BIT18 | BIT17 | BIT16))) >> 16) + 1) * SIZE_128MB;
504
505 PciSegmentReadBuffer (McD2BaseAddress + R_SA_IGD_GMADR, sizeof (UINT64), &GtApertureAdr);
506 GtApertureAdr &= 0xFFFFFFFFFFFFFFF0;
507
508 Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **) &CpuArch);
509 ASSERT_EFI_ERROR (Status);
510
511 Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) &SaPolicy);
512 if (SaPolicy != NULL) {
513 Status = GetConfigBlock ((VOID *) SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
514 ASSERT_EFI_ERROR (Status);
515 }
516 if (MiscDxeConfig->EnableAbove4GBMmio == 1) {
517 //
518 // WORKAROUND for MTRR above 4G issue
519 //
520 GtApertureSize = SIZE_128GB;
521 }
522
523 Status = CpuArch->SetMemoryAttributes (
524 CpuArch,
525 GtApertureAdr,
526 GtApertureSize,
527 EFI_MEMORY_WC
528 );
529 if (EFI_SUCCESS != Status) {
530 DEBUG((DEBUG_INFO, "Setting GmAdr Memory as WriteCombine failed!\n"));
531 ASSERT_EFI_ERROR (Status);
532 }
533 }
534
535 DEBUG ((DEBUG_INFO, "SA Platform PciEnumCompleteCallback End\n"));
536 return;
537 }
SaPlatformInitDxe
VOID SaPlatformInitDxe(VOID)
System Agent platform Initialization.
Definition: SaPlatformInitDxe.c:406
UpdateItbtDmaUuidVariable
VOID UpdateItbtDmaUuidVariable(VOID)
Update Setup variable for keep DMA UUID.
Definition: SaPlatformInitDxe.c:186
PlatformInitDxe.h
Platform Info Driver.
DisplayDimmPopulationErrMsg
VOID DisplayDimmPopulationErrMsg(IN EFI_EVENT Event, IN VOID *Context)
Display DIMM population error message, while Wrong DIMM Population is found.
Definition: SaPlatformInitDxe.c:309
PlatformNvRamHookLib.h
Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NV...
UpdateGmAdrRegionToWriteCombine
VOID UpdateGmAdrRegionToWriteCombine(VOID)
This function will update the GT Aperture Region to Write Combining.
Definition: SaPlatformInitDxe.c:437
UpdateSaPolicyGopVbtPointer
EFI_STATUS UpdateSaPolicyGopVbtPointer(VOID)
Update SaPolicyGopVbtPointer and Size.
Definition: SaPlatformInitDxe.c:132
RegisterDisplayDimmPopulationErrMsg
EFI_STATUS RegisterDisplayDimmPopulationErrMsg(VOID)
Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation.
Definition: SaPlatformInitDxe.c:271
UpdateDimmPopulation
VOID UpdateDimmPopulation(VOID)
Updates DIMM slots status for Desktop,server and workstation boards.
Definition: SaPlatformInitDxe.c:252
UpdateRmrrUsbAddress
VOID UpdateRmrrUsbAddress(VOID)
Update RMRR Base and Limit Address for USB.
Definition: SaPlatformInitDxe.c:82
PciEnumCompleteCallback
VOID PciEnumCompleteCallback(IN EFI_EVENT Event, IN VOID *Context)
This function gets registered as a callback to perform SA functions after PCI enumeration completes...
Definition: SaPlatformInitDxe.c:465
SaveSaDisplayRegisters
VOID SaveSaDisplayRegisters(VOID *SaSetupData, UINT8 DDISelection)
Save the SA settings related to Display.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SaPolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
SaPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for SA DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "SaPolicyInitDxe.h"
35
36
37 //
38 // Function implementations
39 //
40
41 /**
42 Initialize SA DXE Policy
43
44 @param[in] ImageHandle Image handle of this driver.
45
46 @retval EFI_SUCCESS Initialization complete.
47 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
48 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
49 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
50 **/
51 EFI_STATUS
52 EFIAPI
53 SaPolicyInitDxe (
54 IN EFI_HANDLE ImageHandle
55 )
56 {
57 EFI_STATUS Status;
58 SA_POLICY_PROTOCOL *SaPolicy;
59
60 //
61 // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
62 // and get all Intel default policy settings.
63 //
64 Status = CreateSaDxeConfigBlocks(&SaPolicy);
65 DEBUG((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
66 ASSERT_EFI_ERROR(Status);
67
68 UpdateDxeSaPolicyBoardConfig (SaPolicy);
69
70 if (mFirmwareConfiguration != FwConfigDefault) {
71
72 UpdateDxeSaPolicy (SaPolicy);
73 }
74
75 //
76 // Install SaInstallPolicyProtocol.
77 // While installed, RC assumes the Policy is ready and finalized. So please
78 // update and override any setting before calling this function.
79 //
80 Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
81 ASSERT_EFI_ERROR (Status);
82
83 return Status;
84 }
SaPolicyInitDxe
EFI_STATUS SaPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize SA DXE Policy.
Definition: SaPolicyInitDxe.c:53
SaPolicyInitDxe.h
Header file for the SaPolicyInitDxe Driver.
UpdateDxeSaPolicy
EFI_STATUS UpdateDxeSaPolicy(IN OUT SA_POLICY_PROTOCOL *SaPolicy)
Get data for platform policy from setup options.
UpdateDxeSaPolicyBoardConfig
EFI_STATUS UpdateDxeSaPolicyBoardConfig(IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy)
This function performs DXE SA Policy update by board configuration.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SaPolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
SaPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the SaPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _SA_POLICY_INIT_DXE_H_
35 #define _SA_POLICY_INIT_DXE_H_
36
37 #include <Library/BaseMemoryLib.h>
38 #include <Library/MemoryAllocationLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42 #include <Protocol/SaPolicy.h>
43 #include <Library/DxeSaPolicyLib.h>
44 #include <Library/DxePolicyBoardConfigLib.h>
45 #include <Library/DxeSaPolicyUpdateLib.h>
46
47 #include <SaAccess.h>
48
49 extern UINT8 mFirmwareConfiguration;
50
51 /**
52 <b>SA DXE Policy Driver Entry Point</b> \n
53 - <b>Introduction</b> \n
54 System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
55 Platform policy Protocol is initialized with default settings in this funciton.
56 This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
57
58 - @pre
59 - Runtime variable service should be ready if policy initialization required.
60
61 - @result
62 SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use.
63
64 - <b>Porting Recommendations</b> \n
65 Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
66
67 @param[in] ImageHandle - Image handle of this driver.
68
69 @retval EFI_SUCCESS Initialization complete.
70 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
71 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
72 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
73 **/
74 EFI_STATUS
75 EFIAPI
76 SaPolicyInitDxe (
77 IN EFI_HANDLE ImageHandle
78 );
79
80 #endif
DxeSaPolicyUpdateLib.h
DxePolicyBoardConfigLib.h
Header file for the DxePolicyBoardConfig Library.
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
SaPolicyInitDxe
EFI_STATUS SaPolicyInitDxe(IN EFI_HANDLE ImageHandle)
SA DXE Policy Driver Entry Point
Definition: SaPolicyInitDxe.c:53
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SdCard.h Source File

  • IndustryStandard
SdCard.h
Go to the documentation of this file.
1 /** @file
2 Header file for Industry SD Card 2.0 spec.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _SD_CARD_H
35 #define _SD_CARD_H
36
37 #include <IndustryStandard/Mmc.h>
38
39 #pragma pack(1)
40
41 #define CHECK_PATTERN 0xAA ///< Physical Layer Simplified Specification Version 3.01 recommended 0xAA
42
43 #define ACMD6 6
44 #define ACMD13 13
45 #define ACMD23 23
46 #define ACMD41 41
47 #define ACMD42 42
48 #define ACMD51 51
49
50 #define SWITCH_FUNC CMD6
51 #define SEND_IF_COND CMD8
52
53 #define SET_BUS_WIDTH ACMD6
54 #define SD_STATUS ACMD13
55 #define SET_WR_BLK_ERASE_COUNT ACMD23
56 #define SD_SEND_OP_COND ACMD41
57 #define SET_CLR_CARD_DETECT ACMD42
58 #define SEND_SCR ACMD51
59
60 #define SD_BUS_WIDTH_1 0
61 #define SD_BUS_WIDTH_4 2
62
63 #define FREQUENCY_SD_PP (25 * 1000 * 1000)
64 #define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000)
65
66 #define SD_SPEC_10 0
67 #define SD_SPEC_11 1
68 #define SD_SPEC_20 2
69
70 #define VOLTAGE_27_36 0x1
71
72 typedef struct {
73 UINT8 NotUsed: 1; // 1 [0:0]
74 UINT8 CRC: 7; // CRC [7:1]
75 UINT8 ECC: 2; // ECC code [9:8]
76 UINT8 FILE_FORMAT: 2; // File format [11:10]
77 UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
78 UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
79 UINT8 COPY: 1; // Copy flag (OTP) [14:14]
80 UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
81 UINT16 Reserved0: 5; // 0 [20:16]
82 UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
83 UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
84 UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
85 UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]
86 UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
87 UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
88 UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
89 UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
90 UINT16 Reserved1: 1; // 0 [47:47]
91
92 UINT32 C_SIZE: 22; // Device size [69:48]
93 UINT32 Reserved2: 6; // 0 [75:70]
94 UINT32 DSR_IMP: 1; // DSR implemented [76:76]
95 UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
96 UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
97 UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
98
99 UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
100 UINT16 CCC: 12; // Card command classes [95:84]
101 UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
102 UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
103 UINT8 TAAC ; // Data read access-time 1 [119:112]
104 UINT8 Reserved3: 6; // 0 [125:120]
105 UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
106 } CSD_SDV2;
107
108 typedef struct {
109 UINT32 Reserved0;
110 UINT32 Reserved1: 16;
111 UINT32 SD_BUS_WIDTH: 4;
112 UINT32 SD_SECURITY: 3;
113 UINT32 DATA_STAT_AFTER_ERASE: 1;
114 UINT32 SD_SPEC: 4;
115 UINT32 SCR_STRUCT: 4;
116 } SCR;
117
118
119 typedef struct {
120 UINT8 Reserved0[50];
121 UINT8 ERASE_OFFSET: 2;
122 UINT8 ERASE_TIMEOUT: 6;
123 UINT16 ERASE_SIZE;
124 UINT8 Reserved1: 4;
125 UINT8 AU_SIZE: 4;
126 UINT8 PERFORMANCE_MOVE;
127 UINT8 SPEED_CLASS;
128 UINT32 SIZE_OF_PROTECTED_AREA;
129 UINT32 SD_CARD_TYPE: 16;
130 UINT32 Reserved2: 13;
131 UINT32 SECURED_MODE: 1;
132 UINT32 DAT_BUS_WIDTH: 2;
133 } SD_STATUS_REG;
134
135 typedef struct {
136 UINT8 Reserved0[34];
137 UINT16 Group1BusyStatus;
138 UINT16 Group2BusyStatus;
139 UINT16 Group3BusyStatus;
140 UINT16 Group4BusyStatus;
141 UINT16 Group5BusyStatus;
142 UINT16 Group6BusyStatus;
143 UINT8 DataStructureVersion;
144 UINT8 Group21Status;
145 UINT8 Group43Status;
146 UINT8 Group65Status;
147 UINT16 Group1Function;
148 UINT16 Group2Function;
149 UINT16 Group3Function;
150 UINT16 Group4Function;
151 UINT16 Group5Function;
152 UINT16 Group6Function;
153 UINT16 MaxCurrent;
154 } SWITCH_STATUS;
155
156 #pragma pack()
157 #endif
158
Mmc.h
Header file for Industry MMC 4.2 spec.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SdHostIo.h Source File

  • Protocol
SdHostIo.h
Go to the documentation of this file.
1 /** @file
2 Header file for interface definition of EFI_SD_HOST_IO_PROTOCOL.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _SD_HOST_IO_H
35 #define _SD_HOST_IO_H
36
37 #define EFI_SD_HOST_IO_PROTOCOL_GUID \
38 { 0xb63f8ec7, 0xa9c9, 0x4472, { 0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51 } }
39
40 typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL;
41
42 //
43 // TODO: Move to Pci22.h
44 //
45 #define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05
46 #define PCI_IF_STANDARD_HOST_NO_DMA 0x00
47 #define PCI_IF_STANDARD_HOST_SUPPORT_DMA 0x01
48
49 //
50 // TODO: Retire
51 //
52 #define EFI_SD_HOST_IO_PROTOCOL_REVISION_01 0x01
53
54 //
55 // TODO: Do these belong in an Industry Standard include file?
56 //
57 // MMIO Registers definition for MMC/SDIO controller
58 //
59 #define MMIO_DMAADR 0x00
60 #define MMIO_BLKSZ 0x04
61 #define MMIO_BLKCNT 0x06
62 #define MMIO_CMDARG 0x08
63 #define MMIO_XFRMODE 0x0C
64 #define MMIO_SDCMD 0x0E
65 #define MMIO_RESP 0x10
66 #define MMIO_BUFDATA 0x20
67 #define MMIO_PSTATE 0x24
68 #define MMIO_HOSTCTL 0x28
69 #define MMIO_PWRCTL 0x29
70 #define MMIO_BLKGAPCTL 0x2A
71 #define MMIO_WAKECTL 0x2B
72 #define MMIO_CLKCTL 0x2C
73 #define MMIO_TOCTL 0x2E
74 #define MMIO_SWRST 0x2F
75 #define MMIO_NINTSTS 0x30
76 #define MMIO_ERINTSTS 0x32
77 #define MMIO_NINTEN 0x34
78 #define MMIO_ERINTEN 0x36
79 #define MMIO_NINTSIGEN 0x38
80 #define MMIO_ERINTSIGEN 0x3A
81 #define MMIO_AC12ERRSTS 0x3C
82 #define MMIO_HOST_CTL2 0x3E
83 #define MMIO_CAP 0x40
84 #define MMIO_CAP2 0x44
85 #define MMIO_MCCAP 0x48
86 #define MMIO_FORCEEVENTCMD12ERRSTAT 0x50
87 #define MMIO_FORCEEVENTERRINTSTAT 0x52
88 #define MMIO_ADMAERRSTAT 0x54
89 #define MMIO_ADMASYSADDR 0x58
90 #define MMIO_PRESETVALUE0 0x60
91 #define MMIO_PRESETVALUE1 0x64
92 #define MMIO_PRESETVALUE2 0x68
93 #define MMIO_PRESETVALUE3 0x6C
94 #define MMIO_BOOTTIMEOUTCTRL 0x70
95 #define MMIO_DEBUGSEL 0x74
96 #define MMIO_SHAREDBUS 0xE0
97 #define MMIO_SPIINTSUP 0xF0
98 #define MMIO_SLTINTSTS 0xFC
99 #define MMIO_CTRLRVER 0xFE
100
101 typedef enum {
102 ResponseNo = 0,
103 ResponseR1,
104 ResponseR1b,
105 ResponseR2,
106 ResponseR3,
107 ResponseR4,
108 ResponseR5,
109 ResponseR5b,
110 ResponseR6,
111 ResponseR7
112 } RESPONSE_TYPE;
113
114 typedef enum {
115 NoData = 0,
116 InData,
117 OutData
118 } TRANSFER_TYPE;
119
120 typedef enum {
121 Reset_Auto = 0,
122 Reset_DAT,
123 Reset_CMD,
124 Reset_DAT_CMD,
125 Reset_All,
126 Reset_HW
127 } RESET_TYPE;
128
129 typedef enum {
130 SDMA = 0,
131 ADMA2,
132 PIO
133 } DMA_MOD;
134
135 typedef struct {
136 UINT32 HighSpeedSupport: 1; // High speed supported
137 UINT32 V18Support: 1; // 1.8V supported
138 UINT32 V30Support: 1; // 3.0V supported
139 UINT32 V33Support: 1; // 3.3V supported
140 UINT32 SDR50Support: 1;
141 UINT32 SDR104Support: 1;
142 UINT32 DDR50Support: 1;
143 UINT32 HS400Support: 1;
144 UINT32 BusWidth4: 1; // 4 bit width
145 UINT32 BusWidth8: 1; // 8 bit width
146 UINT32 Reserved1: 6;
147 UINT32 SDMASupport: 1;
148 UINT32 ADMA2Support: 1;
149 UINT32 DmaMode: 2;
150 UINT32 ReTuneTimer: 4;
151 UINT32 ReTuneMode: 2;
152 UINT32 Reserved2: 6;
153 UINT32 BoundarySize;
154 } HOST_CAPABILITY;
155
156 /**
157 The main function used to send the command to the card inserted into the SD/MMC host
158 slot. It will assemble the arguments to set the command register and wait for the command
159 and transfer completed until timeout. Then it will read the response register to fill
160 the ResponseData.
161
162 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
163 @param[in] CommandIndex The command index to set the command index field of command register
164 @param[in] Argument Command argument to set the argument field of command register
165 @param[in] DataType TRANSFER_TYPE, indicates no data, data in or data out
166 @param[in] Buffer Contains the data read from / write to the device
167 @param[in] BufferSize The size of the buffer
168 @param[in] ResponseType RESPONSE_TYPE
169 @param[in] TimeOut Time out value in 1 ms unit
170 @param[in] ResponseData Depending on the ResponseType, such as CSD or card status
171
172 @retval EFI_SUCCESS The function completed successfully
173 @retval EFI_INVALID_PARAMETER A parameter was incorrect.
174 @retval EFI_OUT_OF_RESOURCES A resource has run out.
175 @retval EFI_TIMEOUT The timeout time expired.
176 @retval EFI_DEVICE_ERROR The physical device reported an error while attempting the operation
177 **/
178 typedef
179 EFI_STATUS
180 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) (
181 IN EFI_SD_HOST_IO_PROTOCOL *This,
182 IN UINT16 CommandIndex,
183 IN UINT32 Argument,
184 IN TRANSFER_TYPE DataType,
185 IN UINT8 *Buffer, OPTIONAL
186 IN UINT32 BufferSize,
187 IN RESPONSE_TYPE ResponseType,
188 IN UINT32 TimeOut,
189 OUT UINT32 *ResponseData OPTIONAL
190 );
191
192 /**
193 Set max clock frequency of the host, the actual frequency may not be the same
194 as MaxFrequency. It depends on the max frequency the host can support, divider,
195 and host speed mode.
196
197 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
198 @param[in] MaxFrequency Max frequency in HZ
199
200 @retval EFI_SUCCESS The function completed successfully
201 @retval EFI_TIMEOUT The timeout time expired.
202 **/
203 typedef
204 EFI_STATUS
205 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) (
206 IN EFI_SD_HOST_IO_PROTOCOL *This,
207 IN UINT32 MaxFrequency
208 );
209
210 /**
211 Set bus width of the host
212
213 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
214 @param[in] BusWidth Bus width in 1, 4, 8 bits
215
216 @retval EFI_SUCCESS The function completed successfully
217 @retval EFI_INVALID_PARAMETER A parameter was incorrect.
218 **/
219 typedef
220 EFI_STATUS
221 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) (
222 IN EFI_SD_HOST_IO_PROTOCOL *This,
223 IN UINT32 BusWidth
224 );
225
226 /**
227 Set voltage which could supported by the host.
228 Support 0(Power off the host), 1.8V, 3.0V, 3.3V
229
230 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
231 @param[in] Voltage Units in 0.1 V
232
233 @retval EFI_SUCCESS The function completed successfully
234 @retval EFI_INVALID_PARAMETER A parameter was incorrect.
235 **/
236 typedef
237 EFI_STATUS
238 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) (
239 IN EFI_SD_HOST_IO_PROTOCOL *This,
240 IN UINT32 Voltage
241 );
242
243 /**
244 Set Host High Speed
245
246 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
247 @param[in] HighSpeed True for High Speed Mode set, false for normal mode
248
249 @retval EFI_SUCCESS The function completed successfully
250 @retval EFI_INVALID_PARAMETER A parameter was incorrect.
251 **/
252 typedef
253 EFI_STATUS
254 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) (
255 IN EFI_SD_HOST_IO_PROTOCOL *This,
256 IN UINT32 HighSpeed
257 );
258
259 /**
260 Set Host DDR Mode
261
262 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
263 @param[in] DdrMode True for DDR Mode set, false for normal mode
264
265 @retval EFI_SUCCESS The function completed successfully
266 @retval EFI_INVALID_PARAMETER A parameter was incorrect.
267 **/
268 typedef
269 EFI_STATUS
270 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
271 IN EFI_SD_HOST_IO_PROTOCOL *This,
272 IN UINT32 DdrMode
273 );
274
275 /**
276 Set Host SDR Mode
277
278 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
279 @param[in] DdrMode True for SDR Mode set, false for normal mode
280
281 @retval EFI_SUCCESS The function completed successfully
282 @retval EFI_INVALID_PARAMETER A parameter was incorrect.
283 **/
284 typedef
285 EFI_STATUS
286 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE) (
287 IN EFI_SD_HOST_IO_PROTOCOL *This,
288 IN UINT32 SdrMode
289 );
290
291 /**
292 Reset the host
293
294 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
295 @param[in] ResetAll TRUE to reset all
296
297 @retval EFI_SUCCESS The function completed successfully
298 @retval EFI_TIMEOUT The timeout time expired.
299 **/
300 typedef
301 EFI_STATUS
302 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) (
303 IN EFI_SD_HOST_IO_PROTOCOL *This,
304 IN RESET_TYPE ResetType
305 );
306
307 /**
308 Enable Auto Stop Command
309
310 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
311 @param[in] Enable TRUE to enable Auto Stop Command
312
313 @retval EFI_SUCCESS The function completed successfully
314 @retval EFI_TIMEOUT The timeout time expired.
315 **/
316 typedef
317 EFI_STATUS
318 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) (
319 IN EFI_SD_HOST_IO_PROTOCOL *This,
320 IN BOOLEAN Enable
321 );
322
323 /**
324 Find whether these is a card inserted into the slot. If so
325 init the host. If not, return EFI_NOT_FOUND.
326
327 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
328
329 @retval EFI_SUCCESS The function completed successfully
330 @retval EFI_NOT_FOUND The item was not found.
331 **/
332 typedef
333 EFI_STATUS
334 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) (
335 IN EFI_SD_HOST_IO_PROTOCOL *This
336 );
337
338 /**
339 Set the Block length
340
341 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
342 @param[in] BlockLength Card supported block length
343
344 @retval EFI_SUCCESS The function completed successfully
345 @retval EFI_TIMEOUT The timeout time expired.
346 **/
347 typedef
348 EFI_STATUS
349 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) (
350 IN EFI_SD_HOST_IO_PROTOCOL *This,
351 IN UINT32 BlockLength
352 );
353
354 /**
355 Setup Device for card initialization
356
357 @param[in] This Pointer to EFI_SD_HOST_IO_PROTOCOL
358
359 @retval EFI_SUCCESS The function completed successfully
360 **/
361 typedef EFI_STATUS
362 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE)(
363 IN EFI_SD_HOST_IO_PROTOCOL *This
364 );
365
366
367 //
368 // Interface structure for the EFI SD Host I/O Protocol
369 //
370 struct _EFI_SD_HOST_IO_PROTOCOL {
371 UINT32 Revision;
372 HOST_CAPABILITY HostCapability;
373 EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND SendCommand;
374 EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY SetClockFrequency;
375 EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH SetBusWidth;
376 EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE SetHostVoltage;
377 EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE SetHostDdrMode;
378 EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE SetHostSdrMode;
379 EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST ResetSdHost;
380 EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD EnableAutoStopCmd;
381 EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST DetectCardAndInitHost;
382 EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH SetBlockLength;
383 EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE SetupDevice;
384 EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE SetHostSpeedMode;
385 };
386
387 #endif
388
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SDR_MODE)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 SdrMode)
Set Host SDR Mode.
Definition: SdHostIo.h:286
EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE)(IN EFI_SD_HOST_IO_PROTOCOL *This)
Setup Device for card initialization.
Definition: SdHostIo.h:362
EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN BOOLEAN Enable)
Enable Auto Stop Command.
Definition: SdHostIo.h:318
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 DdrMode)
Set Host DDR Mode.
Definition: SdHostIo.h:270
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 Voltage)
Set voltage which could supported by the host.
Definition: SdHostIo.h:238
EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 MaxFrequency)
Set max clock frequency of the host, the actual frequency may not be the same as MaxFrequency.
Definition: SdHostIo.h:205
EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT16 CommandIndex, IN UINT32 Argument, IN TRANSFER_TYPE DataType, IN UINT8 *Buffer, OPTIONAL IN UINT32 BufferSize, IN RESPONSE_TYPE ResponseType, IN UINT32 TimeOut, OUT UINT32 *ResponseData OPTIONAL)
The main function used to send the command to the card inserted into the SD/MMC host slot...
Definition: SdHostIo.h:180
EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 HighSpeed)
Set Host High Speed.
Definition: SdHostIo.h:254
EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST)(IN EFI_SD_HOST_IO_PROTOCOL *This)
Find whether these is a card inserted into the slot.
Definition: SdHostIo.h:334
EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 BlockLength)
Set the Block length.
Definition: SdHostIo.h:349
EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN UINT32 BusWidth)
Set bus width of the host.
Definition: SdHostIo.h:221
EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST
EFI_STATUS(* EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST)(IN EFI_SD_HOST_IO_PROTOCOL *This, IN RESET_TYPE ResetType)
Reset the host.
Definition: SdHostIo.h:302
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Setup.h Source File

Setup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2009 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __SETUP__H__
35 #define __SETUP__H__
36
37 #include "SetupConfiguration.h"
38 #include "SetupVariable.h"
39
40 #ifndef MDEPKG_NDEBUG
41 #define DEBUG_INTERFACE_FORM_ENABLE
42 #endif // MDEPKG_NDEBUG
43 //
44 // Form class guid for the forms those will be showed on first front page.
45 //
46 #define FRONT_PAGE_GUID { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a, 0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } }
47 //
48 // Form class guid for the forms those will be showed on boot maintenance manager menu.
49 //
50 #define BOOT_MAINTENANCE_GUID { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a, 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 } }
51
52 // VFR common Definitions
53 #define INVENTORY(Name,Value) \
54 text \
55 help = STRING_TOKEN(STR_EMPTY), \
56 text = Name, \
57 text = Value, \
58 flags = 0, \
59 key = 0;
60
61 #define SUBTITLE(Text) subtitle text = Text;
62 #define SEPARATOR SUBTITLE(STRING_TOKEN(STR_EMPTY))
63
64 #define INTERACTIVE_TEXT(HelpToken, CaptionToken, ValueToken, Key)\
65 grayoutif TRUE;\
66 oneof varid = SETUP_DATA.InteractiveText,\
67 questionid = Key,\
68 prompt = CaptionToken,\
69 help = HelpToken,\
70 option text = ValueToken, value = 0, flags = INTERACTIVE | DEFAULT;\
71 refresh interval = 1 \
72 endoneof;\
73 endif;
74
75 #define SUPPRESS_GRAYOUT_ENDIF endif; endif;
76 #define DEFAULT_FLAG
77
78 #define SYSTEM_ACCESS_KEY_ID 0xF000
79 //
80 // System Access defintions.
81 //
82 #define SYSTEM_ACCESS_GUID \
83 { 0xE770BB69, 0xBCB4, 0x4D04, 0x9E, 0x97, 0x23, 0xFF, 0x94, 0x56, 0xFE, 0xAC }
84
85 #define SYSTEM_PASSWORD_ADMIN 0
86 #define SYSTEM_PASSWORD_USER 1
87
88 ///
89 /// SHA-256 digest size in bytes
90 ///
91 #define SHA256_DIGEST_SIZE 32
92
93 #pragma pack(1)
94 typedef struct {
95 //
96 // Passwords
97 //
98 UINT8 Access;
99 UINT8 AdminPassword[SHA256_DIGEST_SIZE];
100 UINT8 AdminPwSalt[SHA256_DIGEST_SIZE];
101 } SYSTEM_ACCESS;
102
103 typedef struct _SYSTEM_ACCESS_REQUEST
104 {
105 UINT8 Action;
106 UINT16 AdminPassword[PASSWORD_MAX_SIZE];
107 UINT8 NewAdminPassword[SHA256_DIGEST_SIZE];
108 UINT8 AdminPwSalt[SHA256_DIGEST_SIZE];
109 } SYSTEM_ACCESS_REQUEST;
110
111 //
112 // Record the password status.
113 //
114 typedef struct {
115 UINT8 AdminName;
116 UINT8 UserName;
117 } EFI_PASSWORD_STATUS;
118
119 //
120 // Config Data
121 //
122 typedef struct {
123 UINT8 SerialDebug;
124 UINT8 SerialDebugBaudRate;
125 UINT8 RamDebugInterface;
126 UINT8 UartDebugInterface;
127 UINT8 Usb3DebugInterface;
128 UINT8 SerialIoDebugInterface;
129 UINT8 TraceHubDebugInterface;
130 } DEBUG_CONFIG_DATA;
131
132 //
133 // Config Data Hob
134 //
135 #define DEBUG_CONFIG_DATA_HOB DEBUG_CONFIG_DATA
136
137 #pragma pack()
138
139 //
140 // Varstore statement
141 // Setup is EfiVarStore that is related to EFI variable with attribute 0x07
142 // (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS)
143 //
144 #define SETUP_DATA_VARSTORE\
145 efivarstore SETUP_DATA, varid = 1,\
146 attribute = 0x7, name = Setup, guid = SETUP_GUID;
147 #define SA_SETUP_VARSTORE\
148 efivarstore SA_SETUP, varid = 2,\
149 attribute = 0x7, name = SaSetup, guid = SA_SETUP_GUID;
150 #define CPU_SETUP_VARSTORE\
151 efivarstore CPU_SETUP, varid = 3,\
152 attribute = 0x7, name = CpuSetup, guid = CPU_SETUP_GUID;
153 #define ME_SETUP_VARSTORE\
154 efivarstore ME_SETUP, varid = 4,\
155 attribute = 0x7, name = MeSetup, guid = ME_SETUP_GUID;
156 #define PCH_SETUP_VARSTORE\
157 efivarstore PCH_SETUP, varid = 5,\
158 attribute = 0x7, name = PchSetup, guid = PCH_SETUP_GUID;
159 #define SI_SETUP_VARSTORE\
160 efivarstore SI_SETUP, varid = 6,\
161 attribute = 0x7, name = SiSetup, guid = SI_SETUP_GUID;
162 #ifdef DEBUG_INTERFACE_FORM_ENABLE
163 #define DEBUG_CONFIG_DATA_ID 0xF001
164 #define DEBUG_CONFIG_DATA_VARSTORE\
165 efivarstore DEBUG_CONFIG_DATA, varid = DEBUG_CONFIG_DATA_ID,\
166 attribute = 0x7, name = DebugConfigData, guid = DEBUG_CONFIG_GUID;
167 #endif // DEBUG_INTERFACE_FORM_ENABLE
168 #define SYSTEM_ACCESS_VARSTORE\
169 varstore SYSTEM_ACCESS, varid = SYSTEM_ACCESS_KEY_ID,\
170 name = SystemAccess, guid = SYSTEM_ACCESS_GUID;
171 #define SYSTEM_PASSWORD_VARSTORE\
172 varstore EFI_PASSWORD_STATUS,\
173 name = PasswordStatus, guid = SYSTEM_ACCESS_GUID;
174
175 #define BOOT_FLOW_CONDITION_RECOVERY 2
176 #define BOOT_FLOW_CONDITION_FIRST_BOOT 4
177
178 #endif
SHA256_DIGEST_SIZE
#define SHA256_DIGEST_SIZE
SHA-256 digest size in bytes.
Definition: Setup.h:91
SetupConfiguration.h
Default platform setup configuration settings.
SetupVariable.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SetupConfiguration.h Source File

SetupConfiguration.h
Go to the documentation of this file.
1 /** @file
2 Default platform setup configuration settings.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2009 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _SETUP_CONFIGURATION_H_
36 #define _SETUP_CONFIGURATION_H_
37
38 #define SERIAL_SETUP_OPTION 1
39 #define TOTAL_SIO_SERIAL_PORTS 0x4
40 #define TOTAL_PCI_SERIAL_PORTS 0x1
41 #define TOTAL_SERIAL_PORTS 0x5
42 #define MAX_SIO_SERIAL_PORTS 0x4
43 #define MAX_PCI_SERIAL_PORTS 0x4
44
45 #define DEFAULT_CONSOLE_REDIRECTION_ENABLE 1
46 #define DEFAULT_ACPI_SPCR_COM_PORT 0x0
47 #define DEFAULT_TERMINAL_TYPE 0x3
48 #define DEFAULT_RESOLUTION_TYPE 0x0
49 #define DEFAULT_ACPI_SPCR_CONSOLE_REDIRECTION_ENABLE 1
50 #define DEFAULT_ACPI_SPCR_TABLE_TERMINAL_TYPE 0x2
51 #define HARDWARE_FLOW_CONTROL_SETUP_OPTION 0x1
52 #define SOFTWARE_FLOW_CONTROL_SETUP_OPTION 0x2
53 #define TIMEOUT_FOR_DETERMINING_LONE_ESC_CHAR 0xf4240
54
55 #define DEFAULT_BOOT_TIMEOUT 0x1
56 #define DEFAULT_FAST_BOOT 0
57 #define DEFAULT_QUIET_BOOT 0
58 #define PASSWORD_MAX_SIZE 0x15
59 #define VFR_PASSWORD_MAX_SIZE 0x14
60 #define FORCE_USER_TO_SETUP_ON_FIRST_BOOT 0
61 #define SHOW_ADVANCED_FORMSET 1
62 #define FORCE_USER_TO_SETUP_IF_BOOT_WITH_DEFAULT 0
63 #define LOAD_DEFAULTS_IF_SECONDARY_NVRAM_INIT 1
64
65 #define UART_SERIAL_PORT_0_INDEX 0x0
66 #define UART_SERIAL_PORT_1_INDEX 0x1
67 #define UART_SERIAL_PORT_2_INDEX 0x2
68 #define UART_SERIAL_PORT_3_INDEX 0x3
69 #define PCI_SERIAL_PORT_0_INDEX 0x4
70 #define PCI_SERIAL_PORT_1_INDEX 0x5
71 #define PCI_SERIAL_PORT_2_INDEX 0x6
72 #define PCI_SERIAL_PORT_3_INDEX 0x7
73
74 #define OFFSET_0 0x0
75 #define OFFSET_1 0x1
76 #define OFFSET_2 0x2
77 #define OFFSET_3 0x3
78 #define OFFSET_4 0x4
79 #define OFFSET_5 0x5
80 #define OFFSET_6 0x6
81 #define OFFSET_7 0x7
82 #define OFFSET_8 0x8
83 #define OFFSET_9 0x9
84 #define OFFSET_10 0xa
85 #define OFFSET_11 0xb
86 #define OFFSET_12 0xc
87 #define OFFSET_13 0xd
88 #define OFFSET_14 0xe
89 #define OFFSET_15 0xf
90 #define OFFSET_16 0x10
91 #define OFFSET_17 0x11
92 #define OFFSET_18 0x12
93 #define OFFSET_19 0x13
94 #define OFFSET_20 0x14
95 #define OFFSET_21 0x15
96 #define OFFSET_22 0x16
97 #define OFFSET_23 0x17
98 #define OFFSET_24 0x18
99 #define OFFSET_25 0x19
100 #define OFFSET_26 0x1a
101 #define OFFSET_27 0x1b
102 #define OFFSET_28 0x1c
103 #define OFFSET_29 0x1d
104 #define OFFSET_30 0x1e
105 #define OFFSET_31 0x1f
106 #define OFFSET_32 0x20
107 #define OFFSET_33 0x21
108 #define OFFSET_34 0x22
109 #define OFFSET_35 0x23
110 #define OFFSET_36 0x24
111 #define OFFSET_37 0x25
112 #define OFFSET_38 0x26
113 #define OFFSET_39 0x27
114 #define ENGLISH en-US
115
116 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SetupVariable.h Source File

SetupVariable.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SETUP_VARIABLE_H_
35 #define _SETUP_VARIABLE_H_
36
37 #include <PchLimits.h>
38
39 #ifndef MAX_CUSTOM_P_STATES
40 #define MAX_CUSTOM_P_STATES 40
41 #endif // MAX_CUSTOM_P_STATES
42 #ifndef MAX_16_CUSTOM_P_STATES
43 #define MAX_16_CUSTOM_P_STATES 16
44 #endif // MAX_16_CUSTOM_P_STATES
45
46 #define MAX_IIO_PCI_EXPRESS_ROOT_PORTS 4
47 #define MAX_PCI_ROOT_BRIDGES 1
48 #define SATA_MODE_AHCI 0
49 #define SATA_MODE_RAID 1
50 #define SATA_TEST_MODE_ENABLE 1
51 #define NON_CS_DEVICES 9
52 #define I2C0_SENSOR_DEVICES 7
53 #define I2C1_SENSOR_DEVICES 13
54 #define SERIAL_IO_I2C0 0x0
55 #define SERIAL_IO_I2C1 0x1
56 #define SERIAL_IO_I2C2 0x2
57 #define SERIAL_IO_I2C3 0x3
58 #define SERIAL_IO_I2C4 0x4
59 #define SERIAL_IO_I2C5 0x5
60 #define SERIAL_IO_SPI0 0x6
61 #define SERIAL_IO_SPI1 0x7
62 #define SERIAL_IO_SPI2 0x8
63 #define SERIAL_IO_UART0 0x9
64 #define SERIAL_IO_UART1 0xA
65 #define SERIAL_IO_UART2 0xB
66 #define HDAUDIO_FEATURES 9
67 #define HDAUDIO_PP_MODULES 32
68 #define HDAUDIO_LINK_MODE_HDA 0
69 #define HDAUDIO_LINK_MODE_I2S_SSP 1
70 #define HDAUDIO_LINK_MODE_SNDW 2
71 #define HDAUDIO_LINK_MODE_ADVANCED 3
72 #define HDAUDIO_LINK_HDA 0
73 #define HDAUDIO_LINK_DMIC0 1
74 #define HDAUDIO_LINK_DMIC1 2
75 #define HDAUDIO_LINK_SSP0 3
76 #define HDAUDIO_LINK_SSP1 4
77 #define HDAUDIO_LINK_SSP2 5
78 #define HDAUDIO_LINK_SSP3 6
79 #define HDAUDIO_LINK_SSP4 7
80 #define HDAUDIO_LINK_SSP5 8
81 #define HDAUDIO_LINK_SNDW1 9
82 #define HDAUDIO_LINK_SNDW2 10
83 #define HDAUDIO_LINK_SNDW3 11
84 #define HDAUDIO_LINK_SNDW4 12
85 #define HDAUDIO_LINKS_NUMBER 13
86 #define GUID_CHARS_NUMBER 37 // 36 GUID chars + null termination
87 #ifdef PCH_ICL
88 #define FIVR_RAIL_S0IX_SX_STATES_MAX 5 // Number of availabe S0ix/Sx policy bits in FIVR Rail configuration
89 #endif
90
91 #define EFI_CSM_CONTROL_ALWAYS_ON 0x0
92 #define EFI_CSM_CONTROL_ALWAYS_OFF 0x1
93 #define EFI_CSM_CONTROL_DETECT_LEGACY_VGA 0x2
94
95 #define OPROM_EFI 1
96 #define OPROM_LEGACY 0
97
98 #define MIPICAM_I2C_DEVICES_COUNT 12
99 #define MIPICAM_GPIO_COUNT 4
100 #define MIPICAM_MODULE_NAME_LENGTH 16
101 #define MIPICAM_HID_LENGTH 9
102 #define DTBT_CONTROLLER_SUPPORTED 2
103 #define ITBT_ROOT_PORTS_SUPPORTED 6
104 #define ITBT_HOST_DMA_SUPPORTED 3
105 #ifndef SGX_SOFTWARE_CONTROL
106 #define SGX_SOFTWARE_CONTROL 2
107 #endif
108
109 #pragma pack(1)
110 /**
111 Making any setup structure change after code frozen
112 will need to maintain backward compatibility, bump up
113 structure revision and update below history table\n
114 <b>Revision 1</b>: - Initial version.
115 **/
116
117 #define SETUP_DATA_REVISION 1
118
119 typedef struct {
120 UINT8 Revision;
121 UINT8 FastBoot;
122 UINT8 FastBootWdt;
123 UINT8 SkipHIIUpdate;
124 UINT8 ConInBehavior;
125 UINT8 DisplayBootMode;
126 UINT8 Numlock;
127 UINT8 InteractiveText;
128 UINT8 LazyConIn;
129 UINT8 VirtualKeyboard;
130 UINT8 FirmwareConfiguration;
131 UINT8 OpRomPost; // [Legacy] \ EFI Compatible
132 // General PCI Settings: [] - default
133 UINT8 PciLatency; //[32]\ 64 \ 96 \ 128 \ 160 \ 192 \ 224 \ 248
134 #ifdef PCI_X_SUPPORT
135 UINT8 PciXLatency; // 32 \[64]\ 96 \ 128 \ 160 \ 192 \ 224 \ 248
136 #endif // PCI_X_SUPPORT
137 #ifdef PCI_EXPRESS_SUPPORT
138 #ifdef PCI_EXPRESS_INIT_SUPPORT
139 // PCI Express Device Settings: [] - default
140 UINT8 RelaxedOrdering; //[Disable]\ Enable
141 UINT8 ExtTagField; //[Disable]\ Enable
142 UINT8 NoSnoop; // Disable \[Enable]
143 UINT8 MaxPayload; // [Auto]\ 128 \ 256 \ 512 \ 1024 \ 2048 \ 4096 (in bytes)
144 UINT8 MaxReadRequest; // [Auto]\ 128 \ 256 \ 512 \ 1024 \ 2048 \ 4096 (in bytes)
145 // PCI Express Link settings: [] - default
146 UINT8 AspmMode; // [Disable]\ Auto \ Force L0
147 UINT8 ExtendedSynch; // [Disable]\ Enable
148 #endif // PCI_EXPRESS_INIT_SUPPORT
149 #endif // PCI_EXPRESS_SUPPORT
150 UINT8 AcpiAuto;
151 UINT8 AcpiSleepState;
152 UINT8 AcpiHibernate;
153 UINT8 AcpiTableRevision;
154 UINT8 PciExpNative;
155 UINT8 NativeAspmEnable;
156 UINT8 PtidSupport;
157 // AcpiDebug Setup Options
158 UINT8 AcpiDebug;
159 UINT32 AcpiDebugAddress;
160 UINT8 PciDelayOptimizationEcr;
161 // S5 RTC wakeup setup options
162 UINT8 WakeOnRTCS5;
163 UINT8 RTCWakeupDate;
164 UINT8 RTCWakeupTimeHour;
165 UINT8 RTCWakeupTimeMinute;
166 UINT8 RTCWakeupTimeSecond;
167 UINT8 PeciAccessMethod;
168 UINT8 LowPowerS0Idle;
169 UINT8 PepCpu;
170 UINT8 PepGfx;
171 UINT8 PepSataContraints;
172 UINT8 PepUart;
173 UINT8 PepI2c0;
174 UINT8 PepI2c1;
175 UINT8 PepI2c2;
176 UINT8 PepI2c3;
177 UINT8 PepI2c4;
178 UINT8 PepI2c5;
179 UINT8 PepSpi;
180 UINT8 PepXhci;
181 UINT8 PepAudio;
182 UINT8 PepEmmc;
183 UINT8 PepSdxc;
184 UINT8 PepIpu;
185 UINT8 PepCsme;
186 UINT8 CSNotifyEC;
187 UINT8 CSDebugLightEC;
188 UINT8 EcLowPowerMode;
189 UINT8 EcDebugLed;
190 UINT8 ECBaseCsPwrPolicy;
191 UINT8 SensorStandby;
192 UINT8 PL1LimitCS;
193 UINT16 PL1LimitCSValue;
194 UINT8 TenSecondPowerButtonSupport;
195 UINT8 TenSecondPowerButtonEnable;
196 UINT8 LpitResidencyCounter;
197 UINT8 IrmtConfiguration;
198 // Reading SSDT table from file
199 UINT8 LoadSSDTFromFile;
200 //
201 // On Screen Branding
202 //
203 UINT16 OperatingSystem;
204 UINT16 OemBadgingBrand;
205 UINT8 BootFirstToShell;
206
207 UINT8 SensorHubType;
208 UINT8 DebugUsbUartSupport;
209 UINT8 DebugUsbUart;
210 UINT8 PxeRom;
211 UINT8 EfiNetworkSupport;
212 UINT8 Reserved; // Get rid of "EnableClockSpreadSpec"
213 UINT8 UsbSensorHub;
214
215 UINT8 HddAcousticPowerManagement;
216 UINT8 HddAcousticMode;
217
218 //
219 // Recovery Configuration
220 //
221 UINT8 IsRecoveryJumper;
222
223 //
224 // MipiCam sensor configuration menu
225 //
226 UINT8 MipiCam_ControlLogic0; // None/discrete/PMIC
227 UINT8 MipiCam_ControlLogic1; // None/discrete/PMIC
228 UINT8 MipiCam_ControlLogic2; // None/discrete/PMIC
229 UINT8 MipiCam_ControlLogic3; // None/discrete/PMIC
230
231 UINT8 MipiCam_Link0; // Enabled / Disabled
232 UINT8 MipiCam_Link1; // Enabled / Disabled
233 UINT8 MipiCam_Link2; // Enabled / Disabled
234 UINT8 MipiCam_Link3; // Enabled / Disabled
235
236 UINT8 MipiCam_LanesClkDiv;
237
238 UINT8 MipiCam_ControlLogic0_Type;
239 UINT8 MipiCam_ControlLogic0_CrdVersion;
240 UINT32 MipiCam_ControlLogic0_InputClock;
241 UINT8 MipiCam_ControlLogic0_PchClockSource;
242 UINT8 MipiCam_ControlLogic0_GpioPinsEnabled;
243 UINT8 MipiCam_ControlLogic0_I2cChannel;
244 UINT16 MipiCam_ControlLogic0_I2cAddress;
245 UINT8 MipiCam_ControlLogic0_Pld;
246 UINT8 MipiCam_ControlLogic0_Wled1FlashMaxCurrent;
247 UINT8 MipiCam_ControlLogic0_Wled1TorchMaxCurrent;
248 UINT8 MipiCam_ControlLogic0_Wled2FlashMaxCurrent;
249 UINT8 MipiCam_ControlLogic0_Wled2TorchMaxCurrent;
250 UINT8 MipiCam_ControlLogic0_SubPlatformId;
251 UINT8 MipiCam_ControlLogic0_Wled1Type;
252 UINT8 MipiCam_ControlLogic0_Wled2Type;
253 UINT8 MipiCam_ControlLogic0_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
254 UINT8 MipiCam_ControlLogic0_GpioGroupNumber[MIPICAM_GPIO_COUNT];
255 UINT8 MipiCam_ControlLogic0_GpioFunction[MIPICAM_GPIO_COUNT];
256 UINT8 MipiCam_ControlLogic0_GpioActiveValue[MIPICAM_GPIO_COUNT];
257 UINT8 MipiCam_ControlLogic0_GpioInitialValue[MIPICAM_GPIO_COUNT];
258
259 UINT8 MipiCam_ControlLogic1_Type;
260 UINT8 MipiCam_ControlLogic1_CrdVersion;
261 UINT32 MipiCam_ControlLogic1_InputClock;
262 UINT8 MipiCam_ControlLogic1_PchClockSource;
263 UINT8 MipiCam_ControlLogic1_GpioPinsEnabled;
264 UINT8 MipiCam_ControlLogic1_I2cChannel;
265 UINT16 MipiCam_ControlLogic1_I2cAddress;
266 UINT8 MipiCam_ControlLogic1_Pld;
267 UINT8 MipiCam_ControlLogic1_Wled1FlashMaxCurrent;
268 UINT8 MipiCam_ControlLogic1_Wled1TorchMaxCurrent;
269 UINT8 MipiCam_ControlLogic1_Wled2FlashMaxCurrent;
270 UINT8 MipiCam_ControlLogic1_Wled2TorchMaxCurrent;
271 UINT8 MipiCam_ControlLogic1_SubPlatformId;
272 UINT8 MipiCam_ControlLogic1_Wled1Type;
273 UINT8 MipiCam_ControlLogic1_Wled2Type;
274 UINT8 MipiCam_ControlLogic1_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
275 UINT8 MipiCam_ControlLogic1_GpioGroupNumber[MIPICAM_GPIO_COUNT];
276 UINT8 MipiCam_ControlLogic1_GpioFunction[MIPICAM_GPIO_COUNT];
277 UINT8 MipiCam_ControlLogic1_GpioActiveValue[MIPICAM_GPIO_COUNT];
278 UINT8 MipiCam_ControlLogic1_GpioInitialValue[MIPICAM_GPIO_COUNT];
279
280 UINT8 MipiCam_ControlLogic2_Type;
281 UINT8 MipiCam_ControlLogic2_CrdVersion;
282 UINT32 MipiCam_ControlLogic2_InputClock;
283 UINT8 MipiCam_ControlLogic2_PchClockSource;
284 UINT8 MipiCam_ControlLogic2_GpioPinsEnabled;
285 UINT8 MipiCam_ControlLogic2_I2cChannel;
286 UINT16 MipiCam_ControlLogic2_I2cAddress;
287 UINT8 MipiCam_ControlLogic2_Pld;
288 UINT8 MipiCam_ControlLogic2_Wled1FlashMaxCurrent;
289 UINT8 MipiCam_ControlLogic2_Wled1TorchMaxCurrent;
290 UINT8 MipiCam_ControlLogic2_Wled2FlashMaxCurrent;
291 UINT8 MipiCam_ControlLogic2_Wled2TorchMaxCurrent;
292 UINT8 MipiCam_ControlLogic2_SubPlatformId;
293 UINT8 MipiCam_ControlLogic2_Wled1Type;
294 UINT8 MipiCam_ControlLogic2_Wled2Type;
295 UINT8 MipiCam_ControlLogic2_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
296 UINT8 MipiCam_ControlLogic2_GpioGroupNumber[MIPICAM_GPIO_COUNT];
297 UINT8 MipiCam_ControlLogic2_GpioFunction[MIPICAM_GPIO_COUNT];
298 UINT8 MipiCam_ControlLogic2_GpioActiveValue[MIPICAM_GPIO_COUNT];
299 UINT8 MipiCam_ControlLogic2_GpioInitialValue[MIPICAM_GPIO_COUNT];
300
301 UINT8 MipiCam_ControlLogic3_Type;
302 UINT8 MipiCam_ControlLogic3_CrdVersion;
303 UINT32 MipiCam_ControlLogic3_InputClock;
304 UINT8 MipiCam_ControlLogic3_PchClockSource;
305 UINT8 MipiCam_ControlLogic3_GpioPinsEnabled;
306 UINT8 MipiCam_ControlLogic3_I2cChannel;
307 UINT16 MipiCam_ControlLogic3_I2cAddress;
308 UINT8 MipiCam_ControlLogic3_Pld;
309 UINT8 MipiCam_ControlLogic3_Wled1FlashMaxCurrent;
310 UINT8 MipiCam_ControlLogic3_Wled1TorchMaxCurrent;
311 UINT8 MipiCam_ControlLogic3_Wled2FlashMaxCurrent;
312 UINT8 MipiCam_ControlLogic3_Wled2TorchMaxCurrent;
313 UINT8 MipiCam_ControlLogic3_SubPlatformId;
314 UINT8 MipiCam_ControlLogic3_Wled1Type;
315 UINT8 MipiCam_ControlLogic3_Wled2Type;
316 UINT8 MipiCam_ControlLogic3_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
317 UINT8 MipiCam_ControlLogic3_GpioGroupNumber[MIPICAM_GPIO_COUNT];
318 UINT8 MipiCam_ControlLogic3_GpioFunction[MIPICAM_GPIO_COUNT];
319 UINT8 MipiCam_ControlLogic3_GpioActiveValue[MIPICAM_GPIO_COUNT];
320 UINT8 MipiCam_ControlLogic3_GpioInitialValue[MIPICAM_GPIO_COUNT];
321
322 UINT8 MipiCam_Link0_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User0
323 UINT16 MipiCam_Link0_UserHid[MIPICAM_HID_LENGTH];
324 UINT8 MipiCam_Link0_CameraPhysicalLocation;
325 UINT16 MipiCam_Link0_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
326 UINT8 MipiCam_Link0_I2cDevicesEnabled; // number of I2C devices defined for this link
327 UINT8 MipiCam_Link0_I2cChannel;
328 UINT16 MipiCam_Link0_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
329 UINT8 MipiCam_Link0_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
330 UINT8 MipiCam_Link0_DriverData_Version;
331 UINT8 MipiCam_Link0_DriverData_CrdVersion;
332 UINT8 MipiCam_Link0_DriverData_LaneUsed;
333 UINT8 MipiCam_Link0_DriverData_EepromType;
334 UINT8 MipiCam_Link0_DriverData_VcmType;
335 UINT8 MipiCam_Link0_DriverData_CustomData[4];
336 UINT32 MipiCam_Link0_DriverData_Mclk;
337 UINT8 MipiCam_Link0_DriverData_ControlLogic;
338 UINT8 MipiCam_Link0_DriverData_FlashSupport;
339 UINT8 MipiCam_Link0_DriverData_PrivacyLed;
340 UINT8 MipiCam_Link0_DriverData_Degree;
341 UINT8 MipiCam_Link0_DriverData_PmicPosition;
342 UINT8 MipiCam_Link0_DriverData_VoltageRail;
343
344 UINT8 MipiCam_Link1_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User1
345 UINT16 MipiCam_Link1_UserHid[MIPICAM_HID_LENGTH];
346 UINT8 MipiCam_Link1_CameraPhysicalLocation;
347 UINT16 MipiCam_Link1_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
348 UINT8 MipiCam_Link1_I2cDevicesEnabled; // number of I2C devices defined for this link
349 UINT8 MipiCam_Link1_I2cChannel;
350 UINT16 MipiCam_Link1_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
351 UINT8 MipiCam_Link1_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
352 UINT8 MipiCam_Link1_DriverData_Version;
353 UINT8 MipiCam_Link1_DriverData_CrdVersion;
354 UINT8 MipiCam_Link1_DriverData_LaneUsed;
355 UINT8 MipiCam_Link1_DriverData_EepromType;
356 UINT8 MipiCam_Link1_DriverData_VcmType;
357 UINT8 MipiCam_Link1_DriverData_CustomData[4];
358 UINT32 MipiCam_Link1_DriverData_Mclk;
359 UINT8 MipiCam_Link1_DriverData_ControlLogic;
360 UINT8 MipiCam_Link1_DriverData_FlashSupport;
361 UINT8 MipiCam_Link1_DriverData_PrivacyLed;
362 UINT8 MipiCam_Link1_DriverData_Degree;
363 UINT8 MipiCam_Link1_DriverData_PmicPosition;
364 UINT8 MipiCam_Link1_DriverData_VoltageRail;
365
366 UINT8 MipiCam_Link2_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User2
367 UINT16 MipiCam_Link2_UserHid[MIPICAM_HID_LENGTH];
368 UINT8 MipiCam_Link2_CameraPhysicalLocation;
369 UINT16 MipiCam_Link2_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
370 UINT8 MipiCam_Link2_I2cDevicesEnabled; // number of I2C devices defined for this link
371 UINT8 MipiCam_Link2_I2cChannel;
372 UINT16 MipiCam_Link2_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
373 UINT8 MipiCam_Link2_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
374 UINT8 MipiCam_Link2_DriverData_Version;
375 UINT8 MipiCam_Link2_DriverData_CrdVersion;
376 UINT8 MipiCam_Link2_DriverData_LaneUsed;
377 UINT8 MipiCam_Link2_DriverData_EepromType;
378 UINT8 MipiCam_Link2_DriverData_VcmType;
379 UINT8 MipiCam_Link2_DriverData_CustomData[4];
380 UINT32 MipiCam_Link2_DriverData_Mclk;
381 UINT8 MipiCam_Link2_DriverData_ControlLogic;
382 UINT8 MipiCam_Link2_DriverData_FlashSupport;
383 UINT8 MipiCam_Link2_DriverData_PrivacyLed;
384 UINT8 MipiCam_Link2_DriverData_Degree;
385 UINT8 MipiCam_Link2_DriverData_PmicPosition;
386 UINT8 MipiCam_Link2_DriverData_VoltageRail;
387
388 UINT8 MipiCam_Link3_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User3
389 UINT16 MipiCam_Link3_UserHid[MIPICAM_HID_LENGTH];
390 UINT8 MipiCam_Link3_CameraPhysicalLocation;
391 UINT16 MipiCam_Link3_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
392 UINT8 MipiCam_Link3_I2cDevicesEnabled; // number of I2C devices defined for this link
393 UINT8 MipiCam_Link3_I2cChannel;
394 UINT16 MipiCam_Link3_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
395 UINT8 MipiCam_Link3_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
396 UINT8 MipiCam_Link3_DriverData_Version;
397 UINT8 MipiCam_Link3_DriverData_CrdVersion;
398 UINT8 MipiCam_Link3_DriverData_LaneUsed;
399 UINT8 MipiCam_Link3_DriverData_EepromType;
400 UINT8 MipiCam_Link3_DriverData_VcmType;
401 UINT8 MipiCam_Link3_DriverData_CustomData[4];
402 UINT32 MipiCam_Link3_DriverData_Mclk;
403 UINT8 MipiCam_Link3_DriverData_ControlLogic;
404 UINT8 MipiCam_Link3_DriverData_FlashSupport;
405 UINT8 MipiCam_Link3_DriverData_PrivacyLed;
406 UINT8 MipiCam_Link3_DriverData_Degree;
407 UINT8 MipiCam_Link3_DriverData_PmicPosition;
408 UINT8 MipiCam_Link3_DriverData_VoltageRail;
409
410 UINT8 PchI2c0SensorDevice;
411 UINT8 PchI2c0TouchpadBusAddress;
412 UINT16 PchI2c0TouchpadHidAddress;
413 UINT8 PchI2c0TouchpadSpeed;
414 UINT8 PchI2c0SensorIrqMode;
415 UINT8 PchI2c1SensorDevice;
416 UINT8 PchI2c1SensorIrqMode;
417 UINT8 PchI2c1TouchpanelBusAddress;
418 UINT16 PchI2c1TouchpanelHidAddress;
419 UINT8 PchI2c1TouchpanelSpeed;
420 UINT8 PchI2c2SensorDevice;
421 UINT8 PchI2c2TouchpadBusAddress;
422 UINT16 PchI2c2TouchpadHidAddress;
423 UINT8 PchI2c2TouchpadSpeed;
424 UINT8 PchI2c2SensorIrqMode;
425 UINT8 PchI2c3SensorDevice;
426 UINT8 PchI2c4SensorDevice;
427 UINT8 PchSpi1SensorDevice;
428 UINT8 PchSpi1SensorIrqMode;
429 UINT8 PchI2c5SensorDevice;
430 UINT8 PchUart1SensorDevice;
431 UINT8 PchUart2SensorDevice;
432 UINT8 PchI2cWittDevice;
433 UINT8 PchI2cWittVersion;
434 UINT8 PchUartUtkDevice;
435 UINT8 DiscreteBtModule;
436 UINT8 DiscreteBtModuleIrqMode;
437
438 UINT8 PchSerialIoUseTimingParameters;
439
440 UINT16 PchSerialIoTimingSSH0; // [SSH0] SSCN-HIGH for I2C0
441 UINT16 PchSerialIoTimingSSL0; // [SSL0] SSCN-LOW for I2C0
442 UINT16 PchSerialIoTimingSSD0; // [SSD0] SSCN-HOLD for I2C0
443 UINT16 PchSerialIoTimingFMH0; // [FMH0] FMCN-HIGH for I2C0
444 UINT16 PchSerialIoTimingFML0; // [FML0] FMCN-LOW for I2C0
445 UINT16 PchSerialIoTimingFMD0; // [FMD0] FMCN-HOLD for I2C0
446 UINT16 PchSerialIoTimingFPH0; // [FPH0] FPCN-HIGH for I2C0
447 UINT16 PchSerialIoTimingFPL0; // [FPL0] FPCN-LOW for I2C0
448 UINT16 PchSerialIoTimingFPD0; // [FPD0] FPCN-HOLD for I2C0
449 UINT16 PchSerialIoTimingHMH0; // [HMH0] HMCN-HIGH for I2C0
450 UINT16 PchSerialIoTimingHML0; // [HML0] HMCN-LOW for I2C0
451 UINT16 PchSerialIoTimingHMD0; // [HMD0] HMCN-HOLD for I2C0
452
453 UINT16 PchSerialIoTimingSSH1; // [SSH1] SSCN-HIGH for I2C1
454 UINT16 PchSerialIoTimingSSL1; // [SSL1] SSCN-LOW for I2C1
455 UINT16 PchSerialIoTimingSSD1; // [SSD1] SSCN-HOLD for I2C1
456 UINT16 PchSerialIoTimingFMH1; // [FMH1] FMCN-HIGH for I2C1
457 UINT16 PchSerialIoTimingFML1; // [FML1] FMCN-LOW for I2C1
458 UINT16 PchSerialIoTimingFMD1; // [FMD1] FMCN-HOLD for I2C1
459 UINT16 PchSerialIoTimingFPH1; // [FPH1] FPCN-HIGH for I2C1
460 UINT16 PchSerialIoTimingFPL1; // [FPL1] FPCN-LOW for I2C1
461 UINT16 PchSerialIoTimingFPD1; // [FPD1] FPCN-HOLD for I2C1
462 UINT16 PchSerialIoTimingHMH1; // [HMH1] HMCN-HIGH for I2C1
463 UINT16 PchSerialIoTimingHML1; // [HML1] HMCN-LOW for I2C1
464 UINT16 PchSerialIoTimingHMD1; // [HMD1] HMCN-HOLD for I2C1
465
466 UINT16 PchSerialIoTimingSSH2; // [SSH2] SSCN-HIGH for I2C2
467 UINT16 PchSerialIoTimingSSL2; // [SSL2] SSCN-LOW for I2C2
468 UINT16 PchSerialIoTimingSSD2; // [SSD2] SSCN-HOLD for I2C2
469 UINT16 PchSerialIoTimingFMH2; // [FMH2] FMCN-HIGH for I2C2
470 UINT16 PchSerialIoTimingFML2; // [FML2] FMCN-LOW for I2C2
471 UINT16 PchSerialIoTimingFMD2; // [FMD2] FMCN-HOLD for I2C2
472 UINT16 PchSerialIoTimingFPH2; // [FPH2] FPCN-HIGH for I2C2
473 UINT16 PchSerialIoTimingFPL2; // [FPL2] FPCN-LOW for I2C2
474 UINT16 PchSerialIoTimingFPD2; // [FPD2] FPCN-HOLD for I2C2
475 UINT16 PchSerialIoTimingHMH2; // [HMH2] HMCN-HIGH for I2C2
476 UINT16 PchSerialIoTimingHML2; // [HML2] HMCN-LOW for I2C2
477 UINT16 PchSerialIoTimingHMD2; // [HMD2] HMCN-HOLD for I2C2
478
479 UINT16 PchSerialIoTimingSSH3; // [SSH3] SSCN-HIGH for I2C3
480 UINT16 PchSerialIoTimingSSL3; // [SSL3] SSCN-LOW for I2C3
481 UINT16 PchSerialIoTimingSSD3; // [SSD3] SSCN-HOLD for I2C3
482 UINT16 PchSerialIoTimingFMH3; // [FMH3] FMCN-HIGH for I2C3
483 UINT16 PchSerialIoTimingFML3; // [FML3] FMCN-LOW for I2C3
484 UINT16 PchSerialIoTimingFMD3; // [FMD3] FMCN-HOLD for I2C3
485 UINT16 PchSerialIoTimingFPH3; // [FPH3] FPCN-HIGH for I2C3
486 UINT16 PchSerialIoTimingFPL3; // [FPL3] FPCN-LOW for I2C3
487 UINT16 PchSerialIoTimingFPD3; // [FPD3] FPCN-HOLD for I2C3
488 UINT16 PchSerialIoTimingHMH3; // [HMH3] HMCN-HIGH for I2C3
489 UINT16 PchSerialIoTimingHML3; // [HML3] HMCN-LOW for I2C3
490 UINT16 PchSerialIoTimingHMD3; // [HMD3] HMCN-HOLD for I2C3
491
492 UINT16 PchSerialIoTimingSSH4; // [SSH4] SSCN-HIGH for I2C4
493 UINT16 PchSerialIoTimingSSL4; // [SSL4] SSCN-LOW for I2C4
494 UINT16 PchSerialIoTimingSSD4; // [SSD4] SSCN-HOLD for I2C4
495 UINT16 PchSerialIoTimingFMH4; // [FMH4] FMCN-HIGH for I2C4
496 UINT16 PchSerialIoTimingFML4; // [FML4] FMCN-LOW for I2C4
497 UINT16 PchSerialIoTimingFMD4; // [FMD4] FMCN-HOLD for I2C4
498 UINT16 PchSerialIoTimingFPH4; // [FPH4] FPCN-HIGH for I2C4
499 UINT16 PchSerialIoTimingFPL4; // [FPL4] FPCN-LOW for I2C4
500 UINT16 PchSerialIoTimingFPD4; // [FPD4] FPCN-HOLD for I2C4
501 UINT16 PchSerialIoTimingHMH4; // [HMH4] HMCN-HIGH for I2C4
502 UINT16 PchSerialIoTimingHML4; // [HML4] HMCN-LOW for I2C4
503 UINT16 PchSerialIoTimingHMD4; // [HMD4] HMCN-HOLD for I2C4
504
505 UINT16 PchSerialIoTimingSSH5; // [SSH5] SSCN-HIGH for I2C5
506 UINT16 PchSerialIoTimingSSL5; // [SSL5] SSCN-LOW for I2C5
507 UINT16 PchSerialIoTimingSSD5; // [SSD5] SSCN-HOLD for I2C5
508 UINT16 PchSerialIoTimingFMH5; // [FMH5] FMCN-HIGH for I2C5
509 UINT16 PchSerialIoTimingFML5; // [FML5] FMCN-LOW for I2C5
510 UINT16 PchSerialIoTimingFMD5; // [FMD5] FMCN-HOLD for I2C5
511 UINT16 PchSerialIoTimingFPH5; // [FPH5] FPCN-HIGH for I2C5
512 UINT16 PchSerialIoTimingFPL5; // [FPL5] FPCN-LOW for I2C5
513 UINT16 PchSerialIoTimingFPD5; // [FPD5] FPCN-HOLD for I2C5
514 UINT16 PchSerialIoTimingHMH5; // [HMH5] HMCN-HIGH for I2C5
515 UINT16 PchSerialIoTimingHML5; // [HML5] HMCN-LOW for I2C5
516 UINT16 PchSerialIoTimingHMD5; // [HMD5] HMCN-HOLD for I2C5
517
518 UINT16 PchSerialIoTimingM0C0; // [M0C0] M0D3 for I2C0
519 UINT16 PchSerialIoTimingM1C0; // [M1C0] M1D3 for I2C0
520 UINT16 PchSerialIoTimingM0C1; // [M0C1] M0D3 for I2C1
521 UINT16 PchSerialIoTimingM1C1; // [M1C1] M1D3 for I2C1
522 UINT16 PchSerialIoTimingM0C2; // [M0C2] M0D3 for I2C2
523 UINT16 PchSerialIoTimingM1C2; // [M1C2] M1D3 for I2C2
524 UINT16 PchSerialIoTimingM0C3; // [M0C3] M0D3 for I2C3
525 UINT16 PchSerialIoTimingM1C3; // [M1C3] M1D3 for I2C3
526 UINT16 PchSerialIoTimingM0C4; // [M0C4] M0D3 for I2C4
527 UINT16 PchSerialIoTimingM1C4; // [M1C4] M1D3 for I2C4
528 UINT16 PchSerialIoTimingM0C5; // [M0C5] M0D3 for I2C5
529 UINT16 PchSerialIoTimingM1C5; // [M1C5] M1D3 for I2C5
530 UINT16 PchSerialIoTimingM0C6; // [M0C6] M0D3 for SPI0
531 UINT16 PchSerialIoTimingM1C6; // [M1C6] M1D3 for SPI0
532 UINT16 PchSerialIoTimingM0C7; // [M0C7] M0D3 for SPI1
533 UINT16 PchSerialIoTimingM1C7; // [M1C7] M1D3 for SPI1
534 UINT16 PchSerialIoTimingM0C8; // [M0C8] M0D3 for SPI2
535 UINT16 PchSerialIoTimingM1C8; // [M1C8] M1D3 for SPI2
536 UINT16 PchSerialIoTimingM0C9; // [M0C9] M0D3 for UART0
537 UINT16 PchSerialIoTimingM1C9; // [M1C9] M1D3 for UART0
538 UINT16 PchSerialIoTimingM0CA; // [M0CA] M0D3 for UART1
539 UINT16 PchSerialIoTimingM1CA; // [M1CA] M1D3 for UART1
540 UINT16 PchSerialIoTimingM0CB; // [M0CB] M0D3 for UART2
541 UINT16 PchSerialIoTimingM1CB; // [M1CB] M1D3 for UART2
542
543 UINT8 Ps2KbMsEnable;
544 UINT8 TouchPanelMuxSelector;
545
546 UINT8 Ac1TripPoint;
547 UINT8 Ac0TripPoint;
548 UINT8 Ac1FanSpeed;
549 UINT8 Ac0FanSpeed;
550 UINT8 PassiveThermalTripPoint;
551 UINT8 CriticalThermalTripPoint;
552 UINT8 PassiveTc1Value;
553 UINT8 PassiveTc2Value;
554 UINT8 PassiveTspValue;
555 UINT8 DisableActiveTripPoints;
556 UINT8 DisablePassiveTripPoints;
557 UINT8 DisableCriticalTripPoints;
558 UINT8 PmicVccLevel;
559 UINT8 PmicVddqLevel;
560 UINT8 TwoComponents;
561
562 UINT8 CPUTempReadEnable;
563 UINT8 CPUEnergyReadEnable;
564 UINT8 PCHTempReadEnable;
565 UINT8 AlertEnableLock;
566 UINT8 PchAlert;
567 UINT8 DimmAlert;
568 UINT8 CpuTemp;
569 UINT8 CpuFanSpeed;
570
571 //
572 // DPTF SETUP items begin
573 //
574 UINT8 EnableDptf;
575 UINT8 EnableDCFG;
576
577 UINT8 EnableSaDevice;
578 UINT8 ActiveThermalTripPointSA;
579 UINT8 PassiveThermalTripPointSA;
580 UINT8 CriticalThermalTripPointSA;
581 UINT8 CriticalThermalTripPointSaS3;
582 UINT8 ThermalSamplingPeriodSA;
583 UINT8 HotThermalTripPointSA;
584 UINT32 PpccStepSize;
585 UINT8 LPOEnable;
586 UINT8 LPOStartPState;
587 UINT8 LPOStepSize;
588 UINT8 LPOPowerControlSetting;
589 UINT8 LPOPerformanceControlSetting;
590 UINT16 MinPowerLimit0;
591 UINT16 MinPowerLimit1;
592 UINT16 MinPowerLimit2;
593 UINT8 EnableCtdpPolicy;
594
595 UINT8 EnableFan1Device;
596
597 UINT8 EnableDisplayParticipant;
598 UINT8 DisplayDepthUpperLimit;
599 UINT8 DisplayDepthLowerLimit;
600
601 UINT8 EnableWrlsParticipant;
602 UINT8 ActiveThermalTripPointWrls;
603 UINT8 PassiveThermalTripPointWrls;
604 UINT8 CriticalThermalTripPointWrls;
605 UINT8 CriticalThermalTripPointWrlsS3;
606 UINT8 HotThermalTripPointWrls;
607 UINT8 ThermalSamplingPeriodWrls;
608
609 UINT8 EnableWWANParticipant;
610 UINT8 ActiveThermalTripPointWWAN;
611 UINT8 PassiveThermalTripPointWWAN;
612 UINT8 CriticalThermalTripPointWWAN;
613 UINT8 CriticalThermalTripPointWwanS3;
614 UINT8 HotThermalTripPointWWAN;
615
616 UINT8 EnableChargerParticipant;
617 UINT8 EnablePowerParticipant;
618 UINT16 PowerParticipantPollingRate;
619 UINT8 EnablePowerBossPolicy;
620
621 UINT8 Enable2DCameraParticipant;
622
623 UINT8 EnableStorageParticipantST1;
624 UINT8 ActiveThermalTripPointST1;
625 UINT8 PassiveThermalTripPointST1;
626 UINT8 CriticalThermalTripPointST1;
627 UINT8 CriticalThermalTripPointS3ST1;
628 UINT8 HotThermalTripPointST1;
629
630 UINT8 EnableStorageParticipantST2;
631 UINT8 ActiveThermalTripPointST2;
632 UINT8 PassiveThermalTripPointST2;
633 UINT8 CriticalThermalTripPointST2;
634 UINT8 CriticalThermalTripPointS3ST2;
635 UINT8 HotThermalTripPointST2;
636
637 UINT8 EnableVS1Participant;
638 UINT8 ActiveThermalTripPointVS1;
639 UINT8 PassiveThermalTripPointVS1;
640 UINT8 CriticalThermalTripPointVS1;
641 UINT8 CriticalThermalTripPointVS1S3;
642 UINT8 HotThermalTripPointVS1;
643
644 UINT8 EnableVS2Participant;
645 UINT8 ActiveThermalTripPointVS2;
646 UINT8 PassiveThermalTripPointVS2;
647 UINT8 CriticalThermalTripPointVS2;
648 UINT8 CriticalThermalTripPointVS2S3;
649 UINT8 HotThermalTripPointVS2;
650
651 UINT8 EnableSen1ParticipantSupport;
652 UINT8 EnableSen1Participant;
653 UINT8 ActiveThermalTripPointSen1;
654 UINT8 PassiveThermalTripPointSen1;
655 UINT8 CriticalThermalTripPointSen1;
656 UINT8 CriticalThermalTripPointSen1S3;
657 UINT8 HotThermalTripPointSen1;
658 UINT8 SensorSamplingPeriodSen1;
659
660 UINT8 EnableSen2Participant;
661 UINT8 ActiveThermalTripPointSen2;
662 UINT8 PassiveThermalTripPointSen2;
663 UINT8 CriticalThermalTripPointSen2;
664 UINT8 CriticalThermalTripPointSen2S3;
665 UINT8 HotThermalTripPointSen2;
666 UINT8 SensorSamplingPeriodSen2;
667
668 UINT8 EnableSen3Participant;
669 UINT8 ActiveThermalTripPointSen3;
670 UINT8 PassiveThermalTripPointSen3;
671 UINT8 CriticalThermalTripPointSen3;
672 UINT8 CriticalThermalTripPointSen3S3;
673 UINT8 HotThermalTripPointSen3;
674 UINT8 SensorSamplingPeriodSen3;
675
676 UINT8 EnableSen4Participant;
677 UINT8 ActiveThermalTripPointSen4;
678 UINT8 PassiveThermalTripPointSen4;
679 UINT8 CriticalThermalTripPointSen4;
680 UINT8 CriticalThermalTripPointSen4S3;
681 UINT8 HotThermalTripPointSen4;
682 UINT8 SensorSamplingPeriodSen4;
683
684 UINT8 EnableSen5Participant;
685 UINT8 ActiveThermalTripPointSen5;
686 UINT8 PassiveThermalTripPointSen5;
687 UINT8 CriticalThermalTripPointSen5;
688 UINT8 CriticalThermalTripPointSen5S3;
689 UINT8 HotThermalTripPointSen5;
690 UINT8 SensorSamplingPeriodSen5;
691
692 #ifdef PCH_ICL
693 UINT8 EnablePchFivrParticipant;
694 #endif
695
696 UINT8 EnableActivePolicy;
697 UINT8 EnablePassivePolicy;
698 UINT8 TrtRevision;
699 UINT8 EnableCriticalPolicy;
700 UINT8 EnableRFIMPolicy;
701 UINT8 EnableAPPolicy;
702 UINT8 EnableVSPolicy;
703 UINT8 EnablePIDPolicy;
704
705 UINT8 PpccObject;
706 UINT8 PdrtObject;
707 UINT8 ArtgObject;
708 UINT8 PmaxObject;
709 UINT8 Tmp1Object;
710 UINT8 Tmp2Object;
711 UINT8 Tmp3Object;
712 UINT8 Tmp4Object;
713 UINT8 Tmp5Object;
714 UINT8 Tmp6Object;
715 UINT8 Tmp7Object;
716 UINT8 Tmp8Object;
717 UINT8 OptionalObjects;
718
719 UINT8 OemDesignVariable0;
720 UINT8 OemDesignVariable1;
721 UINT8 OemDesignVariable2;
722 UINT8 OemDesignVariable3;
723 UINT8 OemDesignVariable4;
724 UINT8 OemDesignVariable5;
725
726 //
727 // DPTF SETUP items end
728 //
729 UINT8 Rtd3Support;
730 UINT8 Rtd3P0dl;
731 UINT8 Rtd3UsbPt1;
732 UINT8 Rtd3UsbPt2;
733 UINT16 Rtd3AudioDelay;
734 UINT16 Rtd3TouchPadDelay;
735 UINT16 Rtd3TouchPanelDelay;
736 UINT16 Rtd3SensorHub;
737 UINT16 VRRampUpDelay;
738 UINT8 PstateCapping;
739 UINT8 Rtd3ZpoddSupport;
740 UINT8 Rtd3Zpodd;
741 UINT8 Rtd3WWAN;
742 UINT8 Rtd3SataPort0;
743 UINT8 Rtd3SataPort1;
744 UINT8 Rtd3SataPort2;
745 UINT8 Rtd3SataPort3;
746 UINT8 Rtd3SataPort4;
747 UINT8 Rtd3SataPort5;
748 UINT8 Rtd3WaGpio;
749 UINT8 Rtd3RemapCR1;
750 UINT8 Rtd3RemapCR2;
751 UINT8 Rtd3RemapCR3;
752 UINT8 Rtd3I2CTouchPanel;
753
754 UINT8 PowerSharingManagerEnable;
755 UINT8 PsmSplcDomainType1;
756 UINT32 PsmSplcPowerLimit1;
757 UINT32 PsmSplcTimeWindow1;
758 UINT8 PsmSplcDomainType2;
759 UINT32 PsmSplcPowerLimit2;
760 UINT32 PsmSplcTimeWindow2;
761
762 UINT8 PsmDplcDomainType1;
763 UINT8 PsmDplcDomainPreference1;
764 UINT16 PsmDplcPowerLimitIndex1;
765 UINT16 PsmDplcDefaultPowerLimit1;
766 UINT32 PsmDplcDefaultTimeWindow1;
767 UINT16 PsmDplcMinimumPowerLimit1;
768 UINT16 PsmDplcMaximumPowerLimit1;
769 UINT16 PsmDplcMaximumTimeWindow1;
770
771 UINT8 PsmDplcDomainType2;
772 UINT8 PsmDplcDomainPreference2;
773 UINT16 PsmDplcPowerLimitIndex2;
774 UINT16 PsmDplcDefaultPowerLimit2;
775 UINT32 PsmDplcDefaultTimeWindow2;
776 UINT16 PsmDplcMinimumPowerLimit2;
777 UINT16 PsmDplcMaximumPowerLimit2;
778 UINT16 PsmDplcMaximumTimeWindow2;
779
780 UINT8 WifiEnable;
781 UINT8 WifiDomainType1;
782 UINT16 WifiPowerLimit1;
783 UINT32 WifiTimeWindow1;
784 UINT8 WifiDomainType2;
785 UINT16 WifiPowerLimit2;
786 UINT32 WifiTimeWindow2;
787 UINT8 WifiDomainType3;
788 UINT16 WifiPowerLimit3;
789 UINT32 WifiTimeWindow3;
790 UINT8 TRxDelay0;
791 UINT8 TRxCableLength0;
792 UINT8 TRxDelay1;
793 UINT8 TRxCableLength1;
794 UINT8 WrddDomainType1;
795 UINT16 WrddCountryIndentifier1;
796 UINT8 WrddDomainType2;
797 UINT16 WrddCountryIndentifier2;
798 UINT8 WrdsWiFiSarEnable;
799 UINT8 WrdsWiFiSarTxPowerSet1Limit1;
800 UINT8 WrdsWiFiSarTxPowerSet1Limit2;
801 UINT8 WrdsWiFiSarTxPowerSet1Limit3;
802 UINT8 WrdsWiFiSarTxPowerSet1Limit4;
803 UINT8 WrdsWiFiSarTxPowerSet1Limit5;
804 UINT8 WrdsWiFiSarTxPowerSet1Limit6;
805 UINT8 WrdsWiFiSarTxPowerSet1Limit7;
806 UINT8 WrdsWiFiSarTxPowerSet1Limit8;
807 UINT8 WrdsWiFiSarTxPowerSet1Limit9;
808 UINT8 WrdsWiFiSarTxPowerSet1Limit10;
809 UINT8 WigigRfe;
810 UINT8 WiGigRfeCh1;
811 UINT8 WiGigRfeCh2;
812 UINT8 WiGigRfeCh3;
813 UINT8 WiGigRfeCh4;
814 UINT32 AwvClassIndex;
815 UINT8 BluetoothSar;
816 UINT8 BluetoothSarBr;
817 UINT8 BluetoothSarEdr2;
818 UINT8 BluetoothSarEdr3;
819 UINT8 BluetoothSarLe;
820 UINT8 CoExistenceManager;
821 UINT8 WwanWorkaround;
822 UINT8 UsbFnEnable;
823
824 UINT8 CsmControl;
825
826 UINT8 FanControl;
827 UINT8 CpuFanControl;
828 UINT8 LowestFanSpeed;
829
830 //
831 // Thunderbolt(TM)
832 //
833 UINT8 TbtSetupFormSupport;
834 UINT8 DiscreteTbtSupport;
835 UINT8 IntegratedTbtSupport;
836 UINT8 TbtPcieSupport;
837 UINT8 TbtUsbOn;
838 UINT8 TbtBootOn;
839 UINT8 TbtWakeupSupport;
840 UINT8 Gpio3ForcePwr;
841 UINT16 Gpio3ForcePwrDly;
842 UINT8 SecurityMode;
843 UINT8 CallSmiBeforeBoot;
844 UINT8 TBTHotSMI;
845 UINT8 Gpio5Filter;
846 UINT8 TBTHotNotify;
847 UINT8 EnableMsiInFadt;
848 UINT8 DTbtController[DTBT_CONTROLLER_SUPPORTED];
849 UINT8 TBTSetClkReq;
850 UINT8 TbtAspm;
851 UINT8 TbtLtr;
852 UINT8 DTbthostRouterPortNumber[DTBT_CONTROLLER_SUPPORTED];
853 UINT8 DTbtPcieExtraBusRsvd[DTBT_CONTROLLER_SUPPORTED];
854 UINT16 DTbtPcieMemRsvd[DTBT_CONTROLLER_SUPPORTED];
855 UINT8 DTbtPcieIoRsvd[DTBT_CONTROLLER_SUPPORTED];
856 UINT8 DTbtPcieMemAddrRngMax[DTBT_CONTROLLER_SUPPORTED];
857 UINT16 DTbtPciePMemRsvd[DTBT_CONTROLLER_SUPPORTED];
858 UINT8 DTbtPciePMemAddrRngMax[DTBT_CONTROLLER_SUPPORTED];
859 UINT8 Win10Support;
860 UINT8 TrOsup;
861 UINT8 TbtL1SubStates;
862 UINT16 Go2SxTimeout;
863 // ITBT Specific Setup Options
864 UINT8 ITbtRootPort[ITBT_ROOT_PORTS_SUPPORTED];
865 UINT8 ITbtPcieExtraBusRsvd[ITBT_ROOT_PORTS_SUPPORTED];
866 UINT16 ITbtPcieMemRsvd[ITBT_ROOT_PORTS_SUPPORTED];
867 UINT8 ITbtPcieMemAddrRngMax[ITBT_ROOT_PORTS_SUPPORTED];
868 UINT16 ITbtPciePMemRsvd[ITBT_ROOT_PORTS_SUPPORTED];
869 UINT8 ITbtPciePMemAddrRngMax[ITBT_ROOT_PORTS_SUPPORTED];
870 UINT16 ITbtForcePowerOnTimeout;
871 UINT16 ITbtConnectTopologyTimeout;
872 UINT32 ITbtDmaUuid[ITBT_HOST_DMA_SUPPORTED];
873 UINT16 ReserveMemoryPerSlot;
874 UINT16 ReservePMemoryPerSlot;
875 UINT8 ReserveIoPerSlot;
876 UINT8 TbtSkipPciOprom;
877 UINT8 TbtAcpiRemovalSupport;
878
879 UINT8 IccWdtEnabled;
880 UINT8 IccLockRegisters;
881 UINT8 IccProfile;
882 UINT8 ShowProfile;
883 UINT8 NumProfiles;
884 UINT8 IccPllShutdownEnabled;
885
886 UINT8 CsModeFirst;
887 UINT8 CsMode;
888 UINT8 CsModeChanged;
889
890 UINT8 PlatformUnstable;
891 UINT8 IsOcDefaultsInitalized;
892
893 UINT8 SecureEraseModeRealMode;
894 UINT8 ForceSecureErase;
895
896 UINT8 HidEventFilterDriverEnable;
897
898
899 UINT8 PmicSlpS0VmSupport;
900 UINT8 HebcValueSupport;
901 UINT32 HebcValue;
902
903 UINT8 I2cSarResetDelay;
904
905 UINT8 WWANEnable;
906
907 UINT8 UsbTypecBssbMode;
908
909 #ifdef CPU_ICL
910 UINT8 UsbcBiosTcssHandshake;
911 // EC - BIOS handshake timeouts
912 UINT32 UsbConnStatusTimeout;
913 UINT32 UsbcSxEntryTimeout;
914 UINT32 UsbcSxExitTimeout;
915 #endif // CPU_ICL
916
917 UINT8 PepWiGigF1;
918
919 UINT8 VtioSupport;
920 UINT8 SdevCio2Entry;
921 UINT8 SdevIspEntry;
922 UINT8 SdevXhciEntry;
923 UINT8 SdevHeciEntry;
924 UINT8 SdevSpi1Entry;
925 UINT8 SdevSpi2Entry;
926 UINT8 EcChargingMethod;
927 UINT8 AlternateModeSynchDelay;
928 UINT8 WakeOnWiGigSupport;
929
930 UINT8 TestUsbUnlockForNoa;
931
932 UINT8 EnableCrashLog;
933 UINT8 CrashLogOnAllReset;
934
935 UINT8 SysFwUpdateLoadDefault;
936 UINT8 SysFwUpdateGetUserConsent;
937
938 UINT8 BoardReworkComplainceEnable;
939 UINT8 ItpxdpMuxSupport;
940 UINT8 ItpxdpMux;
941
942 UINT8 SerialPortAcpiDebug;
943
944 } SETUP_DATA;
945
946 /**
947 Making any setup structure change after code frozen
948 will need to maintain backward compatibility, bump up
949 structure revision and update below history table\n
950 <b>Revision 1</b>: - Initial version.
951 **/
952
953 #define CPU_SETUP_REVISION 1
954
955 typedef struct {
956 UINT8 Revision;
957 UINT8 CpuRatio;
958 UINT8 CpuDefaultRatio;
959 UINT8 CpuRatioOverride;
960 UINT8 Peci;
961 UINT8 HyperThreading;
962 UINT8 ActiveCoreCount;
963 UINT8 BistOnReset;
964 UINT8 JtagC10PowerGateDisable;
965 UINT8 EnableGv;
966 UINT8 RaceToHalt;
967 UINT8 EnableHwp;
968 UINT8 EnableItbm;
969 UINT8 EnableItbmDriver;
970
971 UINT8 EnablePerCorePState;
972 UINT8 EnableHwpAutoPerCorePstate;
973 UINT8 EnableHwpAutoEppGrouping;
974 UINT8 EnableEpbPeciOverride;
975 UINT8 EnableFastMsrHwpReq;
976
977 UINT8 BootFrequency;
978 UINT8 EnableCx;
979 UINT8 EnableC1e;
980 UINT8 TurboMode;
981 UINT32 PowerLimit1;
982 UINT8 LongDurationPwrLimitOverride;
983 UINT8 PowerLimit1Time;
984 UINT8 PowerLimit2;
985 UINT32 PowerLimit2Power;
986 UINT8 PowerLimit3Override;
987 UINT32 PowerLimit3;
988 UINT8 PowerLimit3Time;
989 UINT8 PowerLimit3DutyCycle;
990 UINT8 PowerLimit3Lock;
991 UINT8 PowerLimit4Override;
992 UINT32 PowerLimit4;
993 UINT8 PowerLimit4Lock;
994 UINT8 TurboPowerLimitLock;
995 UINT8 PlatformPowerLimit1Enable;
996 UINT32 PlatformPowerLimit1Power;
997 UINT8 PlatformPowerLimit1Time;
998 UINT8 PlatformPowerLimit2Enable;
999 UINT32 PlatformPowerLimit2Power;
1000 UINT8 EnergyEfficientPState;
1001 UINT8 CStatePreWake;
1002 UINT8 CStateAutoDemotion;
1003 UINT8 CStateUnDemotion;
1004 UINT8 PkgCStateDemotion;
1005 UINT8 PkgCStateUnDemotion;
1006 UINT8 EnableThermalMonitor;
1007 UINT8 PmgCstCfgCtrlLock;
1008 UINT8 ConfigTdpLevel;
1009 UINT8 ConfigTdpLock;
1010 UINT8 ConfigTdpBios;
1011 UINT8 TimedMwait;
1012 UINT8 PmgCstCfgCtrIoMwaitRedirection;
1013 UINT8 InterruptRedirectMode;
1014
1015 UINT8 HdcControl;
1016 UINT8 PkgCStateLimit;
1017 UINT8 CstateLatencyControl1TimeUnit;
1018 UINT8 CstateLatencyControl2TimeUnit;
1019 UINT8 CstateLatencyControl3TimeUnit;
1020 UINT8 CstateLatencyControl4TimeUnit;
1021 UINT8 CstateLatencyControl5TimeUnit;
1022 UINT16 CstateLatencyControl1Irtl;
1023 UINT16 CstateLatencyControl2Irtl;
1024 UINT16 CstateLatencyControl3Irtl;
1025 UINT16 CstateLatencyControl4Irtl;
1026 UINT16 CstateLatencyControl5Irtl;
1027
1028 UINT32 Custom1PowerLimit1Power;
1029 UINT32 Custom1PowerLimit2Power;
1030 UINT8 Custom1PowerLimit1Time;
1031 UINT8 Custom1TurboActivationRatio;
1032 UINT32 Custom2PowerLimit1Power;
1033 UINT32 Custom2PowerLimit2Power;
1034 UINT8 Custom2PowerLimit1Time;
1035 UINT8 Custom2TurboActivationRatio;
1036 UINT32 Custom3PowerLimit1Power;
1037 UINT32 Custom3PowerLimit2Power;
1038 UINT8 Custom3PowerLimit1Time;
1039 UINT8 Custom3TurboActivationRatio;
1040 UINT8 TStatesEnable;
1041 UINT8 EnableProcHot;
1042 UINT8 DisableProcHotOut;
1043 UINT8 DisableVrThermalAlert;
1044 UINT8 ProcHotLock;
1045 UINT8 ProcHotResponse;
1046 UINT8 TCCActivationOffset;
1047 UINT8 NumOfCustomPStates;
1048 UINT8 StateRatio[MAX_CUSTOM_P_STATES];
1049 UINT8 StateRatioMax16[MAX_16_CUSTOM_P_STATES];
1050 UINT8 VT;
1051 UINT8 AES;
1052 UINT8 MachineCheck;
1053 UINT8 MonitorMwait;
1054 UINT16 DprSize;
1055 UINT8 HwPrefetcher;
1056 UINT8 AclPrefetch;
1057 UINT8 Txt;
1058 UINT8 LtDprProgramming;
1059 UINT8 ResetAux;
1060 UINT8 AcheckRequest;
1061 UINT8 MsegOpt;
1062 UINT8 MsegSize;
1063
1064 UINT8 EcTurboControlMode;
1065 UINT8 AcBrickCapacity;
1066 UINT8 EcPollingPeriod;
1067 UINT8 EcGuardBandValue;
1068 UINT8 EcAlgorithmSel;
1069
1070 UINT8 IsTurboRatioDefaultsInitalized;
1071 UINT8 FlexRatioOverrideDefault;
1072 UINT8 RatioLimit1Default;
1073 UINT8 RatioLimit2Default;
1074 UINT8 RatioLimit3Default;
1075 UINT8 RatioLimit4Default;
1076 UINT8 RatioLimit5Default;
1077 UINT8 RatioLimit6Default;
1078 UINT8 RatioLimit7Default;
1079 UINT8 RatioLimit8Default;
1080 UINT8 RatioLimit1;
1081 UINT8 RatioLimit2;
1082 UINT8 RatioLimit3;
1083 UINT8 RatioLimit4;
1084 UINT8 RatioLimit5;
1085 UINT8 RatioLimit6;
1086 UINT8 RatioLimit7;
1087 UINT8 RatioLimit8;
1088 UINT8 OverclockingLockDefault;
1089 UINT8 OverclockingLock;
1090
1091 UINT8 BiosGuard;
1092 UINT8 BiosGuardToolsInterface;
1093
1094 UINT8 DebugInterfaceEnable;
1095 UINT8 DebugInterfaceLockEnable;
1096 UINT8 DebugCpuDisabled;
1097
1098 UINT8 EnableC6Dram;
1099 UINT8 EnableSgx;
1100 UINT8 EpochUpdate;
1101 UINT8 ShowEpoch;
1102 UINT32 MaxPrmrrSize;
1103 UINT32 PrmrrSize;
1104 UINT64 SgxEpoch0;
1105 UINT64 SgxEpoch1;
1106 UINT8 ApIdleManner;
1107
1108 UINT8 ProcessorTraceOutputScheme;
1109 UINT8 ProcessorTraceMemSize;
1110 UINT8 ProcessorTraceEnable;
1111
1112 UINT8 SkipStopPbet;
1113 UINT8 ThreeStrikeCounterDisable;
1114 UINT8 EpocFclkFreq;
1115
1116 //
1117 // SA = 0, IA = 1, Ring = 2, GT = 3, FIVR = 4
1118 //
1119 UINT8 PsysSlope;
1120 UINT8 PsysOffset;
1121 UINT16 PsysPmax;
1122 UINT8 VrConfigEnable[5];
1123 UINT16 AcLoadline[5];
1124 UINT16 DcLoadline[5];
1125 UINT16 Psi1Threshold[5];
1126 UINT16 Psi2Threshold[5];
1127 UINT16 Psi3Threshold[5];
1128 UINT8 Psi3Enable[5];
1129 UINT8 Psi4Enable[5];
1130 UINT8 ImonSlope[5];
1131 UINT16 ImonOffset[5];
1132 UINT8 ImonOffsetPrefix[5];
1133 UINT16 IccMax[5];
1134 UINT16 VrVoltageLimit[5];
1135 UINT16 TdcPowerLimit[5];
1136 UINT8 TdcEnable[5];
1137 UINT8 TdcTimeWindow[5];
1138 UINT8 TdcLock[5];
1139
1140 UINT32 TccOffsetTimeWindow;
1141 UINT8 TccOffsetClamp;
1142 UINT8 TccOffsetLock;
1143
1144 //
1145 // CPU related
1146 //
1147 UINT8 FlexOverrideEnable;
1148 UINT8 MaxEfficiencyRatio;
1149 UINT8 MaxNonTurboRatio;
1150 UINT8 FlexRatioOverride;
1151 UINT8 EnableGvDefault;
1152 UINT8 TurboModeDefault;
1153 UINT8 PowerLimit1TimeDefault;
1154 UINT32 PowerLimit1Default;
1155 UINT32 PowerLimit2Default;
1156 UINT16 XeTdcLimit;
1157 UINT16 XeTdcLimitDefault;
1158 UINT16 XeTdpLimitDefault;
1159 UINT16 XeTdcLimitHangBootValue;
1160 UINT16 XeTdpLimitHangBootValue;
1161 UINT8 XeRatioLimit1HangBootValue;
1162 UINT8 XeRatioLimit2HangBootValue;
1163 UINT8 XeRatioLimit3HangBootValue;
1164 UINT8 XeRatioLimit4HangBootValue;
1165
1166 UINT8 BusSpeedEnable;
1167 UINT8 ProcessorBusSpeedOverride;
1168 UINT8 ProcessorBusSpeedOverrideDefault;
1169
1170 UINT8 PciePll;
1171 UINT8 EnergyEfficientTurbo;
1172 //
1173 // Saving MCFrequency to be used in PEI phase during Overclocking
1174 //
1175 UINT16 PrevBootMcFrequency;
1176
1177 UINT8 WDTSupportforNextOSBoot;
1178 UINT16 TimeforNextOSBoot;
1179 UINT8 Ck505Present;
1180
1181 UINT8 EnableDigitalThermalSensor;
1182
1183 //
1184 // OverClocking setup options
1185 //
1186 UINT8 OverclockingSupport;
1187 UINT8 XtuInterfaceEnable;
1188
1189 UINT8 CoreMaxOcRatio;
1190 UINT8 CoreVoltageMode;
1191 UINT16 CoreVoltageOverride;
1192 UINT16 CoreVoltageOffset;
1193 UINT8 CoreVoltageOffsetPrefix;
1194 UINT16 CoreExtraTurboVoltage;
1195 UINT8 Avx2RatioOffset;
1196 UINT8 Avx3RatioOffset;
1197 UINT8 RingMaxOcRatio;
1198 UINT8 RingDownBin;
1199 UINT8 RingVoltageMode;
1200 UINT16 RingVoltageOverride;
1201 UINT16 RingVoltageOffset;
1202 UINT8 RingVoltageOffsetPrefix;
1203 UINT16 RingExtraTurboVoltage;
1204
1205 //
1206 // OverClocking Default setup options
1207 //
1208 UINT8 CoreMaxOcRatioDefault;
1209 UINT8 CoreVoltageModeDefault;
1210 UINT16 CoreVoltageOverrideDefault;
1211 UINT16 CoreVoltageOffsetDefault;
1212 UINT8 CoreVoltageOffsetPrefixDefault;
1213 UINT16 CoreExtraTurboVoltageDefault;
1214 UINT8 Avx2RatioOffsetDefault;
1215 UINT8 Avx3RatioOffsetDefault;
1216 UINT8 RingMaxOcRatioDefault;
1217 UINT8 VoltageOptimization;
1218
1219 UINT8 RingMinOcRatio;
1220 UINT8 RingMinOcRatioDefault;
1221 UINT8 RingVoltageModeDefault;
1222 UINT16 RingVoltageOverrideDefault;
1223 UINT16 RingVoltageOffsetDefault;
1224 UINT8 RingVoltageOffsetPrefixDefault;
1225 UINT16 RingExtraTurboVoltageDefault;
1226 UINT8 AutoThermalReporting;
1227 UINT8 CorePllVoltageOffset;
1228 UINT8 GtPllVoltageOffset;
1229 UINT8 RingPllVoltageOffset;
1230 UINT8 SaPllVoltageOffset;
1231 UINT8 McPllVoltageOffset;
1232 UINT8 TjMaxOffset;
1233
1234 //
1235 // RFI Setup Options
1236 //
1237 UINT16 McivrRfiFrequencyAdjust;
1238 UINT8 McivrRfiFrequencyPrefix;
1239 UINT8 McivrSpreadSpectrum;
1240 UINT16 FivrRfiFrequency;
1241 UINT8 FivrSpreadSpectrum;
1242
1243 //
1244 // Acoustic Noise Mitigation
1245 //
1246 UINT8 AcousticNoiseMitigation;
1247 UINT8 FastPkgCRampDisableIa;
1248 UINT8 FastPkgCRampDisableGt;
1249 UINT8 FastPkgCRampDisableSa;
1250 UINT8 FastPkgCRampDisableFivr;
1251 UINT8 SlowSlewRateForIa;
1252 UINT8 SlowSlewRateForGt;
1253 UINT8 SlowSlewRateForSa;
1254 UINT8 SlowSlewRateForFivr;
1255
1256 UINT8 HwpInterruptControl;
1257 UINT16 IccMaxDefault[5];
1258
1259 #ifndef CPU_CFL
1260 UINT8 FivrFaults;
1261 UINT8 FivrEfficiency;
1262 #endif
1263
1264 } CPU_SETUP;
1265
1266 typedef struct {
1267 UINT16 CpuFamilyModel;
1268 UINT16 CpuExtendedFamilyModel;
1269 UINT8 CpuStepping;
1270 UINT8 EdramSupported;
1271
1272 //
1273 // Vr Topology
1274 //
1275 UINT8 CoreVrLocked;
1276 UINT8 SaVrLocked;
1277 UINT8 GtVrLocked;
1278 UINT8 FivrVrLocked;
1279 } CPU_SETUP_VOLATILE_DATA;
1280
1281
1282 typedef struct {
1283 UINT8 DTbtContollersNumber;
1284 UINT8 ITbtRootPortsNumber;
1285 } TBT_SETUP_VOLATILE_DATA;
1286
1287 /**
1288 Making any setup structure change after code frozen
1289 will need to maintain backward compatibility, bump up
1290 structure revision and update below history table\n
1291 <b>Revision 1</b>: - Initial version.
1292 <b>Revision 2</b>: - Add MctpBroadcastCycle
1293 **/
1294
1295 #define ME_SETUP_REVISION 2
1296
1297 typedef struct {
1298 UINT8 Revision;
1299 //
1300 // Intel ME
1301 //
1302 UINT8 MeFirmwareInfo;
1303 UINT8 MeImageType;
1304 UINT8 MeFwDowngrade;
1305 UINT8 CommsHubEnable;
1306
1307 UINT8 HeciTimeouts;
1308 UINT8 DidInitStat;
1309 UINT8 DisableCpuReplacedPolling;
1310 UINT8 SendDidMsg;
1311 UINT8 DisableHeciRetry;
1312 UINT8 DisableMessageCheck;
1313 UINT8 SkipMbpHob;
1314 UINT8 HeciCommunication2;
1315 UINT8 KtDeviceEnable;
1316 UINT8 DisableD0I3SettingForHeci;
1317 UINT8 MctpBroadcastCycle;
1318
1319 UINT8 ChangeEps;
1320 UINT8 UnconfigOnRtcAvailable;
1321 UINT8 MeUnconfigOnRtcClear;
1322 UINT8 CoreBiosDoneEnabled;
1323 UINT8 EndOfPostMessage;
1324 UINT8 Heci3Enabled;
1325 UINT8 MeJhiSupport;
1326
1327 //
1328 // Intel AMT
1329 //
1330 UINT8 Amt;
1331 UINT8 AmtbxHotKeyPressed;
1332 UINT8 AmtbxSelectionScreen;
1333 UINT8 HideUnConfigureMeConfirm;
1334 UINT8 MebxDebugMsg;
1335 UINT8 UnConfigureMe;
1336 UINT8 AmtCiraRequest;
1337 UINT8 AmtCiraTimeout;
1338 UINT8 UsbProvision;
1339 UINT8 FwProgress;
1340
1341 //
1342 // ASF
1343 //
1344 UINT8 Asf;
1345
1346 //
1347 // WatchDog
1348 //
1349 UINT8 WatchDog;
1350 UINT16 WatchDogTimerOs;
1351 UINT16 WatchDogTimerBios;
1352
1353 //
1354 // MEBx resolution settings
1355 //
1356 UINT8 MebxNonUiTextMode;
1357 UINT8 MebxUiTextMode;
1358 UINT8 MebxGraphicsMode;
1359
1360
1361 } ME_SETUP;
1362
1363 /**
1364 Making any setup structure change after code frozen
1365 will need to maintain backward compatibility, bump up
1366 structure revision and update below history table\n
1367 <b>Revision 1</b>: - Initial version.
1368 **/
1369
1370 #define SA_SETUP_REVISION 1
1371
1372 typedef struct {
1373 UINT8 Revision;
1374 UINT8 BdatEnable;
1375
1376 //
1377 // Memory related
1378 //
1379 UINT8 XmpProfileEnable;
1380 UINT16 MemoryVoltage;
1381 UINT16 MemoryVoltageDefault;
1382 UINT8 DllBwEn0;
1383 UINT8 DllBwEn1;
1384 UINT8 DllBwEn2;
1385 UINT8 DllBwEn3;
1386 //
1387 // Memory timing override (these options are used for Custom/User Profile)
1388 //
1389 UINT8 DdrRefClkDefault;
1390 UINT8 DdrRefClk;
1391 UINT8 DdrRatioDefault;
1392 UINT8 DdrRatio;
1393 UINT8 DdrOddRatioMode;
1394 UINT8 tCL;
1395 UINT8 tCWL;
1396 UINT16 tFAW;
1397 UINT16 tRAS;
1398 UINT8 tRCDtRP;
1399 UINT16 tREFI;
1400 UINT16 tRFC;
1401 UINT8 tRRD;
1402 UINT8 tRTP;
1403 UINT8 tWR;
1404 UINT8 tWTR;
1405 UINT8 NModeSupport;
1406 //
1407 // Default values to restore memory timings to in case of Platform instability
1408 //
1409 UINT8 tCLDefault;
1410 UINT8 tCWLDefault;
1411 UINT16 tFAWDefault;
1412 UINT16 tRASDefault;
1413 UINT8 tRCDtRPDefault;
1414 UINT16 tREFIDefault;
1415 UINT16 tRFCDefault;
1416 UINT8 tRRDDefault;
1417 UINT8 tRTPDefault;
1418 UINT8 tWRDefault;
1419 UINT8 tWTRDefault;
1420 UINT8 NModeDefault;
1421
1422 UINT16 GtDid; // not a SETUP item, used by BIOS to pass GT SKU DID to SETUP items
1423 UINT8 IgdBootType;
1424 UINT8 DisplayPipeB;
1425 UINT8 LcdPanelType;
1426
1427 UINT8 LcdPanelScaling;
1428
1429 UINT8 EnableRenderStandby;
1430 UINT8 IgdLcdBlc;
1431 UINT8 AlsEnable;
1432 UINT8 ActiveLFP;
1433 UINT8 LfpColorDepth;
1434 UINT8 GTTSize;
1435 UINT8 ApertureSize;
1436 UINT8 GtPsmiSupport;
1437 UINT8 GtPsmiRegionSize;
1438 UINT8 PanelPowerEnable;
1439 UINT8 PmSupport;
1440 UINT8 PeiGraphicsPeimInit;
1441 UINT8 PavpEnable;
1442 UINT8 VbiosBrightness;
1443 UINT8 CdynmaxClampEnable;
1444 UINT8 CdClock;
1445 UINT8 GtFreqMax;
1446 UINT8 DisableTurboGt;
1447 #ifdef CPU_ICL
1448 #endif
1449 //
1450 // ICC Related
1451 //
1452 UINT8 BclkOverride;
1453 UINT32 BclkFrequency;
1454
1455 //
1456 // PEG
1457 //
1458 UINT8 PegAspm[4];
1459 UINT8 PegAspmL0s[4];
1460 #ifndef CPU_ICL
1461 #endif
1462 UINT8 Peg0Enable;
1463 UINT8 Peg1Enable;
1464 UINT8 Peg2Enable;
1465 UINT8 Peg3Enable;
1466 UINT8 Peg0MaxLinkSpeed;
1467 UINT8 Peg1MaxLinkSpeed;
1468 UINT8 Peg2MaxLinkSpeed;
1469 UINT8 Peg3MaxLinkSpeed;
1470 UINT8 Peg0MaxLinkWidth;
1471 UINT8 Peg1MaxLinkWidth;
1472 UINT8 Peg2MaxLinkWidth;
1473 UINT8 Peg3MaxLinkWidth;
1474 UINT8 Peg0PowerDownUnusedLanes;
1475 UINT8 Peg1PowerDownUnusedLanes;
1476 UINT8 Peg2PowerDownUnusedLanes;
1477 UINT8 Peg3PowerDownUnusedLanes;
1478 UINT8 PegRxCemTestingMode;
1479 UINT8 PegRxCemLoopbackLane;
1480 UINT8 PegRxCemNonProtocolAwareness;
1481 UINT8 PegDisableSpreadSpectrumClocking;
1482 UINT8 Peg0Gen3EqPh3Method;
1483 UINT8 Peg1Gen3EqPh3Method;
1484 UINT8 Peg2Gen3EqPh3Method;
1485 UINT8 Peg3Gen3EqPh3Method;
1486 UINT8 Peg0Gen3EqPh2Enable;
1487 UINT8 Peg1Gen3EqPh2Enable;
1488 UINT8 Peg2Gen3EqPh2Enable;
1489 UINT8 Peg3Gen3EqPh2Enable;
1490 UINT8 PegDeEmphasis[4];
1491 UINT8 PegMaxPayload[4];
1492 UINT8 Peg0LtrEnable;
1493 UINT8 Peg1LtrEnable;
1494 UINT8 Peg2LtrEnable;
1495 UINT8 Peg3LtrEnable;
1496 UINT8 Peg0ObffEnable;
1497 UINT8 Peg1ObffEnable;
1498 UINT8 Peg2ObffEnable;
1499 UINT8 Peg3ObffEnable;
1500
1501 UINT8 PegGen3ProgramStaticEq;
1502 #ifndef CPU_CFL
1503 UINT8 PegGen3RootPortPreset[20];
1504 UINT8 PegGen3EndPointPreset[20];
1505 UINT8 PegGen3EndPointHint[20];
1506 #else
1507 UINT8 PegGen3RootPortPreset[16];
1508 UINT8 PegGen3EndPointPreset[16];
1509 UINT8 PegGen3EndPointHint[16];
1510 #endif // CPU_CFL
1511 UINT8 PegGen3RxCtlePeaking[8];
1512 UINT8 PegGen3RxCtleOverride;
1513 UINT16 Gen3SwEqJitterDwellTime;
1514 UINT8 Gen3SwEqAlwaysAttempt;
1515 UINT8 InitAspmAfterOprom;
1516 UINT8 PegGen3AllowGpioReset;
1517 UINT16 Gen3SwEqJitterErrorTarget;
1518 UINT8 PegGenerateBdatMarginTable;
1519 UINT8 Gen3SwEqEnableVocTest;
1520 UINT16 Gen3SwEqVocDwellTime;
1521 UINT16 Gen3SwEqVocErrorTarget;
1522 UINT8 Gen3SwEqNumberOfPresets;
1523 UINT8 PegRootPortHPE[4];
1524
1525 UINT8 PegSlotPowerLimitScale[4];
1526 UINT8 PegSlotPowerLimitValue[4];
1527 UINT16 PegPhysicalSlotNumber[4];
1528
1529 //
1530 // PEG Hotplug Resources
1531 //
1532 #ifndef CPU_CFL
1533 UINT8 PegExtraBusRsvd[4];
1534 UINT16 PegMemRsvd[4];
1535 UINT8 PegIoRsvd[4];
1536 #else
1537 UINT8 PegExtraBusRsvd[3];
1538 UINT16 PegMemRsvd[3];
1539 UINT8 PegIoRsvd[3];
1540 #endif // CPU_CFL
1541
1542 UINT8 EpgEnable;
1543 UINT16 Idd3n;
1544 UINT16 Idd3p;
1545
1546 //
1547 // DVMT5.0 Graphic memory setting
1548 //
1549 UINT8 IgdDvmt50PreAlloc;
1550 UINT8 IgdDvmt50TotalAlloc;
1551 //
1552 // SA Device Control
1553 //
1554 #ifndef CPU_ICL
1555 UINT8 SaDevice7;
1556 #endif
1557 UINT8 SaDevice4;
1558 UINT8 EnableVtd;
1559 UINT8 EnableAbove4GBMmio;
1560 UINT8 GnaEnable;
1561 UINT8 SaIpuEnable;
1562 UINT8 SaIpuImrConfiguration;
1563 UINT8 EdramTestMode;
1564 UINT8 IedMemEnable;
1565 #ifndef CPU_CFL
1566 UINT8 CpuTraceHubMode;
1567 UINT8 CpuTraceHubMemReg0Size;
1568 UINT8 CpuTraceHubMemReg1Size;
1569 #endif // CPU_CFL
1570 //
1571 // VT-d
1572 //
1573 UINT8 X2ApicOptOut;
1574
1575 //
1576 // DMI
1577 //
1578 UINT8 DmiMaxLinkSpeed;
1579 UINT8 DmiIot;
1580 UINT8 DmiDeEmphasis;
1581 UINT8 DmiGen3EqPh2Enable;
1582 UINT8 DmiGen3EqPh3Method;
1583 UINT8 DmiGen3ProgramStaticEq;
1584 UINT8 DmiGen3RootPortPreset[8];
1585 UINT8 DmiGen3EndPointPreset[8];
1586 UINT8 DmiGen3EndPointHint[8];
1587 UINT8 DmiGen3RxCtlePeaking[4];
1588 // ASPM
1589 UINT8 DmiAspm;
1590 UINT8 DmiExtSync;
1591 // Stop Grant
1592 UINT8 AutoNsg;
1593 UINT8 NumStopGrant;
1594 // Primary Display Select
1595 UINT8 PrimaryDisplay;
1596 UINT8 PcieCardSelect;
1597 UINT16 DelayAfterPwrEn;
1598 UINT16 DelayAfterHoldReset;
1599 UINT8 InternalGraphics;
1600 // Graphics Turbo IMON Current
1601 UINT8 GfxTurboIMON;
1602 #ifdef CPU_ICL
1603 // TCSS
1604 UINT8 PcieMultipleSegmentEnabled;
1605 UINT8 TcssItbtPcie0En;
1606 UINT8 TcssItbtPcie1En;
1607 UINT8 TcssItbtPcie2En;
1608 UINT8 TcssItbtPcie3En;
1609 UINT8 TcssItbtPcie4En;
1610 UINT8 TcssItbtPcie5En;
1611 UINT8 TcssXhciEn;
1612 UINT8 TcssXdciEn;
1613 UINT8 TcssDma0En;
1614 UINT8 TcssDma1En;
1615 UINT8 TcssDma2En;
1616
1617 // VCCST Status
1618 UINT8 TcssVccstStatus;
1619 // USB Override for IOM
1620 UINT8 UsbOverride;
1621 //Enable D3 Cold in TCSS
1622 UINT8 D3ColdEnable;
1623 //Enable D3 hot in TCSS
1624 UINT8 D3HotEnable;
1625 //
1626 //VMD Setup
1627 //
1628 UINT8 VmdEnable;
1629 UINT8 VmdPortA;
1630 UINT8 VmdPortB;
1631 UINT8 VmdPortC;
1632 UINT8 VmdPortD;
1633 UINT8 VmdCfgBarSz;
1634 UINT8 VmdCfgBarAttr;
1635 UINT8 VmdMemBarSz1;
1636 UINT8 VmdMemBar1Attr;
1637 UINT8 VmdMemBarSz2;
1638 UINT8 VmdMemBar2Attr;
1639
1640 #endif //CPU_ICL
1641 //
1642 // MRC settings
1643 //
1644 UINT8 HobBufferSize;
1645 UINT8 EccSupport;
1646 UINT8 MaxTolud;
1647 UINT16 DdrFreqLimit;
1648 UINT8 SpdProfileSelected;
1649 UINT8 MrcTimeMeasure;
1650 UINT8 MrcFastBoot;
1651 UINT8 MrcFastBootA0B0P0;
1652 UINT8 RmtPerTask;
1653 UINT8 TrainTrace;
1654 UINT8 ChHashEnable;
1655 UINT16 ChHashMask;
1656 UINT8 ChHashInterleaveBit;
1657 UINT8 PerBankRefresh;
1658 UINT8 Vc1ReadMeter;
1659 UINT8 StrongWkLeaker;
1660 UINT8 ForceSingleRank;
1661 UINT8 LpddrMemWriteLatencySet;
1662 UINT8 EvLoader;
1663 UINT8 EvLoaderDelay;
1664 UINT8 RetrainOnFastFail;
1665 UINT8 SafeMode;
1666
1667 #ifdef CPU_CFL
1668 UINT8 ProbelessTrace;
1669 UINT8 MemoryTrace;
1670 UINT8 GdxcIotSize;
1671 UINT8 GdxcMotSize;
1672 #endif // CPU_CFL
1673 UINT8 SaGv;
1674 UINT16 FreqSaGvLow;
1675 UINT16 FreqSaGvMid;
1676
1677 //
1678 // MRC Training Algorithms
1679 //
1680 UINT8 ECT;
1681 UINT8 SOT;
1682 UINT8 ERDMPRTC2D;
1683 UINT8 RDMPRT;
1684 UINT8 RCVET;
1685 UINT8 JWRL;
1686 UINT8 EWRTC2D;
1687 UINT8 ERDTC2D;
1688 UINT8 WRTC1D;
1689 UINT8 WRVC1D;
1690 UINT8 RDTC1D;
1691 UINT8 DIMMODTT;
1692 UINT8 DIMMRONT;
1693 UINT8 WRDSEQT;
1694 UINT8 WRSRT;
1695 UINT8 RDODTT;
1696 UINT8 RDEQT;
1697 UINT8 RDAPT;
1698 UINT8 WRTC2D;
1699 UINT8 RDTC2D;
1700 UINT8 CMDVC;
1701 UINT8 WRVC2D;
1702 UINT8 RDVC2D;
1703 UINT8 LCT;
1704 UINT8 RTL;
1705 UINT8 TAT;
1706 UINT8 RMT;
1707 UINT8 MEMTST;
1708 UINT8 ALIASCHK;
1709 UINT8 RCVENC1D;
1710 UINT8 RMC;
1711 UINT8 WRDSUDT;
1712
1713 //
1714 // Power and Thermal Throttling Options
1715 //
1716 UINT8 EnableExtts;
1717 UINT8 EnableCltm;
1718 UINT8 EnableOltm;
1719 UINT8 EnablePwrDn;
1720 UINT8 EnablePwrDnLpddr;
1721 UINT8 Refresh2X;
1722 UINT8 DdrThermalSensor;
1723 UINT8 LockPTMregs;
1724 UINT8 UserPowerWeightsEn;
1725
1726 UINT8 EnergyScaleFact;
1727 UINT8 RaplPwrFlCh1;
1728 UINT8 RaplPwrFlCh0;
1729
1730 UINT8 RaplLim2Lock;
1731 UINT8 RaplLim2WindX;
1732 UINT8 RaplLim2WindY;
1733 UINT8 RaplLim2Ena;
1734 UINT16 RaplLim2Pwr;
1735 UINT8 RaplLim1WindX;
1736 UINT8 RaplLim1WindY;
1737 UINT8 RaplLim1Ena;
1738 UINT16 RaplLim1Pwr;
1739
1740 UINT8 WarmThresholdCh0Dimm0;
1741 UINT8 WarmThresholdCh0Dimm1;
1742 UINT8 WarmThresholdCh1Dimm0;
1743 UINT8 WarmThresholdCh1Dimm1;
1744 UINT8 HotThresholdCh0Dimm0;
1745 UINT8 HotThresholdCh0Dimm1;
1746 UINT8 HotThresholdCh1Dimm0;
1747 UINT8 HotThresholdCh1Dimm1;
1748 UINT8 WarmBudgetCh0Dimm0;
1749 UINT8 WarmBudgetCh0Dimm1;
1750 UINT8 WarmBudgetCh1Dimm0;
1751 UINT8 WarmBudgetCh1Dimm1;
1752 UINT8 HotBudgetCh0Dimm0;
1753 UINT8 HotBudgetCh0Dimm1;
1754 UINT8 HotBudgetCh1Dimm0;
1755 UINT8 HotBudgetCh1Dimm1;
1756
1757 UINT8 IdleEnergyCh0Dimm1;
1758 UINT8 IdleEnergyCh0Dimm0;
1759 UINT8 PdEnergyCh0Dimm1;
1760 UINT8 PdEnergyCh0Dimm0;
1761 UINT8 ActEnergyCh0Dimm1;
1762 UINT8 ActEnergyCh0Dimm0;
1763 UINT8 RdEnergyCh0Dimm1;
1764 UINT8 RdEnergyCh0Dimm0;
1765 UINT8 WrEnergyCh0Dimm1;
1766 UINT8 WrEnergyCh0Dimm0;
1767
1768 UINT8 IdleEnergyCh1Dimm1;
1769 UINT8 IdleEnergyCh1Dimm0;
1770 UINT8 PdEnergyCh1Dimm1;
1771 UINT8 PdEnergyCh1Dimm0;
1772 UINT8 ActEnergyCh1Dimm1;
1773 UINT8 ActEnergyCh1Dimm0;
1774 UINT8 RdEnergyCh1Dimm1;
1775 UINT8 RdEnergyCh1Dimm0;
1776 UINT8 WrEnergyCh1Dimm1;
1777 UINT8 WrEnergyCh1Dimm0;
1778 UINT8 SrefCfgEna;
1779 UINT16 SrefCfgIdleTmr;
1780 UINT8 ThrtCkeMinDefeat;
1781 UINT8 ThrtCkeMinTmr;
1782 UINT8 ThrtCkeMinDefeatLpddr;
1783 UINT8 ThrtCkeMinTmrLpddr;
1784
1785 UINT8 MemoryThermalManagement;
1786 UINT8 PeciInjectedTemp;
1787 UINT8 ExttsViaTsOnBoard;
1788 UINT8 ExttsViaTsOnDimm;
1789 UINT8 VirtualTempSensor;
1790 UINT8 ScramblerSupport;
1791 UINT8 ForceColdReset;
1792 UINT8 DisableDimmChannel0;
1793 UINT8 DisableDimmChannel1;
1794 UINT8 RemapEnable;
1795 UINT8 MrcSafeConfig;
1796 UINT8 RhPrevention;
1797 UINT8 RhSolution;
1798 UINT8 RhActProbability;
1799 UINT8 MaxRttWr;
1800 UINT8 ExitOnFailure;
1801
1802 #ifdef UP_SERVER_FLAG
1803 UINT8 UserThresholdEnable;
1804 UINT8 UserBudgetEnable;
1805 UINT8 TsodTcritMax;
1806 UINT8 TsodEventMode;
1807 UINT8 TsodEventPolarity;
1808 UINT8 TsodCriticalEventOnly;
1809 UINT8 TsodEventOutputControl;
1810 UINT8 TsodAlarmwindowLockBit;
1811 UINT8 TsodCriticaltripLockBit;
1812 UINT8 TsodShutdownMode;
1813 UINT8 TsodThigMax;
1814 UINT8 TsodManualEnable;
1815 #endif
1816 UINT8 SkipExtGfxScan;
1817 //
1818 // CRID
1819 //
1820 UINT8 CridEnable;
1821
1822 UINT8 SlateIndicatorRT;
1823 UINT8 SlateIndicatorSx;
1824 UINT8 DockIndicatorRT;
1825 UINT8 DockIndicatorSx;
1826 UINT8 IuerButtonEnable;
1827 UINT8 IuerConvertibleEnable;
1828 UINT8 IuerDockEnable;
1829
1830 //
1831 // Uncore Related
1832 //
1833 UINT16 UncoreVoltageOffset;
1834 UINT8 UncoreVoltageOffsetPrefix;
1835
1836 UINT16 UncoreVoltageOffsetDefault;
1837 UINT8 UncoreVoltageOffsetPrefixDefault;
1838
1839 //
1840 // GT related
1841 //
1842 UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio override
1843 UINT8 GtVoltageMode; ///< Specifies whether GT voltage is operating in Adaptive or Override mode - 0: Adaptive, 1: Override
1844 UINT16 GtVoltageOffset; ///< The voltage offset applied to GT. Valid range from -1000mv to 1000mv
1845 UINT8 GtVoltageOffsetPrefix;
1846 UINT16 GtVoltageOverride; ///< The GT voltage override which is applied to the entire range of GT frequencies
1847 UINT16 GtExtraTurboVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV
1848 UINT8 GtusMaxOcRatio; ///< Maximum GT turbo ratio override
1849 UINT8 GtusVoltageMode; ///< Specifies whether GT unslice voltage is operating in Adaptive or Override mode - 0: Adaptive, 1: Override
1850 UINT16 GtusVoltageOffset; ///< The voltage offset applied to GT unslice. Valid range from -1000mv to 1000mv
1851 UINT8 GtusVoltageOffsetPrefix;
1852 UINT16 GtusVoltageOverride; ///< The GT unslice voltage override which is applied to the entire range of GT frequencies
1853 UINT16 GtusExtraTurboVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV
1854
1855 UINT8 GtMaxOcRatioDefault; ///< Maximum GT turbo ratio override
1856 UINT8 GtVoltageModeDefault; ///< Specifies whether GT voltage is operating in Adaptive or Override mode - 0: Adaptive, 1: Override
1857 UINT16 GtVoltageOffsetDefault; ///< The voltage offset applied to GT. Valid range from -1000mv to 1000mv
1858 UINT8 GtVoltageOffsetPrefixDefault;
1859 UINT16 GtVoltageOverrideDefault; ///< The GT voltage override which is applied to the entire range of GT frequencies
1860 UINT16 GtExtraTurboVoltageDefault; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV
1861 UINT8 GtusMaxOcRatioDefault; ///< Maximum GT turbo ratio override
1862 UINT8 GtusVoltageModeDefault; ///< Specifies whether GT unslice voltage is operating in Adaptive or Override mode - 0: Adaptive, 1: Override
1863 UINT16 GtusVoltageOffsetDefault; ///< The voltage offset applied to GT unslice. Valid range from -1000mv to 1000mv
1864 UINT8 GtusVoltageOffsetPrefixDefault;
1865 UINT16 GtusVoltageOverrideDefault; ///< The GT unslice voltage override which is applied to the entire range of GT frequencies
1866 UINT16 GtusExtraTurboVoltageDefault; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV
1867
1868 UINT8 RealtimeMemoryTiming; ///< Realtime memory timing will allow system to perform realtime memory timing changes.
1869 UINT8 BclkChangeWarmReset;
1870 UINT8 BclkChangeContinues;
1871 } SA_SETUP;
1872
1873 /**
1874 Making any setup structure change after code frozen
1875 will need to maintain backward compatibility, bump up
1876 structure revision and update below history table\n
1877 <b>Revision 1</b>: - Initial version.
1878 **/
1879
1880 #define PCH_SETUP_REVISION 1
1881
1882 typedef struct {
1883 UINT8 Revision;
1884 UINT8 ExternalDma;
1885 UINT16 RootPortDid; // not a SETUP item, used by BIOS to pass Root Port DID to SETUP items
1886
1887 UINT8 DeepSxMode;
1888 UINT8 LanWakeFromDeepSx;
1889 UINT8 DisableDsxAcPresentPulldown;
1890 UINT8 PmcReadDisable;
1891 UINT8 OsDebugPort;
1892 UINT8 PchLan;
1893 UINT8 DciUsb3TypecUfpDbg;
1894 UINT8 PchEnableDbcObs;
1895 UINT8 PchWakeOnLan;
1896 UINT8 SlpLanLowDc;
1897 UINT8 PchWakeOnWlan;
1898 UINT8 PchWakeOnWlanDeepSx;
1899 #ifndef PCH_ICL
1900 UINT8 PchLpcClockRun;
1901 #endif // PCH_ICL
1902 UINT8 PchEnergyReport;
1903 UINT8 SlpS0Override;
1904 UINT8 SlpS0DisQForDebug;
1905 UINT8 EnableTcoTimer;
1906 UINT8 PchCrid;
1907 UINT8 PchRtcMemoryLock;
1908 UINT8 PchBiosLock;
1909 UINT8 UnlockGpioPads;
1910 UINT8 PsOnEnable;
1911
1912 UINT8 Hpet;
1913 UINT8 StateAfterG3;
1914 UINT8 IchPort80Route;
1915 UINT8 EnhancePort8xhDecoding;
1916 #ifndef PCH_ICL
1917 UINT8 PchSirqMode;
1918 #endif //PCH_ICL
1919 UINT8 PciePllSsc;
1920 UINT8 WdtEnable;
1921 //
1922 // Usb Config
1923 //
1924 UINT8 PchUsb20[2];
1925 UINT8 PchUsbPortDisable;
1926 UINT8 PchUsbHsPort[PCH_MAX_USB2_PORTS];
1927 UINT8 PchUsbSsPort[PCH_MAX_USB3_PORTS];
1928 UINT8 EnableComplianceMode;
1929 UINT8 PchUsbOverCurrentEnable;
1930 UINT8 PchXhciOcLock;
1931 UINT8 PchXhciAcLock;
1932
1933 //
1934 // xDCI Config
1935 //
1936 UINT8 PchXdciSupport;
1937
1938 //
1939 // Sata CONFIG
1940 //
1941 UINT8 PchSata;
1942 UINT8 SataInterfaceMode;
1943 UINT8 SataRstInterrupt;
1944 UINT8 SataPort[PCH_MAX_SATA_PORTS];
1945 UINT8 SataHotPlug[PCH_MAX_SATA_PORTS];
1946 UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS];
1947 UINT8 SataSpinUp[PCH_MAX_SATA_PORTS];
1948 UINT8 SataExternal[PCH_MAX_SATA_PORTS];
1949 UINT8 SataType[PCH_MAX_SATA_PORTS];
1950 UINT8 SataTopology[PCH_MAX_SATA_PORTS];
1951 UINT8 SataRaidR0;
1952 UINT8 SataRaidR1;
1953 UINT8 SataRaidR10;
1954 UINT8 SataRaidR5;
1955 UINT8 SataRaidIrrt;
1956 UINT8 SataRaidOub;
1957 UINT8 SataHddlk;
1958 UINT8 SataLedl;
1959 UINT8 SataRaidIooe;
1960 UINT8 SataRaidSrt;
1961 UINT8 SataRaidOromDelay;
1962 UINT8 SataRstForceForm;
1963 UINT8 SataLegacyOrom;
1964 UINT8 SataRstOptaneMemory;
1965 UINT8 SataRstCpuAttachedStorage;
1966 UINT8 RaidDeviceId;
1967 UINT8 SataSalp;
1968 UINT8 SataTestMode;
1969 UINT8 PxDevSlp[PCH_MAX_SATA_PORTS];
1970 UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS];
1971 UINT16 DitoVal[PCH_MAX_SATA_PORTS];
1972 UINT8 DmVal[PCH_MAX_SATA_PORTS];
1973 UINT8 RstPcieRemapEnabled[PCH_MAX_PCIE_ROOT_PORTS];
1974
1975 //
1976 // PCI_EXPRESS_CONFIG, MAX 20 root ports
1977 //
1978 UINT8 PcieClockGatingDisabled;
1979 UINT8 PcieRootPort8xhDecode;
1980 UINT8 Pcie8xhDecodePortIndex;
1981 UINT8 PcieRootPortPeerMemoryWriteEnable;
1982 UINT8 PcieComplianceTestMode;
1983 UINT8 PcieUsbGlitchWa;
1984 UINT8 PchPcieClockUsageOverride[PCH_MAX_PCIE_CLOCKS];
1985 UINT8 PchPcieClkReqSupport[PCH_MAX_PCIE_CLOCKS];
1986 UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS];
1987 UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS];
1988 UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS];
1989 UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS];
1990 UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS];
1991 UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS];
1992 UINT8 PcieRootPortCTD[PCH_MAX_PCIE_ROOT_PORTS];
1993 UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS];
1994 UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS];
1995 UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS];
1996 UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS];
1997 UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS];
1998 UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS];
1999 UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS];
2000 UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS];
2001 UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS];
2002 UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS];
2003 UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS];
2004 UINT8 PcieRootPortPTM[PCH_MAX_PCIE_ROOT_PORTS];
2005 UINT8 PcieRootPortDPC[PCH_MAX_PCIE_ROOT_PORTS];
2006 UINT8 PcieRootPortEDPC[PCH_MAX_PCIE_ROOT_PORTS];
2007 UINT8 PcieRootPortEqPh3Method[PCH_MAX_PCIE_ROOT_PORTS];
2008 UINT8 PcieRootPortUptp[PCH_MAX_PCIE_ROOT_PORTS];
2009 UINT8 PcieRootPortDptp[PCH_MAX_PCIE_ROOT_PORTS];
2010 UINT8 PcieLaneCm[PCH_MAX_PCIE_ROOT_PORTS];
2011 UINT8 PcieLaneCp[PCH_MAX_PCIE_ROOT_PORTS];
2012 UINT8 PcieTopology[PCH_MAX_PCIE_ROOT_PORTS];
2013 UINT8 PcieRootPortSI[PCH_MAX_PCIE_ROOT_PORTS];
2014 UINT16 PcieDetectTimeoutMs[PCH_MAX_PCIE_ROOT_PORTS];
2015 UINT8 RpFunctionSwap;
2016
2017 UINT8 PcieSwEqOverride;
2018 UINT8 PcieSwEqCoeffCm[5];
2019 UINT8 PcieSwEqCoeffCp[5];
2020 //
2021 // PCIe IMR
2022 //
2023 UINT8 PcieImrEnable;
2024 UINT16 PcieImrSize;
2025 UINT8 ImrRpSelection;
2026 //
2027 // PCIe LTR Configuration
2028 //
2029 UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS];
2030 UINT8 PchPcieLtrConfigLock[PCH_MAX_PCIE_ROOT_PORTS];
2031 UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
2032 UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
2033 UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
2034 UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
2035 UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
2036 UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
2037 UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS];
2038
2039 //
2040 // DMI Configuration
2041 //
2042 UINT8 PchDmiAspm;
2043
2044 //
2045 // PCI Bridge Resources
2046 //
2047 UINT8 PcieExtraBusRsvd[PCH_MAX_PCIE_ROOT_PORTS];
2048 UINT16 PcieMemRsvd[PCH_MAX_PCIE_ROOT_PORTS];
2049 UINT8 PcieIoRsvd[PCH_MAX_PCIE_ROOT_PORTS];
2050
2051 //
2052 // HD-Audio Configuration
2053 //
2054 UINT8 PchHdAudio;
2055 UINT8 PchHdAudioDsp;
2056 UINT8 PchHdAudioDspUaaCompliance;
2057 UINT8 PchHdaIDisplayCodecDisconnect;
2058 UINT8 PchHdAudioPme;
2059 UINT8 PchHdAudioLinkMode;
2060 UINT8 PchHdAudioLinkConfig[HDAUDIO_LINKS_NUMBER];
2061 UINT8 PchHdaHdAudioLinkFreq;
2062 UINT8 PchHdaIDisplayLinkFreq;
2063 UINT8 PchHdaIDisplayLinkTmode;
2064 UINT8 PchHdAudioCodecSxWakeCapability;
2065 UINT8 PchHdAudioSndwBufferRcomp;
2066 UINT8 PchHdAudioCodecSelect;
2067 UINT8 PchHdAudioI2sCodecSelect;
2068 UINT8 PchHdAudioNhltEndpointDmic;
2069 UINT8 PchHdAudioNhltEndpointBluetooth;
2070 UINT8 PchHdAudioNhltEndpointI2s;
2071 UINT8 PchHdAudioFeature[HDAUDIO_FEATURES];
2072 UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES];
2073 CHAR16 PchHdAudioPostProcessingModCustomGuid1[GUID_CHARS_NUMBER];
2074 CHAR16 PchHdAudioPostProcessingModCustomGuid2[GUID_CHARS_NUMBER];
2075 CHAR16 PchHdAudioPostProcessingModCustomGuid3[GUID_CHARS_NUMBER];
2076
2077 //
2078 // Interrupt Configuration
2079 //
2080 UINT8 PchIoApic24119Entries;
2081
2082 //
2083 // PCH Thermal Throttling
2084 //
2085 UINT8 PchCrossThrottling;
2086 //
2087 // SCS Configuration
2088 //
2089 UINT8 PchScsEmmcEnabled;
2090 UINT8 PchScsEmmcHs400Enabled;
2091 UINT8 PchScsEmmcHs400DriverStrength;
2092 UINT8 PchScsSdCardEnabled;
2093 UINT8 PchScsUfsEnabled;
2094
2095 //
2096 // Integrated Sensor Hub (ISH) configuration
2097 //
2098 UINT8 PchIshEnable;
2099 UINT8 PchIshSpiGpioAssign;
2100 UINT8 PchIshUart0GpioAssign;
2101 UINT8 PchIshUart1GpioAssign;
2102 UINT8 PchIshI2c0GpioAssign;
2103 UINT8 PchIshI2c1GpioAssign;
2104 UINT8 PchIshI2c2GpioAssign;
2105 UINT8 PchIshGp0GpioAssign;
2106 UINT8 PchIshGp1GpioAssign;
2107 UINT8 PchIshGp2GpioAssign;
2108 UINT8 PchIshGp3GpioAssign;
2109 UINT8 PchIshGp4GpioAssign;
2110 UINT8 PchIshGp5GpioAssign;
2111 UINT8 PchIshGp6GpioAssign;
2112 UINT8 PchIshGp7GpioAssign;
2113 UINT8 PchIshPdtUnlock;
2114
2115 UINT8 PchSerialIo;
2116 UINT8 PchSerialIoAcpiMode;
2117 UINT8 PchSerialIoDevice[PCH_MAX_SERIALIO_CONTROLLERS];
2118 UINT8 PchSerialIoDeviceI2C4Support;
2119 UINT8 PchGpio;
2120 UINT8 PchGpioIrqRoute;
2121 UINT8 PchAdditionalSerialIoDevices;
2122 UINT16 PchGpioDebounce;
2123 UINT8 PchGpioTestDevices;
2124 UINT8 PchSpiCsPolaritySelect[2];
2125 UINT8 PchUartHwFlowCtrl[3];
2126
2127 //
2128 // TraceHub Setup Options
2129 //
2130 UINT8 PchTraceHubMode;
2131 UINT8 PchTraceHubMemReg0Size;
2132 UINT8 PchTraceHubMemReg1Size;
2133 //
2134 // Thermal Throttling Level options
2135 //
2136 UINT8 PchTtLevelSuggestSet;
2137 UINT16 PchThrmT0Level;
2138 UINT16 PchThrmT1Level;
2139 UINT16 PchThrmT2Level;
2140 UINT8 PchThrmTtEnable;
2141 UINT8 PchThrmTtState13Enable;
2142 UINT8 PchThrmTtLock;
2143
2144 //
2145 // DMI Thermal Throttling
2146 //
2147 UINT8 PchDmiTsSuggestSet;
2148 UINT8 PchTs0Width;
2149 UINT8 PchTs1Width;
2150 UINT8 PchTs2Width;
2151 UINT8 PchTs3Width;
2152 UINT8 PchDmiTsawEn;
2153 //
2154 // SATA Thermal Throttling
2155 //
2156 UINT8 PchSataTsSuggestSet;
2157 UINT8 PchP0T1M;
2158 UINT8 PchP0T2M;
2159 UINT8 PchP0T3M;
2160 UINT8 PchP0TDisp;
2161 UINT8 PchP0Tinact;
2162 UINT8 PchP0TDispFinit;
2163 UINT8 PchP1T1M;
2164 UINT8 PchP1T2M;
2165 UINT8 PchP1T3M;
2166 UINT8 PchP1TDisp;
2167 UINT8 PchP1Tinact;
2168 UINT8 PchP1TDispFinit;
2169 //
2170 // CNVi
2171 //
2172 UINT8 PchCnviMode;
2173 UINT8 PchCnviMfUart1Type;
2174
2175 //
2176 // eSPI Setup Options
2177 //
2178 UINT8 PchEspiLgmrEnable;
2179 #ifdef PCH_ICL
2180 UINT8 PchEspiHostC10ReportEnable;
2181 #endif
2182
2183 //
2184 // SMBUS
2185 //
2186 UINT8 SmbusSpdWriteDisable;
2187 //
2188 // P2SB
2189 //
2190 UINT8 PchSidebandLock;
2191 //
2192 // Flash Protection configuration
2193 //
2194 UINT8 FprrEnable;
2195 //
2196 // HSIO message
2197 //
2198 UINT8 ChipsetInitMessage;
2199 UINT8 BypassPhySyncReset;
2200
2201 //
2202 // Debug Panel
2203 //
2204 UINT8 PlatformDebugConsent;
2205 UINT8 PmcDbgMsgEn;
2206
2207 #ifdef PCH_ICL
2208 //
2209 // FIVR Configuration;
2210 //
2211 UINT8 ExternalV1p05StateEnable[FIVR_RAIL_S0IX_SX_STATES_MAX];
2212 UINT8 ExternalVnnStateEnable[FIVR_RAIL_S0IX_SX_STATES_MAX];
2213 UINT8 ExternalVnnSxStateEnable[FIVR_RAIL_S0IX_SX_STATES_MAX];
2214
2215 UINT8 ExternalV1p05IccMax;
2216 UINT16 ExternalV1p05Voltage;
2217 UINT8 ExternalVnnIccMax;
2218 UINT16 ExternalVnnVoltage;
2219 UINT8 ExternalVnnSxIccMax;
2220 UINT16 ExternalVnnSxVoltage;
2221
2222 UINT8 PchRetToLowCurModeVolTranTime;
2223 UINT8 PchRetToHighCurModeVolTranTime;
2224 UINT8 PchLowToHighCurModeVolTranTime;
2225 UINT16 PchOffToHighCurModeVolTranTime;
2226 #endif // PCH_ICL
2227
2228 //
2229 // Miscellaneous options
2230 //
2231
2232 // Option to Enable/Disable UCMC/UCSI device
2233 UINT8 PchUcsiUcmcDevice;
2234 } PCH_SETUP;
2235
2236
2237 /**
2238 Making any setup structure change after code frozen
2239 will need to maintain backward compatibility, bump up
2240 structure revision and update below history table.\n
2241 <b>Revision 1</b>: - Initial version.
2242 **/
2243
2244 #define SI_SETUP_REVISION 1
2245
2246 typedef struct {
2247 UINT8 Revision;
2248 UINT8 SkipPostBootSai;
2249 } SI_SETUP;
2250
2251 #pragma pack()
2252
2253 #ifndef PLATFORM_SETUP_VARIABLE_NAME
2254 #define PLATFORM_SETUP_VARIABLE_NAME L"Setup"
2255 #endif
2256
2257 #define SETUP_GUID \
2258 { 0xEC87D643, 0xEBA4, 0x4BB5, { 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 } }
2259
2260 #define SA_SETUP_GUID \
2261 { 0x72c5e28c, 0x7783, 0x43a1, { 0x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4 } }
2262
2263 #define ME_SETUP_GUID \
2264 { 0x5432122d, 0xd034, 0x49d2, { 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74 } }
2265
2266 #define CPU_SETUP_GUID \
2267 { 0xb08f97ff, 0xe6e8, 0x4193, { 0xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32 } }
2268
2269 #define PCH_SETUP_GUID \
2270 { 0x4570b7f1, 0xade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } }
2271
2272 #define SI_SETUP_GUID \
2273 { 0xAAF8E719, 0x48F8, 0x4099, { 0xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D } }
2274
2275 #define DEBUG_CONFIG_GUID \
2276 { 0xDE0A5E74, 0x4E3E, 0x3D96, { 0xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97 } }
2277
2278 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SiliconPolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
SiliconPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #include <SiliconPolicyInitDxe.h>
35 #include <Library/BaseLib.h>
36
37 DXE_SI_POLICY_PROTOCOL mSiPolicyData = { 0 };
38
39 /**
40 Initilize Intel Cpu DXE Platform Policy
41
42 @param[in] ImageHandle Image handle of this driver.
43
44 @retval EFI_SUCCESS Initialization complete.
45 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
46 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
47 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
48 **/
49 EFI_STATUS
50 EFIAPI
51 SiliconPolicyInitDxe (
52 IN EFI_HANDLE ImageHandle
53 )
54 {
55 EFI_STATUS Status;
56
57 mSiPolicyData.Revision = DXE_SI_POLICY_PROTOCOL_REVISION;
58 mSiPolicyData.SmbiosOemTypeFirmwareVersionInfo = (UINT8) PcdGet8 (PcdSmbiosOemTypeFirmwareVersionInfo);
59 ///
60 /// Install the DXE_SI_POLICY_PROTOCOL interface
61 ///
62 Status = gBS->InstallMultipleProtocolInterfaces (
63 &ImageHandle,
64 &gDxeSiPolicyProtocolGuid,
65 &mSiPolicyData,
66 NULL
67 );
68 ASSERT_EFI_ERROR (Status);
69 return Status;
70 }
SiliconPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
SiliconPolicyInitDxe
EFI_STATUS SiliconPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel Cpu DXE Platform Policy.
Definition: SiliconPolicyInitDxe.c:51
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SiliconPolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
SiliconPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the SiliconPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef _SILICON_POLICY_INIT_DXE_H_
36 #define _SILICON_POLICY_INIT_DXE_H_
37
38 #include <Protocol/FirmwareVolume2.h>
39 #include <Guid/StatusCodeDataTypeId.h>
40 #include <Library/MemoryAllocationLib.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <Library/DebugLib.h>
43
44 #include <Protocol/SiPolicyProtocol.h>
45
46 /**
47 Initilize Intel CPU DXE Policy
48
49 @param[in] ImageHandle Image handle of this driver.
50
51 @retval EFI_SUCCESS Initialization complete.
52 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
53 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
54 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
55 **/
56 EFI_STATUS
57 EFIAPI
58 SiliconPolicyInitDxe (
59 IN EFI_HANDLE ImageHandle
60 );
61
62 #endif
SiliconPolicyInitDxe
EFI_STATUS SiliconPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy.
Definition: SiliconPolicyInitDxe.c:51
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SioRegs.h Source File

SioRegs.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SIO_REG_H_
35 #define _SIO_REG_H_
36
37 #define REG_LOGICAL_DEVICE 0x07
38 #define ACTIVATE 0x30
39
40 #define BASE_ADDRESS_HIGH0 0x60
41 #define BASE_ADDRESS_LOW0 0x61
42 #define BASE_ADDRESS_HIGH1 0x62
43 #define BASE_ADDRESS_LOW1 0x63
44 #define BASE_ADDRESS_HIGH2 0x64
45 #define BASE_ADDRESS_LOW2 0x65
46 #define BASE_ADDRESS_HIGH3 0x66
47 #define BASE_ADDRESS_LOW3 0x67
48 #define PRIMARY_INTERRUPT_SELECT 0x70
49 #define WAKEUP_ON_IRQ_EN 0x70
50 #define INTERRUPT_TYPE 0x71
51 #define DMA_CHANNEL_SELECT0 0x74
52 #define DMA_CHANNEL_SELECT1 0x75
53
54
55
56 //
57 //Port address for PILOT - III
58 //
59 #define PILOTIII_CHIP_ID 0x03
60 #define PILOTIII_SIO_INDEX_PORT 0x04E
61 #define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1)
62
63 #define PILOTIII_UNLOCK 0x5A
64 #define PILOTIII_LOCK 0xA5
65
66 //
67 // logical device in PILOT-III
68 //
69 #define PILOTIII_SIO_PSR 0x00
70 #define PILOTIII_SIO_COM2 0x01
71 #define PILOTIII_SIO_COM1 0x02
72 #define PILOTIII_SIO_SWCP 0x03
73 #define PILOTIII_SIO_GPIO 0x04
74 #define PILOTIII_SIO_WDT 0x05
75 #define PILOTIII_SIO_KCS3 0x08
76 #define PILOTIII_SIO_KCS4 0x09
77 #define PILOTIII_SIO_KCS5 0x0A
78 #define PILOTIII_SIO_BT 0x0B
79 #define PILOTIII_SIO_SMIC 0x0C
80 #define PILOTIII_SIO_MAILBOX 0x0D
81 #define PILOTIII_SIO_RTC 0x0E
82 #define PILOTIII_SIO_SPI 0x0F
83 #define PILOTIII_SIO_TAP 0x10
84 //
85 // Regisgers for Pilot-III
86 //
87 #define PILOTIII_CHIP_ID_REG 0x20
88 #define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE
89 #define PILOTIII_ACTIVATE ACTIVATE
90 #define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
91 #define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
92 #define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
93 #define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
94 #define PILOTIII_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
95
96 //
97 // Port address for PC8374
98 //
99 #define PC8374_SIO_INDEX_PORT 0x02E
100 #define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
101
102 //
103 // Logical device in PC8374
104 //
105 #define PC8374_SIO_FLOPPY 0x00
106 #define PC8374_SIO_PARA 0x01
107 #define PC8374_SIO_COM2 0x02
108 #define PC8374_SIO_COM1 0x03
109 #define PC8374_SIO_MOUSE 0x05
110 #define PC8374_SIO_KYBD 0x06
111 #define PC8374_SIO_GPIO 0x07
112
113 //
114 // Registers specific for PC8374
115 //
116 #define PC8374_CLOCK_SELECT 0x2D
117 #define PC8374_CLOCK_CONFIG 0x29
118
119 //
120 // Registers for PC8374
121 //
122 #define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
123 #define PC8374_ACTIVATE ACTIVATE
124 #define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
125 #define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
126 #define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
127 #define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
128
129 #define PC87427_SERVERIO_CNF2 0x22
130
131
132 //
133 // Pilot III Mailbox Data Register definitions
134 //
135 #define MBDAT00_OFFSET 0x00
136 #define MBDAT01_OFFSET 0x01
137 #define MBDAT02_OFFSET 0x02
138 #define MBDAT03_OFFSET 0x03
139 #define MBDAT04_OFFSET 0x04
140 #define MBDAT05_OFFSET 0x05
141 #define MBDAT06_OFFSET 0x06
142 #define MBDAT07_OFFSET 0x07
143 #define MBDAT08_OFFSET 0x08
144 #define MBDAT09_OFFSET 0x09
145 #define MBDAT10_OFFSET 0x0A
146 #define MBDAT11_OFFSET 0x0B
147 #define MBDAT12_OFFSET 0x0C
148 #define MBDAT13_OFFSET 0x0D
149 #define MBDAT14_OFFSET 0x0E
150 #define MBDAT15_OFFSET 0x0F
151 #define MBST0_OFFSET 0x10
152 #define MBST1_OFFSET 0x11
153 #define MBBINT_OFFSET 0x12
154
155 //
156 // Mailbox Bit definitions...
157 //
158 #define MBBINT_MBBIST_BIT 0x80
159 // If both are there, use the default one
160 //
161 #define W83527_EXIST BIT2
162 #define PC8374_EXIST BIT1
163 #define PILOTIII_EXIST BIT0
164 #define DEFAULT_SIO PILOTIII_EXIST
165 #define DEFAULT_KDB PC8374_EXIST
166
167 #define IPMI_DEFAULT_SMM_IO_BASE 0xca2
168 //
169 // For Pilot III
170 //
171
172 #define PILOTIII_SWC_BASE_ADDRESS 0xA00
173 #define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
174 #define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
175 #define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86
176 #define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4
177 #define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5
178 #define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2
179 #define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3
180 #define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600
181 #define PILOTIII_MAILBOX_MASK 0xFFE0
182 #define BMC_KCS_BASE_ADDRESS 0x0CA0
183 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SmbiosPlatformInfoDefault.h Source File

SmbiosPlatformInfoDefault.h
Go to the documentation of this file.
1 /** @file
2 This file contains Default data for Platform SMBIOS tables. This file should not
3 be altered unless update in SMBIOS Specification.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2017 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains 'Framework Code' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may not be
31 modified, except as allowed by additional terms of your license agreement.
32
33 @par Specification Reference:
34
35 **/
36
37 #ifndef _SMBIOS_PLATFORM_INFO_DEFAULT_H_
38 #define _SMBIOS_PLATFORM_INFO_DEFAULT_H_
39
40 #include <SmbiosPlatformInfoDefinition.h>
41 #include <../Features/Smbios/SmbiosMiscDxe/SmbiosMiscStrings.h>
42 //
43 // String Macro Definitions for Default Data
44 //
45 #define TO_BE_FILLED 0
46 #define DEFAULT_BIOSVENDOR_SEGMENT TO_BE_FILLED
47 #define DEFAULT_BIOSVENDOR_SIZE TO_BE_FILLED
48 /**
49 MISC_BIOS_CHARACTERISTICS.BiosCharacteristics
50 Bit0-1 Reserved1,
51 Bit02 Unknown,
52 Bit03 BiosCharacteristicsNotSupported,
53 Bit04 IsaIsSupported,
54 Bit05 McaIsSupported,
55 Bit06 EisaIsSupported,
56 Bit07 PciIsSupported,
57 Bit08 PcmciaIsSupported,
58 Bit09 PlugAndPlayIsSupported,
59 Bit10 ApmIsSupported,
60 Bit11 BiosIsUpgradable,
61 Bit12 BiosShadowingAllowed,
62 Bit13 VLVesaIsSupported,
63 Bit14 EscdSupportIsAvailable,
64 Bit15 BootFromCdIsSupported
65 Bit16 SelectableBootIsSupported,
66 Bit17 RomBiosIsSocketed,
67 Bit18 BootFromPcmciaIsSupported,
68 Bit19 EDDSpecificationIsSupported,
69 Bit20 JapaneseNecFloppyIsSupported,
70 Bit21 JapaneseToshibaFloppyIsSupported,
71 Bit22 Floppy525_360IsSupported,
72 Bit23 Floppy525_12IsSupported,
73 Bit24 Floppy35_720IsSupported,
74 Bit25 Floppy35_288IsSupported,
75 Bit26 PrintScreenIsSupported,
76 Bit27 Keyboard8042IsSupported,
77 Bit28 SerialIsSupported,
78 Bit29 PrinterIsSupported,
79 Bit30 CgaMonoIsSupported,
80 Bit31 NecPc98,
81 Bit32-63 Reserved for BIOS/System Vendor
82 **/
83 #define DEFAULT_BIOSVENDOR_CHARS { 0,0,0,0,0,0,1,0,0,0,1,1,0,0,1,1,0,0,1,0,0,0,0,0,0,1,1,1,1,0,0,0 }
84 /**
85 MISC_BIOS_CHARACTERISTICS_EXTENSION.BiosReserved
86 Bit0 AcpiIsSupported,
87 Bit1 UsbLegacyIsSupported,
88 Bit2 AgpIsSupported,
89 Bit3 I20BootIsSupported,
90 Bit4 Ls120BootIsSupported,
91 Bit5 AtapiZipDriveBootIsSupported,
92 Bit6 Boot1394IsSupported,
93 Bit7 SmartBatteryIsSupported
94 **/
95 #define DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS (UINT8)(BIT0 | BIT1 | BIT4 | BIT5)
96 /**
97 MISC_BIOS_CHARACTERISTICS_EXTENSION.SystemReserved
98 Bit0 BiosBootSpecIsSupported,
99 Bit1 FunctionKeyNetworkBootIsSupported,
100 Bit2 TargetContentDistributionEnabled,
101 Bit3 UefiSpecificationSupported,
102 Bit4 VirtualMachineSupported,
103 Bit5-7 ExtensionByte2Reserved
104 **/
105 #define DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM (UINT8)(BIT0 | BIT1 | BIT2 | BIT3)
106 #define DEFAULT_BIOSVENDOR_EC_RELEASE 0xFF
107 #define DEFAULT_SYSINFO_PRODUCTNAME L"Client Platform"
108 #define DEFAULT_SYSINFO_VERSION L"0.1"
109 #define DEFAULT_SYSINFO_FAMILY L"Client System"
110 #define DEFAULT_BOARDINFO_PRODUCTNAME L"RVP/SDS"
111 #define DEFAULT_BOARDINFO_MANUFACTURER L"Intel Corporation"
112 #define DEFAULT_BOARDINFO_VERSION L"FAB"
113 #define DEFAULT_BOARDINFO_FLAGS { 1,0,0,0,0,0 }
114 #define DEFAULT_BOARDINFO_CHASSIS L"Part Component"
115 #define DEFAULT_CHASSISINFO_MANUFACTURER L"Intel Corporation"
116 #define DEFAULT_CHASSISINFO_VERSION L"0.1"
117 #define DEFAULT_CHASSISINFO_OEM { 0,0,0,0 }
118 #define DEFAULT_CHASSISINFO_HEIGHT 0
119 #define DEFAULT_CHASSISINFO_POWER_CORDS_NUM 1
120 #define DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR L"None"
121 /* Default Port Info { IsPublishRequired, InternalDesignator, InternalConnectorType, ExternalDesignator, InternalConnectorType, PortType } */
122 #define DEFAULT_PORT_INFO { Required, DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR, PortConnectorTypeNone, DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR, PortConnectorTypeNone, PortTypeNone }
123 #define DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION L"To Be Filled by O.E.M."
124 /* Default OnBoard Device Info { IsPublishRequired, Description, DeviceType, DeviceStatus } */
125 #define DEFAULT_ONBOARD_DEV_INFO { Required, DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION, OnBoardDeviceTypeUnknown, Enabled }
126 #define DEFAULT_CONFIG_OPTIONS_STRING L"JUMPER:OPTIONS; NA:NA"
127 #define DEFAULT_BIOS_LANG_INFO_LANGUAGES { L"enUS" }
128 #define DEFAULT_BIOS_LANG_INFO_INSTALL_LANGUAGES MAX_LANGUAGES
129 #define DEFAULT_PORTABLE_BATTERY_LOCATION L"Battery Location"
130 #define DEFAULT_PORTABLE_BATTERY_MANUFACTURER L"Battery Manufacturer"
131 #define DEFAULT_PORTABLE_BATTERY_MANUFACTURER_DATE L"Battery Manufacture Date"
132 #define DEFAULT_PORTABLE_BATTERY_SERIAL_NUMBER L"Battery Serial Number"
133 #define DEFAULT_PORTABLE_BATTERY_DEVICE_NAME L"Battery"
134 /* Default Portable Battery Info { IsPublishRequired, BatteryType, Location, Manufacturer, ManufactureDate, SerialNumber, DevName, DevChemistry, DevCapacity, Voltage, SbdsVersion, MaxErrorInBatteryData, SbdsSerialNumber, SbdsManufactureDate, SbdsDeviceChemistry, CapacityMultiplier, Oem }*/
135 #define DEFAULT_PORTABLE_BATTERY_INFO { Required, Unknown, L"Battery Location", L"Battery Manufacturer", L"Battery Manufacture Date", L"Battery Serial Number", L"Battery", PortableBatteryDeviceChemistryUnknown, 0, 0, L"SBDS Version", 0, 0, 0, L"SBDS Device Chemistry", 1, 0, }
136 /* Default Cooling Device Info { IsPublishRequired, Type, Status, Group, Oem, Speed, Description } */
137 #define DEFAULT_COOLING_DEVICE_INFO { Required, CoolingDeviceTypeUnknown, CoolingDeviceStatusUnknown, 0x01, 0x0, 0x8000, L"Cooling Device" }
138 #define DEFAULT_COOLING_DEVICE_DESC L"Cooling Device"
139 #define TO_BE_FILLED_BY_OEM_STR L"To Be Filled by O.E.M."
140 #define DEFAULT_POWER_SUPPLY_INPUT_VOLT_PROBE 0
141 #define DEFAULT_POWER_SUPPLY_COOLING_DEVICE 0x0A
142 #define DEFAULT_POWER_SUPPLY_INPUT_CURR_PROBE 0
143 #define DEFAULT_POWER_SUPPLY_INFO_GROUP 0x1
144 #define DEFAULT_POWER_SUPPLY_INFO_POWER_CAPACITY 0x8000
145 /* Default Power Supply Characteristics { Bit0 HotReplaceable, Bit1 Present, Bit2 Unplugged, Bit3-6 InputVoltageRangeSwitch, Bit7-9 Status, Bit10-13 Type, Bit14-15 Reserved } */
146 #define DEFAULT_POWER_SUPPLY_INFO_CHARACTERISTICS { FALSE, TRUE, FALSE, InputVoltRangeSwitchUnknown, PowerSupplyStatusUnknown, PowerSupplyTypeUnknown, 0x0 }
147 /* Default OnBoard Device Extended Info { IsPublishRequired, Designation, DeviceType, DeviceStatus, DeviceInstance, Segment, Bus, DevFunc } */
148 #define DEFAULT_ONBOARD_DEV_EXT_INFO { Required, DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION, OnBoardDeviceExtendedTypeUnknown, Enabled, 0, 0xFF, 0xFF, 0xFF }
149 #define DEFAULT_SLOT_DESIGN L"PCI-Express #" // Slot Designation
150 //
151 // Default Bios Vendor Info for SMBIOS Type 0
152 //
153
154 SMBIOS_TABLE_TYPE0 mDefaultBiosVendorInfo = {
155 { // Hdr
156 SMBIOS_TYPE_BIOS_INFORMATION, /// Hdr.Type
157 sizeof (SMBIOS_TABLE_TYPE0), /// Hdr.Length
158 0 /// Hdr.Handle
159 },
160 SMBIOS_MISC_STRING_1, // Vendor
161 SMBIOS_MISC_STRING_2, // BiosVersion
162 DEFAULT_BIOSVENDOR_SEGMENT, // BiosSegment
163 SMBIOS_MISC_STRING_3, // BiosReleaseDate
164 DEFAULT_BIOSVENDOR_SEGMENT, // BiosSize = 64K *(n+1) where n=20 for 2MB
165 DEFAULT_BIOSVENDOR_CHARS, // BiosCharacteristics
166 { // BiosCharacteristicsExtensionBytes
167 DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS,
168 DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM
169 },
170 0x0, // System BIOS Major Release
171 0x1, // System BIOS Minor Release
172 DEFAULT_BIOSVENDOR_EC_RELEASE, // Embedded controller firmware major Release
173 DEFAULT_BIOSVENDOR_EC_RELEASE // Embedded controller firmware minor Release
174 };
175
176 SMBIOS_TABLE_TYPE00_STRINGS mDefaultBiosVendorStrings = {
177 SMBIOS_MISC_TYPE00_VENDOR,
178 SMBIOS_MISC_TYPE00_BIOS_VERSION,
179 SMBIOS_MISC_TYPE00_BIOS_RELEASE_DATE
180 };
181
182 //
183 // Default System Info for SMBIOS Type 1
184 //
185
186 SMBIOS_TABLE_TYPE1 mDefaultSysInfo = {
187 { // Hdr
188 SMBIOS_TYPE_SYSTEM_INFORMATION, /// Hdr.Type
189 sizeof (SMBIOS_TABLE_TYPE1), /// Hdr.Size
190 0 /// Hdr.Handle
191 },
192 SMBIOS_MISC_STRING_1, // SystemManufactrurer
193 SMBIOS_MISC_STRING_2, // SystemProductName
194 SMBIOS_MISC_STRING_3, // SystemVersion
195 SMBIOS_MISC_STRING_4, // SystemSerialNumber
196 { // SystemUuid
197 0x5e24fe9c, 0xc8d0, 0x45bd, { 0xa7, 0x9f, 0x54, 0xea, 0x5f, 0xbd, 0x3d, 0x97 }
198 },
199 SystemWakeupTypeOther, // SystemWakeupType
200 SMBIOS_MISC_STRING_5, // SystemSKUNumber
201 SMBIOS_MISC_STRING_6 // SystemFamily
202 };
203
204 SMBIOS_TABLE_TYPE01_STRINGS mDefaultSysStrings = {
205 SMBIOS_MISC_TYPE01_MANUFACTURER,
206 DEFAULT_SYSINFO_PRODUCTNAME,
207 DEFAULT_SYSINFO_VERSION,
208 SMBIOS_MISC_TYPE01_SERIAL_NUMBER,
209 SMBIOS_MISC_TYPE01_SKU_NUMBER,
210 DEFAULT_SYSINFO_FAMILY
211 };
212
213
214 //
215 // Default Base Board info for RVP Board data
216 //
217 #define DEFAULT_BASE_BOARD_INFO { DEFAULT_BOARDINFO_PRODUCTNAME, DEFAULT_BOARDINFO_MANUFACTURER, DEFAULT_BOARDINFO_VERSION, 0x1, BaseBoardTypeMotherBoard, DEFAULT_BOARDINFO_CHASSIS }
218 BASE_BOARD_INFO mDefaultBaseBoardInfo[] = {
219 DEFAULT_BASE_BOARD_INFO
220 };
221 //
222 // Default BaseBoard Info for SMBIOS Type 2
223 //
224 SMBIOS_TABLE_TYPE2 mDefaultBaseBoardsInfo = {
225 { // Hdr
226 SMBIOS_TYPE_BASEBOARD_INFORMATION, ///< Hdr.Type
227 sizeof (SMBIOS_TABLE_TYPE2), ///< Hdr.Length
228 0 ///< Hdr.Handle
229 },
230 SMBIOS_MISC_STRING_1, ///< Manufacturer
231 SMBIOS_MISC_STRING_2, ///< ProductName
232 SMBIOS_MISC_STRING_3, ///< Version
233 SMBIOS_MISC_STRING_4, ///< SerialNumber
234 SMBIOS_MISC_STRING_5, ///< AssetTag
235 { // FeatureFlags
236 1, ///< Bit0 Motherboard
237 0, ///< Bit1 RequiresDaughterCard
238 0, ///< Bit2 Removable
239 1, ///< Bit3 Replaceable,
240 0, ///< Bit4 HotSwappable
241 0, ///< Bit5-7 Reserved
242 },
243 SMBIOS_MISC_STRING_6, // LocationInChassis
244 0, // ChassisHandle
245 BaseBoardTypeMotherBoard, // BoardType
246 0, // NumberOfContainedObjectHandles
247 { 0 } // ContainedObjectHandles
248 };
249
250 SMBIOS_TABLE_TYPE02_STRINGS mDefaultBaseBoardsStrings = {
251 DEFAULT_BOARDINFO_MANUFACTURER, //Manufacturer
252 DEFAULT_BOARDINFO_PRODUCTNAME, //ProductName
253 DEFAULT_BOARDINFO_VERSION, //Version
254 SMBIOS_MISC_TYPE02_BOARD_SERIAL_NUMBER, //SerialNumber
255 SMBIOS_MISC_TYPE02_BOARD_ASSET_TAG, //AssetTag
256 DEFAULT_BOARDINFO_CHASSIS //LocationInChassis
257 };
258
259
260 //
261 // Default Chassis info for RVP Board data
262 //
263 #define DEFAULT_CHASSIS_INFO { DEFAULT_CHASSISINFO_MANUFACTURER, MiscChassisTypeOther, DEFAULT_CHASSISINFO_VERSION, ChassisStateSafe, ChassisStateSafe, ChassisStateOther, ChassisSecurityStatusOther, DEFAULT_CHASSISINFO_HEIGHT, DEFAULT_CHASSISINFO_POWER_CORDS_NUM }
264 CHASSIS_INFO mDefaultChssisInfo [] = {
265 DEFAULT_CHASSIS_INFO
266 };
267 //
268 // Default Chassis Info for SMBIOS Type 3
269 //
270 SMBIOS_TABLE_TYPE3 mDefaultChssisInfoInfo = {
271 { // Hdr
272 SMBIOS_TYPE_SYSTEM_ENCLOSURE, ///< Hdr.Type
273 sizeof(SMBIOS_TABLE_TYPE3), ///< Hdr.Length
274 0 ///< Hdr.Handle
275 },
276 SMBIOS_MISC_STRING_1, ///< Manufactrurer
277 0, ///< Type
278 SMBIOS_MISC_STRING_2, ///< Version
279 SMBIOS_MISC_STRING_3, ///< SerialNumber
280 SMBIOS_MISC_STRING_4, ///< AssetTag
281 ChassisStateSafe, ///< BootupState
282 ChassisStateSafe, ///< PowerSupplyState
283 ChassisStateOther, ///< ThermalState
284 ChassisSecurityStatusOther, ///< SecurityStatus
285 { // OemDefined[4]
286 0,
287 0,
288 0,
289 0
290 },
291 0, ///< Height
292 1, ///< NumberofPowerCords
293 0, ///< ContainedElementCount
294 0, ///< ContainedElementRecordLength
295 { // ContainedElements
296 {
297 0, ///< ContainedElementType
298 0, ///< ContainedElementMinimum
299 0 ///< ContainedElementMaximum
300 }
301 }
302 };
303
304 SMBIOS_TABLE_TYPE02_STRINGS mDefaultChssisInfoStrings = {
305 DEFAULT_CHASSISINFO_MANUFACTURER, //Manufacturer
306 DEFAULT_CHASSISINFO_VERSION, //Version
307 SMBIOS_MISC_CHASSIS_SERIAL_NUMBER, //SerialNumber
308 SMBIOS_MISC_CHASSIS_ASSET_TAG //AssetTag
309 };
310
311 //
312 // Default Port Info for SMBIOS Type 8
313 //
314
315 SMBIOS_TABLE_TYPE8 mDefaultPortConnectorsInfo = {
316 { // Hdr
317 SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type
318 sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length
319 0 ///< Hdr.Handle
320 },
321 SMBIOS_MISC_STRING_1, ///< InternalConnectorDesignator
322 PortConnectorTypeNone, ///< InternalConnectorType
323 SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator
324 PortConnectorTypeNone, ///< ExternalConnectorType
325 PortTypeNone ///< PortType
326 };
327
328 SMBIOS_TABLE_TYPE8_STRINGS mDefaultPortConnectorsStrings = {
329 DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR,
330 DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR
331 };
332
333 //
334 // Default Supported Port Connectors for RVP Board data
335 //
336 #define DEFAULT_PORT_CONNECTORS_SUPPORT 0x1FFFFFFFFFF // Set from Bit0 to Bit 40 in order to enable all port connectors by default.
337
338 //
339 // Default OnBoard Device Info for SMBIOS Type 10
340 //
341
342 SMBIOS_TABLE_TYPE10 mDefaultOnboardDevInfo = {
343 { // Hdr
344 SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION, ///< Hdr.Type
345 sizeof(SMBIOS_TABLE_TYPE10), ///< Hdr.Length
346 0 ///< Hdr.Handle
347 },
348 {
349 { // Device
350 OnBoardDeviceTypeUnknown, ///< DeviceType
351 SMBIOS_MISC_STRING_1 ///< DescriptionString
352 }
353 }
354 };
355
356 SMBIOS_TABLE_TYPE10_STRINGS mDefaultOnboardDevStrings = {
357 DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION
358 };
359
360 //
361 // Default System Config for SMBIOS Type 12
362 //
363
364 SMBIOS_TABLE_TYPE12 mDefaultSysConfigInfo = {
365 {
366 SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS,
367 sizeof(SMBIOS_TABLE_TYPE12),
368 0
369 },
370 SMBIOS_MISC_STRING_1
371 };
372
373 SMBIOS_TABLE_TYPE12_STRINGS mDefaultSysConfigStrings = {
374 DEFAULT_CONFIG_OPTIONS_STRING //StringCount
375 };
376 //
377 // Default Language Info for SMBIOS Type 13
378 //
379
380 SMBIOS_TABLE_TYPE13 mDefaultBiosLangInfo = {
381 { // Hdr
382 SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, ///< Hdr.Type
383 sizeof(SMBIOS_TABLE_TYPE13), ///< Hdr.Length
384 0 ///< Hdr.Handle
385 },
386 DEFAULT_BIOS_LANG_INFO_INSTALL_LANGUAGES, // NumberOfInstallableLanguages
387 Abbreviated, // LanguageFlags
388 { // Reserve[15]
389 0,
390 0,
391 0,
392 0,
393 0,
394 0,
395 0,
396 0,
397 0,
398 0,
399 0,
400 0,
401 0,
402 0,
403 0
404 },
405 SMBIOS_MISC_STRING_1, // CurrentLanguage
406 };
407 SMBIOS_TABLE_TYPE13_STRINGS mDefaultBiosLangStrings[] = DEFAULT_BIOS_LANG_INFO_LANGUAGES; //CurrentLanguages
408 //
409 // Default Portable Battery Info for SMBIOS Type 22
410 //
411
412 SMBIOS_TABLE_TYPE22 mDefaultPortableBatteryInfo = {
413 { // Hdr
414 SMBIOS_TYPE_PORTABLE_BATTERY, ///< Hdr.Type
415 sizeof(SMBIOS_TABLE_TYPE22), ///< Hdr.Length
416 0 ///< Hdr.Handle
417 },
418 SMBIOS_MISC_STRING_1, ///< Location
419 SMBIOS_MISC_STRING_2, ///< Manufacturer
420 SMBIOS_MISC_STRING_3, ///< ManufacturerDate
421 SMBIOS_MISC_STRING_4, ///< SerialNumber
422 SMBIOS_MISC_STRING_5, ///< DeviceName
423 PortableBatteryDeviceChemistryUnknown, ///< DeviceChemistry
424 0, ///< DeviceCapacity
425 0, ///< DeviceVoltage
426 SMBIOS_MISC_STRING_NULL, ///< SBDSVersionNumber
427 0xff, ///< MaximumErrorInBatteryData
428 0, ///< SBDSSerialNumber
429 0, ///< SBDSManufactureDate
430 SMBIOS_MISC_STRING_NULL, ///< SBDSDeviceChemistry
431 1, ///< DesignCapacityMultiplier
432 0 ///< OEMSpecific
433 };
434 SMBIOS_TABLE_TYPE22_STRINGS mDefaultPortableBatteryStrings = {
435 DEFAULT_PORTABLE_BATTERY_LOCATION, //Location;
436 DEFAULT_PORTABLE_BATTERY_MANUFACTURER, //Manufacturer;
437 DEFAULT_PORTABLE_BATTERY_MANUFACTURER_DATE, //ManufacturerDate;
438 DEFAULT_PORTABLE_BATTERY_SERIAL_NUMBER, //SerialNumber;
439 DEFAULT_PORTABLE_BATTERY_DEVICE_NAME //DeviceName;
440 };
441
442
443 //
444 // Default Cooling device info for RVP Board data
445 //
446 #define DEFAULT_COOLING_DEV_SUPPORT (BIT0 | BIT1)
447 #define DEFAULT_COOLING_DEV { CoolingDeviceTypeUnknown, L"Cooling Device" }
448
449 COOLING_DEV mDefaultCoolingDev [] = {
450 DEFAULT_COOLING_DEV
451 };
452 //
453 // Default Cooling Device Info for SMBIOS Type 27
454 //
455 SMBIOS_TABLE_TYPE27 mDefaultCoolingDeviceInfo = {
456 { // Hdr
457 SMBIOS_TYPE_COOLING_DEVICE, ///< Hdr.Type
458 sizeof(SMBIOS_TABLE_TYPE27), ///< Hdr.Length
459 0 ///< Hdr.Handle
460 },
461 SMBIOS_MISC_TEMP_PROBE_HANDLE, ///< TempratureProbeHandle
462 { // DeviceTypeAndStatus
463 CoolingDeviceTypeUnknown, ///< DeviceTypeAndStatus.CoolingDevice
464 CoolingDeviceStatusUnknown ///< DeviceTypeAndStatus.CoolingDeviceStatus
465 },
466 0x01, ///< CoolingUnitGroup
467 0, ///< OEMDefined
468 0x8000, ///< NominalSpeed
469 SMBIOS_MISC_STRING_1 ///< Description
470 };
471
472 SMBIOS_TABLE_TYPE27_STRINGS mDefaultCoolingDeviceStrings = {
473 DEFAULT_COOLING_DEVICE_DESC //Description
474 };
475
476 //
477 // Default Boot Info for SMBIOS Type 32
478 //
479
480 SMBIOS_TABLE_TYPE32 mDefaultBootInfo = {
481 { // Hdr
482 SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, ///< Hdr.Type
483 sizeof(SMBIOS_TABLE_TYPE32), ///< Hdr.Length
484 0 ///< Hdr.Handle
485 },
486 { // Reserved[6]
487 0,
488 0,
489 0,
490 0,
491 0,
492 0
493 },
494 BootInformationStatusNoError ///< BootStatus
495 };
496 //
497 // Default System Power Supply Info for SMBIOS Type 39
498 //
499
500 SMBIOS_TABLE_TYPE39 mDefaultPowerSupplyInfo = {
501 { // Hdr
502 SMBIOS_TYPE_SYSTEM_POWER_SUPPLY, ///< Hdr.Type
503 sizeof(SMBIOS_TABLE_TYPE39), ///< Hdr.Length
504 0 ///< Hdr.Handle
505 },
506 DEFAULT_POWER_SUPPLY_INFO_GROUP, ///< PowerUnitGroup
507 SMBIOS_MISC_STRING_1, ///< Location
508 SMBIOS_MISC_STRING_2, ///< DeviceName
509 SMBIOS_MISC_STRING_3, ///< Manufacturer
510 SMBIOS_MISC_STRING_4, ///< SerialNumber
511 SMBIOS_MISC_STRING_5, ///< AssertTagNumber
512 SMBIOS_MISC_STRING_6, ///< ModelPartNumber
513 SMBIOS_MISC_STRING_7, ///< RevisionLevel
514 DEFAULT_POWER_SUPPLY_INFO_POWER_CAPACITY, ///< MaxPowerCapacity
515 DEFAULT_POWER_SUPPLY_INFO_CHARACTERISTICS, // PowerSupplyCharacteristics
516 DEFAULT_POWER_SUPPLY_INPUT_VOLT_PROBE, ///< InputVoltageProbeHandle
517 DEFAULT_POWER_SUPPLY_COOLING_DEVICE, ///< CoolingDeviceHandle
518 DEFAULT_POWER_SUPPLY_INPUT_CURR_PROBE ///< InputCurrentProbeHandle
519 };
520
521 SMBIOS_TABLE_TYPE39_STRINGS mDefaultPowerSupplyStrings = {
522 TO_BE_FILLED_BY_OEM_STR, //Location
523 TO_BE_FILLED_BY_OEM_STR, //DeviceName
524 TO_BE_FILLED_BY_OEM_STR, //Manufacturer
525 TO_BE_FILLED_BY_OEM_STR, //SerialNumber
526 TO_BE_FILLED_BY_OEM_STR, //AssetTagNumber
527 TO_BE_FILLED_BY_OEM_STR, //ModelPartNumber
528 TO_BE_FILLED_BY_OEM_STR //RevisionLevel
529 };
530
531
532
533 //
534 // Default OnBoard Device info for RVP Board data
535 //
536 #define DEFAULT_ONBOARD_DEV_SUPPORT (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) // Enable all bits to support all On-board devices
537 #define DEFAULT_ONBOARD_DEV_ADDR { 0, 0xFF, 0xFF, 0xFF }
538
539 ONBOARD_DEV_ADDR mDefaultOnboardDevAddr [] = {
540 DEFAULT_ONBOARD_DEV_ADDR
541 };
542 //
543 // Default OnBoard Device Extended Info for SMBIOS Type 41
544 //
545 SMBIOS_TABLE_TYPE41 mDefaultOnBoardDeviceExtendedRecord = {
546 { // Hdr
547 SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION, ///< Hdr.Type
548 sizeof(SMBIOS_TABLE_TYPE41), ///< Hdr.Length
549 0 ///< Hdr.Handle
550 },
551 // Device
552 SMBIOS_MISC_STRING_1, ///< ReferenceDesignation
553 OnBoardDeviceExtendedTypeUnknown, ///< DeviceType
554 0, ///< DeviceTypeInstance
555 0, ///< SegmentGroupNum
556 0xFF, ///< BusNum
557 0xFF ///< DevFuncNum
558 };
559
560 SMBIOS_TABLE_TYPE41_STRINGS mDefaultOnBoardDeviceExtendedStrings = {
561 DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION //Description String
562 };
563
564 //
565 // Default OEM Type 136
566 //
567 SMBIOS_TABLE_TYPE136 mDefaultOemType136 = {
568 { // Hdr
569 SMBIOS_TYPE_OEM_136, ///< Hdr.Type
570 sizeof(SMBIOS_TABLE_TYPE136), ///< Hdr.Length
571 0 ///< Hdr.Handle
572 },
573 0, ///< RawData
574 0 ///< Zero
575 };
576
577 //
578 // Default System Slot Info for SMBIOS Type 9
579 //
580 SMBIOS_TABLE_TYPE9 mDefaultSystemSlotRecord = {
581 { // Hdr
582 SMBIOS_TYPE_SYSTEM_SLOTS, ///< Hdr.Type
583 sizeof(SMBIOS_TABLE_TYPE9), ///< Hdr.Length
584 0 ///< Hdr.Handle
585 },
586 SMBIOS_MISC_STRING_1, ///< SlotDesignation;
587 SlotTypePciExpress, ///< SlotType
588 SlotDataBusWidth1X, ///< SlotDataBusWidth;
589 SlotUsageAvailable, ///< CurrentUsage;
590 SlotLengthLong, ///< SlotLength;
591 0, ///< SlotID;
592 { ///< SlotCharacteristics1;
593 0, // Bit0 - CharacteristicsUnknown
594 0, // Bit1 - Provides 5.0 Volts
595 1, // Bit2 - Provides 3.3 Volts
596 0, // Bit3 - SharedSlot
597 0, // Bit4 - PcCard16Supported
598 0, // Bit5 - CardBusSupported
599 0, // Bit6 - ZoomVideoSupported
600 0 // Bit7 - ModemRingResumeSupported
601 },
602 { ///< SlotCharacteristics2;
603 1, // Bit0 - PmeSignalSupported
604 1, // Bit1 - HotPlugDevicesSupported
605 1, // Bit2 - SmbusSignalSupported
606 0 // Bit3-7 - Reserved
607 },
608 0x00, ///< SegmentGroupNum;
609 0xFF, ///< BusNum;
610 0xFF ///< DevFuncNum;
611 };
612
613 SMBIOS_TABLE_TYPE9_STRINGS mDefaultSystemSlotStrings = {
614 DEFAULT_SLOT_DESIGN //SlotDesignation
615 };
616
617 //
618 // Default Smbios Platform Info table
619 //
620 SMBIOS_PLATFORM_INFO mDefaultSmbiosPlatformInfo[] = {
621
622 { (VOID*)(&mDefaultBiosVendorInfo), (VOID*)(&mDefaultBiosVendorStrings), SIZEOF_SMBIOS_STRINGS(00), FALSE, 1 }, // SMBIOS Type 0 - BiosVendor
623
624 { (VOID*)(&mDefaultSysInfo), (VOID*)(&mDefaultSysStrings), SIZEOF_SMBIOS_STRINGS(01), FALSE, 1 }, // SMBIOS Type 1 - SystemManufacturer
625
626 { (VOID*)(&mDefaultBaseBoardsInfo), (VOID*)(&mDefaultBaseBoardsStrings), SIZEOF_SMBIOS_STRINGS(02), FALSE, 1 }, // SMBIOS Type 2 - BaseBoardManufacturer
627
628 { (VOID*)(&mDefaultChssisInfoInfo), (VOID*)(&mDefaultChssisInfoStrings), SIZEOF_SMBIOS_STRINGS(03), FALSE, 1 }, // SMBIOS Type 3 - ChassisManufacturer
629
630 { (VOID*)(&mDefaultBootInfo), NULL, 0, FALSE, 1 }, // SMBIOS Type 32 - BootInfoStatus
631
632 { (VOID*)(&mDefaultBiosLangInfo), (VOID*)(&mDefaultBiosLangStrings[0]), SIZEOF_SMBIOS_STRINGS(13), FALSE, 1 }, // SMBIOS Type 13 - BiosLanguagesInfo
633
634 { (VOID*)(&mDefaultSysConfigInfo), (VOID*)(&mDefaultSysConfigStrings), SIZEOF_SMBIOS_STRINGS(12), FALSE, 1 }, // SMBIOS Type 12 - SystemOptionString
635
636 { (VOID*)(&mDefaultPortConnectorsInfo), (VOID*)(&mDefaultPortConnectorsStrings), SIZEOF_SMBIOS_STRINGS(8), FALSE, 1 }, // SMBIOS Type 8 - PortConnectors
637
638 { (VOID*)(&mDefaultOnboardDevInfo), (VOID*)(&mDefaultOnboardDevStrings), SIZEOF_SMBIOS_STRINGS(10), FALSE, 1 }, // SMBIOS Type 10 - OnBoardDevice
639
640 { (VOID*)(&mDefaultOemType136), NULL, 0, FALSE, 1 }, // SMBIOS Type 136 - OemType136
641
642 { (VOID*)(&mDefaultPortableBatteryInfo), (VOID*)(&mDefaultPortableBatteryStrings), SIZEOF_SMBIOS_STRINGS(22), FALSE, 1 }, // SMBIOS Type 22 - PortableBattery
643
644 { (VOID*)(&mDefaultCoolingDeviceInfo), (VOID*)(&mDefaultCoolingDeviceStrings), SIZEOF_SMBIOS_STRINGS(27), FALSE, 1 }, // SMBIOS Type 27 - CoolingDevice
645
646 { (VOID*)(&mDefaultPowerSupplyInfo), (VOID*)(&mDefaultPowerSupplyStrings), SIZEOF_SMBIOS_STRINGS(39), FALSE, 1 }, // SMBIOS Type 39 - SystemPowerSupply
647
648 { (VOID*)(&mDefaultOnBoardDeviceExtendedRecord), (VOID*)(&mDefaultOnBoardDeviceExtendedStrings), SIZEOF_SMBIOS_STRINGS(41), FALSE, 1 }, // SMBIOS Type 41 - OnBoardDeviceExtended
649
650 { (VOID*)(&mDefaultSystemSlotRecord), (VOID*)(&mDefaultSystemSlotStrings), SIZEOF_SMBIOS_STRINGS(9), FALSE, 1 } // SMBIOS Type 9 - SystemSlot
651
652 };
653 //
654 // Default Smbios Board info for RVP Board data
655 //
656 SMBIOS_PLATFORM_BOARD_INFO mDefaultSmbiosBoardInfo = {
657 DEFAULT_SYSINFO_PRODUCTNAME, //SystemProductName
658 DEFAULT_SYSINFO_VERSION, //SystemVersion
659 DEFAULT_SYSINFO_FAMILY, //SystemFamily
660 SystemWakeupTypeOther, //SystemWakeUpType
661 &mDefaultBaseBoardInfo[0], //BaseBoard
662 &mDefaultChssisInfo[0], //ChassisInfo
663 DEFAULT_PORT_CONNECTORS_SUPPORT, //SupportedPortConnectors
664 DEFAULT_CONFIG_OPTIONS_STRING, //SystemConfigOptions
665 &mDefaultCoolingDev[0], //CoolingDevCoolingDev
666 DEFAULT_ONBOARD_DEV_SUPPORT, //SupportedOnboardDev
667 &mDefaultOnboardDevAddr[0] //OnBoardDevAddr
668 };
669
670 #endif //_SMBIOS_PLATFORM_INFO_DEFAULT_H_
DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS
#define DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS
MISC_BIOS_CHARACTERISTICS_EXTENSION.BiosReserved Bit0 AcpiIsSupported, Bit1 UsbLegacyIsSupported, Bit2 AgpIsSupported, Bit3 I20BootIsSupported, Bit4 Ls120BootIsSupported, Bit5 AtapiZipDriveBootIsSupported, Bit6 Boot1394IsSupported, Bit7 SmartBatteryIsSupported.
Definition: SmbiosPlatformInfoDefault.h:95
DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM
#define DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM
MISC_BIOS_CHARACTERISTICS_EXTENSION.SystemReserved Bit0 BiosBootSpecIsSupported, Bit1 FunctionKeyNetw...
Definition: SmbiosPlatformInfoDefault.h:105
DEFAULT_BIOSVENDOR_CHARS
#define DEFAULT_BIOSVENDOR_CHARS
MISC_BIOS_CHARACTERISTICS.BiosCharacteristics Bit0-1 Reserved1, Bit02 Unknown, Bit03 BiosCharacterist...
Definition: SmbiosPlatformInfoDefault.h:83
SmbiosPlatformInfoDefinition.h
This file contains definition for Platform SMBIOS Info.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SmbiosPlatformInfoDefinition.h Source File

SmbiosPlatformInfoDefinition.h
Go to the documentation of this file.
1 /** @file
2 This file contains definition for Platform SMBIOS Info.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _SMBIOS_PLATFORM_INFO_DEFINITION_H_
37 #define _SMBIOS_PLATFORM_INFO_DEFINITION_H_
38
39 #include <IndustryStandard/SmBios.h>
40 //
41 // The below enumeration describes the order in which SMBIOS tables are published by SmbiosMiscDxe driver.
42 //
43 typedef enum{
44
45 BiosVendor = 0,
46 SystemManufacturer,
47 BaseBoardManufacturer,
48 ChassisManufacturer,
49 BootInfoStatus,
50 BiosLanguagesInfo,
51 SystemOptionString,
52 PortConnectors,
53 OnBoardDevice,
54 OemType136,
55 PortableBattery,
56 CoolingDevice,
57 SystemPowerSupply,
58 OnBoardDeviceExtended,
59 SystemSlot
60
61 }PLATFORM_SMBIOS_DATA_ORDER;
62
63 #define SIZEOF_SMBIOS_STRINGS(Type) (sizeof(SMBIOS_TABLE_TYPE ## Type ## _STRINGS) / sizeof (CHAR16*))
64
65 //
66 // Platform Info for Type 0 - BIOS Vendor
67 //
68 typedef struct {
69 UINT16 Segment;
70 UINT32 Size;
71 MISC_BIOS_CHARACTERISTICS Characteristics;
72 MISC_BIOS_CHARACTERISTICS_EXTENSION CharacteristicsExt;
73 UINT8 EcFwMajorRelease;
74 UINT8 EcFwMinorRelease;
75 }BIOS_VENDOR_INFO_TYPE0;
76
77 //
78 // Platform Info for Type 1 - System Info
79 //
80 typedef struct {
81 CHAR16 *ProductName;
82 CHAR16 *Version;
83 CHAR16 *Family;
84 UINT8 WakeUpType;
85 }SYSTEM_INFO_TYPE1;
86
87 //
88 // Platform Info For Type 2 - Base Board Info
89 //
90 typedef struct {
91 CHAR16 *ProductName;
92 CHAR16 *Manufacturer;
93 CHAR16 *Version;
94 BASE_BOARD_FEATURE_FLAGS FeatureFlags;
95 UINT8 BoardType;
96 CHAR16 *LocationInChassis;
97 }BASEBOARD_INFO_TYPE2;
98
99 //
100 // Platform Info For Type 3 - Chassis Info
101 //
102 typedef struct {
103 CHAR16 *Manufacturer;
104 MISC_CHASSIS_TYPE Type;
105 CHAR16 *Version;
106 MISC_CHASSIS_STATE Bootup;
107 MISC_CHASSIS_STATE PowerSupply;
108 MISC_CHASSIS_STATE Thermal;
109 MISC_CHASSIS_SECURITY_STATE Security;
110 UINT8 Oem[4];
111 UINT8 Height;
112 UINT8 NumberofPowerCords;
113 }CHASSIS_INFO_TYPE3;
114
115 //
116 // Platform Info For Type 8 - Port Connector Information
117 //
118 #define NUM_DEFINED_PORT_TYPES 41
119
120 typedef enum {
121 NotRequired=0,
122 Required
123 }PUBLISH_REQ;
124
125 typedef struct {
126 PUBLISH_REQ IsPublishRequired;
127 CHAR16 *InternalDesignator;
128 MISC_PORT_CONNECTOR_TYPE InternalConnectorType;
129 CHAR16 *ExternalDesignator;
130 MISC_PORT_CONNECTOR_TYPE ExternalConnectorType;
131 MISC_PORT_TYPE PortType;
132 } PORT_INFO_TYPE8;
133
134 //
135 // Platform Info For Type 10 - Onboard Device Information
136 //
137 #define NUM_ONBOARD_DEVICES 3
138
139 typedef enum {
140 Disabled=0,
141 Enabled
142 } DEVICE_STATUS;
143
144 typedef struct {
145 PUBLISH_REQ IsPublishRequired;
146 CHAR16 *Description;
147 MISC_ONBOARD_DEVICE_TYPE DeviceType;
148 DEVICE_STATUS DeviceStatus;
149 } ONBOARD_DEV_INFO_TYPE10;
150
151 //
152 // Platform Info For Type 12 - System Config Options
153 //
154 typedef struct {
155 CHAR16 *ConfigOptions;
156 }SYSTEM_CONFIG_TYPE12;
157
158 //
159 // Platform Info For Type 13 - BIOS Language Information
160 //
161
162 typedef enum{
163 Long=0,
164 Abbreviated
165 }LANGUAGES_FORMAT;
166
167 #define MAX_LANGUAGES 1 // TODO: it requires some investigation to update properly
168
169 typedef enum{
170 English = 1,
171 French,
172 Japanese
173 }CURRENT_LANGUAGES;
174
175 typedef struct {
176 CHAR16 *Language[MAX_LANGUAGES];
177 UINT8 InstallableLanguages;
178 LANGUAGES_FORMAT Flags;
179 CURRENT_LANGUAGES CurrentLanguage;
180 }BIOS_LANGUAGE_INFO_TYPE13;
181
182 //
183 // Platform Info For Type 22 - Portable Battery Info
184 //
185 #define NUM_PORTABLE_BATTERIES 3
186
187 typedef enum{
188 Unknown=0,
189 Real1,
190 Real2,
191 Virtual
192 }BATTERY_TYPE;
193
194 typedef struct {
195 PUBLISH_REQ IsPublishRequired;
196 BATTERY_TYPE BatteryType;
197 CHAR16 *Location;
198 CHAR16 *Manufacturer;
199 CHAR16 *ManufactureDate;
200 CHAR16 *SerialNumber;
201 CHAR16 *DevName;
202 PORTABLE_BATTERY_DEVICE_CHEMISTRY DevChemistry;
203 UINT16 DevCapacity;
204 UINT16 Voltage;
205 CHAR16 *SbdsVersion;
206 UINT8 MaxErrorInBatteryData;
207 UINT16 SbdsSerialNumber;
208 UINT16 SbdsManufactureDate;
209 CHAR16 *SbdsDeviceChemistry;
210 UINT8 CapacityMultiplier;
211 UINT32 Oem;
212 } PORTABLE_BATTERY_INFO_TYPE22;
213
214 //
215 // Platform Info For Type 27 - Cooling Device Info
216 //
217
218 typedef enum{
219 CoolingDeviceTypeOther=0x1,
220 CoolingDeviceTypeUnknown,
221 CoolingDeviceTypeFan,
222 CoolingDeviceTypeCentrifugalBlower,
223 CoolingDeviceTypeChipFan,
224 CoolingDeviceTypeCabinetFan,
225 CoolingDeviceTypePowerSupplyFan,
226 CoolingDeviceTypeHeatPipe,
227 CoolingDeviceTypeIntegratedRefrigeration,
228 CoolingDeviceTypeActiveCooling=0x10,
229 CoolingDeviceTypePassiveCooling
230 }COOLING_DEVICE_TYPE;
231
232 typedef enum{
233 CoolingDeviceStatusOther=1,
234 CoolingDeviceStatusUnknown,
235 CoolingDeviceStatusOk,
236 CoolingDeviceStatusNonCritical,
237 CoolingDeviceStatusCritical,
238 CoolingDeviceStatusNonRecoverable
239 }COOLING_DEVICE_STATUS;
240
241 typedef struct {
242 PUBLISH_REQ IsPublishRequired;
243 COOLING_DEVICE_TYPE Type;
244 COOLING_DEVICE_STATUS Status;
245 UINT8 Group;
246 UINT32 Oem;
247 UINT16 Speed;
248 CHAR16 *Description;
249 } COOLING_DEVICE_INFO_TYPE27;
250
251 //
252 // Platform Info For Type 32 - Boot Info Status
253 //
254 typedef struct {
255 MISC_BOOT_INFORMATION_STATUS_DATA_TYPE BootStatus;
256 }BOOT_INFO_TYPE32;
257
258 //
259 // Platform Info For Type 39 - System Power Supply
260 //
261 typedef enum{
262 InputVoltRangeSwitchOther=1,
263 InputVoltRangeSwitchUnknown,
264 InputVoltRangeSwitchManual,
265 InputVoltRangeSwitchAutoSwitch,
266 InputVoltRangeSwitchWideRange,
267 InputVoltRangeSwitchNotApplicable,
268 InputVoltRangeSwitchNotReserved
269 }INPUT_VOLT_RANGE_SWITCH;
270
271 typedef enum{
272 PowerSupplyStatusOther=1,
273 PowerSupplyStatusUnknown,
274 PowerSupplyStatusOk,
275 PowerSupplyStatusNonCritical,
276 PowerSupplyStatusCritical
277 }POWER_SUPPLY_STATUS;
278
279 typedef enum{
280 PowerSupplyTypeOther=1,
281 PowerSupplyTypeUnknown,
282 PowerSupplyTypeLinear,
283 PowerSupplyTypeSwitching,
284 PowerSupplyTypeBattery,
285 PowerSupplyTypeUps,
286 PowerSupplyTypeConverter,
287 PowerSupplyTypeRegulator,
288 PowerSupplyTypeReserved
289 }POWER_SUPPLY_TYPE;
290
291 typedef struct {
292 UINT8 PowerUnitGroup;
293 CHAR16 *Location;
294 CHAR16 *DeviceName;
295 CHAR16 *Manufacturer;
296 CHAR16 *SerialNumber;
297 CHAR16 *AssetTagNumber;
298 CHAR16 *ModelPartNumber;
299 CHAR16 *RevisionLevel;
300 UINT16 MaxPowerCapacity;
301 SYS_POWER_SUPPLY_CHARACTERISTICS Characteristics;
302 }SYS_POWER_SUPPLY_INFO_TYPE39;
303
304 //
305 // Platform Info For Type 41 - OnBoard Device Extended Information
306 //
307
308 typedef struct {
309 PUBLISH_REQ IsPublishRequired;
310 CHAR16 *Designation;
311 ONBOARD_DEVICE_EXTENDED_INFO_TYPE DeviceType;
312 DEVICE_STATUS DeviceStatus;
313 UINT8 DeviceInstance;
314 UINT16 Segment;
315 UINT8 Bus;
316 UINT8 DevFunc;
317 } ONBOARD_DEV_EXT_INFO_TYPE41;
318
319 //
320 // OEM Type 136
321 //
322 #define NUM_OEM_TYPE_136 1
323 #define SMBIOS_TYPE_OEM_136 0x88
324
325 typedef struct {
326 SMBIOS_STRUCTURE Hdr;
327 UINT16 RawData;
328 UINT16 Zero; //terminator
329 } SMBIOS_TABLE_TYPE136;
330
331 //
332 // Smbios Platform Info table
333 //
334 typedef struct {
335 VOID *Info;
336 VOID *Strings;
337 UINTN StringCount;
338 BOOLEAN IsPoolAllocated;
339 UINTN NoOfInstances;
340 }SMBIOS_PLATFORM_INFO;
341
342
343 //
344 // Base Board info for RVP Board data
345 //
346 #define NUM_BASE_BOARDS 0x1
347 typedef struct{
348 CHAR16 *ProductName;
349 CHAR16 *Manufacturer;
350 CHAR16 *Version;
351 UINT8 FeatureFlags;
352 UINT8 BoardType;
353 CHAR16 *LocationInChassis;
354 } BASE_BOARD_INFO;
355 //
356 // Chassis info for RVP Board data
357 //
358 #define NUM_CHASSIS_INFO 0x1
359 typedef struct{
360 CHAR16 *Manufacturer;
361 UINT8 Type;
362 CHAR16 *Version;
363 UINT8 Bootup;
364 UINT8 PowerSupply;
365 UINT8 Thermal;
366 UINT8 Security;
367 UINT8 Height;
368 UINT8 NumberofPowerCords;
369 } CHASSIS_INFO;
370
371 /*
372 The SupportedPortConnectors is represented as below.
373
374 BIT0 Keyboard,
375 BIT1 Mouse,
376 BIT2 Com1,
377 BIT3 Video,
378 BIT4 Hdmi,
379 BIT5 Usb1,
380 BIT6 Usb2,
381 BIT7 Usb3,
382 BIT8 Usb4,
383 BIT9 Usb5,
384 BIT10 Usb201,
385 BIT11 Usb202,
386 BIT12 Network,
387 BIT13 Sata0,
388 BIT14 eSata4,
389 BIT15 eSata3,
390 BIT16 Sata2,
391 BIT17 Sata1,
392 BIT18 Acin,
393 BIT19 PchJtag,
394 BIT20 Port80,
395 BIT21 2X8Header,
396 BIT22 8PinHeader,
397 BIT23 HdaHdmi,
398 BIT24 Mkeyboard,
399 BIT25 Spi,
400 BIT26 LpcDocking,
401 BIT27 Sideband,
402 BIT28 LpcSlot,
403 BIT29 PchXdp,
404 BIT30 SataPower,
405 BIT31 FpHeader,
406 BIT32 AtxPower,
407 BIT33 Avmc,
408 BIT34 Battb,
409 BIT35 Batta,
410 BIT36 CpuFan,
411 BIT37 Xdp,
412 BIT38 Memory1,
413 BIT39 Memory2,
414 BIT40 FanPwr,
415 BIT41-63 Reserved
416 */
417
418 //
419 // Cooling info for RVP Board data
420 //
421 #define NUM_COOLING_DEVICES 2
422 typedef struct{
423 UINT8 Type;
424 CHAR16 *Description;
425 } COOLING_DEV;
426
427 /*
428 The SupportedOnboardDev is represented as below.
429
430 BIT0 Video,
431 BIT1 Ethernet,
432 BIT2 Sound,
433 BIT3 SataController,
434 BIT4 ScsiController,
435 BIT5 TokenRing,
436 BIT6 PataController,
437 BIT7 SasController
438
439 */
440 //
441 // OnBoard Device info for RVP Board data
442 //
443 #define NUM_ONBOARD_DEVICES_EXT 4
444 typedef struct{
445 UINT8 Seg;
446 UINT8 Bus;
447 UINT8 Dev;
448 UINT8 Func;
449 } ONBOARD_DEV_ADDR;
450
451 //
452 // Smbios Board info for RVP Board data
453 //
454 typedef struct {
455 /*System Info Type 1*/
456 CHAR16 *SystemProductName;
457 CHAR16 *SystemVersion;
458 CHAR16 *SystemFamily;
459 UINT8 SystemWakeUpType;
460 /*Base Board Info Type 2*/
461 BASE_BOARD_INFO *BaseBoard;
462 /*Chassis Info Type 3*/
463 CHASSIS_INFO *ChassisInfo;
464 /* Port Connector Info type 8 */
465 UINTN SupportedPortConnectors;
466 /*System Config Options Type 12*/
467 CHAR16 *SystemConfigOptions;
468 /*Cooling device Type 27*/
469 COOLING_DEV *CoolingDev;
470 /* Onboard Device Ext Type 41*/
471 UINT8 SupportedOnboardDev;
472 ONBOARD_DEV_ADDR *OnBoardDevAddr;
473 } SMBIOS_PLATFORM_BOARD_INFO;
474
475 //
476 // Smbios System Slot Board Info
477 //
478 #define MAX_SLOT_ENTRIES 20
479
480 typedef struct {
481 CHAR16 *SlotDesignation;
482 UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.
483 UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
484 UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.
485 UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.
486 UINT16 SlotID;
487 MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;
488 MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;
489 UINT16 SegmentGroupNum; // Valid Only for PCIe Root Ports, Others 0xFF is expected
490 UINT8 BusNum;
491 UINT8 DevNum;
492 UINT8 FuncNum;
493 BOOLEAN Isvalid;
494 } SYSTEM_SLOT_INFO;
495
496 typedef struct {
497 UINT8 Numberofentries;
498 SYSTEM_SLOT_INFO Slotinfo[MAX_SLOT_ENTRIES];
499 }SYSTEM_SLOT_ENTRY;
500
501 #endif // _SMBIOS_PLATFORM_INFO_DEFINITION_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SmmCpuSaveState.h Source File

  • Protocol
SmmCpuSaveState.h
Go to the documentation of this file.
1 /** @file
2 This file declares the SMM CPU Save State protocol, which provides the processor
3 save-state information for IA-32 and Itanium processors.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2010 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification
34 This Protocol is defined in Framework of EFI SMM Core Interface Spec
35 Version 0.91.
36 **/
37
38 #ifndef _SMM_CPU_SAVE_STATE_H_
39 #define _SMM_CPU_SAVE_STATE_H_
40
41 #define EFI_SMM_CPU_SAVE_STATE_PROTOCOL_GUID \
42 { \
43 0x1413d458, 0x4e61, 0x9531, {0x1e, 0xf2, 0xfb, 0x89, 0x39, 0xa8, 0xa0, 0xea} \
44 }
45
46 typedef struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL EFI_SMM_CPU_SAVE_STATE_PROTOCOL;
47
48 #define EFI_SMM_MIN_REV_ID_x64 0x30006
49
50 #pragma pack (1)
51
52 ///
53 /// CPU save-state strcuture for IA32 and X64.
54 ///
55 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because the
56 /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
57 /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]
58 /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for
59 /// the layout and also maintains source comaptibility for access of all fields in this
60 /// union.
61 ///
62 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
63 /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These
64 /// have been changed to use the base types defined in the UEFI Specification.
65 ///
66 typedef struct {
67 UINT8 Reserved[0x200];
68 UINT8 Reserved1[0xf8]; // fe00h
69 UINT32 SMBASE; // fef8h
70 UINT32 SMMRevId; // fefch
71 UINT16 IORestart; // ff00h
72 UINT16 AutoHALTRestart; // ff02h
73 UINT32 IEDBASE; // ff04h
74 UINT8 Reserved2[0x98]; // ff08h
75 UINT32 IOMemAddr; // ffa0h
76 UINT32 IOMisc; // ffa4h
77 UINT32 _ES;
78 UINT32 _CS;
79 UINT32 _SS;
80 UINT32 _DS;
81 UINT32 _FS;
82 UINT32 _GS;
83 UINT32 _LDTBase;
84 UINT32 _TR;
85 UINT32 _DR7;
86 UINT32 _DR6;
87 UINT32 _EAX;
88 UINT32 _ECX;
89 UINT32 _EDX;
90 UINT32 _EBX;
91 UINT32 _ESP;
92 UINT32 _EBP;
93 UINT32 _ESI;
94 UINT32 _EDI;
95 UINT32 _EIP;
96 UINT32 _EFLAGS;
97 UINT32 _CR3;
98 UINT32 _CR0;
99 } EFI_SMM_CPU_STATE32;
100
101 ///
102 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
103 /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These
104 /// have been changed to use the base types defined in the UEFI Specification.
105 ///
106 typedef struct {
107 UINT8 Reserved1[0x1d0]; // fc00h
108 UINT32 GdtBaseHiDword; // fdd0h
109 UINT32 LdtBaseHiDword; // fdd4h
110 UINT32 IdtBaseHiDword; // fdd8h
111 UINT8 Reserved2[0xc]; // fddch
112 UINT64 IO_EIP; // fde8h
113 UINT8 Reserved3[0x50]; // fdf0h
114 UINT32 _CR4; // fe40h
115 UINT8 Reserved4[0x48]; // fe44h
116 UINT32 GdtBaseLoDword; // fe8ch
117 UINT32 GdtLimit; // fe90h
118 UINT32 IdtBaseLoDword; // fe94h
119 UINT32 IdtLimit; // fe98h
120 UINT32 LdtBaseLoDword; // fe9ch
121 UINT32 LdtLimit; // fea0h
122 UINT32 LdtInfo; // fea4h
123 UINT8 Reserved5[0x50]; // fea8h
124 UINT32 SMBASE; // fef8h
125 UINT32 SMMRevId; // fefch
126 UINT16 AutoHALTRestart; // ff00h
127 UINT16 IORestart; // ff02h
128 UINT32 IEDBASE; // ff04h
129 UINT8 Reserved6[0x14]; // ff08h
130 UINT64 _R15; // ff1ch
131 UINT64 _R14;
132 UINT64 _R13;
133 UINT64 _R12;
134 UINT64 _R11;
135 UINT64 _R10;
136 UINT64 _R9;
137 UINT64 _R8;
138 UINT64 _RAX; // ff5ch
139 UINT64 _RCX;
140 UINT64 _RDX;
141 UINT64 _RBX;
142 UINT64 _RSP;
143 UINT64 _RBP;
144 UINT64 _RSI;
145 UINT64 _RDI;
146 UINT64 IOMemAddr; // ff9ch
147 UINT32 IOMisc; // ffa4h
148 UINT32 _ES; // ffa8h
149 UINT32 _CS;
150 UINT32 _SS;
151 UINT32 _DS;
152 UINT32 _FS;
153 UINT32 _GS;
154 UINT32 _LDTR; // ffc0h
155 UINT32 _TR;
156 UINT64 _DR7; // ffc8h
157 UINT64 _DR6;
158 UINT64 _RIP; // ffd8h
159 UINT64 IA32_EFER; // ffe0h
160 UINT64 _RFLAGS; // ffe8h
161 UINT64 _CR3; // fff0h
162 UINT64 _CR0; // fff8h
163 } EFI_SMM_CPU_STATE64;
164
165 ///
166 /// Union of CPU save-state strcutures for IA32 and X64.
167 ///
168 /// This union declaration does not exctly match the Framework SMM CIS 0.91 because the
169 /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
170 /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]
171 /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for
172 /// the layout and also maintains source comaptibility for access of all fields in this
173 /// union.
174 ///
175 typedef union {
176 EFI_SMM_CPU_STATE32 x86;
177 EFI_SMM_CPU_STATE64 x64;
178 } EFI_SMM_CPU_STATE;
179
180 #pragma pack ()
181
182 ///
183 /// Provides a programatic means to access SMM save state.
184 ///
185 struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL {
186 ///
187 /// Reference to a list of save states.
188 ///
189 EFI_SMM_CPU_STATE **CpuSaveState;
190 };
191
192 #endif
EFI_SMM_CPU_STATE64
This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CI...
Definition: SmmCpuSaveState.h:106
EFI_SMM_CPU_STATE32
CPU save-state strcuture for IA32 and X64.
Definition: SmmCpuSaveState.h:66
_EFI_SMM_CPU_SAVE_STATE_PROTOCOL::CpuSaveState
EFI_SMM_CPU_STATE ** CpuSaveState
Reference to a list of save states.
Definition: SmmCpuSaveState.h:189
_EFI_SMM_CPU_SAVE_STATE_PROTOCOL
Provides a programatic means to access SMM save state.
Definition: SmmCpuSaveState.h:185
EFI_SMM_CPU_STATE
Union of CPU save-state strcutures for IA32 and X64.
Definition: SmmCpuSaveState.h:175
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SmmStmConfTable.h Source File

SmmStmConfTable.h
Go to the documentation of this file.
1 /** @file
2 GUID definition for the Smm Stm Configuraion Table
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35 #ifndef _SMM_STM_CONF_TABLE_H_
36 #define _SMM_STM_CONF_TABLE_H_
37
38 #include <Protocol/SmmTxtResource.h>
39
40 ///
41 /// Definitions
42 ///
43 #define STM_OPT_OUT 0
44 #define STM_OPT_IN 1
45 #define STM_INACTIVE 0
46 #define STM_ACTIVE 2
47
48 ///
49 /// STM Configuration Table
50 ///
51 typedef struct _SMM_ENTRY_INIT_STRUCT SMM_ENTRY_INIT_STRUCT;
52
53 typedef
54 EFI_STATUS
55 (EFIAPI *STM_ADD_RESOURCE) (
56 IN VOID *ResourceList,
57 IN UINT32 NumEntries OPTIONAL,
58 IN UINT32 StartOver OPTIONAL
59 );
60
61 #pragma pack(push, 1)
62 typedef struct _STM_CONFIGURATION_TABLE {
63 UINT64 StmFlags;
64 SMM_TXT_RESOURCE_PROTOCOL *SmmTxtRscProtocol;
65 STM_ADD_RESOURCE StmAddResource;
66 } STM_CONFIGURATION_TABLE;
67 #pragma pack(pop)
68
69 #endif
SmmTxtResource.h
This file contains function definitions that can determine the TXT resource of a platform during SMM ...
SMM_ENTRY_INIT_STRUCT
struct _SMM_ENTRY_INIT_STRUCT SMM_ENTRY_INIT_STRUCT
STM Configuration Table.
Definition: SmmStmConfTable.h:51
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SmmStmConfTableLib.h Source File

  • Library
SmmStmConfTableLib.h
Go to the documentation of this file.
1 /** @file
2 Txt Protocol definition include file.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _SMM_STM_CONF_TABLE_H
35 #define _SMM_STM_CONF_TABLE_H
36
37 ///
38 /// BIOS must updated the value depends on how CPU driver designs.
39 ///
40
41 /**
42 STM library Initial Entry
43
44 @param[in] SystemTable A pointer to the EFI System Table
45
46 @retval EFI_SUCCESS If TXT initialization succeed
47 @retval EFI_UNLOAD_IMAGE If TXT criterias are not met
48 **/
49 EFI_STATUS
50 EFIAPI
51 SmmStmConfTableInit (
52 IN EFI_SYSTEM_TABLE *SystemTable
53 );
54
55 #define STS_RESOURCE_PRESENT 0
56 #define STS_CONTINUE_SEARCH 1
57 #define STS_END_OF_AREA 2
58
59 /**
60 Get Mseg Size
61
62 @retval Size Get Mseg Size
63 **/
64 UINT64
65 GetMsegSize (
66 VOID
67 );
68
69 /**
70 Fill Mseg Base/Size to TxtHobInfo
71
72 @param[in] Base Mseg base address
73 @param[in] Size Mseg Size
74
75 **/
76 VOID
77 FillMseg (
78 IN UINT32 Base,
79 IN UINT32 Size
80 );
81
82 /**
83 Fill Tseg Base/Size to TxtHobInfo
84
85 @param[in] Base Mseg base address
86 @param[in] Size Mseg Size
87
88 **/
89 VOID
90 FillTseg (
91 IN UINT32 Base,
92 IN UINT32 Size
93 );
94 #endif
95
FillTseg
VOID FillTseg(IN UINT32 Base, IN UINT32 Size)
Fill Tseg Base/Size to TxtHobInfo.
GetMsegSize
UINT64 GetMsegSize(VOID)
Get Mseg Size.
FillMseg
VOID FillMseg(IN UINT32 Base, IN UINT32 Size)
Fill Mseg Base/Size to TxtHobInfo.
SmmStmConfTableInit
EFI_STATUS SmmStmConfTableInit(IN EFI_SYSTEM_TABLE *SystemTable)
BIOS must updated the value depends on how CPU driver designs.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SmmTxtResource.h Source File

  • Protocol
SmmTxtResource.h
Go to the documentation of this file.
1 /** @file
2 This file contains function definitions that can determine
3 the TXT resource of a platform during SMM and perform
4 certain specific platform tasks that are required for TXT
5 during SMM.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 1999 - 2016 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification Reference:
36
37 **/
38 #ifndef _SMM_TXT_RESOURCE_PROTOCOL_H_
39 #define _SMM_TXT_RESOURCE_PROTOCOL_H_
40
41 ///
42 /// Resource database header
43 ///
44 #pragma pack(push, 1)
45 typedef union _RESOURCE RESOURCE;
46
47 typedef struct _RESOURCE_AREA RESOURCE_AREA;
48
49 struct _RESOURCE_AREA {
50 EFI_PHYSICAL_ADDRESS AreaAddress;
51 UINT32 AreaSize;
52 UINT32 FreeSize;
53 EFI_PHYSICAL_ADDRESS EndOfRscAddress;
54 EFI_PHYSICAL_ADDRESS FreeSpaceAddress;
55 };
56
57 #define MAX_AREAS 4
58 #define AREA_SIZE 0x1000
59 #define APPEND 0
60 #define START_OVER !0
61
62 typedef struct _STM_RESOURCE_HEADER STM_RESOURCE_HEADER;
63
64 struct _STM_RESOURCE_HEADER {
65 UINT32 NumAreas;
66 RESOURCE_AREA Area[MAX_AREAS];
67 };
68
69 ///
70 /// Resource definitions
71 ///
72 #define END_OF_RESOURCES 0
73 #define MEM_RANGE 1
74 #define IO_RANGE 2
75 #define MMIO_RANGE 3
76 #define MACHINE_SPECIFIC_REG 4
77 #define PCI_CFG_RANGE 5
78 #define TRAPPED_IO_RANGE 6
79 #define MAX_DESC_TYPE 6
80
81 #define RD_ACCS 1
82 #define WR_ACCS 2
83 #define EX_ACCS 4
84 #define RDWR_ACCS 3
85 #define FULL_ACCS 7
86
87 typedef struct {
88 UINT32 RscType;
89 UINT16 Length;
90 UINT16 ReturnStatus : 1;
91 UINT16 Res : 14;
92 UINT16 IgnoreResource : 1;
93 } STM_RSC_DESC_HEADER;
94
95 typedef struct {
96 STM_RSC_DESC_HEADER Hdr;
97 UINT64 ResourceListContinuation;
98 } STM_RSC_END;
99
100 typedef struct {
101 STM_RSC_DESC_HEADER Hdr;
102 UINT64 Base;
103 UINT64 Length;
104 UINT32 RWXAttributes;
105 UINT32 Reserved; /// must be 0
106 } STM_RSC_MEM_DESC;
107
108 typedef struct {
109 STM_RSC_DESC_HEADER Hdr;
110 UINT16 Base;
111 UINT16 Length;
112 UINT32 Reserved; /// must be 0
113 } STM_RSC_IO_DESC;
114
115 typedef struct {
116 STM_RSC_DESC_HEADER Hdr;
117 UINT64 Base;
118 UINT64 Length;
119 UINT32 RWXAttributes;
120 UINT32 Reserved; /// must be 0
121 } STM_RSC_MMIO_DESC;
122
123 #define MASK0 0
124 #define MASK64 0xFFFFFFFFFFFFFFFF
125 #define TABLE_END 0xFFFFFFFFFFFFFFFF
126
127 typedef struct {
128 STM_RSC_DESC_HEADER Hdr;
129 UINT64 MsrIndex;
130 UINT64 ReadMask;
131 UINT64 WriteMask;
132 } STM_RSC_MSR_DESC;
133
134 typedef struct {
135 UINT8 PciFunction;
136 UINT8 PciDevice;
137 } STM_PCI_DEVICE_PATH_NODE;
138
139 typedef struct {
140 STM_RSC_DESC_HEADER Hdr;
141 UINT16 RWAttributes;
142 UINT16 Base;
143 UINT16 Length;
144 UINT8 OriginatingBusNumber;
145 UINT8 LastNodeIndex;
146 UINT8 Reserved;
147 STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];
148 } STM_RSC_PCI_CFG_DESC;
149
150 typedef struct {
151 STM_RSC_DESC_HEADER Hdr;
152 UINT16 Base;
153 UINT16 Length;
154 UINT16 In : 1;
155 UINT16 Out : 1;
156 UINT16 Api : 1;
157 UINT16 Reserved1 : 13;
158 UINT16 Reserved2; /// must be 0
159 } STM_RSC_TRAPPED_IO_DESC;
160
161 union _RESOURCE {
162 STM_RSC_DESC_HEADER hdr;
163 STM_RSC_MEM_DESC mem;
164 STM_RSC_IO_DESC io;
165 STM_RSC_MMIO_DESC mmio;
166 STM_RSC_MSR_DESC msr;
167 STM_RSC_PCI_CFG_DESC pci;
168 STM_RSC_TRAPPED_IO_DESC trapio;
169 STM_RSC_END eor;
170 };
171
172 #pragma pack(pop)
173
174 typedef struct _SMM_TXT_RESOURCE_PROTOCOL SMM_TXT_RESOURCE_PROTOCOL;
175 typedef struct _STM_MAP_ADDRESS_RANGE_DESCRIPTOR STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
176 typedef struct _STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
177 typedef struct _STM_API_ADDRESS_LOOKUP_DESCRIPTOR STM_API_ADDRESS_LOOKUP_DESCRIPTOR;
178
179 ///
180 /// Member functions
181 ///
182 typedef
183 EFI_STATUS
184 (EFIAPI *STM_MAP_ADDRESS_RANGE) (
185 STM_MAP_ADDRESS_RANGE_DESCRIPTOR * Buf
186 );
187
188 typedef
189 EFI_STATUS
190 (EFIAPI *STM_UNMAP_ADDRESS_RANGE) (
191 STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR * Buf
192 );
193
194 typedef
195 EFI_STATUS
196 (EFIAPI *STM_API_ADDRESS_LOOKUP) (
197 STM_API_ADDRESS_LOOKUP_DESCRIPTOR * Buf
198 );
199
200 struct _SMM_TXT_RESOURCE_PROTOCOL {
201 STM_MAP_ADDRESS_RANGE StmMapAddressRange;
202 STM_UNMAP_ADDRESS_RANGE StmUnmapAddressRange;
203 STM_API_ADDRESS_LOOKUP StmApiAddressLookup;
204 };
205 #endif
RESOURCE
union _RESOURCE RESOURCE
Resource database header.
Definition: SmmTxtResource.h:45
STM_MAP_ADDRESS_RANGE
EFI_STATUS(* STM_MAP_ADDRESS_RANGE)(STM_MAP_ADDRESS_RANGE_DESCRIPTOR *Buf)
Member functions.
Definition: SmmTxtResource.h:184
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SmmTxtStmService.h Source File

  • Protocol
SmmTxtStmService.h
Go to the documentation of this file.
1 /** @file
2 This file contains function definitions that can determine
3 the TXT resource of a platform during SMM and perform
4 certain specific platform tasks that are required for TXT
5 during SMM.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 1999 - 2016 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification Reference:
36
37 **/
38 #ifndef _SMM_TXT_STM_PROTOCOL_H_
39 #define _SMM_TXT_STM_PROTOCOL_H_
40
41 typedef struct _SMM_TXT_STM_PROTOCOL SMM_TXT_STM_PROTOCOL;
42
43 struct _SMM_TXT_STM_PROTOCOL {
44 VOID *ResourcePtr;
45 };
46
47 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SoftwareGuardSetupData.h Source File

SoftwareGuardSetupData.h
Go to the documentation of this file.
1 /** @file
2 Software Guard Setup Variables and Structures
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _SOFTWARE_GUARD_SETUP_DATA_H_
36 #define _SOFTWARE_GUARD_SETUP_DATA_H_
37
38 #define EPC_BIOS L"EPCBIOS"
39 #define EPC_OS_CTRL L"EPCSW"
40 #define SGX_POLICY L"SOFTWAREGUARDSTATUS"
41
42 #pragma pack(1)
43
44 ///
45 /// EPC data structure for OS Variable
46 ///
47 typedef struct {
48 UINT32 RequestedEpcSize; ///< Requested EPC size in MB
49 } EPC_OS_CONFIG;
50
51 ///
52 /// EPC data structure for BIOS Variable
53 ///
54 typedef struct _EPC_BIOS_CONFIG {
55 UINT32 SupportedPrmBins; ///< supported EPC bins; Bit 0- Support for 1 MB, 1- Support for 2 MB, 2- Support for 4 MB,
56 UINT32 MaxEpcSize; ///< Maximum EPC size supported by platform in MB
57 UINT32 AllocatedEpcSize; ///< Allocated EPC size in MB
58 UINT32 EpcMap[32]; ///< Mapping of PRM size to corresponding EPC size
59 } EPC_BIOS_CONFIG;
60
61 ///
62 /// Data structure for SGX Policy Status
63 /// The presence of this variable implies that SGX is supported
64 /// For backward compatibility:
65 /// Absence of this variable implies that SGX is supported and defaulted to 'Software Controlled'
66 ///
67 typedef struct {
68 /**
69 Bitmap of SGX Policy setting
70 - BIT[1:0]: SgxStatus
71 - 00b = Disabled.
72 - 01b = Enabled.
73 - 10b = Software Controlled.
74 - 11b = Reserved.
75 **/
76 UINT8 SgxStatus:2;
77 UINT8 Reserved:6; ///< Reserved 6 bits
78 } SOFTWARE_GUARD_STATUS;
79
80 #pragma pack()
81
82 #endif
EPC_OS_CONFIG::RequestedEpcSize
UINT32 RequestedEpcSize
Requested EPC size in MB.
Definition: SoftwareGuardSetupData.h:48
EPC_OS_CONFIG
EPC data structure for OS Variable.
Definition: SoftwareGuardSetupData.h:47
_EPC_BIOS_CONFIG
EPC data structure for BIOS Variable.
Definition: SoftwareGuardSetupData.h:54
EPC_BIOS_CONFIG
struct _EPC_BIOS_CONFIG EPC_BIOS_CONFIG
EPC data structure for BIOS Variable.
_EPC_BIOS_CONFIG::EpcMap
UINT32 EpcMap[32]
Mapping of PRM size to corresponding EPC size.
Definition: SoftwareGuardSetupData.h:58
_EPC_BIOS_CONFIG::AllocatedEpcSize
UINT32 AllocatedEpcSize
Allocated EPC size in MB.
Definition: SoftwareGuardSetupData.h:57
_EPC_BIOS_CONFIG::SupportedPrmBins
UINT32 SupportedPrmBins
supported EPC bins; Bit 0- Support for 1 MB, 1- Support for 2 MB, 2- Support for 4 MB...
Definition: SoftwareGuardSetupData.h:55
SOFTWARE_GUARD_STATUS
Data structure for SGX Policy Status The presence of this variable implies that SGX is supported For ...
Definition: SoftwareGuardSetupData.h:67
_EPC_BIOS_CONFIG::MaxEpcSize
UINT32 MaxEpcSize
Maximum EPC size supported by platform in MB.
Definition: SoftwareGuardSetupData.h:56
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SpiFlashCommon.h Source File

  • Library
SpiFlashCommon.h
Go to the documentation of this file.
1 /** @file
2 The header file includes the common header files, defines
3 internal structure and functions used by SpiFlashCommonLib.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2010 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef __SPI_FLASH_COMMON_H__
37 #define __SPI_FLASH_COMMON_H__
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/PcdLib.h>
42 #include <Library/DebugLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/MemoryAllocationLib.h>
45 #include <Library/UefiDriverEntryPoint.h>
46 #include <Library/UefiBootServicesTableLib.h>
47 #include <Protocol/Spi.h>
48
49 #define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
50 /**
51 Enable block protection on the Serial Flash device.
52
53 @retval EFI_SUCCESS Opertion is successful.
54 @retval EFI_DEVICE_ERROR If there is any device errors.
55
56 **/
57 EFI_STATUS
58 EFIAPI
59 SpiFlashLock (
60 VOID
61 );
62
63 /**
64 Read NumBytes bytes of data from the address specified by
65 PAddress into Buffer.
66
67 @param[in] Address The starting physical address of the read.
68 @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
69 of bytes actually read.
70 @param[out] Buffer The destination data buffer for the read.
71
72 @retval EFI_SUCCESS Opertion is successful.
73 @retval EFI_DEVICE_ERROR If there is any device errors.
74
75 **/
76 EFI_STATUS
77 EFIAPI
78 SpiFlashRead (
79 IN UINTN Address,
80 IN OUT UINT32 *NumBytes,
81 OUT UINT8 *Buffer
82 );
83
84 /**
85 Write NumBytes bytes of data from Buffer to the address specified by
86 PAddresss.
87
88 @param[in] Address The starting physical address of the write.
89 @param[in,out] NumBytes On input, the number of bytes to write. On output,
90 the actual number of bytes written.
91 @param[in] Buffer The source data buffer for the write.
92
93 @retval EFI_SUCCESS Opertion is successful.
94 @retval EFI_DEVICE_ERROR If there is any device errors.
95
96 **/
97 EFI_STATUS
98 EFIAPI
99 SpiFlashWrite (
100 IN UINTN Address,
101 IN OUT UINT32 *NumBytes,
102 IN UINT8 *Buffer
103 );
104
105 /**
106 Erase the block starting at Address.
107
108 @param[in] Address The starting physical address of the block to be erased.
109 This library assume that caller garantee that the PAddress
110 is at the starting address of this block.
111 @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
112 On output, the actual number of bytes erased.
113
114 @retval EFI_SUCCESS. Opertion is successful.
115 @retval EFI_DEVICE_ERROR If there is any device errors.
116
117 **/
118 EFI_STATUS
119 EFIAPI
120 SpiFlashBlockErase (
121 IN UINTN Address,
122 IN UINTN *NumBytes
123 );
124
125 #endif
SpiFlashBlockErase
EFI_STATUS SpiFlashBlockErase(IN UINTN Address, IN UINTN *NumBytes)
Erase the block starting at Address.
SpiFlashLock
EFI_STATUS SpiFlashLock(VOID)
Enable block protection on the Serial Flash device.
SpiFlashRead
EFI_STATUS SpiFlashRead(IN UINTN Address, IN OUT UINT32 *NumBytes, OUT UINT8 *Buffer)
Read NumBytes bytes of data from the address specified by PAddress into Buffer.
SpiFlashWrite
EFI_STATUS SpiFlashWrite(IN UINTN Address, IN OUT UINT32 *NumBytes, IN UINT8 *Buffer)
Write NumBytes bytes of data from Buffer to the address specified by PAddresss.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: StmDefinition.h Source File

StmDefinition.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions required to use the TXT STM
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35 #ifndef _TXT_STM_DEFINITION_H_
36 #define _TXT_STM_DEFINITION_H_
37
38 ///
39 /// MSR definitions
40 ///
41 #define MSR_PLATFORM_INFORMATION 0x000000CE
42 #define IA32_MTRR_PHYSBASE0 0x200
43 #define IA32_MTRR_PHYSMASK0 0x201
44 #define IA32_MTRR_PHYSBASE1 0x202
45 #define IA32_MTRR_PHYSMASK1 0x203
46 #define IA32_MTRR_PHYSBASE2 0x204
47 #define IA32_MTRR_PHYSMASK2 0x205
48 #define IA32_MTRR_PHYSBASE3 0x206
49 #define IA32_MTRR_PHYSMASK3 0x207
50 #define IA32_MTRR_PHYSBASE4 0x208
51 #define IA32_MTRR_PHYSMASK4 0x209
52 #define IA32_MTRR_PHYSBASE5 0x20A
53 #define IA32_MTRR_PHYSMASK5 0x20B
54 #define IA32_MTRR_PHYSBASE6 0x20C
55 #define IA32_MTRR_PHYSMASK6 0x20D
56 #define IA32_MTRR_PHYSBASE7 0x20E
57 #define IA32_MTRR_PHYSMASK7 0x20F
58 #define IA32_MTRR_PHYSBASE8 0x210
59 #define IA32_MTRR_PHYSMASK8 0x211
60 #define IA32_MTRR_PHYSBASE9 0x212
61 #define IA32_MTRR_PHYSMASK9 0x213
62
63 ///
64 /// STM Definitions
65 ///
66 ///
67 /// Errors
68 ///
69 #define SMM_SUCCESS 0
70 #define ERROR_SMM_BAD_BUFFER 0x80020001
71 #define ERROR_SMM_MODULE_NOT_FOUND 0x80020002
72 #define ERROR_SMM_MODULE_FAIL_TO_UPDATE 0x80020003
73 #define ERROR_SMM_INVALID_RSC 0x80020004
74 #define ERROR_SMM_INVALID_BUFFER_SIZE 0x80020005
75 #define ERROR_SMM_BUFFER_TOO_SHORT 0x80020006
76 #define ERROR_SMM_INVALID_LIST 0x80020007
77 #define ERROR_SMM_OUT_OF_MEMORY 0x80020008
78 #define ERROR_SMM_AFTER_INIT 0x80020009
79
80 #define ERROR_INVALID_API 0x80030001
81 #define ERROR_INVALID_PARAMETER 0x80030002
82
83 ///
84 /// API values
85 ///
86 #ifndef SW_SMI_STM_GET_BIOS_AC_STATUS_CMD
87 #define SW_SMI_STM_GET_BIOS_AC_STATUS_CMD 0x10
88 #endif
89
90 #ifndef SW_SMI_STM_UPDATE_BIOS_AC_CMD
91 #define SW_SMI_STM_UPDATE_BIOS_AC_CMD 0x11
92 #endif
93
94 #ifndef SW_SMI_STM_GET_SINIT_AC_STATUS_CMD
95 #define SW_SMI_STM_GET_SINIT_AC_STATUS_CMD 0x12
96 #endif
97
98 #ifndef SW_SMI_STM_UPDATE_SINIT_AC_CMD
99 #define SW_SMI_STM_UPDATE_SINIT_AC_CMD 0x13
100 #endif
101
102 #ifndef SW_SMI_STM_GET_STM_STATUS_CMD
103 #define SW_SMI_STM_GET_STM_STATUS_CMD 0x14
104 #endif
105
106 #ifndef SW_SMI_STM_UPDATE_STM_CMD
107 #define SW_SMI_STM_UPDATE_STM_CMD 0x15
108 #endif
109
110 #ifndef SW_SMI_STM_HANDLE_BIOS_RESOURCES_CMD
111 #define SW_SMI_STM_HANDLE_BIOS_RESOURCES_CMD 0x16
112 #endif
113
114 #ifndef SW_SMI_STM_ACCESS_RESOURCES_CMD
115 #define SW_SMI_STM_ACCESS_RESOURCES_CMD 0x17
116 #endif
117
118 #ifndef SW_SMI_STM_LOAD_STM_CMD
119 #define SW_SMI_STM_LOAD_STM_CMD 0x18
120 #endif
121
122 #ifndef SW_SMI_STM_ADD_RESOURCES_CMD
123 #define SW_SMI_STM_ADD_RESOURCES_CMD 0x19
124 #endif
125
126 #define SW_SMI_STM_ADD_RUNTIME_RESOURCES_FUNC 0
127 #define SW_SMI_STM_READ_BIOS_RESOURCES_FUNC 1
128 #define SW_SMI_STM_REPLACE_BIOS_RESOURCES_FUNC 2
129 #define APPEND 0
130 #define START_OVER !0
131
132 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Swbpe.h Source File

Swbpe.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _SWBPE_H_
36 #define _SWBPE_H_
37
38 //
39 // These values represent events types the SWBPE interface supports.
40 //
41 typedef enum {
42 SwbpeTypeUndefined = 0,
43 SwbpeTypeIoIn = 1,
44 SwbpeTypeIoOut = 2,
45 SwbpeTypeMemRead = 3,
46 SwbpeTypeMemWrite = 4,
47 SwbpeTypeIntXX = 5,
48 SwbpeTypeMax = 6
49 } SWBPE_EVENT_TYPE;
50
51 typedef enum {
52 SwbpeWidthByte = 1,
53 SwbpeWidthWord = 2,
54 SwbpeWidthDword = 4
55 } SWBPE_EVENT_DATA_WIDTH;
56
57
58 //
59 // This is the data structure the SWBPE interface uses
60 // to communicate with a debugger.
61 //
62 #pragma pack (push, 1)
63 typedef struct {
64 UINT64 EventType;
65 EFI_PHYSICAL_ADDRESS EventAddress;
66 UINT64 EventData;
67 UINT64 EventDataWidth;
68 EFI_PHYSICAL_ADDRESS DebuggerArgs;
69 EFI_STATUS DebuggerStatus;
70 } SWBPE_MAILBOX;
71 #pragma pack (pop)
72
73
74 VOID
75 SoftwareBreakpointEvent (
76 IN OUT SWBPE_MAILBOX *Mailbox
77 )
78 /*++
79
80 Routine Description:
81
82 This function generates an action that can be trapped by an debugger.
83
84 Arguments:
85
86 Mailbox - A pointer to a data structure that contains information about the event and data payload.
87
88 Returns:
89
90 EFI_SUCCESS - The function event was intercepted by the debugger and handled successfully
91 EFI_UNSUPPORTED - The function event was not intercepted by the debugger
92
93 --*/
94 ;
95
96 #endif // _SWBPE_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SysFwUpdatePlatformProtocol.h Source File

  • Protocol
SysFwUpdatePlatformProtocol.h
Go to the documentation of this file.
1 /** @file
2 Define the data structure and GUID of SysFwUpdatePlatform Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _SYSTEM_FW_UPDATE_PLATFORM_PROTOCOL_H_
36 #define _SYSTEM_FW_UPDATE_PLATFORM_PROTOCOL_H_
37
38 #pragma pack(1)
39
40 typedef struct _SYSTEM_FW_UPDATE_PLATFORM_PROTOCOL SYSTEM_FW_UPDATE_PLATFORM_PROTOCOL;
41
42 typedef struct {
43 UINT16 LoadSetupDefault :1;
44 UINT16 NeedUserConsent :1;
45 UINT16 FullFlashUpdate :1;
46 UINT16 Reserved1 :13;
47 } SYS_FW_UPDATE_POLICY;
48
49 typedef
50 VOID
51 (EFIAPI *SYSTEM_FW_UPDATE_GET_AC_STATUS)(
52 OUT BOOLEAN *IsAcPluggedIn
53 );
54
55 typedef
56 VOID
57 (EFIAPI *SYSTEM_FW_UPDATE_CHECK_BATTERY)(
58 IN UINT8 RequiredCapacity,
59 OUT BOOLEAN *IsBatteryLow
60 );
61
62 typedef
63 EFI_STATUS
64 (EFIAPI *SYSTEM_FW_UPDATE_DISABLE_POWER_BUTTON)(
65 VOID
66 );
67
68 typedef
69 EFI_STATUS
70 (EFIAPI *SYSTEM_FW_UPDATE_ENABLE_POWER_BUTTON)(
71 VOID
72 );
73
74 typedef
75 EFI_STATUS
76 (EFIAPI *SYSTEM_FW_UPDATE_GET_UPDATE_POLICY)(
77 IN SYS_FW_UPDATE_POLICY *SysFwUpdatePolicy
78 );
79
80 typedef struct _SYSTEM_FW_UPDATE_PLATFORM_PROTOCOL {
81 SYSTEM_FW_UPDATE_GET_AC_STATUS GetAcStatus;
82 SYSTEM_FW_UPDATE_CHECK_BATTERY CheckBattery;
83 SYSTEM_FW_UPDATE_DISABLE_POWER_BUTTON DisablePowerButton;
84 SYSTEM_FW_UPDATE_ENABLE_POWER_BUTTON EnablePowerButton;
85 SYSTEM_FW_UPDATE_GET_UPDATE_POLICY GetUpdatePolicy;
86 } SYSTEM_FW_UPDATE_PLATFORM_PROTOCOL;
87
88 #pragma pack()
89
90 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SystemMonitor.h Source File

  • Protocol
SystemMonitor.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SYSTEM_MONITOR_H_
35 #define _SYSTEM_MONITOR_H_
36
37
38 // Device Types
39 #define HECETA6x 0x01
40
41 // Company IDs
42 #define NATIONAL 0x01
43 #define SMSC 0x5C
44 #define ADI 0x41
45
46 //Number of Monitor Device Supported
47 #define MAX_MONITOR_DEVICE 0x03
48
49 #define EC_REG_TSR1_LSB 145
50 #define EC_REG_TSR2_LSB 147
51 #define EC_REG_TSR3_LSB 149
52 #define EC_REG_TSR4_LSB 151
53 #define EC_REG_TSR5_LSB 153
54
55 #define EC_REG_CPU_FAN_SPEED 115
56 #define EC_REG_PCH_DTS_TEMP 129
57 #define EC_REG_TS_ON_DIMM0_TEMP 133
58 #define EC_REG_TS_ON_DIMM1_TEMP 134
59
60 // Structure used to return system status
61 // NOTE:
62 // All voltages have been multiplied by 1000 so that integer data
63 // types can be used. To find the actual voltage divide the voltage
64 // data member by 1000.
65 typedef struct {
66 UINTN V1_5;
67 UINTN Vccp;
68 UINTN V3_3;
69 UINTN V5;
70 UINTN V12;
71 INT8 ProcessorTemp;
72 INT8 InternalTemp;
73 INT8 RemoteTemp;
74 UINT16 Tach1;
75 UINT16 Tach2;
76 UINT16 Tach3;
77 UINT16 Tach4;
78 UINT8 CurrentPwm1;
79 UINT8 CurrentPwm2;
80 UINT8 CurrentPwm3;
81 } EFI_SYSTEM_MONITOR_INFO;
82
83 typedef struct {
84 INT16 EC_TSR1;
85 INT16 EC_TSR2;
86 INT16 EC_TSR3;
87 INT16 EC_TSR4;
88 INT16 EC_TSR5;
89 INT16 EC_TSR6;
90 INT16 EC_TSR7;
91 INT16 EC_TSR8;
92
93 INT16 CPUFanSpeed;
94 INT8 PCHDTSTemp;
95 INT8 TSonDimm0Temp;
96 INT8 TSonDimm1Temp;
97 } MOBILE_SYSTEM_MONITOR_INFO;
98
99 typedef struct {
100 UINT8 MonitorDeviceType;
101 UINT8 CompanyId;
102 UINT8 DeviceVersion;
103 UINT8 DeviceRevision;
104 UINT8 DeviceSmbusAddress;
105 } EFI_MONITOR_DEVICE_INFO;
106
107 // Protocol function prototypes
108 typedef
109 EFI_STATUS
110 (EFIAPI *EFI_GET_SYSTEM_MONITOR_VALUES) (
111 IN UINT8 DeviceSmbusAddress,
112 IN UINT16 KeyValue,
113 OUT EFI_SYSTEM_MONITOR_INFO* MonitorValues
114 );
115
116 typedef
117 EFI_STATUS
118 (EFIAPI *EFI_ACCURATE_TACH_SETTINGS) (
119 IN UINT8 DeviceSmbusAddress,
120 IN BOOLEAN EnablePws
121 );
122
123 // Protocol Definition
124 typedef struct {
125 UINT8 DeviceCount;
126 EFI_MONITOR_DEVICE_INFO DeviceInfoList[MAX_MONITOR_DEVICE];
127 EFI_GET_SYSTEM_MONITOR_VALUES GetMonitorValues;
128 EFI_ACCURATE_TACH_SETTINGS AccurateTachSettings;
129 } EFI_SYSTEM_MONITOR_PROTOCOL;
130
131 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: SystemNvDataGuid.h Source File

  • Guid
SystemNvDataGuid.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _SYSTEM_NV_DATA_GUID_H_
36 #define _SYSTEM_NV_DATA_GUID_H_
37
38
39 typedef struct {
40 EFI_GUID SystemNvDataHobGuid;
41 EFI_GUID SystemNvDataFvGuid;
42 EFI_LBA StartLba;
43 UINTN StartLbaOffset;
44 EFI_LBA EndLba;
45 UINTN EndLbaOffset;
46 UINT32 DataTypeSignature;
47 } NV_SYSTEM_DATA_GUID_TYPE;
48
49 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TbtPolicyInitDxe.c Source File

  • PlatformInit
  • PolicyInitDxe
TbtPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for TBT DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "TbtPolicyInitDxe.h"
35
36
37 //
38 // Function implementations
39 //
40
41 /**
42 Initialize TBT DXE Policy
43
44 @param[in] ImageHandle Image handle of this driver.
45
46 @retval EFI_SUCCESS Initialization complete.
47 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
48 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
49 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
50 **/
51 EFI_STATUS
52 EFIAPI
53 TbtPolicyInitDxe (
54 IN EFI_HANDLE ImageHandle
55 )
56 {
57 EFI_STATUS Status;
58 TBT_POLICY_PROTOCOL *TbtPolicy;
59
60 //
61 // Call CreateTbtDxeConfigBlocks to create & initialize platform policy structure
62 // and get all Intel default policy settings.
63 //
64 Status = CreateTbtDxeConfigBlocks(&TbtPolicy);
65 DEBUG((DEBUG_INFO, "TbtPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", TbtPolicy->TableHeader.NumberOfBlocks));
66 ASSERT_EFI_ERROR(Status);
67
68 if (mFirmwareConfiguration != FwConfigDefault) {
69
70 UpdateDxeTbtPolicy (TbtPolicy);
71 }
72
73 //
74 // Install TbtInstallPolicyProtocol.
75 // While installed, RC assumes the Policy is ready and finalized. So please
76 // update and override any setting before calling this function.
77 //
78 Status = TbtInstallPolicyProtocol (ImageHandle, TbtPolicy);
79 ASSERT_EFI_ERROR (Status);
80
81 return Status;
82 }
UpdateDxeTbtPolicy
EFI_STATUS UpdateDxeTbtPolicy(IN OUT TBT_POLICY_PROTOCOL *TbtPolicy)
Get data for platform policy from setup options.
TbtPolicyInitDxe
EFI_STATUS TbtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize TBT DXE Policy.
Definition: TbtPolicyInitDxe.c:53
TbtPolicyInitDxe.h
Header file for the TbtPolicyInitDxe Driver.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TbtPolicyInitDxe.h Source File

  • PlatformInit
  • PolicyInitDxe
TbtPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the TbtPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _TBT_POLICY_INIT_DXE_H_
35 #define _TBT_POLICY_INIT_DXE_H_
36
37 #include <Library/BaseMemoryLib.h>
38 #include <Library/MemoryAllocationLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42 #include <Protocol/TbtPolicy.h>
43 #include <Library/DxeTbtPolicyLib.h>
44 #include <Library/DxeTbtPolicyUpdateLib.h>
45
46 extern UINT8 mFirmwareConfiguration;
47
48 /**
49 <b>TBT DXE Policy Driver Entry Point</b> \n
50 - <b>Introduction</b> \n
51 TBT DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
52 Platform policy Protocol is initialized with default settings in this funciton.
53 This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
54
55 - @pre
56 - Runtime variable service should be ready if policy initialization required.
57
58 - @result
59 TBT_POLICY_PROTOCOL will be installed successfully and ready for TBT reference code use.
60
61 - <b>Porting Recommendations</b> \n
62 Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
63
64 @param[in] ImageHandle - Image handle of this driver.
65
66 @retval EFI_SUCCESS Initialization complete.
67 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
68 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
69 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
70 **/
71 EFI_STATUS
72 EFIAPI
73 TbtPolicyInitDxe (
74 IN EFI_HANDLE ImageHandle
75 );
76
77 #endif
TbtPolicyInitDxe
EFI_STATUS TbtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
TBT DXE Policy Driver Entry Point
Definition: TbtPolicyInitDxe.c:53
DxeTbtPolicyUpdateLib.h
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Tcg2ConfigHii.h Source File

  • Guid
Tcg2ConfigHii.h
Go to the documentation of this file.
1 /** @file
2 GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __TCG2_CONFIG_HII_GUID_H__
36 #define __TCG2_CONFIG_HII_GUID_H__
37
38 #define TCG2_CONFIG_FORM_SET_GUID \
39 { \
40 0x6339d487, 0x26ba, 0x424b, { 0x9a, 0x5d, 0x68, 0x7e, 0x25, 0xd7, 0x40, 0xbc } \
41 }
42
43 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Tcg2ConfigNvData.h Source File

Tcg2ConfigNvData.h
Go to the documentation of this file.
1 /** @file
2 Header file for NV data structure definition.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __TCG2_CONFIG_NV_DATA_H__
36 #define __TCG2_CONFIG_NV_DATA_H__
37
38 #include <Guid/HiiPlatformSetupFormset.h>
39 #include <Guid/Tcg2ConfigHii.h>
40 #include <IndustryStandard/TcgPhysicalPresence.h>
41 #include <Guid/PttInstance.h>
42 #include <Guid/PttPTPInstanceGuid.h>
43 //
44 // BUGBUG: In order to pass VfrCompiler, we have to redefine below MACRO, which already in <Protocol/Tcg2Protocol.h>.
45 //
46 //#ifndef __TCG2_H__
47 //#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 0x00000001
48 //#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002
49 //#endif
50 #define EFI_TCG2_EVENT_LOG_FORMAT_ALL (EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 | EFI_TCG2_EVENT_LOG_FORMAT_TCG_2)
51
52 #define TCG2_CONFIGURATION_VARSTORE_ID 0x0002
53 #define TCG2_CONFIGURATION_FORM_ID 0x0001
54
55 #define KEY_TPM_DEVICE 0x2000
56 #define KEY_TPM2_OPERATION 0x2001
57 #define KEY_TPM2_OPERATION_PARAMETER 0x2002
58 #define KEY_TPM2_PCR_BANKS_REQUEST_0 0x2003
59 #define KEY_TPM2_PCR_BANKS_REQUEST_1 0x2004
60 #define KEY_TPM2_PCR_BANKS_REQUEST_2 0x2005
61 #define KEY_TPM2_PCR_BANKS_REQUEST_3 0x2006
62 #define KEY_TPM2_PCR_BANKS_REQUEST_4 0x2007
63
64 #define TPM_DEVICE_NULL 0
65 #define TPM_DEVICE_1_2 1
66 #define TPM_DEVICE_2_0_DTPM 2
67 #define TPM_DEVICE_PTT 3
68 #define TPM_DEVICE_MIN TPM_DEVICE_1_2
69 #define TPM_DEVICE_MAX TPM_DEVICE_PTT
70 #define TPM_DEVICE_DEFAULT TPM_DEVICE_2_0_DTPM
71
72 #define TCG2_PROTOCOL_VERSION_DEFAULT 0x0001
73 #define EFI_TCG2_EVENT_LOG_FORMAT_DEFAULT EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2
74
75 //
76 // Nv Data structure referenced by IFR, TPM device user desired
77 //
78 typedef struct {
79 UINT8 TpmDevice;
80 } TCG2_CONFIGURATION;
81
82 //
83 // Variable saved for S3, TPM detected, only valid in S3 path.
84 // This variable is ReadOnly.
85 //
86 typedef struct {
87 UINT8 TpmDeviceDetected;
88 } TCG2_DEVICE_DETECTION;
89
90 #define TCG2_STORAGE_NAME L"TCG2_CONFIGURATION"
91 #define TCG2_DEVICE_DETECTION_NAME L"TCG2_DEVICE_DETECTION"
92
93 #define TPM_INSTANCE_ID_LIST { \
94 {TPM_DEVICE_INTERFACE_NONE, TPM_DEVICE_NULL}, \
95 {TPM_DEVICE_INTERFACE_TPM12, TPM_DEVICE_1_2}, \
96 {TPM_DEVICE_INTERFACE_TPM20_DTPM, TPM_DEVICE_2_0_DTPM}, \
97 {TPM_DEVICE_INTERFACE_TPM20_PTT_PTP, TPM_DEVICE_PTT}, \
98 }
99
100 //
101 // BUGBUG: In order to pass VfrCompiler, we have to redefine GUID here.
102 //
103 #ifndef __BASE_H__
104 typedef struct {
105 UINT32 Data1;
106 UINT16 Data2;
107 UINT16 Data3;
108 UINT8 Data4[8];
109 } GUID;
110 #endif
111
112 typedef struct {
113 GUID TpmInstanceGuid;
114 UINT8 TpmDevice;
115 } TPM_INSTANCE_ID;
116
117 #endif
Tcg2ConfigHii.h
GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.
PttInstance.h
GUID definition for the PTT device instance.
PttPTPInstanceGuid.h
GUID definition for the PTT device instance.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Tcg2PhysicalPresenceLib.h Source File

  • Library
Tcg2PhysicalPresenceLib.h
Go to the documentation of this file.
1 /** @file
2 Ihis library is intended to be used by BDS modules.
3 This library will execute TPM2 request.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2015 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification
34 **/
35
36 #ifndef _TCG2_PHYSICAL_PRESENCE_LIB_H_
37 #define _TCG2_PHYSICAL_PRESENCE_LIB_H_
38
39 #include <IndustryStandard/Tpm20.h>
40 #include <IndustryStandard/TcgPhysicalPresence.h>
41 #include <Protocol/Tcg2Protocol.h>
42
43 //
44 // UEFI TCG2 library definition bit of the BIOS TPM Management Flags
45 //
46 // BIT0 is reserved
47 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CLEAR BIT1
48 // BIT2 is reserved
49 #define TCG2_LIB_PP_FLAG_RESET_TRACK BIT3
50 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_ON BIT4
51 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_OFF BIT5
52 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_EPS BIT6
53 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_PCRS BIT7
54
55 //
56 // UEFI TCG2 library definition bit of the BIOS Information Flags
57 //
58 #define TCG2_BIOS_INFORMATION_FLAG_HIERACHY_CONTROL_STORAGE_DISABLE BIT8
59 #define TCG2_BIOS_INFORMATION_FLAG_HIERACHY_CONTROL_ENDORSEMENT_DISABLE BIT9
60
61 //
62 // UEFI TCG2 library definition bit of the BIOS Storage Management Flags
63 //
64 #define TCG2_BIOS_STORAGE_MANAGEMENT_FLAG_PP_REQUIRED_FOR_ENABLE_BLOCK_SID BIT16
65 #define TCG2_BIOS_STORAGE_MANAGEMENT_FLAG_PP_REQUIRED_FOR_DISABLE_BLOCK_SID BIT17
66
67 //
68 // Default value
69 //
70 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_DEFAULT (TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_OFF | \
71 TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CLEAR | \
72 TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_EPS | \
73 TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_PCRS)
74
75 /**
76 Check and execute the pending TPM request.
77
78 The TPM request may come from OS or BIOS. This API will display request information and wait
79 for user confirmation if TPM request exists. The TPM request will be sent to TPM device after
80 the TPM request is confirmed, and one or more reset may be required to make TPM request to
81 take effect.
82
83 This API should be invoked after console in and console out are all ready as they are required
84 to display request information and get user input to confirm the request.
85
86 @param PlatformAuth platform auth value. NULL means no platform auth change.
87 **/
88 VOID
89 EFIAPI
90 Tcg2PhysicalPresenceLibProcessRequest (
91 IN TPM2B_AUTH *PlatformAuth OPTIONAL
92 );
93
94 /**
95 Check if the pending TPM request needs user input to confirm.
96
97 The TPM request may come from OS. This API will check if TPM request exists and need user
98 input to confirmation.
99
100 @retval TRUE TPM needs input to confirm user physical presence.
101 @retval FALSE TPM doesn't need input to confirm user physical presence.
102
103 **/
104 BOOLEAN
105 EFIAPI
106 Tcg2PhysicalPresenceLibNeedUserConfirm (
107 VOID
108 );
109
110 /**
111 Return TPM2 ManagementFlags set by PP interface.
112
113 @retval ManagementFlags TPM2 Management Flags.
114 **/
115 UINT32
116 EFIAPI
117 Tcg2PhysicalPresenceLibGetManagementFlags (
118 VOID
119 );
120
121 /**
122 The handler for TPM physical presence function:
123 Return TPM Operation Response to OS Environment.
124
125 This API should be invoked in OS runtime phase to interface with ACPI method.
126
127 @param[out] MostRecentRequest Most recent operation request.
128 @param[out] Response Response to the most recent operation request.
129
130 @return Return Code for Return TPM Operation Response to OS Environment.
131 **/
132 UINT32
133 EFIAPI
134 Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction (
135 OUT UINT32 *MostRecentRequest,
136 OUT UINT32 *Response
137 );
138
139
140 /**
141 The handler for TPM physical presence function:
142 Submit TPM Operation Request to Pre-OS Environment and
143 Submit TPM Operation Request to Pre-OS Environment 2.
144
145 This API should be invoked in OS runtime phase to interface with ACPI method.
146
147 Caution: This function may receive untrusted input.
148
149 @param[in] OperationRequest TPM physical presence operation request.
150 @param[in] RequestParameter TPM physical presence operation request parameter.
151
152 @return Return Code for Submit TPM Operation Request to Pre-OS Environment and
153 Submit TPM Operation Request to Pre-OS Environment 2.
154 **/
155 UINT32
156 EFIAPI
157 Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction (
158 IN UINT32 OperationRequest,
159 IN UINT32 RequestParameter
160 );
161
162 /**
163 The handler for TPM physical presence function:
164 Get User Confirmation Status for Operation.
165
166 This API should be invoked in OS runtime phase to interface with ACPI method.
167
168 Caution: This function may receive untrusted input.
169
170 @param[in] OperationRequest TPM physical presence operation request.
171
172 @return Return Code for Get User Confirmation Status for Operation.
173 **/
174 UINT32
175 EFIAPI
176 Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction (
177 IN UINT32 OperationRequest
178 );
179
180 #endif
Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction
UINT32 Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction(IN UINT32 OperationRequest, IN UINT32 RequestParameter)
The handler for TPM physical presence function: Submit TPM Operation Request to Pre-OS Environment an...
Tcg2PhysicalPresenceLibGetManagementFlags
UINT32 Tcg2PhysicalPresenceLibGetManagementFlags(VOID)
Return TPM2 ManagementFlags set by PP interface.
Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction
UINT32 Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction(OUT UINT32 *MostRecentRequest, OUT UINT32 *Response)
The handler for TPM physical presence function: Return TPM Operation Response to OS Environment...
Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction
UINT32 Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction(IN UINT32 OperationRequest)
The handler for TPM physical presence function: Get User Confirmation Status for Operation.
Tcg2PhysicalPresenceLibProcessRequest
VOID Tcg2PhysicalPresenceLibProcessRequest(IN TPM2B_AUTH *PlatformAuth OPTIONAL)
Check and execute the pending TPM request.
Tcg2PhysicalPresenceLibNeedUserConfirm
BOOLEAN Tcg2PhysicalPresenceLibNeedUserConfirm(VOID)
Check if the pending TPM request needs user input to confirm.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Tcg.h Source File

  • Library
Tcg.h
Go to the documentation of this file.
1 /** @file
2 TCG defined values and structures used by the Tcg Core library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _TCG_H_
37 #define _TCG_H_
38
39 #include <Base.h>
40 #define C_ASSERT(e) typedef char __C_ASSERT__[(e)?1:-1]
41
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif
46
47 #ifdef _MSC_VER
48 #pragma warning(push)
49 #pragma warning(disable: 4200) // zero-sized array
50 #pragma warning(disable: 4201) // nameless struct/union
51 #pragma warning(disable: 4214) // bit field types other than int
52 #endif
53
54 #pragma pack(push, 1)
55
56 /// UID in host native byte order
57 typedef UINT64 TcgUid;
58
59 #define TCG_UID(b0, b1, b2, b3, b4, b5, b6, b7) (TcgUid)( \
60 (UINT64)(b0) | \
61 ((UINT64)(b1) << 8) | \
62 ((UINT64)(b2) << 16) | \
63 ((UINT64)(b3) << 24) | \
64 ((UINT64)(b4) << 32) | \
65 ((UINT64)(b5) << 40) | \
66 ((UINT64)(b6) << 48) | \
67 ((UINT64)(b7) << 56))
68
69 typedef struct _TcgComPacket {
70 UINT32 Reserved_BE;
71 UINT16 ComID_BE;
72 UINT16 ComIDExtension_BE;
73 UINT32 OutstandingData_BE;
74 UINT32 MinTransfer_BE;
75 UINT32 Length_BE;
76 UINT8 Payload[ 0 ];
77 } TcgComPacket;
78 C_ASSERT(sizeof(TcgComPacket) == 20);
79
80 typedef struct _TcgPacket {
81 UINT32 TperSessionNumber_BE;
82 UINT32 HostSessionNumber_BE;
83 UINT32 SequenceNumber_BE;
84 UINT16 Reserved_BE;
85 UINT16 AckType_BE;
86 UINT32 Acknowledgement_BE;
87 UINT32 Length_BE;
88 UINT8 Payload[ 0 ];
89 } TcgPacket;
90 C_ASSERT(sizeof(TcgPacket) == 24);
91
92 #define TCG_SUBPACKET_ALIGNMENT 4 // 4-byte alignment per spec
93 //TODO CP_Assert power of 2
94
95 typedef struct _TcgSubPacket {
96 UINT8 Reserved_BE[ 6 ];
97 UINT16 Kind_BE;
98 UINT32 Length_BE;
99 UINT8 Payload[ 0 ];
100 } TcgSubPacket;
101 C_ASSERT(sizeof(TcgSubPacket) == 12);
102
103 #define SUBPACKET_KIND_DATA 0x0000
104 #define SUBPACKET_KIND_CREDIT_CONTROL 0x8001
105
106 #define TCG_ATOM_TYPE_INTEGER 0x0
107 #define TCG_ATOM_TYPE_BYTE 0x1
108
109 typedef struct _TcgSimpleTokenTinyAtom {
110 union {
111 UINT8 raw;
112 struct {
113 UINT8 data : 6;
114 UINT8 sign : 1;
115 UINT8 isZero : 1;
116 };
117 };
118 } TcgSimpleTokenTinyAtom;
119 C_ASSERT(sizeof(TcgSimpleTokenTinyAtom) == 1);
120
121 typedef struct _TcgSimpleTokenShortAtom {
122 union {
123 UINT8 rawHeader;
124 struct {
125 UINT8 length : 4;
126 UINT8 signOrCont : 1;
127 UINT8 byteOrInt : 1;
128 UINT8 isZero : 1;
129 UINT8 isOne : 1;
130 };
131 };
132 } TcgSimpleTokenShortAtom;
133 C_ASSERT(sizeof(TcgSimpleTokenShortAtom) == 1);
134
135 #define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT 8
136 #define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK 0x7
137
138 typedef struct _TcgSimpleTokenMediumAtom {
139 union {
140 UINT16 rawHeader;
141 struct {
142 UINT8 lengthHigh : 3;
143 UINT8 signOrCont : 1;
144 UINT8 byteOrInt : 1;
145 UINT8 isZero : 1;
146 UINT8 isOne1 : 1;
147 UINT8 isOne2 : 1;
148 UINT8 lengthLow;
149 };
150 };
151 } TcgSimpleTokenMediumAtom;
152 C_ASSERT(sizeof(TcgSimpleTokenMediumAtom) == 2);
153
154 #define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT 16
155 #define TCG_LONG_ATOM_LENGTH_MID_SHIFT 8
156
157 typedef struct _TcgSimpleTokenLongAtom {
158 union {
159 UINT32 rawHeader;
160 struct {
161 UINT8 signOrCont : 1;
162 UINT8 byteOrInt : 1;
163 UINT8 reserved : 2;
164 UINT8 isZero : 1;
165 UINT8 isOne1 : 1;
166 UINT8 isOne2 : 1;
167 UINT8 isOne3 : 1;
168 UINT8 lengthHigh;
169 UINT8 lengthMid;
170 UINT8 lengthLow;
171 };
172 };
173 } TcgSimpleTokenLongAtom;
174 C_ASSERT(sizeof(TcgSimpleTokenLongAtom) == 4);
175
176 // TCG Core Spec v2 - Table 04 - Token Types
177 typedef enum _TcgTokenType {
178 TcgTokenType_Reserved,
179 TcgTokenType_TinyAtom,
180 TcgTokenType_ShortAtom,
181 TcgTokenType_MediumAtom,
182 TcgTokenType_LongAtom,
183 TcgTokenType_StartList,
184 TcgTokenType_EndList,
185 TcgTokenType_StartName,
186 TcgTokenType_EndName,
187 TcgTokenType_Call,
188 TcgTokenType_EndOfData,
189 TcgTokenType_EndOfSession,
190 TcgTokenType_StartTransaction,
191 TcgTokenType_EndTransaction,
192 TcgTokenType_EmptyAtom,
193 } TcgTokenType;
194
195 #pragma pack(pop)
196
197 #define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE 0x0F
198 #define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE 0x0F
199 #define TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE 0x7FF
200 #define TCG_TOKEN_LONGATOM_MAX_BYTE_SIZE 0xFFFFFF
201
202 #define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE 0x3F
203 #define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE 0x1F
204 #define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE -32
205
206 // TOKEN TYPES
207 #define TCG_TOKEN_TINYATOM 0x00
208 #define TCG_TOKEN_TINYSIGNEDATOM 0x40
209 #define TCG_TOKEN_SHORTATOM 0x80
210 #define TCG_TOKEN_SHORTSIGNEDATOM 0x90
211 #define TCG_TOKEN_SHORTBYTESATOM 0xA0
212 #define TCG_TOKEN_MEDIUMATOM 0xC0
213 #define TCG_TOKEN_MEDIUMSIGNEDATOM 0xC8
214 #define TCG_TOKEN_MEDIUMBYTESATOM 0xD0
215 #define TCG_TOKEN_LONGATOM 0xE0
216 #define TCG_TOKEN_LONGSIGNEDATOM 0xE1
217 #define TCG_TOKEN_LONGBYTESATOM 0xE2
218 #define TCG_TOKEN_STARTLIST 0xF0
219 #define TCG_TOKEN_ENDLIST 0xF1
220 #define TCG_TOKEN_STARTNAME 0xF2
221 #define TCG_TOKEN_ENDNAME 0xF3
222 // 0xF4 - 0xF7 TCG Reserved
223 #define TCG_TOKEN_CALL 0xF8
224 #define TCG_TOKEN_ENDDATA 0xF9
225 #define TCG_TOKEN_ENDSESSION 0xFA
226 #define TCG_TOKEN_STARTTRANSACTION 0xFB
227 #define TCG_TOKEN_ENDTRANSACTION 0xFC
228 // 0xFD - 0xFE TCG Reserved
229 #define TCG_TOKEN_EMPTY 0xFF
230
231 // CELLBLOCK reserved Names
232 #define TCG_CELL_BLOCK_TABLE_NAME (UINT8)0x00
233 #define TCG_CELL_BLOCK_START_ROW_NAME (UINT8)0x01
234 #define TCG_CELL_BLOCK_END_ROW_NAME (UINT8)0x02
235 #define TCG_CELL_BLOCK_START_COLUMN_NAME (UINT8)0x03
236 #define TCG_CELL_BLOCK_END_COLUMN_NAME (UINT8)0x04
237
238 // METHOD STATUS CODES
239 #define TCG_METHOD_STATUS_CODE_SUCCESS 0x00
240 #define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED 0x01
241 #define TCG_METHOD_STATUS_CODE_OBSOLETE 0x02
242 #define TCG_METHOD_STATUS_CODE_SP_BUSY 0x03
243 #define TCG_METHOD_STATUS_CODE_SP_FAILED 0x04
244 #define TCG_METHOD_STATUS_CODE_SP_DISABLED 0x05
245 #define TCG_METHOD_STATUS_CODE_SP_FROZEN 0x06
246 #define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE 0x07
247 #define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT 0x08
248 #define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE 0x09
249 #define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS 0x0A
250 #define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER 0x0C
251 #define TCG_METHOD_STATUS_CODE_OBSOLETE2 0x0D
252 #define TCG_METHOD_STATUS_CODE_OBSOLETE3 0x0E
253 #define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION 0x0F
254 #define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE 0x10
255 #define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW 0x11
256 #define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT 0x12
257 #define TCG_METHOD_STATUS_CODE_FAIL 0x3F
258
259
260 // Feature Codes
261 #define TCG_FEATURE_INVALID (UINT16)0x0000
262 #define TCG_FEATURE_TPER (UINT16)0x0001
263 #define TCG_FEATURE_LOCKING (UINT16)0x0002
264 #define TCG_FEATURE_GEOMETRY_REPORTING (UINT16)0x0003
265 #define TCG_FEATURE_SINGLE_USER_MODE (UINT16)0x0201
266 #define TCG_FEATURE_DATASTORE_TABLE (UINT16)0x0202
267 #define TCG_FEATURE_OPAL_SSC_V1_0_0 (UINT16)0x0200
268 #define TCG_FEATURE_OPAL_SSC_V2_0_0 (UINT16)0x0203
269 #define TCG_FEATURE_OPAL_SSC_LITE (UINT16)0x0301
270 #define TCG_FEATURE_PYRITE_SSC (UINT16)0x0302
271
272 // ACE Expression values
273 #define TCG_ACE_EXPRESSION_AND 0x0
274 #define TCG_ACE_EXPRESSION_OR 0x1
275
276 /****************************************************************************
277 TRUSTED RECEIVE - supported security protocols list (SP_Specific = 0000h)
278 ATA 8 Rev6a Table 68 7.57.6.2
279 ****************************************************************************/
280 // Security Protocol IDs
281 #define SECURITY_PROTOCOL_INFO 0x00
282 #define OPAL_SECURITY_PROTOCOL_1 0x01
283 #define OPAL_SECURITY_PROTOCOL_2 0x02
284 #define SECURITY_PROTOCOL_TCG3 0x03
285 #define SECURITY_PROTOCOL_TCG4 0x04
286 #define SECURITY_PROTOCOL_TCG5 0x05
287 #define SECURITY_PROTOCOL_TCG6 0x06
288 #define SECURITY_PROTOCOL_CBCS 0x07
289 #define SECURITY_PROTOCOL_TAPE_DATA 0x20
290 #define SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG 0x21
291 #define SECURITY_PROTOCOL_SA_CREATION_CAPS 0x40
292 #define SECURITY_PROTOCOL_IKEV2_SCSI 0x41
293 #define SECURITY_PROTOCOL_JEDEC_UFS 0xEC
294 #define SECURITY_PROTOCOL_SDCARD_SECURITY 0xED
295 #define SECURITY_PROTOCOL_IEEE_1667 0xEE
296 #define SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS 0xEF
297
298 // Security Protocol Specific IDs
299 #define TCG_SP_SPECIFIC_PROTOCOL_LIST 0x0000
300 #define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY 0x0001
301
302 #define TCG_RESERVED_COMID 0x0000
303
304 #pragma pack(push, 1)
305 typedef struct _TCG_SUPPORTED_SECURITY_PROTOCOLS {
306 UINT8 reserved[6];
307 UINT16 listLength_BE; // 6 - 7
308 UINT8 list[504]; // 8...
309 } TCG_SUPPORTED_SECURITY_PROTOCOLS;
310 C_ASSERT(sizeof(TCG_SUPPORTED_SECURITY_PROTOCOLS) == 512);
311
312 // Level 0 Discovery
313 typedef struct _TCG_LEVEL0_DISCOVERY_HEADER {
314 UINT32 length_BE; // number of valid bytes in discovery response, not including length field
315 UINT16 verMajor_BE;
316 UINT16 verMinor_BE;
317 UINT8 reserved[8];
318 UINT8 vendorUnique[32];
319 } TCG_LEVEL0_DISCOVERY_HEADER;
320 C_ASSERT(sizeof(TCG_LEVEL0_DISCOVERY_HEADER) == 48);
321
322 typedef struct _TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER {
323 UINT16 featureCode_BE;
324 UINT8 reserved : 4;
325 UINT8 version : 4;
326 UINT8 length; // length of feature dependent data in bytes
327 } TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER;
328 C_ASSERT(sizeof(TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER) == 4);
329
330 typedef struct _TCG_LOCKING_FEATURE_DESCRIPTOR {
331 TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER header;
332 UINT8 lockingSupported : 1;
333 UINT8 lockingEnabled : 1; // means the locking security provider (SP) is enabled
334 UINT8 locked : 1; // means at least 1 locking range is enabled
335 UINT8 mediaEncryption : 1;
336 UINT8 mbrEnabled : 1;
337 UINT8 mbrDone : 1;
338 UINT8 reserved : 2;
339 UINT8 reserved5_15[11];
340 } TCG_LOCKING_FEATURE_DESCRIPTOR;
341 C_ASSERT(sizeof(TCG_LOCKING_FEATURE_DESCRIPTOR) == 16);
342
343 typedef struct _TCG_TPER_FEATURE_DESCRIPTOR {
344 TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER header;
345 UINT8 SyncSupported : 1;
346 UINT8 AsyncSupported : 1;
347 UINT8 AckNakSupported : 1;
348 UINT8 BufferMgmtSupported : 1;
349 UINT8 StreamingSupported : 1;
350 UINT8 Reserved4b5 : 1;
351 UINT8 ComIdMgmtSupported : 1;
352 UINT8 Reserved4b7 : 1;
353 UINT8 Reserved5_15[11];
354 } TCG_TPER_FEATURE_DESCRIPTOR;
355 C_ASSERT(sizeof(TCG_TPER_FEATURE_DESCRIPTOR) == 16);
356
357 #pragma pack(pop)
358
359
360 // Special Purpose UIDs
361 #define TCG_UID_NULL TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
362 #define TCG_UID_THIS_SP TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01)
363 #define TCG_UID_SMUID TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF)
364
365 // Session Manager Method UIDS
366 #define TCG_UID_SM_PROPERTIES TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01)
367 #define TCG_UID_SM_START_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02)
368 #define TCG_UID_SM_SYNC_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03)
369 #define TCG_UID_SM_START_TRUSTED_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04)
370 #define TCG_UID_SM_SYNC_TRUSTED_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05)
371 #define TCG_UID_SM_CLOSE_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
372
373 // MethodID UIDs
374 #define TCG_UID_METHOD_DELETE_SP TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01)
375 #define TCG_UID_METHOD_CREATE_TABLE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02)
376 #define TCG_UID_METHOD_DELETE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03)
377 #define TCG_UID_METHOD_CREATE_ROW TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04)
378 #define TCG_UID_METHOD_DELETE_ROW TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05)
379 #define TCG_UID_METHOD_NEXT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08)
380 #define TCG_UID_METHOD_GET_FREE_SPACE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09)
381 #define TCG_UID_METHOD_GET_FREE_ROWS TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A)
382 #define TCG_UID_METHOD_DELETE_METHOD TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B)
383 #define TCG_UID_METHOD_GET_ACL TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D)
384 #define TCG_UID_METHOD_ADD_ACE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E)
385 #define TCG_UID_METHOD_REMOVE_ACE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F)
386 #define TCG_UID_METHOD_GEN_KEY TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10)
387 #define TCG_UID_METHOD_GET_PACKAGE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12)
388 #define TCG_UID_METHOD_SET_PACKAGE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13)
389 #define TCG_UID_METHOD_GET TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16)
390 #define TCG_UID_METHOD_SET TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17)
391 #define TCG_UID_METHOD_AUTHENTICATE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C)
392 #define TCG_UID_METHOD_ISSUE_SP TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01)
393 #define TCG_UID_METHOD_GET_CLOCK TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01)
394 #define TCG_UID_METHOD_RESET_CLOCK TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02)
395 #define TCG_UID_METHOD_SET_CLOCK_HIGH TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03)
396 #define TCG_UID_METHOD_SET_LAG_HIGH TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04)
397 #define TCG_UID_METHOD_SET_CLOCK_LOW TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05)
398 #define TCG_UID_METHOD_SET_LAG_LOW TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
399 #define TCG_UID_METHOD_INCREMENT_COUNTER TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07)
400 #define TCG_UID_METHOD_RANDOM TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01)
401 #define TCG_UID_METHOD_SALT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02)
402 #define TCG_UID_METHOD_DECRYPT_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03)
403 #define TCG_UID_METHOD_DECRYPT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04)
404 #define TCG_UID_METHOD_DECRYPT_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05)
405 #define TCG_UID_METHOD_ENCRYPT_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06)
406 #define TCG_UID_METHOD_ENCRYPT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07)
407 #define TCG_UID_METHOD_ENCRYPT_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08)
408 #define TCG_UID_METHOD_HMAC_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09)
409 #define TCG_UID_METHOD_HMAC TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A)
410 #define TCG_UID_METHOD_HMAC_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B)
411 #define TCG_UID_METHOD_HASH_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C)
412 #define TCG_UID_METHOD_HASH TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D)
413 #define TCG_UID_METHOD_HASH_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E)
414 #define TCG_UID_METHOD_SIGN TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F)
415 #define TCG_UID_METHOD_VERIFY TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10)
416 #define TCG_UID_METHOD_XOR TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11)
417 #define TCG_UID_METHOD_ADD_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01)
418 #define TCG_UID_METHOD_CREATE_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02)
419 #define TCG_UID_METHOD_CLEAR_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03)
420 #define TCG_UID_METHOD_FLUSH_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04)
421
422 #ifdef _MSC_VER
423 #pragma warning(pop)
424 #endif
425
426 #ifdef __cplusplus
427 }
428 #endif
429
430 #endif // TCG_H_
TcgUid
UINT64 TcgUid
UID in host native byte order.
Definition: Tcg.h:57
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TcgCore.h Source File

  • Library
TcgCore.h
Go to the documentation of this file.
1 /** @file
2 Public API for the Tcg Core library to perform the lowest level TCG data encoding.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 /**
37 * @file
38 * TCG Core public interface header
39 */
40
41 #ifndef _TCG_CORE_H_
42 #define _TCG_CORE_H_
43
44 #include <Library/Tcg.h>
45 #ifdef __cplusplus
46 extern "C"
47 {
48 #endif
49
50 #ifdef _MSC_VER
51 #define TCG_CALL __stdcall
52 #else
53 #define TCG_CALL
54 #endif
55
56 #ifdef _MSC_VER
57 #pragma warning ( push )
58 #pragma warning(disable: 4200)
59 #endif
60
61 #pragma pack(push, 1)
62
63 /**
64 * Tcg result codes.
65 *
66 * The result code indicates if the Tcg function call was successful or not
67 */
68 typedef enum {
69 /**
70 * This is the return result upon successful completion of a Tcg function call
71 */
72 TcgResult_Success,
73
74 /**
75 * This is the return "catchall" result for the failure of a Tcg function call
76 */
77 TcgResult_Failure,
78
79 /**
80 * This is the return result if a required parameter was Null for a Tcg function call
81 */
82 TcgResult_Failure_NullPointer,
83
84 /**
85 * This is the return result if a required buffersize was 0 for a Tcg function call
86 */
87 TcgResult_Failure_ZeroSize,
88
89 /**
90 * This is the return result if a Tcg function call was executed out of order.
91 * For instance, starting a Tcg subpacket before starting its Tcg packet.
92 */
93 TcgResult_Failure_InvalidAction,
94
95 /**
96 * This is the return result if the buffersize provided is not big enough to add a requested Tcg encoded item.
97 */
98 TcgResult_Failure_BufferTooSmall,
99
100 /**
101 * This is the return result for a Tcg parse function if the end of the parsed buffer is reached, yet data is still attempted to be retrieved.
102 * For instance, attempting to retrieve another Tcg token from the buffer after it has reached the end of the Tcg subpacket payload.
103 */
104 TcgResult_Failure_EndBuffer,
105
106 /**
107 * This is the return result for a Tcg parse function if the Tcg Token item requested is not the expected type.
108 * For instance, the caller requested to receive an integer and the Tcg token was a byte sequence.
109 */
110 TcgResult_Failure_InvalidType,
111 } TcgResult;
112
113
114 /**
115 * @defgroup create Create TCG ComPacket Functions
116 *
117 * These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
118 * as defined in the TCG Storage Architecture Core Specification.
119 *
120 * @{
121 */
122
123
124 /**
125 * Structure that is used to build the Tcg ComPacket. It contains the start buffer pointer and the current position of the
126 * Tcg ComPacket, current Tcg Packet and Tcg SubPacket. This structure must be initialized
127 * by calling tcgInitTcgCreateStruct before it is used as parameter to any other Tcg function.
128 * This structure should NOT be directly modified by the client of this library.
129 *
130 * NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES
131 * INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY
132 *
133 * @sa tcgInitTcgCreateStruct
134 */
135 typedef struct _TcgCreateStruct {
136 /**
137 * Buffer allocated and freed by the client of the Tcg library.
138 * This is the buffer that shall contain the final Tcg encoded compacket.
139 */
140 void* buffer;
141
142 /**
143 * Size of the buffer provided.
144 */
145 UINT32 bufferSize;
146
147 /**
148 * Pointer to the start of the Tcg ComPacket. It should point to a location within buffer.
149 */
150 TcgComPacket* comPacket;
151
152 /**
153 * Current Tcg Packet that is being created. It should point to a location within buffer.
154 */
155 TcgPacket* curPacket;
156
157 /**
158 * Current Tcg SubPacket that is being created. It should point to a location within buffer.
159 */
160 TcgSubPacket* curSubPacket;
161
162 /**
163 * Flag used to indicate if the buffer of the structure should be filled out.
164 * This is intended to be used to support a use-case where the client of library
165 * can perform all the desired tcg calls to determine what the actual size of the final compacket will be.
166 * Then the client can allocate the required buffer size and re-run the tcg calls.
167 * THIS MAY NOT BE IMPLEMENTED... REQUIRES MORE THOUGHT BECAUSE YOU CANNOT SOLVE ISSUE FOR RECEIVE
168 */
169 BOOLEAN dryRun;
170 } TcgCreateStruct;
171
172
173 /**
174 *
175 * Required to be called before calling any other Tcg functions with the TcgCreateStruct.
176 * Initializes the packet variables to NULL. Additionally, the buffer will be memset.
177 */
178 TcgResult TCG_CALL tcgInitTcgCreateStruct(
179
180 /**
181 * [in/out] Structure to initialize
182 */
183 TcgCreateStruct* createStruct,
184
185 /**
186 * [in] Buffer allocated by client of library. It will contain the Tcg encoded packet. This cannot be null.
187 */
188 void* buffer,
189
190 /**
191 * [in] Size of buffer provided. It cannot be 0.
192 */
193 UINT32 bufferSize
194 );
195
196
197 /**
198 *
199 * Encodes the ComPacket header to the data structure.
200 */
201 TcgResult TCG_CALL tcgStartComPacket(
202 /**
203 * [in/out] Structure used to build Tcg Compacket
204 */
205 TcgCreateStruct* createStruct,
206
207 /**
208 * [in] ComID of the Tcg ComPacket.
209 */
210 UINT16 comId,
211
212 /**
213 * [in] ComID Extension of the Tcg ComPacket.
214 */
215 UINT16 comIdExtension
216 );
217
218
219 /**
220 *
221 * Starts a new ComPacket in the data structure.
222 */
223 TcgResult TCG_CALL tcgStartPacket(
224 /**
225 * [in/out] Structure used to add Tcg Packet
226 */
227 TcgCreateStruct* createStruct,
228
229 /**
230 * [in] Packet Tper session number
231 */
232 UINT32 tsn,
233
234 /**
235 * [in] Packet Host session number
236 */
237 UINT32 hsn,
238
239 /**
240 * [in] Packet Sequence Number
241 */
242 UINT32 seqNumber,
243
244 /**
245 * [in] Packet Acknowledge Type
246 */
247 UINT16 ackType,
248
249 /**
250 * [in] Packet Acknowledge
251 */
252 UINT32 ack
253 );
254
255
256 /**
257 *
258 * Starts a new SubPacket in the data structure.
259 */
260 TcgResult TCG_CALL tcgStartSubPacket(
261 /**
262 * [in/out] Structure used to start Tcg SubPacket
263 */
264 TcgCreateStruct* createStruct,
265
266 /**
267 * [in] SubPacket kind
268 */
269 UINT16 kind
270 );
271
272
273 /**
274 *
275 * Ends the current SubPacket in the data structure. This function will also perform the 4-byte padding
276 * required for Subpackets.
277 */
278 TcgResult TCG_CALL tcgEndSubPacket(
279 /**
280 * [in/out] Structure used to end the current Tcg SubPacket
281 */
282 TcgCreateStruct* createStruct
283 );
284
285
286 /**
287 *
288 * Ends the current Packet in the data structure.
289 */
290 TcgResult TCG_CALL tcgEndPacket(
291 /**
292 * [in/out] Structure used to end the current Tcg Packet
293 */
294 TcgCreateStruct* createStruct
295 );
296
297
298 /**
299 *
300 * Ends the ComPacket in the data structure and ret
301 */
302 TcgResult TCG_CALL tcgEndComPacket(
303 /**
304 * [in/out] Structure used to end the Tcg ComPacket
305 */
306 TcgCreateStruct* createStruct,
307
308 /**
309 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
310 */
311 UINT32* size
312 );
313
314
315 /**
316 * @defgroup createSubPacket Create TCG SubPacket Functions
317 *
318 * These functions encode tokens contained in a SubPacket
319 * as defined in the TCG Storage Architecture Core Specification.
320 *
321 * @{
322 */
323
324
325
326 /**
327 * @defgroup createAtom Create TCG Atom Functions
328 *
329 * These functions encode simple atom tokens contained in a SubPacket
330 * as defined in the TCG Storage Architecture Core Specification.
331 *
332 * @{
333 */
334
335 /**
336 *
337 * Adds a single raw token byte to the data structure.
338 */
339 TcgResult TCG_CALL tcgAddRawByte(
340 /**
341 * [in/out] Structure used to add the byte
342 */
343 TcgCreateStruct* createStruct,
344
345 /**
346 * [in] Byte to add
347 */
348 UINT8 byte
349 );
350
351
352 /**
353 *
354 * Adds the data parameter as a byte sequence to the data structure.
355 */
356 TcgResult TCG_CALL tcgAddByteSequence(
357 /**
358 * [in/out] Structure used to add the byte sequence
359 */
360 TcgCreateStruct* createStruct,
361
362 /**
363 * [in] Byte sequence that will be encoded and copied into data structure
364 */
365 const void* data,
366
367 /**
368 * [in] Length of data provided
369 */
370 UINT32 dataSize,
371
372 /**
373 * [in] TRUE if byte sequence is continued or
374 * FALSE if the data contains the entire byte sequence to be encoded
375 */
376 BOOLEAN continued
377 );
378
379
380 /**
381 *
382 * Adds an arbitrary-length integer to the data structure.
383 *
384 * The integer will be encoded using the shortest possible atom.
385 */
386 TcgResult TCG_CALL tcgAddInteger(
387 /**
388 * [in/out] Structure used to add the integer
389 */
390 TcgCreateStruct* createStruct,
391
392 /**
393 * [in] Integer in host byte order that will be encoded and copied into data structure
394 */
395 const void* data,
396
397 /**
398 * [in] Length in bytes of the data provided
399 */
400 UINT32 dataSize,
401
402 /**
403 * [in] TRUE if the integer is signed or FALSE if the integer is unsigned
404 */
405 BOOLEAN signedInteger
406 );
407
408
409 /**
410 *
411 * Adds an 8-bit unsigned integer to the data structure.
412 */
413 TcgResult TCG_CALL tcgAddUINT8(
414 /**
415 * [in/out] Structure used to add the integer
416 */
417 TcgCreateStruct* createStruct,
418
419 /**
420 * [in] Integer value to add
421 */
422 UINT8 value
423 );
424
425
426 /**
427 *
428 * Adds a 16-bit unsigned integer to the data structure.
429 */
430 TcgResult TCG_CALL tcgAddUINT16(
431 /**
432 * [in/out] Structure used to add the integer
433 */
434 TcgCreateStruct* createStruct,
435
436 /**
437 * [in] Integer value to add
438 */
439 UINT16 value
440 );
441
442
443 /**
444 *
445 * Adds a 32-bit unsigned integer to the data structure.
446 */
447 TcgResult TCG_CALL tcgAddUINT32(
448 /**
449 * [in/out] Structure used to add the integer
450 */
451 TcgCreateStruct* createStruct,
452
453 /**
454 * [in] Integer value to add
455 */
456 UINT32 value
457 );
458
459
460 /**
461 *
462 * Adds a 64-bit unsigned integer to the data structure.
463 */
464 TcgResult TCG_CALL tcgAddUINT64(
465 /**
466 * [in/out] Structure used to add the integer
467 */
468 TcgCreateStruct* createStruct,
469
470 /**
471 * [in] Integer value to add
472 */
473 UINT64 value
474 );
475
476
477 /**
478 *
479 * Adds a BOOLEAN to the data structure.
480 */
481 TcgResult TCG_CALL tcgAddBOOLEAN(
482 /**
483 * [in/out] Structure used to add the integer
484 */
485 TcgCreateStruct* createStruct,
486
487 /**
488 * [in] BOOLEAN value to add
489 */
490 BOOLEAN value
491 );
492
493
494 /**
495 *
496 * Adds a TcgUid to the data structure.
497 */
498 TcgResult TCG_CALL tcgAddTcgUid(
499 /**
500 * [in/out] Structure used to add the TcgUid
501 */
502 TcgCreateStruct* createStruct,
503
504 /**
505 * [in] TcgUid value to add
506 */
507 TcgUid uid
508 );
509
510
511 /** @} */ // end of atom functions
512
513
514 /**
515 * @defgroup createSequenceTokens Create TCG Sequence Token Functions
516 *
517 * These functions encode sequence tokens contained in a SubPacket
518 * as defined in the TCG Storage Architecture Core Specification.
519 *
520 * @{
521 */
522
523 /**
524 *
525 * Adds a Start List token to the data structure.
526 */
527 TcgResult TCG_CALL tcgAddStartList(
528 /**
529 * [in/out] Structure used to add the token
530 */
531 TcgCreateStruct* createStruct
532 );
533
534
535 /**
536 *
537 * Adds an End List token to the data structure.
538 */
539 TcgResult TCG_CALL tcgAddEndList(
540 /**
541 * [in/out] Structure used to add the token
542 */
543 TcgCreateStruct* createStruct
544 );
545
546
547 /**
548 *
549 * Adds a Start Name token to the data structure.
550 */
551 TcgResult TCG_CALL tcgAddStartName(
552 /**
553 * [in/out] Structure used to add the token
554 */
555 TcgCreateStruct* createStruct
556 );
557
558
559 /**
560 *
561 * Adds an End Name token to the data structure.
562 */
563 TcgResult TCG_CALL tcgAddEndName(
564 /**
565 * [in/out] Structure used to add the token
566 */
567 TcgCreateStruct* createStruct
568 );
569
570
571 /** @} */ // end of sequence token functions
572
573
574 /**
575 * @defgroup createControlTokens Create TCG Control Token Functions
576 *
577 * These functions encode sequence tokens contained in a SubPacket
578 * as defined in the TCG Storage Architecture Core Specification.
579 *
580 * @{
581 */
582
583 /**
584 *
585 * Adds a Call token to the data structure.
586 */
587 TcgResult TCG_CALL tcgAddCall(
588 /**
589 * [in/out] Structure used to add the token
590 */
591 TcgCreateStruct* createStruct
592 );
593
594
595 /**
596 *
597 * Adds an End of Data token to the data structure.
598 */
599 TcgResult TCG_CALL tcgAddEndOfData(
600 /**
601 * [in/out] Structure used to add the token
602 */
603 TcgCreateStruct* createStruct
604 );
605
606
607 /**
608 *
609 * Adds an End of Session token to the data structure.
610 */
611 TcgResult TCG_CALL tcgAddEndOfSession(
612 /**
613 * [in/out] Structure used to add the token
614 */
615 TcgCreateStruct* createStruct
616 );
617
618
619 /**
620 *
621 * Adds a Start Transaction token to the data structure.
622 */
623 TcgResult TCG_CALL tcgAddStartTransaction(
624 /**
625 * [in/out] Structure used to add the token
626 */
627 TcgCreateStruct* createStruct
628 );
629
630
631 /**
632 *
633 * Adds an End Transaction token to the data structure.
634 */
635 TcgResult TCG_CALL tcgAddEndTransaction(
636 /**
637 * [in/out] Structure used to add the token
638 */
639 TcgCreateStruct* createStruct
640 );
641
642 /** @} */ // end of control token functions
643
644 /** @} */ // end of createSubPacket functions
645
646 /** @} */ // end of create functions
647
648
649
650 /**
651 * @defgroup parse Parse TCG ComPacket Functions
652 *
653 * These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
654 * as defined in the TCG Storage Architecture Core Specification.
655 *
656 * @{
657 */
658
659
660 /**
661 * Structure that is used to parse the Tcg response received. It contains the response buffer pointer
662 * and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket being parsed.
663 * This structure must be initialized by calling tcgInitTcgParseStruct before it is used as parameter to any other Tcg parse function.
664 * This structure should NOT be directly modified by the client of this library.
665 *
666 * NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES
667 * INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY
668 *
669 * @sa tcgInitTcgParseStruct
670 */
671 typedef struct _TcgParseStruct {
672 /**
673 * Buffer allocated and freed by the client of the Tcg library.
674 * This is the buffer that contains the Tcg response to decode/parse.
675 */
676 const void* buffer;
677
678 /**
679 * Size of the buffer provided.
680 */
681 UINT32 bufferSize;
682
683 /**
684 * Pointer to the start of the Tcg ComPacket. It should point to a location within buffer.
685 */
686 const TcgComPacket* comPacket;
687
688 /**
689 * Current Tcg Packet that is being created. It should point to a location within buffer.
690 */
691 const TcgPacket* curPacket;
692
693 /**
694 * Current Tcg SubPacket that is being created. It should point to a location within buffer.
695 */
696 const TcgSubPacket* curSubPacket;
697
698 /**
699 * Current pointer within the current subpacket payload.
700 */
701 const UINT8* curPtr;
702 } TcgParseStruct;
703
704
705 /**
706 * Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.
707 */
708 typedef struct _TcgToken {
709 /**
710 * Describes the type of Tcg token the hdr start points to.
711 */
712 TcgTokenType type;
713
714 /**
715 * Pointer to the beginning of the header of the Tcg token
716 */
717 const UINT8* hdrStart;
718 } TcgToken;
719
720
721 /**
722 *
723 * Intializes the parsing structure used to parse the Tcg response. This must be called before using the
724 * parseStruct with any other function.
725 */
726 TcgResult TCG_CALL tcgInitTcgParseStruct(
727 /**
728 * [in/out] Structure used to parse received TCG response
729 */
730 TcgParseStruct* parseStruct,
731
732 /**
733 * [in] Buffer containing TCG response
734 */
735 const void* buffer,
736
737 /**
738 * [in] Size of buffer containing TCG response
739 */
740 UINT32 bufferSize
741 );
742
743
744 /**
745 *
746 * Retrieves next Tcg Token from the current subpacket payload. The first time it is called on a parse structure
747 * it starts at the first Subpacket of the first Packet.
748 */
749 TcgResult TCG_CALL tcgGetNextToken(
750 /**
751 * [in/out] Structure used to parse received TCG response
752 */
753 TcgParseStruct* parseStruct,
754
755 /**
756 * [in/out] Tcg Token that was found. Buffer was verified to guarantee the entire Token can be accessed by caller.
757 */
758 TcgToken* tcgToken
759 );
760
761
762 /**
763 * Retrieves the next TCG token from the current subpacket payload.
764 * If the token is not of the specified type, an error is returned.
765 *
766 * This function is intended for use with sequence and control tokens that have no payload,
767 * since it does not return the token contents.
768 */
769 TcgResult TCG_CALL tcgGetNextTokenType(
770 /**
771 * [in/out] Structure used to parse received TCG response
772 */
773 TcgParseStruct* parseStruct,
774
775 /**
776 * [in] Expected TCG token type
777 */
778 TcgTokenType type
779 );
780
781
782 /**
783 *
784 * Retrieves information about a simple token containing an atom.
785 */
786 TcgResult TCG_CALL tcgGetAtomInfo(
787 /**
788 * [in/out] TCG token containing simple token atom to retrieve
789 */
790 const TcgToken* tcgToken,
791
792 /**
793 * [out] Length of token header.
794 *
795 * This is the number of bytes from the start of the token up to the beginning of the data.
796 */
797 UINT32* headerLength,
798
799 /**
800 * [out] Length of data.
801 *
802 * This is the size of the byte or integer data following the token header.
803 */
804 UINT32* dataLength,
805
806 /**
807 * [out] Flag indicating whether the atom is a byte sequence (TCG_ATOM_TYPE_BYTE) or integer (TCG_ATOM_TYPE_INTEGER).
808 */
809 UINT8* byteOrInt,
810
811 /**
812 * [out] Flag indicating whether an integer atom is a signed integer or whether a byte sequence atom is continued.
813 */
814 UINT8* signOrCont
815 );
816
817
818 /**
819 *
820 * Retrieves byte sequence from the Tcg Token provided.
821 *
822 * @return NULL if failure occurs, otherwise pointer to beginning of byte sequence.
823 */
824 const UINT8* TCG_CALL tcgGetTokenByteSequence(
825 /**
826 * [in/out] Tcg Token containing byte sequence value to retrieve
827 */
828 const TcgToken* tcgToken,
829
830 /**
831 * [out] Length of the byte sequence retrieved
832 */
833 UINT32* length
834 );
835
836
837 /**
838 *
839 * Retrieves Integer value up to 64-bits in size from the Tcg Token provided.
840 */
841 TcgResult TCG_CALL tcgGetTokenUINT64(
842 /**
843 * [in/out] Tcg Token containing integer value to retrieve
844 */
845 const TcgToken* tcgToken,
846
847 /**
848 * [in/out] Integer value retrieved
849 */
850 UINT64* value
851 );
852
853
854 /**
855 *
856 * Retrieves next token in the current payload. If it is not a UINT8 then a failure is reported.
857 */
858 TcgResult TCG_CALL tcgGetNextUINT8(
859 /**
860 * [in/out] Structure used to parse received TCG response
861 */
862 TcgParseStruct* parseStruct,
863
864 /**
865 * [in/out] UINT8 value retrieved from current payload
866 */
867 UINT8* value
868 );
869
870
871 /**
872 *
873 * Retrieves next token in the current payload. If it is not a UINT16 then a failure is reported.
874 */
875 TcgResult TCG_CALL tcgGetNextUINT16(
876 /**
877 * [in/out] Structure used to parse received TCG response
878 */
879 TcgParseStruct* parseStruct,
880
881 /**
882 * [in/out] UINT16 value retrieved from current payload
883 */
884 UINT16* value
885 );
886
887
888 /**
889 *
890 * Retrieves next token in the current payload. If it not a UINT32 then a failure is reported.
891 */
892 TcgResult TCG_CALL tcgGetNextUINT32(
893 /**
894 * [in/out] Structure used to parse received TCG response
895 */
896 TcgParseStruct* parseStruct,
897
898 /**
899 * [in/out] UINT32 value retrieved from current payload
900 */
901 UINT32* value
902 );
903
904
905 /**
906 *
907 * Retrieves next token in the current payload. If it is not a UINT64 then a failure is reported.
908 */
909 TcgResult TCG_CALL tcgGetNextUINT64(
910 /**
911 * [in/out] Structure used to parse received TCG response
912 */
913 TcgParseStruct* parseStruct,
914
915 /**
916 * [in/out] UINT64 value retrieved from current payload
917 */
918 UINT64* value
919 );
920
921
922 /**
923 *
924 * Retrieves next token in the current payload. If it not a BOOLEAN then a failure is reported.
925 */
926 TcgResult TCG_CALL tcgGetNextBOOLEAN(
927 /**
928 * [in/out] Structure used to parse received TCG response
929 */
930 TcgParseStruct* parseStruct,
931
932 /**
933 * [in/out] BOOLEAN value retrieved from current payload
934 */
935 BOOLEAN* value
936 );
937
938 /**
939 *
940 * Retrieves next token in the current payload. If it is not a TcgUid then a failure is reported.
941 */
942 TcgResult TCG_CALL tcgGetNextTcgUid(
943 /**
944 * [in/out] Structure used to parse received TCG response
945 */
946 TcgParseStruct* parseStruct,
947
948 /**
949 * [out] TcgUid value retrieved from current payload
950 */
951 TcgUid* uid
952 );
953
954
955 /**
956 *
957 * Retrieves next token in the current payload. If it is not a byte sequence, then a failure is reported.
958 */
959 TcgResult TCG_CALL tcgGetNextByteSequence(
960 /**
961 * [in/out] Structure used to parse received TCG response
962 */
963 TcgParseStruct* parseStruct,
964
965 /**
966 * [out] Pointer to the beginning of the byte sequence
967 */
968 const void** data,
969
970 /**
971 * [out] Length of the retrieved byte sequence in bytes
972 */
973 UINT32* length
974 );
975
976
977 /**
978 *
979 * Retrieves next token in the current payload. If it is not a Start List token, then a failure is reported.
980 */
981 TcgResult TCG_CALL tcgGetNextStartList(
982 /**
983 * [in/out] Structure used to parse received TCG response
984 */
985 TcgParseStruct* parseStruct
986 );
987
988
989 /**
990 *
991 * Retrieves next token in the current payload. If it is not an End List token, then a failure is reported.
992 */
993 TcgResult TCG_CALL tcgGetNextEndList(
994 /**
995 * [in/out] Structure used to parse received TCG response
996 */
997 TcgParseStruct* parseStruct
998 );
999
1000
1001 /**
1002 *
1003 * Retrieves next token in the current payload. If it is not a Start Name token, then a failure is reported.
1004 */
1005 TcgResult TCG_CALL tcgGetNextStartName(
1006 /**
1007 * [in/out] Structure used to parse received TCG response
1008 */
1009 TcgParseStruct* parseStruct
1010 );
1011
1012
1013 /**
1014 *
1015 * Retrieves next token in the current payload. If it is not an End Name token, then a failure is reported.
1016 */
1017 TcgResult TCG_CALL tcgGetNextEndName(
1018 /**
1019 * [in/out] Structure used to parse received TCG response
1020 */
1021 TcgParseStruct* parseStruct
1022 );
1023
1024
1025 /**
1026 *
1027 * Retrieves next token in the current payload. If it is not a Call token, then a failure is reported.
1028 */
1029 TcgResult TCG_CALL tcgGetNextCall(
1030 /**
1031 * [in/out] Structure used to parse received TCG response
1032 */
1033 TcgParseStruct* parseStruct
1034 );
1035
1036
1037 /**
1038 *
1039 * Retrieves next token in the current payload. If it is not an End of Data token, then a failure is reported.
1040 */
1041 TcgResult TCG_CALL tcgGetNextEndOfData(
1042 /**
1043 * [in/out] Structure used to parse received TCG response
1044 */
1045 TcgParseStruct* parseStruct
1046 );
1047
1048
1049 /**
1050 *
1051 * Retrieves next token in the current payload. If it is not an End of Session token, then a failure is reported.
1052 */
1053 TcgResult TCG_CALL tcgGetNextEndOfSession(
1054 /**
1055 * [in/out] Structure used to parse received TCG response
1056 */
1057 TcgParseStruct* parseStruct
1058 );
1059
1060
1061 /**
1062 *
1063 * Retrieves next token in the current payload. If it is not a Start Transaction token, then a failure is reported.
1064 */
1065 TcgResult TCG_CALL tcgGetNextStartTransaction(
1066 /**
1067 * [in/out] Structure used to parse received TCG response
1068 */
1069 TcgParseStruct* parseStruct
1070 );
1071
1072
1073 /**
1074 *
1075 * Retrieves next token in the current payload. If it is not an End Transaction token, then a failure is reported.
1076 */
1077 TcgResult TCG_CALL tcgGetNextEndTransaction(
1078 /**
1079 * [in/out] Structure used to parse received TCG response
1080 */
1081 TcgParseStruct* parseStruct
1082 );
1083
1084 /** @} */ // end of parse functions
1085
1086
1087 #pragma pack(pop)
1088 #ifdef _MSC_VER
1089 #pragma warning(pop) // C4200 zero-sized array
1090 #endif
1091
1092 #ifdef __cplusplus
1093 }
1094 #endif
1095
1096 #endif // _TCG_CORE_H_
tcgAddTcgUid
TcgResult TCG_CALL tcgAddTcgUid(TcgCreateStruct *createStruct, TcgUid uid)
Adds a TcgUid to the data structure.
tcgAddUINT16
TcgResult TCG_CALL tcgAddUINT16(TcgCreateStruct *createStruct, UINT16 value)
Adds a 16-bit unsigned integer to the data structure.
tcgAddUINT8
TcgResult TCG_CALL tcgAddUINT8(TcgCreateStruct *createStruct, UINT8 value)
Adds an 8-bit unsigned integer to the data structure.
tcgStartSubPacket
TcgResult TCG_CALL tcgStartSubPacket(TcgCreateStruct *createStruct, UINT16 kind)
Starts a new SubPacket in the data structure.
TcgParseStruct
struct _TcgParseStruct TcgParseStruct
Structure that is used to parse the Tcg response received.
_TcgParseStruct::curPtr
const UINT8 * curPtr
Current pointer within the current subpacket payload.
Definition: TcgCore.h:701
tcgGetNextEndList
TcgResult TCG_CALL tcgGetNextEndList(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
_TcgParseStruct::curSubPacket
const TcgSubPacket * curSubPacket
Current Tcg SubPacket that is being created.
Definition: TcgCore.h:696
tcgAddByteSequence
TcgResult TCG_CALL tcgAddByteSequence(TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN continued)
Adds the data parameter as a byte sequence to the data structure.
tcgGetNextCall
TcgResult TCG_CALL tcgGetNextCall(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgGetNextUINT16
TcgResult TCG_CALL tcgGetNextUINT16(TcgParseStruct *parseStruct, UINT16 *value)
Retrieves next token in the current payload.
tcgInitTcgParseStruct
TcgResult TCG_CALL tcgInitTcgParseStruct(TcgParseStruct *parseStruct, const void *buffer, UINT32 bufferSize)
Intializes the parsing structure used to parse the Tcg response.
tcgGetNextEndOfSession
TcgResult TCG_CALL tcgGetNextEndOfSession(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
_TcgCreateStruct::bufferSize
UINT32 bufferSize
Size of the buffer provided.
Definition: TcgCore.h:145
_TcgParseStruct::bufferSize
UINT32 bufferSize
Size of the buffer provided.
Definition: TcgCore.h:681
tcgGetTokenUINT64
TcgResult TCG_CALL tcgGetTokenUINT64(const TcgToken *tcgToken, UINT64 *value)
Retrieves Integer value up to 64-bits in size from the Tcg Token provided.
TcgResult_Failure_InvalidAction
This is the return result if a Tcg function call was executed out of order.
Definition: TcgCore.h:93
tcgAddEndOfData
TcgResult TCG_CALL tcgAddEndOfData(TcgCreateStruct *createStruct)
Adds an End of Data token to the data structure.
tcgAddUINT64
TcgResult TCG_CALL tcgAddUINT64(TcgCreateStruct *createStruct, UINT64 value)
Adds a 64-bit unsigned integer to the data structure.
tcgAddStartList
TcgResult TCG_CALL tcgAddStartList(TcgCreateStruct *createStruct)
Adds a Start List token to the data structure.
tcgGetNextStartTransaction
TcgResult TCG_CALL tcgGetNextStartTransaction(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgStartComPacket
TcgResult TCG_CALL tcgStartComPacket(TcgCreateStruct *createStruct, UINT16 comId, UINT16 comIdExtension)
Encodes the ComPacket header to the data structure.
tcgEndPacket
TcgResult TCG_CALL tcgEndPacket(TcgCreateStruct *createStruct)
Ends the current Packet in the data structure.
tcgGetNextToken
TcgResult TCG_CALL tcgGetNextToken(TcgParseStruct *parseStruct, TcgToken *tcgToken)
Retrieves next Tcg Token from the current subpacket payload.
_TcgCreateStruct::curPacket
TcgPacket * curPacket
Current Tcg Packet that is being created.
Definition: TcgCore.h:155
TcgResult_Failure_ZeroSize
This is the return result if a required buffersize was 0 for a Tcg function call. ...
Definition: TcgCore.h:87
tcgEndSubPacket
TcgResult TCG_CALL tcgEndSubPacket(TcgCreateStruct *createStruct)
Ends the current SubPacket in the data structure.
tcgAddEndTransaction
TcgResult TCG_CALL tcgAddEndTransaction(TcgCreateStruct *createStruct)
Adds an End Transaction token to the data structure.
TcgResult
TcgResult
Tcg result codes.
Definition: TcgCore.h:68
tcgAddCall
TcgResult TCG_CALL tcgAddCall(TcgCreateStruct *createStruct)
Adds a Call token to the data structure.
tcgGetNextTcgUid
TcgResult TCG_CALL tcgGetNextTcgUid(TcgParseStruct *parseStruct, TcgUid *uid)
Retrieves next token in the current payload.
tcgAddInteger
TcgResult TCG_CALL tcgAddInteger(TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN signedInteger)
Adds an arbitrary-length integer to the data structure.
tcgGetNextUINT8
TcgResult TCG_CALL tcgGetNextUINT8(TcgParseStruct *parseStruct, UINT8 *value)
Retrieves next token in the current payload.
_TcgParseStruct::curPacket
const TcgPacket * curPacket
Current Tcg Packet that is being created.
Definition: TcgCore.h:691
tcgStartPacket
TcgResult TCG_CALL tcgStartPacket(TcgCreateStruct *createStruct, UINT32 tsn, UINT32 hsn, UINT32 seqNumber, UINT16 ackType, UINT32 ack)
Starts a new ComPacket in the data structure.
tcgAddStartName
TcgResult TCG_CALL tcgAddStartName(TcgCreateStruct *createStruct)
Adds a Start Name token to the data structure.
_TcgParseStruct
Structure that is used to parse the Tcg response received.
Definition: TcgCore.h:671
tcgGetNextTokenType
TcgResult TCG_CALL tcgGetNextTokenType(TcgParseStruct *parseStruct, TcgTokenType type)
Retrieves the next TCG token from the current subpacket payload.
tcgGetNextEndTransaction
TcgResult TCG_CALL tcgGetNextEndTransaction(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgAddStartTransaction
TcgResult TCG_CALL tcgAddStartTransaction(TcgCreateStruct *createStruct)
Adds a Start Transaction token to the data structure.
tcgGetNextUINT32
TcgResult TCG_CALL tcgGetNextUINT32(TcgParseStruct *parseStruct, UINT32 *value)
Retrieves next token in the current payload.
tcgGetNextStartName
TcgResult TCG_CALL tcgGetNextStartName(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
TcgToken
struct _TcgToken TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.
tcgAddEndOfSession
TcgResult TCG_CALL tcgAddEndOfSession(TcgCreateStruct *createStruct)
Adds an End of Session token to the data structure.
tcgGetTokenByteSequence
const UINT8 *TCG_CALL tcgGetTokenByteSequence(const TcgToken *tcgToken, UINT32 *length)
Retrieves byte sequence from the Tcg Token provided.
_TcgCreateStruct::dryRun
BOOLEAN dryRun
Flag used to indicate if the buffer of the structure should be filled out.
Definition: TcgCore.h:169
_TcgCreateStruct
Structure that is used to build the Tcg ComPacket.
Definition: TcgCore.h:135
_TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.
Definition: TcgCore.h:708
tcgGetNextByteSequence
TcgResult TCG_CALL tcgGetNextByteSequence(TcgParseStruct *parseStruct, const void **data, UINT32 *length)
Retrieves next token in the current payload.
TcgResult_Failure
This is the return "catchall" result for the failure of a Tcg function call.
Definition: TcgCore.h:77
_TcgCreateStruct::comPacket
TcgComPacket * comPacket
Pointer to the start of the Tcg ComPacket.
Definition: TcgCore.h:150
TcgResult_Success
This is the return result upon successful completion of a Tcg function call.
Definition: TcgCore.h:72
tcgGetNextUINT64
TcgResult TCG_CALL tcgGetNextUINT64(TcgParseStruct *parseStruct, UINT64 *value)
Retrieves next token in the current payload.
_TcgParseStruct::comPacket
const TcgComPacket * comPacket
Pointer to the start of the Tcg ComPacket.
Definition: TcgCore.h:686
tcgAddRawByte
TcgResult TCG_CALL tcgAddRawByte(TcgCreateStruct *createStruct, UINT8 byte)
Adds a single raw token byte to the data structure.
TcgResult_Failure_NullPointer
This is the return result if a required parameter was Null for a Tcg function call.
Definition: TcgCore.h:82
Tcg.h
TCG defined values and structures used by the Tcg Core library.
tcgGetNextBOOLEAN
TcgResult TCG_CALL tcgGetNextBOOLEAN(TcgParseStruct *parseStruct, BOOLEAN *value)
Retrieves next token in the current payload.
TcgResult_Failure_EndBuffer
This is the return result for a Tcg parse function if the end of the parsed buffer is reached...
Definition: TcgCore.h:104
tcgInitTcgCreateStruct
TcgResult TCG_CALL tcgInitTcgCreateStruct(TcgCreateStruct *createStruct, void *buffer, UINT32 bufferSize)
Required to be called before calling any other Tcg functions with the TcgCreateStruct.
TcgResult_Failure_BufferTooSmall
This is the return result if the buffersize provided is not big enough to add a requested Tcg encoded...
Definition: TcgCore.h:98
tcgAddEndList
TcgResult TCG_CALL tcgAddEndList(TcgCreateStruct *createStruct)
Adds an End List token to the data structure.
tcgGetAtomInfo
TcgResult TCG_CALL tcgGetAtomInfo(const TcgToken *tcgToken, UINT32 *headerLength, UINT32 *dataLength, UINT8 *byteOrInt, UINT8 *signOrCont)
Retrieves information about a simple token containing an atom.
TcgCreateStruct
struct _TcgCreateStruct TcgCreateStruct
Structure that is used to build the Tcg ComPacket.
tcgGetNextStartList
TcgResult TCG_CALL tcgGetNextStartList(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
_TcgToken::type
TcgTokenType type
Describes the type of Tcg token the hdr start points to.
Definition: TcgCore.h:712
_TcgCreateStruct::buffer
void * buffer
Buffer allocated and freed by the client of the Tcg library.
Definition: TcgCore.h:140
tcgAddEndName
TcgResult TCG_CALL tcgAddEndName(TcgCreateStruct *createStruct)
Adds an End Name token to the data structure.
_TcgToken::hdrStart
const UINT8 * hdrStart
Pointer to the beginning of the header of the Tcg token.
Definition: TcgCore.h:717
tcgGetNextEndName
TcgResult TCG_CALL tcgGetNextEndName(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
_TcgCreateStruct::curSubPacket
TcgSubPacket * curSubPacket
Current Tcg SubPacket that is being created.
Definition: TcgCore.h:160
TcgUid
UINT64 TcgUid
UID in host native byte order.
Definition: Tcg.h:57
_TcgParseStruct::buffer
const void * buffer
Buffer allocated and freed by the client of the Tcg library.
Definition: TcgCore.h:676
tcgEndComPacket
TcgResult TCG_CALL tcgEndComPacket(TcgCreateStruct *createStruct, UINT32 *size)
Ends the ComPacket in the data structure and ret.
tcgAddBOOLEAN
TcgResult TCG_CALL tcgAddBOOLEAN(TcgCreateStruct *createStruct, BOOLEAN value)
Adds a BOOLEAN to the data structure.
tcgGetNextEndOfData
TcgResult TCG_CALL tcgGetNextEndOfData(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
TcgResult_Failure_InvalidType
This is the return result for a Tcg parse function if the Tcg Token item requested is not the expecte...
Definition: TcgCore.h:110
tcgAddUINT32
TcgResult TCG_CALL tcgAddUINT32(TcgCreateStruct *createStruct, UINT32 value)
Adds a 32-bit unsigned integer to the data structure.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TcgSetup.h Source File

TcgSetup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2011 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #define TCG_SETUP_NAME L"TcgSetup"
35
36 #pragma pack(1)
37 typedef struct {
38 UINT8 dTpm12Present;
39 BOOLEAN HideTpm;
40 UINT8 TpmCurrentState;
41 BOOLEAN MorState;
42 UINT8 dTpm20Present;
43 UINT8 TpmOperation;
44 UINT8 PttPresent;
45 } TCG_SETUP;
46 #pragma pack()
47
48 #ifndef OFFSET_OF
49 #ifdef __GNUC__
50 #if __GNUC__ >= 4
51 #define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
52 #endif
53 #endif
54 #endif
55
56 #ifndef OFFSET_OF
57 #define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
58 #endif
59 #define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8 _VerifyOffset##TYPE##Field[(OFFSET_OF(TYPE, Field) == Offset) / (OFFSET_OF(TYPE, Field) == Offset)]
60
61 //
62 // If TpmSupport/MorStae isn't in this offset, build failure (0 size array or divided by 0) will be generated.
63 // Platform DSC file maps the two field to HII PCD so the offset value is critical.
64 //
65 VERIFY_OFFSET (TCG_SETUP, HideTpm, 0x1);
66 VERIFY_OFFSET (TCG_SETUP, MorState, 0x3);
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TcgUtil.h Source File

  • Library
TcgUtil.h
Go to the documentation of this file.
1 /** @file
2 Provides TCG high-level API to perform common TCG actions on a TCG data packet.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 /**
37 * @file
38 * TCG Core utility public interface header
39 */
40
41 #ifndef _TCG_UTIL_H_
42 #define _TCG_UTIL_H_
43
44 #include <Library/TcgCore.h>
45 #ifdef __cplusplus
46 extern "C"
47 {
48 #endif
49
50 #ifdef _MSC_VER
51 #pragma warning ( push )
52 #pragma warning(disable: 4200)
53 #endif
54
55 #pragma pack(push, 1)
56
57 /**
58 * @defgroup commonCreate Common Create TCG Utility Functions
59 *
60 * These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
61 * as defined in the TCG Storage Architecture Core Specification.
62 *
63 * @{
64 */
65
66 /**
67 *
68 * Adds start Method Call to the data structure using invoking id and method Id provided.
69 */
70 TcgResult TCG_CALL tcgStartMethodCall(
71 /**
72 * [in/out] Structure used to add the method call
73 */
74 TcgCreateStruct* createStruct,
75
76 /**
77 * [in] Invoking ID for the method call
78 */
79 TcgUid invokingId,
80
81 /**
82 * [in] Method ID for the method call
83 */
84 TcgUid methodId
85 );
86
87 /**
88 *
89 * Adds start parameters (STARTLIST) to the data structure.
90 */
91 TcgResult TCG_CALL tcgStartParameters(
92 /**
93 * [in/out] Structure used to add the start parameters
94 */
95 TcgCreateStruct* createStruct
96 );
97
98 /**
99 *
100 * Adds end parameters (ENDLIST) to the data structure.
101 */
102 TcgResult TCG_CALL tcgEndParameters(
103 /**
104 * [in/out] Structure used to add the end parameters
105 */
106 TcgCreateStruct* createStruct
107 );
108
109 /**
110 *
111 * Adds end method call (ENDDATA) to the data structure in addition to the method status list
112 */
113 TcgResult TCG_CALL tcgEndMethodCall(
114 /**
115 * [in/out] Structure used to add the method call
116 */
117 TcgCreateStruct* createStruct
118 );
119
120
121
122 /**
123 *
124 * Adds Start Session call to the data structure. This creates the entire ComPacket structure and
125 * returns the size of the entire compacket in the size parameter.
126 */
127 TcgResult TCG_CALL tcgCreateStartSession(
128 /**
129 * [in/out] Structure used to add the start session call
130 */
131 TcgCreateStruct* createStruct,
132
133 /**
134 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
135 */
136 UINT32* size,
137
138 /**
139 * [in] ComID for the ComPacket
140 */
141 UINT16 comId,
142
143 /**
144 * [in] Extended ComID for the ComPacket
145 */
146 UINT16 comIdExtension,
147
148 /**
149 * [in] Host Session ID
150 */
151 UINT32 hostSessionId,
152
153 /**
154 * [in] Security Provider to start session with
155 */
156 TcgUid spId,
157
158 /**
159 * [in] Write option for start session. TRUE = start session requests write access
160 */
161 BOOLEAN write,
162
163 /**
164 * [in] Length of the host challenge. Length should be 0 if hostChallenge is NULL
165 */
166 UINT32 hostChallengeLength,
167
168 /**
169 * [in] Host challenge for Host Signing Authority. If NULL, then no Host Challenge shall be sent.
170 */
171 const void* hostChallenge,
172
173 /**
174 * [in] Host Signing Authority used for start session. If NULL, then no Host Signing Authority shall be sent.
175 */
176 TcgUid HostSigningAuthority
177 );
178
179 /**
180 *
181 * Creates ComPacket with a Method call that sets the PIN column for the row specified.
182 * This assumes a start session has already been opened with the desired SP.
183 */
184 TcgResult TCG_CALL tcgCreateSetCPin(
185
186 /**
187 * [in/out] Structure used to add method call
188 */
189 TcgCreateStruct* createStruct,
190
191 /**
192 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
193 */
194 UINT32* size,
195
196 /**
197 * [in] ComID for the ComPacket
198 */
199 UINT16 comId,
200
201 /**
202 * [in] Extended ComID for the ComPacket
203 */
204 UINT16 comIdExtension,
205
206 /**
207 * [in] Tper Session ID for the Packet
208 */
209 UINT32 tperSession,
210
211 /**
212 * [in] Host Session ID for the Packet
213 */
214 UINT32 hostSession,
215
216 /**
217 * [in] UID of row of current SP to set PIN column
218 */
219 TcgUid sidRow,
220
221 /**
222 * [in] value of PIN to set
223 */
224 const void* password,
225
226 /**
227 * [in] Size of PIN
228 */
229 UINT32 passwordSize
230 );
231
232 /**
233 *
234 * Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified.
235 * This assumes a start session has already been opened with the desired SP.
236 */
237 TcgResult TCG_CALL tcgSetAuthorityEnabled(
238
239 /**
240 * [in/out] Structure used to add method call
241 */
242 TcgCreateStruct* createStruct,
243
244 /**
245 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
246 */
247 UINT32* size,
248
249 /**
250 * [in] ComID for the ComPacket
251 */
252 UINT16 comId,
253
254 /**
255 * [in] Extended ComID for the ComPacket
256 */
257 UINT16 comIdExtension,
258
259 /**
260 * [in] Tper Session ID for the Packet
261 */
262 UINT32 tperSession,
263
264 /**
265 * [in] Host Session ID for the Packet
266 */
267 UINT32 hostSession,
268
269 /**
270 * [in] Authority UID to modify the "Enabled" column for
271 */
272 TcgUid authorityUid,
273
274 /**
275 * [in] Value to set the "Enabled" column to
276 */
277 BOOLEAN enabled
278 );
279
280 /**
281 *
282 * Creates ComPacket with EndSession.
283 * This assumes a start session has already been opened.
284 */
285 TcgResult TCG_CALL tcgCreateEndSession(
286 /**
287 * [in/out] Structure used to add Endsession
288 */
289 TcgCreateStruct* createStruct,
290
291 /**
292 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
293 */
294 UINT32* size,
295
296 /**
297 * [in] ComID for the ComPacket
298 */
299 UINT16 comId,
300
301 /**
302 * [in] Extended ComID for the ComPacket
303 */
304 UINT16 comIdExtension,
305
306 /**
307 * [in] Host Session ID for the Packet
308 */
309 UINT32 hostSession,
310
311 /**
312 * [in] Tper Session ID for the Packet
313 */
314 UINT32 tpSessionId
315 );
316
317
318
319 /** @} */ // end of createCommon
320
321
322 /**
323 * @defgroup parseCommon Parse TCG ComPacket Utility Functions
324 *
325 * These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
326 * as defined in the TCG Storage Architecture Core Specification.
327 *
328 * @{
329 */
330
331 /**
332 *
333 * Retrieves human-readable token type name.
334 */
335 const char* TCG_CALL tcgTokenTypeString(
336 /**
337 * [in] Token type to retrieve
338 */
339 TcgTokenType type
340 );
341
342
343 /**
344 *
345 * Returns the method status of the current subpacket. Does not affect the current position
346 * in the ComPacket. In other words, it can be called whenever you have a valid SubPacket.
347 */
348 TcgResult TCG_CALL tcgGetMethodStatus(
349 /**
350 * [in/out] Structure used to parse received TCG response
351 */
352 const TcgParseStruct* parseStruct,
353
354 /**
355 * [in/out] Method status retrieved of the current SubPacket
356 */
357 UINT8* methodStatus
358 );
359
360
361 /**
362 * Returns a human-readable string representing a method status return code.
363 */
364 const char* TCG_CALL tcgMethodStatusString(
365 /**
366 * [in] Method status to translate to a string
367 */
368 UINT8 methodStatus
369 );
370
371
372 /**
373 * Retrieves the comID and Extended comID of the ComPacket in the Tcg response.
374 * It is intended to be used to confirm the received Tcg response is intended for user that received it.
375 */
376 TcgResult TCG_CALL tcgGetComIds(
377 /**
378 * [in] Structure used to parse received TCG response
379 */
380 const TcgParseStruct* parseStruct,
381
382 /**
383 * [in/out] comID retrieved from received ComPacket
384 */
385 UINT16* comId,
386
387 /**
388 * [in/out] Extended comID retrieved from received ComPacket
389 */
390 UINT16* comIdExtension
391 );
392
393
394 /**
395 * Checks if the ComIDs of the response match the expected values.
396 */
397 TcgResult TCG_CALL tcgCheckComIds(
398 /**
399 * [in] Structure used to parse received TCG response
400 */
401 const TcgParseStruct* parseStruct,
402
403 /**
404 * [in] Expected comID
405 */
406 UINT16 expectedComId,
407
408 /**
409 * [in] Expected extended comID
410 */
411 UINT16 expectedComIdExtension
412 );
413
414 /**
415 * Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID. If the Sync Session response
416 * parameters do not match the comID, extended ComID and host session ID then a failure is returned.
417 */
418 TcgResult TCG_CALL tcgParseSyncSession(
419 /**
420 * [in/out] Structure used to parse received TCG response, contains Sync Session response.
421 */
422 const TcgParseStruct* parseStruct,
423
424 /**
425 * [in] Expected ComID that is compared to actual ComID of response
426 */
427 UINT16 comId,
428
429 /**
430 * [in] Expected Extended ComID that is compared to actual Extended ComID of response
431 */
432 UINT16 comIdExtension,
433
434 /**
435 * [in] Expected Host Session ID that is compared to actual Host Session ID of response
436 */
437 UINT32 hostSessionId,
438
439 /**
440 * [in/out] Tper Session ID retrieved from the Sync Session response.
441 */
442 UINT32* tperSessionId
443 );
444
445
446 TcgResult TCG_CALL tcgCreateSetAce(
447 TcgCreateStruct* createStruct,
448 UINT32* size,
449 UINT16 comId,
450 UINT16 comIdExtension,
451 UINT32 tperSession,
452 UINT32 hostSession,
453 TcgUid aceRow,
454 TcgUid authority1,
455 BOOLEAN logicalOperator,
456 TcgUid authority2
457 );
458
459
460 typedef BOOLEAN(TCG_CALL* TcgLevel0EnumCallback)(
461 const TCG_LEVEL0_DISCOVERY_HEADER* discoveryHeader,
462 TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER* feature,
463 UINTN featureSize, // includes header
464 void* context
465 );
466
467 BOOLEAN TCG_CALL tcgEnumLevel0Discovery(
468 const TCG_LEVEL0_DISCOVERY_HEADER* discoveryHeader,
469 TcgLevel0EnumCallback callback,
470 void* context
471 );
472
473 const TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER* TCG_CALL tcgGetFeature(
474 const TCG_LEVEL0_DISCOVERY_HEADER* discoveryHeader,
475 UINT16 featureCode,
476 UINTN* featureSize
477 );
478
479 /**
480 *
481 * Determines if the protocol provided is part of the provided supported protocol list.
482 *
483 * @return TRUE = protocol is supported, FALSE = protocol is not supported
484 */
485 BOOLEAN TCG_CALL tcgIsProtocolSupported(
486 /**
487 * [in] Supported protocol list to investigate
488 */
489 const TCG_SUPPORTED_SECURITY_PROTOCOLS* protocolList,
490
491 /**
492 * [in] Protocol value to determine if supported
493 */
494 UINT16 protocol
495 );
496
497 /**
498 *
499 * Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response
500 *
501 * @return TRUE = Locked is set, FALSE = Locked is false
502 */
503 BOOLEAN TCG_CALL tcgIsLocked(
504
505 /**
506 * [in] Level 0 discovery response
507 */
508 const TCG_LEVEL0_DISCOVERY_HEADER* discovery
509 );
510
511 /** @} */ // end of parseCommon functions
512
513 #pragma pack(pop)
514
515 #ifdef _MSC_VER
516 #pragma warning(pop) // C4200 zero-sized array
517 #endif
518
519 #ifdef __cplusplus
520 }
521 #endif
522
523 #endif // _TCG_UTIL_H_
tcgIsLocked
BOOLEAN TCG_CALL tcgIsLocked(const TCG_LEVEL0_DISCOVERY_HEADER *discovery)
Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response.
tcgParseSyncSession
TcgResult TCG_CALL tcgParseSyncSession(const TcgParseStruct *parseStruct, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, UINT32 *tperSessionId)
Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID...
tcgCreateSetCPin
TcgResult TCG_CALL tcgCreateSetCPin(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid sidRow, const void *password, UINT32 passwordSize)
Creates ComPacket with a Method call that sets the PIN column for the row specified.
tcgGetMethodStatus
TcgResult TCG_CALL tcgGetMethodStatus(const TcgParseStruct *parseStruct, UINT8 *methodStatus)
Returns the method status of the current subpacket.
TcgResult
TcgResult
Tcg result codes.
Definition: TcgCore.h:68
_TcgParseStruct
Structure that is used to parse the Tcg response received.
Definition: TcgCore.h:671
tcgTokenTypeString
const char *TCG_CALL tcgTokenTypeString(TcgTokenType type)
Retrieves human-readable token type name.
tcgCreateEndSession
TcgResult TCG_CALL tcgCreateEndSession(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSession, UINT32 tpSessionId)
Creates ComPacket with EndSession.
_TcgCreateStruct
Structure that is used to build the Tcg ComPacket.
Definition: TcgCore.h:135
tcgIsProtocolSupported
BOOLEAN TCG_CALL tcgIsProtocolSupported(const TCG_SUPPORTED_SECURITY_PROTOCOLS *protocolList, UINT16 protocol)
Determines if the protocol provided is part of the provided supported protocol list.
tcgStartParameters
TcgResult TCG_CALL tcgStartParameters(TcgCreateStruct *createStruct)
Adds start parameters (STARTLIST) to the data structure.
tcgStartMethodCall
TcgResult TCG_CALL tcgStartMethodCall(TcgCreateStruct *createStruct, TcgUid invokingId, TcgUid methodId)
Adds start Method Call to the data structure using invoking id and method Id provided.
tcgCheckComIds
TcgResult TCG_CALL tcgCheckComIds(const TcgParseStruct *parseStruct, UINT16 expectedComId, UINT16 expectedComIdExtension)
Checks if the ComIDs of the response match the expected values.
TcgCore.h
Public API for the Tcg Core library to perform the lowest level TCG data encoding.
tcgSetAuthorityEnabled
TcgResult TCG_CALL tcgSetAuthorityEnabled(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid authorityUid, BOOLEAN enabled)
Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the v...
tcgEndParameters
TcgResult TCG_CALL tcgEndParameters(TcgCreateStruct *createStruct)
Adds end parameters (ENDLIST) to the data structure.
tcgGetComIds
TcgResult TCG_CALL tcgGetComIds(const TcgParseStruct *parseStruct, UINT16 *comId, UINT16 *comIdExtension)
Retrieves the comID and Extended comID of the ComPacket in the Tcg response.
tcgEndMethodCall
TcgResult TCG_CALL tcgEndMethodCall(TcgCreateStruct *createStruct)
Adds end method call (ENDDATA) to the data structure in addition to the method status list...
TcgUid
UINT64 TcgUid
UID in host native byte order.
Definition: Tcg.h:57
tcgCreateStartSession
TcgResult TCG_CALL tcgCreateStartSession(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, TcgUid spId, BOOLEAN write, UINT32 hostChallengeLength, const void *hostChallenge, TcgUid HostSigningAuthority)
Adds Start Session call to the data structure.
tcgMethodStatusString
const char *TCG_CALL tcgMethodStatusString(UINT8 methodStatus)
Returns a human-readable string representing a method status return code.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TcoWdtHob.h Source File

  • Guid
TcoWdtHob.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __TCO_WDT_HOB_H__
35 #define __TCO_WDT_HOB_H__
36
37 #define TCO_WDT_HOB_GUID \
38 { \
39 0x3e405418, 0xd8c, 0x4f1a, { 0xb0, 0x55, 0xbe, 0xf9, 0x8, 0x41, 0x46, 0x8d } \
40 }
41
42 #ifndef _PEI_HOB_H_
43 #ifndef __HOB__H__
44 #ifndef __PI_HOB_H__
45 typedef struct _EFI_HOB_GENERIC_HEADER {
46 UINT16 HobType;
47 UINT16 HobLength;
48 UINT32 Reserved;
49 } EFI_HOB_GENERIC_HEADER;
50
51 typedef struct _EFI_HOB_GUID_TYPE {
52 EFI_HOB_GENERIC_HEADER Header;
53 EFI_GUID Name;
54 //
55 // Guid specific data goes here
56 //
57 } EFI_HOB_GUID_TYPE;
58 #endif
59 #endif
60 #endif
61
62 typedef struct {
63 EFI_HOB_GUID_TYPE Header;
64 UINT8 TcoRebootHappened;
65 } TCO_WDT_HOB;
66
67 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TxtOneTouch.h Source File

  • Guid
TxtOneTouch.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions required for One-Touch function.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _TXT_ONE_TOUCH_H_
36 #define _TXT_ONE_TOUCH_H_
37
38 //
39 // Operation
40 //
41 #define ENABLE_VT 128
42 #define DISABLE_VT_TXT 129
43 #define ENABLE_VTD 130
44 #define DISABLE_VTD_TXT 131
45 #define ENABLE_ACTTPM_VT_VTD_TXT_DISABLE_STM 132
46 #define ENABLE_ACTTPM_VT_VTD_TXT_STM 133
47 #define DISABLE_STM 134
48 #define DISABLE_TXT_STM 135
49 #define DISABLE_SENTER_VMX 136
50 #define ENABLE_VMX_SMX_ONLY 137
51 #define ENABLE_VMX_OUTSIDE_SMX 138
52 #define ENABLE_VMX 139
53 #define ENABLE_SENTER_ONLY 140
54 #define ENABLE_SENTER_VMX_IN_SMX 141
55 #define ENABLE_SENTER_VMX_OUTSIDE_SMX 142
56 #define ENABLE_SENTER_VMX 143
57 #define SET_NO_TXT_MAINTENANCE_FALSE 159
58 #define SET_NO_TXT_MAINTENANCE_TRUE 160
59
60 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: TxtOneTouchOp.h Source File

  • Protocol
TxtOneTouchOp.h
Go to the documentation of this file.
1 /** @file
2 Txt specific PPI operation definition.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _TXT_PPI_OPERATION_H_
37 #define _TXT_PPI_OPERATION_H_
38
39 typedef struct _TXT_ONE_TOUCH_OP_PROTOCOL TXT_ONE_TOUCH_OP_PROTOCOL;
40
41 //
42 // Member functions
43 //
44 /*
45 Extend PPI operation for TxT.
46
47 @param[in] This - Point of TXT_ONE_TOUCH_OP_PROTOCOL
48 @param[in] Command - Operation value for TxT
49
50 */
51 typedef
52 EFI_STATUS
53 (EFIAPI *TXT_PPI_EXEC_OPERATION)(
54 IN TXT_ONE_TOUCH_OP_PROTOCOL *This,
55 IN UINT8 Command
56 );
57
58 /*
59 Confirmation dialog for TxT PPI
60
61 @param[in] This - Point of TXT_ONE_TOUCH_OP_PROTOCOL
62 @param[in] Command - Operation value for TxT
63 @param[in] Confirm - User confirm
64 */
65 typedef
66 EFI_STATUS
67 (EFIAPI *TXT_CONFIRMATION_DIALOG)(
68 IN TXT_ONE_TOUCH_OP_PROTOCOL *This,
69 IN UINT8 Command,
70 IN OUT BOOLEAN *Confirm
71 );
72
73 /**
74 Reset system.
75
76 @param[in] This - Point of TXT_ONE_TOUCH_OP_PROTOCOL
77 @param[in] Command - Operation value for TxT
78
79 @retval EFI_SUCCESS - Always return EFI_SUCCESS
80 **/
81 typedef
82 EFI_STATUS
83 (EFIAPI *TXT_RESET_SYSTEM)(
84 IN TXT_ONE_TOUCH_OP_PROTOCOL *This,
85 IN UINT8 Command
86 );
87
88 struct _TXT_ONE_TOUCH_OP_PROTOCOL {
89 TXT_PPI_EXEC_OPERATION ExecuteOperation;
90 TXT_CONFIRMATION_DIALOG ConfirmationDialog;
91 TXT_RESET_SYSTEM ResetSystem;
92 };
93
94 #endif
TXT_RESET_SYSTEM
EFI_STATUS(* TXT_RESET_SYSTEM)(IN TXT_ONE_TOUCH_OP_PROTOCOL *This, IN UINT8 Command)
Reset system.
Definition: TxtOneTouchOp.h:83
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: UsbDeviceLib.h Source File

  • Library
UsbDeviceLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for USBFN library definition.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #ifndef _EFI_XDCI_LIB_H_
35 #define _EFI_XDCI_LIB_H_
36
37 #include <Uefi.h>
38 #include <Library/DebugLib.h>
39 #include <Library/BaseMemoryLib.h>
40 #include <Library/MemoryAllocationLib.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <Protocol/UsbIo.h>
43
44 #define MAX_DESCRIPTOR_SIZE 64
45 #define STRING_ARR_SIZE (MAX_DESCRIPTOR_SIZE - 2)
46 #define USB_ADDRESS_TABLE_SIZE 16 //4
47
48 //
49 // Endpoint Zero
50 //
51 #define USB_EP0_MAX_PKT_SIZE_HS 0x40 // High Speed mode is explicitly set as 64 bytes
52 #define USB_EP0_MAX_PKT_SIZE_SS 0x9 // Must be 0x9 (2^9 = 512 Bytes) in SuperSpeed mode
53 #define USB_EPO_MAX_PKT_SIZE_ALL 512 // Overall max bytes for any type
54
55 //
56 // Bulk Endpoints
57 //
58 #define USB_BULK_EP_PKT_SIZE_HS 0x200 // Bulk-Endpoint HighSpeed
59 #define USB_BULK_EP_PKT_SIZE_SS 0x400 // Bulk-Endpoint SuperSpeed
60 #define USB_BULK_EP_PKT_SIZE_MAX USB_BULK_EP_PKT_SIZE_SS
61
62 //
63 // Transmit Direction Bits
64 //
65 #define USB_ENDPOINT_DIR_OUT 0x00
66
67 //
68 // Endpoint Companion Bulk Attributes
69 //
70 #define USB_EP_BULK_BM_ATTR_MASK 0x1F
71
72 //
73 // Configuration Modifiers (Attributes)
74 //
75 #define USB_BM_ATTR_RESERVED 0x80
76 #define USB_BM_ATTR_SELF_POWERED 0x40
77 #define USB_BM_ATTR_REMOTE_WAKE 0X20
78
79 //
80 // USB BCD version
81 //
82 #define USB_BCD_VERSION_LS 0x0110
83 #define USB_BCD_VERSION_HS 0x0200
84 #define USB_BCD_VERSION_SS 0x0300
85
86 //
87 // Device RequestType Flags
88 //
89 #define USB_RT_TX_DIR_H_TO_D (0x0) // Tx direction Host to Device
90 #define USB_RT_TX_DIR_D_TO_H (0x1 << 7) // Tx direction Device to Host
91 #define USB_RT_TX_DIR_MASK (0x80)
92
93 //
94 // USB request type
95 //
96 #define USB_REQ_TYPE_MASK (0x60)
97
98 //
99 // Usb control transfer target
100 //
101 #define USB_TARGET_MASK (0x1F)
102
103 //
104 // Device GetStatus bits
105 //
106 #define USB_STATUS_SELFPOWERED (0x01)
107 #define USB_STATUS_REMOTEWAKEUP (0x02)
108
109 //
110 // USB Device class identifiers
111 //
112 #define USB_DEVICE_MS_CLASS (0x08)
113 #define USB_DEVICE_VENDOR_CLASS (0xFF)
114
115 //
116 // USB Descriptor types
117 //
118 #define USB_DESC_TYPE_BOS 0x0F
119 #define USB_DESC_TYPE_DEVICE_CAPABILITY 0x10
120 #define USB_DESC_TYPE_SS_ENDPOINT_COMPANION 0x30
121
122 #ifdef SUPPORT_SUPER_SPEED
123 //
124 // USB device capability Type Codes
125 // USB3 Table 9-13
126 //
127 typedef enum {
128 WirelessUSB = 0x01,
129 USB2Extension,
130 SuperSpeedUSB,
131 ContainerID,
132 SuperSpeedPlusUSB = 0x0A
133 } USB_DEVICE_CAP_TYPE_CODE;
134 #endif
135
136
137 //
138 // USB device states from USB spec sec 9.1
139 //
140 typedef enum {
141 UsbDevStateOff = 0,
142 UsbDevStateInit,
143 UsbDevStateAttached,
144 UsbDevStatePowered,
145 UsbDevStateDefault,
146 UsbDevStateAddress,
147 UsbDevStateConfigured,
148 UsbDevStateSuspended,
149 UsbDevStateError
150 } USB_DEVICE_STATE;
151
152
153 //
154 // The following set of structs are used during USB data transaction
155 // operatitions, including requests and completion events.
156 //
157 #pragma pack(1)
158
159 typedef struct {
160 UINT32 EndpointNum;
161 UINT8 EndpointDir;
162 UINT8 EndpointType;
163 UINT32 Length;
164 VOID *Buffer;
165 } EFI_USB_DEVICE_XFER_INFO;
166
167 //
168 // SuperSpeed Endpoint companion descriptor
169 // USB3 table 9-22
170 //
171 typedef struct {
172 UINT8 Length;
173 UINT8 DescriptorType;
174 UINT8 MaxBurst;
175 UINT8 Attributes;
176 UINT16 BytesPerInterval;
177 } EFI_USB_ENDPOINT_COMPANION_DESCRIPTOR;
178
179 typedef struct {
180 EFI_USB_ENDPOINT_DESCRIPTOR *EndpointDesc;
181 EFI_USB_ENDPOINT_COMPANION_DESCRIPTOR *EndpointCompDesc;
182 } USB_DEVICE_ENDPOINT_INFO, USB_DEVICE_ENDPOINT_OBJ;
183
184 typedef struct {
185 VOID *Buffer;
186 UINT32 Length;
187 } USB_DEVICE_IO_INFO;
188
189 typedef struct {
190 USB_DEVICE_IO_INFO IoInfo;
191 USB_DEVICE_ENDPOINT_INFO EndpointInfo;
192 } USB_DEVICE_IO_REQ;
193
194 //
195 // Optional string descriptor
196 //
197 typedef struct {
198 UINT8 Length;
199 UINT8 DescriptorType;
200 UINT16 LangID[STRING_ARR_SIZE];
201 } USB_STRING_DESCRIPTOR;
202
203
204 //
205 // The following structures abstract the device descriptors a class
206 // driver needs to provide to the USBD core.
207 // These structures are filled & owned by the class/function layer.
208 //
209 typedef struct {
210 EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDesc;
211 USB_DEVICE_ENDPOINT_OBJ *EndpointObjs;
212 } USB_DEVICE_INTERFACE_OBJ;
213
214 typedef struct {
215 EFI_USB_CONFIG_DESCRIPTOR *ConfigDesc;
216 VOID *ConfigAll;
217 USB_DEVICE_INTERFACE_OBJ *InterfaceObjs;
218 } USB_DEVICE_CONFIG_OBJ;
219
220 #ifdef SUPPORT_SUPER_SPEED
221 //
222 // SuperSpeed Binary Device Object Store(BOS) descriptor
223 // USB3 9.6.2
224 //
225 typedef struct {
226 UINT8 Length;
227 UINT8 DescriptorType;
228 UINT16 TotalLength;
229 UINT8 NumDeviceCaps;
230 } EFI_USB_BOS_DESCRIPTOR;
231
232 //
233 // Generic Header of Device Capability descriptor
234 // USB3 9.6.2.2
235 //
236 typedef struct {
237 UINT8 Length;
238 UINT8 DescriptorType;
239 UINT8 DevCapabilityType;
240 UINT8 CapDependent;
241 } EFI_USB_SS_DEVICE_CAP_DESCRIPTOR;
242
243 //
244 // USB2.0 Extension descriptor
245 // USB3 Table 9-14
246 //
247 typedef struct {
248 UINT8 Length;
249 UINT8 DescriptorType;
250 UINT8 DeviceCapabilityType;
251 UINT32 Attributes;
252 } EFI_USB_USB2_EXT_CAP_DESCRIPTOR;
253
254
255 //
256 // SuperSpeed USB Device Capability descriptor
257 // USB3 Table 9-15
258 //
259 typedef struct {
260 UINT8 Length;
261 UINT8 DescriptorType;
262 UINT8 DeviceCapabilityType;
263 UINT8 Attributes;
264 UINT16 SpeedSupported;
265 UINT8 FunctionalitySupport;
266 UINT8 U1DevExitLat;
267 UINT16 U2DevExitLat;
268 } EFI_USB_SS_USB_DEV_CAP_DESCRIPTOR;
269
270 //
271 // Container ID descriptor
272 // USB3 Table 9-16
273 //
274 typedef struct {
275 UINT8 Length;
276 UINT8 DescriptorType;
277 UINT8 DeviceCapabilityType;
278 UINT8 Reserved;
279 UINT8 UUID[16];
280 } EFI_USB_CONTAINER_ID_DESCRIPTOR;
281
282 //
283 // Container ID descriptor
284 // USB3 Table 9-16
285 //
286 typedef struct {
287 UINT8 Length;
288 UINT8 DescriptorType;
289 UINT8 DeviceCapabilityType;
290 UINT8 ReservedByte;
291 UINT32 Attributes;
292 UINT16 FunctionalitySupport;
293 UINT16 ReservedWord;
294 UINT32 SublinkSpeedAttr[2];
295 } EFI_USB_SS_PLUS_USB_DEV_CAP_DESCRIPTOR;
296
297 #endif
298
299 typedef
300 EFI_STATUS
301 (EFIAPI *EFI_USB_CONFIG_CALLBACK) (
302 IN UINT8 CfgVal
303 );
304
305 typedef
306 EFI_STATUS
307 (EFIAPI *EFI_USB_SETUP_CALLBACK) (
308 IN EFI_USB_DEVICE_REQUEST *CtrlRequest,
309 IN USB_DEVICE_IO_INFO *IoInfo
310 );
311
312 typedef
313 EFI_STATUS
314 (EFIAPI *EFI_USB_DATA_CALLBACK) (
315 IN EFI_USB_DEVICE_XFER_INFO *XferInfo
316 );
317
318 typedef struct {
319 USB_DEVICE_DESCRIPTOR *DeviceDesc;
320 USB_DEVICE_CONFIG_OBJ *ConfigObjs;
321 USB_STRING_DESCRIPTOR *StringTable;
322 #ifdef SUPPORT_SUPER_SPEED
323 EFI_USB_BOS_DESCRIPTOR *BosDesc;
324 #endif
325 UINT8 StrTblEntries;
326 EFI_USB_CONFIG_CALLBACK ConfigCallback;
327 EFI_USB_SETUP_CALLBACK SetupCallback;
328 EFI_USB_DATA_CALLBACK DataCallback;
329 } USB_DEVICE_OBJ;
330
331
332 //
333 // Main USBD driver object structure containing all data necessary
334 // for USB device mode processing at this layer
335 //
336 typedef struct {
337 USB_DEVICE_OBJ *UsbdDevObj; /* pointer to a Device Object */
338 VOID *XdciDrvObj; /* Opaque handle to XDCI driver */
339 BOOLEAN XdciInitialized; /* flag to specify if the XDCI driver is initialized */
340 USB_DEVICE_CONFIG_OBJ *ActiveConfigObj; /* pointer to currently active configuraiton */
341 USB_DEVICE_STATE State; /* current state of the USB Device state machine */
342 UINT8 Address; /* configured device address */
343 } USB_DEVICE_DRIVER_OBJ;
344
345 #pragma pack()
346
347 #endif
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: UsbDeviceModeProtocol.h Source File

  • Protocol
UsbDeviceModeProtocol.h
Go to the documentation of this file.
1 /**@file
2 Header file for definition of USBFN device mode protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #ifndef _USB_DEVICE_MODE_PROTOCOL_H_
35 #define _USB_DEVICE_MODE_PROTOCOL_H_
36
37 #include <Library/UsbDeviceLib.h>
38
39 ///
40 /// UsbDeviceMode Protocol GUID.
41 ///
42 #define EFI_USB_DEVICE_MODE_PROTOCOL_GUID \
43 {0xC9923F7E, 0x1746, 0x4802, { 0x86, 0x2e, 0x1, 0x1c, 0x2c, 0x2d, 0x9d, 0x86 } }
44
45 typedef struct _EFI_USB_DEVICE_MODE_PROTOCOL EFI_USB_DEVICE_MODE_PROTOCOL;
46
47 typedef
48 EFI_STATUS
49 (EFIAPI *EFI_USB_DEVICE_MODE_INIT_XDCI) (
50 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
51 );
52
53 typedef
54 EFI_STATUS
55 (EFIAPI *EFI_USB_DEVICE_MODE_CONNECT) (
56 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
57 );
58
59 typedef
60 EFI_STATUS
61 (EFIAPI *EFI_USB_DEVICE_MODE_DISCONNECT) (
62 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
63 );
64
65 typedef
66 EFI_STATUS
67 (EFIAPI *EFI_USB_DEVICE_EP_TX_DATA) (
68 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
69 IN USB_DEVICE_IO_REQ *IoRequest
70 );
71
72 typedef
73 EFI_STATUS
74 (EFIAPI *EFI_USB_DEVICE_EP_RX_DATA) (
75 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
76 IN USB_DEVICE_IO_REQ *IoRequest
77 );
78
79 typedef
80 EFI_STATUS
81 (EFIAPI *EFI_USB_DEVICE_MODE_BIND) (
82 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
83 IN USB_DEVICE_OBJ *UsbdDevObj
84 );
85
86 typedef
87 EFI_STATUS
88 (EFIAPI *EFI_USB_DEVICE_MODE_UNBIND) (
89 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
90 );
91
92 typedef
93 EFI_STATUS
94 (EFIAPI *EFI_USB_DEVICE_MODE_STOP) (
95 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
96 );
97
98 typedef
99 EFI_STATUS
100 (EFIAPI *EFI_USB_DEVICE_MODE_RUN) (
101 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
102 IN UINT32 TimeoutMs
103 );
104
105 ///
106 /// Usb Device Mode Protocol Structure.
107 ///
108 struct _EFI_USB_DEVICE_MODE_PROTOCOL {
109 EFI_USB_DEVICE_MODE_INIT_XDCI InitXdci;
110 EFI_USB_DEVICE_MODE_CONNECT Connect;
111 EFI_USB_DEVICE_MODE_DISCONNECT DisConnect;
112 EFI_USB_DEVICE_EP_TX_DATA EpTxData;
113 EFI_USB_DEVICE_EP_RX_DATA EpRxData;
114 EFI_USB_DEVICE_MODE_BIND Bind;
115 EFI_USB_DEVICE_MODE_UNBIND UnBind;
116 EFI_USB_DEVICE_MODE_RUN Run;
117 EFI_USB_DEVICE_MODE_STOP Stop;
118 };
119
120 #endif
_EFI_USB_DEVICE_MODE_PROTOCOL
Usb Device Mode Protocol Structure.
Definition: UsbDeviceModeProtocol.h:108
UsbDeviceLib.h
Header file for USBFN library definition.
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: cse_basic_def.h Source File

  • Library
cse_basic_def.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2013 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _CSE_BASIC_DEF_H_
35 #define _CSE_BASIC_DEF_H_
36
37 //#if !defined(EFIX64) && !defined(WIN64) && !MANUF_TOOLS && !__APPLE__
38 // typedef unsigned int size_t;
39 //#elif __APPLE__
40 // typedef unsigned long size_t;
41 //#endif
42
43 #ifndef NULL
44 #define NULL (void*)0
45 #endif
46
47 typedef unsigned int uint32_t;
48 typedef unsigned char uint8_t;
49 typedef unsigned short uint16_t;
50 typedef unsigned int UINT32;
51 typedef unsigned char UINT8;
52 typedef unsigned short UINT16;
53 typedef unsigned char BOOL;
54
55 #if 0
56 // offset_of macros is a replacement to "offsetof" defined in <stddef.h>
57 #if defined(__GNUC__) || defined(WIN32_EMU) // GCC
58 #ifndef NULL
59 #define NULL (void*)0
60 #endif
61
62 typedef unsigned int uint32_t;
63 typedef unsigned char uint8_t;
64 typedef unsigned short uint16_t;
65 typedef unsigned int UINT32;
66 typedef unsigned char UINT8;
67 typedef unsigned short UINT16;
68 #else
69 #include <stddef.h>
70 #endif // __GNUC__
71 #endif
72
73
74 #if defined(__GNUC__)
75 #ifndef offsetof
76 #define offsetof(type, memeber) __builtin_offsetof(type, memeber)
77 #endif
78 #elif defined(WIN32_EMU)
79 #define offsetof(s,m) ((size_t)&((((s *)0)->m)))
80 #endif
81
82 // C_ASSERT macros isused for compile-time validations (typically size of the objects)
83 #ifndef C_ASSERT
84 #if defined(_MSC_VER)
85 #define C_ASSERT(e) typedef char __C_ASSERT__[(e)?1:-1]
86 #elif defined(__GNUC__)
87 #define C_ASSERT_CONCAT(x, y) C_ASSERT_XCONCAT(x, y)
88 #define C_ASSERT_XCONCAT(x, y) x ## y
89 #define C_ASSERT(e) extern char C_ASSERT_CONCAT(__C_ASSERT__, __COUNTER__)[(e)?1:-1] __attribute__((unused))
90 #else
91 #define C_ASSERT(e)
92 #endif
93 #endif // C_ASSERT
94
95 // force underscore into symbol that must match ld script.
96 #define LD_SYMBOL(name) name
97
98 #ifdef _MSC_VER
99
100 #define COMPILER_MESSAGE_STRINGIZE_HELPER(x) #x
101 #define COMPILER_MESSAGE_STRINGIZE(x) COMPILER_MESSAGE_STRINGIZE_HELPER(x)
102
103 #define COMPILER_MESSAGE_INTERNAL(desc) message(__FILE__ "(" COMPILER_MESSAGE_STRINGIZE(__LINE__) ") : [Developer Message] " #desc)
104 #define COMPILER_MESSAGE(x) __pragma(COMPILER_MESSAGE_INTERNAL(x))
105
106 #elif __GNUC__
107
108 #define COMPILER_MESSAGE_DO_PRAGMA(x) _Pragma (#x)
109 #define COMPILER_MESSAGE(x) COMPILER_MESSAGE_DO_PRAGMA(message ("[Developer Message] " #x))
110
111 #endif
112
113 // NUM_ELEMENTS macros provides number of elements in an array (instead of using constant explicitely)
114 #define NUM_ELEMENTS(array) (sizeof(array)/sizeof((array)[0]))
115
116 #define ONE_KILO 1024
117 #define ONE_MEGA (ONE_KILO * ONE_KILO)
118 #define ONE_GIGA (ONE_KILO * ONE_MEGA)
119
120 #define BITS_PER_BYTE 8
121 #define BITS_PER_DWORD 32
122
123 #endif //_CSE_BASIC_DEF_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: cse_basic_types.h Source File

  • Library
cse_basic_types.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2013 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _CSE_BASIC_TYPES_H_
35 #define _CSE_BASIC_TYPES_H_
36
37 #include "cse_basic_def.h"
38
39 #if ((defined (MANUF_TOOLS)) && !(MANUF_TOOLS)) || ((defined (__APPLE__)) && (__APPLE__))
40 typedef unsigned char uint8_t;
41 typedef unsigned short uint16_t;
42 typedef unsigned int uint32_t;
43 typedef unsigned long long uint64_t;
44
45 C_ASSERT(sizeof(uint8_t) == 1);
46 C_ASSERT(sizeof(uint16_t) == 2);
47 C_ASSERT(sizeof(uint32_t) == 4);
48 C_ASSERT(sizeof(uint64_t) == 8);
49 #endif
50
51 #ifndef UINT8_MAX
52 #define UINT8_MAX (255)
53 #endif
54
55 #ifndef UINT16_MAX
56 #define UINT16_MAX (65535U)
57 #endif
58
59 #ifndef UINT32_MAX
60 #define UINT32_MAX (4294967295UL)
61 #endif
62
63 #ifndef UINT64_MAX
64 #define UINT64_MAX (18446744073709551615ULL)
65 #endif
66
67 #endif //_CSE_BASIC_TYPES_H_
cse_basic_def.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Include -> Guid Relation

  • Include

Include → Guid Relation

File in Include | Includes file in Include/Guid
Tcg2ConfigNvData.h | PttInstance.h
Tcg2ConfigNvData.h | PttPTPInstanceGuid.h
Tcg2ConfigNvData.h | Tcg2ConfigHii.h


IceLake Platform Sample Code: Include -> Protocol Relation

  • Include

Include → Protocol Relation

File in Include | Includes file in Include/Protocol
Library / DxeSmmAcpiCustomLib.h | PlatformNvsArea.h
SmmStmConfTable.h | SmmTxtResource.h


IceLake Platform Sample Code: Hpet Directory Reference

  • Acpi
  • AcpiTables
  • Hpet
Hpet Directory Reference
Directory dependency graph for Hpet:

Files

file Hpet.h [code]
This file describes the contents of the ACPI High Precision Event Timer Description Table (HPET).


IceLake Platform Sample Code: AcpiTables -> Include Relation

  • Acpi
  • AcpiTables

AcpiTables → Include Relation

File in Acpi/AcpiTables | Includes file in Include
AcpiPlatform / Dxe / AcpiPlatform.c | PlatformBoardConfig.h
AcpiPlatform / Dxe / AcpiPlatform.c | PlatformBoardId.h
AcpiPlatform / Dxe / AcpiPlatform.c | PlatformInfo.h
AcpiPlatform / Dxe / AcpiPlatform.c | Guid / S3MemoryVariable.h
AcpiPlatform / Dxe / AcpiPlatform.h | Library / DxeAcpiGnvsInitLib.h
AcpiPlatform / Dxe / AcpiPlatform.h | Library / EcMiscLib.h
AcpiPlatform / Dxe / AcpiPlatform.h | Platform.h
AcpiPlatform / Dxe / AcpiPlatform.h | Protocol / PlatformNvsArea.h
AcpiPlatform / Dxe / AcpiPlatform.h | SetupVariable.h


IceLake Platform Sample Code: Dxe Directory Reference

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe
Dxe Directory Reference
Directory dependency graph for Dxe:

Files

file | AcpiPlatform.c [code]
ACPI Platform Driver.
file | AcpiPlatform.h [code]
This is an implementation of the ACPI platform driver.


IceLake Platform Sample Code: AcpiPlatform -> Include Relation

  • Acpi
  • AcpiTables
  • AcpiPlatform

AcpiPlatform → Include Relation

File in Acpi/AcpiTables/AcpiPlatform | Includes file in Include
Dxe / AcpiPlatform.c | PlatformBoardConfig.h
Dxe / AcpiPlatform.c | PlatformBoardId.h
Dxe / AcpiPlatform.c | PlatformInfo.h
Dxe / AcpiPlatform.c | Guid / S3MemoryVariable.h
Dxe / AcpiPlatform.h | Library / DxeAcpiGnvsInitLib.h
Dxe / AcpiPlatform.h | Library / EcMiscLib.h
Dxe / AcpiPlatform.h | Platform.h
Dxe / AcpiPlatform.h | Protocol / PlatformNvsArea.h
Dxe / AcpiPlatform.h | SetupVariable.h


IceLake Platform Sample Code: AcpiPlatform -> Fadt Relation

  • Acpi
  • AcpiTables
  • AcpiPlatform

AcpiPlatform → Fadt Relation

File in Acpi/AcpiTables/AcpiPlatform | Includes file in Acpi/AcpiTables/Fadt
Dxe / AcpiPlatform.h | Fadt6.1.h


IceLake Platform Sample Code: AcpiPlatform -> Mcfg Relation

  • Acpi
  • AcpiTables
  • AcpiPlatform

AcpiPlatform → Mcfg Relation

File in Acpi/AcpiTables/AcpiPlatform | Includes file in Acpi/AcpiTables/Mcfg
Dxe / AcpiPlatform.c | Mcfg.h


IceLake Platform Sample Code: Mcfg Directory Reference

  • Acpi
  • AcpiTables
  • Mcfg
Mcfg Directory Reference
Directory dependency graph for Mcfg:

Files

file Mcfg.h [code]
This file describes the contents of the ACPI Memory Mapped Configuration Space Access Table (MCFG).


IceLake Platform Sample Code: Dxe -> Include Relation

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe

Dxe → Include Relation

File in Acpi/AcpiTables/AcpiPlatform/Dxe | Includes file in Include
AcpiPlatform.c | PlatformBoardConfig.h
AcpiPlatform.c | PlatformBoardId.h
AcpiPlatform.c | PlatformInfo.h
AcpiPlatform.c | Guid / S3MemoryVariable.h
AcpiPlatform.h | Library / DxeAcpiGnvsInitLib.h
AcpiPlatform.h | Library / EcMiscLib.h
AcpiPlatform.h | Platform.h
AcpiPlatform.h | Protocol / PlatformNvsArea.h
AcpiPlatform.h | SetupVariable.h


IceLake Platform Sample Code: Dxe -> Fadt Relation

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe

Dxe → Fadt Relation

File in Acpi/AcpiTables/AcpiPlatform/Dxe | Includes file in Acpi/AcpiTables/Fadt
AcpiPlatform.h | Fadt6.1.h


IceLake Platform Sample Code: Dxe -> Mcfg Relation

  • Acpi
  • AcpiTables
  • AcpiPlatform
  • Dxe

Dxe → Mcfg Relation

File in Acpi/AcpiTables/AcpiPlatform/Dxe | Includes file in Acpi/AcpiTables/Mcfg
AcpiPlatform.c | Mcfg.h


IceLake Platform Sample Code: PolicyInitDxe -> Include Relation

  • PlatformInit
  • PolicyInitDxe

PolicyInitDxe → Include Relation

File in PlatformInit/PolicyInitDxe | Includes file in Include
AmtPolicyInitDxe.h | Library / DxeAmtPolicyUpdateLib.h
AmtPolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
AmtPolicyInitDxe.h | FirwmareConfigurations.h
CpuPolicyInitDxe.h | Library / DxeCpuPolicyUpdateLib.h
GopPolicyInitDxe.h | Library / EcMiscLib.h
GopPolicyInitDxe.h | PlatformBoardId.h
GopPolicyInitDxe.h | SetupVariable.h
MePolicyInitDxe.h | Library / DxeMePolicyUpdateLib.h
MePolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
MePolicyInitDxe.h | FirwmareConfigurations.h
PchPolicyInitDxe.h | Library / DxePchPolicyUpdateLib.h
PchPolicyInitDxe.h | FirwmareConfigurations.h
PolicyInitDxe.h | SetupVariable.h
SaPolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
SaPolicyInitDxe.h | Library / DxeSaPolicyUpdateLib.h
SaPolicyInitDxe.h | FirwmareConfigurations.h
TbtPolicyInitDxe.h | Library / DxeTbtPolicyUpdateLib.h
TbtPolicyInitDxe.h | FirwmareConfigurations.h


IceLake Platform Sample Code: IndustryStandard Directory Reference

  • IndustryStandard
IndustryStandard Directory Reference
Directory dependency graph for IndustryStandard:

Files

file | CeAta.h [code]
file | Mmc.h [code]
Header file for Industry MMC 4.2 spec.
file | SdCard.h [code]
Header file for Industry SD Card 2.0 spec.


IceLake Platform Sample Code: Protocol -> Library Relation

  • Protocol

Protocol → Library Relation

File in Include/Protocol | Includes file in Include/Library
UsbDeviceModeProtocol.h | UsbDeviceLib.h


IceLake Platform Sample Code: Library -> Protocol Relation

  • Library

Library → Protocol Relation

File in Include/Library | Includes file in Include/Protocol
DxeSmmAcpiCustomLib.h | PlatformNvsArea.h


IceLake Platform Sample Code: PlatformInitDxe Directory Reference

  • PlatformInit
  • PlatformInitDxe
PlatformInitDxe Directory Reference
Directory dependency graph for PlatformInitDxe:

Files

file | EcPlatformInitDxe.c [code]
Source code file for the Platform Init DXE module.
file | GfxInt15Interface.c [code]
This is a driver to produce Int15 hook.
file | PlatformInitDxe.c [code]
Source code file for the Platform Init DXE module.
file | PlatformInitDxe.h [code]
Platform Info Driver.
file | SaPlatformInitDxe.c [code]
Source code file for the Platform Init DXE module.


IceLake Platform Sample Code: PlatformInitDxe -> Include Relation

  • PlatformInit
  • PlatformInitDxe

PlatformInitDxe → Include Relation

File in PlatformInit/PlatformInitDxe | Includes file in Include
PlatformInitDxe.c | Protocol / PlatformNvsArea.h
PlatformInitDxe.c | PlatformPostCode.h
PlatformInitDxe.c | SoftwareGuardSetupData.h
PlatformInitDxe.h | Library / BootGuardRevocationLib.h
PlatformInitDxe.h | OemSetup.h
PlatformInitDxe.h | PlatformBoardConfig.h
PlatformInitDxe.h | PlatformBoardId.h
PlatformInitDxe.h | SetupVariable.h
SaPlatformInitDxe.c | PlatformNvRamHookLib.h


IceLake Platform Sample Code: PcdInitDxe -> Include Relation

  • PlatformInit
  • PcdInitDxe

PcdInitDxe → Include Relation

File in PlatformInit/PcdInitDxe | Includes file in Include
PcdInitDxe.c | SetupVariable.h


IceLake Platform Sample Code: PlatformInitPei -> Include Relation

  • PlatformInit
  • PlatformInitPei

PlatformInitPei → Include Relation

File in PlatformInit/PlatformInitPei | Includes file in Include
PlatformInit.c | AttemptUsbFirst.h
PlatformInit.c | Library / BoardConfigLib.h
PlatformInit.c | Library / EcLib.h
PlatformInit.c | Library / EcTcssLib.h
PlatformInit.c | Library / PeiPolicyInitLib.h
PlatformInit.c | Library / PeiReadWriteVariableLib.h
PlatformInit.c | PlatformBoardId.h
PlatformInit.c | PlatformPostCode.h
PlatformInit.c | SetupVariable.h
PlatformInit.c | Guid / SystemNvDataGuid.h
PlatformInitPreMem.c | Library / BoardConfigLib.h
PlatformInitPreMem.c | DsAllocation.h
PlatformInitPreMem.c | Library / EcCommands.h
PlatformInitPreMem.c | Library / EcMiscLib.h
PlatformInitPreMem.c | FirwmareConfigurations.h
PlatformInitPreMem.c | Library / MultiPlatSupportLib.h
PlatformInitPreMem.c | OemSetup.h
PlatformInitPreMem.c | Library / PeiPlatformLib.h
PlatformInitPreMem.c | Library / PeiPlatformRecoveryLib.h
PlatformInitPreMem.c | Library / PeiPolicyInitLib.h
PlatformInitPreMem.c | Library / PeiWdtAppLib.h
PlatformInitPreMem.c | Platform.h
PlatformInitPreMem.c | PlatformBoardConfig.h
PlatformInitPreMem.c | PlatformBoardId.h
PlatformInitPreMem.c | PlatformNvRamHookLib.h
PlatformInitPreMem.c | PlatformPostCode.h
PlatformInitPreMem.c | Setup.h
PlatformInitPreMem.c | SetupVariable.h
PlatformInitPreMem.c | Guid / TcoWdtHob.h


IceLake Platform Sample Code: Dsdt Directory Reference

  • Acpi
  • AcpiTables
  • Dsdt
Dsdt Directory Reference
Directory dependency graph for Dsdt:

Files

file | MofSampleDev.h [code]
file | MofTestDev.h [code]


IceLake Platform Sample Code: Acpi Directory Reference

  • Acpi
Acpi Directory Reference
Directory dependency graph for Acpi:

Directories

directory AcpiTables


IceLake Platform Sample Code: MultiPlatform Directory Reference

  • MultiPlatform
MultiPlatform Directory Reference
Directory dependency graph for MultiPlatform:

Files

file | _Default_BusNumberTranslator.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Default_MpTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Default_PirqTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Rvp_BusNumberTranslator.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Rvp_MpTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Rvp_PirqTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _RvpDt_BusNumberTranslator.h [code]
Copyright (c) 2011, Intel Corporation.
file | _RvpDt_MpTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _RvpDt_PirqTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _RvpM_BusNumberTranslator.h [code]
Copyright (c) 2011, Intel Corporation.
file | _RvpM_MpTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _RvpM_PirqTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Sds_BusNumberTranslator.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Sds_MpTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | _Sds_PirqTableData.h [code]
Copyright (c) 2011, Intel Corporation.
file | PlatformOpRomTable.h [code]
file | PlatformOptionRomTable_Default.h [code]
file | PlatformOptionRomTable_Rvp.h [code]
file | PlatformOptionRomTable_RvpDt.h [code]
file | PlatformOptionRomTable_RvpM.h [code]
file | PlatformOptionRomTable_Sds.h [code]


IceLake Platform Sample Code: Override Directory Reference

  • Override
Override Directory Reference
Directory dependency graph for Override:

Files

file DoxygenRpOverride.h [code]
This file contains doxygen commands definitions for creating Platform override documentation.


IceLake Platform Sample Code: PlatformInitPei Directory Reference

  • PlatformInit
  • PlatformInitPei
PlatformInitPei Directory Reference
Directory dependency graph for PlatformInitPei:

Files

file | PlatformInit.c [code]
Source code file for Platform Init PEI module.
file | PlatformInitPreMem.c [code]
Source code file for Platform Init Pre-Memory PEI module.


IceLake Platform Sample Code: Ppi Directory Reference

  • Ppi
Ppi Directory Reference
Directory dependency graph for Ppi:

Files

file OverClockPpi.h [code]


IceLake Platform Sample Code: Include Directory Reference

  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

directory | Guid
directory | IndustryStandard
directory | Library
directory | MultiPlatform
directory | Ppi
directory | Protocol

Files

file | AttemptUsbFirst.h [code]
file | CommonDefinitions.h [code]
file | CpuSmm.h [code]
file | CustomOptionControl.h [code]
file | DimmInfo.h [code]
This header file provides Dimm info definitions used by other modules for dimm info presentation.
file | DsAllocation.h [code]
file | DsConfig.h [code]
file | Efi.h [code]
file | FirwmareConfigurations.h [code]
This header file provides definitions of firmware configuration.
file | HstiIbvFeatureBit.h [code]
This file contains various definitions for IHV HSTI implementation including error string definitions.
file | IccSetupData.h [code]
file | MultiPlatSupport.h [code]
file | OcSetupVariable.h [code]
Variable definition for overclocking support.
file | OemSetup.h [code]
OEM Specific Setup Variables and Structures.
file | Platform.h [code]
This header file provides platform specific definitions used by other modules for platform specific initialization.
file | PlatformBoardConfig.h [code]
Header file for Platform Boards Configurations.
file | PlatformBoardId.h [code]
Defines Platform BoardIds.
file | PlatformClock.h [code]
file | PlatformConfigurationChangeVariable.h [code]
Platform configuration change variable definitions.
file | PlatformInfo.h [code]
GUID used for Platform Info Data entries in the HOB list.
file | PlatformNvRamHookLib.h [code]
Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc.
file | PlatformNvsAreaDef.h [code]
ACPI DSDT table.
file | PlatformPostCode.h [code]
file | Setup.h [code]
file | SetupConfiguration.h [code]
Default platform setup configuration settings.
file | SetupVariable.h [code]
file | SioRegs.h [code]
file | SmbiosPlatformInfoDefault.h [code]
This file contains Default data for Platform SMBIOS tables.
file | SmbiosPlatformInfoDefinition.h [code]
This file contains definition for Platform SMBIOS Info.
file | SmmStmConfTable.h [code]
GUID definition for the Smm Stm Configuraion Table.
file | SoftwareGuardSetupData.h [code]
Software Guard Setup Variables and Structures.
file | StmDefinition.h [code]
This file contains definitions required to use the TXT STM.
file | Swbpe.h [code]
file | Tcg2ConfigNvData.h [code]
Header file for NV data structure definition.
file | TcgSetup.h [code]


IceLake Platform Sample Code: Include Directory Reference

  • Acpi
  • AcpiTables
  • Include
Include Directory Reference
Directory dependency graph for Include:

Files

file AcpiCommon.h [code]
Header file for ACPI common Initialization Driver.


IceLake Platform Sample Code: Protocol Directory Reference

  • Protocol
Protocol Directory Reference
Directory dependency graph for Protocol:

Files

file | AmtWrapperProtocol.h [code]
The header file includes the definition of EFI_SPI_PROTOCOL.
file | DxePolicyUpdateProtocol.h [code]
file | EcAccess.h [code]
file | EfiUsbFnIo.h [code]
EFI USB function IO Protocol This protocol supports Usb Function IO API.
file | EmmcCardInfoProtocol.h [code]
file | I2cBusConfigurationManagement.h [code]
I2C bus configuration management interface.
file | I2cMaster.h [code]
I2C Master interface.
file | IccOverClocking.h [code]
file | PlatformNvsArea.h [code]
This file defines the Platform NVS Area Protocol.
file | SdHostIo.h [code]
Header file for interface definition of EFI_SD_HOST_IO_PROTOCOL.
file | SmmCpuSaveState.h [code]
This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors.
file | SmmTxtResource.h [code]
This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM.
file | SmmTxtStmService.h [code]
This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM.
file | SysFwUpdatePlatformProtocol.h [code]
Define the data structure and GUID of SysFwUpdatePlatform Protocol.
file | SystemMonitor.h [code]
file | TxtOneTouchOp.h [code]
Txt specific PPI operation definition.
file | UsbDeviceModeProtocol.h [code]
Header file for definition of USBFN device mode protocol.


IceLake Platform Sample Code: AcpiTables Directory Reference

  • Acpi
  • AcpiTables
AcpiTables Directory Reference
Directory dependency graph for AcpiTables:

Directories

directory | AcpiPlatform
directory | Dsdt
directory | Ecdt
directory | Facs
directory | Fadt
directory | Hpet
directory | Include
directory | Madt
directory | Mcfg


IceLake Platform Sample Code: Ecdt Directory Reference

  • Acpi
  • AcpiTables
  • Ecdt
Ecdt Directory Reference
Directory dependency graph for Ecdt:

Files

file Ecdt.h [code]
This file describes the contents of the ACPI Embedded Controller Boot Resources Table (ECDT).


IceLake Platform Sample Code: PcdInitDxe Directory Reference

  • PlatformInit
  • PcdInitDxe
PcdInitDxe Directory Reference
Directory dependency graph for PcdInitDxe:

Files

file PcdInitDxe.c [code]
Driver for initializing platform dynamic PCDs.


IceLake Platform Sample Code: PolicyInitDxe Directory Reference

  • PlatformInit
  • PolicyInitDxe
PolicyInitDxe Directory Reference
Directory dependency graph for PolicyInitDxe:

Files

file | AmtPolicyInitDxe.c [code]
This file is SampleCode for Intel AMT DXE Policy initialization.
file | AmtPolicyInitDxe.h [code]
Header file for the AmtPolicyInitDxe Driver.
file | CpuPolicyInitDxe.c [code]
This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
file | CpuPolicyInitDxe.h [code]
Header file for the SiliconPolicyInitDxe Driver.
file | GopPolicyInitDxe.c [code]
This file initialises and Installs GopPolicy Protocol.
file | GopPolicyInitDxe.h [code]
Header file for the GopPolicyInitDxe Driver.
file | MePolicyInitDxe.c [code]
This file is SampleCode for Intel ME DXE Policy initialization.
file | MePolicyInitDxe.h [code]
Header file for the MePolicyInitDxe Driver.
file | PchPolicyInitDxe.c [code]
This file is SampleCode for PCH DXE Policy initialization.
file | PchPolicyInitDxe.h [code]
Header file for the PchPolicyInitDxe Driver.
file | PolicyInitDxe.c [code]
This file is a wrapper for Platform Policy driver.
file | PolicyInitDxe.h [code]
Header file for the PolicyInitDxe Driver.
file | SaPolicyInitDxe.c [code]
This file is SampleCode for SA DXE Policy initialization.
file | SaPolicyInitDxe.h [code]
Header file for the SaPolicyInitDxe Driver.
file | SiliconPolicyInitDxe.c [code]
This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
file | SiliconPolicyInitDxe.h [code]
Header file for the SiliconPolicyInitDxe Driver.
file | TbtPolicyInitDxe.c [code]
This file is SampleCode for TBT DXE Policy initialization.
file | TbtPolicyInitDxe.h [code]
Header file for the TbtPolicyInitDxe Driver.


IceLake Platform Sample Code: Guid Directory Reference

  • Guid
Guid Directory Reference
Directory dependency graph for Guid:

Files

file | AcpiVariable.h [code]
file | PlatformEmmcHs400Info.h [code]
GUID used for Platform Emmc Hs400 Tuning Info NVRAM Data.
file | PlatformGlobalVariable.h [code]
GUID for Platform (NVRAM) Variables.
file | PttInstance.h [code]
GUID definition for the PTT device instance.
file | PttPTPInstanceGuid.h [code]
GUID definition for the PTT device instance.
file | S3MemoryVariable.h [code]
file | SystemNvDataGuid.h [code]
file | Tcg2ConfigHii.h [code]
GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.
file | TcoWdtHob.h [code]
file | TxtOneTouch.h [code]
This file contains definitions required for One-Touch function.


IceLake Platform Sample Code: Library Directory Reference

  • Library
Library Directory Reference
Directory dependency graph for Library:

Files

file | BaseCryptLib.h [code]
Defines base cryptographic library APIs.
file | BaseEcFlashLib.h [code]
file | BasePlatformVariableLib.h [code]
file | BoardConfigLib.h [code]
Function prototype of BoardConfigLib.
file | BootGuardRevocationLib.h [code]
Header file for Boot Guard revocation notification.
file | Build.h [code]
file | Common.h [code]
file | cse_basic_def.h [code]
file | cse_basic_types.h [code]
file | DxeAcpiGnvsInitLib.h [code]
Acpi Gnvs Init Library header file.
file | DxeAmtPolicyUpdateLib.h [code]
file | DxeCpuPolicyUpdateLib.h [code]
file | DxeFirmwareVersionInfoLib.h [code]
Private data structures.
file | DxeMePolicyUpdateLib.h [code]
file | DxeOpromPatchLib.h [code]
file | DxePchPolicyUpdateLib.h [code]
file | DxePlatformBootManagerLib.h [code]
Header file for DxePlatformBootManagerLib.
file | DxePolicyBoardConfigLib.h [code]
Header file for the DxePolicyBoardConfig Library.
file | DxeSaPolicyUpdateLib.h [code]
file | DxeSmmAcpiCustomLib.h [code]
This header file provides platform specific definitions used by other modules for platform specific initialization.
file | DxeSmmInternalGraphicDeviceLib.h [code]
file | DxeTbtPolicyUpdateLib.h [code]
file | EcCommands.h [code]
file | EcHwLib.h [code]
EC hardware library functions and definitions.
file | EcLib.h [code]
EC library functions and definitions.
file | EcMiscLib.h [code]
EC miscellaneous library functions.
file | EcTcssLib.h [code]
EC TCSS library functions.
file | FspPolicyInitLib.h [code]
Function prototype of FspPolicyInitLib.
file | Fwu_Common.h [code]
file | FWUpdateLib.h [code]
file | GpioExpanderLib.h [code]
Support for IO expander TCA6424.
file | HidI2cPlatformSupportLib.h [code]
Support for IO expander TCA6424.
file | I2cAccessLib.h [code]
Support for IO expander TCA6424.
file | I2cMmioConfigLib.h [code]
Memory mapped I/O specific configuration declarations.
file | me_status.h [code]
file | mkhi_hdrs.h [code]
file | MultiPlatSupportLib.h [code]
file | PdtUpdateLib.h [code]
file | PeiBootGuardEventLogLib.h [code]
This file contains functions for creating TPM Event Log.
file | PeiCpuPolicyDebugLib.h [code]
SampleCode header file of the library for Intel CPU PEI Debug Policy initialization.
file | PeiDxeBoardIdsLib.h [code]
Header file for Board Information boot time changes.
file | PeiPchPolicyDebugLib.h [code]
SampleCode header file of the library for Intel PCH PEI Debug Policy initialization.
file | PeiPlatformLib.h [code]
file | PeiPlatformRecoveryLib.h [code]
This library provides platform recovery module.
file | PeiPolicyBoardConfigLib.h [code]
Header file for the PeiPolicyBoardConfig Library.
file | PeiPolicyInitLib.h [code]
Header file for the PolicyInitPei Library.
file | PeiReadWriteVariableLib.h [code]
file | PeiSaPolicyDebugLib.h [code]
SampleCode header file of the library for Intel SA PEI Debug Policy initialization.
file | PeiSiPolicyDebugLib.h [code]
SampleCode header file of the library for Intel SI PEI Debug Policy initialization.
file | PeiSwbpeLib.h [code]
file | PeiWdtAppLib.h [code]
PEI WDT App library definitions.
file | PlatformInitLib.h [code]
Function prototype of PlatformInitLib.
file | PlatformSecureLib.h [code]
Provides a secure platform-specific method to detect physically present user.
file | PlatformSmmIoLib.h [code]
This library provides SMM functions for IO and PCI IO access.
file | SmmStmConfTableLib.h [code]
Txt Protocol definition include file.
file | SpiFlashCommon.h [code]
The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib.
file | Tcg.h [code]
TCG defined values and structures used by the Tcg Core library.
file | Tcg2PhysicalPresenceLib.h [code]
Ihis library is intended to be used by BDS modules.
file | TcgCore.h [code]
Public API for the Tcg Core library to perform the lowest level TCG data encoding.
file | TcgUtil.h [code]
Provides TCG high-level API to perform common TCG actions on a TCG data packet.
file | typedef.h [code]
file | UsbDeviceLib.h [code]
Header file for USBFN library definition.
file | ver.h [code]
Contains definitions of the MAJOR, MINOR, & HOTFIX versions used throughout the code.


IceLake Platform Sample Code: PlatformInit Directory Reference

  • PlatformInit
PlatformInit Directory Reference
Directory dependency graph for PlatformInit:

Directories

directory | PcdInitDxe
directory | PlatformInitDxe
directory | PlatformInitPei
directory | PolicyInitDxe


IceLake Platform Sample Code: AcpiPlatform Directory Reference

  • Acpi
  • AcpiTables
  • AcpiPlatform
AcpiPlatform Directory Reference
Directory dependency graph for AcpiPlatform:

Directories

directory Dxe


IceLake Platform Sample Code: Fadt Directory Reference

  • Acpi
  • AcpiTables
  • Fadt
Fadt Directory Reference
Directory dependency graph for Fadt:

Files

file Fadt6.1.h [code]
This file describes the contents of the ACPI Fixed ACPI Description Table (FADT).


IceLake Platform Sample Code: Madt Directory Reference

  • Acpi
  • AcpiTables
  • Madt
Madt Directory Reference
Directory dependency graph for Madt:

Files

file Madt.h [code]
This file describes the contents of the ACPI Multiple APIC Description Table (MADT).


IceLake Platform Sample Code: Facs Directory Reference

  • Acpi
  • AcpiTables
  • Facs
Facs Directory Reference
Directory dependency graph for Facs:

Files

file Facs.h [code]
This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS).


IceLake Platform Sample Code: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

1 /*! Invisible class because of truncation */
2 class Invisible { };
3
4 /*! Truncated class, inheritance relation is hidden */
5 class Truncated : public Invisible { };
6
7 /* Class not documented with doxygen comments */
8 class Undocumented { };
9
10 /*! Class that is inherited using public inheritance */
11 class PublicBase : public Truncated { };
12
13 /*! A template class */
14 template<class T> class Templ { };
15
16 /*! Class that is inherited using protected inheritance */
17 class ProtectedBase { };
18
19 /*! Class that is inherited using private inheritance */
20 class PrivateBase { };
21
22 /*! Class that is used by the Inherited class */
23 class Used { };
24
25 /*! Super class that inherits a number of other classes */
26 class Inherited : public PublicBase,
27 protected ProtectedBase,
28 private PrivateBase,
29 public Undocumented,
30 public Templ<int>
31 {
32 private:
33 Used *m_usedClass;
34 };

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a gray border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.


IceLake Platform Sample Code: me_status.h Source File

  • Library
me_status.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2005 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _ME_STATUS_H_
35 #define _ME_STATUS_H_
36
37 ///////////////////////////////////////////////////////////////////////////////
38 // ERROR & STATUS CODE RANGES //
39 ///////////////////////////////////////////////////////////////////////////////
40 // RANGE // DESCRIPTION //
41 ///////////////////////////////////////////////////////////////////////////////
42 // 0x0000FFFF - 0x00000000 // Pre-defined standard error values used by all //
43 // // ME Components and interfaces //
44 ///////////////////////////////////////////////////////////////////////////////
45 // 0x0001FFFF - 0x00010000 // Capability Module specific error codes //
46 ///////////////////////////////////////////////////////////////////////////////
47 // 0xFFFFFFFF - 0x00020000 // Reserved for future use. //
48 ///////////////////////////////////////////////////////////////////////////////
49
50 ///////////////////////////////////////////////////////////////////////////////
51 // KERNEL STATUS AND ERROR CODES //
52 //The following are the status and error codes returned by the ME Kernel. //
53 //ThreadX Codes range from (0x00 to 0x7F) //
54 //Other Kernel codes range from (0x80 to 0xFF) //
55 ///////////////////////////////////////////////////////////////////////////////
56
57
58
59
60 //
61 //STATUS_SUCCESS
62 // The operation completed successfully.
63 //
64
65 /**
66 * @brief The operation completed successfully.
67 */
68 #define STATUS_SUCCESS 0x0
69
70 //
71 //STATUS_DELETED
72 // The requested object has been deleted.
73 //
74 #define STATUS_DELETED 0x1
75
76 //
77 //STATUS_POOL_ERROR
78 // An invalid memory pool pointer (NULL) was given or the pool is
79 // already created.
80 //
81 #define STATUS_POOL_ERROR 0x2
82
83 //
84 //STATUS_PTR_ERROR
85 // An invalid pointer was provided.
86 //
87 #define STATUS_PTR_ERROR 0x3
88
89 //
90 //STATUS_WAIT_ERROR
91 // The specified wait option is invalid.
92 //
93 #define STATUS_WAIT_ERROR 0x4
94
95 //
96 //STATUS_SIZE_ERROR
97 // The size of the specified object (memory pool, stack, message queue,
98 // etc.) is invalid.
99 //
100 #define STATUS_SIZE_ERROR 0x5
101
102 //
103 //STATUS_GROUP_ERROR
104 // An invalid group pointer was provided. The pointer is NULL or points
105 // to an already created group.
106 //
107 #define STATUS_GROUP_ERROR 0x6
108
109 //
110 //STATUS_NO_EVENTS
111 // The requested event could not be found.
112 //
113 #define STATUS_NO_EVENTS 0x7
114
115 //
116 //STATUS_OPTION_ERROR
117 // Invalid event flag set option (AND, OR).
118 //
119 #define STATUS_OPTION_ERROR 0x8
120
121 //
122 //STATUS_QUEUE_ERROR
123 // An invalid queue pointer passed or the queue is already created.
124 //
125 #define STATUS_QUEUE_ERROR 0x9
126
127 //
128 //STATUS_QUEUE_EMPTY
129 // The requested queue is empty.
130 //
131 #define STATUS_QUEUE_EMPTY 0xA
132
133 //
134 //STATUS_QUEUE_FULL
135 // The requested queue is full.
136 //
137 #define STATUS_QUEUE_FULL 0xB
138
139 //
140 //STATUS_SEMAPHORE_ERROR
141 // An invalid semaphore pointer provided or the semaphore is already created.
142 //
143 #define STATUS_SEMAPHORE_ERROR 0xC
144
145 //
146 //STATUS_NO_INSTANCE
147 // The requested instance was not found (semaphore count is 0x0).
148 //
149 #define STATUS_NO_INSTANCE 0xD
150
151 //
152 //STATUS_THREAD_ERROR
153 // An invalid thread control pointer provided or the thread is already created.
154 //
155 #define STATUS_THREAD_ERROR 0xE
156
157 //
158 //STATUS_PRIORITY_ERROR
159 // An invalid thread priority level has been given.
160 //
161 #define STATUS_PRIORITY_ERROR 0xF
162
163 //
164 //STATUS_START_ERROR
165 // An invalid auto-start selection was given during thread creation.
166 // NOTE: This value is the same a as STATUS_NO_MEMORY.
167 //
168 #define STATUS_START_ERROR 0x10
169
170 //
171 //STATUS_DELETE_ERROR
172 // The requested object can not be deleted. This can occur if an attempt is
173 // made to delete a thread that is not in a terminated or completed state.
174 //
175 #define STATUS_DELETE_ERROR 0x11
176
177 //
178 //STATUS_RESUME_ERROR
179 // The thread can not be resumed (e.g. the specified thread is not in a
180 // suspended state or was suspended by a driver other than the RTOS protocol).
181 //
182 #define STATUS_RESUME_ERROR 0x12
183
184 //
185 //STATUS_CALLER_ERROR
186 // Invalid caller of this service.
187 //
188 #define STATUS_CALLER_ERROR 0x13
189
190 //
191 //STATUS_SUSPEND_ERROR
192 // The thead can not be suspended (e.g. the specified thread is in a
193 // terminated or completed state).
194 //
195 #define STATUS_SUSPEND_ERROR 0x14
196
197 //
198 //STATUS_TIMER_ERROR
199 // An invalid timer object pointer was given.
200 //
201 #define STATUS_TIMER_ERROR 0x15
202
203 //
204 //STATUS_TICK_ERROR
205 // An invalid value (0x0) supplied for the initial tick count.
206 //
207 #define STATUS_TICK_ERROR 0x16
208
209 //
210 //STATUS_ACTIVATE_ERROR
211 // The object is already active.
212 //
213 #define STATUS_ACTIVATE_ERROR 0x17
214
215 //
216 //STATUS_THRESH_ERROR
217 // An invalid preemption threashold was specified.
218 //
219 #define STATUS_THRESH_ERROR 0x18
220
221 //
222 //STATUS_SUSPEND_LIFTED
223 // An attempt to resume a thread marked for delayed suspension has
224 // occurred.
225 //
226 #define STATUS_SUSPEND_LIFTED 0x19
227
228 //
229 //STATUS_WAIT_ABORTED
230 // The wait condition on which the thread is waiting has been aborted.
231 //
232 #define STATUS_WAIT_ABORTED 0x1A
233
234 //
235 //STATUS_WAIT_ABORT_ERROR
236 // An attempt to abort a waiting thread was attempted on a thread that is
237 // not in a waiting condition (terminated, ready, completed, etc.).
238 //
239 #define STATUS_WAIT_ABORT_ERROR 0x1B
240
241 //
242 //STATUS_MUTEX_ERROR
243 // An invalid mutex pointer was provided.
244 //
245 #define STATUS_MUTEX_ERROR 0x1C
246
247 //
248 //STATUS_NOT_AVAILABLE
249 // An attempt to remove a mutex on which a thread is suspended has been
250 // attempted.
251 //
252 #define STATUS_NOT_AVAILABLE 0x1D
253
254 //
255 //STATUS_NOT_OWNED
256 // An attempt to access a mutex not owned by the caller was made.
257 //
258 #define STATUS_NOT_OWNED 0x1E
259
260 //
261 //STATUS_INHERIT_ERROR
262 // An invalid inherit option was given when trying to create a mutex.
263 //
264 #define STATUS_INHERIT_ERROR 0x1F
265
266 //
267 //STATUS_TIMER_RUNNING
268 // An attempt to set an alarm was made while alarm is already enabled.
269 //
270 #define STATUS_TIMER_RUNNING 0x20
271
272 //
273 //STATUS_INVALID_FUNCTION
274 // The requested function was not found.
275 //
276 #define STATUS_INVALID_FUNCTION 0x80
277
278 //
279 //STATUS_NOT_FOUND
280 // The requested item could not be found.
281 //
282 #define STATUS_NOT_FOUND 0x81
283
284 //
285 //STATUS_ACCESS_DENIED
286 // Access to the requested object could not be granted.
287 //
288 #define STATUS_ACCESS_DENIED 0x82
289
290 //
291 //STATUS_INVALID_HANDLE
292 // The provided handle does not exist.
293 //
294 #define STATUS_INVALID_HANDLE 0x83
295
296 //
297 //STATUS_INVALID_ACCESS
298 // An attempt was made to access an inaccessible or unavailable object.
299 //
300 #define STATUS_INVALID_ACCESS 0x84
301
302 //
303 //STATUS_INVALID_PARAMS
304 // One or more parameters are invalid.
305 //
306 #define STATUS_INVALID_PARAMS 0x85
307
308 //
309 //STATUS_INVALID_PARAMS
310 // Request could not be processed because a Power Management event is already
311 // in progress.
312 //
313 #define STATUS_PM_EVENT_IN_PROGRESS 0x86
314
315 //
316 //STATUS_WRITE_PROTECTED
317 // The media is write protected. When writing to flash, this means
318 // the flash block is write protected.
319 //
320 #define STATUS_WRITE_PROTECTED 0x87
321
322 //
323 //STATUS_NOT_READY
324 // The h/w device is not ready.
325 //
326 #define STATUS_NOT_READY 0x88
327
328 //
329 //STATUS_NOT_SUPPORTED
330 // The function, message or request is not recognized or supported.
331 //
332 #define STATUS_NOT_SUPPORTED 0x89
333
334 //
335 //STATUS_NETWORK_BUSY
336 // The network device is busy.
337 //
338 #define STATUS_NETWORK_BUSY 0x8A
339
340 //
341 //STATUS_DEVICE_ERROR
342 // The h/w device reported an error while attempting the operation.
343 //
344 #define STATUS_DEVICE_ERROR 0x8B
345
346 //
347 //STATUS_INVALID_ADDRESS
348 // The address provided in invalid.
349 //
350 #define STATUS_INVALID_ADDRESS 0x8C
351
352 //
353 //STATUS_INVALID_COMMAND
354 // The requested command is unrecognized or invalid.
355 //
356 #define STATUS_INVALID_COMMAND 0x8D
357
358 //
359 //STATUS_STACK_OVERFLOW
360 // The request caused a stack overflow.
361 //
362 #define STATUS_STACK_OVER_FLOW 0x8E
363
364 //
365 //STATUS_BUFFER_TOO_SMALL
366 // The provided buffer is too small to hold the requested data.
367 //
368 #define STATUS_BUFFER_TOO_SMALL 0x8F
369
370 //
371 //STATUS_LOAD_ERROR
372 // The image failed to load.
373 //
374 #define STATUS_LOAD_ERROR 0x90
375
376 //
377 //STATUS_INVALID_BUFFER
378 // The buffer was not the proper size for the request.
379 //
380 #define STATUS_INVALID_BUFFER 0x91
381
382 //
383 //STATUS_NO_RESPONSE
384 // No response was received from the requested target.
385 //
386 #define STATUS_NO_RESPONSE 0x92
387
388 //
389 //STATUS_TIMED_OUT
390 // The device or object timed out and was unable to complete the request.
391 //
392 #define STATUS_TIMED_OUT 0x93
393
394 //
395 //STATUS_NOT_STARTED
396 // The requested operation could not be started. For protocols, this
397 // error indicates the protocol has not been started.
398 //
399 #define STATUS_NOT_STARTED 0x94
400
401 //
402 //STATUS_ALREADY_STARTED
403 // The requested operation has already been started.
404 // - For protocols, this error
405 // indicates the protocol has already been started.
406 // - For Policy Manager this error means
407 // that the MKHI group ID is already registered.
408 // For FW update, we only allow one process to do the update at a time, this means error
409 // case where FW update is already in progress, the current process will have to try later.
410 //
411 #define STATUS_ALREADY_STARTED 0x95
412
413 //
414 //STATUS_PROTOCOL_ERROR
415 // The protocol in use has generated an error. For network traffic this error
416 // means the networking protocol returned and error. When returned from a
417 // protocol this means the protocol itself generated an error.
418 //
419 #define STATUS_PROTOCOL_ERROR 0x96
420
421 //
422 //STATUS_INCOMPATIBLE_VERSION
423 // The version of the object is incompatible with the request. For protocols,
424 // this indicates that the protocol version number is not supported.
425 //
426 #define STATUS_INCOMPATIBLE_VERSION 0x97
427
428 //
429 //STATUS_SECURITY_VIOLATION
430 // A security violation has occurred.
431 //
432 #define STATUS_SECURITY_VIOLATION 0x98
433
434 //
435 //STATUS_AUTHENTICATION_FAIL
436 // The authentication of an object has failed.
437 //
438 #define STATUS_AUTHENTICATION_FAIL 0x99
439
440 //
441 //STATUS_INVALID_MEM_TYPE
442 // The target memory is invalid for the requested operation (e.g. DMA to
443 // ROM or cypto DMA from system memory).
444 //
445 #define STATUS_INVALID_MEM_TYPE 0x9A
446
447 //
448 //STATUS_MODE_NOT_SUPPORTED
449 // The type of blocking mode is not supported. Refer to the documentation on
450 // the specific interface.
451 //
452 #define STATUS_MODE_NOT_SUPPORTED 0x9B
453
454 //
455 //STATUS_RESOURCE_BUSY
456 // The requested resource is busy or can not be acquired.
457 //
458 #define STATUS_RESOURCE_BUSY 0x9C
459
460 //
461 //STATUS_OUT_OF_RESOURCES
462 // Insufficient resources to perform the request. Used by components operating
463 // in non-blocking mode. A caller will be returned this error when a component
464 // does not have enough resources like command buffers, PRDs etc... to entertain
465 // a new request.
466 //
467 #define STATUS_OUT_OF_RESOURCES 0x9D
468
469 //
470 //STATUS_FAILURE
471 // A unknown error encountered while performing a requested transaction.
472 //
473 #define STATUS_FAILURE 0x9E
474
475 //
476 //STATUS_QUEUED
477 // A requested has been successfully placed in a command queue. This status
478 // is returned by non-blocking components after successfully queuing a request
479 // in their command queue.
480 //
481 #define STATUS_QUEUED 0x9F
482
483 //
484 //STATUS_WEAR_OUT_VIOLATION
485 // The partition manager returns this error code when it can not perform a
486 // requested erase operation due to flash wear out constraints.
487 #define STATUS_WEAR_OUT_VIOLATION 0xA0
488
489 //
490 //STATUS_GENERAL_ERROR
491 // This is a general error code used for errors that do not require a specific
492 // code.
493 #define STATUS_GENERAL_ERROR 0xA1
494
495 //
496 //STATUS_SMB_EMPTY
497 // The smbus slave circular buffer does not contain any smbus transactions data.
498 #define STATUS_SMB_EMPTY 0xA2
499
500 //
501 //STATUS_SMB_NO_MORE_ENTRIES
502 // The smbus slave has reached its maximal number of registered transactions.
503 // New transactions can not be added until the removal of one of the current
504 // registered ones.
505 #define STATUS_SMB_NO_MORE_ENTRIES 0xA3
506
507 //
508 //STATUS_BUS_ERROR
509 // Generic error code for bus errors. Common cause could be losing arbitration
510 // on a multi-mastered bus.
511 #define STATUS_BUS_ERROR 0xA4
512
513 //
514 //STATUS_IMAGE_INVALID
515 // The FW Update image content is invalid.
516 #define STATUS_IMAGE_INVALID 0xA5
517
518 //
519 //STATUS_UPDATE_AUTH_FAILED
520 // The FW Update image authentication failed.
521 #define STATUS_UPDATE_AUTH_FAILED 0xA6
522
523 //
524 //STATUS_UPDATE_ALLOWED
525 // Used in the policy manager to indicate whether a policy can be updated at
526 // the time of this request.
527 #define STATUS_UPDATE_ALLOWED 0xA7
528
529 //
530 //STATUS_UPDATE_NOT_ALLOWED
531 // Used in the policy manager to indicate that a policy cannot be updated at
532 // the time of this request.
533 #define STATUS_UPDATE_NOT_ALLOWED 0xA8
534
535 //
536 //STATUS_LOCKED
537 // Indicates policy element has been already locked and cannot be updated.
538 #define STATUS_LOCKED 0xA9
539
540 //
541 //STATUS_NOT_INITIALIZED
542 // Indicates that SDM core is not initialized
543 #define STATUS_NOT_INITIALIZED 0xAA //REQUIRES COORDINATION!!!
544
545 //
546 //STATUS_END_OF_FILE
547 // Indicates that EOF is reached while accessing a file
548 #define STATUS_END_OF_FILE 0xAB //REQUIRES COORDINATION!!!
549
550 //
551 //STATUS_NO_STORAGE_AVAILABLE
552 // Indicates policy element could not be stored in the NVAR.
553 #define STATUS_NO_STORAGE_AVAILABLE 0xB0
554
555 //
556 //STATUS_LOCKING_NOT_ALLOWED
557 // Indicates policy element cannot be locked.
558 #define STATUS_LOCKING_NOT_ALLOWED 0xB1
559
560 //
561 //STATUS_UNKNOWN_LAN_FUSE_CAPS
562 // Indicates a unknown capability of the LAN device is being set.
563 #define STATUS_UNKNOWN_LAN_FUSE_CAPS 0xB2
564
565 //
566 //STATUS_INVALID_FEATURE_ID
567 // Indicates an invalid feature ID.
568 #define STATUS_INVALID_FEATURE_ID 0xB3
569
570 //
571 //STATUS_PET_TRANSMIT_DISABLED
572 // The transmission of pet packets is disabled.
573 #define STATUS_PET_TRANSMIT_DISABLED 0xB4
574
575 // STATUS_MAX_KERB_DOMAIN_REACHED
576 // indicates that in the kerberos ACL there are users from MAX DOMAINS (4).
577 #define STATUS_MAX_KERB_DOMAIN_REACHED 0xB5
578
579 // STATUS_UPDATE_MISMATCH_HW_SKU
580 // Indicates that there is a mismatch between the current HW SKU and the
581 // one in the new image.
582 #define STATUS_UPDATE_MISMATCH_HW_SKU 0xB6
583
584 // STATUS_UPDATE_MISMATCH_FW_SKU
585 // Indicates that there is a mismatch between the current FW SKU and the
586 // one in the new image.
587 #define STATUS_UPDATE_MISMATCH_FW_SKU 0xB7
588
589 // STATUS_UPDATE_MISMATCH_VERSION
590 // Indicates that there is a mismatch between the current FW version and the
591 // one in the new image.
592 #define STATUS_UPDATE_MISMATCH_VERSION 0xB8
593
594 // STATUS_EVENT_DISABLED_CONFIG
595 // This wake event is configured to be disabled (via MEBx setup or remote
596 // configuration).
597 #define STATUS_EVENT_DISABLED_CONFIG 0xB9
598
599 // STATUS_NOT_REGISTERED
600 // Caller is trying to use an interface that requires registration, but the
601 // registration process has not been completed.
602 #define STATUS_NOT_REGISTERED 0xBA
603
604
605 // STATUS_INVALID_EVENT
606 // Caller is trying to use a wake event code which is invalid
607 #define STATUS_INVALID_EVENT 0xBB
608
609 // STATUS_INVALID_EVENT
610 // Caller is trying to use an event context which is invalid
611 #define STATUS_BAD_CONTEXT 0xBC
612
613
614 //
615 //STATUS_NET_RESTART_NEEDED
616 // The network stack need restart to continue working.
617 #define STATUS_NET_RESTART_NEEDED 0xBD
618
619 //
620 //STATUS_OUT_OF_MEMORY
621 // This error can be returned for the following reasons:
622 // 1.Attempt to allocate memory and no memory is available
623 // 2.Attempt to free a memory block on which a thread is suspended
624 // NOTE: This value is the same a as STATUS_START_ERROR.
625 //
626 #define STATUS_OUT_OF_MEMORY 0xBE
627
628
629 //
630 //STATUS_COUNTER_ROLLOVER
631 // This error can be returned by MC_PROTOCOL IncrementCounter()
632 // if given monotonic counter reaches maximum value.
633 // Along with error, counter will be initialized with value "1"
634 //
635 // The value will also be returned by TIME_PROTOCOL GetPRTC()
636 // if the PRTC rolls over
637 #define STATUS_COUNTER_ROLLOVER 0xBF
638
639
640 //
641 // BLOB SERVICE SPECIFIC FAILURES
642 //
643 // STATUS_BLOB_INTEGRITY_FAILED
644 // STATUS_BLOB_CONFIDENTIALITY_FAILED
645 // STATUS_BLOB_AR_FAILED
646 #define STATUS_BLOB_INTEGRITY_FAILED 0xC0
647 #define STATUS_BLOB_CONFIDENTIALITY_FAILED 0xC1
648 #define STATUS_BLOB_AR_FAILED 0xC2
649
650
651
652 //STATUS_PROCESSING
653 // Caller is asking for process result that is not already finished
654 #define STATUS_PROCESSING 0xC3
655
656 //STATUS_REGISTERED
657 // Caller registered for something that itself or others already did
658 #define STATUS_REGISTERED 0xC4
659 //
660 //STATUS_EAC_NOT_PERMITTED
661 // This error can be returned for the following reasons:
662 // 1.Attempt to enable EAC when sign certificate is not set
663
664 //
665 #define STATUS_EAC_NOT_PERMITTED 0xC5
666
667 //
668 //STATUS_EAC_NO_ASSOCIATION
669 // This error can be returned for the following reasons:
670 // 1.Attempt to receive a posture or posture hash sign certificate is not set
671
672 //
673 #define STATUS_EAC_NO_ASSOCIATION 0xC6
674
675 //
676 //STATUS_AUDIT_FAIL
677 // This error can be returned when these conditions are met:
678 // 1. The action should be logged to the Audit Log
679 // 2. The event was defined as critical
680 // 3. The Audit Log is enabled
681 // 4. Either:
682 // a. The Audit Log is currently Locked
683 // b. The storage for the Audit Log is full
684
685 //
686 #define STATUS_AUDIT_FAIL 0xC7
687
688 #define STATUS_DUPLICATED 0xC8
689
690 //
691 //STATUS_IPP_INTERNAL_ERROR
692 // This error can bb returned in case of internal IPP function failed.
693 #define STATUS_IPP_INTERNAL_ERROR 0xC9
694
695 //
696 //STATUS_IPP_CORRUPTED_KEY
697 // This error can be returned when trying to load or validate corrupted RSA key
698 // using the IPP stack.
699 // Can be returned RsaEncryptDecrypt and RsaValidateKey functions.
700 #define STATUS_IPP_CORRUPTED_KEY 0xCA
701
702 //
703 //STATUS_IPP_DATA_NOT_ALIGNED
704 // This error can be returned when trying to load, create or validate RSA key using the
705 // IPP stack, and the data is not aligned.
706 // Can be returned RsaGenerateKey, RsaEncryptDecrypt and RsaValidateKey functions.
707 #define STATUS_IPP_DATA_NOT_ALIGNED 0xCB
708
709 //
710 //STATUS_IPP_OPERATION_ABORTED
711 // This error will be returned if the IPP aborted key generation before completion.
712 #define STATUS_IPP_OPERATION_ABORTED 0xCC
713
714 //
715 //STATUS_IPP_CACHE_CONVERTION_FAILED
716 // This error can be returned if the TRAMD-Cache conversion failed.
717 #define STATUS_IPP_CACHE_CONVERTION_FAILED 0xCD
718
719 //
720 //STATUS_IPP_EXPONENT_CHANGED
721 // This error will be returned if the IPP decided to use differnt exponent (E)
722 // than the one the caller supplied.
723 #define STATUS_IPP_EXPONENT_CHANGED 0xCE
724
725 // STATUS_PERMIT_EXPIRED
726 // iCLS Permit has expired
727 #define STATUS_PERMIT_EXPIRED 0xCF
728
729 // STATUS_PERMIT_RESET_REQUIRED
730 // iCLS permit is invalid in some way (for example expired)
731 // and HW fuses are overided by permit still
732 #define STATUS_PERMIT_RESET_REQUIRED 0xD0
733
734 // STATUS_CLOSED_BY_HOST
735 // HECI will return this in the event that AddBuffer call is failing because
736 // the connection is in a close pending status.
737 // This will indicate that freeing the SendBufferQ and BufferQ is not permitted at
738 // this time and the client should wait for a HIE_CLOSED message to cleanup HECI_CONNECTION.
739 #define STATUS_CLOSED_BY_HOST 0xD1
740
741
742 // STATUS_DISABLED_BY_POLICY
743 // This error will be returned if the call is blocked by previous defined policy
744 #define STATUS_DISABLED_BY_POLICY 0xD2
745
746 //STATUS_INVALID_COMP_HANDLE
747 // The provided component handle does not exist.
748 //
749 #define STATUS_INVALID_COMP_HANDLE 0xD3
750
751 //
752 //Status Codes used by state manager to indicate ME Database status
753 //and general Client/Daemon registration problems in state manager
754 //that prohibit the Daemon from returning more exact status.
755 //
756
757 //
758 //STATUS_ALREADY_REGISTERED
759 // This error is used to indicate if a Daemon is already
760 // registered with state manager.
761 #define STATUS_ALREADY_REGISTERED 0xD4
762
763 //
764 //STATUS_DATABASE_IN_USE
765 // This error is used to indicate if a ME Database is currently in
766 // use when a delete is called on it.
767 #define STATUS_DATABASE_IN_USE 0xD5
768
769 //
770 //STATUS_ENTRY_IN_USE
771 // This error is used to indicate if an entry in a ME Database is
772 // currently in use when a release is called on it.
773 #define STATUS_ENTRY_IN_USE 0xD6
774
775 //
776 //STATUS_UNABLE_TO_REGISTER
777 // This error is used to indicate that a Daemon cannot register
778 // with state manager.
779 #define STATUS_UNABLE_TO_REGISTER 0xD7
780
781 //
782 // STATUS_TLB_ENTRY_NOT_FOUND
783 // This error indicates that a free TLB entry or the specified TLB entry
784 // could not be found.
785 //
786 #define STATUS_TLB_ENTRY_NOT_FOUND 0xD8
787
788 //
789 //STATUS_UNABLE_TO_UNREGISTER
790 // This error code is used to indicate that a Daemon cannot
791 // unregister with the state manager.
792 #define STATUS_UNABLE_TO_UNREGISTER 0xD9
793
794 //
795 //STATUS_TIMER_VALUE_NOT_SET
796 // Error used by PRTC to indicate the alarm value
797 // has not been set prior to enabling the alarm.
798 #define STATUS_TIMER_VALUE_NOT_SET 0xDA
799
800 //
801 //STATUS_ICV_CHECK_ERROR
802 // HW reported an ICV check failure
803 #define STATUS_ICV_CHECK_ERROR 0xDB
804
805 // STATUS_SUCCESS_WITH_ERRORS
806 // This error will be returned if the opration completed but had some errors (e,eg Transfer AHCI for DT)
807 // It is shared between Danbury components
808 #define STATUS_SUCCESS_WITH_ERRORS 0xDC
809
810 // STATUS_SUCCESS_HOST_RESET_REQUIRED
811 // This status will be returned by FwUpdateMgr after successfully updating FW
812 // if Danbury is enabled
813 #define STATUS_SUCCESS_HOST_RESET_REQUIRED 0xDD
814
815 // STATUS_FIPS_FAILURE
816 // This status will be returned by when FIPS self-tests fail
817 #define STATUS_FIPS_FAILURE 0xDE
818
819 //STATUS_PRIVILEGE_CHECK
820 // Privileged component access
821 #define STATUS_PRIVILEGE_CHECK 0xDF
822
823 // STATUS_INCOMPLETE
824 // This error indicates that the operation is incomplete
825 #define STATUS_INCOMPLETE 0xE0
826
827 // STATUS_RETRY
828 // This error indicates that the operation is being retried or needs to be retried
829 #define STATUS_RETRY 0xE1
830
831 #define STATUS_NOT_RUN 0xE2
832
833 #define STATUS_NOT_IMPLEMENTED 0xE3
834
835
836 #define STATUS_INVALID_INDEX 0xE4
837 #define STATUS_SLOT_IN_USE 0xE5
838 #define STATUS_SLOT_EMPTY 0xE6
839
840 // STATUS_OVERRIDDEN
841 // This error indicates that the operation can't be performed because
842 // it was overridden by some other logic/request
843 #define STATUS_OVERRIDDEN 0xE7
844
845 //STATUS_PERMIT_IS_DEACTIVE
846 // iCLS Permit has been deactivated
847 #define STATUS_PERMIT_IS_DEACTIVE 0xF0
848
849 //Return this if it is a Patsburg chipset
850 #define STATUS_UNKNOWN_CPUID 0xF1
851
852 #define STATUS_CRC_ERROR 0xF2
853
854 #if 1
855 //STATUS for task isolation
856 #define STATUS_HECI_CONNECTION_ACCEPT 0xF3
857 #define STATUS_HECI_CONNECTION_REJECT 0xF4
858 #define STATUS_RETURN_NOT_AVAILABLE 0xF5
859 #endif
860 //STATUS for PG
861 #define STATUS_PG_ENTRY_IN_PROGRESS 0xF6
862
863 // Intel Secret Key Unavailable
864 // RCR CCG0100111613
865 #define STATUS_BLOB_UNAVAILABLE 0xF6
866
867 #define STATUS_FPF_READ_MISMATCH 0xF7
868 #define STATUS_FPF_ARRAY_FULL 0xF8
869 #define STATUS_FPF_WRITE_FAILED 0xF9
870 #define STATUS_FPF_FILE_INVALID 0xFA
871 #define STATUS_FPF_FILE_FULL 0xFB
872 #define STATUS_FPF_FILE_LOCKED 0xFC
873 #define STATUS_FPF_NOT_AVAILABLE 0xFD
874 #define STATUS_FPF_BUSY 0xFE // FPF write currently in progress
875 #define STATUS_FPF_FATAL_ERROR 0xFF // Fatal error, fuses are no longer valid (bad PCH)
876 #define STATUS_FPF_FILE_EMPTY 0x100 // File has not been written to
877 #define STATUS_FPF_ALREADY_COMMITTED 0x101
878 #define STATUS_FPF_COMMIT_FAILED_EOM_NOT_SET 0x102
879 #define STATUS_FPF_INVALID_SB_VALUES 0x103
880 #define STATUS_FPF_NOT_COMMITTED 0x104
881 #define STATUS_FPF_NVAR_MISMATCH 0x105
882 #define STATUS_FPF_FILE_UNLOCKED 0x106
883 #define STATUS_FPF_COMMIT_NOT_ALLOWED 0x107
884 #define STATUS_FPF_CANARY_FAILURE 0x108
885 #define STATUS_FPF_SENSE_FAILED 0x109
886
887 #define STATUS_ECC_POINT_NOT_ON_CURVE 0x110
888 #define STATUS_ECC_POINT_AT_INFINITY 0x111
889 #define STATUS_ECC_PRIV_KEY_OUT_OF_RANGE 0x112
890 #define STATUS_ECC_KEYPAIR_INVALID 0x113
891
892 // RPMC-specific error codes
893 #define STATUS_RPMC_CRYPTO_ERROR 0x180
894 #define STATUS_RPMC_FPF_ERROR 0x181
895
896 #if 1
897 // STATUS for FWU kernel between 0x200 to 0x2FF
898 #define FW_UPDATE_STATUS UINT32
899
900 #define NO_UPDATE 0
901 #define STATUS_UPDATE_SUCCESS 0x0 // Zero for sucess anything else is consider failures
902 #define STATUS_UPDATE_IMAGE_INVALID 0x201
903 #define STATUS_UPDATE_INTEGRITY_FAILURE 0x202
904 #define STATUS_UPDATE_SKU_MISMATCH 0x203
905 #define STATUS_UPDATE_FW_VERSION_MISMATCH 0x204
906 #define STATUS_UPDATE_GENERAL_FAILURE 0x205
907 #define STATUS_UPDATE_OUT_OF_RESOURCES 0x206
908 #define STATUS_UPDATE_AUDIT_POLICY_FAILURE 0x207
909 #define STATUS_UPDATE_ERROR_CREATING_FT 0x208
910 #define STATUS_UPDATE_SAL_NOTIFICATION_ERROR 0x209
911 #define STATUS_UPDATE_IMG_LOADING 0x20A
912 #define STATUS_UPDATE_IMG_AUTHENTICATING 0x20B
913 #define STATUS_UPDATE_IMG_PROCESSING 0x20C
914 #define STATUS_UPDATE_CREATING_FT 0x20D
915 #define STATUS_UPDATE_UPDATING_CODE 0x20E
916 #define STATUS_UPDATE_UPDATING_NFT 0x20F
917 #define STATUS_UPDATE_FLASH_CODE_PARTITION_INVALID 0x210
918 #define STATUS_UPDATE_FLASH_NFT_PARTITION_INVALID 0x211
919 #define STATUS_UPDATE_ILLEGAL_IMAGE_LENGTH 0x212
920 #define STATUS_UPDATE_NOT_READY 0x213
921
922 #define STATUS_UPDATE_HOST_RESET_REQUIRED 0x214
923 #define STATUS_INVALID_GLUT 0x215
924 #define STATUS_INVALID_OEM_ID 0x216
925
926 // New for CPT add below here
927 #define STATUS_UPDATE_IMAGE_BLACKLISTED 0x217
928 #define STATUS_UPDATE_IMAGE_VERSION_HISTORY_CHECK_FAILURE 0x218
929 #define STATUS_UPDATE_DOWNGRADE_VETOED 0x219
930 #define STATUS_UPDATE_WRITE_FILE_FAILURE 0x22A
931 #define STATUS_UPDATE_READ_FILE_FAILURE 0x22B
932 #define STATUS_UPDATE_DELETE_FILE_FAILURE 0x22C
933 #define STATUS_UPDATE_PARTITION_LAYOUT_NOT_COMPATIBLE 0x22D // FW Update is not possible due to partition move
934 #define STATUS_DOWNGRADE_NOT_ALLOWED_DATA_MISMATCHED 0x22E
935 #define STATUS_UPDATE_FW_UPDATE_IS_DISABLED 0x22F
936 #define STATUS_UPDATE_PASSWORD_NOT_MATCHED 0x230
937 #define STATUS_UPDATE_PASSWORD_EXCEED_MAXIMUM_RETRY 0x231
938 #define STATUS_UPDATE_INRECOVERY_MODE_RESTRICT_UPDATE_TO_ATTEMPTED_VERSION 0x232 // They have to update with the same image that they started with.
939
940
941 // New for Partial FW update
942 #define STATUS_UPDATE_UPV_VERSION_MISMATCHED 0x233 // UPV version mismatched update is not allow
943 #define STATUS_UPDATE_INSTID_IS_NOT_EXPECTED_ID 0x234 // Reject update, instance ID sent is not one of expected ID
944 #define STATUS_UPDATE_INFO_NOT_AVAILABLE 0x235 // While in the middle of update IPU attrib info will bot be available
945 #define STATUS_UPDATE_REJ_IPU_FULL_UPDATE_NEEDED 0x236 // Can't do IPU update while we are in Full recovery mode.
946 #define STATUS_UPDATE_IPU_NAMEID_NOT_FOUND 0x237 // IPU name not found when compare with UPV extension
947
948 #define STATUS_UPDATE_RESTORE_POINT_INVALID 0x238
949 #define STATUS_UPDATE_RESTORE_POINT_VALID_BUT_NOT_LATEST 0x239
950 #define STATUS_UPDATE_RESTORE_POINT_OPERATION_NOT_ALLOWED 0x23A
951 #define STATUS_DOWNGRADE_NOT_ALLOWED_SVN_RESTRICTION 0x23B
952 #define STATUS_DOWNGRADE_NOT_ALLOWED_VCN_RESTRICTION 0x23C
953 #define STATUS_INVALID_SVN 0x23D
954 #define STATUS_UPDATE_OUT_OF_SVN_RESOURCES 0x23E
955 #define STATUS_UPDATE_REJECT_RESTORE_POINT_REQUEST_FLASH_IN_RECOVERY 0x23F
956 #define STATUS_UPDATE_REJECTED_BY_UPDATE_POLICY 0x240
957 #define STATUS_UPDATE_REJECTED_INCOMPATIBLE_TOOL_USAGE 0x241
958 #define STATUS_UPDATE_REJECTED_CROSSPOINT_UPDATE_NOT_ALLOWED 0x242
959 #define STATUS_UPDATE_REJECTED_CROSSHOTFIX_UPDATE_NOT_ALLOWED 0x243
960 #define STATUS_UPDATE_REJECTED_CURRENT_FW_NOT_ELIGIBLE_FOR_UPDATE 0x244
961 #define STATUS_UPDATE_REJECTED_WRONG_UPDATE_OPERATION 0x245
962 #define STATUS_UPDATE_REJECTED_WRONG_UPDATE_IMAGE_FOUND 0x246
963 #define STATUS_UPDATE_REJECTED_IFR_UPDATE_NOT_ALLOWED 0x247
964 #define STATUS_UPDATE_FAILURE_OCCURRED_DURING_ROLLBACK 0x248
965
966 //.........................................................................
967 //......................................................................... // Reserve for FWU usage
968 #define STATUS_UPDATE_LAST_STATUS_CODE 0x2FF
969
970 // Hotham-specific error codes
971 #define STATUS_HTM_HOST_NOT_RDY 0x300
972 #define STATUS_HTM_INTERNAL_ERROR 0x301
973 #define STATUS_HTM_REQ_IN_PROGRESS 0x302
974 #define STATUS_HTM_RESP_IN_PROGRESS 0x303
975 #define STATUS_HTM_INVALID_FRAGMENT 0x304
976 #define STATUS_HTM_RESP_NONE_ACTIVE 0x305
977 #define STATUS_HTM_NOT_CONNECTED 0x306
978 //...
979 //... Reserved for future use
980 #define STATUS_HTM_LAST_STATUS_CODE 0x31F
981
982 #define STATUS_LOAD_ERROR_NON_CRITICAL 0x320
983
984
985
986 // means internal FW operation errors
987 //#define STATUS_UPDATE_UNKNOWN = 0xFFFFFFFF
988
989
990 #endif
991
992
993 #endif // _ME_STATUS_H_
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: mkhi_hdrs.h Source File

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mkhi_hdrs.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2012 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #include "cse_basic_types.h"
35 #include "typedef.h"
36
37 #ifndef MKHI_HDRS_H_
38 #define MKHI_HDRS_H_
39
40 /**
41 *@page page2 MKHI Specification
42 *@section abstract ABSTRACT
43
44 Intel platforms provide manageability features that allow IT departments to better manage corporate
45 assets as well as ensure the client systems independence on operating system being present.
46 These features are provided via manageability engine which runs out of band of host system and
47 therefore is able to execute and provide manageability even when host system is down.
48 ME accomplishes this task by participating in all system level activities such as power management
49 transitions, communication with host OS through selected drivers such as HECI driver etc. ME,
50 for the most part, operates independently of host, however in certain cases it does overlaps
51 with host; most notably in its requirement of h/w resources. For example, BIOS initializes memory
52 and informs ME such that it can utilize BIOS settings to initialize memory when needed.
53 Similarly before ME can provide client specific manageability, it needs to be configured.
54 One possible method to configure ME is MEBx, which runs during BIOS POST and communicates with ME over HECI messages.
55 Communication between ME and host is intricate and can be broadly divided in following categories:
56
57 <b> MKHI specification is divided into following sub-sections: </b> \n
58 * \li \ref groupid
59 * \li \ref group2
60 * \li \ref group6
61 * \li \ref bios-me
62 * \li \ref page4
63 */
64
65 /** \defgroup group2 MKHI messages Generic Types and Structures
66 *@{
67 *BIOS interacts with Intel ME over Intel ME interface.The MEI(aka HCI)message header is the first dword of any MEI message.It is described with the following C prototype:
68 \li _CBM_HECI_MSG_HEADER. \n
69
70 * @}
71 */
72
73 /** \defgroup group6 BIOS/MRC -ME Kernel Register Based HECI communication
74 * @{
75 Beginning with the Cougar Point chipset, the ME kernel and BIOS MRC will no longer use MKHI messages to communicate the DRAM INIT status.Instead the MRC will use HECI PCI CFG Space offset 0x4C to send the DRAM INIT message.The FW will then use Host HECI PCI CFG Space offset 0x40 to acknowledge the DRAM init message from BIOS as wells as the biosaction that FW requests of BIOS.Additionally, each processor may have its own requirements for placing ME UMA in the system memory map and these requirements may be found in the specific processor's MRC BIOS Specification. \n
76 DRAM INIT request and reponse are defined below.
77 \code
78 DRAM INIT REQUEST
79 Bits Action
80 31:28 0x01 = DRAM Init Done
81 27:24 0x00 = Success
82 0x01 = No Memory in Channels
83 0x02 = Memory Init Error
84 0x03 = 0x0F = Reserved
85 23:16 Reserved
86 15:0 1M aligned ME UMA base address (maximum address bits supported - 36) This value
87 is to be read from MESEG_BASE[35:20]
88 NOTE: 1M alignment is a new requirement for Cougar Point. The Intel 5 Series chipset
89 is 64K alignment for ME UMA.
90 \endcode
91
92 \code
93 DRAM INIT RESPONSE
94 Bits Action
95 31:28 BIOS MSG ACK
96 0x01 = DRAM Init Done ACK
97 27:25 ACK DATA (ME BIOS Action)
98 0x00 = No DID Ack received
99 0x01 = Non-power cycle reset
100 0x02 = Power cycle reset
101 0x03 = Go to S3
102 0x04 = Go to S4
103 0x05 = Go to S5
104 0x06 = Global reset
105 0x07 = Continue to boot
106 \endcode
107 * @}
108 */
109
110 /** \page bios-me BIOS-ME Kernel HECI Communication
111 This section covers the HECI messages that are exchanged between BIOS POST and ME firmware. Note that some of these messages might get used by the BIOS MRC however they are not restricted to MRC like messages. Related HECI messages are described below.
112 * \li \ref resetblock
113 * \li \ref mfgmrstblock
114 * \li \ref eopblock
115 * \li \ref memaddressblock
116 *
117 */
118
119 /** \page page4 MEBx-ME Kernel HECI communication messages
120 This section covers HECI messages that are exchanged between MEBx and ME firmware (both kernel and application modules). Note that this section controls the MKHI version in that any changes in this section effectively increase the MKHI version.Upon starting, MEBx checks the MKHI and AMTHI version numbers and if compatible, runs on the platform. If MEBx is not compatible with either of these revisions then it displays an error message. This functionality allows MEBx to run from one platform to another a long as there have been no changes in MKHI or AMTHI version numbers.Related HECI messages are described below.
121 * \li \ref mkhiversion
122 * \li \ref fwversion
123 * \li \ref meunconfigure
124 * \li \ref merule
125 * \li \ref mepasswd
126 * \li \ref mefwsku
127 * \li \ref cpubrand
128 * \li \ref fwupdate
129 * \li \ref MdesMessages
130 * \li \ref MEBISTMessages
131 * \li \ref medbgMessages
132 *
133 */
134
135 /** \defgroup resetblock 1.1 Resets
136 <b>Reset System</b> \n
137 In ME enabled system, ME is running in parallel to the host system. Any attempts to cause global reset without synchronizing the two
138 sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if host were to cause a global reset without
139 informing ME and allowing ME to handle it first. \n
140 \n
141 Therefore to maintain appropriate synchronization, following rules must be followed by host system: \n
142 1. If BIOS needs to do Global Reset and either of following is true then it must send the reset request HECI message instead of generating the global reset using CF9 based mechanisms:
143 \verbatim
144 BIOS is in boot block and ME is in M3.
145 BIOS is in POST (has exited the boot block) and ME f/w status code is
146 initializing or initialized (does not reflect ERROR)
147 MEBx binary is requesting the global reset
148 \endverbatim
149
150 2. If BIOS needs to do a host reset before memory initialization is complete then it must request ME firmware to perform the host reset using messages data structures and commands below. \n
151
152 <b>Reset Request</b>\n
153 This message is sent by the system BIOS, MEBx binary or host, when it needs to do a global reset in ME enabled system. Note that although this message does support requesting a host only reset, currently there are no known use cases where BIOS would be required to use this message to cause host only reset.
154 \verbatim
155 Response Message Required: In normal case, No. In case or error, yes
156 NOTE: If this message is sent after END_OF_POST message, it is denied and an error
157 response is sent
158 \endverbatim
159 */
160
161
162 /** \defgroup mfgmrstblock 1.2 Manufacturing ME reset and Halt */
163 /** \defgroup eopblock 1.3 END OF POST */
164 /** \defgroup memaddressblock 1.4 Set Debug Memory Address Request */
165
166
167
168 /** \defgroup mkhiversion 2.1 Get MKHI Version */
169 /** \defgroup fwversion 2.2 Get FW Version */
170 /** \defgroup meunconfigure 2.3 ME Unconfigure */
171 /** \defgroup merule 2.4 Get and Set ME Rule */
172 /** \defgroup mepasswd 2.5 Get and Set ME Password */
173 /** \defgroup mefwsku 2.6 Get and set ME FW SKU and Capabilities */
174 /** \defgroup cpubrand 2.7 CPU Brand Class Related messages */
175 /** \defgroup fwupdate 2.8 FW Update Messages */
176 /** \defgroup MdesMessages 2.9 ME MDES Messages */
177 /** \defgroup MEBISTMessages 2.10 ME BIST Messages */
178 /** \defgroup medbgMessages 2.12 ME Debug Messages */
179
180 /** @addtogroup group2
181 * The MKHI message header is defined here <b>_MKHI_MESSAGE_HEADER</b> and consists of the following elements.
182 * \code
183 typedef union _MKHI_MESSAGE_HEADER
184 {
185 // brief DWORD of MKHI header
186 uint32_t Data;
187 struct
188 {
189 /// @brief GroupId of MKHI command specific to a client which will process the message.
190 uint32_t GroupId :8;
191 /// @brief command specific to HECI client.
192 uint32_t Command :7;
193 /// @brief resonnse from client which requires a client to respond.
194 uint32_t IsResponse :1;
195 /// @brief reserved bit field.
196 uint32_t Reserved :8;
197 /// @brief result
198 uint32_t Result :8;
199 }Fields;
200 }MKHI_MESSAGE_HEADER;
201
202 GroupId:8
203 Kernel Client specific information for dispatching. Refer to Table in MKHI messages Group ID for
204 possible values.
205
206 Command:7
207 Command code specific to MEI client.
208
209 IsResponse:
210 Set to 1 in response message.
211
212 Result:8
213 Result of the request message
214 \endcode
215 *
216 *
217 */
218
219 //MKHI host message header. This header is part of HECI message sent from MEBx via
220 //Host Configuration Interface (HCI). ME Configuration Manager or Power Configuration
221 //Manager also include this header with appropriate fields set as part of the
222 //response message to the HCI.
223
224 typedef UINT32 uint32_t;
225
226 typedef union _mkhi_message_header_t
227 {
228 UINT32 data;
229 struct
230 {
231 UINT32 group_id :8; /// the target client id registered to process the message
232 UINT32 command :7; /// command specific to HECI client
233 UINT32 is_response :1; /// response from client
234 UINT32 reserved :8; /// reserved bit field
235 UINT32 result :8; /// result
236 } fields;
237 } mkhi_message_header_t;
238 C_ASSERT(sizeof(mkhi_message_header_t) == 4);
239
240 //#if 1 // Legacy ME typedef
241 //typedef union _MKHI_MESSAGE_HEADER
242 //{
243 // UINT32 Data;
244 // struct
245 // {
246 // /// @brief Group Id of MKHI command specific to a client which will process the message.
247 // UINT32 GroupId :8;
248 // /// @brief command specific to HECI client.
249 // UINT32 Command :7;
250 // /// @brief resonnse from client which requires a client to respond.
251 // uint32_t IsResponse :1;
252 // /// @brief reserved bit field.
253 // uint32_t Reserved :8;
254 // /// @brief result
255 // uint32_t Result :8;
256 // }Fields;
257 //}MKHI_MESSAGE_HEADER;
258 //C_ASSERT(sizeof(MKHI_MESSAGE_HEADER) == 4);
259 //#endif
260
261 // Typedef for GroupID
262 /** \page groupid MKHI messages Group ID
263 *Each MKHI client in firmware is identified by its GROUP ID. Following GROUPIDs are supported in firmware:
264 *<table border = "3">
265 <tr>
266 <td><center><b> Group ID </b></center></td>
267 <td><center><b>Category Details</b></center></td>
268 </tr>
269 <tr>
270 <td>MKHI_CBM_GROUP_ID=0x00</td>
271 <td>Core BIOS Messages targeted for PM driver</td>
272 </tr>
273 <tr>
274 <td>MKHI_PM_GROUP_ID=0x01</td>
275 <td>PM Config Messages</td>
276 </tr>
277 <tr>
278 <td>MKHI_PWD_GROUP_ID=0x02</td>
279 <td>Password config messages</td>
280 </tr>
281 <tr>
282 <td>MKHI_FWCAPS_GROUP_ID=0x03</td>
283 <td>FW Capabilities config messages</td>
284 </tr>
285 <tr>
286 <td>MKHI_APP_GROUP_ID=0x04</td>
287 <td>Application config data access messages</td>
288 </tr>
289 <tr>
290 <td>MKHI_FWUPDATE_GROUP_ID=0x05</td>
291 <td>Used to Query and resume FW update process. This is used for manufacturing downgrade.</td>
292 </tr>
293 <tr>
294 <td>MKHI_FIRMWARE_UPDATE_GROUP_ID=0x06</td>
295 <td>Used for FW upgrade process. Need to check with FWU team..</td>
296 </tr>
297 <tr>
298 <td>MKHI_BIST_GROUP_ID=0x07</td>
299 <td>Used for perform ME BIST tests.</td>
300 </tr>
301 <tr>
302 <td>MKHI_MDES_GROUP_ID=0x08</td>
303 <td>Used for ME debug MDES messaging </td>
304 </tr>
305 <tr>
306 <td>MKHI_ME_DBG_GROUP_ID=0x09</td>
307 <td>Used internally for ME debug.</td>
308 </tr>
309 <tr>
310 <td>MKHI_FPF_GROUP_ID=0x10</td>
311 <td> Maximum value of MKHI group ID</td>
312 </tr>
313 <tr>
314 <td>MKHI_MAX_GROUP_ID=0x11</td>
315 <td> Maximum value of MKHI group ID</td>
316 </tr>
317 <tr>
318 <td>MKHI_GEN_GROUP_ID =0xff</td>
319 <td>General messages targeted to MKHI fw client</td>
320 </tr>
321 *</table>
322 */
323
324 typedef enum
325 {
326 MKHI_GROUP_ID_CBM = 0x00, //policy
327 MKHI_GROUP_ID_PM = 0x01, //Reserved
328 MKHI_GROUP_ID_PWD = 0x02, //policy
329 MKHI_GROUP_ID_FWCAPS = 0x03, //policy
330 MKHI_GROUP_ID_APP = 0x04, //Reserved
331 MKHI_GROUP_ID_FWUPDATE = 0x05, //FWU (HMRPFO)
332 MKHI_GROUP_ID_FIRMWARE_UPDATE = 0x06, //FWU
333 MKHI_GROUP_ID_BIST = 0x07, //policy
334 MKHI_GROUP_ID_MDES = 0x08, //Reserved
335 MKHI_GROUP_ID_ME_DBG = 0x09, //Reserved
336 MKHI_GROUP_ID_MCA = 0x0A, //MCA
337 MKHI_GROUP_ID_BUP_COMMON = 0xF0, //policy-bup
338 MKHI_GROUP_ID_BUP_ICC = 0xF1, //icc-bup
339 MKHI_GROUP_ID_BUP_MPHY = 0xF2, //icc-bup
340 MKHI_GROUP_ID_BUP_PM = 0xF3, //policy- bup
341 MKHI_GROUP_ID_GEN = 0xFF //policy
342 } mkhi_group_id_t;
343
344 #endif /* MKHI_HDRS_H_ */
cse_basic_types.h
typedef.h
Generated on Sun Aug 13 2017 12:04:36 for IceLake Platform Sample Code by doxygen 1.8.10


IceLake Platform Sample Code: Related Pages

Related Pages
Here is a list of all related documentation pages:
[detail level 123]
MKHI Specification |
BIOS-ME Kernel HECI Communication | This section covers the HECI messages that are exchanged between BIOS POST and ME firmware
MEBx-ME Kernel HECI communication messages | This section covers HECI messages that are exchanged between MEBx and ME firmware (both kernel and application modules)
MKHI messages Group ID | Each MKHI client in firmware is identified by its GROUP ID
▼ 2 - Platform Sample Module |
▼ 2.1 - ACPI |
2.1.1 - Architectural Overview |
2.1.2 - Rationale |
2.1.3 - Requirements |
2.1.4 - API |
2.1.5 - Build Flags |
2.1.6 - MiscInfo |
3 - Royal Park Platform Override (RPPO) | Royal Park Platform Override tags (RPPO-XXX-XXXX) document issues that a Platform team has resolved with an override of Royal Park
4 - RoyalPark & PlatSamplePkg build Integration Guide | When building SiPkg/SiBinPkg with RoyalPark and PlatSamplePkg please follow below steps:
5 - MiscInfo |
6 - Bios Image | 0
7 - Power Button Override | Both pre-OS & OS via PCH register programming are enabled 10 seconds override feature but It's not easy to observe in pre-OS phase, because in pre-OS phase Power Button SMI will be triggered first with system shutdown before 10 seconds override timer expiration
8 - Post Code |
Todo List |


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_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL Member List

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EnableI2cBusConfiguration | _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2cBusConfigurationCount | _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL


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BusFrequencySet | _EFI_I2C_MASTER_PROTOCOL
MaximumReceiveBytes | _EFI_I2C_MASTER_PROTOCOL
MaximumTotalBytes | _EFI_I2C_MASTER_PROTOCOL
MaximumTransmitBytes | _EFI_I2C_MASTER_PROTOCOL
Reset | _EFI_I2C_MASTER_PROTOCOL
StartRequest | _EFI_I2C_MASTER_PROTOCOL


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CpuSaveState _EFI_SMM_CPU_SAVE_STATE_PROTOCOL


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AllocatedEpcSize | _EPC_BIOS_CONFIG
EpcMap | _EPC_BIOS_CONFIG
MaxEpcSize | _EPC_BIOS_CONFIG
SupportedPrmBins | _EPC_BIOS_CONFIG


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Hs400RxStrobe1Dll | _PLATFORM_EMMC_TUNING_DATA
Hs400TxDataDll | _PLATFORM_EMMC_TUNING_DATA


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buffer | _TcgCreateStruct
bufferSize | _TcgCreateStruct
comPacket | _TcgCreateStruct
curPacket | _TcgCreateStruct
curSubPacket | _TcgCreateStruct
dryRun | _TcgCreateStruct


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bufferSize | _TcgParseStruct
comPacket | _TcgParseStruct
curPacket | _TcgParseStruct
curPtr | _TcgParseStruct
curSubPacket | _TcgParseStruct


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type | _TcgToken


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DataSize | AUTHENTICATED_VARIABLE_HEADER
MonotonicCount | AUTHENTICATED_VARIABLE_HEADER
NameSize | AUTHENTICATED_VARIABLE_HEADER
PubKeyIndex | AUTHENTICATED_VARIABLE_HEADER
StartId | AUTHENTICATED_VARIABLE_HEADER
State | AUTHENTICATED_VARIABLE_HEADER
TimeStamp | AUTHENTICATED_VARIABLE_HEADER
VendorGuid | AUTHENTICATED_VARIABLE_HEADER


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Timeout | EFI_I2C_REQUEST_PACKET
WriteBuffer | EFI_I2C_REQUEST_PACKET
WriteBytes | EFI_I2C_REQUEST_PACKET


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RequestedEpcSize EPC_OS_CONFIG
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SgxStatus | SOFTWARE_GUARD_STATUS


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Signature | VARIABLE_STORE_HEADER
Size | VARIABLE_STORE_HEADER
State | VARIABLE_STORE_HEADER


IceLake Platform Sample Code: typedef.h Source File

  • Library
typedef.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2009 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _TYPEDEF_H_
35 #define _TYPEDEF_H_
36
37 #ifdef _MSC_VER
38 // disable the "zero-sized array" warning
39 #pragma warning(disable:4200)
40 #endif
41
42 /*++
43 ********************************************************************************
44 **
45 ** FUNCTION: C_ASSERT
46 **
47 ** DESCRIPTION:
48 ** C_ASSERT() can be used to perform many compile-time assertions:
49 ** type sizes, field offsets, etc.
50 ** An assertion failure results in error C2118: negative subscript.
51 **
52 ********************************************************************************
53 --*/
54
55 #if defined(_DOS) || defined(_LINUX)
56 #define C_ASSERT(x)
57 #else
58 #define C_ASSERT(e) typedef char __C_ASSERT__[(e)?1:-1]
59 #endif
60
61 //#ifdef EFIX64
62 #define bool BOOLEAN
63 //#endif
64
65
66 #ifdef WIN32
67 /*++
68 ********************************************************************************
69 **
70 ** FUNCTION: C_ASSERT
71 **
72 ** DESCRIPTION:
73 ** C_ASSERT() can be used to perform many compile-time assertions:
74 ** type sizes, field offsets, etc.
75 ** An assertion failure results in error C2118: negative subscript.
76 **
77 ********************************************************************************
78 --*/
79 #define C_ASSERT(e) typedef char __C_ASSERT__[(e)?1:-1]
80 #endif
81
82 #ifdef _LINUX
83 #define U32 unsigned long
84 #define U8 unsigned char
85 #define U16 unsigned short
86 #else
87
88 #ifndef EFIX64
89 #ifndef _BASETSD_H_
90 typedef unsigned char UINT8;
91 typedef unsigned short UINT16;
92 #ifndef _DOS
93 typedef unsigned int UINT32;
94 #endif
95 #endif
96 #endif
97
98 //#ifdef EFIX64
99
100 #define true 1
101 #define false 0
102 #define True 1
103 #define False 0
104
105
106 #ifdef _MSC_VER
107 typedef UINT32 DWORD;
108 typedef DWORD * PDWORD, *DWORD_PTR;
109 typedef char INT8;
110 typedef UINT8 UCHAR;
111 typedef INT8 CHAR;
112 typedef CHAR * PCHAR;
113 //typedef CHAR GUID[16];
114 #endif
115
116 //#endif
117
118
119
120
121
122 #ifdef __cplusplus
123 extern "C" {
124 #endif
125
126 typedef unsigned char UINT8;
127 typedef unsigned short UINT16;
128 typedef short INT16;
129
130 typedef UINT8 U8;
131 typedef UINT16 U16;
132 typedef unsigned int U32;
133
134 typedef struct
135 {
136 unsigned long Data1;
137 unsigned short Data2;
138 unsigned short Data3;
139 unsigned char Data4[8];
140 } _UUID;
141
142 #ifdef __cplusplus
143 }
144 #endif
145
146 #endif
147
148
149 /** Declare a structure before it is used to allow of structure pointers within the structure */
150 #define FORWARD_DECLARATION(x) typedef struct _##x x
151
152 //typedef unsigned int UINT; /**< Unsigned Integer */
153 //typedef int INT; /**< Integer (INT) */
154
155
156 #endif
157
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IceLake Platform Sample Code: ver.h Source File

  • Library
ver.h
Go to the documentation of this file.
1 /** @file
2 ** @brief Contains definitions of the MAJOR, MINOR, & HOTFIX versions used
3 ** throughout the code.
4 **
5 ** @author Christopher Spiegel and John Traver
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 2005 - 2016 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification
36 **/
37 #ifndef _VER_H_
38 #define _VER_H_
39
40 /* Include Files
41 *****************/
42 #include "Build.h"
43 #include "typedef.h"
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /* Global Declarations
50 **************************/
51
52 /* Version and definitions */
53 // Default is 10.0
54
55 //
56 // 10.0 DEFINITIONS
57 //
58 #define VER_MAJOR 11 /**< Major Version */
59 #define VER_MAJOR_STR "11" /**< Major Version String */
60 #define VER_MINOR 5 /**< Minor Version */
61 #define VER_MINOR_STR "5" /**< Minor Version String*/
62 #define VER_HOTFIX 0 /**< Default Hotfix Version */
63 #define VER_HOTFIX_STR "0" /**< Default Hotfix Version String */
64
65 #define VER_SEPARATOR_STR "." /**< Separator String used between major, minor, hotfix and build strings */
66
67 /* Flags set based on build type */
68 #ifdef DBG
69 /** Define "DBG" string that is attached to version string when DBG build */
70 #define VER_DEBUG_TAG " (DBG)"
71 #else
72 /** Define string that is attached to version string when release build */
73 #define VER_DEBUG_TAG
74 #endif
75
76
77 /** Combined file version information */
78 #define VERSION_STR VER_MAJOR_STR VER_SEPARATOR_STR VER_MINOR_STR VER_SEPARATOR_STR VER_HOTFIX_STR VER_SEPARATOR_STR VER_BUILD_STR VER_DEBUG_TAG
79
80 /** @brief Defines a generic version structure used in the software build process. This structure will be used to
81 * represent versions of ROM, FW and Recovery modules.
82 */
83 typedef struct _VERSION
84 {
85 UINT16 Major;
86 UINT16 Minor;
87 UINT16 Hotfix;
88 UINT16 Build;
89 }VERSION;
90
91 #define VER_PRODUCTVERSION VER_MAJOR,VER_MINOR,VER_HOTFIX,VER_BUILD
92 #define VER_PRODUCTVERSION_STR VERSION_STR
93
94
95 /** Adding the current year date string for use in updating the year component of the
96 *** displayed copyright message.
97 *** the string needs to be the full 4 char value without spaces or special characters.
98 *** For example:
99 *** "2012"
100 */
101 #define CURRENT_YEAR_STRING "2015"
102
103 #ifdef __cplusplus
104 }
105 #endif
106
107 /* Global Functions
108 **************************/
109
110 #endif // _VER_H_
111
Build.h
typedef.h
_VERSION
Defines a generic version structure used in the software build process.
Definition: ver.h:83
VERSION
struct _VERSION VERSION
Defines a generic version structure used in the software build process.
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