234 lines
6.0 KiB
Diff
234 lines
6.0 KiB
Diff
--- a/arch/mips/include/asm/mach-ralink/mt7621.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
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@@ -17,6 +17,10 @@
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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+#define SYSC_REG_CLKCFG0 0x2c
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+#define SYSC_REG_CUR_CLK_STS 0x44
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+
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+#define MEMC_REG_CPU_PLL 0x648
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#define CHIP_REV_PKG_MASK 0x1
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#define CHIP_REV_PKG_SHIFT 16
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@@ -24,6 +28,22 @@
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#define CHIP_REV_VER_SHIFT 8
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#define CHIP_REV_ECO_MASK 0xf
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+#define XTAL_MODE_SEL_MASK 0x7
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+#define XTAL_MODE_SEL_SHIFT 6
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+
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+#define CPU_CLK_SEL_MASK 0x3
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+#define CPU_CLK_SEL_SHIFT 30
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+
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+#define CUR_CPU_FDIV_MASK 0x1f
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+#define CUR_CPU_FDIV_SHIFT 8
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+#define CUR_CPU_FFRAC_MASK 0x1f
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+#define CUR_CPU_FFRAC_SHIFT 0
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+
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+#define CPU_PLL_PREDIV_MASK 0x3
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+#define CPU_PLL_PREDIV_SHIFT 12
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+#define CPU_PLL_FBDIV_MASK 0x7f
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+#define CPU_PLL_FBDIV_SHIFT 4
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+
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#define MT7621_DRAM_BASE 0x0
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#define MT7621_DDR2_SIZE_MIN 32
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#define MT7621_DDR2_SIZE_MAX 256
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -8,6 +8,10 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/jiffies.h>
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+#include <linux/clk.h>
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+#include <linux/clkdev.h>
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+#include <linux/clk-provider.h>
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+#include <dt-bindings/clock/mt7621-clk.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-ops.h>
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@@ -16,16 +20,12 @@
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#include <asm/mach-ralink/mt7621.h>
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#include <asm/mips-boards/launch.h>
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#include <asm/delay.h>
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+#include <asm/time.h>
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#include <pinmux.h>
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#include "common.h"
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-#define SYSC_REG_SYSCFG 0x10
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-#define SYSC_REG_CPLL_CLKCFG0 0x2c
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-#define SYSC_REG_CUR_CLK_STS 0x44
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-#define CPU_CLK_SEL (BIT(30) | BIT(31))
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-
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#define MT7621_GPIO_MODE_UART1 1
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#define MT7621_GPIO_MODE_I2C 2
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#define MT7621_GPIO_MODE_UART3_MASK 0x3
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@@ -111,49 +111,98 @@ static struct rt2880_pmx_group mt7621_pi
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{ 0 }
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};
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+static struct clk *clks[MT7621_CLK_MAX];
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+static struct clk_onecell_data clk_data = {
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+ .clks = clks,
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+ .clk_num = ARRAY_SIZE(clks),
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+};
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+
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phys_addr_t mips_cpc_default_phys_base(void)
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{
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panic("Cannot detect cpc address");
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}
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-void __init ralink_clk_init(void)
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+static struct clk *__init mt7621_add_sys_clkdev(
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+ const char *id, unsigned long rate)
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{
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- int cpu_fdiv = 0;
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- int cpu_ffrac = 0;
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- int fbdiv = 0;
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- u32 clk_sts, syscfg;
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- u8 clk_sel = 0, xtal_mode;
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- u32 cpu_clk;
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+ struct clk *clk;
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+ int err;
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+
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+ clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
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+ if (IS_ERR(clk))
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+ panic("failed to allocate %s clock structure", id);
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+
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+ err = clk_register_clkdev(clk, id, NULL);
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+ if (err)
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+ panic("unable to register %s clock device", id);
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- if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
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- clk_sel = 1;
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+ return clk;
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+}
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+
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+void __init ralink_clk_init(void)
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+{
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+ u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
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+ u32 pll, prediv, fbdiv;
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+ u32 xtal_clk, cpu_clk, bus_clk;
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+ const static u32 prediv_tbl[] = {0, 1, 2, 2};
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+
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+ syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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+ xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
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+
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+ clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);
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+ clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;
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+
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+ curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
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+ ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;
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+ ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;
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+
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+ if (xtal_sel <= 2)
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+ xtal_clk = 20 * 1000 * 1000;
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+ else if (xtal_sel <= 5)
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+ xtal_clk = 40 * 1000 * 1000;
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+ else
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+ xtal_clk = 25 * 1000 * 1000;
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switch (clk_sel) {
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case 0:
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- clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
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- cpu_fdiv = ((clk_sts >> 8) & 0x1F);
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- cpu_ffrac = (clk_sts & 0x1F);
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- cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
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+ cpu_clk = 500 * 1000 * 1000;
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break;
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-
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case 1:
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- fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
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- syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
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- xtal_mode = (syscfg >> 6) & 0x7;
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- if (xtal_mode >= 6) {
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- /* 25Mhz Xtal */
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- cpu_clk = 25 * fbdiv * 1000 * 1000;
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- } else if (xtal_mode >= 3) {
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- /* 40Mhz Xtal */
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- cpu_clk = 40 * fbdiv * 1000 * 1000;
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- } else {
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- /* 20Mhz Xtal */
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- cpu_clk = 20 * fbdiv * 1000 * 1000;
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- }
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+ pll = rt_memc_r32(MEMC_REG_CPU_PLL);
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+ if ((pll & 0x7f0) == 0x2b0) {
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+ volatile u32 i;
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+
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+ pr_info("CPU Clock: 880MHz, start overclocking\n");
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+ pll &= ~0x7ff;
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+ pll |= 0x312;
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+ rt_memc_w32(pll, MEMC_REG_CPU_PLL);
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+ for (i = 0; i < 1000; i++);
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+ }
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+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
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+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
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+ cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
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break;
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+ default:
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+ cpu_clk = xtal_clk;
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}
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+
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+ cpu_clk = cpu_clk / ffiv * ffrac;
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+ bus_clk = cpu_clk / 4;
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+
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+ clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk);
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+ clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk);
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+
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+ pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);
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+ mips_hpt_frequency = cpu_clk / 2;
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}
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+static void __init mt7621_clocks_init_dt(struct device_node *np)
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+{
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+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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+}
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+
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+CLK_OF_DECLARE(ar7100, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
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+
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
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--- a/arch/mips/ralink/timer-gic.c
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+++ b/arch/mips/ralink/timer-gic.c
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@@ -9,14 +9,14 @@
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#include <linux/of.h>
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#include <linux/clk-provider.h>
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-#include <linux/clocksource.h>
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+#include <asm/time.h>
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#include "common.h"
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void __init plat_time_init(void)
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{
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ralink_of_remap();
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-
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+ ralink_clk_init();
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of_clk_init(NULL);
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timer_probe();
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}
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--- /dev/null
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+++ b/include/dt-bindings/clock/mt7621-clk.h
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@@ -0,0 +1,18 @@
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+/*
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+ * Copyright (C) 2018 Weijie Gao <hackpascal@gmail.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#ifndef __DT_BINDINGS_MT7621_CLK_H
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+#define __DT_BINDINGS_MT7621_CLK_H
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+
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+#define MT7621_CLK_CPU 0
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+#define MT7621_CLK_BUS 1
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+
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+#define MT7621_CLK_MAX 2
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+
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+#endif /* __DT_BINDINGS_MT7621_CLK_H */
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